2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
27 #include <linux/kvm_host.h>
28 #include <linux/types.h>
29 #include <linux/string.h>
31 #include <linux/highmem.h>
32 #include <linux/module.h>
33 #include <linux/swap.h>
34 #include <linux/hugetlb.h>
35 #include <linux/compiler.h>
36 #include <linux/srcu.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
41 #include <asm/cmpxchg.h>
44 #include <asm/kvm_page_track.h>
47 * When setting this variable to true it enables Two-Dimensional-Paging
48 * where the hardware walks 2 page tables:
49 * 1. the guest-virtual to guest-physical
50 * 2. while doing 1. it walks guest-physical to host-physical
51 * If the hardware supports that we don't need to do shadow paging.
53 bool tdp_enabled
= false;
57 AUDIT_POST_PAGE_FAULT
,
68 module_param(dbg
, bool, 0644);
70 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
71 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
72 #define MMU_WARN_ON(x) WARN_ON(x)
74 #define pgprintk(x...) do { } while (0)
75 #define rmap_printk(x...) do { } while (0)
76 #define MMU_WARN_ON(x) do { } while (0)
79 #define PTE_PREFETCH_NUM 8
81 #define PT_FIRST_AVAIL_BITS_SHIFT 10
82 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
84 #define PT64_LEVEL_BITS 9
86 #define PT64_LEVEL_SHIFT(level) \
87 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
89 #define PT64_INDEX(address, level)\
90 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
93 #define PT32_LEVEL_BITS 10
95 #define PT32_LEVEL_SHIFT(level) \
96 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
98 #define PT32_LVL_OFFSET_MASK(level) \
99 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
100 * PT32_LEVEL_BITS))) - 1))
102 #define PT32_INDEX(address, level)\
103 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
106 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
107 #define PT64_DIR_BASE_ADDR_MASK \
108 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
109 #define PT64_LVL_ADDR_MASK(level) \
110 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
111 * PT64_LEVEL_BITS))) - 1))
112 #define PT64_LVL_OFFSET_MASK(level) \
113 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
114 * PT64_LEVEL_BITS))) - 1))
116 #define PT32_BASE_ADDR_MASK PAGE_MASK
117 #define PT32_DIR_BASE_ADDR_MASK \
118 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
119 #define PT32_LVL_ADDR_MASK(level) \
120 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
121 * PT32_LEVEL_BITS))) - 1))
123 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
124 | shadow_x_mask | shadow_nx_mask)
126 #define ACC_EXEC_MASK 1
127 #define ACC_WRITE_MASK PT_WRITABLE_MASK
128 #define ACC_USER_MASK PT_USER_MASK
129 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
131 #include <trace/events/kvm.h>
133 #define CREATE_TRACE_POINTS
134 #include "mmutrace.h"
136 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
137 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
139 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
141 /* make pte_list_desc fit well in cache line */
142 #define PTE_LIST_EXT 3
144 struct pte_list_desc
{
145 u64
*sptes
[PTE_LIST_EXT
];
146 struct pte_list_desc
*more
;
149 struct kvm_shadow_walk_iterator
{
157 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
158 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
159 shadow_walk_okay(&(_walker)); \
160 shadow_walk_next(&(_walker)))
162 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
163 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
164 shadow_walk_okay(&(_walker)) && \
165 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
166 __shadow_walk_next(&(_walker), spte))
168 static struct kmem_cache
*pte_list_desc_cache
;
169 static struct kmem_cache
*mmu_page_header_cache
;
170 static struct percpu_counter kvm_total_used_mmu_pages
;
172 static u64 __read_mostly shadow_nx_mask
;
173 static u64 __read_mostly shadow_x_mask
; /* mutual exclusive with nx_mask */
174 static u64 __read_mostly shadow_user_mask
;
175 static u64 __read_mostly shadow_accessed_mask
;
176 static u64 __read_mostly shadow_dirty_mask
;
177 static u64 __read_mostly shadow_mmio_mask
;
179 static void mmu_spte_set(u64
*sptep
, u64 spte
);
180 static void mmu_free_roots(struct kvm_vcpu
*vcpu
);
182 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask
)
184 shadow_mmio_mask
= mmio_mask
;
186 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask
);
189 * the low bit of the generation number is always presumed to be zero.
190 * This disables mmio caching during memslot updates. The concept is
191 * similar to a seqcount but instead of retrying the access we just punt
192 * and ignore the cache.
194 * spte bits 3-11 are used as bits 1-9 of the generation number,
195 * the bits 52-61 are used as bits 10-19 of the generation number.
197 #define MMIO_SPTE_GEN_LOW_SHIFT 2
198 #define MMIO_SPTE_GEN_HIGH_SHIFT 52
200 #define MMIO_GEN_SHIFT 20
201 #define MMIO_GEN_LOW_SHIFT 10
202 #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2)
203 #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1)
205 static u64
generation_mmio_spte_mask(unsigned int gen
)
209 WARN_ON(gen
& ~MMIO_GEN_MASK
);
211 mask
= (gen
& MMIO_GEN_LOW_MASK
) << MMIO_SPTE_GEN_LOW_SHIFT
;
212 mask
|= ((u64
)gen
>> MMIO_GEN_LOW_SHIFT
) << MMIO_SPTE_GEN_HIGH_SHIFT
;
216 static unsigned int get_mmio_spte_generation(u64 spte
)
220 spte
&= ~shadow_mmio_mask
;
222 gen
= (spte
>> MMIO_SPTE_GEN_LOW_SHIFT
) & MMIO_GEN_LOW_MASK
;
223 gen
|= (spte
>> MMIO_SPTE_GEN_HIGH_SHIFT
) << MMIO_GEN_LOW_SHIFT
;
227 static unsigned int kvm_current_mmio_generation(struct kvm_vcpu
*vcpu
)
229 return kvm_vcpu_memslots(vcpu
)->generation
& MMIO_GEN_MASK
;
232 static void mark_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, u64 gfn
,
235 unsigned int gen
= kvm_current_mmio_generation(vcpu
);
236 u64 mask
= generation_mmio_spte_mask(gen
);
238 access
&= ACC_WRITE_MASK
| ACC_USER_MASK
;
239 mask
|= shadow_mmio_mask
| access
| gfn
<< PAGE_SHIFT
;
241 trace_mark_mmio_spte(sptep
, gfn
, access
, gen
);
242 mmu_spte_set(sptep
, mask
);
245 static bool is_mmio_spte(u64 spte
)
247 return (spte
& shadow_mmio_mask
) == shadow_mmio_mask
;
250 static gfn_t
get_mmio_spte_gfn(u64 spte
)
252 u64 mask
= generation_mmio_spte_mask(MMIO_GEN_MASK
) | shadow_mmio_mask
;
253 return (spte
& ~mask
) >> PAGE_SHIFT
;
256 static unsigned get_mmio_spte_access(u64 spte
)
258 u64 mask
= generation_mmio_spte_mask(MMIO_GEN_MASK
) | shadow_mmio_mask
;
259 return (spte
& ~mask
) & ~PAGE_MASK
;
262 static bool set_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, gfn_t gfn
,
263 kvm_pfn_t pfn
, unsigned access
)
265 if (unlikely(is_noslot_pfn(pfn
))) {
266 mark_mmio_spte(vcpu
, sptep
, gfn
, access
);
273 static bool check_mmio_spte(struct kvm_vcpu
*vcpu
, u64 spte
)
275 unsigned int kvm_gen
, spte_gen
;
277 kvm_gen
= kvm_current_mmio_generation(vcpu
);
278 spte_gen
= get_mmio_spte_generation(spte
);
280 trace_check_mmio_spte(spte
, kvm_gen
, spte_gen
);
281 return likely(kvm_gen
== spte_gen
);
284 void kvm_mmu_set_mask_ptes(u64 user_mask
, u64 accessed_mask
,
285 u64 dirty_mask
, u64 nx_mask
, u64 x_mask
)
287 shadow_user_mask
= user_mask
;
288 shadow_accessed_mask
= accessed_mask
;
289 shadow_dirty_mask
= dirty_mask
;
290 shadow_nx_mask
= nx_mask
;
291 shadow_x_mask
= x_mask
;
293 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes
);
295 static int is_cpuid_PSE36(void)
300 static int is_nx(struct kvm_vcpu
*vcpu
)
302 return vcpu
->arch
.efer
& EFER_NX
;
305 static int is_shadow_present_pte(u64 pte
)
307 return pte
& PT_PRESENT_MASK
&& !is_mmio_spte(pte
);
310 static int is_large_pte(u64 pte
)
312 return pte
& PT_PAGE_SIZE_MASK
;
315 static int is_last_spte(u64 pte
, int level
)
317 if (level
== PT_PAGE_TABLE_LEVEL
)
319 if (is_large_pte(pte
))
324 static kvm_pfn_t
spte_to_pfn(u64 pte
)
326 return (pte
& PT64_BASE_ADDR_MASK
) >> PAGE_SHIFT
;
329 static gfn_t
pse36_gfn_delta(u32 gpte
)
331 int shift
= 32 - PT32_DIR_PSE36_SHIFT
- PAGE_SHIFT
;
333 return (gpte
& PT32_DIR_PSE36_MASK
) << shift
;
337 static void __set_spte(u64
*sptep
, u64 spte
)
342 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
347 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
349 return xchg(sptep
, spte
);
352 static u64
__get_spte_lockless(u64
*sptep
)
354 return ACCESS_ONCE(*sptep
);
365 static void count_spte_clear(u64
*sptep
, u64 spte
)
367 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
369 if (is_shadow_present_pte(spte
))
372 /* Ensure the spte is completely set before we increase the count */
374 sp
->clear_spte_count
++;
377 static void __set_spte(u64
*sptep
, u64 spte
)
379 union split_spte
*ssptep
, sspte
;
381 ssptep
= (union split_spte
*)sptep
;
382 sspte
= (union split_spte
)spte
;
384 ssptep
->spte_high
= sspte
.spte_high
;
387 * If we map the spte from nonpresent to present, We should store
388 * the high bits firstly, then set present bit, so cpu can not
389 * fetch this spte while we are setting the spte.
393 ssptep
->spte_low
= sspte
.spte_low
;
396 static void __update_clear_spte_fast(u64
*sptep
, u64 spte
)
398 union split_spte
*ssptep
, sspte
;
400 ssptep
= (union split_spte
*)sptep
;
401 sspte
= (union split_spte
)spte
;
403 ssptep
->spte_low
= sspte
.spte_low
;
406 * If we map the spte from present to nonpresent, we should clear
407 * present bit firstly to avoid vcpu fetch the old high bits.
411 ssptep
->spte_high
= sspte
.spte_high
;
412 count_spte_clear(sptep
, spte
);
415 static u64
__update_clear_spte_slow(u64
*sptep
, u64 spte
)
417 union split_spte
*ssptep
, sspte
, orig
;
419 ssptep
= (union split_spte
*)sptep
;
420 sspte
= (union split_spte
)spte
;
422 /* xchg acts as a barrier before the setting of the high bits */
423 orig
.spte_low
= xchg(&ssptep
->spte_low
, sspte
.spte_low
);
424 orig
.spte_high
= ssptep
->spte_high
;
425 ssptep
->spte_high
= sspte
.spte_high
;
426 count_spte_clear(sptep
, spte
);
432 * The idea using the light way get the spte on x86_32 guest is from
433 * gup_get_pte(arch/x86/mm/gup.c).
435 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
436 * coalesces them and we are running out of the MMU lock. Therefore
437 * we need to protect against in-progress updates of the spte.
439 * Reading the spte while an update is in progress may get the old value
440 * for the high part of the spte. The race is fine for a present->non-present
441 * change (because the high part of the spte is ignored for non-present spte),
442 * but for a present->present change we must reread the spte.
444 * All such changes are done in two steps (present->non-present and
445 * non-present->present), hence it is enough to count the number of
446 * present->non-present updates: if it changed while reading the spte,
447 * we might have hit the race. This is done using clear_spte_count.
449 static u64
__get_spte_lockless(u64
*sptep
)
451 struct kvm_mmu_page
*sp
= page_header(__pa(sptep
));
452 union split_spte spte
, *orig
= (union split_spte
*)sptep
;
456 count
= sp
->clear_spte_count
;
459 spte
.spte_low
= orig
->spte_low
;
462 spte
.spte_high
= orig
->spte_high
;
465 if (unlikely(spte
.spte_low
!= orig
->spte_low
||
466 count
!= sp
->clear_spte_count
))
473 static bool spte_is_locklessly_modifiable(u64 spte
)
475 return (spte
& (SPTE_HOST_WRITEABLE
| SPTE_MMU_WRITEABLE
)) ==
476 (SPTE_HOST_WRITEABLE
| SPTE_MMU_WRITEABLE
);
479 static bool spte_has_volatile_bits(u64 spte
)
482 * Always atomically update spte if it can be updated
483 * out of mmu-lock, it can ensure dirty bit is not lost,
484 * also, it can help us to get a stable is_writable_pte()
485 * to ensure tlb flush is not missed.
487 if (spte_is_locklessly_modifiable(spte
))
490 if (!shadow_accessed_mask
)
493 if (!is_shadow_present_pte(spte
))
496 if ((spte
& shadow_accessed_mask
) &&
497 (!is_writable_pte(spte
) || (spte
& shadow_dirty_mask
)))
503 static bool spte_is_bit_cleared(u64 old_spte
, u64 new_spte
, u64 bit_mask
)
505 return (old_spte
& bit_mask
) && !(new_spte
& bit_mask
);
508 static bool spte_is_bit_changed(u64 old_spte
, u64 new_spte
, u64 bit_mask
)
510 return (old_spte
& bit_mask
) != (new_spte
& bit_mask
);
513 /* Rules for using mmu_spte_set:
514 * Set the sptep from nonpresent to present.
515 * Note: the sptep being assigned *must* be either not present
516 * or in a state where the hardware will not attempt to update
519 static void mmu_spte_set(u64
*sptep
, u64 new_spte
)
521 WARN_ON(is_shadow_present_pte(*sptep
));
522 __set_spte(sptep
, new_spte
);
525 /* Rules for using mmu_spte_update:
526 * Update the state bits, it means the mapped pfn is not changged.
528 * Whenever we overwrite a writable spte with a read-only one we
529 * should flush remote TLBs. Otherwise rmap_write_protect
530 * will find a read-only spte, even though the writable spte
531 * might be cached on a CPU's TLB, the return value indicates this
534 static bool mmu_spte_update(u64
*sptep
, u64 new_spte
)
536 u64 old_spte
= *sptep
;
539 WARN_ON(!is_shadow_present_pte(new_spte
));
541 if (!is_shadow_present_pte(old_spte
)) {
542 mmu_spte_set(sptep
, new_spte
);
546 if (!spte_has_volatile_bits(old_spte
))
547 __update_clear_spte_fast(sptep
, new_spte
);
549 old_spte
= __update_clear_spte_slow(sptep
, new_spte
);
552 * For the spte updated out of mmu-lock is safe, since
553 * we always atomically update it, see the comments in
554 * spte_has_volatile_bits().
556 if (spte_is_locklessly_modifiable(old_spte
) &&
557 !is_writable_pte(new_spte
))
560 if (!shadow_accessed_mask
)
564 * Flush TLB when accessed/dirty bits are changed in the page tables,
565 * to guarantee consistency between TLB and page tables.
567 if (spte_is_bit_changed(old_spte
, new_spte
,
568 shadow_accessed_mask
| shadow_dirty_mask
))
571 if (spte_is_bit_cleared(old_spte
, new_spte
, shadow_accessed_mask
))
572 kvm_set_pfn_accessed(spte_to_pfn(old_spte
));
573 if (spte_is_bit_cleared(old_spte
, new_spte
, shadow_dirty_mask
))
574 kvm_set_pfn_dirty(spte_to_pfn(old_spte
));
580 * Rules for using mmu_spte_clear_track_bits:
581 * It sets the sptep from present to nonpresent, and track the
582 * state bits, it is used to clear the last level sptep.
584 static int mmu_spte_clear_track_bits(u64
*sptep
)
587 u64 old_spte
= *sptep
;
589 if (!spte_has_volatile_bits(old_spte
))
590 __update_clear_spte_fast(sptep
, 0ull);
592 old_spte
= __update_clear_spte_slow(sptep
, 0ull);
594 if (!is_shadow_present_pte(old_spte
))
597 pfn
= spte_to_pfn(old_spte
);
600 * KVM does not hold the refcount of the page used by
601 * kvm mmu, before reclaiming the page, we should
602 * unmap it from mmu first.
604 WARN_ON(!kvm_is_reserved_pfn(pfn
) && !page_count(pfn_to_page(pfn
)));
606 if (!shadow_accessed_mask
|| old_spte
& shadow_accessed_mask
)
607 kvm_set_pfn_accessed(pfn
);
608 if (!shadow_dirty_mask
|| (old_spte
& shadow_dirty_mask
))
609 kvm_set_pfn_dirty(pfn
);
614 * Rules for using mmu_spte_clear_no_track:
615 * Directly clear spte without caring the state bits of sptep,
616 * it is used to set the upper level spte.
618 static void mmu_spte_clear_no_track(u64
*sptep
)
620 __update_clear_spte_fast(sptep
, 0ull);
623 static u64
mmu_spte_get_lockless(u64
*sptep
)
625 return __get_spte_lockless(sptep
);
628 static void walk_shadow_page_lockless_begin(struct kvm_vcpu
*vcpu
)
631 * Prevent page table teardown by making any free-er wait during
632 * kvm_flush_remote_tlbs() IPI to all active vcpus.
637 * Make sure a following spte read is not reordered ahead of the write
640 smp_store_mb(vcpu
->mode
, READING_SHADOW_PAGE_TABLES
);
643 static void walk_shadow_page_lockless_end(struct kvm_vcpu
*vcpu
)
646 * Make sure the write to vcpu->mode is not reordered in front of
647 * reads to sptes. If it does, kvm_commit_zap_page() can see us
648 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
650 smp_store_release(&vcpu
->mode
, OUTSIDE_GUEST_MODE
);
654 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache
*cache
,
655 struct kmem_cache
*base_cache
, int min
)
659 if (cache
->nobjs
>= min
)
661 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
662 obj
= kmem_cache_zalloc(base_cache
, GFP_KERNEL
);
665 cache
->objects
[cache
->nobjs
++] = obj
;
670 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache
*cache
)
675 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache
*mc
,
676 struct kmem_cache
*cache
)
679 kmem_cache_free(cache
, mc
->objects
[--mc
->nobjs
]);
682 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache
*cache
,
687 if (cache
->nobjs
>= min
)
689 while (cache
->nobjs
< ARRAY_SIZE(cache
->objects
)) {
690 page
= (void *)__get_free_page(GFP_KERNEL
);
693 cache
->objects
[cache
->nobjs
++] = page
;
698 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache
*mc
)
701 free_page((unsigned long)mc
->objects
[--mc
->nobjs
]);
704 static int mmu_topup_memory_caches(struct kvm_vcpu
*vcpu
)
708 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
709 pte_list_desc_cache
, 8 + PTE_PREFETCH_NUM
);
712 r
= mmu_topup_memory_cache_page(&vcpu
->arch
.mmu_page_cache
, 8);
715 r
= mmu_topup_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
716 mmu_page_header_cache
, 4);
721 static void mmu_free_memory_caches(struct kvm_vcpu
*vcpu
)
723 mmu_free_memory_cache(&vcpu
->arch
.mmu_pte_list_desc_cache
,
724 pte_list_desc_cache
);
725 mmu_free_memory_cache_page(&vcpu
->arch
.mmu_page_cache
);
726 mmu_free_memory_cache(&vcpu
->arch
.mmu_page_header_cache
,
727 mmu_page_header_cache
);
730 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache
*mc
)
735 p
= mc
->objects
[--mc
->nobjs
];
739 static struct pte_list_desc
*mmu_alloc_pte_list_desc(struct kvm_vcpu
*vcpu
)
741 return mmu_memory_cache_alloc(&vcpu
->arch
.mmu_pte_list_desc_cache
);
744 static void mmu_free_pte_list_desc(struct pte_list_desc
*pte_list_desc
)
746 kmem_cache_free(pte_list_desc_cache
, pte_list_desc
);
749 static gfn_t
kvm_mmu_page_get_gfn(struct kvm_mmu_page
*sp
, int index
)
751 if (!sp
->role
.direct
)
752 return sp
->gfns
[index
];
754 return sp
->gfn
+ (index
<< ((sp
->role
.level
- 1) * PT64_LEVEL_BITS
));
757 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page
*sp
, int index
, gfn_t gfn
)
760 BUG_ON(gfn
!= kvm_mmu_page_get_gfn(sp
, index
));
762 sp
->gfns
[index
] = gfn
;
766 * Return the pointer to the large page information for a given gfn,
767 * handling slots that are not large page aligned.
769 static struct kvm_lpage_info
*lpage_info_slot(gfn_t gfn
,
770 struct kvm_memory_slot
*slot
,
775 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
776 return &slot
->arch
.lpage_info
[level
- 2][idx
];
779 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot
*slot
,
780 gfn_t gfn
, int count
)
782 struct kvm_lpage_info
*linfo
;
785 for (i
= PT_DIRECTORY_LEVEL
; i
<= PT_MAX_HUGEPAGE_LEVEL
; ++i
) {
786 linfo
= lpage_info_slot(gfn
, slot
, i
);
787 linfo
->disallow_lpage
+= count
;
788 WARN_ON(linfo
->disallow_lpage
< 0);
792 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot
*slot
, gfn_t gfn
)
794 update_gfn_disallow_lpage_count(slot
, gfn
, 1);
797 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot
*slot
, gfn_t gfn
)
799 update_gfn_disallow_lpage_count(slot
, gfn
, -1);
802 static void account_shadowed(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
804 struct kvm_memslots
*slots
;
805 struct kvm_memory_slot
*slot
;
808 kvm
->arch
.indirect_shadow_pages
++;
810 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
811 slot
= __gfn_to_memslot(slots
, gfn
);
813 /* the non-leaf shadow pages are keeping readonly. */
814 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
815 return kvm_slot_page_track_add_page(kvm
, slot
, gfn
,
816 KVM_PAGE_TRACK_WRITE
);
818 kvm_mmu_gfn_disallow_lpage(slot
, gfn
);
821 static void unaccount_shadowed(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
823 struct kvm_memslots
*slots
;
824 struct kvm_memory_slot
*slot
;
827 kvm
->arch
.indirect_shadow_pages
--;
829 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
830 slot
= __gfn_to_memslot(slots
, gfn
);
831 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
832 return kvm_slot_page_track_remove_page(kvm
, slot
, gfn
,
833 KVM_PAGE_TRACK_WRITE
);
835 kvm_mmu_gfn_allow_lpage(slot
, gfn
);
838 static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn
, int level
,
839 struct kvm_memory_slot
*slot
)
841 struct kvm_lpage_info
*linfo
;
844 linfo
= lpage_info_slot(gfn
, slot
, level
);
845 return !!linfo
->disallow_lpage
;
851 static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
854 struct kvm_memory_slot
*slot
;
856 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
857 return __mmu_gfn_lpage_is_disallowed(gfn
, level
, slot
);
860 static int host_mapping_level(struct kvm
*kvm
, gfn_t gfn
)
862 unsigned long page_size
;
865 page_size
= kvm_host_page_size(kvm
, gfn
);
867 for (i
= PT_PAGE_TABLE_LEVEL
; i
<= PT_MAX_HUGEPAGE_LEVEL
; ++i
) {
868 if (page_size
>= KVM_HPAGE_SIZE(i
))
877 static inline bool memslot_valid_for_gpte(struct kvm_memory_slot
*slot
,
880 if (!slot
|| slot
->flags
& KVM_MEMSLOT_INVALID
)
882 if (no_dirty_log
&& slot
->dirty_bitmap
)
888 static struct kvm_memory_slot
*
889 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
892 struct kvm_memory_slot
*slot
;
894 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
895 if (!memslot_valid_for_gpte(slot
, no_dirty_log
))
901 static int mapping_level(struct kvm_vcpu
*vcpu
, gfn_t large_gfn
,
902 bool *force_pt_level
)
904 int host_level
, level
, max_level
;
905 struct kvm_memory_slot
*slot
;
907 if (unlikely(*force_pt_level
))
908 return PT_PAGE_TABLE_LEVEL
;
910 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, large_gfn
);
911 *force_pt_level
= !memslot_valid_for_gpte(slot
, true);
912 if (unlikely(*force_pt_level
))
913 return PT_PAGE_TABLE_LEVEL
;
915 host_level
= host_mapping_level(vcpu
->kvm
, large_gfn
);
917 if (host_level
== PT_PAGE_TABLE_LEVEL
)
920 max_level
= min(kvm_x86_ops
->get_lpage_level(), host_level
);
922 for (level
= PT_DIRECTORY_LEVEL
; level
<= max_level
; ++level
)
923 if (__mmu_gfn_lpage_is_disallowed(large_gfn
, level
, slot
))
930 * About rmap_head encoding:
932 * If the bit zero of rmap_head->val is clear, then it points to the only spte
933 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
934 * pte_list_desc containing more mappings.
938 * Returns the number of pointers in the rmap chain, not counting the new one.
940 static int pte_list_add(struct kvm_vcpu
*vcpu
, u64
*spte
,
941 struct kvm_rmap_head
*rmap_head
)
943 struct pte_list_desc
*desc
;
946 if (!rmap_head
->val
) {
947 rmap_printk("pte_list_add: %p %llx 0->1\n", spte
, *spte
);
948 rmap_head
->val
= (unsigned long)spte
;
949 } else if (!(rmap_head
->val
& 1)) {
950 rmap_printk("pte_list_add: %p %llx 1->many\n", spte
, *spte
);
951 desc
= mmu_alloc_pte_list_desc(vcpu
);
952 desc
->sptes
[0] = (u64
*)rmap_head
->val
;
953 desc
->sptes
[1] = spte
;
954 rmap_head
->val
= (unsigned long)desc
| 1;
957 rmap_printk("pte_list_add: %p %llx many->many\n", spte
, *spte
);
958 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
959 while (desc
->sptes
[PTE_LIST_EXT
-1] && desc
->more
) {
961 count
+= PTE_LIST_EXT
;
963 if (desc
->sptes
[PTE_LIST_EXT
-1]) {
964 desc
->more
= mmu_alloc_pte_list_desc(vcpu
);
967 for (i
= 0; desc
->sptes
[i
]; ++i
)
969 desc
->sptes
[i
] = spte
;
975 pte_list_desc_remove_entry(struct kvm_rmap_head
*rmap_head
,
976 struct pte_list_desc
*desc
, int i
,
977 struct pte_list_desc
*prev_desc
)
981 for (j
= PTE_LIST_EXT
- 1; !desc
->sptes
[j
] && j
> i
; --j
)
983 desc
->sptes
[i
] = desc
->sptes
[j
];
984 desc
->sptes
[j
] = NULL
;
987 if (!prev_desc
&& !desc
->more
)
988 rmap_head
->val
= (unsigned long)desc
->sptes
[0];
991 prev_desc
->more
= desc
->more
;
993 rmap_head
->val
= (unsigned long)desc
->more
| 1;
994 mmu_free_pte_list_desc(desc
);
997 static void pte_list_remove(u64
*spte
, struct kvm_rmap_head
*rmap_head
)
999 struct pte_list_desc
*desc
;
1000 struct pte_list_desc
*prev_desc
;
1003 if (!rmap_head
->val
) {
1004 printk(KERN_ERR
"pte_list_remove: %p 0->BUG\n", spte
);
1006 } else if (!(rmap_head
->val
& 1)) {
1007 rmap_printk("pte_list_remove: %p 1->0\n", spte
);
1008 if ((u64
*)rmap_head
->val
!= spte
) {
1009 printk(KERN_ERR
"pte_list_remove: %p 1->BUG\n", spte
);
1014 rmap_printk("pte_list_remove: %p many->many\n", spte
);
1015 desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1018 for (i
= 0; i
< PTE_LIST_EXT
&& desc
->sptes
[i
]; ++i
) {
1019 if (desc
->sptes
[i
] == spte
) {
1020 pte_list_desc_remove_entry(rmap_head
,
1021 desc
, i
, prev_desc
);
1028 pr_err("pte_list_remove: %p many->many\n", spte
);
1033 static struct kvm_rmap_head
*__gfn_to_rmap(gfn_t gfn
, int level
,
1034 struct kvm_memory_slot
*slot
)
1038 idx
= gfn_to_index(gfn
, slot
->base_gfn
, level
);
1039 return &slot
->arch
.rmap
[level
- PT_PAGE_TABLE_LEVEL
][idx
];
1042 static struct kvm_rmap_head
*gfn_to_rmap(struct kvm
*kvm
, gfn_t gfn
,
1043 struct kvm_mmu_page
*sp
)
1045 struct kvm_memslots
*slots
;
1046 struct kvm_memory_slot
*slot
;
1048 slots
= kvm_memslots_for_spte_role(kvm
, sp
->role
);
1049 slot
= __gfn_to_memslot(slots
, gfn
);
1050 return __gfn_to_rmap(gfn
, sp
->role
.level
, slot
);
1053 static bool rmap_can_add(struct kvm_vcpu
*vcpu
)
1055 struct kvm_mmu_memory_cache
*cache
;
1057 cache
= &vcpu
->arch
.mmu_pte_list_desc_cache
;
1058 return mmu_memory_cache_free_objects(cache
);
1061 static int rmap_add(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1063 struct kvm_mmu_page
*sp
;
1064 struct kvm_rmap_head
*rmap_head
;
1066 sp
= page_header(__pa(spte
));
1067 kvm_mmu_page_set_gfn(sp
, spte
- sp
->spt
, gfn
);
1068 rmap_head
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
);
1069 return pte_list_add(vcpu
, spte
, rmap_head
);
1072 static void rmap_remove(struct kvm
*kvm
, u64
*spte
)
1074 struct kvm_mmu_page
*sp
;
1076 struct kvm_rmap_head
*rmap_head
;
1078 sp
= page_header(__pa(spte
));
1079 gfn
= kvm_mmu_page_get_gfn(sp
, spte
- sp
->spt
);
1080 rmap_head
= gfn_to_rmap(kvm
, gfn
, sp
);
1081 pte_list_remove(spte
, rmap_head
);
1085 * Used by the following functions to iterate through the sptes linked by a
1086 * rmap. All fields are private and not assumed to be used outside.
1088 struct rmap_iterator
{
1089 /* private fields */
1090 struct pte_list_desc
*desc
; /* holds the sptep if not NULL */
1091 int pos
; /* index of the sptep */
1095 * Iteration must be started by this function. This should also be used after
1096 * removing/dropping sptes from the rmap link because in such cases the
1097 * information in the itererator may not be valid.
1099 * Returns sptep if found, NULL otherwise.
1101 static u64
*rmap_get_first(struct kvm_rmap_head
*rmap_head
,
1102 struct rmap_iterator
*iter
)
1106 if (!rmap_head
->val
)
1109 if (!(rmap_head
->val
& 1)) {
1111 sptep
= (u64
*)rmap_head
->val
;
1115 iter
->desc
= (struct pte_list_desc
*)(rmap_head
->val
& ~1ul);
1117 sptep
= iter
->desc
->sptes
[iter
->pos
];
1119 BUG_ON(!is_shadow_present_pte(*sptep
));
1124 * Must be used with a valid iterator: e.g. after rmap_get_first().
1126 * Returns sptep if found, NULL otherwise.
1128 static u64
*rmap_get_next(struct rmap_iterator
*iter
)
1133 if (iter
->pos
< PTE_LIST_EXT
- 1) {
1135 sptep
= iter
->desc
->sptes
[iter
->pos
];
1140 iter
->desc
= iter
->desc
->more
;
1144 /* desc->sptes[0] cannot be NULL */
1145 sptep
= iter
->desc
->sptes
[iter
->pos
];
1152 BUG_ON(!is_shadow_present_pte(*sptep
));
1156 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1157 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1158 _spte_; _spte_ = rmap_get_next(_iter_))
1160 static void drop_spte(struct kvm
*kvm
, u64
*sptep
)
1162 if (mmu_spte_clear_track_bits(sptep
))
1163 rmap_remove(kvm
, sptep
);
1167 static bool __drop_large_spte(struct kvm
*kvm
, u64
*sptep
)
1169 if (is_large_pte(*sptep
)) {
1170 WARN_ON(page_header(__pa(sptep
))->role
.level
==
1171 PT_PAGE_TABLE_LEVEL
);
1172 drop_spte(kvm
, sptep
);
1180 static void drop_large_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
)
1182 if (__drop_large_spte(vcpu
->kvm
, sptep
))
1183 kvm_flush_remote_tlbs(vcpu
->kvm
);
1187 * Write-protect on the specified @sptep, @pt_protect indicates whether
1188 * spte write-protection is caused by protecting shadow page table.
1190 * Note: write protection is difference between dirty logging and spte
1192 * - for dirty logging, the spte can be set to writable at anytime if
1193 * its dirty bitmap is properly set.
1194 * - for spte protection, the spte can be writable only after unsync-ing
1197 * Return true if tlb need be flushed.
1199 static bool spte_write_protect(struct kvm
*kvm
, u64
*sptep
, bool pt_protect
)
1203 if (!is_writable_pte(spte
) &&
1204 !(pt_protect
&& spte_is_locklessly_modifiable(spte
)))
1207 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep
, *sptep
);
1210 spte
&= ~SPTE_MMU_WRITEABLE
;
1211 spte
= spte
& ~PT_WRITABLE_MASK
;
1213 return mmu_spte_update(sptep
, spte
);
1216 static bool __rmap_write_protect(struct kvm
*kvm
,
1217 struct kvm_rmap_head
*rmap_head
,
1221 struct rmap_iterator iter
;
1224 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1225 flush
|= spte_write_protect(kvm
, sptep
, pt_protect
);
1230 static bool spte_clear_dirty(struct kvm
*kvm
, u64
*sptep
)
1234 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep
, *sptep
);
1236 spte
&= ~shadow_dirty_mask
;
1238 return mmu_spte_update(sptep
, spte
);
1241 static bool __rmap_clear_dirty(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1244 struct rmap_iterator iter
;
1247 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1248 flush
|= spte_clear_dirty(kvm
, sptep
);
1253 static bool spte_set_dirty(struct kvm
*kvm
, u64
*sptep
)
1257 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep
, *sptep
);
1259 spte
|= shadow_dirty_mask
;
1261 return mmu_spte_update(sptep
, spte
);
1264 static bool __rmap_set_dirty(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1267 struct rmap_iterator iter
;
1270 for_each_rmap_spte(rmap_head
, &iter
, sptep
)
1271 flush
|= spte_set_dirty(kvm
, sptep
);
1277 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1278 * @kvm: kvm instance
1279 * @slot: slot to protect
1280 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1281 * @mask: indicates which pages we should protect
1283 * Used when we do not need to care about huge page mappings: e.g. during dirty
1284 * logging we do not have any such mappings.
1286 static void kvm_mmu_write_protect_pt_masked(struct kvm
*kvm
,
1287 struct kvm_memory_slot
*slot
,
1288 gfn_t gfn_offset
, unsigned long mask
)
1290 struct kvm_rmap_head
*rmap_head
;
1293 rmap_head
= __gfn_to_rmap(slot
->base_gfn
+ gfn_offset
+ __ffs(mask
),
1294 PT_PAGE_TABLE_LEVEL
, slot
);
1295 __rmap_write_protect(kvm
, rmap_head
, false);
1297 /* clear the first set bit */
1303 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages
1304 * @kvm: kvm instance
1305 * @slot: slot to clear D-bit
1306 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1307 * @mask: indicates which pages we should clear D-bit
1309 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1311 void kvm_mmu_clear_dirty_pt_masked(struct kvm
*kvm
,
1312 struct kvm_memory_slot
*slot
,
1313 gfn_t gfn_offset
, unsigned long mask
)
1315 struct kvm_rmap_head
*rmap_head
;
1318 rmap_head
= __gfn_to_rmap(slot
->base_gfn
+ gfn_offset
+ __ffs(mask
),
1319 PT_PAGE_TABLE_LEVEL
, slot
);
1320 __rmap_clear_dirty(kvm
, rmap_head
);
1322 /* clear the first set bit */
1326 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked
);
1329 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1332 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1333 * enable dirty logging for them.
1335 * Used when we do not need to care about huge page mappings: e.g. during dirty
1336 * logging we do not have any such mappings.
1338 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm
*kvm
,
1339 struct kvm_memory_slot
*slot
,
1340 gfn_t gfn_offset
, unsigned long mask
)
1342 if (kvm_x86_ops
->enable_log_dirty_pt_masked
)
1343 kvm_x86_ops
->enable_log_dirty_pt_masked(kvm
, slot
, gfn_offset
,
1346 kvm_mmu_write_protect_pt_masked(kvm
, slot
, gfn_offset
, mask
);
1349 bool kvm_mmu_slot_gfn_write_protect(struct kvm
*kvm
,
1350 struct kvm_memory_slot
*slot
, u64 gfn
)
1352 struct kvm_rmap_head
*rmap_head
;
1354 bool write_protected
= false;
1356 for (i
= PT_PAGE_TABLE_LEVEL
; i
<= PT_MAX_HUGEPAGE_LEVEL
; ++i
) {
1357 rmap_head
= __gfn_to_rmap(gfn
, i
, slot
);
1358 write_protected
|= __rmap_write_protect(kvm
, rmap_head
, true);
1361 return write_protected
;
1364 static bool rmap_write_protect(struct kvm_vcpu
*vcpu
, u64 gfn
)
1366 struct kvm_memory_slot
*slot
;
1368 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
1369 return kvm_mmu_slot_gfn_write_protect(vcpu
->kvm
, slot
, gfn
);
1372 static bool kvm_zap_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
)
1375 struct rmap_iterator iter
;
1378 while ((sptep
= rmap_get_first(rmap_head
, &iter
))) {
1379 rmap_printk("%s: spte %p %llx.\n", __func__
, sptep
, *sptep
);
1381 drop_spte(kvm
, sptep
);
1388 static int kvm_unmap_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1389 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1392 return kvm_zap_rmapp(kvm
, rmap_head
);
1395 static int kvm_set_pte_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1396 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1400 struct rmap_iterator iter
;
1403 pte_t
*ptep
= (pte_t
*)data
;
1406 WARN_ON(pte_huge(*ptep
));
1407 new_pfn
= pte_pfn(*ptep
);
1410 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
1411 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1412 sptep
, *sptep
, gfn
, level
);
1416 if (pte_write(*ptep
)) {
1417 drop_spte(kvm
, sptep
);
1420 new_spte
= *sptep
& ~PT64_BASE_ADDR_MASK
;
1421 new_spte
|= (u64
)new_pfn
<< PAGE_SHIFT
;
1423 new_spte
&= ~PT_WRITABLE_MASK
;
1424 new_spte
&= ~SPTE_HOST_WRITEABLE
;
1425 new_spte
&= ~shadow_accessed_mask
;
1427 mmu_spte_clear_track_bits(sptep
);
1428 mmu_spte_set(sptep
, new_spte
);
1433 kvm_flush_remote_tlbs(kvm
);
1438 struct slot_rmap_walk_iterator
{
1440 struct kvm_memory_slot
*slot
;
1446 /* output fields. */
1448 struct kvm_rmap_head
*rmap
;
1451 /* private field. */
1452 struct kvm_rmap_head
*end_rmap
;
1456 rmap_walk_init_level(struct slot_rmap_walk_iterator
*iterator
, int level
)
1458 iterator
->level
= level
;
1459 iterator
->gfn
= iterator
->start_gfn
;
1460 iterator
->rmap
= __gfn_to_rmap(iterator
->gfn
, level
, iterator
->slot
);
1461 iterator
->end_rmap
= __gfn_to_rmap(iterator
->end_gfn
, level
,
1466 slot_rmap_walk_init(struct slot_rmap_walk_iterator
*iterator
,
1467 struct kvm_memory_slot
*slot
, int start_level
,
1468 int end_level
, gfn_t start_gfn
, gfn_t end_gfn
)
1470 iterator
->slot
= slot
;
1471 iterator
->start_level
= start_level
;
1472 iterator
->end_level
= end_level
;
1473 iterator
->start_gfn
= start_gfn
;
1474 iterator
->end_gfn
= end_gfn
;
1476 rmap_walk_init_level(iterator
, iterator
->start_level
);
1479 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator
*iterator
)
1481 return !!iterator
->rmap
;
1484 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator
*iterator
)
1486 if (++iterator
->rmap
<= iterator
->end_rmap
) {
1487 iterator
->gfn
+= (1UL << KVM_HPAGE_GFN_SHIFT(iterator
->level
));
1491 if (++iterator
->level
> iterator
->end_level
) {
1492 iterator
->rmap
= NULL
;
1496 rmap_walk_init_level(iterator
, iterator
->level
);
1499 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1500 _start_gfn, _end_gfn, _iter_) \
1501 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1502 _end_level_, _start_gfn, _end_gfn); \
1503 slot_rmap_walk_okay(_iter_); \
1504 slot_rmap_walk_next(_iter_))
1506 static int kvm_handle_hva_range(struct kvm
*kvm
,
1507 unsigned long start
,
1510 int (*handler
)(struct kvm
*kvm
,
1511 struct kvm_rmap_head
*rmap_head
,
1512 struct kvm_memory_slot
*slot
,
1515 unsigned long data
))
1517 struct kvm_memslots
*slots
;
1518 struct kvm_memory_slot
*memslot
;
1519 struct slot_rmap_walk_iterator iterator
;
1523 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
1524 slots
= __kvm_memslots(kvm
, i
);
1525 kvm_for_each_memslot(memslot
, slots
) {
1526 unsigned long hva_start
, hva_end
;
1527 gfn_t gfn_start
, gfn_end
;
1529 hva_start
= max(start
, memslot
->userspace_addr
);
1530 hva_end
= min(end
, memslot
->userspace_addr
+
1531 (memslot
->npages
<< PAGE_SHIFT
));
1532 if (hva_start
>= hva_end
)
1535 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1536 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1538 gfn_start
= hva_to_gfn_memslot(hva_start
, memslot
);
1539 gfn_end
= hva_to_gfn_memslot(hva_end
+ PAGE_SIZE
- 1, memslot
);
1541 for_each_slot_rmap_range(memslot
, PT_PAGE_TABLE_LEVEL
,
1542 PT_MAX_HUGEPAGE_LEVEL
,
1543 gfn_start
, gfn_end
- 1,
1545 ret
|= handler(kvm
, iterator
.rmap
, memslot
,
1546 iterator
.gfn
, iterator
.level
, data
);
1553 static int kvm_handle_hva(struct kvm
*kvm
, unsigned long hva
,
1555 int (*handler
)(struct kvm
*kvm
,
1556 struct kvm_rmap_head
*rmap_head
,
1557 struct kvm_memory_slot
*slot
,
1558 gfn_t gfn
, int level
,
1559 unsigned long data
))
1561 return kvm_handle_hva_range(kvm
, hva
, hva
+ 1, data
, handler
);
1564 int kvm_unmap_hva(struct kvm
*kvm
, unsigned long hva
)
1566 return kvm_handle_hva(kvm
, hva
, 0, kvm_unmap_rmapp
);
1569 int kvm_unmap_hva_range(struct kvm
*kvm
, unsigned long start
, unsigned long end
)
1571 return kvm_handle_hva_range(kvm
, start
, end
, 0, kvm_unmap_rmapp
);
1574 void kvm_set_spte_hva(struct kvm
*kvm
, unsigned long hva
, pte_t pte
)
1576 kvm_handle_hva(kvm
, hva
, (unsigned long)&pte
, kvm_set_pte_rmapp
);
1579 static int kvm_age_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1580 struct kvm_memory_slot
*slot
, gfn_t gfn
, int level
,
1584 struct rmap_iterator
uninitialized_var(iter
);
1587 BUG_ON(!shadow_accessed_mask
);
1589 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
1590 if (*sptep
& shadow_accessed_mask
) {
1592 clear_bit((ffs(shadow_accessed_mask
) - 1),
1593 (unsigned long *)sptep
);
1597 trace_kvm_age_page(gfn
, level
, slot
, young
);
1601 static int kvm_test_age_rmapp(struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
,
1602 struct kvm_memory_slot
*slot
, gfn_t gfn
,
1603 int level
, unsigned long data
)
1606 struct rmap_iterator iter
;
1610 * If there's no access bit in the secondary pte set by the
1611 * hardware it's up to gup-fast/gup to set the access bit in
1612 * the primary pte or in the page structure.
1614 if (!shadow_accessed_mask
)
1617 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
1618 if (*sptep
& shadow_accessed_mask
) {
1627 #define RMAP_RECYCLE_THRESHOLD 1000
1629 static void rmap_recycle(struct kvm_vcpu
*vcpu
, u64
*spte
, gfn_t gfn
)
1631 struct kvm_rmap_head
*rmap_head
;
1632 struct kvm_mmu_page
*sp
;
1634 sp
= page_header(__pa(spte
));
1636 rmap_head
= gfn_to_rmap(vcpu
->kvm
, gfn
, sp
);
1638 kvm_unmap_rmapp(vcpu
->kvm
, rmap_head
, NULL
, gfn
, sp
->role
.level
, 0);
1639 kvm_flush_remote_tlbs(vcpu
->kvm
);
1642 int kvm_age_hva(struct kvm
*kvm
, unsigned long start
, unsigned long end
)
1645 * In case of absence of EPT Access and Dirty Bits supports,
1646 * emulate the accessed bit for EPT, by checking if this page has
1647 * an EPT mapping, and clearing it if it does. On the next access,
1648 * a new EPT mapping will be established.
1649 * This has some overhead, but not as much as the cost of swapping
1650 * out actively used pages or breaking up actively used hugepages.
1652 if (!shadow_accessed_mask
) {
1654 * We are holding the kvm->mmu_lock, and we are blowing up
1655 * shadow PTEs. MMU notifier consumers need to be kept at bay.
1656 * This is correct as long as we don't decouple the mmu_lock
1657 * protected regions (like invalidate_range_start|end does).
1659 kvm
->mmu_notifier_seq
++;
1660 return kvm_handle_hva_range(kvm
, start
, end
, 0,
1664 return kvm_handle_hva_range(kvm
, start
, end
, 0, kvm_age_rmapp
);
1667 int kvm_test_age_hva(struct kvm
*kvm
, unsigned long hva
)
1669 return kvm_handle_hva(kvm
, hva
, 0, kvm_test_age_rmapp
);
1673 static int is_empty_shadow_page(u64
*spt
)
1678 for (pos
= spt
, end
= pos
+ PAGE_SIZE
/ sizeof(u64
); pos
!= end
; pos
++)
1679 if (is_shadow_present_pte(*pos
)) {
1680 printk(KERN_ERR
"%s: %p %llx\n", __func__
,
1689 * This value is the sum of all of the kvm instances's
1690 * kvm->arch.n_used_mmu_pages values. We need a global,
1691 * aggregate version in order to make the slab shrinker
1694 static inline void kvm_mod_used_mmu_pages(struct kvm
*kvm
, int nr
)
1696 kvm
->arch
.n_used_mmu_pages
+= nr
;
1697 percpu_counter_add(&kvm_total_used_mmu_pages
, nr
);
1700 static void kvm_mmu_free_page(struct kvm_mmu_page
*sp
)
1702 MMU_WARN_ON(!is_empty_shadow_page(sp
->spt
));
1703 hlist_del(&sp
->hash_link
);
1704 list_del(&sp
->link
);
1705 free_page((unsigned long)sp
->spt
);
1706 if (!sp
->role
.direct
)
1707 free_page((unsigned long)sp
->gfns
);
1708 kmem_cache_free(mmu_page_header_cache
, sp
);
1711 static unsigned kvm_page_table_hashfn(gfn_t gfn
)
1713 return gfn
& ((1 << KVM_MMU_HASH_SHIFT
) - 1);
1716 static void mmu_page_add_parent_pte(struct kvm_vcpu
*vcpu
,
1717 struct kvm_mmu_page
*sp
, u64
*parent_pte
)
1722 pte_list_add(vcpu
, parent_pte
, &sp
->parent_ptes
);
1725 static void mmu_page_remove_parent_pte(struct kvm_mmu_page
*sp
,
1728 pte_list_remove(parent_pte
, &sp
->parent_ptes
);
1731 static void drop_parent_pte(struct kvm_mmu_page
*sp
,
1734 mmu_page_remove_parent_pte(sp
, parent_pte
);
1735 mmu_spte_clear_no_track(parent_pte
);
1738 static struct kvm_mmu_page
*kvm_mmu_alloc_page(struct kvm_vcpu
*vcpu
, int direct
)
1740 struct kvm_mmu_page
*sp
;
1742 sp
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_header_cache
);
1743 sp
->spt
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
);
1745 sp
->gfns
= mmu_memory_cache_alloc(&vcpu
->arch
.mmu_page_cache
);
1746 set_page_private(virt_to_page(sp
->spt
), (unsigned long)sp
);
1749 * The active_mmu_pages list is the FIFO list, do not move the
1750 * page until it is zapped. kvm_zap_obsolete_pages depends on
1751 * this feature. See the comments in kvm_zap_obsolete_pages().
1753 list_add(&sp
->link
, &vcpu
->kvm
->arch
.active_mmu_pages
);
1754 kvm_mod_used_mmu_pages(vcpu
->kvm
, +1);
1758 static void mark_unsync(u64
*spte
);
1759 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page
*sp
)
1762 struct rmap_iterator iter
;
1764 for_each_rmap_spte(&sp
->parent_ptes
, &iter
, sptep
) {
1769 static void mark_unsync(u64
*spte
)
1771 struct kvm_mmu_page
*sp
;
1774 sp
= page_header(__pa(spte
));
1775 index
= spte
- sp
->spt
;
1776 if (__test_and_set_bit(index
, sp
->unsync_child_bitmap
))
1778 if (sp
->unsync_children
++)
1780 kvm_mmu_mark_parents_unsync(sp
);
1783 static int nonpaging_sync_page(struct kvm_vcpu
*vcpu
,
1784 struct kvm_mmu_page
*sp
)
1789 static void nonpaging_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
1793 static void nonpaging_update_pte(struct kvm_vcpu
*vcpu
,
1794 struct kvm_mmu_page
*sp
, u64
*spte
,
1800 #define KVM_PAGE_ARRAY_NR 16
1802 struct kvm_mmu_pages
{
1803 struct mmu_page_and_offset
{
1804 struct kvm_mmu_page
*sp
;
1806 } page
[KVM_PAGE_ARRAY_NR
];
1810 static int mmu_pages_add(struct kvm_mmu_pages
*pvec
, struct kvm_mmu_page
*sp
,
1816 for (i
=0; i
< pvec
->nr
; i
++)
1817 if (pvec
->page
[i
].sp
== sp
)
1820 pvec
->page
[pvec
->nr
].sp
= sp
;
1821 pvec
->page
[pvec
->nr
].idx
= idx
;
1823 return (pvec
->nr
== KVM_PAGE_ARRAY_NR
);
1826 static inline void clear_unsync_child_bit(struct kvm_mmu_page
*sp
, int idx
)
1828 --sp
->unsync_children
;
1829 WARN_ON((int)sp
->unsync_children
< 0);
1830 __clear_bit(idx
, sp
->unsync_child_bitmap
);
1833 static int __mmu_unsync_walk(struct kvm_mmu_page
*sp
,
1834 struct kvm_mmu_pages
*pvec
)
1836 int i
, ret
, nr_unsync_leaf
= 0;
1838 for_each_set_bit(i
, sp
->unsync_child_bitmap
, 512) {
1839 struct kvm_mmu_page
*child
;
1840 u64 ent
= sp
->spt
[i
];
1842 if (!is_shadow_present_pte(ent
) || is_large_pte(ent
)) {
1843 clear_unsync_child_bit(sp
, i
);
1847 child
= page_header(ent
& PT64_BASE_ADDR_MASK
);
1849 if (child
->unsync_children
) {
1850 if (mmu_pages_add(pvec
, child
, i
))
1853 ret
= __mmu_unsync_walk(child
, pvec
);
1855 clear_unsync_child_bit(sp
, i
);
1857 } else if (ret
> 0) {
1858 nr_unsync_leaf
+= ret
;
1861 } else if (child
->unsync
) {
1863 if (mmu_pages_add(pvec
, child
, i
))
1866 clear_unsync_child_bit(sp
, i
);
1869 return nr_unsync_leaf
;
1872 #define INVALID_INDEX (-1)
1874 static int mmu_unsync_walk(struct kvm_mmu_page
*sp
,
1875 struct kvm_mmu_pages
*pvec
)
1878 if (!sp
->unsync_children
)
1881 mmu_pages_add(pvec
, sp
, INVALID_INDEX
);
1882 return __mmu_unsync_walk(sp
, pvec
);
1885 static void kvm_unlink_unsync_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
1887 WARN_ON(!sp
->unsync
);
1888 trace_kvm_mmu_sync_page(sp
);
1890 --kvm
->stat
.mmu_unsync
;
1893 static int kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
1894 struct list_head
*invalid_list
);
1895 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
1896 struct list_head
*invalid_list
);
1899 * NOTE: we should pay more attention on the zapped-obsolete page
1900 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
1901 * since it has been deleted from active_mmu_pages but still can be found
1904 * for_each_gfn_indirect_valid_sp has skipped that kind of page and
1905 * kvm_mmu_get_page(), the only user of for_each_gfn_sp(), has skipped
1906 * all the obsolete pages.
1908 #define for_each_gfn_sp(_kvm, _sp, _gfn) \
1909 hlist_for_each_entry(_sp, \
1910 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
1911 if ((_sp)->gfn != (_gfn)) {} else
1913 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1914 for_each_gfn_sp(_kvm, _sp, _gfn) \
1915 if ((_sp)->role.direct || (_sp)->role.invalid) {} else
1917 /* @sp->gfn should be write-protected at the call site */
1918 static bool __kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
1919 struct list_head
*invalid_list
)
1921 if (sp
->role
.cr4_pae
!= !!is_pae(vcpu
)) {
1922 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
1926 if (vcpu
->arch
.mmu
.sync_page(vcpu
, sp
) == 0) {
1927 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, invalid_list
);
1934 static void kvm_mmu_flush_or_zap(struct kvm_vcpu
*vcpu
,
1935 struct list_head
*invalid_list
,
1936 bool remote_flush
, bool local_flush
)
1938 if (!list_empty(invalid_list
)) {
1939 kvm_mmu_commit_zap_page(vcpu
->kvm
, invalid_list
);
1944 kvm_flush_remote_tlbs(vcpu
->kvm
);
1945 else if (local_flush
)
1946 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1949 #ifdef CONFIG_KVM_MMU_AUDIT
1950 #include "mmu_audit.c"
1952 static void kvm_mmu_audit(struct kvm_vcpu
*vcpu
, int point
) { }
1953 static void mmu_audit_disable(void) { }
1956 static bool kvm_sync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
1957 struct list_head
*invalid_list
)
1959 kvm_unlink_unsync_page(vcpu
->kvm
, sp
);
1960 return __kvm_sync_page(vcpu
, sp
, invalid_list
);
1963 /* @gfn should be write-protected at the call site */
1964 static bool kvm_sync_pages(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
1965 struct list_head
*invalid_list
)
1967 struct kvm_mmu_page
*s
;
1970 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, s
, gfn
) {
1974 WARN_ON(s
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
1975 ret
|= kvm_sync_page(vcpu
, s
, invalid_list
);
1981 struct mmu_page_path
{
1982 struct kvm_mmu_page
*parent
[PT64_ROOT_LEVEL
];
1983 unsigned int idx
[PT64_ROOT_LEVEL
];
1986 #define for_each_sp(pvec, sp, parents, i) \
1987 for (i = mmu_pages_first(&pvec, &parents); \
1988 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1989 i = mmu_pages_next(&pvec, &parents, i))
1991 static int mmu_pages_next(struct kvm_mmu_pages
*pvec
,
1992 struct mmu_page_path
*parents
,
1997 for (n
= i
+1; n
< pvec
->nr
; n
++) {
1998 struct kvm_mmu_page
*sp
= pvec
->page
[n
].sp
;
1999 unsigned idx
= pvec
->page
[n
].idx
;
2000 int level
= sp
->role
.level
;
2002 parents
->idx
[level
-1] = idx
;
2003 if (level
== PT_PAGE_TABLE_LEVEL
)
2006 parents
->parent
[level
-2] = sp
;
2012 static int mmu_pages_first(struct kvm_mmu_pages
*pvec
,
2013 struct mmu_page_path
*parents
)
2015 struct kvm_mmu_page
*sp
;
2021 WARN_ON(pvec
->page
[0].idx
!= INVALID_INDEX
);
2023 sp
= pvec
->page
[0].sp
;
2024 level
= sp
->role
.level
;
2025 WARN_ON(level
== PT_PAGE_TABLE_LEVEL
);
2027 parents
->parent
[level
-2] = sp
;
2029 /* Also set up a sentinel. Further entries in pvec are all
2030 * children of sp, so this element is never overwritten.
2032 parents
->parent
[level
-1] = NULL
;
2033 return mmu_pages_next(pvec
, parents
, 0);
2036 static void mmu_pages_clear_parents(struct mmu_page_path
*parents
)
2038 struct kvm_mmu_page
*sp
;
2039 unsigned int level
= 0;
2042 unsigned int idx
= parents
->idx
[level
];
2043 sp
= parents
->parent
[level
];
2047 WARN_ON(idx
== INVALID_INDEX
);
2048 clear_unsync_child_bit(sp
, idx
);
2050 } while (!sp
->unsync_children
);
2053 static void mmu_sync_children(struct kvm_vcpu
*vcpu
,
2054 struct kvm_mmu_page
*parent
)
2057 struct kvm_mmu_page
*sp
;
2058 struct mmu_page_path parents
;
2059 struct kvm_mmu_pages pages
;
2060 LIST_HEAD(invalid_list
);
2063 while (mmu_unsync_walk(parent
, &pages
)) {
2064 bool protected = false;
2066 for_each_sp(pages
, sp
, parents
, i
)
2067 protected |= rmap_write_protect(vcpu
, sp
->gfn
);
2070 kvm_flush_remote_tlbs(vcpu
->kvm
);
2074 for_each_sp(pages
, sp
, parents
, i
) {
2075 flush
|= kvm_sync_page(vcpu
, sp
, &invalid_list
);
2076 mmu_pages_clear_parents(&parents
);
2078 if (need_resched() || spin_needbreak(&vcpu
->kvm
->mmu_lock
)) {
2079 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2080 cond_resched_lock(&vcpu
->kvm
->mmu_lock
);
2085 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2088 static void __clear_sp_write_flooding_count(struct kvm_mmu_page
*sp
)
2090 atomic_set(&sp
->write_flooding_count
, 0);
2093 static void clear_sp_write_flooding_count(u64
*spte
)
2095 struct kvm_mmu_page
*sp
= page_header(__pa(spte
));
2097 __clear_sp_write_flooding_count(sp
);
2100 static bool is_obsolete_sp(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2102 return unlikely(sp
->mmu_valid_gen
!= kvm
->arch
.mmu_valid_gen
);
2105 static struct kvm_mmu_page
*kvm_mmu_get_page(struct kvm_vcpu
*vcpu
,
2112 union kvm_mmu_page_role role
;
2114 struct kvm_mmu_page
*sp
;
2115 bool need_sync
= false;
2117 LIST_HEAD(invalid_list
);
2119 role
= vcpu
->arch
.mmu
.base_role
;
2121 role
.direct
= direct
;
2124 role
.access
= access
;
2125 if (!vcpu
->arch
.mmu
.direct_map
2126 && vcpu
->arch
.mmu
.root_level
<= PT32_ROOT_LEVEL
) {
2127 quadrant
= gaddr
>> (PAGE_SHIFT
+ (PT64_PT_BITS
* level
));
2128 quadrant
&= (1 << ((PT32_PT_BITS
- PT64_PT_BITS
) * level
)) - 1;
2129 role
.quadrant
= quadrant
;
2131 for_each_gfn_sp(vcpu
->kvm
, sp
, gfn
) {
2132 if (is_obsolete_sp(vcpu
->kvm
, sp
))
2135 if (!need_sync
&& sp
->unsync
)
2138 if (sp
->role
.word
!= role
.word
)
2142 /* The page is good, but __kvm_sync_page might still end
2143 * up zapping it. If so, break in order to rebuild it.
2145 if (!__kvm_sync_page(vcpu
, sp
, &invalid_list
))
2148 WARN_ON(!list_empty(&invalid_list
));
2149 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2152 if (sp
->unsync_children
)
2153 kvm_make_request(KVM_REQ_MMU_SYNC
, vcpu
);
2155 __clear_sp_write_flooding_count(sp
);
2156 trace_kvm_mmu_get_page(sp
, false);
2160 ++vcpu
->kvm
->stat
.mmu_cache_miss
;
2162 sp
= kvm_mmu_alloc_page(vcpu
, direct
);
2166 hlist_add_head(&sp
->hash_link
,
2167 &vcpu
->kvm
->arch
.mmu_page_hash
[kvm_page_table_hashfn(gfn
)]);
2170 * we should do write protection before syncing pages
2171 * otherwise the content of the synced shadow page may
2172 * be inconsistent with guest page table.
2174 account_shadowed(vcpu
->kvm
, sp
);
2175 if (level
== PT_PAGE_TABLE_LEVEL
&&
2176 rmap_write_protect(vcpu
, gfn
))
2177 kvm_flush_remote_tlbs(vcpu
->kvm
);
2179 if (level
> PT_PAGE_TABLE_LEVEL
&& need_sync
)
2180 flush
|= kvm_sync_pages(vcpu
, gfn
, &invalid_list
);
2182 sp
->mmu_valid_gen
= vcpu
->kvm
->arch
.mmu_valid_gen
;
2183 clear_page(sp
->spt
);
2184 trace_kvm_mmu_get_page(sp
, true);
2186 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, false, flush
);
2190 static void shadow_walk_init(struct kvm_shadow_walk_iterator
*iterator
,
2191 struct kvm_vcpu
*vcpu
, u64 addr
)
2193 iterator
->addr
= addr
;
2194 iterator
->shadow_addr
= vcpu
->arch
.mmu
.root_hpa
;
2195 iterator
->level
= vcpu
->arch
.mmu
.shadow_root_level
;
2197 if (iterator
->level
== PT64_ROOT_LEVEL
&&
2198 vcpu
->arch
.mmu
.root_level
< PT64_ROOT_LEVEL
&&
2199 !vcpu
->arch
.mmu
.direct_map
)
2202 if (iterator
->level
== PT32E_ROOT_LEVEL
) {
2203 iterator
->shadow_addr
2204 = vcpu
->arch
.mmu
.pae_root
[(addr
>> 30) & 3];
2205 iterator
->shadow_addr
&= PT64_BASE_ADDR_MASK
;
2207 if (!iterator
->shadow_addr
)
2208 iterator
->level
= 0;
2212 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator
*iterator
)
2214 if (iterator
->level
< PT_PAGE_TABLE_LEVEL
)
2217 iterator
->index
= SHADOW_PT_INDEX(iterator
->addr
, iterator
->level
);
2218 iterator
->sptep
= ((u64
*)__va(iterator
->shadow_addr
)) + iterator
->index
;
2222 static void __shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
,
2225 if (is_last_spte(spte
, iterator
->level
)) {
2226 iterator
->level
= 0;
2230 iterator
->shadow_addr
= spte
& PT64_BASE_ADDR_MASK
;
2234 static void shadow_walk_next(struct kvm_shadow_walk_iterator
*iterator
)
2236 return __shadow_walk_next(iterator
, *iterator
->sptep
);
2239 static void link_shadow_page(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2240 struct kvm_mmu_page
*sp
)
2244 BUILD_BUG_ON(VMX_EPT_READABLE_MASK
!= PT_PRESENT_MASK
||
2245 VMX_EPT_WRITABLE_MASK
!= PT_WRITABLE_MASK
);
2247 spte
= __pa(sp
->spt
) | PT_PRESENT_MASK
| PT_WRITABLE_MASK
|
2248 shadow_user_mask
| shadow_x_mask
| shadow_accessed_mask
;
2250 mmu_spte_set(sptep
, spte
);
2252 mmu_page_add_parent_pte(vcpu
, sp
, sptep
);
2254 if (sp
->unsync_children
|| sp
->unsync
)
2258 static void validate_direct_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2259 unsigned direct_access
)
2261 if (is_shadow_present_pte(*sptep
) && !is_large_pte(*sptep
)) {
2262 struct kvm_mmu_page
*child
;
2265 * For the direct sp, if the guest pte's dirty bit
2266 * changed form clean to dirty, it will corrupt the
2267 * sp's access: allow writable in the read-only sp,
2268 * so we should update the spte at this point to get
2269 * a new sp with the correct access.
2271 child
= page_header(*sptep
& PT64_BASE_ADDR_MASK
);
2272 if (child
->role
.access
== direct_access
)
2275 drop_parent_pte(child
, sptep
);
2276 kvm_flush_remote_tlbs(vcpu
->kvm
);
2280 static bool mmu_page_zap_pte(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2284 struct kvm_mmu_page
*child
;
2287 if (is_shadow_present_pte(pte
)) {
2288 if (is_last_spte(pte
, sp
->role
.level
)) {
2289 drop_spte(kvm
, spte
);
2290 if (is_large_pte(pte
))
2293 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
2294 drop_parent_pte(child
, spte
);
2299 if (is_mmio_spte(pte
))
2300 mmu_spte_clear_no_track(spte
);
2305 static void kvm_mmu_page_unlink_children(struct kvm
*kvm
,
2306 struct kvm_mmu_page
*sp
)
2310 for (i
= 0; i
< PT64_ENT_PER_PAGE
; ++i
)
2311 mmu_page_zap_pte(kvm
, sp
, sp
->spt
+ i
);
2314 static void kvm_mmu_unlink_parents(struct kvm
*kvm
, struct kvm_mmu_page
*sp
)
2317 struct rmap_iterator iter
;
2319 while ((sptep
= rmap_get_first(&sp
->parent_ptes
, &iter
)))
2320 drop_parent_pte(sp
, sptep
);
2323 static int mmu_zap_unsync_children(struct kvm
*kvm
,
2324 struct kvm_mmu_page
*parent
,
2325 struct list_head
*invalid_list
)
2328 struct mmu_page_path parents
;
2329 struct kvm_mmu_pages pages
;
2331 if (parent
->role
.level
== PT_PAGE_TABLE_LEVEL
)
2334 while (mmu_unsync_walk(parent
, &pages
)) {
2335 struct kvm_mmu_page
*sp
;
2337 for_each_sp(pages
, sp
, parents
, i
) {
2338 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
2339 mmu_pages_clear_parents(&parents
);
2347 static int kvm_mmu_prepare_zap_page(struct kvm
*kvm
, struct kvm_mmu_page
*sp
,
2348 struct list_head
*invalid_list
)
2352 trace_kvm_mmu_prepare_zap_page(sp
);
2353 ++kvm
->stat
.mmu_shadow_zapped
;
2354 ret
= mmu_zap_unsync_children(kvm
, sp
, invalid_list
);
2355 kvm_mmu_page_unlink_children(kvm
, sp
);
2356 kvm_mmu_unlink_parents(kvm
, sp
);
2358 if (!sp
->role
.invalid
&& !sp
->role
.direct
)
2359 unaccount_shadowed(kvm
, sp
);
2362 kvm_unlink_unsync_page(kvm
, sp
);
2363 if (!sp
->root_count
) {
2366 list_move(&sp
->link
, invalid_list
);
2367 kvm_mod_used_mmu_pages(kvm
, -1);
2369 list_move(&sp
->link
, &kvm
->arch
.active_mmu_pages
);
2372 * The obsolete pages can not be used on any vcpus.
2373 * See the comments in kvm_mmu_invalidate_zap_all_pages().
2375 if (!sp
->role
.invalid
&& !is_obsolete_sp(kvm
, sp
))
2376 kvm_reload_remote_mmus(kvm
);
2379 sp
->role
.invalid
= 1;
2383 static void kvm_mmu_commit_zap_page(struct kvm
*kvm
,
2384 struct list_head
*invalid_list
)
2386 struct kvm_mmu_page
*sp
, *nsp
;
2388 if (list_empty(invalid_list
))
2392 * We need to make sure everyone sees our modifications to
2393 * the page tables and see changes to vcpu->mode here. The barrier
2394 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2395 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2397 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2398 * guest mode and/or lockless shadow page table walks.
2400 kvm_flush_remote_tlbs(kvm
);
2402 list_for_each_entry_safe(sp
, nsp
, invalid_list
, link
) {
2403 WARN_ON(!sp
->role
.invalid
|| sp
->root_count
);
2404 kvm_mmu_free_page(sp
);
2408 static bool prepare_zap_oldest_mmu_page(struct kvm
*kvm
,
2409 struct list_head
*invalid_list
)
2411 struct kvm_mmu_page
*sp
;
2413 if (list_empty(&kvm
->arch
.active_mmu_pages
))
2416 sp
= list_last_entry(&kvm
->arch
.active_mmu_pages
,
2417 struct kvm_mmu_page
, link
);
2418 kvm_mmu_prepare_zap_page(kvm
, sp
, invalid_list
);
2424 * Changing the number of mmu pages allocated to the vm
2425 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2427 void kvm_mmu_change_mmu_pages(struct kvm
*kvm
, unsigned int goal_nr_mmu_pages
)
2429 LIST_HEAD(invalid_list
);
2431 spin_lock(&kvm
->mmu_lock
);
2433 if (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
) {
2434 /* Need to free some mmu pages to achieve the goal. */
2435 while (kvm
->arch
.n_used_mmu_pages
> goal_nr_mmu_pages
)
2436 if (!prepare_zap_oldest_mmu_page(kvm
, &invalid_list
))
2439 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2440 goal_nr_mmu_pages
= kvm
->arch
.n_used_mmu_pages
;
2443 kvm
->arch
.n_max_mmu_pages
= goal_nr_mmu_pages
;
2445 spin_unlock(&kvm
->mmu_lock
);
2448 int kvm_mmu_unprotect_page(struct kvm
*kvm
, gfn_t gfn
)
2450 struct kvm_mmu_page
*sp
;
2451 LIST_HEAD(invalid_list
);
2454 pgprintk("%s: looking for gfn %llx\n", __func__
, gfn
);
2456 spin_lock(&kvm
->mmu_lock
);
2457 for_each_gfn_indirect_valid_sp(kvm
, sp
, gfn
) {
2458 pgprintk("%s: gfn %llx role %x\n", __func__
, gfn
,
2461 kvm_mmu_prepare_zap_page(kvm
, sp
, &invalid_list
);
2463 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
2464 spin_unlock(&kvm
->mmu_lock
);
2468 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page
);
2470 static void kvm_unsync_page(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
)
2472 trace_kvm_mmu_unsync_page(sp
);
2473 ++vcpu
->kvm
->stat
.mmu_unsync
;
2476 kvm_mmu_mark_parents_unsync(sp
);
2479 static bool mmu_need_write_protect(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2482 struct kvm_mmu_page
*sp
;
2484 if (kvm_page_track_is_active(vcpu
, gfn
, KVM_PAGE_TRACK_WRITE
))
2487 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
) {
2494 WARN_ON(sp
->role
.level
!= PT_PAGE_TABLE_LEVEL
);
2495 kvm_unsync_page(vcpu
, sp
);
2501 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn
)
2504 return !is_zero_pfn(pfn
) && PageReserved(pfn_to_page(pfn
));
2509 static int set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
,
2510 unsigned pte_access
, int level
,
2511 gfn_t gfn
, kvm_pfn_t pfn
, bool speculative
,
2512 bool can_unsync
, bool host_writable
)
2517 if (set_mmio_spte(vcpu
, sptep
, gfn
, pfn
, pte_access
))
2520 spte
= PT_PRESENT_MASK
;
2522 spte
|= shadow_accessed_mask
;
2524 if (pte_access
& ACC_EXEC_MASK
)
2525 spte
|= shadow_x_mask
;
2527 spte
|= shadow_nx_mask
;
2529 if (pte_access
& ACC_USER_MASK
)
2530 spte
|= shadow_user_mask
;
2532 if (level
> PT_PAGE_TABLE_LEVEL
)
2533 spte
|= PT_PAGE_SIZE_MASK
;
2535 spte
|= kvm_x86_ops
->get_mt_mask(vcpu
, gfn
,
2536 kvm_is_mmio_pfn(pfn
));
2539 spte
|= SPTE_HOST_WRITEABLE
;
2541 pte_access
&= ~ACC_WRITE_MASK
;
2543 spte
|= (u64
)pfn
<< PAGE_SHIFT
;
2545 if (pte_access
& ACC_WRITE_MASK
) {
2548 * Other vcpu creates new sp in the window between
2549 * mapping_level() and acquiring mmu-lock. We can
2550 * allow guest to retry the access, the mapping can
2551 * be fixed if guest refault.
2553 if (level
> PT_PAGE_TABLE_LEVEL
&&
2554 mmu_gfn_lpage_is_disallowed(vcpu
, gfn
, level
))
2557 spte
|= PT_WRITABLE_MASK
| SPTE_MMU_WRITEABLE
;
2560 * Optimization: for pte sync, if spte was writable the hash
2561 * lookup is unnecessary (and expensive). Write protection
2562 * is responsibility of mmu_get_page / kvm_sync_page.
2563 * Same reasoning can be applied to dirty page accounting.
2565 if (!can_unsync
&& is_writable_pte(*sptep
))
2568 if (mmu_need_write_protect(vcpu
, gfn
, can_unsync
)) {
2569 pgprintk("%s: found shadow page for %llx, marking ro\n",
2572 pte_access
&= ~ACC_WRITE_MASK
;
2573 spte
&= ~(PT_WRITABLE_MASK
| SPTE_MMU_WRITEABLE
);
2577 if (pte_access
& ACC_WRITE_MASK
) {
2578 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
2579 spte
|= shadow_dirty_mask
;
2583 if (mmu_spte_update(sptep
, spte
))
2584 kvm_flush_remote_tlbs(vcpu
->kvm
);
2589 static bool mmu_set_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, unsigned pte_access
,
2590 int write_fault
, int level
, gfn_t gfn
, kvm_pfn_t pfn
,
2591 bool speculative
, bool host_writable
)
2593 int was_rmapped
= 0;
2595 bool emulate
= false;
2597 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__
,
2598 *sptep
, write_fault
, gfn
);
2600 if (is_shadow_present_pte(*sptep
)) {
2602 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2603 * the parent of the now unreachable PTE.
2605 if (level
> PT_PAGE_TABLE_LEVEL
&&
2606 !is_large_pte(*sptep
)) {
2607 struct kvm_mmu_page
*child
;
2610 child
= page_header(pte
& PT64_BASE_ADDR_MASK
);
2611 drop_parent_pte(child
, sptep
);
2612 kvm_flush_remote_tlbs(vcpu
->kvm
);
2613 } else if (pfn
!= spte_to_pfn(*sptep
)) {
2614 pgprintk("hfn old %llx new %llx\n",
2615 spte_to_pfn(*sptep
), pfn
);
2616 drop_spte(vcpu
->kvm
, sptep
);
2617 kvm_flush_remote_tlbs(vcpu
->kvm
);
2622 if (set_spte(vcpu
, sptep
, pte_access
, level
, gfn
, pfn
, speculative
,
2623 true, host_writable
)) {
2626 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2629 if (unlikely(is_mmio_spte(*sptep
)))
2632 pgprintk("%s: setting spte %llx\n", __func__
, *sptep
);
2633 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2634 is_large_pte(*sptep
)? "2MB" : "4kB",
2635 *sptep
& PT_PRESENT_MASK
?"RW":"R", gfn
,
2637 if (!was_rmapped
&& is_large_pte(*sptep
))
2638 ++vcpu
->kvm
->stat
.lpages
;
2640 if (is_shadow_present_pte(*sptep
)) {
2642 rmap_count
= rmap_add(vcpu
, sptep
, gfn
);
2643 if (rmap_count
> RMAP_RECYCLE_THRESHOLD
)
2644 rmap_recycle(vcpu
, sptep
, gfn
);
2648 kvm_release_pfn_clean(pfn
);
2653 static kvm_pfn_t
pte_prefetch_gfn_to_pfn(struct kvm_vcpu
*vcpu
, gfn_t gfn
,
2656 struct kvm_memory_slot
*slot
;
2658 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, no_dirty_log
);
2660 return KVM_PFN_ERR_FAULT
;
2662 return gfn_to_pfn_memslot_atomic(slot
, gfn
);
2665 static int direct_pte_prefetch_many(struct kvm_vcpu
*vcpu
,
2666 struct kvm_mmu_page
*sp
,
2667 u64
*start
, u64
*end
)
2669 struct page
*pages
[PTE_PREFETCH_NUM
];
2670 struct kvm_memory_slot
*slot
;
2671 unsigned access
= sp
->role
.access
;
2675 gfn
= kvm_mmu_page_get_gfn(sp
, start
- sp
->spt
);
2676 slot
= gfn_to_memslot_dirty_bitmap(vcpu
, gfn
, access
& ACC_WRITE_MASK
);
2680 ret
= gfn_to_page_many_atomic(slot
, gfn
, pages
, end
- start
);
2684 for (i
= 0; i
< ret
; i
++, gfn
++, start
++)
2685 mmu_set_spte(vcpu
, start
, access
, 0, sp
->role
.level
, gfn
,
2686 page_to_pfn(pages
[i
]), true, true);
2691 static void __direct_pte_prefetch(struct kvm_vcpu
*vcpu
,
2692 struct kvm_mmu_page
*sp
, u64
*sptep
)
2694 u64
*spte
, *start
= NULL
;
2697 WARN_ON(!sp
->role
.direct
);
2699 i
= (sptep
- sp
->spt
) & ~(PTE_PREFETCH_NUM
- 1);
2702 for (i
= 0; i
< PTE_PREFETCH_NUM
; i
++, spte
++) {
2703 if (is_shadow_present_pte(*spte
) || spte
== sptep
) {
2706 if (direct_pte_prefetch_many(vcpu
, sp
, start
, spte
) < 0)
2714 static void direct_pte_prefetch(struct kvm_vcpu
*vcpu
, u64
*sptep
)
2716 struct kvm_mmu_page
*sp
;
2719 * Since it's no accessed bit on EPT, it's no way to
2720 * distinguish between actually accessed translations
2721 * and prefetched, so disable pte prefetch if EPT is
2724 if (!shadow_accessed_mask
)
2727 sp
= page_header(__pa(sptep
));
2728 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
2731 __direct_pte_prefetch(vcpu
, sp
, sptep
);
2734 static int __direct_map(struct kvm_vcpu
*vcpu
, int write
, int map_writable
,
2735 int level
, gfn_t gfn
, kvm_pfn_t pfn
, bool prefault
)
2737 struct kvm_shadow_walk_iterator iterator
;
2738 struct kvm_mmu_page
*sp
;
2742 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
2745 for_each_shadow_entry(vcpu
, (u64
)gfn
<< PAGE_SHIFT
, iterator
) {
2746 if (iterator
.level
== level
) {
2747 emulate
= mmu_set_spte(vcpu
, iterator
.sptep
, ACC_ALL
,
2748 write
, level
, gfn
, pfn
, prefault
,
2750 direct_pte_prefetch(vcpu
, iterator
.sptep
);
2751 ++vcpu
->stat
.pf_fixed
;
2755 drop_large_spte(vcpu
, iterator
.sptep
);
2756 if (!is_shadow_present_pte(*iterator
.sptep
)) {
2757 u64 base_addr
= iterator
.addr
;
2759 base_addr
&= PT64_LVL_ADDR_MASK(iterator
.level
);
2760 pseudo_gfn
= base_addr
>> PAGE_SHIFT
;
2761 sp
= kvm_mmu_get_page(vcpu
, pseudo_gfn
, iterator
.addr
,
2762 iterator
.level
- 1, 1, ACC_ALL
);
2764 link_shadow_page(vcpu
, iterator
.sptep
, sp
);
2770 static void kvm_send_hwpoison_signal(unsigned long address
, struct task_struct
*tsk
)
2774 info
.si_signo
= SIGBUS
;
2776 info
.si_code
= BUS_MCEERR_AR
;
2777 info
.si_addr
= (void __user
*)address
;
2778 info
.si_addr_lsb
= PAGE_SHIFT
;
2780 send_sig_info(SIGBUS
, &info
, tsk
);
2783 static int kvm_handle_bad_page(struct kvm_vcpu
*vcpu
, gfn_t gfn
, kvm_pfn_t pfn
)
2786 * Do not cache the mmio info caused by writing the readonly gfn
2787 * into the spte otherwise read access on readonly gfn also can
2788 * caused mmio page fault and treat it as mmio access.
2789 * Return 1 to tell kvm to emulate it.
2791 if (pfn
== KVM_PFN_ERR_RO_FAULT
)
2794 if (pfn
== KVM_PFN_ERR_HWPOISON
) {
2795 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu
, gfn
), current
);
2802 static void transparent_hugepage_adjust(struct kvm_vcpu
*vcpu
,
2803 gfn_t
*gfnp
, kvm_pfn_t
*pfnp
,
2806 kvm_pfn_t pfn
= *pfnp
;
2808 int level
= *levelp
;
2811 * Check if it's a transparent hugepage. If this would be an
2812 * hugetlbfs page, level wouldn't be set to
2813 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2816 if (!is_error_noslot_pfn(pfn
) && !kvm_is_reserved_pfn(pfn
) &&
2817 level
== PT_PAGE_TABLE_LEVEL
&&
2818 PageTransCompound(pfn_to_page(pfn
)) &&
2819 !mmu_gfn_lpage_is_disallowed(vcpu
, gfn
, PT_DIRECTORY_LEVEL
)) {
2822 * mmu_notifier_retry was successful and we hold the
2823 * mmu_lock here, so the pmd can't become splitting
2824 * from under us, and in turn
2825 * __split_huge_page_refcount() can't run from under
2826 * us and we can safely transfer the refcount from
2827 * PG_tail to PG_head as we switch the pfn to tail to
2830 *levelp
= level
= PT_DIRECTORY_LEVEL
;
2831 mask
= KVM_PAGES_PER_HPAGE(level
) - 1;
2832 VM_BUG_ON((gfn
& mask
) != (pfn
& mask
));
2836 kvm_release_pfn_clean(pfn
);
2844 static bool handle_abnormal_pfn(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
,
2845 kvm_pfn_t pfn
, unsigned access
, int *ret_val
)
2847 /* The pfn is invalid, report the error! */
2848 if (unlikely(is_error_pfn(pfn
))) {
2849 *ret_val
= kvm_handle_bad_page(vcpu
, gfn
, pfn
);
2853 if (unlikely(is_noslot_pfn(pfn
)))
2854 vcpu_cache_mmio_info(vcpu
, gva
, gfn
, access
);
2859 static bool page_fault_can_be_fast(u32 error_code
)
2862 * Do not fix the mmio spte with invalid generation number which
2863 * need to be updated by slow page fault path.
2865 if (unlikely(error_code
& PFERR_RSVD_MASK
))
2869 * #PF can be fast only if the shadow page table is present and it
2870 * is caused by write-protect, that means we just need change the
2871 * W bit of the spte which can be done out of mmu-lock.
2873 if (!(error_code
& PFERR_PRESENT_MASK
) ||
2874 !(error_code
& PFERR_WRITE_MASK
))
2881 fast_pf_fix_direct_spte(struct kvm_vcpu
*vcpu
, struct kvm_mmu_page
*sp
,
2882 u64
*sptep
, u64 spte
)
2886 WARN_ON(!sp
->role
.direct
);
2889 * The gfn of direct spte is stable since it is calculated
2892 gfn
= kvm_mmu_page_get_gfn(sp
, sptep
- sp
->spt
);
2895 * Theoretically we could also set dirty bit (and flush TLB) here in
2896 * order to eliminate unnecessary PML logging. See comments in
2897 * set_spte. But fast_page_fault is very unlikely to happen with PML
2898 * enabled, so we do not do this. This might result in the same GPA
2899 * to be logged in PML buffer again when the write really happens, and
2900 * eventually to be called by mark_page_dirty twice. But it's also no
2901 * harm. This also avoids the TLB flush needed after setting dirty bit
2902 * so non-PML cases won't be impacted.
2904 * Compare with set_spte where instead shadow_dirty_mask is set.
2906 if (cmpxchg64(sptep
, spte
, spte
| PT_WRITABLE_MASK
) == spte
)
2907 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
2914 * - true: let the vcpu to access on the same address again.
2915 * - false: let the real page fault path to fix it.
2917 static bool fast_page_fault(struct kvm_vcpu
*vcpu
, gva_t gva
, int level
,
2920 struct kvm_shadow_walk_iterator iterator
;
2921 struct kvm_mmu_page
*sp
;
2925 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
2928 if (!page_fault_can_be_fast(error_code
))
2931 walk_shadow_page_lockless_begin(vcpu
);
2932 for_each_shadow_entry_lockless(vcpu
, gva
, iterator
, spte
)
2933 if (!is_shadow_present_pte(spte
) || iterator
.level
< level
)
2937 * If the mapping has been changed, let the vcpu fault on the
2938 * same address again.
2940 if (!is_shadow_present_pte(spte
)) {
2945 sp
= page_header(__pa(iterator
.sptep
));
2946 if (!is_last_spte(spte
, sp
->role
.level
))
2950 * Check if it is a spurious fault caused by TLB lazily flushed.
2952 * Need not check the access of upper level table entries since
2953 * they are always ACC_ALL.
2955 if (is_writable_pte(spte
)) {
2961 * Currently, to simplify the code, only the spte write-protected
2962 * by dirty-log can be fast fixed.
2964 if (!spte_is_locklessly_modifiable(spte
))
2968 * Do not fix write-permission on the large spte since we only dirty
2969 * the first page into the dirty-bitmap in fast_pf_fix_direct_spte()
2970 * that means other pages are missed if its slot is dirty-logged.
2972 * Instead, we let the slow page fault path create a normal spte to
2975 * See the comments in kvm_arch_commit_memory_region().
2977 if (sp
->role
.level
> PT_PAGE_TABLE_LEVEL
)
2981 * Currently, fast page fault only works for direct mapping since
2982 * the gfn is not stable for indirect shadow page.
2983 * See Documentation/virtual/kvm/locking.txt to get more detail.
2985 ret
= fast_pf_fix_direct_spte(vcpu
, sp
, iterator
.sptep
, spte
);
2987 trace_fast_page_fault(vcpu
, gva
, error_code
, iterator
.sptep
,
2989 walk_shadow_page_lockless_end(vcpu
);
2994 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
2995 gva_t gva
, kvm_pfn_t
*pfn
, bool write
, bool *writable
);
2996 static void make_mmu_pages_available(struct kvm_vcpu
*vcpu
);
2998 static int nonpaging_map(struct kvm_vcpu
*vcpu
, gva_t v
, u32 error_code
,
2999 gfn_t gfn
, bool prefault
)
3003 bool force_pt_level
= false;
3005 unsigned long mmu_seq
;
3006 bool map_writable
, write
= error_code
& PFERR_WRITE_MASK
;
3008 level
= mapping_level(vcpu
, gfn
, &force_pt_level
);
3009 if (likely(!force_pt_level
)) {
3011 * This path builds a PAE pagetable - so we can map
3012 * 2mb pages at maximum. Therefore check if the level
3013 * is larger than that.
3015 if (level
> PT_DIRECTORY_LEVEL
)
3016 level
= PT_DIRECTORY_LEVEL
;
3018 gfn
&= ~(KVM_PAGES_PER_HPAGE(level
) - 1);
3021 if (fast_page_fault(vcpu
, v
, level
, error_code
))
3024 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
3027 if (try_async_pf(vcpu
, prefault
, gfn
, v
, &pfn
, write
, &map_writable
))
3030 if (handle_abnormal_pfn(vcpu
, v
, gfn
, pfn
, ACC_ALL
, &r
))
3033 spin_lock(&vcpu
->kvm
->mmu_lock
);
3034 if (mmu_notifier_retry(vcpu
->kvm
, mmu_seq
))
3036 make_mmu_pages_available(vcpu
);
3037 if (likely(!force_pt_level
))
3038 transparent_hugepage_adjust(vcpu
, &gfn
, &pfn
, &level
);
3039 r
= __direct_map(vcpu
, write
, map_writable
, level
, gfn
, pfn
, prefault
);
3040 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3045 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3046 kvm_release_pfn_clean(pfn
);
3051 static void mmu_free_roots(struct kvm_vcpu
*vcpu
)
3054 struct kvm_mmu_page
*sp
;
3055 LIST_HEAD(invalid_list
);
3057 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3060 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
&&
3061 (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
||
3062 vcpu
->arch
.mmu
.direct_map
)) {
3063 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
3065 spin_lock(&vcpu
->kvm
->mmu_lock
);
3066 sp
= page_header(root
);
3068 if (!sp
->root_count
&& sp
->role
.invalid
) {
3069 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
3070 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
3072 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3073 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
3077 spin_lock(&vcpu
->kvm
->mmu_lock
);
3078 for (i
= 0; i
< 4; ++i
) {
3079 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3082 root
&= PT64_BASE_ADDR_MASK
;
3083 sp
= page_header(root
);
3085 if (!sp
->root_count
&& sp
->role
.invalid
)
3086 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
,
3089 vcpu
->arch
.mmu
.pae_root
[i
] = INVALID_PAGE
;
3091 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
3092 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3093 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
3096 static int mmu_check_root(struct kvm_vcpu
*vcpu
, gfn_t root_gfn
)
3100 if (!kvm_is_visible_gfn(vcpu
->kvm
, root_gfn
)) {
3101 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
3108 static int mmu_alloc_direct_roots(struct kvm_vcpu
*vcpu
)
3110 struct kvm_mmu_page
*sp
;
3113 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
) {
3114 spin_lock(&vcpu
->kvm
->mmu_lock
);
3115 make_mmu_pages_available(vcpu
);
3116 sp
= kvm_mmu_get_page(vcpu
, 0, 0, PT64_ROOT_LEVEL
, 1, ACC_ALL
);
3118 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3119 vcpu
->arch
.mmu
.root_hpa
= __pa(sp
->spt
);
3120 } else if (vcpu
->arch
.mmu
.shadow_root_level
== PT32E_ROOT_LEVEL
) {
3121 for (i
= 0; i
< 4; ++i
) {
3122 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3124 MMU_WARN_ON(VALID_PAGE(root
));
3125 spin_lock(&vcpu
->kvm
->mmu_lock
);
3126 make_mmu_pages_available(vcpu
);
3127 sp
= kvm_mmu_get_page(vcpu
, i
<< (30 - PAGE_SHIFT
),
3128 i
<< 30, PT32_ROOT_LEVEL
, 1, ACC_ALL
);
3129 root
= __pa(sp
->spt
);
3131 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3132 vcpu
->arch
.mmu
.pae_root
[i
] = root
| PT_PRESENT_MASK
;
3134 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.pae_root
);
3141 static int mmu_alloc_shadow_roots(struct kvm_vcpu
*vcpu
)
3143 struct kvm_mmu_page
*sp
;
3148 root_gfn
= vcpu
->arch
.mmu
.get_cr3(vcpu
) >> PAGE_SHIFT
;
3150 if (mmu_check_root(vcpu
, root_gfn
))
3154 * Do we shadow a long mode page table? If so we need to
3155 * write-protect the guests page table root.
3157 if (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
) {
3158 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
3160 MMU_WARN_ON(VALID_PAGE(root
));
3162 spin_lock(&vcpu
->kvm
->mmu_lock
);
3163 make_mmu_pages_available(vcpu
);
3164 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, 0, PT64_ROOT_LEVEL
,
3166 root
= __pa(sp
->spt
);
3168 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3169 vcpu
->arch
.mmu
.root_hpa
= root
;
3174 * We shadow a 32 bit page table. This may be a legacy 2-level
3175 * or a PAE 3-level page table. In either case we need to be aware that
3176 * the shadow page table may be a PAE or a long mode page table.
3178 pm_mask
= PT_PRESENT_MASK
;
3179 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
)
3180 pm_mask
|= PT_ACCESSED_MASK
| PT_WRITABLE_MASK
| PT_USER_MASK
;
3182 for (i
= 0; i
< 4; ++i
) {
3183 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3185 MMU_WARN_ON(VALID_PAGE(root
));
3186 if (vcpu
->arch
.mmu
.root_level
== PT32E_ROOT_LEVEL
) {
3187 pdptr
= vcpu
->arch
.mmu
.get_pdptr(vcpu
, i
);
3188 if (!is_present_gpte(pdptr
)) {
3189 vcpu
->arch
.mmu
.pae_root
[i
] = 0;
3192 root_gfn
= pdptr
>> PAGE_SHIFT
;
3193 if (mmu_check_root(vcpu
, root_gfn
))
3196 spin_lock(&vcpu
->kvm
->mmu_lock
);
3197 make_mmu_pages_available(vcpu
);
3198 sp
= kvm_mmu_get_page(vcpu
, root_gfn
, i
<< 30, PT32_ROOT_LEVEL
,
3200 root
= __pa(sp
->spt
);
3202 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3204 vcpu
->arch
.mmu
.pae_root
[i
] = root
| pm_mask
;
3206 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.pae_root
);
3209 * If we shadow a 32 bit page table with a long mode page
3210 * table we enter this path.
3212 if (vcpu
->arch
.mmu
.shadow_root_level
== PT64_ROOT_LEVEL
) {
3213 if (vcpu
->arch
.mmu
.lm_root
== NULL
) {
3215 * The additional page necessary for this is only
3216 * allocated on demand.
3221 lm_root
= (void*)get_zeroed_page(GFP_KERNEL
);
3222 if (lm_root
== NULL
)
3225 lm_root
[0] = __pa(vcpu
->arch
.mmu
.pae_root
) | pm_mask
;
3227 vcpu
->arch
.mmu
.lm_root
= lm_root
;
3230 vcpu
->arch
.mmu
.root_hpa
= __pa(vcpu
->arch
.mmu
.lm_root
);
3236 static int mmu_alloc_roots(struct kvm_vcpu
*vcpu
)
3238 if (vcpu
->arch
.mmu
.direct_map
)
3239 return mmu_alloc_direct_roots(vcpu
);
3241 return mmu_alloc_shadow_roots(vcpu
);
3244 static void mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3247 struct kvm_mmu_page
*sp
;
3249 if (vcpu
->arch
.mmu
.direct_map
)
3252 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3255 vcpu_clear_mmio_info(vcpu
, MMIO_GVA_ANY
);
3256 kvm_mmu_audit(vcpu
, AUDIT_PRE_SYNC
);
3257 if (vcpu
->arch
.mmu
.root_level
== PT64_ROOT_LEVEL
) {
3258 hpa_t root
= vcpu
->arch
.mmu
.root_hpa
;
3259 sp
= page_header(root
);
3260 mmu_sync_children(vcpu
, sp
);
3261 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3264 for (i
= 0; i
< 4; ++i
) {
3265 hpa_t root
= vcpu
->arch
.mmu
.pae_root
[i
];
3267 if (root
&& VALID_PAGE(root
)) {
3268 root
&= PT64_BASE_ADDR_MASK
;
3269 sp
= page_header(root
);
3270 mmu_sync_children(vcpu
, sp
);
3273 kvm_mmu_audit(vcpu
, AUDIT_POST_SYNC
);
3276 void kvm_mmu_sync_roots(struct kvm_vcpu
*vcpu
)
3278 spin_lock(&vcpu
->kvm
->mmu_lock
);
3279 mmu_sync_roots(vcpu
);
3280 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3282 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots
);
3284 static gpa_t
nonpaging_gva_to_gpa(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
3285 u32 access
, struct x86_exception
*exception
)
3288 exception
->error_code
= 0;
3292 static gpa_t
nonpaging_gva_to_gpa_nested(struct kvm_vcpu
*vcpu
, gva_t vaddr
,
3294 struct x86_exception
*exception
)
3297 exception
->error_code
= 0;
3298 return vcpu
->arch
.nested_mmu
.translate_gpa(vcpu
, vaddr
, access
, exception
);
3302 __is_rsvd_bits_set(struct rsvd_bits_validate
*rsvd_check
, u64 pte
, int level
)
3304 int bit7
= (pte
>> 7) & 1, low6
= pte
& 0x3f;
3306 return (pte
& rsvd_check
->rsvd_bits_mask
[bit7
][level
-1]) |
3307 ((rsvd_check
->bad_mt_xwr
& (1ull << low6
)) != 0);
3310 static bool is_rsvd_bits_set(struct kvm_mmu
*mmu
, u64 gpte
, int level
)
3312 return __is_rsvd_bits_set(&mmu
->guest_rsvd_check
, gpte
, level
);
3315 static bool is_shadow_zero_bits_set(struct kvm_mmu
*mmu
, u64 spte
, int level
)
3317 return __is_rsvd_bits_set(&mmu
->shadow_zero_check
, spte
, level
);
3320 static bool mmio_info_in_cache(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3323 return vcpu_match_mmio_gpa(vcpu
, addr
);
3325 return vcpu_match_mmio_gva(vcpu
, addr
);
3328 /* return true if reserved bit is detected on spte. */
3330 walk_shadow_page_get_mmio_spte(struct kvm_vcpu
*vcpu
, u64 addr
, u64
*sptep
)
3332 struct kvm_shadow_walk_iterator iterator
;
3333 u64 sptes
[PT64_ROOT_LEVEL
], spte
= 0ull;
3335 bool reserved
= false;
3337 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3340 walk_shadow_page_lockless_begin(vcpu
);
3342 for (shadow_walk_init(&iterator
, vcpu
, addr
),
3343 leaf
= root
= iterator
.level
;
3344 shadow_walk_okay(&iterator
);
3345 __shadow_walk_next(&iterator
, spte
)) {
3346 spte
= mmu_spte_get_lockless(iterator
.sptep
);
3348 sptes
[leaf
- 1] = spte
;
3351 if (!is_shadow_present_pte(spte
))
3354 reserved
|= is_shadow_zero_bits_set(&vcpu
->arch
.mmu
, spte
,
3358 walk_shadow_page_lockless_end(vcpu
);
3361 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3363 while (root
> leaf
) {
3364 pr_err("------ spte 0x%llx level %d.\n",
3365 sptes
[root
- 1], root
);
3374 int handle_mmio_page_fault(struct kvm_vcpu
*vcpu
, u64 addr
, bool direct
)
3379 if (mmio_info_in_cache(vcpu
, addr
, direct
))
3380 return RET_MMIO_PF_EMULATE
;
3382 reserved
= walk_shadow_page_get_mmio_spte(vcpu
, addr
, &spte
);
3383 if (WARN_ON(reserved
))
3384 return RET_MMIO_PF_BUG
;
3386 if (is_mmio_spte(spte
)) {
3387 gfn_t gfn
= get_mmio_spte_gfn(spte
);
3388 unsigned access
= get_mmio_spte_access(spte
);
3390 if (!check_mmio_spte(vcpu
, spte
))
3391 return RET_MMIO_PF_INVALID
;
3396 trace_handle_mmio_page_fault(addr
, gfn
, access
);
3397 vcpu_cache_mmio_info(vcpu
, addr
, gfn
, access
);
3398 return RET_MMIO_PF_EMULATE
;
3402 * If the page table is zapped by other cpus, let CPU fault again on
3405 return RET_MMIO_PF_RETRY
;
3407 EXPORT_SYMBOL_GPL(handle_mmio_page_fault
);
3409 static bool page_fault_handle_page_track(struct kvm_vcpu
*vcpu
,
3410 u32 error_code
, gfn_t gfn
)
3412 if (unlikely(error_code
& PFERR_RSVD_MASK
))
3415 if (!(error_code
& PFERR_PRESENT_MASK
) ||
3416 !(error_code
& PFERR_WRITE_MASK
))
3420 * guest is writing the page which is write tracked which can
3421 * not be fixed by page fault handler.
3423 if (kvm_page_track_is_active(vcpu
, gfn
, KVM_PAGE_TRACK_WRITE
))
3429 static void shadow_page_table_clear_flood(struct kvm_vcpu
*vcpu
, gva_t addr
)
3431 struct kvm_shadow_walk_iterator iterator
;
3434 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3437 walk_shadow_page_lockless_begin(vcpu
);
3438 for_each_shadow_entry_lockless(vcpu
, addr
, iterator
, spte
) {
3439 clear_sp_write_flooding_count(iterator
.sptep
);
3440 if (!is_shadow_present_pte(spte
))
3443 walk_shadow_page_lockless_end(vcpu
);
3446 static int nonpaging_page_fault(struct kvm_vcpu
*vcpu
, gva_t gva
,
3447 u32 error_code
, bool prefault
)
3449 gfn_t gfn
= gva
>> PAGE_SHIFT
;
3452 pgprintk("%s: gva %lx error %x\n", __func__
, gva
, error_code
);
3454 if (page_fault_handle_page_track(vcpu
, error_code
, gfn
))
3457 r
= mmu_topup_memory_caches(vcpu
);
3461 MMU_WARN_ON(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3464 return nonpaging_map(vcpu
, gva
& PAGE_MASK
,
3465 error_code
, gfn
, prefault
);
3468 static int kvm_arch_setup_async_pf(struct kvm_vcpu
*vcpu
, gva_t gva
, gfn_t gfn
)
3470 struct kvm_arch_async_pf arch
;
3472 arch
.token
= (vcpu
->arch
.apf
.id
++ << 12) | vcpu
->vcpu_id
;
3474 arch
.direct_map
= vcpu
->arch
.mmu
.direct_map
;
3475 arch
.cr3
= vcpu
->arch
.mmu
.get_cr3(vcpu
);
3477 return kvm_setup_async_pf(vcpu
, gva
, kvm_vcpu_gfn_to_hva(vcpu
, gfn
), &arch
);
3480 static bool can_do_async_pf(struct kvm_vcpu
*vcpu
)
3482 if (unlikely(!lapic_in_kernel(vcpu
) ||
3483 kvm_event_needs_reinjection(vcpu
)))
3486 return kvm_x86_ops
->interrupt_allowed(vcpu
);
3489 static bool try_async_pf(struct kvm_vcpu
*vcpu
, bool prefault
, gfn_t gfn
,
3490 gva_t gva
, kvm_pfn_t
*pfn
, bool write
, bool *writable
)
3492 struct kvm_memory_slot
*slot
;
3495 slot
= kvm_vcpu_gfn_to_memslot(vcpu
, gfn
);
3497 *pfn
= __gfn_to_pfn_memslot(slot
, gfn
, false, &async
, write
, writable
);
3499 return false; /* *pfn has correct page already */
3501 if (!prefault
&& can_do_async_pf(vcpu
)) {
3502 trace_kvm_try_async_get_page(gva
, gfn
);
3503 if (kvm_find_async_pf_gfn(vcpu
, gfn
)) {
3504 trace_kvm_async_pf_doublefault(gva
, gfn
);
3505 kvm_make_request(KVM_REQ_APF_HALT
, vcpu
);
3507 } else if (kvm_arch_setup_async_pf(vcpu
, gva
, gfn
))
3511 *pfn
= __gfn_to_pfn_memslot(slot
, gfn
, false, NULL
, write
, writable
);
3516 check_hugepage_cache_consistency(struct kvm_vcpu
*vcpu
, gfn_t gfn
, int level
)
3518 int page_num
= KVM_PAGES_PER_HPAGE(level
);
3520 gfn
&= ~(page_num
- 1);
3522 return kvm_mtrr_check_gfn_range_consistency(vcpu
, gfn
, page_num
);
3525 static int tdp_page_fault(struct kvm_vcpu
*vcpu
, gva_t gpa
, u32 error_code
,
3531 bool force_pt_level
;
3532 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
3533 unsigned long mmu_seq
;
3534 int write
= error_code
& PFERR_WRITE_MASK
;
3537 MMU_WARN_ON(!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
3539 if (page_fault_handle_page_track(vcpu
, error_code
, gfn
))
3542 r
= mmu_topup_memory_caches(vcpu
);
3546 force_pt_level
= !check_hugepage_cache_consistency(vcpu
, gfn
,
3547 PT_DIRECTORY_LEVEL
);
3548 level
= mapping_level(vcpu
, gfn
, &force_pt_level
);
3549 if (likely(!force_pt_level
)) {
3550 if (level
> PT_DIRECTORY_LEVEL
&&
3551 !check_hugepage_cache_consistency(vcpu
, gfn
, level
))
3552 level
= PT_DIRECTORY_LEVEL
;
3553 gfn
&= ~(KVM_PAGES_PER_HPAGE(level
) - 1);
3556 if (fast_page_fault(vcpu
, gpa
, level
, error_code
))
3559 mmu_seq
= vcpu
->kvm
->mmu_notifier_seq
;
3562 if (try_async_pf(vcpu
, prefault
, gfn
, gpa
, &pfn
, write
, &map_writable
))
3565 if (handle_abnormal_pfn(vcpu
, 0, gfn
, pfn
, ACC_ALL
, &r
))
3568 spin_lock(&vcpu
->kvm
->mmu_lock
);
3569 if (mmu_notifier_retry(vcpu
->kvm
, mmu_seq
))
3571 make_mmu_pages_available(vcpu
);
3572 if (likely(!force_pt_level
))
3573 transparent_hugepage_adjust(vcpu
, &gfn
, &pfn
, &level
);
3574 r
= __direct_map(vcpu
, write
, map_writable
, level
, gfn
, pfn
, prefault
);
3575 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3580 spin_unlock(&vcpu
->kvm
->mmu_lock
);
3581 kvm_release_pfn_clean(pfn
);
3585 static void nonpaging_init_context(struct kvm_vcpu
*vcpu
,
3586 struct kvm_mmu
*context
)
3588 context
->page_fault
= nonpaging_page_fault
;
3589 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
3590 context
->sync_page
= nonpaging_sync_page
;
3591 context
->invlpg
= nonpaging_invlpg
;
3592 context
->update_pte
= nonpaging_update_pte
;
3593 context
->root_level
= 0;
3594 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
3595 context
->root_hpa
= INVALID_PAGE
;
3596 context
->direct_map
= true;
3597 context
->nx
= false;
3600 void kvm_mmu_new_cr3(struct kvm_vcpu
*vcpu
)
3602 mmu_free_roots(vcpu
);
3605 static unsigned long get_cr3(struct kvm_vcpu
*vcpu
)
3607 return kvm_read_cr3(vcpu
);
3610 static void inject_page_fault(struct kvm_vcpu
*vcpu
,
3611 struct x86_exception
*fault
)
3613 vcpu
->arch
.mmu
.inject_page_fault(vcpu
, fault
);
3616 static bool sync_mmio_spte(struct kvm_vcpu
*vcpu
, u64
*sptep
, gfn_t gfn
,
3617 unsigned access
, int *nr_present
)
3619 if (unlikely(is_mmio_spte(*sptep
))) {
3620 if (gfn
!= get_mmio_spte_gfn(*sptep
)) {
3621 mmu_spte_clear_no_track(sptep
);
3626 mark_mmio_spte(vcpu
, sptep
, gfn
, access
);
3633 static inline bool is_last_gpte(struct kvm_mmu
*mmu
,
3634 unsigned level
, unsigned gpte
)
3637 * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set
3638 * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means
3639 * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then.
3641 gpte
|= level
- PT_PAGE_TABLE_LEVEL
- 1;
3644 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
3645 * If it is clear, there are no large pages at this level, so clear
3646 * PT_PAGE_SIZE_MASK in gpte if that is the case.
3648 gpte
&= level
- mmu
->last_nonleaf_level
;
3650 return gpte
& PT_PAGE_SIZE_MASK
;
3653 #define PTTYPE_EPT 18 /* arbitrary */
3654 #define PTTYPE PTTYPE_EPT
3655 #include "paging_tmpl.h"
3659 #include "paging_tmpl.h"
3663 #include "paging_tmpl.h"
3667 __reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
3668 struct rsvd_bits_validate
*rsvd_check
,
3669 int maxphyaddr
, int level
, bool nx
, bool gbpages
,
3672 u64 exb_bit_rsvd
= 0;
3673 u64 gbpages_bit_rsvd
= 0;
3674 u64 nonleaf_bit8_rsvd
= 0;
3676 rsvd_check
->bad_mt_xwr
= 0;
3679 exb_bit_rsvd
= rsvd_bits(63, 63);
3681 gbpages_bit_rsvd
= rsvd_bits(7, 7);
3684 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
3685 * leaf entries) on AMD CPUs only.
3688 nonleaf_bit8_rsvd
= rsvd_bits(8, 8);
3691 case PT32_ROOT_LEVEL
:
3692 /* no rsvd bits for 2 level 4K page table entries */
3693 rsvd_check
->rsvd_bits_mask
[0][1] = 0;
3694 rsvd_check
->rsvd_bits_mask
[0][0] = 0;
3695 rsvd_check
->rsvd_bits_mask
[1][0] =
3696 rsvd_check
->rsvd_bits_mask
[0][0];
3699 rsvd_check
->rsvd_bits_mask
[1][1] = 0;
3703 if (is_cpuid_PSE36())
3704 /* 36bits PSE 4MB page */
3705 rsvd_check
->rsvd_bits_mask
[1][1] = rsvd_bits(17, 21);
3707 /* 32 bits PSE 4MB page */
3708 rsvd_check
->rsvd_bits_mask
[1][1] = rsvd_bits(13, 21);
3710 case PT32E_ROOT_LEVEL
:
3711 rsvd_check
->rsvd_bits_mask
[0][2] =
3712 rsvd_bits(maxphyaddr
, 63) |
3713 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
3714 rsvd_check
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
3715 rsvd_bits(maxphyaddr
, 62); /* PDE */
3716 rsvd_check
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
3717 rsvd_bits(maxphyaddr
, 62); /* PTE */
3718 rsvd_check
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
3719 rsvd_bits(maxphyaddr
, 62) |
3720 rsvd_bits(13, 20); /* large page */
3721 rsvd_check
->rsvd_bits_mask
[1][0] =
3722 rsvd_check
->rsvd_bits_mask
[0][0];
3724 case PT64_ROOT_LEVEL
:
3725 rsvd_check
->rsvd_bits_mask
[0][3] = exb_bit_rsvd
|
3726 nonleaf_bit8_rsvd
| rsvd_bits(7, 7) |
3727 rsvd_bits(maxphyaddr
, 51);
3728 rsvd_check
->rsvd_bits_mask
[0][2] = exb_bit_rsvd
|
3729 nonleaf_bit8_rsvd
| gbpages_bit_rsvd
|
3730 rsvd_bits(maxphyaddr
, 51);
3731 rsvd_check
->rsvd_bits_mask
[0][1] = exb_bit_rsvd
|
3732 rsvd_bits(maxphyaddr
, 51);
3733 rsvd_check
->rsvd_bits_mask
[0][0] = exb_bit_rsvd
|
3734 rsvd_bits(maxphyaddr
, 51);
3735 rsvd_check
->rsvd_bits_mask
[1][3] =
3736 rsvd_check
->rsvd_bits_mask
[0][3];
3737 rsvd_check
->rsvd_bits_mask
[1][2] = exb_bit_rsvd
|
3738 gbpages_bit_rsvd
| rsvd_bits(maxphyaddr
, 51) |
3740 rsvd_check
->rsvd_bits_mask
[1][1] = exb_bit_rsvd
|
3741 rsvd_bits(maxphyaddr
, 51) |
3742 rsvd_bits(13, 20); /* large page */
3743 rsvd_check
->rsvd_bits_mask
[1][0] =
3744 rsvd_check
->rsvd_bits_mask
[0][0];
3749 static void reset_rsvds_bits_mask(struct kvm_vcpu
*vcpu
,
3750 struct kvm_mmu
*context
)
3752 __reset_rsvds_bits_mask(vcpu
, &context
->guest_rsvd_check
,
3753 cpuid_maxphyaddr(vcpu
), context
->root_level
,
3754 context
->nx
, guest_cpuid_has_gbpages(vcpu
),
3755 is_pse(vcpu
), guest_cpuid_is_amd(vcpu
));
3759 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate
*rsvd_check
,
3760 int maxphyaddr
, bool execonly
)
3764 rsvd_check
->rsvd_bits_mask
[0][3] =
3765 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 7);
3766 rsvd_check
->rsvd_bits_mask
[0][2] =
3767 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 6);
3768 rsvd_check
->rsvd_bits_mask
[0][1] =
3769 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(3, 6);
3770 rsvd_check
->rsvd_bits_mask
[0][0] = rsvd_bits(maxphyaddr
, 51);
3773 rsvd_check
->rsvd_bits_mask
[1][3] = rsvd_check
->rsvd_bits_mask
[0][3];
3774 rsvd_check
->rsvd_bits_mask
[1][2] =
3775 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(12, 29);
3776 rsvd_check
->rsvd_bits_mask
[1][1] =
3777 rsvd_bits(maxphyaddr
, 51) | rsvd_bits(12, 20);
3778 rsvd_check
->rsvd_bits_mask
[1][0] = rsvd_check
->rsvd_bits_mask
[0][0];
3780 bad_mt_xwr
= 0xFFull
<< (2 * 8); /* bits 3..5 must not be 2 */
3781 bad_mt_xwr
|= 0xFFull
<< (3 * 8); /* bits 3..5 must not be 3 */
3782 bad_mt_xwr
|= 0xFFull
<< (7 * 8); /* bits 3..5 must not be 7 */
3783 bad_mt_xwr
|= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
3784 bad_mt_xwr
|= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
3786 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
3787 bad_mt_xwr
|= REPEAT_BYTE(1ull << 4);
3789 rsvd_check
->bad_mt_xwr
= bad_mt_xwr
;
3792 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu
*vcpu
,
3793 struct kvm_mmu
*context
, bool execonly
)
3795 __reset_rsvds_bits_mask_ept(&context
->guest_rsvd_check
,
3796 cpuid_maxphyaddr(vcpu
), execonly
);
3800 * the page table on host is the shadow page table for the page
3801 * table in guest or amd nested guest, its mmu features completely
3802 * follow the features in guest.
3805 reset_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*context
)
3807 bool uses_nx
= context
->nx
|| context
->base_role
.smep_andnot_wp
;
3810 * Passing "true" to the last argument is okay; it adds a check
3811 * on bit 8 of the SPTEs which KVM doesn't use anyway.
3813 __reset_rsvds_bits_mask(vcpu
, &context
->shadow_zero_check
,
3814 boot_cpu_data
.x86_phys_bits
,
3815 context
->shadow_root_level
, uses_nx
,
3816 guest_cpuid_has_gbpages(vcpu
), is_pse(vcpu
),
3819 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask
);
3821 static inline bool boot_cpu_is_amd(void)
3823 WARN_ON_ONCE(!tdp_enabled
);
3824 return shadow_x_mask
== 0;
3828 * the direct page table on host, use as much mmu features as
3829 * possible, however, kvm currently does not do execution-protection.
3832 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
,
3833 struct kvm_mmu
*context
)
3835 if (boot_cpu_is_amd())
3836 __reset_rsvds_bits_mask(vcpu
, &context
->shadow_zero_check
,
3837 boot_cpu_data
.x86_phys_bits
,
3838 context
->shadow_root_level
, false,
3839 cpu_has_gbpages
, true, true);
3841 __reset_rsvds_bits_mask_ept(&context
->shadow_zero_check
,
3842 boot_cpu_data
.x86_phys_bits
,
3848 * as the comments in reset_shadow_zero_bits_mask() except it
3849 * is the shadow page table for intel nested guest.
3852 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu
*vcpu
,
3853 struct kvm_mmu
*context
, bool execonly
)
3855 __reset_rsvds_bits_mask_ept(&context
->shadow_zero_check
,
3856 boot_cpu_data
.x86_phys_bits
, execonly
);
3859 static void update_permission_bitmask(struct kvm_vcpu
*vcpu
,
3860 struct kvm_mmu
*mmu
, bool ept
)
3862 unsigned bit
, byte
, pfec
;
3864 bool fault
, x
, w
, u
, wf
, uf
, ff
, smapf
, cr4_smap
, cr4_smep
, smap
= 0;
3866 cr4_smep
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
);
3867 cr4_smap
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMAP
);
3868 for (byte
= 0; byte
< ARRAY_SIZE(mmu
->permissions
); ++byte
) {
3871 wf
= pfec
& PFERR_WRITE_MASK
;
3872 uf
= pfec
& PFERR_USER_MASK
;
3873 ff
= pfec
& PFERR_FETCH_MASK
;
3875 * PFERR_RSVD_MASK bit is set in PFEC if the access is not
3876 * subject to SMAP restrictions, and cleared otherwise. The
3877 * bit is only meaningful if the SMAP bit is set in CR4.
3879 smapf
= !(pfec
& PFERR_RSVD_MASK
);
3880 for (bit
= 0; bit
< 8; ++bit
) {
3881 x
= bit
& ACC_EXEC_MASK
;
3882 w
= bit
& ACC_WRITE_MASK
;
3883 u
= bit
& ACC_USER_MASK
;
3886 /* Not really needed: !nx will cause pte.nx to fault */
3888 /* Allow supervisor writes if !cr0.wp */
3889 w
|= !is_write_protection(vcpu
) && !uf
;
3890 /* Disallow supervisor fetches of user code if cr4.smep */
3891 x
&= !(cr4_smep
&& u
&& !uf
);
3894 * SMAP:kernel-mode data accesses from user-mode
3895 * mappings should fault. A fault is considered
3896 * as a SMAP violation if all of the following
3897 * conditions are ture:
3898 * - X86_CR4_SMAP is set in CR4
3899 * - An user page is accessed
3900 * - Page fault in kernel mode
3901 * - if CPL = 3 or X86_EFLAGS_AC is clear
3903 * Here, we cover the first three conditions.
3904 * The fourth is computed dynamically in
3905 * permission_fault() and is in smapf.
3907 * Also, SMAP does not affect instruction
3908 * fetches, add the !ff check here to make it
3911 smap
= cr4_smap
&& u
&& !uf
&& !ff
;
3913 /* Not really needed: no U/S accesses on ept */
3916 fault
= (ff
&& !x
) || (uf
&& !u
) || (wf
&& !w
) ||
3918 map
|= fault
<< bit
;
3920 mmu
->permissions
[byte
] = map
;
3925 * PKU is an additional mechanism by which the paging controls access to
3926 * user-mode addresses based on the value in the PKRU register. Protection
3927 * key violations are reported through a bit in the page fault error code.
3928 * Unlike other bits of the error code, the PK bit is not known at the
3929 * call site of e.g. gva_to_gpa; it must be computed directly in
3930 * permission_fault based on two bits of PKRU, on some machine state (CR4,
3931 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
3933 * In particular the following conditions come from the error code, the
3934 * page tables and the machine state:
3935 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
3936 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
3937 * - PK is always zero if U=0 in the page tables
3938 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
3940 * The PKRU bitmask caches the result of these four conditions. The error
3941 * code (minus the P bit) and the page table's U bit form an index into the
3942 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
3943 * with the two bits of the PKRU register corresponding to the protection key.
3944 * For the first three conditions above the bits will be 00, thus masking
3945 * away both AD and WD. For all reads or if the last condition holds, WD
3946 * only will be masked away.
3948 static void update_pkru_bitmask(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
,
3959 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
3960 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
) || !is_long_mode(vcpu
)) {
3965 wp
= is_write_protection(vcpu
);
3967 for (bit
= 0; bit
< ARRAY_SIZE(mmu
->permissions
); ++bit
) {
3968 unsigned pfec
, pkey_bits
;
3969 bool check_pkey
, check_write
, ff
, uf
, wf
, pte_user
;
3972 ff
= pfec
& PFERR_FETCH_MASK
;
3973 uf
= pfec
& PFERR_USER_MASK
;
3974 wf
= pfec
& PFERR_WRITE_MASK
;
3976 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
3977 pte_user
= pfec
& PFERR_RSVD_MASK
;
3980 * Only need to check the access which is not an
3981 * instruction fetch and is to a user page.
3983 check_pkey
= (!ff
&& pte_user
);
3985 * write access is controlled by PKRU if it is a
3986 * user access or CR0.WP = 1.
3988 check_write
= check_pkey
&& wf
&& (uf
|| wp
);
3990 /* PKRU.AD stops both read and write access. */
3991 pkey_bits
= !!check_pkey
;
3992 /* PKRU.WD stops write access. */
3993 pkey_bits
|= (!!check_write
) << 1;
3995 mmu
->pkru_mask
|= (pkey_bits
& 3) << pfec
;
3999 static void update_last_nonleaf_level(struct kvm_vcpu
*vcpu
, struct kvm_mmu
*mmu
)
4001 unsigned root_level
= mmu
->root_level
;
4003 mmu
->last_nonleaf_level
= root_level
;
4004 if (root_level
== PT32_ROOT_LEVEL
&& is_pse(vcpu
))
4005 mmu
->last_nonleaf_level
++;
4008 static void paging64_init_context_common(struct kvm_vcpu
*vcpu
,
4009 struct kvm_mmu
*context
,
4012 context
->nx
= is_nx(vcpu
);
4013 context
->root_level
= level
;
4015 reset_rsvds_bits_mask(vcpu
, context
);
4016 update_permission_bitmask(vcpu
, context
, false);
4017 update_pkru_bitmask(vcpu
, context
, false);
4018 update_last_nonleaf_level(vcpu
, context
);
4020 MMU_WARN_ON(!is_pae(vcpu
));
4021 context
->page_fault
= paging64_page_fault
;
4022 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4023 context
->sync_page
= paging64_sync_page
;
4024 context
->invlpg
= paging64_invlpg
;
4025 context
->update_pte
= paging64_update_pte
;
4026 context
->shadow_root_level
= level
;
4027 context
->root_hpa
= INVALID_PAGE
;
4028 context
->direct_map
= false;
4031 static void paging64_init_context(struct kvm_vcpu
*vcpu
,
4032 struct kvm_mmu
*context
)
4034 paging64_init_context_common(vcpu
, context
, PT64_ROOT_LEVEL
);
4037 static void paging32_init_context(struct kvm_vcpu
*vcpu
,
4038 struct kvm_mmu
*context
)
4040 context
->nx
= false;
4041 context
->root_level
= PT32_ROOT_LEVEL
;
4043 reset_rsvds_bits_mask(vcpu
, context
);
4044 update_permission_bitmask(vcpu
, context
, false);
4045 update_pkru_bitmask(vcpu
, context
, false);
4046 update_last_nonleaf_level(vcpu
, context
);
4048 context
->page_fault
= paging32_page_fault
;
4049 context
->gva_to_gpa
= paging32_gva_to_gpa
;
4050 context
->sync_page
= paging32_sync_page
;
4051 context
->invlpg
= paging32_invlpg
;
4052 context
->update_pte
= paging32_update_pte
;
4053 context
->shadow_root_level
= PT32E_ROOT_LEVEL
;
4054 context
->root_hpa
= INVALID_PAGE
;
4055 context
->direct_map
= false;
4058 static void paging32E_init_context(struct kvm_vcpu
*vcpu
,
4059 struct kvm_mmu
*context
)
4061 paging64_init_context_common(vcpu
, context
, PT32E_ROOT_LEVEL
);
4064 static void init_kvm_tdp_mmu(struct kvm_vcpu
*vcpu
)
4066 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4068 context
->base_role
.word
= 0;
4069 context
->base_role
.smm
= is_smm(vcpu
);
4070 context
->page_fault
= tdp_page_fault
;
4071 context
->sync_page
= nonpaging_sync_page
;
4072 context
->invlpg
= nonpaging_invlpg
;
4073 context
->update_pte
= nonpaging_update_pte
;
4074 context
->shadow_root_level
= kvm_x86_ops
->get_tdp_level();
4075 context
->root_hpa
= INVALID_PAGE
;
4076 context
->direct_map
= true;
4077 context
->set_cr3
= kvm_x86_ops
->set_tdp_cr3
;
4078 context
->get_cr3
= get_cr3
;
4079 context
->get_pdptr
= kvm_pdptr_read
;
4080 context
->inject_page_fault
= kvm_inject_page_fault
;
4082 if (!is_paging(vcpu
)) {
4083 context
->nx
= false;
4084 context
->gva_to_gpa
= nonpaging_gva_to_gpa
;
4085 context
->root_level
= 0;
4086 } else if (is_long_mode(vcpu
)) {
4087 context
->nx
= is_nx(vcpu
);
4088 context
->root_level
= PT64_ROOT_LEVEL
;
4089 reset_rsvds_bits_mask(vcpu
, context
);
4090 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4091 } else if (is_pae(vcpu
)) {
4092 context
->nx
= is_nx(vcpu
);
4093 context
->root_level
= PT32E_ROOT_LEVEL
;
4094 reset_rsvds_bits_mask(vcpu
, context
);
4095 context
->gva_to_gpa
= paging64_gva_to_gpa
;
4097 context
->nx
= false;
4098 context
->root_level
= PT32_ROOT_LEVEL
;
4099 reset_rsvds_bits_mask(vcpu
, context
);
4100 context
->gva_to_gpa
= paging32_gva_to_gpa
;
4103 update_permission_bitmask(vcpu
, context
, false);
4104 update_pkru_bitmask(vcpu
, context
, false);
4105 update_last_nonleaf_level(vcpu
, context
);
4106 reset_tdp_shadow_zero_bits_mask(vcpu
, context
);
4109 void kvm_init_shadow_mmu(struct kvm_vcpu
*vcpu
)
4111 bool smep
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMEP
);
4112 bool smap
= kvm_read_cr4_bits(vcpu
, X86_CR4_SMAP
);
4113 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4115 MMU_WARN_ON(VALID_PAGE(context
->root_hpa
));
4117 if (!is_paging(vcpu
))
4118 nonpaging_init_context(vcpu
, context
);
4119 else if (is_long_mode(vcpu
))
4120 paging64_init_context(vcpu
, context
);
4121 else if (is_pae(vcpu
))
4122 paging32E_init_context(vcpu
, context
);
4124 paging32_init_context(vcpu
, context
);
4126 context
->base_role
.nxe
= is_nx(vcpu
);
4127 context
->base_role
.cr4_pae
= !!is_pae(vcpu
);
4128 context
->base_role
.cr0_wp
= is_write_protection(vcpu
);
4129 context
->base_role
.smep_andnot_wp
4130 = smep
&& !is_write_protection(vcpu
);
4131 context
->base_role
.smap_andnot_wp
4132 = smap
&& !is_write_protection(vcpu
);
4133 context
->base_role
.smm
= is_smm(vcpu
);
4134 reset_shadow_zero_bits_mask(vcpu
, context
);
4136 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu
);
4138 void kvm_init_shadow_ept_mmu(struct kvm_vcpu
*vcpu
, bool execonly
)
4140 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4142 MMU_WARN_ON(VALID_PAGE(context
->root_hpa
));
4144 context
->shadow_root_level
= kvm_x86_ops
->get_tdp_level();
4147 context
->page_fault
= ept_page_fault
;
4148 context
->gva_to_gpa
= ept_gva_to_gpa
;
4149 context
->sync_page
= ept_sync_page
;
4150 context
->invlpg
= ept_invlpg
;
4151 context
->update_pte
= ept_update_pte
;
4152 context
->root_level
= context
->shadow_root_level
;
4153 context
->root_hpa
= INVALID_PAGE
;
4154 context
->direct_map
= false;
4156 update_permission_bitmask(vcpu
, context
, true);
4157 update_pkru_bitmask(vcpu
, context
, true);
4158 reset_rsvds_bits_mask_ept(vcpu
, context
, execonly
);
4159 reset_ept_shadow_zero_bits_mask(vcpu
, context
, execonly
);
4161 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu
);
4163 static void init_kvm_softmmu(struct kvm_vcpu
*vcpu
)
4165 struct kvm_mmu
*context
= &vcpu
->arch
.mmu
;
4167 kvm_init_shadow_mmu(vcpu
);
4168 context
->set_cr3
= kvm_x86_ops
->set_cr3
;
4169 context
->get_cr3
= get_cr3
;
4170 context
->get_pdptr
= kvm_pdptr_read
;
4171 context
->inject_page_fault
= kvm_inject_page_fault
;
4174 static void init_kvm_nested_mmu(struct kvm_vcpu
*vcpu
)
4176 struct kvm_mmu
*g_context
= &vcpu
->arch
.nested_mmu
;
4178 g_context
->get_cr3
= get_cr3
;
4179 g_context
->get_pdptr
= kvm_pdptr_read
;
4180 g_context
->inject_page_fault
= kvm_inject_page_fault
;
4183 * Note that arch.mmu.gva_to_gpa translates l2_gpa to l1_gpa using
4184 * L1's nested page tables (e.g. EPT12). The nested translation
4185 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4186 * L2's page tables as the first level of translation and L1's
4187 * nested page tables as the second level of translation. Basically
4188 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4190 if (!is_paging(vcpu
)) {
4191 g_context
->nx
= false;
4192 g_context
->root_level
= 0;
4193 g_context
->gva_to_gpa
= nonpaging_gva_to_gpa_nested
;
4194 } else if (is_long_mode(vcpu
)) {
4195 g_context
->nx
= is_nx(vcpu
);
4196 g_context
->root_level
= PT64_ROOT_LEVEL
;
4197 reset_rsvds_bits_mask(vcpu
, g_context
);
4198 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
4199 } else if (is_pae(vcpu
)) {
4200 g_context
->nx
= is_nx(vcpu
);
4201 g_context
->root_level
= PT32E_ROOT_LEVEL
;
4202 reset_rsvds_bits_mask(vcpu
, g_context
);
4203 g_context
->gva_to_gpa
= paging64_gva_to_gpa_nested
;
4205 g_context
->nx
= false;
4206 g_context
->root_level
= PT32_ROOT_LEVEL
;
4207 reset_rsvds_bits_mask(vcpu
, g_context
);
4208 g_context
->gva_to_gpa
= paging32_gva_to_gpa_nested
;
4211 update_permission_bitmask(vcpu
, g_context
, false);
4212 update_pkru_bitmask(vcpu
, g_context
, false);
4213 update_last_nonleaf_level(vcpu
, g_context
);
4216 static void init_kvm_mmu(struct kvm_vcpu
*vcpu
)
4218 if (mmu_is_nested(vcpu
))
4219 init_kvm_nested_mmu(vcpu
);
4220 else if (tdp_enabled
)
4221 init_kvm_tdp_mmu(vcpu
);
4223 init_kvm_softmmu(vcpu
);
4226 void kvm_mmu_reset_context(struct kvm_vcpu
*vcpu
)
4228 kvm_mmu_unload(vcpu
);
4231 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context
);
4233 int kvm_mmu_load(struct kvm_vcpu
*vcpu
)
4237 r
= mmu_topup_memory_caches(vcpu
);
4240 r
= mmu_alloc_roots(vcpu
);
4241 kvm_mmu_sync_roots(vcpu
);
4244 /* set_cr3() should ensure TLB has been flushed */
4245 vcpu
->arch
.mmu
.set_cr3(vcpu
, vcpu
->arch
.mmu
.root_hpa
);
4249 EXPORT_SYMBOL_GPL(kvm_mmu_load
);
4251 void kvm_mmu_unload(struct kvm_vcpu
*vcpu
)
4253 mmu_free_roots(vcpu
);
4254 WARN_ON(VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
4256 EXPORT_SYMBOL_GPL(kvm_mmu_unload
);
4258 static void mmu_pte_write_new_pte(struct kvm_vcpu
*vcpu
,
4259 struct kvm_mmu_page
*sp
, u64
*spte
,
4262 if (sp
->role
.level
!= PT_PAGE_TABLE_LEVEL
) {
4263 ++vcpu
->kvm
->stat
.mmu_pde_zapped
;
4267 ++vcpu
->kvm
->stat
.mmu_pte_updated
;
4268 vcpu
->arch
.mmu
.update_pte(vcpu
, sp
, spte
, new);
4271 static bool need_remote_flush(u64 old
, u64
new)
4273 if (!is_shadow_present_pte(old
))
4275 if (!is_shadow_present_pte(new))
4277 if ((old
^ new) & PT64_BASE_ADDR_MASK
)
4279 old
^= shadow_nx_mask
;
4280 new ^= shadow_nx_mask
;
4281 return (old
& ~new & PT64_PERM_MASK
) != 0;
4284 static u64
mmu_pte_write_fetch_gpte(struct kvm_vcpu
*vcpu
, gpa_t
*gpa
,
4285 const u8
*new, int *bytes
)
4291 * Assume that the pte write on a page table of the same type
4292 * as the current vcpu paging mode since we update the sptes only
4293 * when they have the same mode.
4295 if (is_pae(vcpu
) && *bytes
== 4) {
4296 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4299 r
= kvm_vcpu_read_guest(vcpu
, *gpa
, &gentry
, 8);
4302 new = (const u8
*)&gentry
;
4307 gentry
= *(const u32
*)new;
4310 gentry
= *(const u64
*)new;
4321 * If we're seeing too many writes to a page, it may no longer be a page table,
4322 * or we may be forking, in which case it is better to unmap the page.
4324 static bool detect_write_flooding(struct kvm_mmu_page
*sp
)
4327 * Skip write-flooding detected for the sp whose level is 1, because
4328 * it can become unsync, then the guest page is not write-protected.
4330 if (sp
->role
.level
== PT_PAGE_TABLE_LEVEL
)
4333 atomic_inc(&sp
->write_flooding_count
);
4334 return atomic_read(&sp
->write_flooding_count
) >= 3;
4338 * Misaligned accesses are too much trouble to fix up; also, they usually
4339 * indicate a page is not used as a page table.
4341 static bool detect_write_misaligned(struct kvm_mmu_page
*sp
, gpa_t gpa
,
4344 unsigned offset
, pte_size
, misaligned
;
4346 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4347 gpa
, bytes
, sp
->role
.word
);
4349 offset
= offset_in_page(gpa
);
4350 pte_size
= sp
->role
.cr4_pae
? 8 : 4;
4353 * Sometimes, the OS only writes the last one bytes to update status
4354 * bits, for example, in linux, andb instruction is used in clear_bit().
4356 if (!(offset
& (pte_size
- 1)) && bytes
== 1)
4359 misaligned
= (offset
^ (offset
+ bytes
- 1)) & ~(pte_size
- 1);
4360 misaligned
|= bytes
< 4;
4365 static u64
*get_written_sptes(struct kvm_mmu_page
*sp
, gpa_t gpa
, int *nspte
)
4367 unsigned page_offset
, quadrant
;
4371 page_offset
= offset_in_page(gpa
);
4372 level
= sp
->role
.level
;
4374 if (!sp
->role
.cr4_pae
) {
4375 page_offset
<<= 1; /* 32->64 */
4377 * A 32-bit pde maps 4MB while the shadow pdes map
4378 * only 2MB. So we need to double the offset again
4379 * and zap two pdes instead of one.
4381 if (level
== PT32_ROOT_LEVEL
) {
4382 page_offset
&= ~7; /* kill rounding error */
4386 quadrant
= page_offset
>> PAGE_SHIFT
;
4387 page_offset
&= ~PAGE_MASK
;
4388 if (quadrant
!= sp
->role
.quadrant
)
4392 spte
= &sp
->spt
[page_offset
/ sizeof(*spte
)];
4396 static void kvm_mmu_pte_write(struct kvm_vcpu
*vcpu
, gpa_t gpa
,
4397 const u8
*new, int bytes
)
4399 gfn_t gfn
= gpa
>> PAGE_SHIFT
;
4400 struct kvm_mmu_page
*sp
;
4401 LIST_HEAD(invalid_list
);
4402 u64 entry
, gentry
, *spte
;
4404 bool remote_flush
, local_flush
;
4405 union kvm_mmu_page_role mask
= { };
4410 mask
.smep_andnot_wp
= 1;
4411 mask
.smap_andnot_wp
= 1;
4415 * If we don't have indirect shadow pages, it means no page is
4416 * write-protected, so we can exit simply.
4418 if (!ACCESS_ONCE(vcpu
->kvm
->arch
.indirect_shadow_pages
))
4421 remote_flush
= local_flush
= false;
4423 pgprintk("%s: gpa %llx bytes %d\n", __func__
, gpa
, bytes
);
4425 gentry
= mmu_pte_write_fetch_gpte(vcpu
, &gpa
, new, &bytes
);
4428 * No need to care whether allocation memory is successful
4429 * or not since pte prefetch is skiped if it does not have
4430 * enough objects in the cache.
4432 mmu_topup_memory_caches(vcpu
);
4434 spin_lock(&vcpu
->kvm
->mmu_lock
);
4435 ++vcpu
->kvm
->stat
.mmu_pte_write
;
4436 kvm_mmu_audit(vcpu
, AUDIT_PRE_PTE_WRITE
);
4438 for_each_gfn_indirect_valid_sp(vcpu
->kvm
, sp
, gfn
) {
4439 if (detect_write_misaligned(sp
, gpa
, bytes
) ||
4440 detect_write_flooding(sp
)) {
4441 kvm_mmu_prepare_zap_page(vcpu
->kvm
, sp
, &invalid_list
);
4442 ++vcpu
->kvm
->stat
.mmu_flooded
;
4446 spte
= get_written_sptes(sp
, gpa
, &npte
);
4453 mmu_page_zap_pte(vcpu
->kvm
, sp
, spte
);
4455 !((sp
->role
.word
^ vcpu
->arch
.mmu
.base_role
.word
)
4456 & mask
.word
) && rmap_can_add(vcpu
))
4457 mmu_pte_write_new_pte(vcpu
, sp
, spte
, &gentry
);
4458 if (need_remote_flush(entry
, *spte
))
4459 remote_flush
= true;
4463 kvm_mmu_flush_or_zap(vcpu
, &invalid_list
, remote_flush
, local_flush
);
4464 kvm_mmu_audit(vcpu
, AUDIT_POST_PTE_WRITE
);
4465 spin_unlock(&vcpu
->kvm
->mmu_lock
);
4468 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu
*vcpu
, gva_t gva
)
4473 if (vcpu
->arch
.mmu
.direct_map
)
4476 gpa
= kvm_mmu_gva_to_gpa_read(vcpu
, gva
, NULL
);
4478 r
= kvm_mmu_unprotect_page(vcpu
->kvm
, gpa
>> PAGE_SHIFT
);
4482 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt
);
4484 static void make_mmu_pages_available(struct kvm_vcpu
*vcpu
)
4486 LIST_HEAD(invalid_list
);
4488 if (likely(kvm_mmu_available_pages(vcpu
->kvm
) >= KVM_MIN_FREE_MMU_PAGES
))
4491 while (kvm_mmu_available_pages(vcpu
->kvm
) < KVM_REFILL_PAGES
) {
4492 if (!prepare_zap_oldest_mmu_page(vcpu
->kvm
, &invalid_list
))
4495 ++vcpu
->kvm
->stat
.mmu_recycled
;
4497 kvm_mmu_commit_zap_page(vcpu
->kvm
, &invalid_list
);
4500 int kvm_mmu_page_fault(struct kvm_vcpu
*vcpu
, gva_t cr2
, u32 error_code
,
4501 void *insn
, int insn_len
)
4503 int r
, emulation_type
= EMULTYPE_RETRY
;
4504 enum emulation_result er
;
4505 bool direct
= vcpu
->arch
.mmu
.direct_map
|| mmu_is_nested(vcpu
);
4507 if (unlikely(error_code
& PFERR_RSVD_MASK
)) {
4508 r
= handle_mmio_page_fault(vcpu
, cr2
, direct
);
4509 if (r
== RET_MMIO_PF_EMULATE
) {
4513 if (r
== RET_MMIO_PF_RETRY
)
4519 r
= vcpu
->arch
.mmu
.page_fault(vcpu
, cr2
, error_code
, false);
4525 if (mmio_info_in_cache(vcpu
, cr2
, direct
))
4528 er
= x86_emulate_instruction(vcpu
, cr2
, emulation_type
, insn
, insn_len
);
4533 case EMULATE_USER_EXIT
:
4534 ++vcpu
->stat
.mmio_exits
;
4542 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault
);
4544 void kvm_mmu_invlpg(struct kvm_vcpu
*vcpu
, gva_t gva
)
4546 vcpu
->arch
.mmu
.invlpg(vcpu
, gva
);
4547 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
4548 ++vcpu
->stat
.invlpg
;
4550 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg
);
4552 void kvm_enable_tdp(void)
4556 EXPORT_SYMBOL_GPL(kvm_enable_tdp
);
4558 void kvm_disable_tdp(void)
4560 tdp_enabled
= false;
4562 EXPORT_SYMBOL_GPL(kvm_disable_tdp
);
4564 static void free_mmu_pages(struct kvm_vcpu
*vcpu
)
4566 free_page((unsigned long)vcpu
->arch
.mmu
.pae_root
);
4567 if (vcpu
->arch
.mmu
.lm_root
!= NULL
)
4568 free_page((unsigned long)vcpu
->arch
.mmu
.lm_root
);
4571 static int alloc_mmu_pages(struct kvm_vcpu
*vcpu
)
4577 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4578 * Therefore we need to allocate shadow page tables in the first
4579 * 4GB of memory, which happens to fit the DMA32 zone.
4581 page
= alloc_page(GFP_KERNEL
| __GFP_DMA32
);
4585 vcpu
->arch
.mmu
.pae_root
= page_address(page
);
4586 for (i
= 0; i
< 4; ++i
)
4587 vcpu
->arch
.mmu
.pae_root
[i
] = INVALID_PAGE
;
4592 int kvm_mmu_create(struct kvm_vcpu
*vcpu
)
4594 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
4595 vcpu
->arch
.mmu
.root_hpa
= INVALID_PAGE
;
4596 vcpu
->arch
.mmu
.translate_gpa
= translate_gpa
;
4597 vcpu
->arch
.nested_mmu
.translate_gpa
= translate_nested_gpa
;
4599 return alloc_mmu_pages(vcpu
);
4602 void kvm_mmu_setup(struct kvm_vcpu
*vcpu
)
4604 MMU_WARN_ON(VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
));
4609 void kvm_mmu_init_vm(struct kvm
*kvm
)
4611 struct kvm_page_track_notifier_node
*node
= &kvm
->arch
.mmu_sp_tracker
;
4613 node
->track_write
= kvm_mmu_pte_write
;
4614 kvm_page_track_register_notifier(kvm
, node
);
4617 void kvm_mmu_uninit_vm(struct kvm
*kvm
)
4619 struct kvm_page_track_notifier_node
*node
= &kvm
->arch
.mmu_sp_tracker
;
4621 kvm_page_track_unregister_notifier(kvm
, node
);
4624 /* The return value indicates if tlb flush on all vcpus is needed. */
4625 typedef bool (*slot_level_handler
) (struct kvm
*kvm
, struct kvm_rmap_head
*rmap_head
);
4627 /* The caller should hold mmu-lock before calling this function. */
4629 slot_handle_level_range(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
4630 slot_level_handler fn
, int start_level
, int end_level
,
4631 gfn_t start_gfn
, gfn_t end_gfn
, bool lock_flush_tlb
)
4633 struct slot_rmap_walk_iterator iterator
;
4636 for_each_slot_rmap_range(memslot
, start_level
, end_level
, start_gfn
,
4637 end_gfn
, &iterator
) {
4639 flush
|= fn(kvm
, iterator
.rmap
);
4641 if (need_resched() || spin_needbreak(&kvm
->mmu_lock
)) {
4642 if (flush
&& lock_flush_tlb
) {
4643 kvm_flush_remote_tlbs(kvm
);
4646 cond_resched_lock(&kvm
->mmu_lock
);
4650 if (flush
&& lock_flush_tlb
) {
4651 kvm_flush_remote_tlbs(kvm
);
4659 slot_handle_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
4660 slot_level_handler fn
, int start_level
, int end_level
,
4661 bool lock_flush_tlb
)
4663 return slot_handle_level_range(kvm
, memslot
, fn
, start_level
,
4664 end_level
, memslot
->base_gfn
,
4665 memslot
->base_gfn
+ memslot
->npages
- 1,
4670 slot_handle_all_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
4671 slot_level_handler fn
, bool lock_flush_tlb
)
4673 return slot_handle_level(kvm
, memslot
, fn
, PT_PAGE_TABLE_LEVEL
,
4674 PT_MAX_HUGEPAGE_LEVEL
, lock_flush_tlb
);
4678 slot_handle_large_level(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
4679 slot_level_handler fn
, bool lock_flush_tlb
)
4681 return slot_handle_level(kvm
, memslot
, fn
, PT_PAGE_TABLE_LEVEL
+ 1,
4682 PT_MAX_HUGEPAGE_LEVEL
, lock_flush_tlb
);
4686 slot_handle_leaf(struct kvm
*kvm
, struct kvm_memory_slot
*memslot
,
4687 slot_level_handler fn
, bool lock_flush_tlb
)
4689 return slot_handle_level(kvm
, memslot
, fn
, PT_PAGE_TABLE_LEVEL
,
4690 PT_PAGE_TABLE_LEVEL
, lock_flush_tlb
);
4693 void kvm_zap_gfn_range(struct kvm
*kvm
, gfn_t gfn_start
, gfn_t gfn_end
)
4695 struct kvm_memslots
*slots
;
4696 struct kvm_memory_slot
*memslot
;
4699 spin_lock(&kvm
->mmu_lock
);
4700 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
4701 slots
= __kvm_memslots(kvm
, i
);
4702 kvm_for_each_memslot(memslot
, slots
) {
4705 start
= max(gfn_start
, memslot
->base_gfn
);
4706 end
= min(gfn_end
, memslot
->base_gfn
+ memslot
->npages
);
4710 slot_handle_level_range(kvm
, memslot
, kvm_zap_rmapp
,
4711 PT_PAGE_TABLE_LEVEL
, PT_MAX_HUGEPAGE_LEVEL
,
4712 start
, end
- 1, true);
4716 spin_unlock(&kvm
->mmu_lock
);
4719 static bool slot_rmap_write_protect(struct kvm
*kvm
,
4720 struct kvm_rmap_head
*rmap_head
)
4722 return __rmap_write_protect(kvm
, rmap_head
, false);
4725 void kvm_mmu_slot_remove_write_access(struct kvm
*kvm
,
4726 struct kvm_memory_slot
*memslot
)
4730 spin_lock(&kvm
->mmu_lock
);
4731 flush
= slot_handle_all_level(kvm
, memslot
, slot_rmap_write_protect
,
4733 spin_unlock(&kvm
->mmu_lock
);
4736 * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
4737 * which do tlb flush out of mmu-lock should be serialized by
4738 * kvm->slots_lock otherwise tlb flush would be missed.
4740 lockdep_assert_held(&kvm
->slots_lock
);
4743 * We can flush all the TLBs out of the mmu lock without TLB
4744 * corruption since we just change the spte from writable to
4745 * readonly so that we only need to care the case of changing
4746 * spte from present to present (changing the spte from present
4747 * to nonpresent will flush all the TLBs immediately), in other
4748 * words, the only case we care is mmu_spte_update() where we
4749 * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
4750 * instead of PT_WRITABLE_MASK, that means it does not depend
4751 * on PT_WRITABLE_MASK anymore.
4754 kvm_flush_remote_tlbs(kvm
);
4757 static bool kvm_mmu_zap_collapsible_spte(struct kvm
*kvm
,
4758 struct kvm_rmap_head
*rmap_head
)
4761 struct rmap_iterator iter
;
4762 int need_tlb_flush
= 0;
4764 struct kvm_mmu_page
*sp
;
4767 for_each_rmap_spte(rmap_head
, &iter
, sptep
) {
4768 sp
= page_header(__pa(sptep
));
4769 pfn
= spte_to_pfn(*sptep
);
4772 * We cannot do huge page mapping for indirect shadow pages,
4773 * which are found on the last rmap (level = 1) when not using
4774 * tdp; such shadow pages are synced with the page table in
4775 * the guest, and the guest page table is using 4K page size
4776 * mapping if the indirect sp has level = 1.
4778 if (sp
->role
.direct
&&
4779 !kvm_is_reserved_pfn(pfn
) &&
4780 PageTransCompound(pfn_to_page(pfn
))) {
4781 drop_spte(kvm
, sptep
);
4787 return need_tlb_flush
;
4790 void kvm_mmu_zap_collapsible_sptes(struct kvm
*kvm
,
4791 const struct kvm_memory_slot
*memslot
)
4793 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
4794 spin_lock(&kvm
->mmu_lock
);
4795 slot_handle_leaf(kvm
, (struct kvm_memory_slot
*)memslot
,
4796 kvm_mmu_zap_collapsible_spte
, true);
4797 spin_unlock(&kvm
->mmu_lock
);
4800 void kvm_mmu_slot_leaf_clear_dirty(struct kvm
*kvm
,
4801 struct kvm_memory_slot
*memslot
)
4805 spin_lock(&kvm
->mmu_lock
);
4806 flush
= slot_handle_leaf(kvm
, memslot
, __rmap_clear_dirty
, false);
4807 spin_unlock(&kvm
->mmu_lock
);
4809 lockdep_assert_held(&kvm
->slots_lock
);
4812 * It's also safe to flush TLBs out of mmu lock here as currently this
4813 * function is only used for dirty logging, in which case flushing TLB
4814 * out of mmu lock also guarantees no dirty pages will be lost in
4818 kvm_flush_remote_tlbs(kvm
);
4820 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty
);
4822 void kvm_mmu_slot_largepage_remove_write_access(struct kvm
*kvm
,
4823 struct kvm_memory_slot
*memslot
)
4827 spin_lock(&kvm
->mmu_lock
);
4828 flush
= slot_handle_large_level(kvm
, memslot
, slot_rmap_write_protect
,
4830 spin_unlock(&kvm
->mmu_lock
);
4832 /* see kvm_mmu_slot_remove_write_access */
4833 lockdep_assert_held(&kvm
->slots_lock
);
4836 kvm_flush_remote_tlbs(kvm
);
4838 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access
);
4840 void kvm_mmu_slot_set_dirty(struct kvm
*kvm
,
4841 struct kvm_memory_slot
*memslot
)
4845 spin_lock(&kvm
->mmu_lock
);
4846 flush
= slot_handle_all_level(kvm
, memslot
, __rmap_set_dirty
, false);
4847 spin_unlock(&kvm
->mmu_lock
);
4849 lockdep_assert_held(&kvm
->slots_lock
);
4851 /* see kvm_mmu_slot_leaf_clear_dirty */
4853 kvm_flush_remote_tlbs(kvm
);
4855 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty
);
4857 #define BATCH_ZAP_PAGES 10
4858 static void kvm_zap_obsolete_pages(struct kvm
*kvm
)
4860 struct kvm_mmu_page
*sp
, *node
;
4864 list_for_each_entry_safe_reverse(sp
, node
,
4865 &kvm
->arch
.active_mmu_pages
, link
) {
4869 * No obsolete page exists before new created page since
4870 * active_mmu_pages is the FIFO list.
4872 if (!is_obsolete_sp(kvm
, sp
))
4876 * Since we are reversely walking the list and the invalid
4877 * list will be moved to the head, skip the invalid page
4878 * can help us to avoid the infinity list walking.
4880 if (sp
->role
.invalid
)
4884 * Need not flush tlb since we only zap the sp with invalid
4885 * generation number.
4887 if (batch
>= BATCH_ZAP_PAGES
&&
4888 cond_resched_lock(&kvm
->mmu_lock
)) {
4893 ret
= kvm_mmu_prepare_zap_page(kvm
, sp
,
4894 &kvm
->arch
.zapped_obsolete_pages
);
4902 * Should flush tlb before free page tables since lockless-walking
4903 * may use the pages.
4905 kvm_mmu_commit_zap_page(kvm
, &kvm
->arch
.zapped_obsolete_pages
);
4909 * Fast invalidate all shadow pages and use lock-break technique
4910 * to zap obsolete pages.
4912 * It's required when memslot is being deleted or VM is being
4913 * destroyed, in these cases, we should ensure that KVM MMU does
4914 * not use any resource of the being-deleted slot or all slots
4915 * after calling the function.
4917 void kvm_mmu_invalidate_zap_all_pages(struct kvm
*kvm
)
4919 spin_lock(&kvm
->mmu_lock
);
4920 trace_kvm_mmu_invalidate_zap_all_pages(kvm
);
4921 kvm
->arch
.mmu_valid_gen
++;
4924 * Notify all vcpus to reload its shadow page table
4925 * and flush TLB. Then all vcpus will switch to new
4926 * shadow page table with the new mmu_valid_gen.
4928 * Note: we should do this under the protection of
4929 * mmu-lock, otherwise, vcpu would purge shadow page
4930 * but miss tlb flush.
4932 kvm_reload_remote_mmus(kvm
);
4934 kvm_zap_obsolete_pages(kvm
);
4935 spin_unlock(&kvm
->mmu_lock
);
4938 static bool kvm_has_zapped_obsolete_pages(struct kvm
*kvm
)
4940 return unlikely(!list_empty_careful(&kvm
->arch
.zapped_obsolete_pages
));
4943 void kvm_mmu_invalidate_mmio_sptes(struct kvm
*kvm
, struct kvm_memslots
*slots
)
4946 * The very rare case: if the generation-number is round,
4947 * zap all shadow pages.
4949 if (unlikely((slots
->generation
& MMIO_GEN_MASK
) == 0)) {
4950 printk_ratelimited(KERN_DEBUG
"kvm: zapping shadow pages for mmio generation wraparound\n");
4951 kvm_mmu_invalidate_zap_all_pages(kvm
);
4955 static unsigned long
4956 mmu_shrink_scan(struct shrinker
*shrink
, struct shrink_control
*sc
)
4959 int nr_to_scan
= sc
->nr_to_scan
;
4960 unsigned long freed
= 0;
4962 spin_lock(&kvm_lock
);
4964 list_for_each_entry(kvm
, &vm_list
, vm_list
) {
4966 LIST_HEAD(invalid_list
);
4969 * Never scan more than sc->nr_to_scan VM instances.
4970 * Will not hit this condition practically since we do not try
4971 * to shrink more than one VM and it is very unlikely to see
4972 * !n_used_mmu_pages so many times.
4977 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4978 * here. We may skip a VM instance errorneosly, but we do not
4979 * want to shrink a VM that only started to populate its MMU
4982 if (!kvm
->arch
.n_used_mmu_pages
&&
4983 !kvm_has_zapped_obsolete_pages(kvm
))
4986 idx
= srcu_read_lock(&kvm
->srcu
);
4987 spin_lock(&kvm
->mmu_lock
);
4989 if (kvm_has_zapped_obsolete_pages(kvm
)) {
4990 kvm_mmu_commit_zap_page(kvm
,
4991 &kvm
->arch
.zapped_obsolete_pages
);
4995 if (prepare_zap_oldest_mmu_page(kvm
, &invalid_list
))
4997 kvm_mmu_commit_zap_page(kvm
, &invalid_list
);
5000 spin_unlock(&kvm
->mmu_lock
);
5001 srcu_read_unlock(&kvm
->srcu
, idx
);
5004 * unfair on small ones
5005 * per-vm shrinkers cry out
5006 * sadness comes quickly
5008 list_move_tail(&kvm
->vm_list
, &vm_list
);
5012 spin_unlock(&kvm_lock
);
5016 static unsigned long
5017 mmu_shrink_count(struct shrinker
*shrink
, struct shrink_control
*sc
)
5019 return percpu_counter_read_positive(&kvm_total_used_mmu_pages
);
5022 static struct shrinker mmu_shrinker
= {
5023 .count_objects
= mmu_shrink_count
,
5024 .scan_objects
= mmu_shrink_scan
,
5025 .seeks
= DEFAULT_SEEKS
* 10,
5028 static void mmu_destroy_caches(void)
5030 if (pte_list_desc_cache
)
5031 kmem_cache_destroy(pte_list_desc_cache
);
5032 if (mmu_page_header_cache
)
5033 kmem_cache_destroy(mmu_page_header_cache
);
5036 int kvm_mmu_module_init(void)
5038 pte_list_desc_cache
= kmem_cache_create("pte_list_desc",
5039 sizeof(struct pte_list_desc
),
5041 if (!pte_list_desc_cache
)
5044 mmu_page_header_cache
= kmem_cache_create("kvm_mmu_page_header",
5045 sizeof(struct kvm_mmu_page
),
5047 if (!mmu_page_header_cache
)
5050 if (percpu_counter_init(&kvm_total_used_mmu_pages
, 0, GFP_KERNEL
))
5053 register_shrinker(&mmu_shrinker
);
5058 mmu_destroy_caches();
5063 * Caculate mmu pages needed for kvm.
5065 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm
*kvm
)
5067 unsigned int nr_mmu_pages
;
5068 unsigned int nr_pages
= 0;
5069 struct kvm_memslots
*slots
;
5070 struct kvm_memory_slot
*memslot
;
5073 for (i
= 0; i
< KVM_ADDRESS_SPACE_NUM
; i
++) {
5074 slots
= __kvm_memslots(kvm
, i
);
5076 kvm_for_each_memslot(memslot
, slots
)
5077 nr_pages
+= memslot
->npages
;
5080 nr_mmu_pages
= nr_pages
* KVM_PERMILLE_MMU_PAGES
/ 1000;
5081 nr_mmu_pages
= max(nr_mmu_pages
,
5082 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES
);
5084 return nr_mmu_pages
;
5087 void kvm_mmu_destroy(struct kvm_vcpu
*vcpu
)
5089 kvm_mmu_unload(vcpu
);
5090 free_mmu_pages(vcpu
);
5091 mmu_free_memory_caches(vcpu
);
5094 void kvm_mmu_module_exit(void)
5096 mmu_destroy_caches();
5097 percpu_counter_destroy(&kvm_total_used_mmu_pages
);
5098 unregister_shrinker(&mmu_shrinker
);
5099 mmu_audit_disable();