2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include "kvm_cache_regs.h"
43 #include <asm/virtext.h>
45 #include <asm/fpu/internal.h>
46 #include <asm/perf_event.h>
47 #include <asm/debugreg.h>
48 #include <asm/kexec.h>
50 #include <asm/irq_remapping.h>
55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
56 #define __ex_clear(x, reg) \
57 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
59 MODULE_AUTHOR("Qumranet");
60 MODULE_LICENSE("GPL");
62 static const struct x86_cpu_id vmx_cpu_id
[] = {
63 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
66 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
68 static bool __read_mostly enable_vpid
= 1;
69 module_param_named(vpid
, enable_vpid
, bool, 0444);
71 static bool __read_mostly flexpriority_enabled
= 1;
72 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
74 static bool __read_mostly enable_ept
= 1;
75 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
77 static bool __read_mostly enable_unrestricted_guest
= 1;
78 module_param_named(unrestricted_guest
,
79 enable_unrestricted_guest
, bool, S_IRUGO
);
81 static bool __read_mostly enable_ept_ad_bits
= 1;
82 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
84 static bool __read_mostly emulate_invalid_guest_state
= true;
85 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
87 static bool __read_mostly vmm_exclusive
= 1;
88 module_param(vmm_exclusive
, bool, S_IRUGO
);
90 static bool __read_mostly fasteoi
= 1;
91 module_param(fasteoi
, bool, S_IRUGO
);
93 static bool __read_mostly enable_apicv
= 1;
94 module_param(enable_apicv
, bool, S_IRUGO
);
96 static bool __read_mostly enable_shadow_vmcs
= 1;
97 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
99 * If nested=1, nested virtualization is supported, i.e., guests may use
100 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
101 * use VMX instructions.
103 static bool __read_mostly nested
= 0;
104 module_param(nested
, bool, S_IRUGO
);
106 static u64 __read_mostly host_xss
;
108 static bool __read_mostly enable_pml
= 1;
109 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
111 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
113 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
114 static int __read_mostly cpu_preemption_timer_multi
;
115 static bool __read_mostly enable_preemption_timer
= 1;
117 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
122 #define KVM_VM_CR0_ALWAYS_ON \
123 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
124 #define KVM_CR4_GUEST_OWNED_BITS \
125 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
126 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
136 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
137 * ple_gap: upper bound on the amount of time between two successive
138 * executions of PAUSE in a loop. Also indicate if ple enabled.
139 * According to test, this time is usually smaller than 128 cycles.
140 * ple_window: upper bound on the amount of time a guest is allowed to execute
141 * in a PAUSE loop. Tests indicate that most spinlocks are held for
142 * less than 2^12 cycles
143 * Time is measured based on a counter that runs at the same rate as the TSC,
144 * refer SDM volume 3b section 21.6.13 & 22.1.3.
146 #define KVM_VMX_DEFAULT_PLE_GAP 128
147 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
148 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
149 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
150 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
151 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
153 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
154 module_param(ple_gap
, int, S_IRUGO
);
156 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
157 module_param(ple_window
, int, S_IRUGO
);
159 /* Default doubles per-vcpu window every exit. */
160 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
161 module_param(ple_window_grow
, int, S_IRUGO
);
163 /* Default resets per-vcpu window every exit to ple_window. */
164 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
165 module_param(ple_window_shrink
, int, S_IRUGO
);
167 /* Default is to compute the maximum so we can never overflow. */
168 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
169 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
170 module_param(ple_window_max
, int, S_IRUGO
);
172 extern const ulong vmx_return
;
174 #define NR_AUTOLOAD_MSRS 8
175 #define VMCS02_POOL_SIZE 1
184 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
185 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
186 * loaded on this CPU (so we can clear them if the CPU goes down).
192 struct list_head loaded_vmcss_on_cpu_link
;
195 struct shared_msr_entry
{
202 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
203 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
204 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
205 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
206 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
207 * More than one of these structures may exist, if L1 runs multiple L2 guests.
208 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
209 * underlying hardware which will be used to run L2.
210 * This structure is packed to ensure that its layout is identical across
211 * machines (necessary for live migration).
212 * If there are changes in this struct, VMCS12_REVISION must be changed.
214 typedef u64 natural_width
;
215 struct __packed vmcs12
{
216 /* According to the Intel spec, a VMCS region must start with the
217 * following two fields. Then follow implementation-specific data.
222 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
223 u32 padding
[7]; /* room for future expansion */
228 u64 vm_exit_msr_store_addr
;
229 u64 vm_exit_msr_load_addr
;
230 u64 vm_entry_msr_load_addr
;
232 u64 virtual_apic_page_addr
;
233 u64 apic_access_addr
;
234 u64 posted_intr_desc_addr
;
236 u64 eoi_exit_bitmap0
;
237 u64 eoi_exit_bitmap1
;
238 u64 eoi_exit_bitmap2
;
239 u64 eoi_exit_bitmap3
;
241 u64 guest_physical_address
;
242 u64 vmcs_link_pointer
;
243 u64 guest_ia32_debugctl
;
246 u64 guest_ia32_perf_global_ctrl
;
254 u64 host_ia32_perf_global_ctrl
;
255 u64 padding64
[8]; /* room for future expansion */
257 * To allow migration of L1 (complete with its L2 guests) between
258 * machines of different natural widths (32 or 64 bit), we cannot have
259 * unsigned long fields with no explict size. We use u64 (aliased
260 * natural_width) instead. Luckily, x86 is little-endian.
262 natural_width cr0_guest_host_mask
;
263 natural_width cr4_guest_host_mask
;
264 natural_width cr0_read_shadow
;
265 natural_width cr4_read_shadow
;
266 natural_width cr3_target_value0
;
267 natural_width cr3_target_value1
;
268 natural_width cr3_target_value2
;
269 natural_width cr3_target_value3
;
270 natural_width exit_qualification
;
271 natural_width guest_linear_address
;
272 natural_width guest_cr0
;
273 natural_width guest_cr3
;
274 natural_width guest_cr4
;
275 natural_width guest_es_base
;
276 natural_width guest_cs_base
;
277 natural_width guest_ss_base
;
278 natural_width guest_ds_base
;
279 natural_width guest_fs_base
;
280 natural_width guest_gs_base
;
281 natural_width guest_ldtr_base
;
282 natural_width guest_tr_base
;
283 natural_width guest_gdtr_base
;
284 natural_width guest_idtr_base
;
285 natural_width guest_dr7
;
286 natural_width guest_rsp
;
287 natural_width guest_rip
;
288 natural_width guest_rflags
;
289 natural_width guest_pending_dbg_exceptions
;
290 natural_width guest_sysenter_esp
;
291 natural_width guest_sysenter_eip
;
292 natural_width host_cr0
;
293 natural_width host_cr3
;
294 natural_width host_cr4
;
295 natural_width host_fs_base
;
296 natural_width host_gs_base
;
297 natural_width host_tr_base
;
298 natural_width host_gdtr_base
;
299 natural_width host_idtr_base
;
300 natural_width host_ia32_sysenter_esp
;
301 natural_width host_ia32_sysenter_eip
;
302 natural_width host_rsp
;
303 natural_width host_rip
;
304 natural_width paddingl
[8]; /* room for future expansion */
305 u32 pin_based_vm_exec_control
;
306 u32 cpu_based_vm_exec_control
;
307 u32 exception_bitmap
;
308 u32 page_fault_error_code_mask
;
309 u32 page_fault_error_code_match
;
310 u32 cr3_target_count
;
311 u32 vm_exit_controls
;
312 u32 vm_exit_msr_store_count
;
313 u32 vm_exit_msr_load_count
;
314 u32 vm_entry_controls
;
315 u32 vm_entry_msr_load_count
;
316 u32 vm_entry_intr_info_field
;
317 u32 vm_entry_exception_error_code
;
318 u32 vm_entry_instruction_len
;
320 u32 secondary_vm_exec_control
;
321 u32 vm_instruction_error
;
323 u32 vm_exit_intr_info
;
324 u32 vm_exit_intr_error_code
;
325 u32 idt_vectoring_info_field
;
326 u32 idt_vectoring_error_code
;
327 u32 vm_exit_instruction_len
;
328 u32 vmx_instruction_info
;
335 u32 guest_ldtr_limit
;
337 u32 guest_gdtr_limit
;
338 u32 guest_idtr_limit
;
339 u32 guest_es_ar_bytes
;
340 u32 guest_cs_ar_bytes
;
341 u32 guest_ss_ar_bytes
;
342 u32 guest_ds_ar_bytes
;
343 u32 guest_fs_ar_bytes
;
344 u32 guest_gs_ar_bytes
;
345 u32 guest_ldtr_ar_bytes
;
346 u32 guest_tr_ar_bytes
;
347 u32 guest_interruptibility_info
;
348 u32 guest_activity_state
;
349 u32 guest_sysenter_cs
;
350 u32 host_ia32_sysenter_cs
;
351 u32 vmx_preemption_timer_value
;
352 u32 padding32
[7]; /* room for future expansion */
353 u16 virtual_processor_id
;
355 u16 guest_es_selector
;
356 u16 guest_cs_selector
;
357 u16 guest_ss_selector
;
358 u16 guest_ds_selector
;
359 u16 guest_fs_selector
;
360 u16 guest_gs_selector
;
361 u16 guest_ldtr_selector
;
362 u16 guest_tr_selector
;
363 u16 guest_intr_status
;
364 u16 host_es_selector
;
365 u16 host_cs_selector
;
366 u16 host_ss_selector
;
367 u16 host_ds_selector
;
368 u16 host_fs_selector
;
369 u16 host_gs_selector
;
370 u16 host_tr_selector
;
374 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
375 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
376 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
378 #define VMCS12_REVISION 0x11e57ed0
381 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
382 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
383 * current implementation, 4K are reserved to avoid future complications.
385 #define VMCS12_SIZE 0x1000
387 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
389 struct list_head list
;
391 struct loaded_vmcs vmcs02
;
395 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
396 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
399 /* Has the level1 guest done vmxon? */
403 /* The guest-physical address of the current VMCS L1 keeps for L2 */
405 /* The host-usable pointer to the above */
406 struct page
*current_vmcs12_page
;
407 struct vmcs12
*current_vmcs12
;
409 * Cache of the guest's VMCS, existing outside of guest memory.
410 * Loaded from guest memory during VMPTRLD. Flushed to guest
411 * memory during VMXOFF, VMCLEAR, VMPTRLD.
413 struct vmcs12
*cached_vmcs12
;
414 struct vmcs
*current_shadow_vmcs
;
416 * Indicates if the shadow vmcs must be updated with the
417 * data hold by vmcs12
419 bool sync_shadow_vmcs
;
421 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
422 struct list_head vmcs02_pool
;
424 u64 vmcs01_tsc_offset
;
425 bool change_vmcs01_virtual_x2apic_mode
;
426 /* L2 must run next, and mustn't decide to exit to L1. */
427 bool nested_run_pending
;
429 * Guest pages referred to in vmcs02 with host-physical pointers, so
430 * we must keep them pinned while L2 runs.
432 struct page
*apic_access_page
;
433 struct page
*virtual_apic_page
;
434 struct page
*pi_desc_page
;
435 struct pi_desc
*pi_desc
;
439 unsigned long *msr_bitmap
;
441 struct hrtimer preemption_timer
;
442 bool preemption_timer_expired
;
444 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
450 u32 nested_vmx_procbased_ctls_low
;
451 u32 nested_vmx_procbased_ctls_high
;
452 u32 nested_vmx_true_procbased_ctls_low
;
453 u32 nested_vmx_secondary_ctls_low
;
454 u32 nested_vmx_secondary_ctls_high
;
455 u32 nested_vmx_pinbased_ctls_low
;
456 u32 nested_vmx_pinbased_ctls_high
;
457 u32 nested_vmx_exit_ctls_low
;
458 u32 nested_vmx_exit_ctls_high
;
459 u32 nested_vmx_true_exit_ctls_low
;
460 u32 nested_vmx_entry_ctls_low
;
461 u32 nested_vmx_entry_ctls_high
;
462 u32 nested_vmx_true_entry_ctls_low
;
463 u32 nested_vmx_misc_low
;
464 u32 nested_vmx_misc_high
;
465 u32 nested_vmx_ept_caps
;
466 u32 nested_vmx_vpid_caps
;
469 #define POSTED_INTR_ON 0
470 #define POSTED_INTR_SN 1
472 /* Posted-Interrupt Descriptor */
474 u32 pir
[8]; /* Posted interrupt requested */
477 /* bit 256 - Outstanding Notification */
479 /* bit 257 - Suppress Notification */
481 /* bit 271:258 - Reserved */
483 /* bit 279:272 - Notification Vector */
485 /* bit 287:280 - Reserved */
487 /* bit 319:288 - Notification Destination */
495 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
497 return test_and_set_bit(POSTED_INTR_ON
,
498 (unsigned long *)&pi_desc
->control
);
501 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
503 return test_and_clear_bit(POSTED_INTR_ON
,
504 (unsigned long *)&pi_desc
->control
);
507 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
509 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
512 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
514 return clear_bit(POSTED_INTR_SN
,
515 (unsigned long *)&pi_desc
->control
);
518 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
520 return set_bit(POSTED_INTR_SN
,
521 (unsigned long *)&pi_desc
->control
);
524 static inline int pi_test_on(struct pi_desc
*pi_desc
)
526 return test_bit(POSTED_INTR_ON
,
527 (unsigned long *)&pi_desc
->control
);
530 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
532 return test_bit(POSTED_INTR_SN
,
533 (unsigned long *)&pi_desc
->control
);
537 struct kvm_vcpu vcpu
;
538 unsigned long host_rsp
;
540 bool nmi_known_unmasked
;
542 u32 idt_vectoring_info
;
544 struct shared_msr_entry
*guest_msrs
;
547 unsigned long host_idt_base
;
549 u64 msr_host_kernel_gs_base
;
550 u64 msr_guest_kernel_gs_base
;
552 u32 vm_entry_controls_shadow
;
553 u32 vm_exit_controls_shadow
;
555 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
556 * non-nested (L1) guest, it always points to vmcs01. For a nested
557 * guest (L2), it points to a different VMCS.
559 struct loaded_vmcs vmcs01
;
560 struct loaded_vmcs
*loaded_vmcs
;
561 bool __launched
; /* temporary, used in vmx_vcpu_run */
562 struct msr_autoload
{
564 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
565 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
569 u16 fs_sel
, gs_sel
, ldt_sel
;
573 int gs_ldt_reload_needed
;
574 int fs_reload_needed
;
575 u64 msr_host_bndcfgs
;
576 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
581 struct kvm_segment segs
[8];
584 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
585 struct kvm_save_segment
{
593 bool emulation_required
;
595 /* Support for vnmi-less CPUs */
596 int soft_vnmi_blocked
;
598 s64 vnmi_blocked_time
;
601 /* Posted interrupt descriptor */
602 struct pi_desc pi_desc
;
604 /* Support for a guest hypervisor (nested VMX) */
605 struct nested_vmx nested
;
607 /* Dynamic PLE window. */
609 bool ple_window_dirty
;
611 /* Support for PML */
612 #define PML_ENTITY_NUM 512
615 /* apic deadline value in host tsc */
618 u64 current_tsc_ratio
;
620 bool guest_pkru_valid
;
625 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
626 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
627 * in msr_ia32_feature_control_valid_bits.
629 u64 msr_ia32_feature_control
;
630 u64 msr_ia32_feature_control_valid_bits
;
633 enum segment_cache_field
{
642 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
644 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
647 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
649 return &(to_vmx(vcpu
)->pi_desc
);
652 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
653 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
654 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
655 [number##_HIGH] = VMCS12_OFFSET(name)+4
658 static unsigned long shadow_read_only_fields
[] = {
660 * We do NOT shadow fields that are modified when L0
661 * traps and emulates any vmx instruction (e.g. VMPTRLD,
662 * VMXON...) executed by L1.
663 * For example, VM_INSTRUCTION_ERROR is read
664 * by L1 if a vmx instruction fails (part of the error path).
665 * Note the code assumes this logic. If for some reason
666 * we start shadowing these fields then we need to
667 * force a shadow sync when L0 emulates vmx instructions
668 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
669 * by nested_vmx_failValid)
673 VM_EXIT_INSTRUCTION_LEN
,
674 IDT_VECTORING_INFO_FIELD
,
675 IDT_VECTORING_ERROR_CODE
,
676 VM_EXIT_INTR_ERROR_CODE
,
678 GUEST_LINEAR_ADDRESS
,
679 GUEST_PHYSICAL_ADDRESS
681 static int max_shadow_read_only_fields
=
682 ARRAY_SIZE(shadow_read_only_fields
);
684 static unsigned long shadow_read_write_fields
[] = {
691 GUEST_INTERRUPTIBILITY_INFO
,
704 CPU_BASED_VM_EXEC_CONTROL
,
705 VM_ENTRY_EXCEPTION_ERROR_CODE
,
706 VM_ENTRY_INTR_INFO_FIELD
,
707 VM_ENTRY_INSTRUCTION_LEN
,
708 VM_ENTRY_EXCEPTION_ERROR_CODE
,
714 static int max_shadow_read_write_fields
=
715 ARRAY_SIZE(shadow_read_write_fields
);
717 static const unsigned short vmcs_field_to_offset_table
[] = {
718 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
719 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
720 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
721 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
722 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
723 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
724 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
725 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
726 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
727 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
728 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
729 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
730 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
731 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
732 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
733 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
734 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
735 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
736 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
737 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
738 FIELD64(MSR_BITMAP
, msr_bitmap
),
739 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
740 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
741 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
742 FIELD64(TSC_OFFSET
, tsc_offset
),
743 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
744 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
745 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
746 FIELD64(EPT_POINTER
, ept_pointer
),
747 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
748 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
749 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
750 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
751 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
752 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
753 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
754 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
755 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
756 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
757 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
758 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
759 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
760 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
761 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
762 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
763 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
764 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
765 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
766 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
767 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
768 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
769 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
770 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
771 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
772 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
773 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
774 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
775 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
776 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
777 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
778 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
779 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
780 FIELD(TPR_THRESHOLD
, tpr_threshold
),
781 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
782 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
783 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
784 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
785 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
786 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
787 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
788 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
789 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
790 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
791 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
792 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
793 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
794 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
795 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
796 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
797 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
798 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
799 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
800 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
801 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
802 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
803 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
804 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
805 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
806 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
807 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
808 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
809 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
810 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
811 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
812 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
813 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
814 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
815 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
816 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
817 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
818 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
819 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
820 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
821 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
822 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
823 FIELD(GUEST_CR0
, guest_cr0
),
824 FIELD(GUEST_CR3
, guest_cr3
),
825 FIELD(GUEST_CR4
, guest_cr4
),
826 FIELD(GUEST_ES_BASE
, guest_es_base
),
827 FIELD(GUEST_CS_BASE
, guest_cs_base
),
828 FIELD(GUEST_SS_BASE
, guest_ss_base
),
829 FIELD(GUEST_DS_BASE
, guest_ds_base
),
830 FIELD(GUEST_FS_BASE
, guest_fs_base
),
831 FIELD(GUEST_GS_BASE
, guest_gs_base
),
832 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
833 FIELD(GUEST_TR_BASE
, guest_tr_base
),
834 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
835 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
836 FIELD(GUEST_DR7
, guest_dr7
),
837 FIELD(GUEST_RSP
, guest_rsp
),
838 FIELD(GUEST_RIP
, guest_rip
),
839 FIELD(GUEST_RFLAGS
, guest_rflags
),
840 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
841 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
842 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
843 FIELD(HOST_CR0
, host_cr0
),
844 FIELD(HOST_CR3
, host_cr3
),
845 FIELD(HOST_CR4
, host_cr4
),
846 FIELD(HOST_FS_BASE
, host_fs_base
),
847 FIELD(HOST_GS_BASE
, host_gs_base
),
848 FIELD(HOST_TR_BASE
, host_tr_base
),
849 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
850 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
851 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
852 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
853 FIELD(HOST_RSP
, host_rsp
),
854 FIELD(HOST_RIP
, host_rip
),
857 static inline short vmcs_field_to_offset(unsigned long field
)
859 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
861 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
862 vmcs_field_to_offset_table
[field
] == 0)
865 return vmcs_field_to_offset_table
[field
];
868 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
870 return to_vmx(vcpu
)->nested
.cached_vmcs12
;
873 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
875 struct page
*page
= kvm_vcpu_gfn_to_page(vcpu
, addr
>> PAGE_SHIFT
);
876 if (is_error_page(page
))
882 static void nested_release_page(struct page
*page
)
884 kvm_release_page_dirty(page
);
887 static void nested_release_page_clean(struct page
*page
)
889 kvm_release_page_clean(page
);
892 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
893 static u64
construct_eptp(unsigned long root_hpa
);
894 static void kvm_cpu_vmxon(u64 addr
);
895 static void kvm_cpu_vmxoff(void);
896 static bool vmx_xsaves_supported(void);
897 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
898 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
899 struct kvm_segment
*var
, int seg
);
900 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
901 struct kvm_segment
*var
, int seg
);
902 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
903 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
904 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
905 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
906 static int alloc_identity_pagetable(struct kvm
*kvm
);
908 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
909 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
911 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
912 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
914 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
915 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
918 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
919 * can find which vCPU should be waken up.
921 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
922 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
924 static unsigned long *vmx_io_bitmap_a
;
925 static unsigned long *vmx_io_bitmap_b
;
926 static unsigned long *vmx_msr_bitmap_legacy
;
927 static unsigned long *vmx_msr_bitmap_longmode
;
928 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
929 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
930 static unsigned long *vmx_vmread_bitmap
;
931 static unsigned long *vmx_vmwrite_bitmap
;
933 static bool cpu_has_load_ia32_efer
;
934 static bool cpu_has_load_perf_global_ctrl
;
936 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
937 static DEFINE_SPINLOCK(vmx_vpid_lock
);
939 static struct vmcs_config
{
944 u32 pin_based_exec_ctrl
;
945 u32 cpu_based_exec_ctrl
;
946 u32 cpu_based_2nd_exec_ctrl
;
951 static struct vmx_capability
{
956 #define VMX_SEGMENT_FIELD(seg) \
957 [VCPU_SREG_##seg] = { \
958 .selector = GUEST_##seg##_SELECTOR, \
959 .base = GUEST_##seg##_BASE, \
960 .limit = GUEST_##seg##_LIMIT, \
961 .ar_bytes = GUEST_##seg##_AR_BYTES, \
964 static const struct kvm_vmx_segment_field
{
969 } kvm_vmx_segment_fields
[] = {
970 VMX_SEGMENT_FIELD(CS
),
971 VMX_SEGMENT_FIELD(DS
),
972 VMX_SEGMENT_FIELD(ES
),
973 VMX_SEGMENT_FIELD(FS
),
974 VMX_SEGMENT_FIELD(GS
),
975 VMX_SEGMENT_FIELD(SS
),
976 VMX_SEGMENT_FIELD(TR
),
977 VMX_SEGMENT_FIELD(LDTR
),
980 static u64 host_efer
;
982 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
985 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
986 * away by decrementing the array size.
988 static const u32 vmx_msr_index
[] = {
990 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
992 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
995 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
997 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
998 INTR_INFO_VALID_MASK
)) ==
999 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
1002 static inline bool is_debug(u32 intr_info
)
1004 return is_exception_n(intr_info
, DB_VECTOR
);
1007 static inline bool is_breakpoint(u32 intr_info
)
1009 return is_exception_n(intr_info
, BP_VECTOR
);
1012 static inline bool is_page_fault(u32 intr_info
)
1014 return is_exception_n(intr_info
, PF_VECTOR
);
1017 static inline bool is_no_device(u32 intr_info
)
1019 return is_exception_n(intr_info
, NM_VECTOR
);
1022 static inline bool is_invalid_opcode(u32 intr_info
)
1024 return is_exception_n(intr_info
, UD_VECTOR
);
1027 static inline bool is_external_interrupt(u32 intr_info
)
1029 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1030 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1033 static inline bool is_machine_check(u32 intr_info
)
1035 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1036 INTR_INFO_VALID_MASK
)) ==
1037 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1040 static inline bool cpu_has_vmx_msr_bitmap(void)
1042 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1045 static inline bool cpu_has_vmx_tpr_shadow(void)
1047 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1050 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1052 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1055 static inline bool cpu_has_secondary_exec_ctrls(void)
1057 return vmcs_config
.cpu_based_exec_ctrl
&
1058 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1061 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1063 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1064 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1067 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1069 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1070 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1073 static inline bool cpu_has_vmx_apic_register_virt(void)
1075 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1076 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1079 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1081 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1082 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1086 * Comment's format: document - errata name - stepping - processor name.
1088 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1090 static u32 vmx_preemption_cpu_tfms
[] = {
1091 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1093 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1094 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1095 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1097 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1099 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1100 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1102 * 320767.pdf - AAP86 - B1 -
1103 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1106 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1108 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1110 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1112 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1113 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1114 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1118 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1120 u32 eax
= cpuid_eax(0x00000001), i
;
1122 /* Clear the reserved bits */
1123 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
1124 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
1125 if (eax
== vmx_preemption_cpu_tfms
[i
])
1131 static inline bool cpu_has_vmx_preemption_timer(void)
1133 return vmcs_config
.pin_based_exec_ctrl
&
1134 PIN_BASED_VMX_PREEMPTION_TIMER
;
1137 static inline bool cpu_has_vmx_posted_intr(void)
1139 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1140 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1143 static inline bool cpu_has_vmx_apicv(void)
1145 return cpu_has_vmx_apic_register_virt() &&
1146 cpu_has_vmx_virtual_intr_delivery() &&
1147 cpu_has_vmx_posted_intr();
1150 static inline bool cpu_has_vmx_flexpriority(void)
1152 return cpu_has_vmx_tpr_shadow() &&
1153 cpu_has_vmx_virtualize_apic_accesses();
1156 static inline bool cpu_has_vmx_ept_execute_only(void)
1158 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1161 static inline bool cpu_has_vmx_ept_2m_page(void)
1163 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1166 static inline bool cpu_has_vmx_ept_1g_page(void)
1168 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1171 static inline bool cpu_has_vmx_ept_4levels(void)
1173 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1176 static inline bool cpu_has_vmx_ept_ad_bits(void)
1178 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1181 static inline bool cpu_has_vmx_invept_context(void)
1183 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1186 static inline bool cpu_has_vmx_invept_global(void)
1188 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1191 static inline bool cpu_has_vmx_invvpid_single(void)
1193 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1196 static inline bool cpu_has_vmx_invvpid_global(void)
1198 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1201 static inline bool cpu_has_vmx_ept(void)
1203 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1204 SECONDARY_EXEC_ENABLE_EPT
;
1207 static inline bool cpu_has_vmx_unrestricted_guest(void)
1209 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1210 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1213 static inline bool cpu_has_vmx_ple(void)
1215 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1216 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1219 static inline bool cpu_has_vmx_basic_inout(void)
1221 return (((u64
)vmcs_config
.basic_cap
<< 32) & VMX_BASIC_INOUT
);
1224 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1226 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1229 static inline bool cpu_has_vmx_vpid(void)
1231 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1232 SECONDARY_EXEC_ENABLE_VPID
;
1235 static inline bool cpu_has_vmx_rdtscp(void)
1237 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1238 SECONDARY_EXEC_RDTSCP
;
1241 static inline bool cpu_has_vmx_invpcid(void)
1243 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1244 SECONDARY_EXEC_ENABLE_INVPCID
;
1247 static inline bool cpu_has_virtual_nmis(void)
1249 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1252 static inline bool cpu_has_vmx_wbinvd_exit(void)
1254 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1255 SECONDARY_EXEC_WBINVD_EXITING
;
1258 static inline bool cpu_has_vmx_shadow_vmcs(void)
1261 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1262 /* check if the cpu supports writing r/o exit information fields */
1263 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1266 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1267 SECONDARY_EXEC_SHADOW_VMCS
;
1270 static inline bool cpu_has_vmx_pml(void)
1272 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1275 static inline bool cpu_has_vmx_tsc_scaling(void)
1277 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1278 SECONDARY_EXEC_TSC_SCALING
;
1281 static inline bool report_flexpriority(void)
1283 return flexpriority_enabled
;
1286 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1288 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1291 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1293 return (vmcs12
->cpu_based_vm_exec_control
&
1294 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1295 (vmcs12
->secondary_vm_exec_control
& bit
);
1298 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1300 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1303 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1305 return vmcs12
->pin_based_vm_exec_control
&
1306 PIN_BASED_VMX_PREEMPTION_TIMER
;
1309 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1311 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1314 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1316 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
) &&
1317 vmx_xsaves_supported();
1320 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1322 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1325 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1327 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1330 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1332 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1335 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1337 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1340 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1342 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1345 static inline bool is_exception(u32 intr_info
)
1347 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1348 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
1351 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1353 unsigned long exit_qualification
);
1354 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1355 struct vmcs12
*vmcs12
,
1356 u32 reason
, unsigned long qualification
);
1358 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1362 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1363 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1368 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1374 } operand
= { vpid
, 0, gva
};
1376 asm volatile (__ex(ASM_VMX_INVVPID
)
1377 /* CF==1 or ZF==1 --> rc = -1 */
1378 "; ja 1f ; ud2 ; 1:"
1379 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1382 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1386 } operand
= {eptp
, gpa
};
1388 asm volatile (__ex(ASM_VMX_INVEPT
)
1389 /* CF==1 or ZF==1 --> rc = -1 */
1390 "; ja 1f ; ud2 ; 1:\n"
1391 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1394 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1398 i
= __find_msr_index(vmx
, msr
);
1400 return &vmx
->guest_msrs
[i
];
1404 static void vmcs_clear(struct vmcs
*vmcs
)
1406 u64 phys_addr
= __pa(vmcs
);
1409 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1410 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1413 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1417 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1419 vmcs_clear(loaded_vmcs
->vmcs
);
1420 loaded_vmcs
->cpu
= -1;
1421 loaded_vmcs
->launched
= 0;
1424 static void vmcs_load(struct vmcs
*vmcs
)
1426 u64 phys_addr
= __pa(vmcs
);
1429 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1430 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1433 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1437 #ifdef CONFIG_KEXEC_CORE
1439 * This bitmap is used to indicate whether the vmclear
1440 * operation is enabled on all cpus. All disabled by
1443 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1445 static inline void crash_enable_local_vmclear(int cpu
)
1447 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1450 static inline void crash_disable_local_vmclear(int cpu
)
1452 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1455 static inline int crash_local_vmclear_enabled(int cpu
)
1457 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1460 static void crash_vmclear_local_loaded_vmcss(void)
1462 int cpu
= raw_smp_processor_id();
1463 struct loaded_vmcs
*v
;
1465 if (!crash_local_vmclear_enabled(cpu
))
1468 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1469 loaded_vmcss_on_cpu_link
)
1470 vmcs_clear(v
->vmcs
);
1473 static inline void crash_enable_local_vmclear(int cpu
) { }
1474 static inline void crash_disable_local_vmclear(int cpu
) { }
1475 #endif /* CONFIG_KEXEC_CORE */
1477 static void __loaded_vmcs_clear(void *arg
)
1479 struct loaded_vmcs
*loaded_vmcs
= arg
;
1480 int cpu
= raw_smp_processor_id();
1482 if (loaded_vmcs
->cpu
!= cpu
)
1483 return; /* vcpu migration can race with cpu offline */
1484 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1485 per_cpu(current_vmcs
, cpu
) = NULL
;
1486 crash_disable_local_vmclear(cpu
);
1487 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1490 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1491 * is before setting loaded_vmcs->vcpu to -1 which is done in
1492 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1493 * then adds the vmcs into percpu list before it is deleted.
1497 loaded_vmcs_init(loaded_vmcs
);
1498 crash_enable_local_vmclear(cpu
);
1501 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1503 int cpu
= loaded_vmcs
->cpu
;
1506 smp_call_function_single(cpu
,
1507 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1510 static inline void vpid_sync_vcpu_single(int vpid
)
1515 if (cpu_has_vmx_invvpid_single())
1516 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1519 static inline void vpid_sync_vcpu_global(void)
1521 if (cpu_has_vmx_invvpid_global())
1522 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1525 static inline void vpid_sync_context(int vpid
)
1527 if (cpu_has_vmx_invvpid_single())
1528 vpid_sync_vcpu_single(vpid
);
1530 vpid_sync_vcpu_global();
1533 static inline void ept_sync_global(void)
1535 if (cpu_has_vmx_invept_global())
1536 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1539 static inline void ept_sync_context(u64 eptp
)
1542 if (cpu_has_vmx_invept_context())
1543 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1549 static __always_inline
void vmcs_check16(unsigned long field
)
1551 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1552 "16-bit accessor invalid for 64-bit field");
1553 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1554 "16-bit accessor invalid for 64-bit high field");
1555 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1556 "16-bit accessor invalid for 32-bit high field");
1557 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1558 "16-bit accessor invalid for natural width field");
1561 static __always_inline
void vmcs_check32(unsigned long field
)
1563 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1564 "32-bit accessor invalid for 16-bit field");
1565 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1566 "32-bit accessor invalid for natural width field");
1569 static __always_inline
void vmcs_check64(unsigned long field
)
1571 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1572 "64-bit accessor invalid for 16-bit field");
1573 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1574 "64-bit accessor invalid for 64-bit high field");
1575 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1576 "64-bit accessor invalid for 32-bit field");
1577 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1578 "64-bit accessor invalid for natural width field");
1581 static __always_inline
void vmcs_checkl(unsigned long field
)
1583 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1584 "Natural width accessor invalid for 16-bit field");
1585 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1586 "Natural width accessor invalid for 64-bit field");
1587 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1588 "Natural width accessor invalid for 64-bit high field");
1589 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1590 "Natural width accessor invalid for 32-bit field");
1593 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1595 unsigned long value
;
1597 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1598 : "=a"(value
) : "d"(field
) : "cc");
1602 static __always_inline u16
vmcs_read16(unsigned long field
)
1604 vmcs_check16(field
);
1605 return __vmcs_readl(field
);
1608 static __always_inline u32
vmcs_read32(unsigned long field
)
1610 vmcs_check32(field
);
1611 return __vmcs_readl(field
);
1614 static __always_inline u64
vmcs_read64(unsigned long field
)
1616 vmcs_check64(field
);
1617 #ifdef CONFIG_X86_64
1618 return __vmcs_readl(field
);
1620 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1624 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1627 return __vmcs_readl(field
);
1630 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1632 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1633 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1637 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1641 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1642 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1643 if (unlikely(error
))
1644 vmwrite_error(field
, value
);
1647 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1649 vmcs_check16(field
);
1650 __vmcs_writel(field
, value
);
1653 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1655 vmcs_check32(field
);
1656 __vmcs_writel(field
, value
);
1659 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1661 vmcs_check64(field
);
1662 __vmcs_writel(field
, value
);
1663 #ifndef CONFIG_X86_64
1665 __vmcs_writel(field
+1, value
>> 32);
1669 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1672 __vmcs_writel(field
, value
);
1675 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1677 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1678 "vmcs_clear_bits does not support 64-bit fields");
1679 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1682 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1684 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1685 "vmcs_set_bits does not support 64-bit fields");
1686 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1689 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1691 vmx
->vm_entry_controls_shadow
= vmcs_read32(VM_ENTRY_CONTROLS
);
1694 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1696 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1697 vmx
->vm_entry_controls_shadow
= val
;
1700 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1702 if (vmx
->vm_entry_controls_shadow
!= val
)
1703 vm_entry_controls_init(vmx
, val
);
1706 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1708 return vmx
->vm_entry_controls_shadow
;
1712 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1714 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1717 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1719 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1722 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1724 vmx
->vm_exit_controls_shadow
= vmcs_read32(VM_EXIT_CONTROLS
);
1727 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1729 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1730 vmx
->vm_exit_controls_shadow
= val
;
1733 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1735 if (vmx
->vm_exit_controls_shadow
!= val
)
1736 vm_exit_controls_init(vmx
, val
);
1739 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1741 return vmx
->vm_exit_controls_shadow
;
1745 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1747 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1750 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1752 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1755 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1757 vmx
->segment_cache
.bitmask
= 0;
1760 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1764 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1766 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1767 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1768 vmx
->segment_cache
.bitmask
= 0;
1770 ret
= vmx
->segment_cache
.bitmask
& mask
;
1771 vmx
->segment_cache
.bitmask
|= mask
;
1775 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1777 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1779 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1780 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1784 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1786 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1788 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1789 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1793 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1795 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1797 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1798 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1802 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1804 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1806 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1807 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1811 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1815 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1816 (1u << NM_VECTOR
) | (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1817 if ((vcpu
->guest_debug
&
1818 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1819 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1820 eb
|= 1u << BP_VECTOR
;
1821 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1824 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1825 if (vcpu
->fpu_active
)
1826 eb
&= ~(1u << NM_VECTOR
);
1828 /* When we are running a nested L2 guest and L1 specified for it a
1829 * certain exception bitmap, we must trap the same exceptions and pass
1830 * them to L1. When running L2, we will only handle the exceptions
1831 * specified above if L1 did not want them.
1833 if (is_guest_mode(vcpu
))
1834 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1836 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1839 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1840 unsigned long entry
, unsigned long exit
)
1842 vm_entry_controls_clearbit(vmx
, entry
);
1843 vm_exit_controls_clearbit(vmx
, exit
);
1846 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1849 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1853 if (cpu_has_load_ia32_efer
) {
1854 clear_atomic_switch_msr_special(vmx
,
1855 VM_ENTRY_LOAD_IA32_EFER
,
1856 VM_EXIT_LOAD_IA32_EFER
);
1860 case MSR_CORE_PERF_GLOBAL_CTRL
:
1861 if (cpu_has_load_perf_global_ctrl
) {
1862 clear_atomic_switch_msr_special(vmx
,
1863 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1864 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1870 for (i
= 0; i
< m
->nr
; ++i
)
1871 if (m
->guest
[i
].index
== msr
)
1877 m
->guest
[i
] = m
->guest
[m
->nr
];
1878 m
->host
[i
] = m
->host
[m
->nr
];
1879 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1880 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1883 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1884 unsigned long entry
, unsigned long exit
,
1885 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1886 u64 guest_val
, u64 host_val
)
1888 vmcs_write64(guest_val_vmcs
, guest_val
);
1889 vmcs_write64(host_val_vmcs
, host_val
);
1890 vm_entry_controls_setbit(vmx
, entry
);
1891 vm_exit_controls_setbit(vmx
, exit
);
1894 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1895 u64 guest_val
, u64 host_val
)
1898 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1902 if (cpu_has_load_ia32_efer
) {
1903 add_atomic_switch_msr_special(vmx
,
1904 VM_ENTRY_LOAD_IA32_EFER
,
1905 VM_EXIT_LOAD_IA32_EFER
,
1908 guest_val
, host_val
);
1912 case MSR_CORE_PERF_GLOBAL_CTRL
:
1913 if (cpu_has_load_perf_global_ctrl
) {
1914 add_atomic_switch_msr_special(vmx
,
1915 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1916 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1917 GUEST_IA32_PERF_GLOBAL_CTRL
,
1918 HOST_IA32_PERF_GLOBAL_CTRL
,
1919 guest_val
, host_val
);
1923 case MSR_IA32_PEBS_ENABLE
:
1924 /* PEBS needs a quiescent period after being disabled (to write
1925 * a record). Disabling PEBS through VMX MSR swapping doesn't
1926 * provide that period, so a CPU could write host's record into
1929 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
1932 for (i
= 0; i
< m
->nr
; ++i
)
1933 if (m
->guest
[i
].index
== msr
)
1936 if (i
== NR_AUTOLOAD_MSRS
) {
1937 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1938 "Can't add msr %x\n", msr
);
1940 } else if (i
== m
->nr
) {
1942 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1943 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1946 m
->guest
[i
].index
= msr
;
1947 m
->guest
[i
].value
= guest_val
;
1948 m
->host
[i
].index
= msr
;
1949 m
->host
[i
].value
= host_val
;
1952 static void reload_tss(void)
1955 * VT restores TR but not its size. Useless.
1957 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1958 struct desc_struct
*descs
;
1960 descs
= (void *)gdt
->address
;
1961 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1965 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1967 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
1968 u64 ignore_bits
= 0;
1972 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
1973 * host CPUID is more efficient than testing guest CPUID
1974 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
1976 if (boot_cpu_has(X86_FEATURE_SMEP
))
1977 guest_efer
|= EFER_NX
;
1978 else if (!(guest_efer
& EFER_NX
))
1979 ignore_bits
|= EFER_NX
;
1983 * LMA and LME handled by hardware; SCE meaningless outside long mode.
1985 ignore_bits
|= EFER_SCE
;
1986 #ifdef CONFIG_X86_64
1987 ignore_bits
|= EFER_LMA
| EFER_LME
;
1988 /* SCE is meaningful only in long mode on Intel */
1989 if (guest_efer
& EFER_LMA
)
1990 ignore_bits
&= ~(u64
)EFER_SCE
;
1993 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1996 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1997 * On CPUs that support "load IA32_EFER", always switch EFER
1998 * atomically, since it's faster than switching it manually.
2000 if (cpu_has_load_ia32_efer
||
2001 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
2002 if (!(guest_efer
& EFER_LMA
))
2003 guest_efer
&= ~EFER_LME
;
2004 if (guest_efer
!= host_efer
)
2005 add_atomic_switch_msr(vmx
, MSR_EFER
,
2006 guest_efer
, host_efer
);
2009 guest_efer
&= ~ignore_bits
;
2010 guest_efer
|= host_efer
& ignore_bits
;
2012 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
2013 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
2019 static unsigned long segment_base(u16 selector
)
2021 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
2022 struct desc_struct
*d
;
2023 unsigned long table_base
;
2026 if (!(selector
& ~3))
2029 table_base
= gdt
->address
;
2031 if (selector
& 4) { /* from ldt */
2032 u16 ldt_selector
= kvm_read_ldt();
2034 if (!(ldt_selector
& ~3))
2037 table_base
= segment_base(ldt_selector
);
2039 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
2040 v
= get_desc_base(d
);
2041 #ifdef CONFIG_X86_64
2042 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
2043 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
2048 static inline unsigned long kvm_read_tr_base(void)
2051 asm("str %0" : "=g"(tr
));
2052 return segment_base(tr
);
2055 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
2057 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2060 if (vmx
->host_state
.loaded
)
2063 vmx
->host_state
.loaded
= 1;
2065 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2066 * allow segment selectors with cpl > 0 or ti == 1.
2068 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
2069 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
2070 savesegment(fs
, vmx
->host_state
.fs_sel
);
2071 if (!(vmx
->host_state
.fs_sel
& 7)) {
2072 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
2073 vmx
->host_state
.fs_reload_needed
= 0;
2075 vmcs_write16(HOST_FS_SELECTOR
, 0);
2076 vmx
->host_state
.fs_reload_needed
= 1;
2078 savesegment(gs
, vmx
->host_state
.gs_sel
);
2079 if (!(vmx
->host_state
.gs_sel
& 7))
2080 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
2082 vmcs_write16(HOST_GS_SELECTOR
, 0);
2083 vmx
->host_state
.gs_ldt_reload_needed
= 1;
2086 #ifdef CONFIG_X86_64
2087 savesegment(ds
, vmx
->host_state
.ds_sel
);
2088 savesegment(es
, vmx
->host_state
.es_sel
);
2091 #ifdef CONFIG_X86_64
2092 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
2093 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
2095 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
2096 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
2099 #ifdef CONFIG_X86_64
2100 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2101 if (is_long_mode(&vmx
->vcpu
))
2102 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2104 if (boot_cpu_has(X86_FEATURE_MPX
))
2105 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2106 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2107 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2108 vmx
->guest_msrs
[i
].data
,
2109 vmx
->guest_msrs
[i
].mask
);
2112 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
2114 if (!vmx
->host_state
.loaded
)
2117 ++vmx
->vcpu
.stat
.host_state_reload
;
2118 vmx
->host_state
.loaded
= 0;
2119 #ifdef CONFIG_X86_64
2120 if (is_long_mode(&vmx
->vcpu
))
2121 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2123 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2124 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2125 #ifdef CONFIG_X86_64
2126 load_gs_index(vmx
->host_state
.gs_sel
);
2128 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2131 if (vmx
->host_state
.fs_reload_needed
)
2132 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2133 #ifdef CONFIG_X86_64
2134 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2135 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2136 loadsegment(es
, vmx
->host_state
.es_sel
);
2140 #ifdef CONFIG_X86_64
2141 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2143 if (vmx
->host_state
.msr_host_bndcfgs
)
2144 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2146 * If the FPU is not active (through the host task or
2147 * the guest vcpu), then restore the cr0.TS bit.
2149 if (!fpregs_active() && !vmx
->vcpu
.guest_fpu_loaded
)
2151 load_gdt(this_cpu_ptr(&host_gdt
));
2154 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2157 __vmx_load_host_state(vmx
);
2161 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2163 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2164 struct pi_desc old
, new;
2167 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2168 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2169 !kvm_vcpu_apicv_active(vcpu
))
2173 old
.control
= new.control
= pi_desc
->control
;
2176 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2177 * are two possible cases:
2178 * 1. After running 'pre_block', context switch
2179 * happened. For this case, 'sn' was set in
2180 * vmx_vcpu_put(), so we need to clear it here.
2181 * 2. After running 'pre_block', we were blocked,
2182 * and woken up by some other guy. For this case,
2183 * we don't need to do anything, 'pi_post_block'
2184 * will do everything for us. However, we cannot
2185 * check whether it is case #1 or case #2 here
2186 * (maybe, not needed), so we also clear sn here,
2187 * I think it is not a big deal.
2189 if (pi_desc
->nv
!= POSTED_INTR_WAKEUP_VECTOR
) {
2190 if (vcpu
->cpu
!= cpu
) {
2191 dest
= cpu_physical_id(cpu
);
2193 if (x2apic_enabled())
2196 new.ndst
= (dest
<< 8) & 0xFF00;
2199 /* set 'NV' to 'notification vector' */
2200 new.nv
= POSTED_INTR_VECTOR
;
2203 /* Allow posting non-urgent interrupts */
2205 } while (cmpxchg(&pi_desc
->control
, old
.control
,
2206 new.control
) != old
.control
);
2209 static void decache_tsc_multiplier(struct vcpu_vmx
*vmx
)
2211 vmx
->current_tsc_ratio
= vmx
->vcpu
.arch
.tsc_scaling_ratio
;
2212 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2216 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2217 * vcpu mutex is already taken.
2219 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2221 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2222 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2223 bool already_loaded
= vmx
->loaded_vmcs
->cpu
== cpu
;
2226 kvm_cpu_vmxon(phys_addr
);
2227 else if (!already_loaded
)
2228 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2230 if (!already_loaded
) {
2231 local_irq_disable();
2232 crash_disable_local_vmclear(cpu
);
2235 * Read loaded_vmcs->cpu should be before fetching
2236 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2237 * See the comments in __loaded_vmcs_clear().
2241 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2242 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2243 crash_enable_local_vmclear(cpu
);
2247 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2248 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2249 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2252 if (!already_loaded
) {
2253 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
2254 unsigned long sysenter_esp
;
2256 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2259 * Linux uses per-cpu TSS and GDT, so set these when switching
2262 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
2263 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
2265 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2266 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2268 vmx
->loaded_vmcs
->cpu
= cpu
;
2271 /* Setup TSC multiplier */
2272 if (kvm_has_tsc_control
&&
2273 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
)
2274 decache_tsc_multiplier(vmx
);
2276 vmx_vcpu_pi_load(vcpu
, cpu
);
2277 vmx
->host_pkru
= read_pkru();
2280 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2282 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2284 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2285 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2286 !kvm_vcpu_apicv_active(vcpu
))
2289 /* Set SN when the vCPU is preempted */
2290 if (vcpu
->preempted
)
2294 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2296 vmx_vcpu_pi_put(vcpu
);
2298 __vmx_load_host_state(to_vmx(vcpu
));
2299 if (!vmm_exclusive
) {
2300 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
2306 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
2310 if (vcpu
->fpu_active
)
2312 vcpu
->fpu_active
= 1;
2313 cr0
= vmcs_readl(GUEST_CR0
);
2314 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
2315 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
2316 vmcs_writel(GUEST_CR0
, cr0
);
2317 update_exception_bitmap(vcpu
);
2318 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
2319 if (is_guest_mode(vcpu
))
2320 vcpu
->arch
.cr0_guest_owned_bits
&=
2321 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
2322 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
2325 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2328 * Return the cr0 value that a nested guest would read. This is a combination
2329 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2330 * its hypervisor (cr0_read_shadow).
2332 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2334 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2335 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2337 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2339 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2340 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2343 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
2345 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2346 * set this *before* calling this function.
2348 vmx_decache_cr0_guest_bits(vcpu
);
2349 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
2350 update_exception_bitmap(vcpu
);
2351 vcpu
->arch
.cr0_guest_owned_bits
= 0;
2352 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
2353 if (is_guest_mode(vcpu
)) {
2355 * L1's specified read shadow might not contain the TS bit,
2356 * so now that we turned on shadowing of this bit, we need to
2357 * set this bit of the shadow. Like in nested_vmx_run we need
2358 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2359 * up-to-date here because we just decached cr0.TS (and we'll
2360 * only update vmcs12->guest_cr0 on nested exit).
2362 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2363 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
2364 (vcpu
->arch
.cr0
& X86_CR0_TS
);
2365 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
2367 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
2370 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2372 unsigned long rflags
, save_rflags
;
2374 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2375 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2376 rflags
= vmcs_readl(GUEST_RFLAGS
);
2377 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2378 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2379 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2380 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2382 to_vmx(vcpu
)->rflags
= rflags
;
2384 return to_vmx(vcpu
)->rflags
;
2387 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2389 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2390 to_vmx(vcpu
)->rflags
= rflags
;
2391 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2392 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2393 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2395 vmcs_writel(GUEST_RFLAGS
, rflags
);
2398 static u32
vmx_get_pkru(struct kvm_vcpu
*vcpu
)
2400 return to_vmx(vcpu
)->guest_pkru
;
2403 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2405 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2408 if (interruptibility
& GUEST_INTR_STATE_STI
)
2409 ret
|= KVM_X86_SHADOW_INT_STI
;
2410 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2411 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2416 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2418 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2419 u32 interruptibility
= interruptibility_old
;
2421 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2423 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2424 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2425 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2426 interruptibility
|= GUEST_INTR_STATE_STI
;
2428 if ((interruptibility
!= interruptibility_old
))
2429 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2432 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2436 rip
= kvm_rip_read(vcpu
);
2437 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2438 kvm_rip_write(vcpu
, rip
);
2440 /* skipping an emulated instruction also counts */
2441 vmx_set_interrupt_shadow(vcpu
, 0);
2445 * KVM wants to inject page-faults which it got to the guest. This function
2446 * checks whether in a nested guest, we need to inject them to L1 or L2.
2448 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
2450 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2452 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
2455 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
2456 vmcs_read32(VM_EXIT_INTR_INFO
),
2457 vmcs_readl(EXIT_QUALIFICATION
));
2461 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
2462 bool has_error_code
, u32 error_code
,
2465 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2466 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2468 if (!reinject
&& is_guest_mode(vcpu
) &&
2469 nested_vmx_check_exception(vcpu
, nr
))
2472 if (has_error_code
) {
2473 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2474 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2477 if (vmx
->rmode
.vm86_active
) {
2479 if (kvm_exception_is_soft(nr
))
2480 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2481 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2482 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2486 if (kvm_exception_is_soft(nr
)) {
2487 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2488 vmx
->vcpu
.arch
.event_exit_inst_len
);
2489 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2491 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2493 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2496 static bool vmx_rdtscp_supported(void)
2498 return cpu_has_vmx_rdtscp();
2501 static bool vmx_invpcid_supported(void)
2503 return cpu_has_vmx_invpcid() && enable_ept
;
2507 * Swap MSR entry in host/guest MSR entry array.
2509 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2511 struct shared_msr_entry tmp
;
2513 tmp
= vmx
->guest_msrs
[to
];
2514 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2515 vmx
->guest_msrs
[from
] = tmp
;
2518 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2520 unsigned long *msr_bitmap
;
2522 if (is_guest_mode(vcpu
))
2523 msr_bitmap
= to_vmx(vcpu
)->nested
.msr_bitmap
;
2524 else if (cpu_has_secondary_exec_ctrls() &&
2525 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
2526 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
2527 if (is_long_mode(vcpu
))
2528 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2530 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2532 if (is_long_mode(vcpu
))
2533 msr_bitmap
= vmx_msr_bitmap_longmode
;
2535 msr_bitmap
= vmx_msr_bitmap_legacy
;
2538 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2542 * Set up the vmcs to automatically save and restore system
2543 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2544 * mode, as fiddling with msrs is very expensive.
2546 static void setup_msrs(struct vcpu_vmx
*vmx
)
2548 int save_nmsrs
, index
;
2551 #ifdef CONFIG_X86_64
2552 if (is_long_mode(&vmx
->vcpu
)) {
2553 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2555 move_msr_up(vmx
, index
, save_nmsrs
++);
2556 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2558 move_msr_up(vmx
, index
, save_nmsrs
++);
2559 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2561 move_msr_up(vmx
, index
, save_nmsrs
++);
2562 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2563 if (index
>= 0 && guest_cpuid_has_rdtscp(&vmx
->vcpu
))
2564 move_msr_up(vmx
, index
, save_nmsrs
++);
2566 * MSR_STAR is only needed on long mode guests, and only
2567 * if efer.sce is enabled.
2569 index
= __find_msr_index(vmx
, MSR_STAR
);
2570 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2571 move_msr_up(vmx
, index
, save_nmsrs
++);
2574 index
= __find_msr_index(vmx
, MSR_EFER
);
2575 if (index
>= 0 && update_transition_efer(vmx
, index
))
2576 move_msr_up(vmx
, index
, save_nmsrs
++);
2578 vmx
->save_nmsrs
= save_nmsrs
;
2580 if (cpu_has_vmx_msr_bitmap())
2581 vmx_set_msr_bitmap(&vmx
->vcpu
);
2585 * reads and returns guest's timestamp counter "register"
2586 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2587 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2589 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2591 u64 host_tsc
, tsc_offset
;
2594 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2595 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2599 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2600 * counter, even if a nested guest (L2) is currently running.
2602 static u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
2606 tsc_offset
= is_guest_mode(vcpu
) ?
2607 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
2608 vmcs_read64(TSC_OFFSET
);
2609 return host_tsc
+ tsc_offset
;
2612 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
2614 return vmcs_read64(TSC_OFFSET
);
2618 * writes 'offset' into guest's timestamp counter offset register
2620 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2622 if (is_guest_mode(vcpu
)) {
2624 * We're here if L1 chose not to trap WRMSR to TSC. According
2625 * to the spec, this should set L1's TSC; The offset that L1
2626 * set for L2 remains unchanged, and still needs to be added
2627 * to the newly set TSC to get L2's TSC.
2629 struct vmcs12
*vmcs12
;
2630 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
2631 /* recalculate vmcs02.TSC_OFFSET: */
2632 vmcs12
= get_vmcs12(vcpu
);
2633 vmcs_write64(TSC_OFFSET
, offset
+
2634 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2635 vmcs12
->tsc_offset
: 0));
2637 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2638 vmcs_read64(TSC_OFFSET
), offset
);
2639 vmcs_write64(TSC_OFFSET
, offset
);
2643 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu
*vcpu
, s64 adjustment
)
2645 u64 offset
= vmcs_read64(TSC_OFFSET
);
2647 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
2648 if (is_guest_mode(vcpu
)) {
2649 /* Even when running L2, the adjustment needs to apply to L1 */
2650 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
2652 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
, offset
,
2653 offset
+ adjustment
);
2656 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2658 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2659 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2663 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2664 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2665 * all guests if the "nested" module option is off, and can also be disabled
2666 * for a single guest by disabling its VMX cpuid bit.
2668 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2670 return nested
&& guest_cpuid_has_vmx(vcpu
);
2674 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2675 * returned for the various VMX controls MSRs when nested VMX is enabled.
2676 * The same values should also be used to verify that vmcs12 control fields are
2677 * valid during nested entry from L1 to L2.
2678 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2679 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2680 * bit in the high half is on if the corresponding bit in the control field
2681 * may be on. See also vmx_control_verify().
2683 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2686 * Note that as a general rule, the high half of the MSRs (bits in
2687 * the control fields which may be 1) should be initialized by the
2688 * intersection of the underlying hardware's MSR (i.e., features which
2689 * can be supported) and the list of features we want to expose -
2690 * because they are known to be properly supported in our code.
2691 * Also, usually, the low half of the MSRs (bits which must be 1) can
2692 * be set to 0, meaning that L1 may turn off any of these bits. The
2693 * reason is that if one of these bits is necessary, it will appear
2694 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2695 * fields of vmcs01 and vmcs02, will turn these bits off - and
2696 * nested_vmx_exit_handled() will not pass related exits to L1.
2697 * These rules have exceptions below.
2700 /* pin-based controls */
2701 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2702 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2703 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2704 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2705 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2706 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2707 PIN_BASED_EXT_INTR_MASK
|
2708 PIN_BASED_NMI_EXITING
|
2709 PIN_BASED_VIRTUAL_NMIS
;
2710 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2711 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2712 PIN_BASED_VMX_PREEMPTION_TIMER
;
2713 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2714 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2715 PIN_BASED_POSTED_INTR
;
2718 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2719 vmx
->nested
.nested_vmx_exit_ctls_low
,
2720 vmx
->nested
.nested_vmx_exit_ctls_high
);
2721 vmx
->nested
.nested_vmx_exit_ctls_low
=
2722 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2724 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2725 #ifdef CONFIG_X86_64
2726 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2728 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2729 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2730 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2731 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2732 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2734 if (kvm_mpx_supported())
2735 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2737 /* We support free control of debug control saving. */
2738 vmx
->nested
.nested_vmx_true_exit_ctls_low
=
2739 vmx
->nested
.nested_vmx_exit_ctls_low
&
2740 ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2742 /* entry controls */
2743 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2744 vmx
->nested
.nested_vmx_entry_ctls_low
,
2745 vmx
->nested
.nested_vmx_entry_ctls_high
);
2746 vmx
->nested
.nested_vmx_entry_ctls_low
=
2747 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2748 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2749 #ifdef CONFIG_X86_64
2750 VM_ENTRY_IA32E_MODE
|
2752 VM_ENTRY_LOAD_IA32_PAT
;
2753 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2754 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2755 if (kvm_mpx_supported())
2756 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2758 /* We support free control of debug control loading. */
2759 vmx
->nested
.nested_vmx_true_entry_ctls_low
=
2760 vmx
->nested
.nested_vmx_entry_ctls_low
&
2761 ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2763 /* cpu-based controls */
2764 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2765 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2766 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2767 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2768 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2769 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2770 CPU_BASED_VIRTUAL_INTR_PENDING
|
2771 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2772 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2773 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2774 CPU_BASED_CR3_STORE_EXITING
|
2775 #ifdef CONFIG_X86_64
2776 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2778 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2779 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2780 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2781 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2782 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2784 * We can allow some features even when not supported by the
2785 * hardware. For example, L1 can specify an MSR bitmap - and we
2786 * can use it to avoid exits to L1 - even when L0 runs L2
2787 * without MSR bitmaps.
2789 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2790 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2791 CPU_BASED_USE_MSR_BITMAPS
;
2793 /* We support free control of CR3 access interception. */
2794 vmx
->nested
.nested_vmx_true_procbased_ctls_low
=
2795 vmx
->nested
.nested_vmx_procbased_ctls_low
&
2796 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2798 /* secondary cpu-based controls */
2799 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2800 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2801 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2802 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2803 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2804 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2805 SECONDARY_EXEC_RDTSCP
|
2806 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2807 SECONDARY_EXEC_ENABLE_VPID
|
2808 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2809 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2810 SECONDARY_EXEC_WBINVD_EXITING
|
2811 SECONDARY_EXEC_XSAVES
;
2814 /* nested EPT: emulate EPT also to L1 */
2815 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2816 SECONDARY_EXEC_ENABLE_EPT
;
2817 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2818 VMX_EPTP_WB_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2820 if (cpu_has_vmx_ept_execute_only())
2821 vmx
->nested
.nested_vmx_ept_caps
|=
2822 VMX_EPT_EXECUTE_ONLY_BIT
;
2823 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2824 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2825 VMX_EPT_EXTENT_CONTEXT_BIT
;
2827 vmx
->nested
.nested_vmx_ept_caps
= 0;
2830 * Old versions of KVM use the single-context version without
2831 * checking for support, so declare that it is supported even
2832 * though it is treated as global context. The alternative is
2833 * not failing the single-context invvpid, and it is worse.
2836 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2837 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
|
2838 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
2840 vmx
->nested
.nested_vmx_vpid_caps
= 0;
2842 if (enable_unrestricted_guest
)
2843 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2844 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2846 /* miscellaneous data */
2847 rdmsr(MSR_IA32_VMX_MISC
,
2848 vmx
->nested
.nested_vmx_misc_low
,
2849 vmx
->nested
.nested_vmx_misc_high
);
2850 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2851 vmx
->nested
.nested_vmx_misc_low
|=
2852 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2853 VMX_MISC_ACTIVITY_HLT
;
2854 vmx
->nested
.nested_vmx_misc_high
= 0;
2857 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2860 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2862 return ((control
& high
) | low
) == control
;
2865 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2867 return low
| ((u64
)high
<< 32);
2870 /* Returns 0 on success, non-0 otherwise. */
2871 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2873 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2875 switch (msr_index
) {
2876 case MSR_IA32_VMX_BASIC
:
2878 * This MSR reports some information about VMX support. We
2879 * should return information about the VMX we emulate for the
2880 * guest, and the VMCS structure we give it - not about the
2881 * VMX support of the underlying hardware.
2883 *pdata
= VMCS12_REVISION
| VMX_BASIC_TRUE_CTLS
|
2884 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2885 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2886 if (cpu_has_vmx_basic_inout())
2887 *pdata
|= VMX_BASIC_INOUT
;
2889 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2890 case MSR_IA32_VMX_PINBASED_CTLS
:
2891 *pdata
= vmx_control_msr(
2892 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2893 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2895 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2896 *pdata
= vmx_control_msr(
2897 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
2898 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2900 case MSR_IA32_VMX_PROCBASED_CTLS
:
2901 *pdata
= vmx_control_msr(
2902 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2903 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2905 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2906 *pdata
= vmx_control_msr(
2907 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
2908 vmx
->nested
.nested_vmx_exit_ctls_high
);
2910 case MSR_IA32_VMX_EXIT_CTLS
:
2911 *pdata
= vmx_control_msr(
2912 vmx
->nested
.nested_vmx_exit_ctls_low
,
2913 vmx
->nested
.nested_vmx_exit_ctls_high
);
2915 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2916 *pdata
= vmx_control_msr(
2917 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
2918 vmx
->nested
.nested_vmx_entry_ctls_high
);
2920 case MSR_IA32_VMX_ENTRY_CTLS
:
2921 *pdata
= vmx_control_msr(
2922 vmx
->nested
.nested_vmx_entry_ctls_low
,
2923 vmx
->nested
.nested_vmx_entry_ctls_high
);
2925 case MSR_IA32_VMX_MISC
:
2926 *pdata
= vmx_control_msr(
2927 vmx
->nested
.nested_vmx_misc_low
,
2928 vmx
->nested
.nested_vmx_misc_high
);
2931 * These MSRs specify bits which the guest must keep fixed (on or off)
2932 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2933 * We picked the standard core2 setting.
2935 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2936 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2937 case MSR_IA32_VMX_CR0_FIXED0
:
2938 *pdata
= VMXON_CR0_ALWAYSON
;
2940 case MSR_IA32_VMX_CR0_FIXED1
:
2943 case MSR_IA32_VMX_CR4_FIXED0
:
2944 *pdata
= VMXON_CR4_ALWAYSON
;
2946 case MSR_IA32_VMX_CR4_FIXED1
:
2949 case MSR_IA32_VMX_VMCS_ENUM
:
2950 *pdata
= 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2952 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2953 *pdata
= vmx_control_msr(
2954 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2955 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2957 case MSR_IA32_VMX_EPT_VPID_CAP
:
2958 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
2959 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
2968 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
2971 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
2973 return !(val
& ~valid_bits
);
2977 * Reads an msr value (of 'msr_index') into 'pdata'.
2978 * Returns 0 on success, non-0 otherwise.
2979 * Assumes vcpu_load() was already called.
2981 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2983 struct shared_msr_entry
*msr
;
2985 switch (msr_info
->index
) {
2986 #ifdef CONFIG_X86_64
2988 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
2991 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
2993 case MSR_KERNEL_GS_BASE
:
2994 vmx_load_host_state(to_vmx(vcpu
));
2995 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2999 return kvm_get_msr_common(vcpu
, msr_info
);
3001 msr_info
->data
= guest_read_tsc(vcpu
);
3003 case MSR_IA32_SYSENTER_CS
:
3004 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
3006 case MSR_IA32_SYSENTER_EIP
:
3007 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
3009 case MSR_IA32_SYSENTER_ESP
:
3010 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
3012 case MSR_IA32_BNDCFGS
:
3013 if (!kvm_mpx_supported())
3015 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
3017 case MSR_IA32_MCG_EXT_CTL
:
3018 if (!msr_info
->host_initiated
&&
3019 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3020 FEATURE_CONTROL_LMCE
))
3022 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
3024 case MSR_IA32_FEATURE_CONTROL
:
3025 msr_info
->data
= to_vmx(vcpu
)->msr_ia32_feature_control
;
3027 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3028 if (!nested_vmx_allowed(vcpu
))
3030 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
3032 if (!vmx_xsaves_supported())
3034 msr_info
->data
= vcpu
->arch
.ia32_xss
;
3037 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3039 /* Otherwise falls through */
3041 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
3043 msr_info
->data
= msr
->data
;
3046 return kvm_get_msr_common(vcpu
, msr_info
);
3052 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
3055 * Writes msr value into into the appropriate "register".
3056 * Returns 0 on success, non-0 otherwise.
3057 * Assumes vcpu_load() was already called.
3059 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3061 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3062 struct shared_msr_entry
*msr
;
3064 u32 msr_index
= msr_info
->index
;
3065 u64 data
= msr_info
->data
;
3067 switch (msr_index
) {
3069 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3071 #ifdef CONFIG_X86_64
3073 vmx_segment_cache_clear(vmx
);
3074 vmcs_writel(GUEST_FS_BASE
, data
);
3077 vmx_segment_cache_clear(vmx
);
3078 vmcs_writel(GUEST_GS_BASE
, data
);
3080 case MSR_KERNEL_GS_BASE
:
3081 vmx_load_host_state(vmx
);
3082 vmx
->msr_guest_kernel_gs_base
= data
;
3085 case MSR_IA32_SYSENTER_CS
:
3086 vmcs_write32(GUEST_SYSENTER_CS
, data
);
3088 case MSR_IA32_SYSENTER_EIP
:
3089 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
3091 case MSR_IA32_SYSENTER_ESP
:
3092 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
3094 case MSR_IA32_BNDCFGS
:
3095 if (!kvm_mpx_supported())
3097 vmcs_write64(GUEST_BNDCFGS
, data
);
3100 kvm_write_tsc(vcpu
, msr_info
);
3102 case MSR_IA32_CR_PAT
:
3103 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3104 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
3106 vmcs_write64(GUEST_IA32_PAT
, data
);
3107 vcpu
->arch
.pat
= data
;
3110 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3112 case MSR_IA32_TSC_ADJUST
:
3113 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3115 case MSR_IA32_MCG_EXT_CTL
:
3116 if ((!msr_info
->host_initiated
&&
3117 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3118 FEATURE_CONTROL_LMCE
)) ||
3119 (data
& ~MCG_EXT_CTL_LMCE_EN
))
3121 vcpu
->arch
.mcg_ext_ctl
= data
;
3123 case MSR_IA32_FEATURE_CONTROL
:
3124 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
3125 (to_vmx(vcpu
)->msr_ia32_feature_control
&
3126 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
3128 vmx
->msr_ia32_feature_control
= data
;
3129 if (msr_info
->host_initiated
&& data
== 0)
3130 vmx_leave_nested(vcpu
);
3132 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3133 return 1; /* they are read-only */
3135 if (!vmx_xsaves_supported())
3138 * The only supported bit as of Skylake is bit 8, but
3139 * it is not supported on KVM.
3143 vcpu
->arch
.ia32_xss
= data
;
3144 if (vcpu
->arch
.ia32_xss
!= host_xss
)
3145 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
3146 vcpu
->arch
.ia32_xss
, host_xss
);
3148 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
3151 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3153 /* Check reserved bit, higher 32 bits should be zero */
3154 if ((data
>> 32) != 0)
3156 /* Otherwise falls through */
3158 msr
= find_msr_entry(vmx
, msr_index
);
3160 u64 old_msr_data
= msr
->data
;
3162 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3164 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3168 msr
->data
= old_msr_data
;
3172 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3178 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3180 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3183 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3186 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3188 case VCPU_EXREG_PDPTR
:
3190 ept_save_pdptrs(vcpu
);
3197 static __init
int cpu_has_kvm_support(void)
3199 return cpu_has_vmx();
3202 static __init
int vmx_disabled_by_bios(void)
3206 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3207 if (msr
& FEATURE_CONTROL_LOCKED
) {
3208 /* launched w/ TXT and VMX disabled */
3209 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3212 /* launched w/o TXT and VMX only enabled w/ TXT */
3213 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3214 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3215 && !tboot_enabled()) {
3216 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3217 "activate TXT before enabling KVM\n");
3220 /* launched w/o TXT and VMX disabled */
3221 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3222 && !tboot_enabled())
3229 static void kvm_cpu_vmxon(u64 addr
)
3231 intel_pt_handle_vmx(1);
3233 asm volatile (ASM_VMX_VMXON_RAX
3234 : : "a"(&addr
), "m"(addr
)
3238 static int hardware_enable(void)
3240 int cpu
= raw_smp_processor_id();
3241 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3244 if (cr4_read_shadow() & X86_CR4_VMXE
)
3247 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3248 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3249 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3252 * Now we can enable the vmclear operation in kdump
3253 * since the loaded_vmcss_on_cpu list on this cpu
3254 * has been initialized.
3256 * Though the cpu is not in VMX operation now, there
3257 * is no problem to enable the vmclear operation
3258 * for the loaded_vmcss_on_cpu list is empty!
3260 crash_enable_local_vmclear(cpu
);
3262 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3264 test_bits
= FEATURE_CONTROL_LOCKED
;
3265 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3266 if (tboot_enabled())
3267 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3269 if ((old
& test_bits
) != test_bits
) {
3270 /* enable and lock */
3271 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3273 cr4_set_bits(X86_CR4_VMXE
);
3275 if (vmm_exclusive
) {
3276 kvm_cpu_vmxon(phys_addr
);
3280 native_store_gdt(this_cpu_ptr(&host_gdt
));
3285 static void vmclear_local_loaded_vmcss(void)
3287 int cpu
= raw_smp_processor_id();
3288 struct loaded_vmcs
*v
, *n
;
3290 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3291 loaded_vmcss_on_cpu_link
)
3292 __loaded_vmcs_clear(v
);
3296 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3299 static void kvm_cpu_vmxoff(void)
3301 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3303 intel_pt_handle_vmx(0);
3306 static void hardware_disable(void)
3308 if (vmm_exclusive
) {
3309 vmclear_local_loaded_vmcss();
3312 cr4_clear_bits(X86_CR4_VMXE
);
3315 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3316 u32 msr
, u32
*result
)
3318 u32 vmx_msr_low
, vmx_msr_high
;
3319 u32 ctl
= ctl_min
| ctl_opt
;
3321 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3323 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3324 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3326 /* Ensure minimum (required) set of control bits are supported. */
3334 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3336 u32 vmx_msr_low
, vmx_msr_high
;
3338 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3339 return vmx_msr_high
& ctl
;
3342 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3344 u32 vmx_msr_low
, vmx_msr_high
;
3345 u32 min
, opt
, min2
, opt2
;
3346 u32 _pin_based_exec_control
= 0;
3347 u32 _cpu_based_exec_control
= 0;
3348 u32 _cpu_based_2nd_exec_control
= 0;
3349 u32 _vmexit_control
= 0;
3350 u32 _vmentry_control
= 0;
3352 min
= CPU_BASED_HLT_EXITING
|
3353 #ifdef CONFIG_X86_64
3354 CPU_BASED_CR8_LOAD_EXITING
|
3355 CPU_BASED_CR8_STORE_EXITING
|
3357 CPU_BASED_CR3_LOAD_EXITING
|
3358 CPU_BASED_CR3_STORE_EXITING
|
3359 CPU_BASED_USE_IO_BITMAPS
|
3360 CPU_BASED_MOV_DR_EXITING
|
3361 CPU_BASED_USE_TSC_OFFSETING
|
3362 CPU_BASED_MWAIT_EXITING
|
3363 CPU_BASED_MONITOR_EXITING
|
3364 CPU_BASED_INVLPG_EXITING
|
3365 CPU_BASED_RDPMC_EXITING
;
3367 opt
= CPU_BASED_TPR_SHADOW
|
3368 CPU_BASED_USE_MSR_BITMAPS
|
3369 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3370 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3371 &_cpu_based_exec_control
) < 0)
3373 #ifdef CONFIG_X86_64
3374 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3375 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3376 ~CPU_BASED_CR8_STORE_EXITING
;
3378 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3380 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3381 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3382 SECONDARY_EXEC_WBINVD_EXITING
|
3383 SECONDARY_EXEC_ENABLE_VPID
|
3384 SECONDARY_EXEC_ENABLE_EPT
|
3385 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3386 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3387 SECONDARY_EXEC_RDTSCP
|
3388 SECONDARY_EXEC_ENABLE_INVPCID
|
3389 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3390 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3391 SECONDARY_EXEC_SHADOW_VMCS
|
3392 SECONDARY_EXEC_XSAVES
|
3393 SECONDARY_EXEC_ENABLE_PML
|
3394 SECONDARY_EXEC_TSC_SCALING
;
3395 if (adjust_vmx_controls(min2
, opt2
,
3396 MSR_IA32_VMX_PROCBASED_CTLS2
,
3397 &_cpu_based_2nd_exec_control
) < 0)
3400 #ifndef CONFIG_X86_64
3401 if (!(_cpu_based_2nd_exec_control
&
3402 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3403 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3406 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3407 _cpu_based_2nd_exec_control
&= ~(
3408 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3409 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3410 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3412 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3413 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3415 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3416 CPU_BASED_CR3_STORE_EXITING
|
3417 CPU_BASED_INVLPG_EXITING
);
3418 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3419 vmx_capability
.ept
, vmx_capability
.vpid
);
3422 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
3423 #ifdef CONFIG_X86_64
3424 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3426 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3427 VM_EXIT_CLEAR_BNDCFGS
;
3428 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3429 &_vmexit_control
) < 0)
3432 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
3433 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
|
3434 PIN_BASED_VMX_PREEMPTION_TIMER
;
3435 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3436 &_pin_based_exec_control
) < 0)
3439 if (cpu_has_broken_vmx_preemption_timer())
3440 _pin_based_exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
3441 if (!(_cpu_based_2nd_exec_control
&
3442 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
3443 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3445 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3446 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3447 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3448 &_vmentry_control
) < 0)
3451 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3453 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3454 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3457 #ifdef CONFIG_X86_64
3458 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3459 if (vmx_msr_high
& (1u<<16))
3463 /* Require Write-Back (WB) memory type for VMCS accesses. */
3464 if (((vmx_msr_high
>> 18) & 15) != 6)
3467 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3468 vmcs_conf
->order
= get_order(vmcs_conf
->size
);
3469 vmcs_conf
->basic_cap
= vmx_msr_high
& ~0x1fff;
3470 vmcs_conf
->revision_id
= vmx_msr_low
;
3472 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3473 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3474 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3475 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3476 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3478 cpu_has_load_ia32_efer
=
3479 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3480 VM_ENTRY_LOAD_IA32_EFER
)
3481 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3482 VM_EXIT_LOAD_IA32_EFER
);
3484 cpu_has_load_perf_global_ctrl
=
3485 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3486 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3487 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3488 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3491 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3492 * but due to errata below it can't be used. Workaround is to use
3493 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3495 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3500 * BC86,AAY89,BD102 (model 44)
3504 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3505 switch (boot_cpu_data
.x86_model
) {
3511 cpu_has_load_perf_global_ctrl
= false;
3512 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3513 "does not work properly. Using workaround\n");
3520 if (boot_cpu_has(X86_FEATURE_XSAVES
))
3521 rdmsrl(MSR_IA32_XSS
, host_xss
);
3526 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3528 int node
= cpu_to_node(cpu
);
3532 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3535 vmcs
= page_address(pages
);
3536 memset(vmcs
, 0, vmcs_config
.size
);
3537 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3541 static struct vmcs
*alloc_vmcs(void)
3543 return alloc_vmcs_cpu(raw_smp_processor_id());
3546 static void free_vmcs(struct vmcs
*vmcs
)
3548 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3552 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3554 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3556 if (!loaded_vmcs
->vmcs
)
3558 loaded_vmcs_clear(loaded_vmcs
);
3559 free_vmcs(loaded_vmcs
->vmcs
);
3560 loaded_vmcs
->vmcs
= NULL
;
3563 static void free_kvm_area(void)
3567 for_each_possible_cpu(cpu
) {
3568 free_vmcs(per_cpu(vmxarea
, cpu
));
3569 per_cpu(vmxarea
, cpu
) = NULL
;
3573 static void init_vmcs_shadow_fields(void)
3577 /* No checks for read only fields yet */
3579 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3580 switch (shadow_read_write_fields
[i
]) {
3582 if (!kvm_mpx_supported())
3590 shadow_read_write_fields
[j
] =
3591 shadow_read_write_fields
[i
];
3594 max_shadow_read_write_fields
= j
;
3596 /* shadowed fields guest access without vmexit */
3597 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3598 clear_bit(shadow_read_write_fields
[i
],
3599 vmx_vmwrite_bitmap
);
3600 clear_bit(shadow_read_write_fields
[i
],
3603 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
3604 clear_bit(shadow_read_only_fields
[i
],
3608 static __init
int alloc_kvm_area(void)
3612 for_each_possible_cpu(cpu
) {
3615 vmcs
= alloc_vmcs_cpu(cpu
);
3621 per_cpu(vmxarea
, cpu
) = vmcs
;
3626 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3628 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3631 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3632 struct kvm_segment
*save
)
3634 if (!emulate_invalid_guest_state
) {
3636 * CS and SS RPL should be equal during guest entry according
3637 * to VMX spec, but in reality it is not always so. Since vcpu
3638 * is in the middle of the transition from real mode to
3639 * protected mode it is safe to assume that RPL 0 is a good
3642 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3643 save
->selector
&= ~SEGMENT_RPL_MASK
;
3644 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3647 vmx_set_segment(vcpu
, save
, seg
);
3650 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3652 unsigned long flags
;
3653 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3656 * Update real mode segment cache. It may be not up-to-date if sement
3657 * register was written while vcpu was in a guest mode.
3659 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3660 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3661 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3662 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3663 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3664 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3666 vmx
->rmode
.vm86_active
= 0;
3668 vmx_segment_cache_clear(vmx
);
3670 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3672 flags
= vmcs_readl(GUEST_RFLAGS
);
3673 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3674 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3675 vmcs_writel(GUEST_RFLAGS
, flags
);
3677 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3678 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3680 update_exception_bitmap(vcpu
);
3682 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3683 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3684 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3685 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3686 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3687 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3690 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3692 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3693 struct kvm_segment var
= *save
;
3696 if (seg
== VCPU_SREG_CS
)
3699 if (!emulate_invalid_guest_state
) {
3700 var
.selector
= var
.base
>> 4;
3701 var
.base
= var
.base
& 0xffff0;
3711 if (save
->base
& 0xf)
3712 printk_once(KERN_WARNING
"kvm: segment base is not "
3713 "paragraph aligned when entering "
3714 "protected mode (seg=%d)", seg
);
3717 vmcs_write16(sf
->selector
, var
.selector
);
3718 vmcs_write32(sf
->base
, var
.base
);
3719 vmcs_write32(sf
->limit
, var
.limit
);
3720 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3723 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3725 unsigned long flags
;
3726 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3728 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3729 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3730 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3731 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3732 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3733 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3734 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3736 vmx
->rmode
.vm86_active
= 1;
3739 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3740 * vcpu. Warn the user that an update is overdue.
3742 if (!vcpu
->kvm
->arch
.tss_addr
)
3743 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3744 "called before entering vcpu\n");
3746 vmx_segment_cache_clear(vmx
);
3748 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3749 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3750 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3752 flags
= vmcs_readl(GUEST_RFLAGS
);
3753 vmx
->rmode
.save_rflags
= flags
;
3755 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3757 vmcs_writel(GUEST_RFLAGS
, flags
);
3758 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3759 update_exception_bitmap(vcpu
);
3761 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3762 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3763 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3764 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3765 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3766 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3768 kvm_mmu_reset_context(vcpu
);
3771 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3773 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3774 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3780 * Force kernel_gs_base reloading before EFER changes, as control
3781 * of this msr depends on is_long_mode().
3783 vmx_load_host_state(to_vmx(vcpu
));
3784 vcpu
->arch
.efer
= efer
;
3785 if (efer
& EFER_LMA
) {
3786 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3789 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3791 msr
->data
= efer
& ~EFER_LME
;
3796 #ifdef CONFIG_X86_64
3798 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3802 vmx_segment_cache_clear(to_vmx(vcpu
));
3804 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3805 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
3806 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3808 vmcs_write32(GUEST_TR_AR_BYTES
,
3809 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
3810 | VMX_AR_TYPE_BUSY_64_TSS
);
3812 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3815 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3817 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3818 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3823 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
3825 vpid_sync_context(vpid
);
3827 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3829 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3833 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3835 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
3838 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3840 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3842 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3843 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3846 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3848 if (enable_ept
&& is_paging(vcpu
))
3849 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3850 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3853 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3855 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3857 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3858 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3861 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3863 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3865 if (!test_bit(VCPU_EXREG_PDPTR
,
3866 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3869 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3870 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
3871 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
3872 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
3873 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
3877 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3879 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3881 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3882 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3883 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3884 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3885 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3888 __set_bit(VCPU_EXREG_PDPTR
,
3889 (unsigned long *)&vcpu
->arch
.regs_avail
);
3890 __set_bit(VCPU_EXREG_PDPTR
,
3891 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3894 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3896 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3898 struct kvm_vcpu
*vcpu
)
3900 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3901 vmx_decache_cr3(vcpu
);
3902 if (!(cr0
& X86_CR0_PG
)) {
3903 /* From paging/starting to nonpaging */
3904 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3905 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3906 (CPU_BASED_CR3_LOAD_EXITING
|
3907 CPU_BASED_CR3_STORE_EXITING
));
3908 vcpu
->arch
.cr0
= cr0
;
3909 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3910 } else if (!is_paging(vcpu
)) {
3911 /* From nonpaging to paging */
3912 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3913 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3914 ~(CPU_BASED_CR3_LOAD_EXITING
|
3915 CPU_BASED_CR3_STORE_EXITING
));
3916 vcpu
->arch
.cr0
= cr0
;
3917 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3920 if (!(cr0
& X86_CR0_WP
))
3921 *hw_cr0
&= ~X86_CR0_WP
;
3924 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3926 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3927 unsigned long hw_cr0
;
3929 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3930 if (enable_unrestricted_guest
)
3931 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3933 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3935 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3938 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3942 #ifdef CONFIG_X86_64
3943 if (vcpu
->arch
.efer
& EFER_LME
) {
3944 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3946 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3952 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3954 if (!vcpu
->fpu_active
)
3955 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3957 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3958 vmcs_writel(GUEST_CR0
, hw_cr0
);
3959 vcpu
->arch
.cr0
= cr0
;
3961 /* depends on vcpu->arch.cr0 to be set to a new value */
3962 vmx
->emulation_required
= emulation_required(vcpu
);
3965 static u64
construct_eptp(unsigned long root_hpa
)
3969 /* TODO write the value reading from MSR */
3970 eptp
= VMX_EPT_DEFAULT_MT
|
3971 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3972 if (enable_ept_ad_bits
)
3973 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3974 eptp
|= (root_hpa
& PAGE_MASK
);
3979 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3981 unsigned long guest_cr3
;
3986 eptp
= construct_eptp(cr3
);
3987 vmcs_write64(EPT_POINTER
, eptp
);
3988 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
3989 guest_cr3
= kvm_read_cr3(vcpu
);
3991 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
3992 ept_load_pdptrs(vcpu
);
3995 vmx_flush_tlb(vcpu
);
3996 vmcs_writel(GUEST_CR3
, guest_cr3
);
3999 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
4002 * Pass through host's Machine Check Enable value to hw_cr4, which
4003 * is in force while we are in guest mode. Do not let guests control
4004 * this bit, even if host CR4.MCE == 0.
4006 unsigned long hw_cr4
=
4007 (cr4_read_shadow() & X86_CR4_MCE
) |
4008 (cr4
& ~X86_CR4_MCE
) |
4009 (to_vmx(vcpu
)->rmode
.vm86_active
?
4010 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
4012 if (cr4
& X86_CR4_VMXE
) {
4014 * To use VMXON (and later other VMX instructions), a guest
4015 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4016 * So basically the check on whether to allow nested VMX
4019 if (!nested_vmx_allowed(vcpu
))
4022 if (to_vmx(vcpu
)->nested
.vmxon
&&
4023 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
4026 vcpu
->arch
.cr4
= cr4
;
4028 if (!is_paging(vcpu
)) {
4029 hw_cr4
&= ~X86_CR4_PAE
;
4030 hw_cr4
|= X86_CR4_PSE
;
4031 } else if (!(cr4
& X86_CR4_PAE
)) {
4032 hw_cr4
&= ~X86_CR4_PAE
;
4036 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
4038 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4039 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4040 * to be manually disabled when guest switches to non-paging
4043 * If !enable_unrestricted_guest, the CPU is always running
4044 * with CR0.PG=1 and CR4 needs to be modified.
4045 * If enable_unrestricted_guest, the CPU automatically
4046 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4048 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
4050 vmcs_writel(CR4_READ_SHADOW
, cr4
);
4051 vmcs_writel(GUEST_CR4
, hw_cr4
);
4055 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
4056 struct kvm_segment
*var
, int seg
)
4058 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4061 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4062 *var
= vmx
->rmode
.segs
[seg
];
4063 if (seg
== VCPU_SREG_TR
4064 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
4066 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4067 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4070 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4071 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
4072 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4073 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
4074 var
->unusable
= (ar
>> 16) & 1;
4075 var
->type
= ar
& 15;
4076 var
->s
= (ar
>> 4) & 1;
4077 var
->dpl
= (ar
>> 5) & 3;
4079 * Some userspaces do not preserve unusable property. Since usable
4080 * segment has to be present according to VMX spec we can use present
4081 * property to amend userspace bug by making unusable segment always
4082 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4083 * segment as unusable.
4085 var
->present
= !var
->unusable
;
4086 var
->avl
= (ar
>> 12) & 1;
4087 var
->l
= (ar
>> 13) & 1;
4088 var
->db
= (ar
>> 14) & 1;
4089 var
->g
= (ar
>> 15) & 1;
4092 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
4094 struct kvm_segment s
;
4096 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
4097 vmx_get_segment(vcpu
, &s
, seg
);
4100 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
4103 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
4105 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4107 if (unlikely(vmx
->rmode
.vm86_active
))
4110 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
4111 return VMX_AR_DPL(ar
);
4115 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
4119 if (var
->unusable
|| !var
->present
)
4122 ar
= var
->type
& 15;
4123 ar
|= (var
->s
& 1) << 4;
4124 ar
|= (var
->dpl
& 3) << 5;
4125 ar
|= (var
->present
& 1) << 7;
4126 ar
|= (var
->avl
& 1) << 12;
4127 ar
|= (var
->l
& 1) << 13;
4128 ar
|= (var
->db
& 1) << 14;
4129 ar
|= (var
->g
& 1) << 15;
4135 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
4136 struct kvm_segment
*var
, int seg
)
4138 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4139 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4141 vmx_segment_cache_clear(vmx
);
4143 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4144 vmx
->rmode
.segs
[seg
] = *var
;
4145 if (seg
== VCPU_SREG_TR
)
4146 vmcs_write16(sf
->selector
, var
->selector
);
4148 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
4152 vmcs_writel(sf
->base
, var
->base
);
4153 vmcs_write32(sf
->limit
, var
->limit
);
4154 vmcs_write16(sf
->selector
, var
->selector
);
4157 * Fix the "Accessed" bit in AR field of segment registers for older
4159 * IA32 arch specifies that at the time of processor reset the
4160 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4161 * is setting it to 0 in the userland code. This causes invalid guest
4162 * state vmexit when "unrestricted guest" mode is turned on.
4163 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4164 * tree. Newer qemu binaries with that qemu fix would not need this
4167 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
4168 var
->type
|= 0x1; /* Accessed */
4170 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4173 vmx
->emulation_required
= emulation_required(vcpu
);
4176 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4178 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4180 *db
= (ar
>> 14) & 1;
4181 *l
= (ar
>> 13) & 1;
4184 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4186 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4187 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4190 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4192 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4193 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4196 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4198 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4199 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4202 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4204 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4205 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4208 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4210 struct kvm_segment var
;
4213 vmx_get_segment(vcpu
, &var
, seg
);
4215 if (seg
== VCPU_SREG_CS
)
4217 ar
= vmx_segment_access_rights(&var
);
4219 if (var
.base
!= (var
.selector
<< 4))
4221 if (var
.limit
!= 0xffff)
4229 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4231 struct kvm_segment cs
;
4232 unsigned int cs_rpl
;
4234 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4235 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4239 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4243 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4244 if (cs
.dpl
> cs_rpl
)
4247 if (cs
.dpl
!= cs_rpl
)
4253 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4257 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4259 struct kvm_segment ss
;
4260 unsigned int ss_rpl
;
4262 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4263 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4267 if (ss
.type
!= 3 && ss
.type
!= 7)
4271 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4279 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4281 struct kvm_segment var
;
4284 vmx_get_segment(vcpu
, &var
, seg
);
4285 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4293 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4294 if (var
.dpl
< rpl
) /* DPL < RPL */
4298 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4304 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4306 struct kvm_segment tr
;
4308 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4312 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4314 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4322 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4324 struct kvm_segment ldtr
;
4326 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4330 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4340 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4342 struct kvm_segment cs
, ss
;
4344 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4345 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4347 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4348 (ss
.selector
& SEGMENT_RPL_MASK
));
4352 * Check if guest state is valid. Returns true if valid, false if
4354 * We assume that registers are always usable
4356 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4358 if (enable_unrestricted_guest
)
4361 /* real mode guest state checks */
4362 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4363 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4365 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4367 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4369 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4371 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4373 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4376 /* protected mode guest state checks */
4377 if (!cs_ss_rpl_check(vcpu
))
4379 if (!code_segment_valid(vcpu
))
4381 if (!stack_segment_valid(vcpu
))
4383 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4385 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4387 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4389 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4391 if (!tr_valid(vcpu
))
4393 if (!ldtr_valid(vcpu
))
4397 * - Add checks on RIP
4398 * - Add checks on RFLAGS
4404 static int init_rmode_tss(struct kvm
*kvm
)
4410 idx
= srcu_read_lock(&kvm
->srcu
);
4411 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4412 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4415 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4416 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4417 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4420 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4423 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4427 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4428 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4431 srcu_read_unlock(&kvm
->srcu
, idx
);
4435 static int init_rmode_identity_map(struct kvm
*kvm
)
4438 kvm_pfn_t identity_map_pfn
;
4444 /* Protect kvm->arch.ept_identity_pagetable_done. */
4445 mutex_lock(&kvm
->slots_lock
);
4447 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4450 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4452 r
= alloc_identity_pagetable(kvm
);
4456 idx
= srcu_read_lock(&kvm
->srcu
);
4457 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4460 /* Set up identity-mapping pagetable for EPT in real mode */
4461 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4462 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4463 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4464 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4465 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4469 kvm
->arch
.ept_identity_pagetable_done
= true;
4472 srcu_read_unlock(&kvm
->srcu
, idx
);
4475 mutex_unlock(&kvm
->slots_lock
);
4479 static void seg_setup(int seg
)
4481 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4484 vmcs_write16(sf
->selector
, 0);
4485 vmcs_writel(sf
->base
, 0);
4486 vmcs_write32(sf
->limit
, 0xffff);
4488 if (seg
== VCPU_SREG_CS
)
4489 ar
|= 0x08; /* code segment */
4491 vmcs_write32(sf
->ar_bytes
, ar
);
4494 static int alloc_apic_access_page(struct kvm
*kvm
)
4499 mutex_lock(&kvm
->slots_lock
);
4500 if (kvm
->arch
.apic_access_page_done
)
4502 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4503 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4507 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4508 if (is_error_page(page
)) {
4514 * Do not pin the page in memory, so that memory hot-unplug
4515 * is able to migrate it.
4518 kvm
->arch
.apic_access_page_done
= true;
4520 mutex_unlock(&kvm
->slots_lock
);
4524 static int alloc_identity_pagetable(struct kvm
*kvm
)
4526 /* Called with kvm->slots_lock held. */
4530 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4532 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4533 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4538 static int allocate_vpid(void)
4544 spin_lock(&vmx_vpid_lock
);
4545 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4546 if (vpid
< VMX_NR_VPIDS
)
4547 __set_bit(vpid
, vmx_vpid_bitmap
);
4550 spin_unlock(&vmx_vpid_lock
);
4554 static void free_vpid(int vpid
)
4556 if (!enable_vpid
|| vpid
== 0)
4558 spin_lock(&vmx_vpid_lock
);
4559 __clear_bit(vpid
, vmx_vpid_bitmap
);
4560 spin_unlock(&vmx_vpid_lock
);
4563 #define MSR_TYPE_R 1
4564 #define MSR_TYPE_W 2
4565 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4568 int f
= sizeof(unsigned long);
4570 if (!cpu_has_vmx_msr_bitmap())
4574 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4575 * have the write-low and read-high bitmap offsets the wrong way round.
4576 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4578 if (msr
<= 0x1fff) {
4579 if (type
& MSR_TYPE_R
)
4581 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4583 if (type
& MSR_TYPE_W
)
4585 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4587 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4589 if (type
& MSR_TYPE_R
)
4591 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4593 if (type
& MSR_TYPE_W
)
4595 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4600 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
4603 int f
= sizeof(unsigned long);
4605 if (!cpu_has_vmx_msr_bitmap())
4609 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4610 * have the write-low and read-high bitmap offsets the wrong way round.
4611 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4613 if (msr
<= 0x1fff) {
4614 if (type
& MSR_TYPE_R
)
4616 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
4618 if (type
& MSR_TYPE_W
)
4620 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
4622 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4624 if (type
& MSR_TYPE_R
)
4626 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
4628 if (type
& MSR_TYPE_W
)
4630 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4636 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4637 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4639 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4640 unsigned long *msr_bitmap_nested
,
4643 int f
= sizeof(unsigned long);
4645 if (!cpu_has_vmx_msr_bitmap()) {
4651 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4652 * have the write-low and read-high bitmap offsets the wrong way round.
4653 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4655 if (msr
<= 0x1fff) {
4656 if (type
& MSR_TYPE_R
&&
4657 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4659 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4661 if (type
& MSR_TYPE_W
&&
4662 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4664 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4666 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4668 if (type
& MSR_TYPE_R
&&
4669 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4671 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4673 if (type
& MSR_TYPE_W
&&
4674 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4676 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4681 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4684 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4685 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4686 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4687 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4690 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
4692 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4694 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4698 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
4700 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4702 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4706 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
4708 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4710 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4714 static bool vmx_get_enable_apicv(void)
4716 return enable_apicv
;
4719 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
4721 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4726 if (vmx
->nested
.pi_desc
&&
4727 vmx
->nested
.pi_pending
) {
4728 vmx
->nested
.pi_pending
= false;
4729 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
4732 max_irr
= find_last_bit(
4733 (unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
4738 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
4743 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
4744 kunmap(vmx
->nested
.virtual_apic_page
);
4746 status
= vmcs_read16(GUEST_INTR_STATUS
);
4747 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
4749 status
|= (u8
)max_irr
;
4750 vmcs_write16(GUEST_INTR_STATUS
, status
);
4756 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
)
4759 if (vcpu
->mode
== IN_GUEST_MODE
) {
4760 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4763 * Currently, we don't support urgent interrupt,
4764 * all interrupts are recognized as non-urgent
4765 * interrupt, so we cannot post interrupts when
4768 * If the vcpu is in guest mode, it means it is
4769 * running instead of being scheduled out and
4770 * waiting in the run queue, and that's the only
4771 * case when 'SN' is set currently, warning if
4774 WARN_ON_ONCE(pi_test_sn(&vmx
->pi_desc
));
4776 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4777 POSTED_INTR_VECTOR
);
4784 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
4787 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4789 if (is_guest_mode(vcpu
) &&
4790 vector
== vmx
->nested
.posted_intr_nv
) {
4791 /* the PIR and ON have been set by L1. */
4792 kvm_vcpu_trigger_posted_interrupt(vcpu
);
4794 * If a posted intr is not recognized by hardware,
4795 * we will accomplish it in the next vmentry.
4797 vmx
->nested
.pi_pending
= true;
4798 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4804 * Send interrupt to vcpu via posted interrupt way.
4805 * 1. If target vcpu is running(non-root mode), send posted interrupt
4806 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4807 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4808 * interrupt from PIR in next vmentry.
4810 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4812 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4815 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
4819 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4822 r
= pi_test_and_set_on(&vmx
->pi_desc
);
4823 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4824 if (r
|| !kvm_vcpu_trigger_posted_interrupt(vcpu
))
4825 kvm_vcpu_kick(vcpu
);
4828 static void vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4830 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4832 if (!pi_test_and_clear_on(&vmx
->pi_desc
))
4835 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
4839 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4840 * will not change in the lifetime of the guest.
4841 * Note that host-state that does change is set elsewhere. E.g., host-state
4842 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4844 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4851 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
4852 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4854 /* Save the most likely value for this task's CR4 in the VMCS. */
4855 cr4
= cr4_read_shadow();
4856 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
4857 vmx
->host_state
.vmcs_host_cr4
= cr4
;
4859 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4860 #ifdef CONFIG_X86_64
4862 * Load null selectors, so we can avoid reloading them in
4863 * __vmx_load_host_state(), in case userspace uses the null selectors
4864 * too (the expected case).
4866 vmcs_write16(HOST_DS_SELECTOR
, 0);
4867 vmcs_write16(HOST_ES_SELECTOR
, 0);
4869 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4870 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4872 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4873 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4875 native_store_idt(&dt
);
4876 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4877 vmx
->host_idt_base
= dt
.address
;
4879 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4881 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4882 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4883 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4884 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4886 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4887 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4888 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4892 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4894 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4896 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4897 if (is_guest_mode(&vmx
->vcpu
))
4898 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4899 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4900 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4903 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4905 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4907 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
4908 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4909 /* Enable the preemption timer dynamically */
4910 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
4911 return pin_based_exec_ctrl
;
4914 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
4916 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4918 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4919 if (cpu_has_secondary_exec_ctrls()) {
4920 if (kvm_vcpu_apicv_active(vcpu
))
4921 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
4922 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4923 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4925 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
4926 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4927 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4930 if (cpu_has_vmx_msr_bitmap())
4931 vmx_set_msr_bitmap(vcpu
);
4934 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4936 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4938 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
4939 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
4941 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
4942 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4943 #ifdef CONFIG_X86_64
4944 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4945 CPU_BASED_CR8_LOAD_EXITING
;
4949 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4950 CPU_BASED_CR3_LOAD_EXITING
|
4951 CPU_BASED_INVLPG_EXITING
;
4952 return exec_control
;
4955 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4957 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4958 if (!cpu_need_virtualize_apic_accesses(&vmx
->vcpu
))
4959 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4961 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4963 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4964 enable_unrestricted_guest
= 0;
4965 /* Enable INVPCID for non-ept guests may cause performance regression. */
4966 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4968 if (!enable_unrestricted_guest
)
4969 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4971 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4972 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
4973 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4974 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4975 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4976 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4978 We can NOT enable shadow_vmcs here because we don't have yet
4981 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4984 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
4986 return exec_control
;
4989 static void ept_set_mmio_spte_mask(void)
4992 * EPT Misconfigurations can be generated if the value of bits 2:0
4993 * of an EPT paging-structure entry is 110b (write/execute).
4994 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4997 kvm_mmu_set_mmio_spte_mask((0x3ull
<< 62) | 0x6ull
);
5000 #define VMX_XSS_EXIT_BITMAP 0
5002 * Sets up the vmcs for emulated real mode.
5004 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
5006 #ifdef CONFIG_X86_64
5012 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
5013 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
5015 if (enable_shadow_vmcs
) {
5016 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
5017 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
5019 if (cpu_has_vmx_msr_bitmap())
5020 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
5022 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
5025 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5026 vmx
->hv_deadline_tsc
= -1;
5028 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
5030 if (cpu_has_secondary_exec_ctrls()) {
5031 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
5032 vmx_secondary_exec_control(vmx
));
5035 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
5036 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
5037 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
5038 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
5039 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
5041 vmcs_write16(GUEST_INTR_STATUS
, 0);
5043 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
5044 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
5048 vmcs_write32(PLE_GAP
, ple_gap
);
5049 vmx
->ple_window
= ple_window
;
5050 vmx
->ple_window_dirty
= true;
5053 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
5054 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
5055 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
5057 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
5058 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
5059 vmx_set_constant_host_state(vmx
);
5060 #ifdef CONFIG_X86_64
5061 rdmsrl(MSR_FS_BASE
, a
);
5062 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
5063 rdmsrl(MSR_GS_BASE
, a
);
5064 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
5066 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
5067 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
5070 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
5071 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
5072 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
5073 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
5074 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
5076 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
5077 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
5079 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
5080 u32 index
= vmx_msr_index
[i
];
5081 u32 data_low
, data_high
;
5084 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
5086 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
5088 vmx
->guest_msrs
[j
].index
= i
;
5089 vmx
->guest_msrs
[j
].data
= 0;
5090 vmx
->guest_msrs
[j
].mask
= -1ull;
5095 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
5097 /* 22.2.1, 20.8.1 */
5098 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
5100 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
5101 set_cr4_guest_host_mask(vmx
);
5103 if (vmx_xsaves_supported())
5104 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
5107 ASSERT(vmx
->pml_pg
);
5108 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
5109 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
5115 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
5117 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5118 struct msr_data apic_base_msr
;
5121 vmx
->rmode
.vm86_active
= 0;
5123 vmx
->soft_vnmi_blocked
= 0;
5125 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
5126 kvm_set_cr8(vcpu
, 0);
5129 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
5130 MSR_IA32_APICBASE_ENABLE
;
5131 if (kvm_vcpu_is_reset_bsp(vcpu
))
5132 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
5133 apic_base_msr
.host_initiated
= true;
5134 kvm_set_apic_base(vcpu
, &apic_base_msr
);
5137 vmx_segment_cache_clear(vmx
);
5139 seg_setup(VCPU_SREG_CS
);
5140 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
5141 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
5143 seg_setup(VCPU_SREG_DS
);
5144 seg_setup(VCPU_SREG_ES
);
5145 seg_setup(VCPU_SREG_FS
);
5146 seg_setup(VCPU_SREG_GS
);
5147 seg_setup(VCPU_SREG_SS
);
5149 vmcs_write16(GUEST_TR_SELECTOR
, 0);
5150 vmcs_writel(GUEST_TR_BASE
, 0);
5151 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
5152 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5154 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
5155 vmcs_writel(GUEST_LDTR_BASE
, 0);
5156 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
5157 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
5160 vmcs_write32(GUEST_SYSENTER_CS
, 0);
5161 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
5162 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
5163 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
5166 vmcs_writel(GUEST_RFLAGS
, 0x02);
5167 kvm_rip_write(vcpu
, 0xfff0);
5169 vmcs_writel(GUEST_GDTR_BASE
, 0);
5170 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
5172 vmcs_writel(GUEST_IDTR_BASE
, 0);
5173 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
5175 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
5176 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
5177 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
5181 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
5183 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
5184 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
5185 if (cpu_need_tpr_shadow(vcpu
))
5186 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
5187 __pa(vcpu
->arch
.apic
->regs
));
5188 vmcs_write32(TPR_THRESHOLD
, 0);
5191 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5193 if (kvm_vcpu_apicv_active(vcpu
))
5194 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
5197 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5199 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5200 vmx
->vcpu
.arch
.cr0
= cr0
;
5201 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5202 vmx_set_cr4(vcpu
, 0);
5203 vmx_set_efer(vcpu
, 0);
5204 vmx_fpu_activate(vcpu
);
5205 update_exception_bitmap(vcpu
);
5207 vpid_sync_context(vmx
->vpid
);
5211 * In nested virtualization, check if L1 asked to exit on external interrupts.
5212 * For most existing hypervisors, this will always return true.
5214 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5216 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5217 PIN_BASED_EXT_INTR_MASK
;
5221 * In nested virtualization, check if L1 has set
5222 * VM_EXIT_ACK_INTR_ON_EXIT
5224 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5226 return get_vmcs12(vcpu
)->vm_exit_controls
&
5227 VM_EXIT_ACK_INTR_ON_EXIT
;
5230 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5232 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5233 PIN_BASED_NMI_EXITING
;
5236 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5238 u32 cpu_based_vm_exec_control
;
5240 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5241 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
5242 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5245 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5247 u32 cpu_based_vm_exec_control
;
5249 if (!cpu_has_virtual_nmis() ||
5250 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5251 enable_irq_window(vcpu
);
5255 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5256 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
5257 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5260 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5262 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5264 int irq
= vcpu
->arch
.interrupt
.nr
;
5266 trace_kvm_inj_virq(irq
);
5268 ++vcpu
->stat
.irq_injections
;
5269 if (vmx
->rmode
.vm86_active
) {
5271 if (vcpu
->arch
.interrupt
.soft
)
5272 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5273 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5274 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5277 intr
= irq
| INTR_INFO_VALID_MASK
;
5278 if (vcpu
->arch
.interrupt
.soft
) {
5279 intr
|= INTR_TYPE_SOFT_INTR
;
5280 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5281 vmx
->vcpu
.arch
.event_exit_inst_len
);
5283 intr
|= INTR_TYPE_EXT_INTR
;
5284 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5287 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5289 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5291 if (is_guest_mode(vcpu
))
5294 if (!cpu_has_virtual_nmis()) {
5296 * Tracking the NMI-blocked state in software is built upon
5297 * finding the next open IRQ window. This, in turn, depends on
5298 * well-behaving guests: They have to keep IRQs disabled at
5299 * least as long as the NMI handler runs. Otherwise we may
5300 * cause NMI nesting, maybe breaking the guest. But as this is
5301 * highly unlikely, we can live with the residual risk.
5303 vmx
->soft_vnmi_blocked
= 1;
5304 vmx
->vnmi_blocked_time
= 0;
5307 ++vcpu
->stat
.nmi_injections
;
5308 vmx
->nmi_known_unmasked
= false;
5309 if (vmx
->rmode
.vm86_active
) {
5310 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5311 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5314 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5315 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5318 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5320 if (!cpu_has_virtual_nmis())
5321 return to_vmx(vcpu
)->soft_vnmi_blocked
;
5322 if (to_vmx(vcpu
)->nmi_known_unmasked
)
5324 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5327 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5329 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5331 if (!cpu_has_virtual_nmis()) {
5332 if (vmx
->soft_vnmi_blocked
!= masked
) {
5333 vmx
->soft_vnmi_blocked
= masked
;
5334 vmx
->vnmi_blocked_time
= 0;
5337 vmx
->nmi_known_unmasked
= !masked
;
5339 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5340 GUEST_INTR_STATE_NMI
);
5342 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5343 GUEST_INTR_STATE_NMI
);
5347 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5349 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5352 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
5355 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5356 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5357 | GUEST_INTR_STATE_NMI
));
5360 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5362 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5363 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5364 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5365 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5368 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5372 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5376 kvm
->arch
.tss_addr
= addr
;
5377 return init_rmode_tss(kvm
);
5380 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5385 * Update instruction length as we may reinject the exception
5386 * from user space while in guest debugging mode.
5388 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5389 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5390 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5394 if (vcpu
->guest_debug
&
5395 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5412 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5413 int vec
, u32 err_code
)
5416 * Instruction with address size override prefix opcode 0x67
5417 * Cause the #SS fault with 0 error code in VM86 mode.
5419 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5420 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5421 if (vcpu
->arch
.halt_request
) {
5422 vcpu
->arch
.halt_request
= 0;
5423 return kvm_vcpu_halt(vcpu
);
5431 * Forward all other exceptions that are valid in real mode.
5432 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5433 * the required debugging infrastructure rework.
5435 kvm_queue_exception(vcpu
, vec
);
5440 * Trigger machine check on the host. We assume all the MSRs are already set up
5441 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5442 * We pass a fake environment to the machine check handler because we want
5443 * the guest to be always treated like user space, no matter what context
5444 * it used internally.
5446 static void kvm_machine_check(void)
5448 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5449 struct pt_regs regs
= {
5450 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5451 .flags
= X86_EFLAGS_IF
,
5454 do_machine_check(®s
, 0);
5458 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5460 /* already handled by vcpu_run */
5464 static int handle_exception(struct kvm_vcpu
*vcpu
)
5466 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5467 struct kvm_run
*kvm_run
= vcpu
->run
;
5468 u32 intr_info
, ex_no
, error_code
;
5469 unsigned long cr2
, rip
, dr6
;
5471 enum emulation_result er
;
5473 vect_info
= vmx
->idt_vectoring_info
;
5474 intr_info
= vmx
->exit_intr_info
;
5476 if (is_machine_check(intr_info
))
5477 return handle_machine_check(vcpu
);
5479 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
5480 return 1; /* already handled by vmx_vcpu_run() */
5482 if (is_no_device(intr_info
)) {
5483 vmx_fpu_activate(vcpu
);
5487 if (is_invalid_opcode(intr_info
)) {
5488 if (is_guest_mode(vcpu
)) {
5489 kvm_queue_exception(vcpu
, UD_VECTOR
);
5492 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5493 if (er
!= EMULATE_DONE
)
5494 kvm_queue_exception(vcpu
, UD_VECTOR
);
5499 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5500 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5503 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5504 * MMIO, it is better to report an internal error.
5505 * See the comments in vmx_handle_exit.
5507 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5508 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5509 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5510 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5511 vcpu
->run
->internal
.ndata
= 3;
5512 vcpu
->run
->internal
.data
[0] = vect_info
;
5513 vcpu
->run
->internal
.data
[1] = intr_info
;
5514 vcpu
->run
->internal
.data
[2] = error_code
;
5518 if (is_page_fault(intr_info
)) {
5519 /* EPT won't cause page fault directly */
5521 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5522 trace_kvm_page_fault(cr2
, error_code
);
5524 if (kvm_event_needs_reinjection(vcpu
))
5525 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
5526 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
5529 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5531 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5532 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5536 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
5539 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5540 if (!(vcpu
->guest_debug
&
5541 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5542 vcpu
->arch
.dr6
&= ~15;
5543 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5544 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5545 skip_emulated_instruction(vcpu
);
5547 kvm_queue_exception(vcpu
, DB_VECTOR
);
5550 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5551 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5555 * Update instruction length as we may reinject #BP from
5556 * user space while in guest debugging mode. Reading it for
5557 * #DB as well causes no harm, it is not used in that case.
5559 vmx
->vcpu
.arch
.event_exit_inst_len
=
5560 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5561 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5562 rip
= kvm_rip_read(vcpu
);
5563 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5564 kvm_run
->debug
.arch
.exception
= ex_no
;
5567 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5568 kvm_run
->ex
.exception
= ex_no
;
5569 kvm_run
->ex
.error_code
= error_code
;
5575 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5577 ++vcpu
->stat
.irq_exits
;
5581 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5583 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5587 static int handle_io(struct kvm_vcpu
*vcpu
)
5589 unsigned long exit_qualification
;
5590 int size
, in
, string
;
5593 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5594 string
= (exit_qualification
& 16) != 0;
5595 in
= (exit_qualification
& 8) != 0;
5597 ++vcpu
->stat
.io_exits
;
5600 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5602 port
= exit_qualification
>> 16;
5603 size
= (exit_qualification
& 7) + 1;
5604 skip_emulated_instruction(vcpu
);
5606 return kvm_fast_pio_out(vcpu
, size
, port
);
5610 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5613 * Patch in the VMCALL instruction:
5615 hypercall
[0] = 0x0f;
5616 hypercall
[1] = 0x01;
5617 hypercall
[2] = 0xc1;
5620 static bool nested_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
5622 unsigned long always_on
= VMXON_CR0_ALWAYSON
;
5623 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5625 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
5626 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
5627 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
5628 always_on
&= ~(X86_CR0_PE
| X86_CR0_PG
);
5629 return (val
& always_on
) == always_on
;
5632 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5633 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5635 if (is_guest_mode(vcpu
)) {
5636 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5637 unsigned long orig_val
= val
;
5640 * We get here when L2 changed cr0 in a way that did not change
5641 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5642 * but did change L0 shadowed bits. So we first calculate the
5643 * effective cr0 value that L1 would like to write into the
5644 * hardware. It consists of the L2-owned bits from the new
5645 * value combined with the L1-owned bits from L1's guest_cr0.
5647 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5648 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5650 if (!nested_cr0_valid(vcpu
, val
))
5653 if (kvm_set_cr0(vcpu
, val
))
5655 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5658 if (to_vmx(vcpu
)->nested
.vmxon
&&
5659 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
5661 return kvm_set_cr0(vcpu
, val
);
5665 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5667 if (is_guest_mode(vcpu
)) {
5668 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5669 unsigned long orig_val
= val
;
5671 /* analogously to handle_set_cr0 */
5672 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5673 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5674 if (kvm_set_cr4(vcpu
, val
))
5676 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5679 return kvm_set_cr4(vcpu
, val
);
5682 /* called to set cr0 as appropriate for clts instruction exit. */
5683 static void handle_clts(struct kvm_vcpu
*vcpu
)
5685 if (is_guest_mode(vcpu
)) {
5687 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5688 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5689 * just pretend it's off (also in arch.cr0 for fpu_activate).
5691 vmcs_writel(CR0_READ_SHADOW
,
5692 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
5693 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
5695 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5698 static int handle_cr(struct kvm_vcpu
*vcpu
)
5700 unsigned long exit_qualification
, val
;
5705 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5706 cr
= exit_qualification
& 15;
5707 reg
= (exit_qualification
>> 8) & 15;
5708 switch ((exit_qualification
>> 4) & 3) {
5709 case 0: /* mov to cr */
5710 val
= kvm_register_readl(vcpu
, reg
);
5711 trace_kvm_cr_write(cr
, val
);
5714 err
= handle_set_cr0(vcpu
, val
);
5715 kvm_complete_insn_gp(vcpu
, err
);
5718 err
= kvm_set_cr3(vcpu
, val
);
5719 kvm_complete_insn_gp(vcpu
, err
);
5722 err
= handle_set_cr4(vcpu
, val
);
5723 kvm_complete_insn_gp(vcpu
, err
);
5726 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5728 err
= kvm_set_cr8(vcpu
, cr8
);
5729 kvm_complete_insn_gp(vcpu
, err
);
5730 if (lapic_in_kernel(vcpu
))
5732 if (cr8_prev
<= cr8
)
5734 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5741 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5742 skip_emulated_instruction(vcpu
);
5743 vmx_fpu_activate(vcpu
);
5745 case 1: /*mov from cr*/
5748 val
= kvm_read_cr3(vcpu
);
5749 kvm_register_write(vcpu
, reg
, val
);
5750 trace_kvm_cr_read(cr
, val
);
5751 skip_emulated_instruction(vcpu
);
5754 val
= kvm_get_cr8(vcpu
);
5755 kvm_register_write(vcpu
, reg
, val
);
5756 trace_kvm_cr_read(cr
, val
);
5757 skip_emulated_instruction(vcpu
);
5762 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5763 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5764 kvm_lmsw(vcpu
, val
);
5766 skip_emulated_instruction(vcpu
);
5771 vcpu
->run
->exit_reason
= 0;
5772 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5773 (int)(exit_qualification
>> 4) & 3, cr
);
5777 static int handle_dr(struct kvm_vcpu
*vcpu
)
5779 unsigned long exit_qualification
;
5782 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5783 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5785 /* First, if DR does not exist, trigger UD */
5786 if (!kvm_require_dr(vcpu
, dr
))
5789 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5790 if (!kvm_require_cpl(vcpu
, 0))
5792 dr7
= vmcs_readl(GUEST_DR7
);
5795 * As the vm-exit takes precedence over the debug trap, we
5796 * need to emulate the latter, either for the host or the
5797 * guest debugging itself.
5799 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5800 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5801 vcpu
->run
->debug
.arch
.dr7
= dr7
;
5802 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
5803 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5804 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5807 vcpu
->arch
.dr6
&= ~15;
5808 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
5809 kvm_queue_exception(vcpu
, DB_VECTOR
);
5814 if (vcpu
->guest_debug
== 0) {
5815 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
5816 CPU_BASED_MOV_DR_EXITING
);
5819 * No more DR vmexits; force a reload of the debug registers
5820 * and reenter on this instruction. The next vmexit will
5821 * retrieve the full state of the debug registers.
5823 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5827 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5828 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5831 if (kvm_get_dr(vcpu
, dr
, &val
))
5833 kvm_register_write(vcpu
, reg
, val
);
5835 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
5838 skip_emulated_instruction(vcpu
);
5842 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5844 return vcpu
->arch
.dr6
;
5847 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5851 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5853 get_debugreg(vcpu
->arch
.db
[0], 0);
5854 get_debugreg(vcpu
->arch
.db
[1], 1);
5855 get_debugreg(vcpu
->arch
.db
[2], 2);
5856 get_debugreg(vcpu
->arch
.db
[3], 3);
5857 get_debugreg(vcpu
->arch
.dr6
, 6);
5858 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
5860 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
5861 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
5864 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5866 vmcs_writel(GUEST_DR7
, val
);
5869 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5871 kvm_emulate_cpuid(vcpu
);
5875 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5877 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5878 struct msr_data msr_info
;
5880 msr_info
.index
= ecx
;
5881 msr_info
.host_initiated
= false;
5882 if (vmx_get_msr(vcpu
, &msr_info
)) {
5883 trace_kvm_msr_read_ex(ecx
);
5884 kvm_inject_gp(vcpu
, 0);
5888 trace_kvm_msr_read(ecx
, msr_info
.data
);
5890 /* FIXME: handling of bits 32:63 of rax, rdx */
5891 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
5892 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
5893 skip_emulated_instruction(vcpu
);
5897 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5899 struct msr_data msr
;
5900 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5901 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5902 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5906 msr
.host_initiated
= false;
5907 if (kvm_set_msr(vcpu
, &msr
) != 0) {
5908 trace_kvm_msr_write_ex(ecx
, data
);
5909 kvm_inject_gp(vcpu
, 0);
5913 trace_kvm_msr_write(ecx
, data
);
5914 skip_emulated_instruction(vcpu
);
5918 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5920 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5924 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5926 u32 cpu_based_vm_exec_control
;
5928 /* clear pending irq */
5929 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5930 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
5931 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5933 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5935 ++vcpu
->stat
.irq_window_exits
;
5939 static int handle_halt(struct kvm_vcpu
*vcpu
)
5941 return kvm_emulate_halt(vcpu
);
5944 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5946 return kvm_emulate_hypercall(vcpu
);
5949 static int handle_invd(struct kvm_vcpu
*vcpu
)
5951 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5954 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5956 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5958 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5959 skip_emulated_instruction(vcpu
);
5963 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5967 err
= kvm_rdpmc(vcpu
);
5968 kvm_complete_insn_gp(vcpu
, err
);
5973 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5975 kvm_emulate_wbinvd(vcpu
);
5979 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5981 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5982 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5984 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5985 skip_emulated_instruction(vcpu
);
5989 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
5991 skip_emulated_instruction(vcpu
);
5992 WARN(1, "this should never happen\n");
5996 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
5998 skip_emulated_instruction(vcpu
);
5999 WARN(1, "this should never happen\n");
6003 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
6005 if (likely(fasteoi
)) {
6006 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6007 int access_type
, offset
;
6009 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
6010 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
6012 * Sane guest uses MOV to write EOI, with written value
6013 * not cared. So make a short-circuit here by avoiding
6014 * heavy instruction emulation.
6016 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
6017 (offset
== APIC_EOI
)) {
6018 kvm_lapic_set_eoi(vcpu
);
6019 skip_emulated_instruction(vcpu
);
6023 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6026 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
6028 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6029 int vector
= exit_qualification
& 0xff;
6031 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6032 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
6036 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
6038 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6039 u32 offset
= exit_qualification
& 0xfff;
6041 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6042 kvm_apic_write_nodecode(vcpu
, offset
);
6046 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
6048 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6049 unsigned long exit_qualification
;
6050 bool has_error_code
= false;
6053 int reason
, type
, idt_v
, idt_index
;
6055 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
6056 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
6057 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
6059 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6061 reason
= (u32
)exit_qualification
>> 30;
6062 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
6064 case INTR_TYPE_NMI_INTR
:
6065 vcpu
->arch
.nmi_injected
= false;
6066 vmx_set_nmi_mask(vcpu
, true);
6068 case INTR_TYPE_EXT_INTR
:
6069 case INTR_TYPE_SOFT_INTR
:
6070 kvm_clear_interrupt_queue(vcpu
);
6072 case INTR_TYPE_HARD_EXCEPTION
:
6073 if (vmx
->idt_vectoring_info
&
6074 VECTORING_INFO_DELIVER_CODE_MASK
) {
6075 has_error_code
= true;
6077 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6080 case INTR_TYPE_SOFT_EXCEPTION
:
6081 kvm_clear_exception_queue(vcpu
);
6087 tss_selector
= exit_qualification
;
6089 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
6090 type
!= INTR_TYPE_EXT_INTR
&&
6091 type
!= INTR_TYPE_NMI_INTR
))
6092 skip_emulated_instruction(vcpu
);
6094 if (kvm_task_switch(vcpu
, tss_selector
,
6095 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
6096 has_error_code
, error_code
) == EMULATE_FAIL
) {
6097 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6098 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6099 vcpu
->run
->internal
.ndata
= 0;
6104 * TODO: What about debug traps on tss switch?
6105 * Are we supposed to inject them and update dr6?
6111 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
6113 unsigned long exit_qualification
;
6118 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6120 gla_validity
= (exit_qualification
>> 7) & 0x3;
6121 if (gla_validity
== 0x2) {
6122 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
6123 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6124 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
6125 vmcs_readl(GUEST_LINEAR_ADDRESS
));
6126 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
6127 (long unsigned int)exit_qualification
);
6128 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6129 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
6134 * EPT violation happened while executing iret from NMI,
6135 * "blocked by NMI" bit has to be set before next VM entry.
6136 * There are errata that may cause this bit to not be set:
6139 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6140 cpu_has_virtual_nmis() &&
6141 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
6142 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
6144 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6145 trace_kvm_page_fault(gpa
, exit_qualification
);
6147 /* it is a read fault? */
6148 error_code
= (exit_qualification
<< 2) & PFERR_USER_MASK
;
6149 /* it is a write fault? */
6150 error_code
|= exit_qualification
& PFERR_WRITE_MASK
;
6151 /* It is a fetch fault? */
6152 error_code
|= (exit_qualification
<< 2) & PFERR_FETCH_MASK
;
6153 /* ept page table is present? */
6154 error_code
|= (exit_qualification
& 0x38) != 0;
6156 vcpu
->arch
.exit_qualification
= exit_qualification
;
6158 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
6161 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
6166 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6167 if (!kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
6168 skip_emulated_instruction(vcpu
);
6169 trace_kvm_fast_mmio(gpa
);
6173 ret
= handle_mmio_page_fault(vcpu
, gpa
, true);
6174 if (likely(ret
== RET_MMIO_PF_EMULATE
))
6175 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
6178 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
6179 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
6181 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
6184 /* It is the real ept misconfig */
6187 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6188 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6193 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6195 u32 cpu_based_vm_exec_control
;
6197 /* clear pending NMI */
6198 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6199 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
6200 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
6201 ++vcpu
->stat
.nmi_window_exits
;
6202 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6207 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6209 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6210 enum emulation_result err
= EMULATE_DONE
;
6213 bool intr_window_requested
;
6214 unsigned count
= 130;
6216 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6217 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6219 while (vmx
->emulation_required
&& count
-- != 0) {
6220 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6221 return handle_interrupt_window(&vmx
->vcpu
);
6223 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
6226 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
6228 if (err
== EMULATE_USER_EXIT
) {
6229 ++vcpu
->stat
.mmio_exits
;
6234 if (err
!= EMULATE_DONE
) {
6235 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6236 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6237 vcpu
->run
->internal
.ndata
= 0;
6241 if (vcpu
->arch
.halt_request
) {
6242 vcpu
->arch
.halt_request
= 0;
6243 ret
= kvm_vcpu_halt(vcpu
);
6247 if (signal_pending(current
))
6257 static int __grow_ple_window(int val
)
6259 if (ple_window_grow
< 1)
6262 val
= min(val
, ple_window_actual_max
);
6264 if (ple_window_grow
< ple_window
)
6265 val
*= ple_window_grow
;
6267 val
+= ple_window_grow
;
6272 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6277 if (modifier
< ple_window
)
6282 return max(val
, minimum
);
6285 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6287 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6288 int old
= vmx
->ple_window
;
6290 vmx
->ple_window
= __grow_ple_window(old
);
6292 if (vmx
->ple_window
!= old
)
6293 vmx
->ple_window_dirty
= true;
6295 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6298 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6300 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6301 int old
= vmx
->ple_window
;
6303 vmx
->ple_window
= __shrink_ple_window(old
,
6304 ple_window_shrink
, ple_window
);
6306 if (vmx
->ple_window
!= old
)
6307 vmx
->ple_window_dirty
= true;
6309 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6313 * ple_window_actual_max is computed to be one grow_ple_window() below
6314 * ple_window_max. (See __grow_ple_window for the reason.)
6315 * This prevents overflows, because ple_window_max is int.
6316 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6318 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6320 static void update_ple_window_actual_max(void)
6322 ple_window_actual_max
=
6323 __shrink_ple_window(max(ple_window_max
, ple_window
),
6324 ple_window_grow
, INT_MIN
);
6328 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6330 static void wakeup_handler(void)
6332 struct kvm_vcpu
*vcpu
;
6333 int cpu
= smp_processor_id();
6335 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6336 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6337 blocked_vcpu_list
) {
6338 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6340 if (pi_test_on(pi_desc
) == 1)
6341 kvm_vcpu_kick(vcpu
);
6343 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6346 static __init
int hardware_setup(void)
6348 int r
= -ENOMEM
, i
, msr
;
6350 rdmsrl_safe(MSR_EFER
, &host_efer
);
6352 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6353 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6355 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6356 if (!vmx_io_bitmap_a
)
6359 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6360 if (!vmx_io_bitmap_b
)
6363 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6364 if (!vmx_msr_bitmap_legacy
)
6367 vmx_msr_bitmap_legacy_x2apic
=
6368 (unsigned long *)__get_free_page(GFP_KERNEL
);
6369 if (!vmx_msr_bitmap_legacy_x2apic
)
6372 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6373 if (!vmx_msr_bitmap_longmode
)
6376 vmx_msr_bitmap_longmode_x2apic
=
6377 (unsigned long *)__get_free_page(GFP_KERNEL
);
6378 if (!vmx_msr_bitmap_longmode_x2apic
)
6381 vmx_vmread_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6382 if (!vmx_vmread_bitmap
)
6385 vmx_vmwrite_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6386 if (!vmx_vmwrite_bitmap
)
6389 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6390 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6393 * Allow direct access to the PC debug port (it is often used for I/O
6394 * delays, but the vmexits simply slow things down).
6396 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6397 clear_bit(0x80, vmx_io_bitmap_a
);
6399 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6401 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6402 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6404 if (setup_vmcs_config(&vmcs_config
) < 0) {
6409 if (boot_cpu_has(X86_FEATURE_NX
))
6410 kvm_enable_efer_bits(EFER_NX
);
6412 if (!cpu_has_vmx_vpid())
6414 if (!cpu_has_vmx_shadow_vmcs())
6415 enable_shadow_vmcs
= 0;
6416 if (enable_shadow_vmcs
)
6417 init_vmcs_shadow_fields();
6419 if (!cpu_has_vmx_ept() ||
6420 !cpu_has_vmx_ept_4levels()) {
6422 enable_unrestricted_guest
= 0;
6423 enable_ept_ad_bits
= 0;
6426 if (!cpu_has_vmx_ept_ad_bits())
6427 enable_ept_ad_bits
= 0;
6429 if (!cpu_has_vmx_unrestricted_guest())
6430 enable_unrestricted_guest
= 0;
6432 if (!cpu_has_vmx_flexpriority())
6433 flexpriority_enabled
= 0;
6436 * set_apic_access_page_addr() is used to reload apic access
6437 * page upon invalidation. No need to do anything if not
6438 * using the APIC_ACCESS_ADDR VMCS field.
6440 if (!flexpriority_enabled
)
6441 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6443 if (!cpu_has_vmx_tpr_shadow())
6444 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6446 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6447 kvm_disable_largepages();
6449 if (!cpu_has_vmx_ple())
6452 if (!cpu_has_vmx_apicv())
6455 if (cpu_has_vmx_tsc_scaling()) {
6456 kvm_has_tsc_control
= true;
6457 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
6458 kvm_tsc_scaling_ratio_frac_bits
= 48;
6461 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6462 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6463 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6464 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6465 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6466 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6467 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS
, true);
6469 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6470 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6471 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6472 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6474 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6476 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
6477 vmx_disable_intercept_msr_read_x2apic(msr
);
6480 vmx_enable_intercept_msr_read_x2apic(0x839);
6482 vmx_disable_intercept_msr_write_x2apic(0x808);
6484 vmx_disable_intercept_msr_write_x2apic(0x80b);
6486 vmx_disable_intercept_msr_write_x2apic(0x83f);
6489 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK
,
6490 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
6491 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
6492 0ull, VMX_EPT_EXECUTABLE_MASK
,
6493 cpu_has_vmx_ept_execute_only() ?
6494 0ull : VMX_EPT_READABLE_MASK
);
6495 ept_set_mmio_spte_mask();
6500 update_ple_window_actual_max();
6503 * Only enable PML when hardware supports PML feature, and both EPT
6504 * and EPT A/D bit features are enabled -- PML depends on them to work.
6506 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6510 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6511 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6512 kvm_x86_ops
->flush_log_dirty
= NULL
;
6513 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6516 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer
) {
6519 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
6520 cpu_preemption_timer_multi
=
6521 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
6523 kvm_x86_ops
->set_hv_timer
= NULL
;
6524 kvm_x86_ops
->cancel_hv_timer
= NULL
;
6527 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6529 kvm_mce_cap_supported
|= MCG_LMCE_P
;
6531 return alloc_kvm_area();
6534 free_page((unsigned long)vmx_vmwrite_bitmap
);
6536 free_page((unsigned long)vmx_vmread_bitmap
);
6538 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
6540 free_page((unsigned long)vmx_msr_bitmap_longmode
);
6542 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
6544 free_page((unsigned long)vmx_msr_bitmap_legacy
);
6546 free_page((unsigned long)vmx_io_bitmap_b
);
6548 free_page((unsigned long)vmx_io_bitmap_a
);
6553 static __exit
void hardware_unsetup(void)
6555 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
6556 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
6557 free_page((unsigned long)vmx_msr_bitmap_legacy
);
6558 free_page((unsigned long)vmx_msr_bitmap_longmode
);
6559 free_page((unsigned long)vmx_io_bitmap_b
);
6560 free_page((unsigned long)vmx_io_bitmap_a
);
6561 free_page((unsigned long)vmx_vmwrite_bitmap
);
6562 free_page((unsigned long)vmx_vmread_bitmap
);
6568 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6569 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6571 static int handle_pause(struct kvm_vcpu
*vcpu
)
6574 grow_ple_window(vcpu
);
6576 skip_emulated_instruction(vcpu
);
6577 kvm_vcpu_on_spin(vcpu
);
6582 static int handle_nop(struct kvm_vcpu
*vcpu
)
6584 skip_emulated_instruction(vcpu
);
6588 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6590 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6591 return handle_nop(vcpu
);
6594 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6599 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6601 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6602 return handle_nop(vcpu
);
6606 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6607 * We could reuse a single VMCS for all the L2 guests, but we also want the
6608 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6609 * allows keeping them loaded on the processor, and in the future will allow
6610 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6611 * every entry if they never change.
6612 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6613 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6615 * The following functions allocate and free a vmcs02 in this pool.
6618 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6619 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6621 struct vmcs02_list
*item
;
6622 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6623 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6624 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6625 return &item
->vmcs02
;
6628 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6629 /* Recycle the least recently used VMCS. */
6630 item
= list_last_entry(&vmx
->nested
.vmcs02_pool
,
6631 struct vmcs02_list
, list
);
6632 item
->vmptr
= vmx
->nested
.current_vmptr
;
6633 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6634 return &item
->vmcs02
;
6637 /* Create a new VMCS */
6638 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6641 item
->vmcs02
.vmcs
= alloc_vmcs();
6642 if (!item
->vmcs02
.vmcs
) {
6646 loaded_vmcs_init(&item
->vmcs02
);
6647 item
->vmptr
= vmx
->nested
.current_vmptr
;
6648 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6649 vmx
->nested
.vmcs02_num
++;
6650 return &item
->vmcs02
;
6653 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6654 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6656 struct vmcs02_list
*item
;
6657 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6658 if (item
->vmptr
== vmptr
) {
6659 free_loaded_vmcs(&item
->vmcs02
);
6660 list_del(&item
->list
);
6662 vmx
->nested
.vmcs02_num
--;
6668 * Free all VMCSs saved for this vcpu, except the one pointed by
6669 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6670 * must be &vmx->vmcs01.
6672 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
6674 struct vmcs02_list
*item
, *n
;
6676 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
6677 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
6679 * Something will leak if the above WARN triggers. Better than
6682 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
6685 free_loaded_vmcs(&item
->vmcs02
);
6686 list_del(&item
->list
);
6688 vmx
->nested
.vmcs02_num
--;
6693 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6694 * set the success or error code of an emulated VMX instruction, as specified
6695 * by Vol 2B, VMX Instruction Reference, "Conventions".
6697 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6699 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6700 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6701 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6704 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6706 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6707 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6708 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6712 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6713 u32 vm_instruction_error
)
6715 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
6717 * failValid writes the error number to the current VMCS, which
6718 * can't be done there isn't a current VMCS.
6720 nested_vmx_failInvalid(vcpu
);
6723 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6724 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6725 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6727 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
6729 * We don't need to force a shadow sync because
6730 * VM_INSTRUCTION_ERROR is not shadowed
6734 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
6736 /* TODO: not to reset guest simply here. */
6737 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6738 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator
);
6741 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
6743 struct vcpu_vmx
*vmx
=
6744 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
6746 vmx
->nested
.preemption_timer_expired
= true;
6747 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6748 kvm_vcpu_kick(&vmx
->vcpu
);
6750 return HRTIMER_NORESTART
;
6754 * Decode the memory-address operand of a vmx instruction, as recorded on an
6755 * exit caused by such an instruction (run by a guest hypervisor).
6756 * On success, returns 0. When the operand is invalid, returns 1 and throws
6759 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
6760 unsigned long exit_qualification
,
6761 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
6765 struct kvm_segment s
;
6768 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6769 * Execution", on an exit, vmx_instruction_info holds most of the
6770 * addressing components of the operand. Only the displacement part
6771 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6772 * For how an actual address is calculated from all these components,
6773 * refer to Vol. 1, "Operand Addressing".
6775 int scaling
= vmx_instruction_info
& 3;
6776 int addr_size
= (vmx_instruction_info
>> 7) & 7;
6777 bool is_reg
= vmx_instruction_info
& (1u << 10);
6778 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
6779 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
6780 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
6781 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
6782 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
6785 kvm_queue_exception(vcpu
, UD_VECTOR
);
6789 /* Addr = segment_base + offset */
6790 /* offset = base + [index * scale] + displacement */
6791 off
= exit_qualification
; /* holds the displacement */
6793 off
+= kvm_register_read(vcpu
, base_reg
);
6795 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
6796 vmx_get_segment(vcpu
, &s
, seg_reg
);
6797 *ret
= s
.base
+ off
;
6799 if (addr_size
== 1) /* 32 bit */
6802 /* Checks for #GP/#SS exceptions. */
6804 if (is_long_mode(vcpu
)) {
6805 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6806 * non-canonical form. This is the only check on the memory
6807 * destination for long mode!
6809 exn
= is_noncanonical_address(*ret
);
6810 } else if (is_protmode(vcpu
)) {
6811 /* Protected mode: apply checks for segment validity in the
6813 * - segment type check (#GP(0) may be thrown)
6814 * - usability check (#GP(0)/#SS(0))
6815 * - limit check (#GP(0)/#SS(0))
6818 /* #GP(0) if the destination operand is located in a
6819 * read-only data segment or any code segment.
6821 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
6823 /* #GP(0) if the source operand is located in an
6824 * execute-only code segment
6826 exn
= ((s
.type
& 0xa) == 8);
6828 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
6831 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6833 exn
= (s
.unusable
!= 0);
6834 /* Protected mode: #GP(0)/#SS(0) if the memory
6835 * operand is outside the segment limit.
6837 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
6840 kvm_queue_exception_e(vcpu
,
6841 seg_reg
== VCPU_SREG_SS
?
6842 SS_VECTOR
: GP_VECTOR
,
6851 * This function performs the various checks including
6852 * - if it's 4KB aligned
6853 * - No bits beyond the physical address width are set
6854 * - Returns 0 on success or else 1
6855 * (Intel SDM Section 30.3)
6857 static int nested_vmx_check_vmptr(struct kvm_vcpu
*vcpu
, int exit_reason
,
6862 struct x86_exception e
;
6864 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6865 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
6867 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6868 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
6871 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6872 sizeof(vmptr
), &e
)) {
6873 kvm_inject_page_fault(vcpu
, &e
);
6877 switch (exit_reason
) {
6878 case EXIT_REASON_VMON
:
6881 * The first 4 bytes of VMXON region contain the supported
6882 * VMCS revision identifier
6884 * Note - IA32_VMX_BASIC[48] will never be 1
6885 * for the nested case;
6886 * which replaces physical address width with 32
6889 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6890 nested_vmx_failInvalid(vcpu
);
6891 skip_emulated_instruction(vcpu
);
6895 page
= nested_get_page(vcpu
, vmptr
);
6897 *(u32
*)kmap(page
) != VMCS12_REVISION
) {
6898 nested_vmx_failInvalid(vcpu
);
6900 skip_emulated_instruction(vcpu
);
6904 vmx
->nested
.vmxon_ptr
= vmptr
;
6906 case EXIT_REASON_VMCLEAR
:
6907 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6908 nested_vmx_failValid(vcpu
,
6909 VMXERR_VMCLEAR_INVALID_ADDRESS
);
6910 skip_emulated_instruction(vcpu
);
6914 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6915 nested_vmx_failValid(vcpu
,
6916 VMXERR_VMCLEAR_VMXON_POINTER
);
6917 skip_emulated_instruction(vcpu
);
6921 case EXIT_REASON_VMPTRLD
:
6922 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6923 nested_vmx_failValid(vcpu
,
6924 VMXERR_VMPTRLD_INVALID_ADDRESS
);
6925 skip_emulated_instruction(vcpu
);
6929 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6930 nested_vmx_failValid(vcpu
,
6931 VMXERR_VMCLEAR_VMXON_POINTER
);
6932 skip_emulated_instruction(vcpu
);
6937 return 1; /* shouldn't happen */
6946 * Emulate the VMXON instruction.
6947 * Currently, we just remember that VMX is active, and do not save or even
6948 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6949 * do not currently need to store anything in that guest-allocated memory
6950 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6951 * argument is different from the VMXON pointer (which the spec says they do).
6953 static int handle_vmon(struct kvm_vcpu
*vcpu
)
6955 struct kvm_segment cs
;
6956 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6957 struct vmcs
*shadow_vmcs
;
6958 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
6959 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
6961 /* The Intel VMX Instruction Reference lists a bunch of bits that
6962 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6963 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6964 * Otherwise, we should fail with #UD. We test these now:
6966 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
6967 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
6968 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
6969 kvm_queue_exception(vcpu
, UD_VECTOR
);
6973 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6974 if (is_long_mode(vcpu
) && !cs
.l
) {
6975 kvm_queue_exception(vcpu
, UD_VECTOR
);
6979 if (vmx_get_cpl(vcpu
)) {
6980 kvm_inject_gp(vcpu
, 0);
6984 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMON
, NULL
))
6987 if (vmx
->nested
.vmxon
) {
6988 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
6989 skip_emulated_instruction(vcpu
);
6993 if ((vmx
->msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
6994 != VMXON_NEEDED_FEATURES
) {
6995 kvm_inject_gp(vcpu
, 0);
6999 if (cpu_has_vmx_msr_bitmap()) {
7000 vmx
->nested
.msr_bitmap
=
7001 (unsigned long *)__get_free_page(GFP_KERNEL
);
7002 if (!vmx
->nested
.msr_bitmap
)
7003 goto out_msr_bitmap
;
7006 vmx
->nested
.cached_vmcs12
= kmalloc(VMCS12_SIZE
, GFP_KERNEL
);
7007 if (!vmx
->nested
.cached_vmcs12
)
7008 goto out_cached_vmcs12
;
7010 if (enable_shadow_vmcs
) {
7011 shadow_vmcs
= alloc_vmcs();
7013 goto out_shadow_vmcs
;
7014 /* mark vmcs as shadow */
7015 shadow_vmcs
->revision_id
|= (1u << 31);
7016 /* init shadow vmcs */
7017 vmcs_clear(shadow_vmcs
);
7018 vmx
->nested
.current_shadow_vmcs
= shadow_vmcs
;
7021 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
7022 vmx
->nested
.vmcs02_num
= 0;
7024 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
7025 HRTIMER_MODE_REL_PINNED
);
7026 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
7028 vmx
->nested
.vmxon
= true;
7030 skip_emulated_instruction(vcpu
);
7031 nested_vmx_succeed(vcpu
);
7035 kfree(vmx
->nested
.cached_vmcs12
);
7038 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7045 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7046 * for running VMX instructions (except VMXON, whose prerequisites are
7047 * slightly different). It also specifies what exception to inject otherwise.
7049 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
7051 struct kvm_segment cs
;
7052 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7054 if (!vmx
->nested
.vmxon
) {
7055 kvm_queue_exception(vcpu
, UD_VECTOR
);
7059 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
7060 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
7061 (is_long_mode(vcpu
) && !cs
.l
)) {
7062 kvm_queue_exception(vcpu
, UD_VECTOR
);
7066 if (vmx_get_cpl(vcpu
)) {
7067 kvm_inject_gp(vcpu
, 0);
7074 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
7076 if (vmx
->nested
.current_vmptr
== -1ull)
7079 /* current_vmptr and current_vmcs12 are always set/reset together */
7080 if (WARN_ON(vmx
->nested
.current_vmcs12
== NULL
))
7083 if (enable_shadow_vmcs
) {
7084 /* copy to memory all shadowed fields in case
7085 they were modified */
7086 copy_shadow_to_vmcs12(vmx
);
7087 vmx
->nested
.sync_shadow_vmcs
= false;
7088 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
7089 SECONDARY_EXEC_SHADOW_VMCS
);
7090 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7092 vmx
->nested
.posted_intr_nv
= -1;
7094 /* Flush VMCS12 to guest memory */
7095 memcpy(vmx
->nested
.current_vmcs12
, vmx
->nested
.cached_vmcs12
,
7098 kunmap(vmx
->nested
.current_vmcs12_page
);
7099 nested_release_page(vmx
->nested
.current_vmcs12_page
);
7100 vmx
->nested
.current_vmptr
= -1ull;
7101 vmx
->nested
.current_vmcs12
= NULL
;
7105 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7106 * just stops using VMX.
7108 static void free_nested(struct vcpu_vmx
*vmx
)
7110 if (!vmx
->nested
.vmxon
)
7113 vmx
->nested
.vmxon
= false;
7114 free_vpid(vmx
->nested
.vpid02
);
7115 nested_release_vmcs12(vmx
);
7116 if (vmx
->nested
.msr_bitmap
) {
7117 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7118 vmx
->nested
.msr_bitmap
= NULL
;
7120 if (enable_shadow_vmcs
)
7121 free_vmcs(vmx
->nested
.current_shadow_vmcs
);
7122 kfree(vmx
->nested
.cached_vmcs12
);
7123 /* Unpin physical memory we referred to in current vmcs02 */
7124 if (vmx
->nested
.apic_access_page
) {
7125 nested_release_page(vmx
->nested
.apic_access_page
);
7126 vmx
->nested
.apic_access_page
= NULL
;
7128 if (vmx
->nested
.virtual_apic_page
) {
7129 nested_release_page(vmx
->nested
.virtual_apic_page
);
7130 vmx
->nested
.virtual_apic_page
= NULL
;
7132 if (vmx
->nested
.pi_desc_page
) {
7133 kunmap(vmx
->nested
.pi_desc_page
);
7134 nested_release_page(vmx
->nested
.pi_desc_page
);
7135 vmx
->nested
.pi_desc_page
= NULL
;
7136 vmx
->nested
.pi_desc
= NULL
;
7139 nested_free_all_saved_vmcss(vmx
);
7142 /* Emulate the VMXOFF instruction */
7143 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
7145 if (!nested_vmx_check_permission(vcpu
))
7147 free_nested(to_vmx(vcpu
));
7148 skip_emulated_instruction(vcpu
);
7149 nested_vmx_succeed(vcpu
);
7153 /* Emulate the VMCLEAR instruction */
7154 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
7156 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7158 struct vmcs12
*vmcs12
;
7161 if (!nested_vmx_check_permission(vcpu
))
7164 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMCLEAR
, &vmptr
))
7167 if (vmptr
== vmx
->nested
.current_vmptr
)
7168 nested_release_vmcs12(vmx
);
7170 page
= nested_get_page(vcpu
, vmptr
);
7173 * For accurate processor emulation, VMCLEAR beyond available
7174 * physical memory should do nothing at all. However, it is
7175 * possible that a nested vmx bug, not a guest hypervisor bug,
7176 * resulted in this case, so let's shut down before doing any
7179 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
7182 vmcs12
= kmap(page
);
7183 vmcs12
->launch_state
= 0;
7185 nested_release_page(page
);
7187 nested_free_vmcs02(vmx
, vmptr
);
7189 skip_emulated_instruction(vcpu
);
7190 nested_vmx_succeed(vcpu
);
7194 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
7196 /* Emulate the VMLAUNCH instruction */
7197 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
7199 return nested_vmx_run(vcpu
, true);
7202 /* Emulate the VMRESUME instruction */
7203 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
7206 return nested_vmx_run(vcpu
, false);
7209 enum vmcs_field_type
{
7210 VMCS_FIELD_TYPE_U16
= 0,
7211 VMCS_FIELD_TYPE_U64
= 1,
7212 VMCS_FIELD_TYPE_U32
= 2,
7213 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
7216 static inline int vmcs_field_type(unsigned long field
)
7218 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
7219 return VMCS_FIELD_TYPE_U32
;
7220 return (field
>> 13) & 0x3 ;
7223 static inline int vmcs_field_readonly(unsigned long field
)
7225 return (((field
>> 10) & 0x3) == 1);
7229 * Read a vmcs12 field. Since these can have varying lengths and we return
7230 * one type, we chose the biggest type (u64) and zero-extend the return value
7231 * to that size. Note that the caller, handle_vmread, might need to use only
7232 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7233 * 64-bit fields are to be returned).
7235 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7236 unsigned long field
, u64
*ret
)
7238 short offset
= vmcs_field_to_offset(field
);
7244 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7246 switch (vmcs_field_type(field
)) {
7247 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7248 *ret
= *((natural_width
*)p
);
7250 case VMCS_FIELD_TYPE_U16
:
7253 case VMCS_FIELD_TYPE_U32
:
7256 case VMCS_FIELD_TYPE_U64
:
7266 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7267 unsigned long field
, u64 field_value
){
7268 short offset
= vmcs_field_to_offset(field
);
7269 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7273 switch (vmcs_field_type(field
)) {
7274 case VMCS_FIELD_TYPE_U16
:
7275 *(u16
*)p
= field_value
;
7277 case VMCS_FIELD_TYPE_U32
:
7278 *(u32
*)p
= field_value
;
7280 case VMCS_FIELD_TYPE_U64
:
7281 *(u64
*)p
= field_value
;
7283 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7284 *(natural_width
*)p
= field_value
;
7293 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7296 unsigned long field
;
7298 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
7299 const unsigned long *fields
= shadow_read_write_fields
;
7300 const int num_fields
= max_shadow_read_write_fields
;
7304 vmcs_load(shadow_vmcs
);
7306 for (i
= 0; i
< num_fields
; i
++) {
7308 switch (vmcs_field_type(field
)) {
7309 case VMCS_FIELD_TYPE_U16
:
7310 field_value
= vmcs_read16(field
);
7312 case VMCS_FIELD_TYPE_U32
:
7313 field_value
= vmcs_read32(field
);
7315 case VMCS_FIELD_TYPE_U64
:
7316 field_value
= vmcs_read64(field
);
7318 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7319 field_value
= vmcs_readl(field
);
7325 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7328 vmcs_clear(shadow_vmcs
);
7329 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7334 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7336 const unsigned long *fields
[] = {
7337 shadow_read_write_fields
,
7338 shadow_read_only_fields
7340 const int max_fields
[] = {
7341 max_shadow_read_write_fields
,
7342 max_shadow_read_only_fields
7345 unsigned long field
;
7346 u64 field_value
= 0;
7347 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
7349 vmcs_load(shadow_vmcs
);
7351 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7352 for (i
= 0; i
< max_fields
[q
]; i
++) {
7353 field
= fields
[q
][i
];
7354 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7356 switch (vmcs_field_type(field
)) {
7357 case VMCS_FIELD_TYPE_U16
:
7358 vmcs_write16(field
, (u16
)field_value
);
7360 case VMCS_FIELD_TYPE_U32
:
7361 vmcs_write32(field
, (u32
)field_value
);
7363 case VMCS_FIELD_TYPE_U64
:
7364 vmcs_write64(field
, (u64
)field_value
);
7366 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7367 vmcs_writel(field
, (long)field_value
);
7376 vmcs_clear(shadow_vmcs
);
7377 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7381 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7382 * used before) all generate the same failure when it is missing.
7384 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7386 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7387 if (vmx
->nested
.current_vmptr
== -1ull) {
7388 nested_vmx_failInvalid(vcpu
);
7389 skip_emulated_instruction(vcpu
);
7395 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7397 unsigned long field
;
7399 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7400 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7403 if (!nested_vmx_check_permission(vcpu
) ||
7404 !nested_vmx_check_vmcs12(vcpu
))
7407 /* Decode instruction info and find the field to read */
7408 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7409 /* Read the field, zero-extended to a u64 field_value */
7410 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7411 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7412 skip_emulated_instruction(vcpu
);
7416 * Now copy part of this value to register or memory, as requested.
7417 * Note that the number of bits actually copied is 32 or 64 depending
7418 * on the guest's mode (32 or 64 bit), not on the given field's length.
7420 if (vmx_instruction_info
& (1u << 10)) {
7421 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7424 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7425 vmx_instruction_info
, true, &gva
))
7427 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7428 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7429 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7432 nested_vmx_succeed(vcpu
);
7433 skip_emulated_instruction(vcpu
);
7438 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7440 unsigned long field
;
7442 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7443 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7444 /* The value to write might be 32 or 64 bits, depending on L1's long
7445 * mode, and eventually we need to write that into a field of several
7446 * possible lengths. The code below first zero-extends the value to 64
7447 * bit (field_value), and then copies only the appropriate number of
7448 * bits into the vmcs12 field.
7450 u64 field_value
= 0;
7451 struct x86_exception e
;
7453 if (!nested_vmx_check_permission(vcpu
) ||
7454 !nested_vmx_check_vmcs12(vcpu
))
7457 if (vmx_instruction_info
& (1u << 10))
7458 field_value
= kvm_register_readl(vcpu
,
7459 (((vmx_instruction_info
) >> 3) & 0xf));
7461 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7462 vmx_instruction_info
, false, &gva
))
7464 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7465 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7466 kvm_inject_page_fault(vcpu
, &e
);
7472 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7473 if (vmcs_field_readonly(field
)) {
7474 nested_vmx_failValid(vcpu
,
7475 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7476 skip_emulated_instruction(vcpu
);
7480 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7481 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7482 skip_emulated_instruction(vcpu
);
7486 nested_vmx_succeed(vcpu
);
7487 skip_emulated_instruction(vcpu
);
7491 /* Emulate the VMPTRLD instruction */
7492 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7494 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7497 if (!nested_vmx_check_permission(vcpu
))
7500 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMPTRLD
, &vmptr
))
7503 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7504 struct vmcs12
*new_vmcs12
;
7506 page
= nested_get_page(vcpu
, vmptr
);
7508 nested_vmx_failInvalid(vcpu
);
7509 skip_emulated_instruction(vcpu
);
7512 new_vmcs12
= kmap(page
);
7513 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7515 nested_release_page_clean(page
);
7516 nested_vmx_failValid(vcpu
,
7517 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7518 skip_emulated_instruction(vcpu
);
7522 nested_release_vmcs12(vmx
);
7523 vmx
->nested
.current_vmptr
= vmptr
;
7524 vmx
->nested
.current_vmcs12
= new_vmcs12
;
7525 vmx
->nested
.current_vmcs12_page
= page
;
7527 * Load VMCS12 from guest memory since it is not already
7530 memcpy(vmx
->nested
.cached_vmcs12
,
7531 vmx
->nested
.current_vmcs12
, VMCS12_SIZE
);
7533 if (enable_shadow_vmcs
) {
7534 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7535 SECONDARY_EXEC_SHADOW_VMCS
);
7536 vmcs_write64(VMCS_LINK_POINTER
,
7537 __pa(vmx
->nested
.current_shadow_vmcs
));
7538 vmx
->nested
.sync_shadow_vmcs
= true;
7542 nested_vmx_succeed(vcpu
);
7543 skip_emulated_instruction(vcpu
);
7547 /* Emulate the VMPTRST instruction */
7548 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7550 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7551 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7553 struct x86_exception e
;
7555 if (!nested_vmx_check_permission(vcpu
))
7558 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7559 vmx_instruction_info
, true, &vmcs_gva
))
7561 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7562 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7563 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7565 kvm_inject_page_fault(vcpu
, &e
);
7568 nested_vmx_succeed(vcpu
);
7569 skip_emulated_instruction(vcpu
);
7573 /* Emulate the INVEPT instruction */
7574 static int handle_invept(struct kvm_vcpu
*vcpu
)
7576 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7577 u32 vmx_instruction_info
, types
;
7580 struct x86_exception e
;
7585 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7586 SECONDARY_EXEC_ENABLE_EPT
) ||
7587 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7588 kvm_queue_exception(vcpu
, UD_VECTOR
);
7592 if (!nested_vmx_check_permission(vcpu
))
7595 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
7596 kvm_queue_exception(vcpu
, UD_VECTOR
);
7600 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7601 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7603 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7605 if (!(types
& (1UL << type
))) {
7606 nested_vmx_failValid(vcpu
,
7607 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7608 skip_emulated_instruction(vcpu
);
7612 /* According to the Intel VMX instruction reference, the memory
7613 * operand is read even if it isn't needed (e.g., for type==global)
7615 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7616 vmx_instruction_info
, false, &gva
))
7618 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7619 sizeof(operand
), &e
)) {
7620 kvm_inject_page_fault(vcpu
, &e
);
7625 case VMX_EPT_EXTENT_GLOBAL
:
7627 * TODO: track mappings and invalidate
7628 * single context requests appropriately
7630 case VMX_EPT_EXTENT_CONTEXT
:
7631 kvm_mmu_sync_roots(vcpu
);
7632 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7633 nested_vmx_succeed(vcpu
);
7640 skip_emulated_instruction(vcpu
);
7644 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7646 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7647 u32 vmx_instruction_info
;
7648 unsigned long type
, types
;
7650 struct x86_exception e
;
7653 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7654 SECONDARY_EXEC_ENABLE_VPID
) ||
7655 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7656 kvm_queue_exception(vcpu
, UD_VECTOR
);
7660 if (!nested_vmx_check_permission(vcpu
))
7663 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7664 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7666 types
= (vmx
->nested
.nested_vmx_vpid_caps
>> 8) & 0x7;
7668 if (!(types
& (1UL << type
))) {
7669 nested_vmx_failValid(vcpu
,
7670 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7671 skip_emulated_instruction(vcpu
);
7675 /* according to the intel vmx instruction reference, the memory
7676 * operand is read even if it isn't needed (e.g., for type==global)
7678 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7679 vmx_instruction_info
, false, &gva
))
7681 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vpid
,
7683 kvm_inject_page_fault(vcpu
, &e
);
7688 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
7690 * Old versions of KVM use the single-context version so we
7691 * have to support it; just treat it the same as all-context.
7693 case VMX_VPID_EXTENT_ALL_CONTEXT
:
7694 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
7695 nested_vmx_succeed(vcpu
);
7698 /* Trap individual address invalidation invvpid calls */
7703 skip_emulated_instruction(vcpu
);
7707 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7709 unsigned long exit_qualification
;
7711 trace_kvm_pml_full(vcpu
->vcpu_id
);
7713 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7716 * PML buffer FULL happened while executing iret from NMI,
7717 * "blocked by NMI" bit has to be set before next VM entry.
7719 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7720 cpu_has_virtual_nmis() &&
7721 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7722 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7723 GUEST_INTR_STATE_NMI
);
7726 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7727 * here.., and there's no userspace involvement needed for PML.
7732 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
7734 kvm_lapic_expired_hv_timer(vcpu
);
7739 * The exit handlers return 1 if the exit was handled fully and guest execution
7740 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7741 * to be done to userspace and return 0.
7743 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
7744 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
7745 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
7746 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
7747 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
7748 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
7749 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
7750 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
7751 [EXIT_REASON_CPUID
] = handle_cpuid
,
7752 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
7753 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
7754 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
7755 [EXIT_REASON_HLT
] = handle_halt
,
7756 [EXIT_REASON_INVD
] = handle_invd
,
7757 [EXIT_REASON_INVLPG
] = handle_invlpg
,
7758 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
7759 [EXIT_REASON_VMCALL
] = handle_vmcall
,
7760 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
7761 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
7762 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
7763 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
7764 [EXIT_REASON_VMREAD
] = handle_vmread
,
7765 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
7766 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
7767 [EXIT_REASON_VMOFF
] = handle_vmoff
,
7768 [EXIT_REASON_VMON
] = handle_vmon
,
7769 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
7770 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
7771 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
7772 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
7773 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
7774 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
7775 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
7776 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
7777 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
7778 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
7779 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
7780 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
7781 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
7782 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
7783 [EXIT_REASON_INVEPT
] = handle_invept
,
7784 [EXIT_REASON_INVVPID
] = handle_invvpid
,
7785 [EXIT_REASON_XSAVES
] = handle_xsaves
,
7786 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
7787 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
7788 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
7791 static const int kvm_vmx_max_exit_handlers
=
7792 ARRAY_SIZE(kvm_vmx_exit_handlers
);
7794 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
7795 struct vmcs12
*vmcs12
)
7797 unsigned long exit_qualification
;
7798 gpa_t bitmap
, last_bitmap
;
7803 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
7804 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
7806 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7808 port
= exit_qualification
>> 16;
7809 size
= (exit_qualification
& 7) + 1;
7811 last_bitmap
= (gpa_t
)-1;
7816 bitmap
= vmcs12
->io_bitmap_a
;
7817 else if (port
< 0x10000)
7818 bitmap
= vmcs12
->io_bitmap_b
;
7821 bitmap
+= (port
& 0x7fff) / 8;
7823 if (last_bitmap
!= bitmap
)
7824 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
7826 if (b
& (1 << (port
& 7)))
7831 last_bitmap
= bitmap
;
7838 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7839 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7840 * disinterest in the current event (read or write a specific MSR) by using an
7841 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7843 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
7844 struct vmcs12
*vmcs12
, u32 exit_reason
)
7846 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7849 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
7853 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7854 * for the four combinations of read/write and low/high MSR numbers.
7855 * First we need to figure out which of the four to use:
7857 bitmap
= vmcs12
->msr_bitmap
;
7858 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
7860 if (msr_index
>= 0xc0000000) {
7861 msr_index
-= 0xc0000000;
7865 /* Then read the msr_index'th bit from this bitmap: */
7866 if (msr_index
< 1024*8) {
7868 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
7870 return 1 & (b
>> (msr_index
& 7));
7872 return true; /* let L1 handle the wrong parameter */
7876 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7877 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7878 * intercept (via guest_host_mask etc.) the current event.
7880 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
7881 struct vmcs12
*vmcs12
)
7883 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7884 int cr
= exit_qualification
& 15;
7885 int reg
= (exit_qualification
>> 8) & 15;
7886 unsigned long val
= kvm_register_readl(vcpu
, reg
);
7888 switch ((exit_qualification
>> 4) & 3) {
7889 case 0: /* mov to cr */
7892 if (vmcs12
->cr0_guest_host_mask
&
7893 (val
^ vmcs12
->cr0_read_shadow
))
7897 if ((vmcs12
->cr3_target_count
>= 1 &&
7898 vmcs12
->cr3_target_value0
== val
) ||
7899 (vmcs12
->cr3_target_count
>= 2 &&
7900 vmcs12
->cr3_target_value1
== val
) ||
7901 (vmcs12
->cr3_target_count
>= 3 &&
7902 vmcs12
->cr3_target_value2
== val
) ||
7903 (vmcs12
->cr3_target_count
>= 4 &&
7904 vmcs12
->cr3_target_value3
== val
))
7906 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
7910 if (vmcs12
->cr4_guest_host_mask
&
7911 (vmcs12
->cr4_read_shadow
^ val
))
7915 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
7921 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
7922 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
7925 case 1: /* mov from cr */
7928 if (vmcs12
->cpu_based_vm_exec_control
&
7929 CPU_BASED_CR3_STORE_EXITING
)
7933 if (vmcs12
->cpu_based_vm_exec_control
&
7934 CPU_BASED_CR8_STORE_EXITING
)
7941 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7942 * cr0. Other attempted changes are ignored, with no exit.
7944 if (vmcs12
->cr0_guest_host_mask
& 0xe &
7945 (val
^ vmcs12
->cr0_read_shadow
))
7947 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
7948 !(vmcs12
->cr0_read_shadow
& 0x1) &&
7957 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7958 * should handle it ourselves in L0 (and then continue L2). Only call this
7959 * when in is_guest_mode (L2).
7961 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
7963 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7964 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7965 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7966 u32 exit_reason
= vmx
->exit_reason
;
7968 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
7969 vmcs_readl(EXIT_QUALIFICATION
),
7970 vmx
->idt_vectoring_info
,
7972 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
7975 if (vmx
->nested
.nested_run_pending
)
7978 if (unlikely(vmx
->fail
)) {
7979 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
7980 vmcs_read32(VM_INSTRUCTION_ERROR
));
7984 switch (exit_reason
) {
7985 case EXIT_REASON_EXCEPTION_NMI
:
7986 if (!is_exception(intr_info
))
7988 else if (is_page_fault(intr_info
))
7990 else if (is_no_device(intr_info
) &&
7991 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
7993 else if (is_debug(intr_info
) &&
7995 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
7997 else if (is_breakpoint(intr_info
) &&
7998 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
8000 return vmcs12
->exception_bitmap
&
8001 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
8002 case EXIT_REASON_EXTERNAL_INTERRUPT
:
8004 case EXIT_REASON_TRIPLE_FAULT
:
8006 case EXIT_REASON_PENDING_INTERRUPT
:
8007 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
8008 case EXIT_REASON_NMI_WINDOW
:
8009 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
8010 case EXIT_REASON_TASK_SWITCH
:
8012 case EXIT_REASON_CPUID
:
8013 if (kvm_register_read(vcpu
, VCPU_REGS_RAX
) == 0xa)
8016 case EXIT_REASON_HLT
:
8017 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
8018 case EXIT_REASON_INVD
:
8020 case EXIT_REASON_INVLPG
:
8021 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8022 case EXIT_REASON_RDPMC
:
8023 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
8024 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
8025 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
8026 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
8027 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
8028 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
8029 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
8030 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
8031 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
8033 * VMX instructions trap unconditionally. This allows L1 to
8034 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8037 case EXIT_REASON_CR_ACCESS
:
8038 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
8039 case EXIT_REASON_DR_ACCESS
:
8040 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
8041 case EXIT_REASON_IO_INSTRUCTION
:
8042 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
8043 case EXIT_REASON_MSR_READ
:
8044 case EXIT_REASON_MSR_WRITE
:
8045 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
8046 case EXIT_REASON_INVALID_STATE
:
8048 case EXIT_REASON_MWAIT_INSTRUCTION
:
8049 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
8050 case EXIT_REASON_MONITOR_TRAP_FLAG
:
8051 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
8052 case EXIT_REASON_MONITOR_INSTRUCTION
:
8053 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
8054 case EXIT_REASON_PAUSE_INSTRUCTION
:
8055 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
8056 nested_cpu_has2(vmcs12
,
8057 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
8058 case EXIT_REASON_MCE_DURING_VMENTRY
:
8060 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
8061 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
8062 case EXIT_REASON_APIC_ACCESS
:
8063 return nested_cpu_has2(vmcs12
,
8064 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
8065 case EXIT_REASON_APIC_WRITE
:
8066 case EXIT_REASON_EOI_INDUCED
:
8067 /* apic_write and eoi_induced should exit unconditionally. */
8069 case EXIT_REASON_EPT_VIOLATION
:
8071 * L0 always deals with the EPT violation. If nested EPT is
8072 * used, and the nested mmu code discovers that the address is
8073 * missing in the guest EPT table (EPT12), the EPT violation
8074 * will be injected with nested_ept_inject_page_fault()
8077 case EXIT_REASON_EPT_MISCONFIG
:
8079 * L2 never uses directly L1's EPT, but rather L0's own EPT
8080 * table (shadow on EPT) or a merged EPT table that L0 built
8081 * (EPT on EPT). So any problems with the structure of the
8082 * table is L0's fault.
8085 case EXIT_REASON_WBINVD
:
8086 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
8087 case EXIT_REASON_XSETBV
:
8089 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
8091 * This should never happen, since it is not possible to
8092 * set XSS to a non-zero value---neither in L1 nor in L2.
8093 * If if it were, XSS would have to be checked against
8094 * the XSS exit bitmap in vmcs12.
8096 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
8097 case EXIT_REASON_PREEMPTION_TIMER
:
8104 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
8106 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
8107 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
8110 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
8113 __free_page(vmx
->pml_pg
);
8118 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
8120 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8124 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
8126 /* Do nothing if PML buffer is empty */
8127 if (pml_idx
== (PML_ENTITY_NUM
- 1))
8130 /* PML index always points to next available PML buffer entity */
8131 if (pml_idx
>= PML_ENTITY_NUM
)
8136 pml_buf
= page_address(vmx
->pml_pg
);
8137 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
8140 gpa
= pml_buf
[pml_idx
];
8141 WARN_ON(gpa
& (PAGE_SIZE
- 1));
8142 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
8145 /* reset PML index */
8146 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8150 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8151 * Called before reporting dirty_bitmap to userspace.
8153 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
8156 struct kvm_vcpu
*vcpu
;
8158 * We only need to kick vcpu out of guest mode here, as PML buffer
8159 * is flushed at beginning of all VMEXITs, and it's obvious that only
8160 * vcpus running in guest are possible to have unflushed GPAs in PML
8163 kvm_for_each_vcpu(i
, vcpu
, kvm
)
8164 kvm_vcpu_kick(vcpu
);
8167 static void vmx_dump_sel(char *name
, uint32_t sel
)
8169 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8170 name
, vmcs_read32(sel
),
8171 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8172 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8173 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8176 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8178 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8179 name
, vmcs_read32(limit
),
8180 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8183 static void dump_vmcs(void)
8185 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8186 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8187 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8188 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8189 u32 secondary_exec_control
= 0;
8190 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8191 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8194 if (cpu_has_secondary_exec_ctrls())
8195 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8197 pr_err("*** Guest State ***\n");
8198 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8199 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8200 vmcs_readl(CR0_GUEST_HOST_MASK
));
8201 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8202 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8203 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8204 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8205 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8207 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8208 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8209 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8210 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8212 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8213 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8214 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8215 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8216 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8217 vmcs_readl(GUEST_SYSENTER_ESP
),
8218 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8219 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8220 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8221 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8222 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8223 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8224 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8225 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8226 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8227 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8228 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8229 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8230 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8231 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8232 efer
, vmcs_read64(GUEST_IA32_PAT
));
8233 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8234 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8235 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8236 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8237 pr_err("PerfGlobCtl = 0x%016llx\n",
8238 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8239 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8240 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8241 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8242 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8243 vmcs_read32(GUEST_ACTIVITY_STATE
));
8244 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8245 pr_err("InterruptStatus = %04x\n",
8246 vmcs_read16(GUEST_INTR_STATUS
));
8248 pr_err("*** Host State ***\n");
8249 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8250 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8251 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8252 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8253 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8254 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8255 vmcs_read16(HOST_TR_SELECTOR
));
8256 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8257 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8258 vmcs_readl(HOST_TR_BASE
));
8259 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8260 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8261 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8262 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8263 vmcs_readl(HOST_CR4
));
8264 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8265 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8266 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8267 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8268 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8269 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8270 vmcs_read64(HOST_IA32_EFER
),
8271 vmcs_read64(HOST_IA32_PAT
));
8272 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8273 pr_err("PerfGlobCtl = 0x%016llx\n",
8274 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8276 pr_err("*** Control State ***\n");
8277 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8278 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8279 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8280 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8281 vmcs_read32(EXCEPTION_BITMAP
),
8282 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8283 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8284 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8285 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8286 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8287 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8288 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8289 vmcs_read32(VM_EXIT_INTR_INFO
),
8290 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8291 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8292 pr_err(" reason=%08x qualification=%016lx\n",
8293 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8294 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8295 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8296 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8297 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8298 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8299 pr_err("TSC Multiplier = 0x%016llx\n",
8300 vmcs_read64(TSC_MULTIPLIER
));
8301 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8302 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8303 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8304 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8305 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8306 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8307 n
= vmcs_read32(CR3_TARGET_COUNT
);
8308 for (i
= 0; i
+ 1 < n
; i
+= 4)
8309 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8310 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8311 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8313 pr_err("CR3 target%u=%016lx\n",
8314 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8315 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8316 pr_err("PLE Gap=%08x Window=%08x\n",
8317 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8318 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8319 pr_err("Virtual processor ID = 0x%04x\n",
8320 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8324 * The guest has exited. See if we can fix it or if we need userspace
8327 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8329 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8330 u32 exit_reason
= vmx
->exit_reason
;
8331 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8333 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8336 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8337 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8338 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8339 * mode as if vcpus is in root mode, the PML buffer must has been
8343 vmx_flush_pml_buffer(vcpu
);
8345 /* If guest state is invalid, start emulating */
8346 if (vmx
->emulation_required
)
8347 return handle_invalid_guest_state(vcpu
);
8349 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
8350 nested_vmx_vmexit(vcpu
, exit_reason
,
8351 vmcs_read32(VM_EXIT_INTR_INFO
),
8352 vmcs_readl(EXIT_QUALIFICATION
));
8356 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8358 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8359 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8364 if (unlikely(vmx
->fail
)) {
8365 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8366 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8367 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8373 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8374 * delivery event since it indicates guest is accessing MMIO.
8375 * The vm-exit can be triggered again after return to guest that
8376 * will cause infinite loop.
8378 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8379 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8380 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8381 exit_reason
!= EXIT_REASON_PML_FULL
&&
8382 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8383 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8384 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8385 vcpu
->run
->internal
.ndata
= 2;
8386 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8387 vcpu
->run
->internal
.data
[1] = exit_reason
;
8391 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
8392 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
8393 get_vmcs12(vcpu
))))) {
8394 if (vmx_interrupt_allowed(vcpu
)) {
8395 vmx
->soft_vnmi_blocked
= 0;
8396 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
8397 vcpu
->arch
.nmi_pending
) {
8399 * This CPU don't support us in finding the end of an
8400 * NMI-blocked window if the guest runs with IRQs
8401 * disabled. So we pull the trigger after 1 s of
8402 * futile waiting, but inform the user about this.
8404 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
8405 "state on VCPU %d after 1 s timeout\n",
8406 __func__
, vcpu
->vcpu_id
);
8407 vmx
->soft_vnmi_blocked
= 0;
8411 if (exit_reason
< kvm_vmx_max_exit_handlers
8412 && kvm_vmx_exit_handlers
[exit_reason
])
8413 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8415 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason
);
8416 kvm_queue_exception(vcpu
, UD_VECTOR
);
8421 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8423 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8425 if (is_guest_mode(vcpu
) &&
8426 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8429 if (irr
== -1 || tpr
< irr
) {
8430 vmcs_write32(TPR_THRESHOLD
, 0);
8434 vmcs_write32(TPR_THRESHOLD
, irr
);
8437 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8439 u32 sec_exec_control
;
8441 /* Postpone execution until vmcs01 is the current VMCS. */
8442 if (is_guest_mode(vcpu
)) {
8443 to_vmx(vcpu
)->nested
.change_vmcs01_virtual_x2apic_mode
= true;
8448 * There is not point to enable virtualize x2apic without enable
8451 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8452 !kvm_vcpu_apicv_active(vcpu
))
8455 if (!cpu_need_tpr_shadow(vcpu
))
8458 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8461 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8462 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8464 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8465 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8467 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8469 vmx_set_msr_bitmap(vcpu
);
8472 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8474 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8477 * Currently we do not handle the nested case where L2 has an
8478 * APIC access page of its own; that page is still pinned.
8479 * Hence, we skip the case where the VCPU is in guest mode _and_
8480 * L1 prepared an APIC access page for L2.
8482 * For the case where L1 and L2 share the same APIC access page
8483 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8484 * in the vmcs12), this function will only update either the vmcs01
8485 * or the vmcs02. If the former, the vmcs02 will be updated by
8486 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8487 * the next L2->L1 exit.
8489 if (!is_guest_mode(vcpu
) ||
8490 !nested_cpu_has2(get_vmcs12(&vmx
->vcpu
),
8491 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
8492 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8495 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
8503 status
= vmcs_read16(GUEST_INTR_STATUS
);
8505 if (max_isr
!= old
) {
8507 status
|= max_isr
<< 8;
8508 vmcs_write16(GUEST_INTR_STATUS
, status
);
8512 static void vmx_set_rvi(int vector
)
8520 status
= vmcs_read16(GUEST_INTR_STATUS
);
8521 old
= (u8
)status
& 0xff;
8522 if ((u8
)vector
!= old
) {
8524 status
|= (u8
)vector
;
8525 vmcs_write16(GUEST_INTR_STATUS
, status
);
8529 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8531 if (!is_guest_mode(vcpu
)) {
8532 vmx_set_rvi(max_irr
);
8540 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8543 if (nested_exit_on_intr(vcpu
))
8547 * Else, fall back to pre-APICv interrupt injection since L2
8548 * is run without virtual interrupt delivery.
8550 if (!kvm_event_needs_reinjection(vcpu
) &&
8551 vmx_interrupt_allowed(vcpu
)) {
8552 kvm_queue_interrupt(vcpu
, max_irr
, false);
8553 vmx_inject_irq(vcpu
);
8557 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
8559 if (!kvm_vcpu_apicv_active(vcpu
))
8562 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8563 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8564 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
8565 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
8568 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
8572 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
8573 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
8576 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8577 exit_intr_info
= vmx
->exit_intr_info
;
8579 /* Handle machine checks before interrupts are enabled */
8580 if (is_machine_check(exit_intr_info
))
8581 kvm_machine_check();
8583 /* We need to handle NMIs before interrupts are enabled */
8584 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
8585 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
8586 kvm_before_handle_nmi(&vmx
->vcpu
);
8588 kvm_after_handle_nmi(&vmx
->vcpu
);
8592 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
8594 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8595 register void *__sp
asm(_ASM_SP
);
8598 * If external interrupt exists, IF bit is set in rflags/eflags on the
8599 * interrupt stack frame, and interrupt will be enabled on a return
8600 * from interrupt handler.
8602 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
8603 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
8604 unsigned int vector
;
8605 unsigned long entry
;
8607 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8608 #ifdef CONFIG_X86_64
8612 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8613 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
8614 entry
= gate_offset(*desc
);
8616 #ifdef CONFIG_X86_64
8617 "mov %%" _ASM_SP
", %[sp]\n\t"
8618 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
8623 __ASM_SIZE(push
) " $%c[cs]\n\t"
8624 "call *%[entry]\n\t"
8626 #ifdef CONFIG_X86_64
8632 [ss
]"i"(__KERNEL_DS
),
8633 [cs
]"i"(__KERNEL_CS
)
8638 static bool vmx_has_high_real_mode_segbase(void)
8640 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
8643 static bool vmx_mpx_supported(void)
8645 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
8646 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
8649 static bool vmx_xsaves_supported(void)
8651 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
8652 SECONDARY_EXEC_XSAVES
;
8655 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
8660 bool idtv_info_valid
;
8662 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8664 if (cpu_has_virtual_nmis()) {
8665 if (vmx
->nmi_known_unmasked
)
8668 * Can't use vmx->exit_intr_info since we're not sure what
8669 * the exit reason is.
8671 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8672 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
8673 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8675 * SDM 3: 27.7.1.2 (September 2008)
8676 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8677 * a guest IRET fault.
8678 * SDM 3: 23.2.2 (September 2008)
8679 * Bit 12 is undefined in any of the following cases:
8680 * If the VM exit sets the valid bit in the IDT-vectoring
8681 * information field.
8682 * If the VM exit is due to a double fault.
8684 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
8685 vector
!= DF_VECTOR
&& !idtv_info_valid
)
8686 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8687 GUEST_INTR_STATE_NMI
);
8689 vmx
->nmi_known_unmasked
=
8690 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
8691 & GUEST_INTR_STATE_NMI
);
8692 } else if (unlikely(vmx
->soft_vnmi_blocked
))
8693 vmx
->vnmi_blocked_time
+=
8694 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
8697 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
8698 u32 idt_vectoring_info
,
8699 int instr_len_field
,
8700 int error_code_field
)
8704 bool idtv_info_valid
;
8706 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8708 vcpu
->arch
.nmi_injected
= false;
8709 kvm_clear_exception_queue(vcpu
);
8710 kvm_clear_interrupt_queue(vcpu
);
8712 if (!idtv_info_valid
)
8715 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8717 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
8718 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
8721 case INTR_TYPE_NMI_INTR
:
8722 vcpu
->arch
.nmi_injected
= true;
8724 * SDM 3: 27.7.1.2 (September 2008)
8725 * Clear bit "block by NMI" before VM entry if a NMI
8728 vmx_set_nmi_mask(vcpu
, false);
8730 case INTR_TYPE_SOFT_EXCEPTION
:
8731 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8733 case INTR_TYPE_HARD_EXCEPTION
:
8734 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
8735 u32 err
= vmcs_read32(error_code_field
);
8736 kvm_requeue_exception_e(vcpu
, vector
, err
);
8738 kvm_requeue_exception(vcpu
, vector
);
8740 case INTR_TYPE_SOFT_INTR
:
8741 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8743 case INTR_TYPE_EXT_INTR
:
8744 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
8751 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
8753 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
8754 VM_EXIT_INSTRUCTION_LEN
,
8755 IDT_VECTORING_ERROR_CODE
);
8758 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
8760 __vmx_complete_interrupts(vcpu
,
8761 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8762 VM_ENTRY_INSTRUCTION_LEN
,
8763 VM_ENTRY_EXCEPTION_ERROR_CODE
);
8765 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
8768 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
8771 struct perf_guest_switch_msr
*msrs
;
8773 msrs
= perf_guest_get_msrs(&nr_msrs
);
8778 for (i
= 0; i
< nr_msrs
; i
++)
8779 if (msrs
[i
].host
== msrs
[i
].guest
)
8780 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
8782 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
8786 void vmx_arm_hv_timer(struct kvm_vcpu
*vcpu
)
8788 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8792 if (vmx
->hv_deadline_tsc
== -1)
8796 if (vmx
->hv_deadline_tsc
> tscl
)
8797 /* sure to be 32 bit only because checked on set_hv_timer */
8798 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
8799 cpu_preemption_timer_multi
);
8803 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, delta_tsc
);
8806 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
8808 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8809 unsigned long debugctlmsr
, cr4
;
8811 /* Record the guest's net vcpu time for enforced NMI injections. */
8812 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
8813 vmx
->entry_time
= ktime_get();
8815 /* Don't enter VMX if guest state is invalid, let the exit handler
8816 start emulation until we arrive back to a valid state */
8817 if (vmx
->emulation_required
)
8820 if (vmx
->ple_window_dirty
) {
8821 vmx
->ple_window_dirty
= false;
8822 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
8825 if (vmx
->nested
.sync_shadow_vmcs
) {
8826 copy_vmcs12_to_shadow(vmx
);
8827 vmx
->nested
.sync_shadow_vmcs
= false;
8830 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8831 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
8832 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8833 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
8835 cr4
= cr4_read_shadow();
8836 if (unlikely(cr4
!= vmx
->host_state
.vmcs_host_cr4
)) {
8837 vmcs_writel(HOST_CR4
, cr4
);
8838 vmx
->host_state
.vmcs_host_cr4
= cr4
;
8841 /* When single-stepping over STI and MOV SS, we must clear the
8842 * corresponding interruptibility bits in the guest state. Otherwise
8843 * vmentry fails as it then expects bit 14 (BS) in pending debug
8844 * exceptions being set, but that's not correct for the guest debugging
8846 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
8847 vmx_set_interrupt_shadow(vcpu
, 0);
8849 if (vmx
->guest_pkru_valid
)
8850 __write_pkru(vmx
->guest_pkru
);
8852 atomic_switch_perf_msrs(vmx
);
8853 debugctlmsr
= get_debugctlmsr();
8855 vmx_arm_hv_timer(vcpu
);
8857 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
8859 /* Store host registers */
8860 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
8861 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
8862 "push %%" _ASM_CX
" \n\t"
8863 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8865 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8866 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
8868 /* Reload cr2 if changed */
8869 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
8870 "mov %%cr2, %%" _ASM_DX
" \n\t"
8871 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
8873 "mov %%" _ASM_AX
", %%cr2 \n\t"
8875 /* Check if vmlaunch of vmresume is needed */
8876 "cmpl $0, %c[launched](%0) \n\t"
8877 /* Load guest registers. Don't clobber flags. */
8878 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
8879 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
8880 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
8881 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
8882 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
8883 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
8884 #ifdef CONFIG_X86_64
8885 "mov %c[r8](%0), %%r8 \n\t"
8886 "mov %c[r9](%0), %%r9 \n\t"
8887 "mov %c[r10](%0), %%r10 \n\t"
8888 "mov %c[r11](%0), %%r11 \n\t"
8889 "mov %c[r12](%0), %%r12 \n\t"
8890 "mov %c[r13](%0), %%r13 \n\t"
8891 "mov %c[r14](%0), %%r14 \n\t"
8892 "mov %c[r15](%0), %%r15 \n\t"
8894 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
8896 /* Enter guest mode */
8898 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
8900 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
8902 /* Save guest registers, load host registers, keep flags */
8903 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
8905 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
8906 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
8907 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
8908 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
8909 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
8910 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
8911 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
8912 #ifdef CONFIG_X86_64
8913 "mov %%r8, %c[r8](%0) \n\t"
8914 "mov %%r9, %c[r9](%0) \n\t"
8915 "mov %%r10, %c[r10](%0) \n\t"
8916 "mov %%r11, %c[r11](%0) \n\t"
8917 "mov %%r12, %c[r12](%0) \n\t"
8918 "mov %%r13, %c[r13](%0) \n\t"
8919 "mov %%r14, %c[r14](%0) \n\t"
8920 "mov %%r15, %c[r15](%0) \n\t"
8922 "mov %%cr2, %%" _ASM_AX
" \n\t"
8923 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
8925 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
8926 "setbe %c[fail](%0) \n\t"
8927 ".pushsection .rodata \n\t"
8928 ".global vmx_return \n\t"
8929 "vmx_return: " _ASM_PTR
" 2b \n\t"
8931 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
8932 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
8933 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
8934 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
8935 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
8936 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
8937 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
8938 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
8939 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
8940 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
8941 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
8942 #ifdef CONFIG_X86_64
8943 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
8944 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
8945 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
8946 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
8947 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
8948 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
8949 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
8950 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
8952 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
8953 [wordsize
]"i"(sizeof(ulong
))
8955 #ifdef CONFIG_X86_64
8956 , "rax", "rbx", "rdi", "rsi"
8957 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8959 , "eax", "ebx", "edi", "esi"
8963 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8965 update_debugctlmsr(debugctlmsr
);
8967 #ifndef CONFIG_X86_64
8969 * The sysexit path does not restore ds/es, so we must set them to
8970 * a reasonable value ourselves.
8972 * We can't defer this to vmx_load_host_state() since that function
8973 * may be executed in interrupt context, which saves and restore segments
8974 * around it, nullifying its effect.
8976 loadsegment(ds
, __USER_DS
);
8977 loadsegment(es
, __USER_DS
);
8980 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
8981 | (1 << VCPU_EXREG_RFLAGS
)
8982 | (1 << VCPU_EXREG_PDPTR
)
8983 | (1 << VCPU_EXREG_SEGMENTS
)
8984 | (1 << VCPU_EXREG_CR3
));
8985 vcpu
->arch
.regs_dirty
= 0;
8987 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
8989 vmx
->loaded_vmcs
->launched
= 1;
8991 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
8994 * eager fpu is enabled if PKEY is supported and CR4 is switched
8995 * back on host, so it is safe to read guest PKRU from current
8998 if (boot_cpu_has(X86_FEATURE_OSPKE
)) {
8999 vmx
->guest_pkru
= __read_pkru();
9000 if (vmx
->guest_pkru
!= vmx
->host_pkru
) {
9001 vmx
->guest_pkru_valid
= true;
9002 __write_pkru(vmx
->host_pkru
);
9004 vmx
->guest_pkru_valid
= false;
9008 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9009 * we did not inject a still-pending event to L1 now because of
9010 * nested_run_pending, we need to re-enable this bit.
9012 if (vmx
->nested
.nested_run_pending
)
9013 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9015 vmx
->nested
.nested_run_pending
= 0;
9017 vmx_complete_atomic_exit(vmx
);
9018 vmx_recover_nmi_blocking(vmx
);
9019 vmx_complete_interrupts(vmx
);
9022 static void vmx_load_vmcs01(struct kvm_vcpu
*vcpu
)
9024 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9027 if (vmx
->loaded_vmcs
== &vmx
->vmcs01
)
9031 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9033 vmx_vcpu_load(vcpu
, cpu
);
9039 * Ensure that the current vmcs of the logical processor is the
9040 * vmcs01 of the vcpu before calling free_nested().
9042 static void vmx_free_vcpu_nested(struct kvm_vcpu
*vcpu
)
9044 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9047 r
= vcpu_load(vcpu
);
9049 vmx_load_vmcs01(vcpu
);
9054 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
9056 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9059 vmx_destroy_pml_buffer(vmx
);
9060 free_vpid(vmx
->vpid
);
9061 leave_guest_mode(vcpu
);
9062 vmx_free_vcpu_nested(vcpu
);
9063 free_loaded_vmcs(vmx
->loaded_vmcs
);
9064 kfree(vmx
->guest_msrs
);
9065 kvm_vcpu_uninit(vcpu
);
9066 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9069 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
9072 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
9076 return ERR_PTR(-ENOMEM
);
9078 vmx
->vpid
= allocate_vpid();
9080 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
9087 * If PML is turned on, failure on enabling PML just results in failure
9088 * of creating the vcpu, therefore we can simplify PML logic (by
9089 * avoiding dealing with cases, such as enabling PML partially on vcpus
9090 * for the guest, etc.
9093 vmx
->pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
9098 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
9099 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
9102 if (!vmx
->guest_msrs
)
9105 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9106 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
9107 if (!vmx
->loaded_vmcs
->vmcs
)
9110 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
9111 loaded_vmcs_init(vmx
->loaded_vmcs
);
9116 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
9117 vmx
->vcpu
.cpu
= cpu
;
9118 err
= vmx_vcpu_setup(vmx
);
9119 vmx_vcpu_put(&vmx
->vcpu
);
9123 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9124 err
= alloc_apic_access_page(kvm
);
9130 if (!kvm
->arch
.ept_identity_map_addr
)
9131 kvm
->arch
.ept_identity_map_addr
=
9132 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
9133 err
= init_rmode_identity_map(kvm
);
9139 nested_vmx_setup_ctls_msrs(vmx
);
9140 vmx
->nested
.vpid02
= allocate_vpid();
9143 vmx
->nested
.posted_intr_nv
= -1;
9144 vmx
->nested
.current_vmptr
= -1ull;
9145 vmx
->nested
.current_vmcs12
= NULL
;
9147 vmx
->msr_ia32_feature_control_valid_bits
= FEATURE_CONTROL_LOCKED
;
9152 free_vpid(vmx
->nested
.vpid02
);
9153 free_loaded_vmcs(vmx
->loaded_vmcs
);
9155 kfree(vmx
->guest_msrs
);
9157 vmx_destroy_pml_buffer(vmx
);
9159 kvm_vcpu_uninit(&vmx
->vcpu
);
9161 free_vpid(vmx
->vpid
);
9162 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9163 return ERR_PTR(err
);
9166 static void __init
vmx_check_processor_compat(void *rtn
)
9168 struct vmcs_config vmcs_conf
;
9171 if (setup_vmcs_config(&vmcs_conf
) < 0)
9173 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
9174 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
9175 smp_processor_id());
9180 static int get_ept_level(void)
9182 return VMX_EPT_DEFAULT_GAW
+ 1;
9185 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
9190 /* For VT-d and EPT combination
9191 * 1. MMIO: always map as UC
9193 * a. VT-d without snooping control feature: can't guarantee the
9194 * result, try to trust guest.
9195 * b. VT-d with snooping control feature: snooping control feature of
9196 * VT-d engine can guarantee the cache correctness. Just set it
9197 * to WB to keep consistent with host. So the same as item 3.
9198 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9199 * consistent with host MTRR
9202 cache
= MTRR_TYPE_UNCACHABLE
;
9206 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
9207 ipat
= VMX_EPT_IPAT_BIT
;
9208 cache
= MTRR_TYPE_WRBACK
;
9212 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
9213 ipat
= VMX_EPT_IPAT_BIT
;
9214 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9215 cache
= MTRR_TYPE_WRBACK
;
9217 cache
= MTRR_TYPE_UNCACHABLE
;
9221 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9224 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9227 static int vmx_get_lpage_level(void)
9229 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9230 return PT_DIRECTORY_LEVEL
;
9232 /* For shadow and EPT supported 1GB page */
9233 return PT_PDPE_LEVEL
;
9236 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9239 * These bits in the secondary execution controls field
9240 * are dynamic, the others are mostly based on the hypervisor
9241 * architecture and the guest's CPUID. Do not touch the
9245 SECONDARY_EXEC_SHADOW_VMCS
|
9246 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9247 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9249 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9251 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9252 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9255 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9257 struct kvm_cpuid_entry2
*best
;
9258 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9259 u32 secondary_exec_ctl
= vmx_secondary_exec_control(vmx
);
9261 if (vmx_rdtscp_supported()) {
9262 bool rdtscp_enabled
= guest_cpuid_has_rdtscp(vcpu
);
9263 if (!rdtscp_enabled
)
9264 secondary_exec_ctl
&= ~SECONDARY_EXEC_RDTSCP
;
9268 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
9269 SECONDARY_EXEC_RDTSCP
;
9271 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
9272 ~SECONDARY_EXEC_RDTSCP
;
9276 /* Exposing INVPCID only when PCID is exposed */
9277 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9278 if (vmx_invpcid_supported() &&
9279 (!best
|| !(best
->ebx
& bit(X86_FEATURE_INVPCID
)) ||
9280 !guest_cpuid_has_pcid(vcpu
))) {
9281 secondary_exec_ctl
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
9284 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
9287 if (cpu_has_secondary_exec_ctrls())
9288 vmcs_set_secondary_exec_control(secondary_exec_ctl
);
9290 if (nested_vmx_allowed(vcpu
))
9291 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
9292 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9294 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
9295 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9298 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9300 if (func
== 1 && nested
)
9301 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9304 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9305 struct x86_exception
*fault
)
9307 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9310 if (fault
->error_code
& PFERR_RSVD_MASK
)
9311 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9313 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9314 nested_vmx_vmexit(vcpu
, exit_reason
, 0, vcpu
->arch
.exit_qualification
);
9315 vmcs12
->guest_physical_address
= fault
->address
;
9318 /* Callbacks for nested_ept_init_mmu_context: */
9320 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
9322 /* return the page table to be shadowed - in our case, EPT12 */
9323 return get_vmcs12(vcpu
)->ept_pointer
;
9326 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
9328 WARN_ON(mmu_is_nested(vcpu
));
9329 kvm_init_shadow_ept_mmu(vcpu
,
9330 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
9331 VMX_EPT_EXECUTE_ONLY_BIT
);
9332 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
9333 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
9334 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
9336 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
9339 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
9341 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
9344 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
9347 bool inequality
, bit
;
9349 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
9351 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9352 vmcs12
->page_fault_error_code_match
;
9353 return inequality
^ bit
;
9356 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9357 struct x86_exception
*fault
)
9359 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9361 WARN_ON(!is_guest_mode(vcpu
));
9363 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
))
9364 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
9365 vmcs_read32(VM_EXIT_INTR_INFO
),
9366 vmcs_readl(EXIT_QUALIFICATION
));
9368 kvm_inject_page_fault(vcpu
, fault
);
9371 static bool nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
9372 struct vmcs12
*vmcs12
)
9374 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9375 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9377 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9378 if (!PAGE_ALIGNED(vmcs12
->apic_access_addr
) ||
9379 vmcs12
->apic_access_addr
>> maxphyaddr
)
9383 * Translate L1 physical address to host physical
9384 * address for vmcs02. Keep the page pinned, so this
9385 * physical address remains valid. We keep a reference
9386 * to it so we can release it later.
9388 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
9389 nested_release_page(vmx
->nested
.apic_access_page
);
9390 vmx
->nested
.apic_access_page
=
9391 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
9394 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9395 if (!PAGE_ALIGNED(vmcs12
->virtual_apic_page_addr
) ||
9396 vmcs12
->virtual_apic_page_addr
>> maxphyaddr
)
9399 if (vmx
->nested
.virtual_apic_page
) /* shouldn't happen */
9400 nested_release_page(vmx
->nested
.virtual_apic_page
);
9401 vmx
->nested
.virtual_apic_page
=
9402 nested_get_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9405 * Failing the vm entry is _not_ what the processor does
9406 * but it's basically the only possibility we have.
9407 * We could still enter the guest if CR8 load exits are
9408 * enabled, CR8 store exits are enabled, and virtualize APIC
9409 * access is disabled; in this case the processor would never
9410 * use the TPR shadow and we could simply clear the bit from
9411 * the execution control. But such a configuration is useless,
9412 * so let's keep the code simple.
9414 if (!vmx
->nested
.virtual_apic_page
)
9418 if (nested_cpu_has_posted_intr(vmcs12
)) {
9419 if (!IS_ALIGNED(vmcs12
->posted_intr_desc_addr
, 64) ||
9420 vmcs12
->posted_intr_desc_addr
>> maxphyaddr
)
9423 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
9424 kunmap(vmx
->nested
.pi_desc_page
);
9425 nested_release_page(vmx
->nested
.pi_desc_page
);
9427 vmx
->nested
.pi_desc_page
=
9428 nested_get_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
9429 if (!vmx
->nested
.pi_desc_page
)
9432 vmx
->nested
.pi_desc
=
9433 (struct pi_desc
*)kmap(vmx
->nested
.pi_desc_page
);
9434 if (!vmx
->nested
.pi_desc
) {
9435 nested_release_page_clean(vmx
->nested
.pi_desc_page
);
9438 vmx
->nested
.pi_desc
=
9439 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
9440 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9447 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
9449 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
9450 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9452 if (vcpu
->arch
.virtual_tsc_khz
== 0)
9455 /* Make sure short timeouts reliably trigger an immediate vmexit.
9456 * hrtimer_start does not guarantee this. */
9457 if (preemption_timeout
<= 1) {
9458 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
9462 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9463 preemption_timeout
*= 1000000;
9464 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
9465 hrtimer_start(&vmx
->nested
.preemption_timer
,
9466 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
9469 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
9470 struct vmcs12
*vmcs12
)
9475 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
9478 if (vmcs12_read_any(vcpu
, MSR_BITMAP
, &addr
)) {
9482 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9484 if (!PAGE_ALIGNED(vmcs12
->msr_bitmap
) ||
9485 ((addr
+ PAGE_SIZE
) >> maxphyaddr
))
9492 * Merge L0's and L1's MSR bitmap, return false to indicate that
9493 * we do not use the hardware.
9495 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9496 struct vmcs12
*vmcs12
)
9500 unsigned long *msr_bitmap_l1
;
9501 unsigned long *msr_bitmap_l0
= to_vmx(vcpu
)->nested
.msr_bitmap
;
9503 /* This shortcut is ok because we support only x2APIC MSRs so far. */
9504 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
9507 page
= nested_get_page(vcpu
, vmcs12
->msr_bitmap
);
9512 msr_bitmap_l1
= (unsigned long *)kmap(page
);
9513 if (!msr_bitmap_l1
) {
9514 nested_release_page_clean(page
);
9519 memset(msr_bitmap_l0
, 0xff, PAGE_SIZE
);
9521 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
9522 if (nested_cpu_has_apic_reg_virt(vmcs12
))
9523 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9524 nested_vmx_disable_intercept_for_msr(
9525 msr_bitmap_l1
, msr_bitmap_l0
,
9528 nested_vmx_disable_intercept_for_msr(
9529 msr_bitmap_l1
, msr_bitmap_l0
,
9530 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9531 MSR_TYPE_R
| MSR_TYPE_W
);
9533 if (nested_cpu_has_vid(vmcs12
)) {
9534 nested_vmx_disable_intercept_for_msr(
9535 msr_bitmap_l1
, msr_bitmap_l0
,
9536 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9538 nested_vmx_disable_intercept_for_msr(
9539 msr_bitmap_l1
, msr_bitmap_l0
,
9540 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9545 nested_release_page_clean(page
);
9550 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
9551 struct vmcs12
*vmcs12
)
9553 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9554 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
9555 !nested_cpu_has_vid(vmcs12
) &&
9556 !nested_cpu_has_posted_intr(vmcs12
))
9560 * If virtualize x2apic mode is enabled,
9561 * virtualize apic access must be disabled.
9563 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9564 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
9568 * If virtual interrupt delivery is enabled,
9569 * we must exit on external interrupts.
9571 if (nested_cpu_has_vid(vmcs12
) &&
9572 !nested_exit_on_intr(vcpu
))
9576 * bits 15:8 should be zero in posted_intr_nv,
9577 * the descriptor address has been already checked
9578 * in nested_get_vmcs12_pages.
9580 if (nested_cpu_has_posted_intr(vmcs12
) &&
9581 (!nested_cpu_has_vid(vmcs12
) ||
9582 !nested_exit_intr_ack_set(vcpu
) ||
9583 vmcs12
->posted_intr_nv
& 0xff00))
9586 /* tpr shadow is needed by all apicv features. */
9587 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
9593 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
9594 unsigned long count_field
,
9595 unsigned long addr_field
)
9600 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
9601 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
9607 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9608 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
9609 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
9610 pr_debug_ratelimited(
9611 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9612 addr_field
, maxphyaddr
, count
, addr
);
9618 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
9619 struct vmcs12
*vmcs12
)
9621 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
9622 vmcs12
->vm_exit_msr_store_count
== 0 &&
9623 vmcs12
->vm_entry_msr_load_count
== 0)
9624 return 0; /* Fast path */
9625 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
9626 VM_EXIT_MSR_LOAD_ADDR
) ||
9627 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
9628 VM_EXIT_MSR_STORE_ADDR
) ||
9629 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
9630 VM_ENTRY_MSR_LOAD_ADDR
))
9635 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
9636 struct vmx_msr_entry
*e
)
9638 /* x2APIC MSR accesses are not allowed */
9639 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
9641 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
9642 e
->index
== MSR_IA32_UCODE_REV
)
9644 if (e
->reserved
!= 0)
9649 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
9650 struct vmx_msr_entry
*e
)
9652 if (e
->index
== MSR_FS_BASE
||
9653 e
->index
== MSR_GS_BASE
||
9654 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
9655 nested_vmx_msr_check_common(vcpu
, e
))
9660 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
9661 struct vmx_msr_entry
*e
)
9663 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
9664 nested_vmx_msr_check_common(vcpu
, e
))
9670 * Load guest's/host's msr at nested entry/exit.
9671 * return 0 for success, entry index for failure.
9673 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9676 struct vmx_msr_entry e
;
9677 struct msr_data msr
;
9679 msr
.host_initiated
= false;
9680 for (i
= 0; i
< count
; i
++) {
9681 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
9683 pr_debug_ratelimited(
9684 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9685 __func__
, i
, gpa
+ i
* sizeof(e
));
9688 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
9689 pr_debug_ratelimited(
9690 "%s check failed (%u, 0x%x, 0x%x)\n",
9691 __func__
, i
, e
.index
, e
.reserved
);
9694 msr
.index
= e
.index
;
9696 if (kvm_set_msr(vcpu
, &msr
)) {
9697 pr_debug_ratelimited(
9698 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9699 __func__
, i
, e
.index
, e
.value
);
9708 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9711 struct vmx_msr_entry e
;
9713 for (i
= 0; i
< count
; i
++) {
9714 struct msr_data msr_info
;
9715 if (kvm_vcpu_read_guest(vcpu
,
9716 gpa
+ i
* sizeof(e
),
9717 &e
, 2 * sizeof(u32
))) {
9718 pr_debug_ratelimited(
9719 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9720 __func__
, i
, gpa
+ i
* sizeof(e
));
9723 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
9724 pr_debug_ratelimited(
9725 "%s check failed (%u, 0x%x, 0x%x)\n",
9726 __func__
, i
, e
.index
, e
.reserved
);
9729 msr_info
.host_initiated
= false;
9730 msr_info
.index
= e
.index
;
9731 if (kvm_get_msr(vcpu
, &msr_info
)) {
9732 pr_debug_ratelimited(
9733 "%s cannot read MSR (%u, 0x%x)\n",
9734 __func__
, i
, e
.index
);
9737 if (kvm_vcpu_write_guest(vcpu
,
9738 gpa
+ i
* sizeof(e
) +
9739 offsetof(struct vmx_msr_entry
, value
),
9740 &msr_info
.data
, sizeof(msr_info
.data
))) {
9741 pr_debug_ratelimited(
9742 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9743 __func__
, i
, e
.index
, msr_info
.data
);
9751 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9752 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9753 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9754 * guest in a way that will both be appropriate to L1's requests, and our
9755 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9756 * function also has additional necessary side-effects, like setting various
9757 * vcpu->arch fields.
9759 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
9761 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9764 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
9765 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
9766 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
9767 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
9768 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
9769 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
9770 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
9771 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
9772 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
9773 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
9774 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
9775 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
9776 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
9777 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
9778 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
9779 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
9780 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
9781 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
9782 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
9783 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
9784 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
9785 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
9786 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
9787 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
9788 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
9789 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
9790 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
9791 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
9792 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
9793 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
9794 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
9795 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
9796 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
9797 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
9798 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
9799 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
9801 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
) {
9802 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
9803 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
9805 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
9806 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
9808 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
9809 vmcs12
->vm_entry_intr_info_field
);
9810 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
9811 vmcs12
->vm_entry_exception_error_code
);
9812 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
9813 vmcs12
->vm_entry_instruction_len
);
9814 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
9815 vmcs12
->guest_interruptibility_info
);
9816 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
9817 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
9818 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
9819 vmcs12
->guest_pending_dbg_exceptions
);
9820 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
9821 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
9823 if (nested_cpu_has_xsaves(vmcs12
))
9824 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
9825 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
9827 exec_control
= vmcs12
->pin_based_vm_exec_control
;
9829 /* Preemption timer setting is only taken from vmcs01. */
9830 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
9831 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
9832 if (vmx
->hv_deadline_tsc
== -1)
9833 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
9835 /* Posted interrupts setting is only taken from vmcs12. */
9836 if (nested_cpu_has_posted_intr(vmcs12
)) {
9838 * Note that we use L0's vector here and in
9839 * vmx_deliver_nested_posted_interrupt.
9841 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
9842 vmx
->nested
.pi_pending
= false;
9843 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
9844 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9845 page_to_phys(vmx
->nested
.pi_desc_page
) +
9846 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9849 exec_control
&= ~PIN_BASED_POSTED_INTR
;
9851 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
9853 vmx
->nested
.preemption_timer_expired
= false;
9854 if (nested_cpu_has_preemption_timer(vmcs12
))
9855 vmx_start_preemption_timer(vcpu
);
9858 * Whether page-faults are trapped is determined by a combination of
9859 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9860 * If enable_ept, L0 doesn't care about page faults and we should
9861 * set all of these to L1's desires. However, if !enable_ept, L0 does
9862 * care about (at least some) page faults, and because it is not easy
9863 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9864 * to exit on each and every L2 page fault. This is done by setting
9865 * MASK=MATCH=0 and (see below) EB.PF=1.
9866 * Note that below we don't need special code to set EB.PF beyond the
9867 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9868 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9869 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9871 * A problem with this approach (when !enable_ept) is that L1 may be
9872 * injected with more page faults than it asked for. This could have
9873 * caused problems, but in practice existing hypervisors don't care.
9874 * To fix this, we will need to emulate the PFEC checking (on the L1
9875 * page tables), using walk_addr(), when injecting PFs to L1.
9877 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
9878 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
9879 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
9880 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
9882 if (cpu_has_secondary_exec_ctrls()) {
9883 exec_control
= vmx_secondary_exec_control(vmx
);
9885 /* Take the following fields only from vmcs12 */
9886 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
9887 SECONDARY_EXEC_RDTSCP
|
9888 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
9889 SECONDARY_EXEC_APIC_REGISTER_VIRT
);
9890 if (nested_cpu_has(vmcs12
,
9891 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
9892 exec_control
|= vmcs12
->secondary_vm_exec_control
;
9894 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
9896 * If translation failed, no matter: This feature asks
9897 * to exit when accessing the given address, and if it
9898 * can never be accessed, this feature won't do
9901 if (!vmx
->nested
.apic_access_page
)
9903 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9905 vmcs_write64(APIC_ACCESS_ADDR
,
9906 page_to_phys(vmx
->nested
.apic_access_page
));
9907 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9908 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9910 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9911 kvm_vcpu_reload_apic_access_page(vcpu
);
9914 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
9915 vmcs_write64(EOI_EXIT_BITMAP0
,
9916 vmcs12
->eoi_exit_bitmap0
);
9917 vmcs_write64(EOI_EXIT_BITMAP1
,
9918 vmcs12
->eoi_exit_bitmap1
);
9919 vmcs_write64(EOI_EXIT_BITMAP2
,
9920 vmcs12
->eoi_exit_bitmap2
);
9921 vmcs_write64(EOI_EXIT_BITMAP3
,
9922 vmcs12
->eoi_exit_bitmap3
);
9923 vmcs_write16(GUEST_INTR_STATUS
,
9924 vmcs12
->guest_intr_status
);
9927 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
9932 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9933 * Some constant fields are set here by vmx_set_constant_host_state().
9934 * Other fields are different per CPU, and will be set later when
9935 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9937 vmx_set_constant_host_state(vmx
);
9940 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9941 * entry, but only if the current (host) sp changed from the value
9942 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9943 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9944 * here we just force the write to happen on entry.
9948 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
9949 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
9950 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
9951 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
9952 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
9954 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
9955 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
9956 page_to_phys(vmx
->nested
.virtual_apic_page
));
9957 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
9960 if (cpu_has_vmx_msr_bitmap() &&
9961 exec_control
& CPU_BASED_USE_MSR_BITMAPS
&&
9962 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
))
9963 ; /* MSR_BITMAP will be set by following vmx_set_efer. */
9965 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
9968 * Merging of IO bitmap not currently supported.
9969 * Rather, exit every time.
9971 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
9972 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
9974 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
9976 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9977 * bitwise-or of what L1 wants to trap for L2, and what we want to
9978 * trap. Note that CR0.TS also needs updating - we do this later.
9980 update_exception_bitmap(vcpu
);
9981 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
9982 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
9984 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9985 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9986 * bits are further modified by vmx_set_efer() below.
9988 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
9990 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9991 * emulated by vmx_set_efer(), below.
9993 vm_entry_controls_init(vmx
,
9994 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
9995 ~VM_ENTRY_IA32E_MODE
) |
9996 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
9998 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
) {
9999 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
10000 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
10001 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
10002 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
10005 set_cr4_guest_host_mask(vmx
);
10007 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
10008 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
10010 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
10011 vmcs_write64(TSC_OFFSET
,
10012 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
10014 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
10015 if (kvm_has_tsc_control
)
10016 decache_tsc_multiplier(vmx
);
10020 * There is no direct mapping between vpid02 and vpid12, the
10021 * vpid02 is per-vCPU for L0 and reused while the value of
10022 * vpid12 is changed w/ one invvpid during nested vmentry.
10023 * The vpid12 is allocated by L1 for L2, so it will not
10024 * influence global bitmap(for vpid01 and vpid02 allocation)
10025 * even if spawn a lot of nested vCPUs.
10027 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
10028 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
10029 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
10030 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
10031 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
10034 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
10035 vmx_flush_tlb(vcpu
);
10040 if (nested_cpu_has_ept(vmcs12
)) {
10041 kvm_mmu_unload(vcpu
);
10042 nested_ept_init_mmu_context(vcpu
);
10045 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
10046 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
10047 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
10048 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10050 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10051 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10052 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10055 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
10056 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
10057 * The CR0_READ_SHADOW is what L2 should have expected to read given
10058 * the specifications by L1; It's not enough to take
10059 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10060 * have more bits than L1 expected.
10062 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
10063 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
10065 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
10066 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
10068 /* shadow page tables on either EPT or shadow page tables */
10069 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
10070 kvm_mmu_reset_context(vcpu
);
10073 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
10076 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10079 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
10080 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
10081 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
10082 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
10085 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
10086 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
10090 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10091 * for running an L2 nested guest.
10093 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
10095 struct vmcs12
*vmcs12
;
10096 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10098 struct loaded_vmcs
*vmcs02
;
10102 if (!nested_vmx_check_permission(vcpu
) ||
10103 !nested_vmx_check_vmcs12(vcpu
))
10106 skip_emulated_instruction(vcpu
);
10107 vmcs12
= get_vmcs12(vcpu
);
10109 if (enable_shadow_vmcs
)
10110 copy_shadow_to_vmcs12(vmx
);
10113 * The nested entry process starts with enforcing various prerequisites
10114 * on vmcs12 as required by the Intel SDM, and act appropriately when
10115 * they fail: As the SDM explains, some conditions should cause the
10116 * instruction to fail, while others will cause the instruction to seem
10117 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10118 * To speed up the normal (success) code path, we should avoid checking
10119 * for misconfigurations which will anyway be caught by the processor
10120 * when using the merged vmcs02.
10122 if (vmcs12
->launch_state
== launch
) {
10123 nested_vmx_failValid(vcpu
,
10124 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10125 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
10129 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
10130 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
) {
10131 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
10135 if (!nested_get_vmcs12_pages(vcpu
, vmcs12
)) {
10136 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
10140 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
)) {
10141 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
10145 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
)) {
10146 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
10150 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
)) {
10151 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
10155 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
10156 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
10157 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
10158 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
10159 vmx
->nested
.nested_vmx_secondary_ctls_low
,
10160 vmx
->nested
.nested_vmx_secondary_ctls_high
) ||
10161 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
10162 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
10163 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
10164 !vmx_control_verify(vmcs12
->vm_exit_controls
,
10165 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
10166 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
10167 !vmx_control_verify(vmcs12
->vm_entry_controls
,
10168 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
10169 vmx
->nested
.nested_vmx_entry_ctls_high
))
10171 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
10175 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
10176 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
10177 nested_vmx_failValid(vcpu
,
10178 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
10182 if (!nested_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
10183 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
10184 nested_vmx_entry_failure(vcpu
, vmcs12
,
10185 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
10188 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
10189 nested_vmx_entry_failure(vcpu
, vmcs12
,
10190 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
10195 * If the load IA32_EFER VM-entry control is 1, the following checks
10196 * are performed on the field for the IA32_EFER MSR:
10197 * - Bits reserved in the IA32_EFER MSR must be 0.
10198 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10199 * the IA-32e mode guest VM-exit control. It must also be identical
10200 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10203 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
) {
10204 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
10205 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
10206 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
10207 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
10208 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
))) {
10209 nested_vmx_entry_failure(vcpu
, vmcs12
,
10210 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
10216 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10217 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10218 * the values of the LMA and LME bits in the field must each be that of
10219 * the host address-space size VM-exit control.
10221 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
10222 ia32e
= (vmcs12
->vm_exit_controls
&
10223 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
10224 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
10225 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
10226 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
)) {
10227 nested_vmx_entry_failure(vcpu
, vmcs12
,
10228 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
10234 * We're finally done with prerequisite checking, and can start with
10235 * the nested entry.
10238 vmcs02
= nested_get_current_vmcs02(vmx
);
10242 enter_guest_mode(vcpu
);
10244 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
10246 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
10247 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10250 vmx
->loaded_vmcs
= vmcs02
;
10251 vmx_vcpu_put(vcpu
);
10252 vmx_vcpu_load(vcpu
, cpu
);
10256 vmx_segment_cache_clear(vmx
);
10258 prepare_vmcs02(vcpu
, vmcs12
);
10260 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
10261 vmcs12
->vm_entry_msr_load_addr
,
10262 vmcs12
->vm_entry_msr_load_count
);
10263 if (msr_entry_idx
) {
10264 leave_guest_mode(vcpu
);
10265 vmx_load_vmcs01(vcpu
);
10266 nested_vmx_entry_failure(vcpu
, vmcs12
,
10267 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
10271 vmcs12
->launch_state
= 1;
10273 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
10274 return kvm_vcpu_halt(vcpu
);
10276 vmx
->nested
.nested_run_pending
= 1;
10279 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10280 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10281 * returned as far as L1 is concerned. It will only return (and set
10282 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10288 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10289 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10290 * This function returns the new value we should put in vmcs12.guest_cr0.
10291 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10292 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10293 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10294 * didn't trap the bit, because if L1 did, so would L0).
10295 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10296 * been modified by L2, and L1 knows it. So just leave the old value of
10297 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10298 * isn't relevant, because if L0 traps this bit it can set it to anything.
10299 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10300 * changed these bits, and therefore they need to be updated, but L0
10301 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10302 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10304 static inline unsigned long
10305 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10308 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
10309 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
10310 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
10311 vcpu
->arch
.cr0_guest_owned_bits
));
10314 static inline unsigned long
10315 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10318 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
10319 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
10320 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
10321 vcpu
->arch
.cr4_guest_owned_bits
));
10324 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
10325 struct vmcs12
*vmcs12
)
10330 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
10331 nr
= vcpu
->arch
.exception
.nr
;
10332 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10334 if (kvm_exception_is_soft(nr
)) {
10335 vmcs12
->vm_exit_instruction_len
=
10336 vcpu
->arch
.event_exit_inst_len
;
10337 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
10339 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
10341 if (vcpu
->arch
.exception
.has_error_code
) {
10342 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
10343 vmcs12
->idt_vectoring_error_code
=
10344 vcpu
->arch
.exception
.error_code
;
10347 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10348 } else if (vcpu
->arch
.nmi_injected
) {
10349 vmcs12
->idt_vectoring_info_field
=
10350 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
10351 } else if (vcpu
->arch
.interrupt
.pending
) {
10352 nr
= vcpu
->arch
.interrupt
.nr
;
10353 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10355 if (vcpu
->arch
.interrupt
.soft
) {
10356 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
10357 vmcs12
->vm_entry_instruction_len
=
10358 vcpu
->arch
.event_exit_inst_len
;
10360 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
10362 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10366 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
10368 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10370 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
10371 vmx
->nested
.preemption_timer_expired
) {
10372 if (vmx
->nested
.nested_run_pending
)
10374 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
10378 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
10379 if (vmx
->nested
.nested_run_pending
||
10380 vcpu
->arch
.interrupt
.pending
)
10382 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
10383 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
10384 INTR_INFO_VALID_MASK
, 0);
10386 * The NMI-triggered VM exit counts as injection:
10387 * clear this one and block further NMIs.
10389 vcpu
->arch
.nmi_pending
= 0;
10390 vmx_set_nmi_mask(vcpu
, true);
10394 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
10395 nested_exit_on_intr(vcpu
)) {
10396 if (vmx
->nested
.nested_run_pending
)
10398 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
10402 return vmx_complete_nested_posted_interrupt(vcpu
);
10405 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
10407 ktime_t remaining
=
10408 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
10411 if (ktime_to_ns(remaining
) <= 0)
10414 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
10415 do_div(value
, 1000000);
10416 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
10420 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10421 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10422 * and this function updates it to reflect the changes to the guest state while
10423 * L2 was running (and perhaps made some exits which were handled directly by L0
10424 * without going back to L1), and to reflect the exit reason.
10425 * Note that we do not have to copy here all VMCS fields, just those that
10426 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10427 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10428 * which already writes to vmcs12 directly.
10430 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10431 u32 exit_reason
, u32 exit_intr_info
,
10432 unsigned long exit_qualification
)
10434 /* update guest state fields: */
10435 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
10436 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
10438 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
10439 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
10440 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
10442 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
10443 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
10444 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
10445 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
10446 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
10447 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
10448 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
10449 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
10450 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
10451 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
10452 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
10453 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
10454 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
10455 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
10456 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
10457 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
10458 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
10459 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
10460 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
10461 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
10462 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
10463 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
10464 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
10465 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
10466 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
10467 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
10468 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
10469 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
10470 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
10471 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
10472 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
10473 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
10474 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
10475 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
10476 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
10477 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
10479 vmcs12
->guest_interruptibility_info
=
10480 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
10481 vmcs12
->guest_pending_dbg_exceptions
=
10482 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
10483 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
10484 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
10486 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
10488 if (nested_cpu_has_preemption_timer(vmcs12
)) {
10489 if (vmcs12
->vm_exit_controls
&
10490 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
10491 vmcs12
->vmx_preemption_timer_value
=
10492 vmx_get_preemption_timer_value(vcpu
);
10493 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
10497 * In some cases (usually, nested EPT), L2 is allowed to change its
10498 * own CR3 without exiting. If it has changed it, we must keep it.
10499 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10500 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10502 * Additionally, restore L2's PDPTR to vmcs12.
10505 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
10506 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
10507 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
10508 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
10509 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
10512 if (nested_cpu_has_ept(vmcs12
))
10513 vmcs12
->guest_linear_address
= vmcs_readl(GUEST_LINEAR_ADDRESS
);
10515 if (nested_cpu_has_vid(vmcs12
))
10516 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
10518 vmcs12
->vm_entry_controls
=
10519 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
10520 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
10522 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
10523 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
10524 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10527 /* TODO: These cannot have changed unless we have MSR bitmaps and
10528 * the relevant bit asks not to trap the change */
10529 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
10530 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
10531 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
10532 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
10533 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
10534 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
10535 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
10536 if (kvm_mpx_supported())
10537 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
10538 if (nested_cpu_has_xsaves(vmcs12
))
10539 vmcs12
->xss_exit_bitmap
= vmcs_read64(XSS_EXIT_BITMAP
);
10541 /* update exit information fields: */
10543 vmcs12
->vm_exit_reason
= exit_reason
;
10544 vmcs12
->exit_qualification
= exit_qualification
;
10546 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
10547 if ((vmcs12
->vm_exit_intr_info
&
10548 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
10549 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
10550 vmcs12
->vm_exit_intr_error_code
=
10551 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
10552 vmcs12
->idt_vectoring_info_field
= 0;
10553 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
10554 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
10556 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
10557 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10558 * instead of reading the real value. */
10559 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
10562 * Transfer the event that L0 or L1 may wanted to inject into
10563 * L2 to IDT_VECTORING_INFO_FIELD.
10565 vmcs12_save_pending_event(vcpu
, vmcs12
);
10569 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10570 * preserved above and would only end up incorrectly in L1.
10572 vcpu
->arch
.nmi_injected
= false;
10573 kvm_clear_exception_queue(vcpu
);
10574 kvm_clear_interrupt_queue(vcpu
);
10578 * A part of what we need to when the nested L2 guest exits and we want to
10579 * run its L1 parent, is to reset L1's guest state to the host state specified
10581 * This function is to be called not only on normal nested exit, but also on
10582 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10583 * Failures During or After Loading Guest State").
10584 * This function should be called when the active VMCS is L1's (vmcs01).
10586 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
10587 struct vmcs12
*vmcs12
)
10589 struct kvm_segment seg
;
10591 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
10592 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
10593 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10594 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10596 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10597 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10599 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
10600 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
10601 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
10603 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10604 * actually changed, because it depends on the current state of
10605 * fpu_active (which may have changed).
10606 * Note that vmx_set_cr0 refers to efer set above.
10608 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
10610 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10611 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10612 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10614 update_exception_bitmap(vcpu
);
10615 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
10616 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10619 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10620 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10622 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
10623 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
10625 nested_ept_uninit_mmu_context(vcpu
);
10627 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
10628 kvm_mmu_reset_context(vcpu
);
10631 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
10635 * Trivially support vpid by letting L2s share their parent
10636 * L1's vpid. TODO: move to a more elaborate solution, giving
10637 * each L2 its own vpid and exposing the vpid feature to L1.
10639 vmx_flush_tlb(vcpu
);
10643 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
10644 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
10645 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
10646 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
10647 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
10649 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10650 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
10651 vmcs_write64(GUEST_BNDCFGS
, 0);
10653 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
10654 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
10655 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
10657 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
10658 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
10659 vmcs12
->host_ia32_perf_global_ctrl
);
10661 /* Set L1 segment info according to Intel SDM
10662 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10663 seg
= (struct kvm_segment
) {
10665 .limit
= 0xFFFFFFFF,
10666 .selector
= vmcs12
->host_cs_selector
,
10672 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10676 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
10677 seg
= (struct kvm_segment
) {
10679 .limit
= 0xFFFFFFFF,
10686 seg
.selector
= vmcs12
->host_ds_selector
;
10687 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
10688 seg
.selector
= vmcs12
->host_es_selector
;
10689 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
10690 seg
.selector
= vmcs12
->host_ss_selector
;
10691 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
10692 seg
.selector
= vmcs12
->host_fs_selector
;
10693 seg
.base
= vmcs12
->host_fs_base
;
10694 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
10695 seg
.selector
= vmcs12
->host_gs_selector
;
10696 seg
.base
= vmcs12
->host_gs_base
;
10697 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
10698 seg
= (struct kvm_segment
) {
10699 .base
= vmcs12
->host_tr_base
,
10701 .selector
= vmcs12
->host_tr_selector
,
10705 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
10707 kvm_set_dr(vcpu
, 7, 0x400);
10708 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
10710 if (cpu_has_vmx_msr_bitmap())
10711 vmx_set_msr_bitmap(vcpu
);
10713 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
10714 vmcs12
->vm_exit_msr_load_count
))
10715 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
10719 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10720 * and modify vmcs12 to make it see what it would expect to see there if
10721 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10723 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
10724 u32 exit_intr_info
,
10725 unsigned long exit_qualification
)
10727 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10728 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10730 /* trying to cancel vmlaunch/vmresume is a bug */
10731 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
10733 leave_guest_mode(vcpu
);
10734 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
10735 exit_qualification
);
10737 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
10738 vmcs12
->vm_exit_msr_store_count
))
10739 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
10741 vmx_load_vmcs01(vcpu
);
10743 if ((exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
)
10744 && nested_exit_intr_ack_set(vcpu
)) {
10745 int irq
= kvm_cpu_get_interrupt(vcpu
);
10747 vmcs12
->vm_exit_intr_info
= irq
|
10748 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
10751 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
10752 vmcs12
->exit_qualification
,
10753 vmcs12
->idt_vectoring_info_field
,
10754 vmcs12
->vm_exit_intr_info
,
10755 vmcs12
->vm_exit_intr_error_code
,
10758 vm_entry_controls_reset_shadow(vmx
);
10759 vm_exit_controls_reset_shadow(vmx
);
10760 vmx_segment_cache_clear(vmx
);
10762 /* if no vmcs02 cache requested, remove the one we used */
10763 if (VMCS02_POOL_SIZE
== 0)
10764 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
10766 load_vmcs12_host_state(vcpu
, vmcs12
);
10768 /* Update any VMCS fields that might have changed while L2 ran */
10769 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
10770 if (vmx
->hv_deadline_tsc
== -1)
10771 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
10772 PIN_BASED_VMX_PREEMPTION_TIMER
);
10774 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
10775 PIN_BASED_VMX_PREEMPTION_TIMER
);
10776 if (kvm_has_tsc_control
)
10777 decache_tsc_multiplier(vmx
);
10779 if (vmx
->nested
.change_vmcs01_virtual_x2apic_mode
) {
10780 vmx
->nested
.change_vmcs01_virtual_x2apic_mode
= false;
10781 vmx_set_virtual_x2apic_mode(vcpu
,
10782 vcpu
->arch
.apic_base
& X2APIC_ENABLE
);
10785 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10788 /* Unpin physical memory we referred to in vmcs02 */
10789 if (vmx
->nested
.apic_access_page
) {
10790 nested_release_page(vmx
->nested
.apic_access_page
);
10791 vmx
->nested
.apic_access_page
= NULL
;
10793 if (vmx
->nested
.virtual_apic_page
) {
10794 nested_release_page(vmx
->nested
.virtual_apic_page
);
10795 vmx
->nested
.virtual_apic_page
= NULL
;
10797 if (vmx
->nested
.pi_desc_page
) {
10798 kunmap(vmx
->nested
.pi_desc_page
);
10799 nested_release_page(vmx
->nested
.pi_desc_page
);
10800 vmx
->nested
.pi_desc_page
= NULL
;
10801 vmx
->nested
.pi_desc
= NULL
;
10805 * We are now running in L2, mmu_notifier will force to reload the
10806 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10808 kvm_vcpu_reload_apic_access_page(vcpu
);
10811 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10812 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10813 * success or failure flag accordingly.
10815 if (unlikely(vmx
->fail
)) {
10817 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
10819 nested_vmx_succeed(vcpu
);
10820 if (enable_shadow_vmcs
)
10821 vmx
->nested
.sync_shadow_vmcs
= true;
10823 /* in case we halted in L2 */
10824 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
10828 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10830 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
10832 if (is_guest_mode(vcpu
))
10833 nested_vmx_vmexit(vcpu
, -1, 0, 0);
10834 free_nested(to_vmx(vcpu
));
10838 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10839 * 23.7 "VM-entry failures during or after loading guest state" (this also
10840 * lists the acceptable exit-reason and exit-qualification parameters).
10841 * It should only be called before L2 actually succeeded to run, and when
10842 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10844 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
10845 struct vmcs12
*vmcs12
,
10846 u32 reason
, unsigned long qualification
)
10848 load_vmcs12_host_state(vcpu
, vmcs12
);
10849 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
10850 vmcs12
->exit_qualification
= qualification
;
10851 nested_vmx_succeed(vcpu
);
10852 if (enable_shadow_vmcs
)
10853 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
10856 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
10857 struct x86_instruction_info
*info
,
10858 enum x86_intercept_stage stage
)
10860 return X86EMUL_CONTINUE
;
10863 #ifdef CONFIG_X86_64
10864 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
10865 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
10866 u64 divisor
, u64
*result
)
10868 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
10870 /* To avoid the overflow on divq */
10871 if (high
>= divisor
)
10874 /* Low hold the result, high hold rem which is discarded */
10875 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
10876 "rm" (divisor
), "0" (low
), "1" (high
));
10882 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
)
10884 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10885 u64 tscl
= rdtsc();
10886 u64 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
10887 u64 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
10889 /* Convert to host delta tsc if tsc scaling is enabled */
10890 if (vcpu
->arch
.tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
10891 u64_shl_div_u64(delta_tsc
,
10892 kvm_tsc_scaling_ratio_frac_bits
,
10893 vcpu
->arch
.tsc_scaling_ratio
,
10898 * If the delta tsc can't fit in the 32 bit after the multi shift,
10899 * we can't use the preemption timer.
10900 * It's possible that it fits on later vmentries, but checking
10901 * on every vmentry is costly so we just use an hrtimer.
10903 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
10906 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
10907 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
10908 PIN_BASED_VMX_PREEMPTION_TIMER
);
10912 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
10914 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10915 vmx
->hv_deadline_tsc
= -1;
10916 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
10917 PIN_BASED_VMX_PREEMPTION_TIMER
);
10921 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
10924 shrink_ple_window(vcpu
);
10927 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
10928 struct kvm_memory_slot
*slot
)
10930 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
10931 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
10934 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
10935 struct kvm_memory_slot
*slot
)
10937 kvm_mmu_slot_set_dirty(kvm
, slot
);
10940 static void vmx_flush_log_dirty(struct kvm
*kvm
)
10942 kvm_flush_pml_buffers(kvm
);
10945 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
10946 struct kvm_memory_slot
*memslot
,
10947 gfn_t offset
, unsigned long mask
)
10949 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
10953 * This routine does the following things for vCPU which is going
10954 * to be blocked if VT-d PI is enabled.
10955 * - Store the vCPU to the wakeup list, so when interrupts happen
10956 * we can find the right vCPU to wake up.
10957 * - Change the Posted-interrupt descriptor as below:
10958 * 'NDST' <-- vcpu->pre_pcpu
10959 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10960 * - If 'ON' is set during this process, which means at least one
10961 * interrupt is posted for this vCPU, we cannot block it, in
10962 * this case, return 1, otherwise, return 0.
10965 static int pi_pre_block(struct kvm_vcpu
*vcpu
)
10967 unsigned long flags
;
10969 struct pi_desc old
, new;
10970 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
10972 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
10973 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
10974 !kvm_vcpu_apicv_active(vcpu
))
10977 vcpu
->pre_pcpu
= vcpu
->cpu
;
10978 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
10979 vcpu
->pre_pcpu
), flags
);
10980 list_add_tail(&vcpu
->blocked_vcpu_list
,
10981 &per_cpu(blocked_vcpu_on_cpu
,
10983 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock
,
10984 vcpu
->pre_pcpu
), flags
);
10987 old
.control
= new.control
= pi_desc
->control
;
10990 * We should not block the vCPU if
10991 * an interrupt is posted for it.
10993 if (pi_test_on(pi_desc
) == 1) {
10994 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
10995 vcpu
->pre_pcpu
), flags
);
10996 list_del(&vcpu
->blocked_vcpu_list
);
10997 spin_unlock_irqrestore(
10998 &per_cpu(blocked_vcpu_on_cpu_lock
,
10999 vcpu
->pre_pcpu
), flags
);
11000 vcpu
->pre_pcpu
= -1;
11005 WARN((pi_desc
->sn
== 1),
11006 "Warning: SN field of posted-interrupts "
11007 "is set before blocking\n");
11010 * Since vCPU can be preempted during this process,
11011 * vcpu->cpu could be different with pre_pcpu, we
11012 * need to set pre_pcpu as the destination of wakeup
11013 * notification event, then we can find the right vCPU
11014 * to wakeup in wakeup handler if interrupts happen
11015 * when the vCPU is in blocked state.
11017 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
11019 if (x2apic_enabled())
11022 new.ndst
= (dest
<< 8) & 0xFF00;
11024 /* set 'NV' to 'wakeup vector' */
11025 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
11026 } while (cmpxchg(&pi_desc
->control
, old
.control
,
11027 new.control
) != old
.control
);
11032 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
11034 if (pi_pre_block(vcpu
))
11037 if (kvm_lapic_hv_timer_in_use(vcpu
))
11038 kvm_lapic_switch_to_sw_timer(vcpu
);
11043 static void pi_post_block(struct kvm_vcpu
*vcpu
)
11045 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11046 struct pi_desc old
, new;
11048 unsigned long flags
;
11050 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11051 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11052 !kvm_vcpu_apicv_active(vcpu
))
11056 old
.control
= new.control
= pi_desc
->control
;
11058 dest
= cpu_physical_id(vcpu
->cpu
);
11060 if (x2apic_enabled())
11063 new.ndst
= (dest
<< 8) & 0xFF00;
11065 /* Allow posting non-urgent interrupts */
11068 /* set 'NV' to 'notification vector' */
11069 new.nv
= POSTED_INTR_VECTOR
;
11070 } while (cmpxchg(&pi_desc
->control
, old
.control
,
11071 new.control
) != old
.control
);
11073 if(vcpu
->pre_pcpu
!= -1) {
11075 &per_cpu(blocked_vcpu_on_cpu_lock
,
11076 vcpu
->pre_pcpu
), flags
);
11077 list_del(&vcpu
->blocked_vcpu_list
);
11078 spin_unlock_irqrestore(
11079 &per_cpu(blocked_vcpu_on_cpu_lock
,
11080 vcpu
->pre_pcpu
), flags
);
11081 vcpu
->pre_pcpu
= -1;
11085 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
11087 if (kvm_x86_ops
->set_hv_timer
)
11088 kvm_lapic_switch_to_hv_timer(vcpu
);
11090 pi_post_block(vcpu
);
11094 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11097 * @host_irq: host irq of the interrupt
11098 * @guest_irq: gsi of the interrupt
11099 * @set: set or unset PI
11100 * returns 0 on success, < 0 on failure
11102 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
11103 uint32_t guest_irq
, bool set
)
11105 struct kvm_kernel_irq_routing_entry
*e
;
11106 struct kvm_irq_routing_table
*irq_rt
;
11107 struct kvm_lapic_irq irq
;
11108 struct kvm_vcpu
*vcpu
;
11109 struct vcpu_data vcpu_info
;
11110 int idx
, ret
= -EINVAL
;
11112 if (!kvm_arch_has_assigned_device(kvm
) ||
11113 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11114 !kvm_vcpu_apicv_active(kvm
->vcpus
[0]))
11117 idx
= srcu_read_lock(&kvm
->irq_srcu
);
11118 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
11119 BUG_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
11121 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
11122 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
11125 * VT-d PI cannot support posting multicast/broadcast
11126 * interrupts to a vCPU, we still use interrupt remapping
11127 * for these kind of interrupts.
11129 * For lowest-priority interrupts, we only support
11130 * those with single CPU as the destination, e.g. user
11131 * configures the interrupts via /proc/irq or uses
11132 * irqbalance to make the interrupts single-CPU.
11134 * We will support full lowest-priority interrupt later.
11137 kvm_set_msi_irq(kvm
, e
, &irq
);
11138 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
11140 * Make sure the IRTE is in remapped mode if
11141 * we don't handle it in posted mode.
11143 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11146 "failed to back to remapped mode, irq: %u\n",
11154 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
11155 vcpu_info
.vector
= irq
.vector
;
11157 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
11158 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
11161 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
11163 /* suppress notification event before unposting */
11164 pi_set_sn(vcpu_to_pi_desc(vcpu
));
11165 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11166 pi_clear_sn(vcpu_to_pi_desc(vcpu
));
11170 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
11178 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
11182 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
11184 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
11185 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
11186 FEATURE_CONTROL_LMCE
;
11188 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
11189 ~FEATURE_CONTROL_LMCE
;
11192 static struct kvm_x86_ops vmx_x86_ops __ro_after_init
= {
11193 .cpu_has_kvm_support
= cpu_has_kvm_support
,
11194 .disabled_by_bios
= vmx_disabled_by_bios
,
11195 .hardware_setup
= hardware_setup
,
11196 .hardware_unsetup
= hardware_unsetup
,
11197 .check_processor_compatibility
= vmx_check_processor_compat
,
11198 .hardware_enable
= hardware_enable
,
11199 .hardware_disable
= hardware_disable
,
11200 .cpu_has_accelerated_tpr
= report_flexpriority
,
11201 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
11203 .vcpu_create
= vmx_create_vcpu
,
11204 .vcpu_free
= vmx_free_vcpu
,
11205 .vcpu_reset
= vmx_vcpu_reset
,
11207 .prepare_guest_switch
= vmx_save_host_state
,
11208 .vcpu_load
= vmx_vcpu_load
,
11209 .vcpu_put
= vmx_vcpu_put
,
11211 .update_bp_intercept
= update_exception_bitmap
,
11212 .get_msr
= vmx_get_msr
,
11213 .set_msr
= vmx_set_msr
,
11214 .get_segment_base
= vmx_get_segment_base
,
11215 .get_segment
= vmx_get_segment
,
11216 .set_segment
= vmx_set_segment
,
11217 .get_cpl
= vmx_get_cpl
,
11218 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
11219 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
11220 .decache_cr3
= vmx_decache_cr3
,
11221 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
11222 .set_cr0
= vmx_set_cr0
,
11223 .set_cr3
= vmx_set_cr3
,
11224 .set_cr4
= vmx_set_cr4
,
11225 .set_efer
= vmx_set_efer
,
11226 .get_idt
= vmx_get_idt
,
11227 .set_idt
= vmx_set_idt
,
11228 .get_gdt
= vmx_get_gdt
,
11229 .set_gdt
= vmx_set_gdt
,
11230 .get_dr6
= vmx_get_dr6
,
11231 .set_dr6
= vmx_set_dr6
,
11232 .set_dr7
= vmx_set_dr7
,
11233 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
11234 .cache_reg
= vmx_cache_reg
,
11235 .get_rflags
= vmx_get_rflags
,
11236 .set_rflags
= vmx_set_rflags
,
11238 .get_pkru
= vmx_get_pkru
,
11240 .fpu_activate
= vmx_fpu_activate
,
11241 .fpu_deactivate
= vmx_fpu_deactivate
,
11243 .tlb_flush
= vmx_flush_tlb
,
11245 .run
= vmx_vcpu_run
,
11246 .handle_exit
= vmx_handle_exit
,
11247 .skip_emulated_instruction
= skip_emulated_instruction
,
11248 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
11249 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
11250 .patch_hypercall
= vmx_patch_hypercall
,
11251 .set_irq
= vmx_inject_irq
,
11252 .set_nmi
= vmx_inject_nmi
,
11253 .queue_exception
= vmx_queue_exception
,
11254 .cancel_injection
= vmx_cancel_injection
,
11255 .interrupt_allowed
= vmx_interrupt_allowed
,
11256 .nmi_allowed
= vmx_nmi_allowed
,
11257 .get_nmi_mask
= vmx_get_nmi_mask
,
11258 .set_nmi_mask
= vmx_set_nmi_mask
,
11259 .enable_nmi_window
= enable_nmi_window
,
11260 .enable_irq_window
= enable_irq_window
,
11261 .update_cr8_intercept
= update_cr8_intercept
,
11262 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
11263 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
11264 .get_enable_apicv
= vmx_get_enable_apicv
,
11265 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
11266 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
11267 .hwapic_irr_update
= vmx_hwapic_irr_update
,
11268 .hwapic_isr_update
= vmx_hwapic_isr_update
,
11269 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
11270 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
11272 .set_tss_addr
= vmx_set_tss_addr
,
11273 .get_tdp_level
= get_ept_level
,
11274 .get_mt_mask
= vmx_get_mt_mask
,
11276 .get_exit_info
= vmx_get_exit_info
,
11278 .get_lpage_level
= vmx_get_lpage_level
,
11280 .cpuid_update
= vmx_cpuid_update
,
11282 .rdtscp_supported
= vmx_rdtscp_supported
,
11283 .invpcid_supported
= vmx_invpcid_supported
,
11285 .set_supported_cpuid
= vmx_set_supported_cpuid
,
11287 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
11289 .read_tsc_offset
= vmx_read_tsc_offset
,
11290 .write_tsc_offset
= vmx_write_tsc_offset
,
11291 .adjust_tsc_offset_guest
= vmx_adjust_tsc_offset_guest
,
11292 .read_l1_tsc
= vmx_read_l1_tsc
,
11294 .set_tdp_cr3
= vmx_set_cr3
,
11296 .check_intercept
= vmx_check_intercept
,
11297 .handle_external_intr
= vmx_handle_external_intr
,
11298 .mpx_supported
= vmx_mpx_supported
,
11299 .xsaves_supported
= vmx_xsaves_supported
,
11301 .check_nested_events
= vmx_check_nested_events
,
11303 .sched_in
= vmx_sched_in
,
11305 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
11306 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
11307 .flush_log_dirty
= vmx_flush_log_dirty
,
11308 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
11310 .pre_block
= vmx_pre_block
,
11311 .post_block
= vmx_post_block
,
11313 .pmu_ops
= &intel_pmu_ops
,
11315 .update_pi_irte
= vmx_update_pi_irte
,
11317 #ifdef CONFIG_X86_64
11318 .set_hv_timer
= vmx_set_hv_timer
,
11319 .cancel_hv_timer
= vmx_cancel_hv_timer
,
11322 .setup_mce
= vmx_setup_mce
,
11325 static int __init
vmx_init(void)
11327 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
11328 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
11332 #ifdef CONFIG_KEXEC_CORE
11333 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
11334 crash_vmclear_local_loaded_vmcss
);
11340 static void __exit
vmx_exit(void)
11342 #ifdef CONFIG_KEXEC_CORE
11343 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
11350 module_init(vmx_init
)
11351 module_exit(vmx_exit
)