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Merge 4.8-rc5 into tty-next
[deliverable/linux.git] / drivers / dma / imx-sdma.c
1 /*
2 * drivers/dma/imx-sdma.c
3 *
4 * This file contains a driver for the Freescale Smart DMA engine
5 *
6 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
7 *
8 * Based on code from Freescale:
9 *
10 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
11 *
12 * The code contained herein is licensed under the GNU General Public
13 * License. You may obtain a copy of the GNU General Public License
14 * Version 2 or later at the following locations:
15 *
16 * http://www.opensource.org/licenses/gpl-license.html
17 * http://www.gnu.org/copyleft/gpl.html
18 */
19
20 #include <linux/init.h>
21 #include <linux/iopoll.h>
22 #include <linux/module.h>
23 #include <linux/types.h>
24 #include <linux/bitops.h>
25 #include <linux/mm.h>
26 #include <linux/interrupt.h>
27 #include <linux/clk.h>
28 #include <linux/delay.h>
29 #include <linux/sched.h>
30 #include <linux/semaphore.h>
31 #include <linux/spinlock.h>
32 #include <linux/device.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/firmware.h>
35 #include <linux/slab.h>
36 #include <linux/platform_device.h>
37 #include <linux/dmaengine.h>
38 #include <linux/of.h>
39 #include <linux/of_address.h>
40 #include <linux/of_device.h>
41 #include <linux/of_dma.h>
42
43 #include <asm/irq.h>
44 #include <linux/platform_data/dma-imx-sdma.h>
45 #include <linux/platform_data/dma-imx.h>
46 #include <linux/regmap.h>
47 #include <linux/mfd/syscon.h>
48 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
49
50 #include "dmaengine.h"
51
52 /* SDMA registers */
53 #define SDMA_H_C0PTR 0x000
54 #define SDMA_H_INTR 0x004
55 #define SDMA_H_STATSTOP 0x008
56 #define SDMA_H_START 0x00c
57 #define SDMA_H_EVTOVR 0x010
58 #define SDMA_H_DSPOVR 0x014
59 #define SDMA_H_HOSTOVR 0x018
60 #define SDMA_H_EVTPEND 0x01c
61 #define SDMA_H_DSPENBL 0x020
62 #define SDMA_H_RESET 0x024
63 #define SDMA_H_EVTERR 0x028
64 #define SDMA_H_INTRMSK 0x02c
65 #define SDMA_H_PSW 0x030
66 #define SDMA_H_EVTERRDBG 0x034
67 #define SDMA_H_CONFIG 0x038
68 #define SDMA_ONCE_ENB 0x040
69 #define SDMA_ONCE_DATA 0x044
70 #define SDMA_ONCE_INSTR 0x048
71 #define SDMA_ONCE_STAT 0x04c
72 #define SDMA_ONCE_CMD 0x050
73 #define SDMA_EVT_MIRROR 0x054
74 #define SDMA_ILLINSTADDR 0x058
75 #define SDMA_CHN0ADDR 0x05c
76 #define SDMA_ONCE_RTB 0x060
77 #define SDMA_XTRIG_CONF1 0x070
78 #define SDMA_XTRIG_CONF2 0x074
79 #define SDMA_CHNENBL0_IMX35 0x200
80 #define SDMA_CHNENBL0_IMX31 0x080
81 #define SDMA_CHNPRI_0 0x100
82
83 /*
84 * Buffer descriptor status values.
85 */
86 #define BD_DONE 0x01
87 #define BD_WRAP 0x02
88 #define BD_CONT 0x04
89 #define BD_INTR 0x08
90 #define BD_RROR 0x10
91 #define BD_LAST 0x20
92 #define BD_EXTD 0x80
93
94 /*
95 * Data Node descriptor status values.
96 */
97 #define DND_END_OF_FRAME 0x80
98 #define DND_END_OF_XFER 0x40
99 #define DND_DONE 0x20
100 #define DND_UNUSED 0x01
101
102 /*
103 * IPCV2 descriptor status values.
104 */
105 #define BD_IPCV2_END_OF_FRAME 0x40
106
107 #define IPCV2_MAX_NODES 50
108 /*
109 * Error bit set in the CCB status field by the SDMA,
110 * in setbd routine, in case of a transfer error
111 */
112 #define DATA_ERROR 0x10000000
113
114 /*
115 * Buffer descriptor commands.
116 */
117 #define C0_ADDR 0x01
118 #define C0_LOAD 0x02
119 #define C0_DUMP 0x03
120 #define C0_SETCTX 0x07
121 #define C0_GETCTX 0x03
122 #define C0_SETDM 0x01
123 #define C0_SETPM 0x04
124 #define C0_GETDM 0x02
125 #define C0_GETPM 0x08
126 /*
127 * Change endianness indicator in the BD command field
128 */
129 #define CHANGE_ENDIANNESS 0x80
130
131 /*
132 * p_2_p watermark_level description
133 * Bits Name Description
134 * 0-7 Lower WML Lower watermark level
135 * 8 PS 1: Pad Swallowing
136 * 0: No Pad Swallowing
137 * 9 PA 1: Pad Adding
138 * 0: No Pad Adding
139 * 10 SPDIF If this bit is set both source
140 * and destination are on SPBA
141 * 11 Source Bit(SP) 1: Source on SPBA
142 * 0: Source on AIPS
143 * 12 Destination Bit(DP) 1: Destination on SPBA
144 * 0: Destination on AIPS
145 * 13-15 --------- MUST BE 0
146 * 16-23 Higher WML HWML
147 * 24-27 N Total number of samples after
148 * which Pad adding/Swallowing
149 * must be done. It must be odd.
150 * 28 Lower WML Event(LWE) SDMA events reg to check for
151 * LWML event mask
152 * 0: LWE in EVENTS register
153 * 1: LWE in EVENTS2 register
154 * 29 Higher WML Event(HWE) SDMA events reg to check for
155 * HWML event mask
156 * 0: HWE in EVENTS register
157 * 1: HWE in EVENTS2 register
158 * 30 --------- MUST BE 0
159 * 31 CONT 1: Amount of samples to be
160 * transferred is unknown and
161 * script will keep on
162 * transferring samples as long as
163 * both events are detected and
164 * script must be manually stopped
165 * by the application
166 * 0: The amount of samples to be
167 * transferred is equal to the
168 * count field of mode word
169 */
170 #define SDMA_WATERMARK_LEVEL_LWML 0xFF
171 #define SDMA_WATERMARK_LEVEL_PS BIT(8)
172 #define SDMA_WATERMARK_LEVEL_PA BIT(9)
173 #define SDMA_WATERMARK_LEVEL_SPDIF BIT(10)
174 #define SDMA_WATERMARK_LEVEL_SP BIT(11)
175 #define SDMA_WATERMARK_LEVEL_DP BIT(12)
176 #define SDMA_WATERMARK_LEVEL_HWML (0xFF << 16)
177 #define SDMA_WATERMARK_LEVEL_LWE BIT(28)
178 #define SDMA_WATERMARK_LEVEL_HWE BIT(29)
179 #define SDMA_WATERMARK_LEVEL_CONT BIT(31)
180
181 /*
182 * Mode/Count of data node descriptors - IPCv2
183 */
184 struct sdma_mode_count {
185 u32 count : 16; /* size of the buffer pointed by this BD */
186 u32 status : 8; /* E,R,I,C,W,D status bits stored here */
187 u32 command : 8; /* command mostlky used for channel 0 */
188 };
189
190 /*
191 * Buffer descriptor
192 */
193 struct sdma_buffer_descriptor {
194 struct sdma_mode_count mode;
195 u32 buffer_addr; /* address of the buffer described */
196 u32 ext_buffer_addr; /* extended buffer address */
197 } __attribute__ ((packed));
198
199 /**
200 * struct sdma_channel_control - Channel control Block
201 *
202 * @current_bd_ptr current buffer descriptor processed
203 * @base_bd_ptr first element of buffer descriptor array
204 * @unused padding. The SDMA engine expects an array of 128 byte
205 * control blocks
206 */
207 struct sdma_channel_control {
208 u32 current_bd_ptr;
209 u32 base_bd_ptr;
210 u32 unused[2];
211 } __attribute__ ((packed));
212
213 /**
214 * struct sdma_state_registers - SDMA context for a channel
215 *
216 * @pc: program counter
217 * @t: test bit: status of arithmetic & test instruction
218 * @rpc: return program counter
219 * @sf: source fault while loading data
220 * @spc: loop start program counter
221 * @df: destination fault while storing data
222 * @epc: loop end program counter
223 * @lm: loop mode
224 */
225 struct sdma_state_registers {
226 u32 pc :14;
227 u32 unused1: 1;
228 u32 t : 1;
229 u32 rpc :14;
230 u32 unused0: 1;
231 u32 sf : 1;
232 u32 spc :14;
233 u32 unused2: 1;
234 u32 df : 1;
235 u32 epc :14;
236 u32 lm : 2;
237 } __attribute__ ((packed));
238
239 /**
240 * struct sdma_context_data - sdma context specific to a channel
241 *
242 * @channel_state: channel state bits
243 * @gReg: general registers
244 * @mda: burst dma destination address register
245 * @msa: burst dma source address register
246 * @ms: burst dma status register
247 * @md: burst dma data register
248 * @pda: peripheral dma destination address register
249 * @psa: peripheral dma source address register
250 * @ps: peripheral dma status register
251 * @pd: peripheral dma data register
252 * @ca: CRC polynomial register
253 * @cs: CRC accumulator register
254 * @dda: dedicated core destination address register
255 * @dsa: dedicated core source address register
256 * @ds: dedicated core status register
257 * @dd: dedicated core data register
258 */
259 struct sdma_context_data {
260 struct sdma_state_registers channel_state;
261 u32 gReg[8];
262 u32 mda;
263 u32 msa;
264 u32 ms;
265 u32 md;
266 u32 pda;
267 u32 psa;
268 u32 ps;
269 u32 pd;
270 u32 ca;
271 u32 cs;
272 u32 dda;
273 u32 dsa;
274 u32 ds;
275 u32 dd;
276 u32 scratch0;
277 u32 scratch1;
278 u32 scratch2;
279 u32 scratch3;
280 u32 scratch4;
281 u32 scratch5;
282 u32 scratch6;
283 u32 scratch7;
284 } __attribute__ ((packed));
285
286 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
287
288 struct sdma_engine;
289
290 /**
291 * struct sdma_channel - housekeeping for a SDMA channel
292 *
293 * @sdma pointer to the SDMA engine for this channel
294 * @channel the channel number, matches dmaengine chan_id + 1
295 * @direction transfer type. Needed for setting SDMA script
296 * @peripheral_type Peripheral type. Needed for setting SDMA script
297 * @event_id0 aka dma request line
298 * @event_id1 for channels that use 2 events
299 * @word_size peripheral access size
300 * @buf_tail ID of the buffer that was processed
301 * @num_bd max NUM_BD. number of descriptors currently handling
302 */
303 struct sdma_channel {
304 struct sdma_engine *sdma;
305 unsigned int channel;
306 enum dma_transfer_direction direction;
307 enum sdma_peripheral_type peripheral_type;
308 unsigned int event_id0;
309 unsigned int event_id1;
310 enum dma_slave_buswidth word_size;
311 unsigned int buf_tail;
312 unsigned int num_bd;
313 unsigned int period_len;
314 struct sdma_buffer_descriptor *bd;
315 dma_addr_t bd_phys;
316 unsigned int pc_from_device, pc_to_device;
317 unsigned int device_to_device;
318 unsigned long flags;
319 dma_addr_t per_address, per_address2;
320 unsigned long event_mask[2];
321 unsigned long watermark_level;
322 u32 shp_addr, per_addr;
323 struct dma_chan chan;
324 spinlock_t lock;
325 struct dma_async_tx_descriptor desc;
326 enum dma_status status;
327 unsigned int chn_count;
328 unsigned int chn_real_count;
329 struct tasklet_struct tasklet;
330 struct imx_dma_data data;
331 };
332
333 #define IMX_DMA_SG_LOOP BIT(0)
334
335 #define MAX_DMA_CHANNELS 32
336 #define MXC_SDMA_DEFAULT_PRIORITY 1
337 #define MXC_SDMA_MIN_PRIORITY 1
338 #define MXC_SDMA_MAX_PRIORITY 7
339
340 #define SDMA_FIRMWARE_MAGIC 0x414d4453
341
342 /**
343 * struct sdma_firmware_header - Layout of the firmware image
344 *
345 * @magic "SDMA"
346 * @version_major increased whenever layout of struct sdma_script_start_addrs
347 * changes.
348 * @version_minor firmware minor version (for binary compatible changes)
349 * @script_addrs_start offset of struct sdma_script_start_addrs in this image
350 * @num_script_addrs Number of script addresses in this image
351 * @ram_code_start offset of SDMA ram image in this firmware image
352 * @ram_code_size size of SDMA ram image
353 * @script_addrs Stores the start address of the SDMA scripts
354 * (in SDMA memory space)
355 */
356 struct sdma_firmware_header {
357 u32 magic;
358 u32 version_major;
359 u32 version_minor;
360 u32 script_addrs_start;
361 u32 num_script_addrs;
362 u32 ram_code_start;
363 u32 ram_code_size;
364 };
365
366 struct sdma_driver_data {
367 int chnenbl0;
368 int num_events;
369 struct sdma_script_start_addrs *script_addrs;
370 };
371
372 struct sdma_engine {
373 struct device *dev;
374 struct device_dma_parameters dma_parms;
375 struct sdma_channel channel[MAX_DMA_CHANNELS];
376 struct sdma_channel_control *channel_control;
377 void __iomem *regs;
378 struct sdma_context_data *context;
379 dma_addr_t context_phys;
380 struct dma_device dma_device;
381 struct clk *clk_ipg;
382 struct clk *clk_ahb;
383 spinlock_t channel_0_lock;
384 u32 script_number;
385 struct sdma_script_start_addrs *script_addrs;
386 const struct sdma_driver_data *drvdata;
387 u32 spba_start_addr;
388 u32 spba_end_addr;
389 unsigned int irq;
390 };
391
392 static struct sdma_driver_data sdma_imx31 = {
393 .chnenbl0 = SDMA_CHNENBL0_IMX31,
394 .num_events = 32,
395 };
396
397 static struct sdma_script_start_addrs sdma_script_imx25 = {
398 .ap_2_ap_addr = 729,
399 .uart_2_mcu_addr = 904,
400 .per_2_app_addr = 1255,
401 .mcu_2_app_addr = 834,
402 .uartsh_2_mcu_addr = 1120,
403 .per_2_shp_addr = 1329,
404 .mcu_2_shp_addr = 1048,
405 .ata_2_mcu_addr = 1560,
406 .mcu_2_ata_addr = 1479,
407 .app_2_per_addr = 1189,
408 .app_2_mcu_addr = 770,
409 .shp_2_per_addr = 1407,
410 .shp_2_mcu_addr = 979,
411 };
412
413 static struct sdma_driver_data sdma_imx25 = {
414 .chnenbl0 = SDMA_CHNENBL0_IMX35,
415 .num_events = 48,
416 .script_addrs = &sdma_script_imx25,
417 };
418
419 static struct sdma_driver_data sdma_imx35 = {
420 .chnenbl0 = SDMA_CHNENBL0_IMX35,
421 .num_events = 48,
422 };
423
424 static struct sdma_script_start_addrs sdma_script_imx51 = {
425 .ap_2_ap_addr = 642,
426 .uart_2_mcu_addr = 817,
427 .mcu_2_app_addr = 747,
428 .mcu_2_shp_addr = 961,
429 .ata_2_mcu_addr = 1473,
430 .mcu_2_ata_addr = 1392,
431 .app_2_per_addr = 1033,
432 .app_2_mcu_addr = 683,
433 .shp_2_per_addr = 1251,
434 .shp_2_mcu_addr = 892,
435 };
436
437 static struct sdma_driver_data sdma_imx51 = {
438 .chnenbl0 = SDMA_CHNENBL0_IMX35,
439 .num_events = 48,
440 .script_addrs = &sdma_script_imx51,
441 };
442
443 static struct sdma_script_start_addrs sdma_script_imx53 = {
444 .ap_2_ap_addr = 642,
445 .app_2_mcu_addr = 683,
446 .mcu_2_app_addr = 747,
447 .uart_2_mcu_addr = 817,
448 .shp_2_mcu_addr = 891,
449 .mcu_2_shp_addr = 960,
450 .uartsh_2_mcu_addr = 1032,
451 .spdif_2_mcu_addr = 1100,
452 .mcu_2_spdif_addr = 1134,
453 .firi_2_mcu_addr = 1193,
454 .mcu_2_firi_addr = 1290,
455 };
456
457 static struct sdma_driver_data sdma_imx53 = {
458 .chnenbl0 = SDMA_CHNENBL0_IMX35,
459 .num_events = 48,
460 .script_addrs = &sdma_script_imx53,
461 };
462
463 static struct sdma_script_start_addrs sdma_script_imx6q = {
464 .ap_2_ap_addr = 642,
465 .uart_2_mcu_addr = 817,
466 .mcu_2_app_addr = 747,
467 .per_2_per_addr = 6331,
468 .uartsh_2_mcu_addr = 1032,
469 .mcu_2_shp_addr = 960,
470 .app_2_mcu_addr = 683,
471 .shp_2_mcu_addr = 891,
472 .spdif_2_mcu_addr = 1100,
473 .mcu_2_spdif_addr = 1134,
474 };
475
476 static struct sdma_driver_data sdma_imx6q = {
477 .chnenbl0 = SDMA_CHNENBL0_IMX35,
478 .num_events = 48,
479 .script_addrs = &sdma_script_imx6q,
480 };
481
482 static const struct platform_device_id sdma_devtypes[] = {
483 {
484 .name = "imx25-sdma",
485 .driver_data = (unsigned long)&sdma_imx25,
486 }, {
487 .name = "imx31-sdma",
488 .driver_data = (unsigned long)&sdma_imx31,
489 }, {
490 .name = "imx35-sdma",
491 .driver_data = (unsigned long)&sdma_imx35,
492 }, {
493 .name = "imx51-sdma",
494 .driver_data = (unsigned long)&sdma_imx51,
495 }, {
496 .name = "imx53-sdma",
497 .driver_data = (unsigned long)&sdma_imx53,
498 }, {
499 .name = "imx6q-sdma",
500 .driver_data = (unsigned long)&sdma_imx6q,
501 }, {
502 /* sentinel */
503 }
504 };
505 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
506
507 static const struct of_device_id sdma_dt_ids[] = {
508 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
509 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
510 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
511 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
512 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
513 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
514 { /* sentinel */ }
515 };
516 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
517
518 #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */
519 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */
520 #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */
521 #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/
522
523 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
524 {
525 u32 chnenbl0 = sdma->drvdata->chnenbl0;
526 return chnenbl0 + event * 4;
527 }
528
529 static int sdma_config_ownership(struct sdma_channel *sdmac,
530 bool event_override, bool mcu_override, bool dsp_override)
531 {
532 struct sdma_engine *sdma = sdmac->sdma;
533 int channel = sdmac->channel;
534 unsigned long evt, mcu, dsp;
535
536 if (event_override && mcu_override && dsp_override)
537 return -EINVAL;
538
539 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
540 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
541 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
542
543 if (dsp_override)
544 __clear_bit(channel, &dsp);
545 else
546 __set_bit(channel, &dsp);
547
548 if (event_override)
549 __clear_bit(channel, &evt);
550 else
551 __set_bit(channel, &evt);
552
553 if (mcu_override)
554 __clear_bit(channel, &mcu);
555 else
556 __set_bit(channel, &mcu);
557
558 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
559 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
560 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
561
562 return 0;
563 }
564
565 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
566 {
567 writel(BIT(channel), sdma->regs + SDMA_H_START);
568 }
569
570 /*
571 * sdma_run_channel0 - run a channel and wait till it's done
572 */
573 static int sdma_run_channel0(struct sdma_engine *sdma)
574 {
575 int ret;
576 u32 reg;
577
578 sdma_enable_channel(sdma, 0);
579
580 ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP,
581 reg, !(reg & 1), 1, 500);
582 if (ret)
583 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
584
585 /* Set bits of CONFIG register with dynamic context switching */
586 if (readl(sdma->regs + SDMA_H_CONFIG) == 0)
587 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
588
589 return ret;
590 }
591
592 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
593 u32 address)
594 {
595 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
596 void *buf_virt;
597 dma_addr_t buf_phys;
598 int ret;
599 unsigned long flags;
600
601 buf_virt = dma_alloc_coherent(NULL,
602 size,
603 &buf_phys, GFP_KERNEL);
604 if (!buf_virt) {
605 return -ENOMEM;
606 }
607
608 spin_lock_irqsave(&sdma->channel_0_lock, flags);
609
610 bd0->mode.command = C0_SETPM;
611 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
612 bd0->mode.count = size / 2;
613 bd0->buffer_addr = buf_phys;
614 bd0->ext_buffer_addr = address;
615
616 memcpy(buf_virt, buf, size);
617
618 ret = sdma_run_channel0(sdma);
619
620 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
621
622 dma_free_coherent(NULL, size, buf_virt, buf_phys);
623
624 return ret;
625 }
626
627 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
628 {
629 struct sdma_engine *sdma = sdmac->sdma;
630 int channel = sdmac->channel;
631 unsigned long val;
632 u32 chnenbl = chnenbl_ofs(sdma, event);
633
634 val = readl_relaxed(sdma->regs + chnenbl);
635 __set_bit(channel, &val);
636 writel_relaxed(val, sdma->regs + chnenbl);
637 }
638
639 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
640 {
641 struct sdma_engine *sdma = sdmac->sdma;
642 int channel = sdmac->channel;
643 u32 chnenbl = chnenbl_ofs(sdma, event);
644 unsigned long val;
645
646 val = readl_relaxed(sdma->regs + chnenbl);
647 __clear_bit(channel, &val);
648 writel_relaxed(val, sdma->regs + chnenbl);
649 }
650
651 static void sdma_update_channel_loop(struct sdma_channel *sdmac)
652 {
653 struct sdma_buffer_descriptor *bd;
654 int error = 0;
655 enum dma_status old_status = sdmac->status;
656
657 /*
658 * loop mode. Iterate over descriptors, re-setup them and
659 * call callback function.
660 */
661 while (1) {
662 bd = &sdmac->bd[sdmac->buf_tail];
663
664 if (bd->mode.status & BD_DONE)
665 break;
666
667 if (bd->mode.status & BD_RROR) {
668 bd->mode.status &= ~BD_RROR;
669 sdmac->status = DMA_ERROR;
670 error = -EIO;
671 }
672
673 /*
674 * We use bd->mode.count to calculate the residue, since contains
675 * the number of bytes present in the current buffer descriptor.
676 */
677
678 sdmac->chn_real_count = bd->mode.count;
679 bd->mode.status |= BD_DONE;
680 bd->mode.count = sdmac->period_len;
681
682 /*
683 * The callback is called from the interrupt context in order
684 * to reduce latency and to avoid the risk of altering the
685 * SDMA transaction status by the time the client tasklet is
686 * executed.
687 */
688
689 if (sdmac->desc.callback)
690 sdmac->desc.callback(sdmac->desc.callback_param);
691
692 sdmac->buf_tail++;
693 sdmac->buf_tail %= sdmac->num_bd;
694
695 if (error)
696 sdmac->status = old_status;
697 }
698 }
699
700 static void mxc_sdma_handle_channel_normal(unsigned long data)
701 {
702 struct sdma_channel *sdmac = (struct sdma_channel *) data;
703 struct sdma_buffer_descriptor *bd;
704 int i, error = 0;
705
706 sdmac->chn_real_count = 0;
707 /*
708 * non loop mode. Iterate over all descriptors, collect
709 * errors and call callback function
710 */
711 for (i = 0; i < sdmac->num_bd; i++) {
712 bd = &sdmac->bd[i];
713
714 if (bd->mode.status & (BD_DONE | BD_RROR))
715 error = -EIO;
716 sdmac->chn_real_count += bd->mode.count;
717 }
718
719 if (error)
720 sdmac->status = DMA_ERROR;
721 else
722 sdmac->status = DMA_COMPLETE;
723
724 dma_cookie_complete(&sdmac->desc);
725 if (sdmac->desc.callback)
726 sdmac->desc.callback(sdmac->desc.callback_param);
727 }
728
729 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
730 {
731 struct sdma_engine *sdma = dev_id;
732 unsigned long stat;
733
734 stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
735 writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
736 /* channel 0 is special and not handled here, see run_channel0() */
737 stat &= ~1;
738
739 while (stat) {
740 int channel = fls(stat) - 1;
741 struct sdma_channel *sdmac = &sdma->channel[channel];
742
743 if (sdmac->flags & IMX_DMA_SG_LOOP)
744 sdma_update_channel_loop(sdmac);
745 else
746 tasklet_schedule(&sdmac->tasklet);
747
748 __clear_bit(channel, &stat);
749 }
750
751 return IRQ_HANDLED;
752 }
753
754 /*
755 * sets the pc of SDMA script according to the peripheral type
756 */
757 static void sdma_get_pc(struct sdma_channel *sdmac,
758 enum sdma_peripheral_type peripheral_type)
759 {
760 struct sdma_engine *sdma = sdmac->sdma;
761 int per_2_emi = 0, emi_2_per = 0;
762 /*
763 * These are needed once we start to support transfers between
764 * two peripherals or memory-to-memory transfers
765 */
766 int per_2_per = 0;
767
768 sdmac->pc_from_device = 0;
769 sdmac->pc_to_device = 0;
770 sdmac->device_to_device = 0;
771
772 switch (peripheral_type) {
773 case IMX_DMATYPE_MEMORY:
774 break;
775 case IMX_DMATYPE_DSP:
776 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
777 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
778 break;
779 case IMX_DMATYPE_FIRI:
780 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
781 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
782 break;
783 case IMX_DMATYPE_UART:
784 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
785 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
786 break;
787 case IMX_DMATYPE_UART_SP:
788 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
789 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
790 break;
791 case IMX_DMATYPE_ATA:
792 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
793 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
794 break;
795 case IMX_DMATYPE_CSPI:
796 case IMX_DMATYPE_EXT:
797 case IMX_DMATYPE_SSI:
798 case IMX_DMATYPE_SAI:
799 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
800 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
801 break;
802 case IMX_DMATYPE_SSI_DUAL:
803 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
804 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
805 break;
806 case IMX_DMATYPE_SSI_SP:
807 case IMX_DMATYPE_MMC:
808 case IMX_DMATYPE_SDHC:
809 case IMX_DMATYPE_CSPI_SP:
810 case IMX_DMATYPE_ESAI:
811 case IMX_DMATYPE_MSHC_SP:
812 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
813 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
814 break;
815 case IMX_DMATYPE_ASRC:
816 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
817 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
818 per_2_per = sdma->script_addrs->per_2_per_addr;
819 break;
820 case IMX_DMATYPE_ASRC_SP:
821 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
822 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
823 per_2_per = sdma->script_addrs->per_2_per_addr;
824 break;
825 case IMX_DMATYPE_MSHC:
826 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
827 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
828 break;
829 case IMX_DMATYPE_CCM:
830 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
831 break;
832 case IMX_DMATYPE_SPDIF:
833 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
834 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
835 break;
836 case IMX_DMATYPE_IPU_MEMORY:
837 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
838 break;
839 default:
840 break;
841 }
842
843 sdmac->pc_from_device = per_2_emi;
844 sdmac->pc_to_device = emi_2_per;
845 sdmac->device_to_device = per_2_per;
846 }
847
848 static int sdma_load_context(struct sdma_channel *sdmac)
849 {
850 struct sdma_engine *sdma = sdmac->sdma;
851 int channel = sdmac->channel;
852 int load_address;
853 struct sdma_context_data *context = sdma->context;
854 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
855 int ret;
856 unsigned long flags;
857
858 if (sdmac->direction == DMA_DEV_TO_MEM)
859 load_address = sdmac->pc_from_device;
860 else if (sdmac->direction == DMA_DEV_TO_DEV)
861 load_address = sdmac->device_to_device;
862 else
863 load_address = sdmac->pc_to_device;
864
865 if (load_address < 0)
866 return load_address;
867
868 dev_dbg(sdma->dev, "load_address = %d\n", load_address);
869 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
870 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
871 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
872 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
873 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
874
875 spin_lock_irqsave(&sdma->channel_0_lock, flags);
876
877 memset(context, 0, sizeof(*context));
878 context->channel_state.pc = load_address;
879
880 /* Send by context the event mask,base address for peripheral
881 * and watermark level
882 */
883 context->gReg[0] = sdmac->event_mask[1];
884 context->gReg[1] = sdmac->event_mask[0];
885 context->gReg[2] = sdmac->per_addr;
886 context->gReg[6] = sdmac->shp_addr;
887 context->gReg[7] = sdmac->watermark_level;
888
889 bd0->mode.command = C0_SETDM;
890 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
891 bd0->mode.count = sizeof(*context) / 4;
892 bd0->buffer_addr = sdma->context_phys;
893 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
894 ret = sdma_run_channel0(sdma);
895
896 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
897
898 return ret;
899 }
900
901 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
902 {
903 return container_of(chan, struct sdma_channel, chan);
904 }
905
906 static int sdma_disable_channel(struct dma_chan *chan)
907 {
908 struct sdma_channel *sdmac = to_sdma_chan(chan);
909 struct sdma_engine *sdma = sdmac->sdma;
910 int channel = sdmac->channel;
911
912 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
913 sdmac->status = DMA_ERROR;
914
915 return 0;
916 }
917
918 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
919 {
920 struct sdma_engine *sdma = sdmac->sdma;
921
922 int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML;
923 int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16;
924
925 set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]);
926 set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]);
927
928 if (sdmac->event_id0 > 31)
929 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE;
930
931 if (sdmac->event_id1 > 31)
932 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE;
933
934 /*
935 * If LWML(src_maxburst) > HWML(dst_maxburst), we need
936 * swap LWML and HWML of INFO(A.3.2.5.1), also need swap
937 * r0(event_mask[1]) and r1(event_mask[0]).
938 */
939 if (lwml > hwml) {
940 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML |
941 SDMA_WATERMARK_LEVEL_HWML);
942 sdmac->watermark_level |= hwml;
943 sdmac->watermark_level |= lwml << 16;
944 swap(sdmac->event_mask[0], sdmac->event_mask[1]);
945 }
946
947 if (sdmac->per_address2 >= sdma->spba_start_addr &&
948 sdmac->per_address2 <= sdma->spba_end_addr)
949 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP;
950
951 if (sdmac->per_address >= sdma->spba_start_addr &&
952 sdmac->per_address <= sdma->spba_end_addr)
953 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP;
954
955 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
956 }
957
958 static int sdma_config_channel(struct dma_chan *chan)
959 {
960 struct sdma_channel *sdmac = to_sdma_chan(chan);
961 int ret;
962
963 sdma_disable_channel(chan);
964
965 sdmac->event_mask[0] = 0;
966 sdmac->event_mask[1] = 0;
967 sdmac->shp_addr = 0;
968 sdmac->per_addr = 0;
969
970 if (sdmac->event_id0) {
971 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
972 return -EINVAL;
973 sdma_event_enable(sdmac, sdmac->event_id0);
974 }
975
976 if (sdmac->event_id1) {
977 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
978 return -EINVAL;
979 sdma_event_enable(sdmac, sdmac->event_id1);
980 }
981
982 switch (sdmac->peripheral_type) {
983 case IMX_DMATYPE_DSP:
984 sdma_config_ownership(sdmac, false, true, true);
985 break;
986 case IMX_DMATYPE_MEMORY:
987 sdma_config_ownership(sdmac, false, true, false);
988 break;
989 default:
990 sdma_config_ownership(sdmac, true, true, false);
991 break;
992 }
993
994 sdma_get_pc(sdmac, sdmac->peripheral_type);
995
996 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
997 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
998 /* Handle multiple event channels differently */
999 if (sdmac->event_id1) {
1000 if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
1001 sdmac->peripheral_type == IMX_DMATYPE_ASRC)
1002 sdma_set_watermarklevel_for_p2p(sdmac);
1003 } else
1004 __set_bit(sdmac->event_id0, sdmac->event_mask);
1005
1006 /* Address */
1007 sdmac->shp_addr = sdmac->per_address;
1008 sdmac->per_addr = sdmac->per_address2;
1009 } else {
1010 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
1011 }
1012
1013 ret = sdma_load_context(sdmac);
1014
1015 return ret;
1016 }
1017
1018 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
1019 unsigned int priority)
1020 {
1021 struct sdma_engine *sdma = sdmac->sdma;
1022 int channel = sdmac->channel;
1023
1024 if (priority < MXC_SDMA_MIN_PRIORITY
1025 || priority > MXC_SDMA_MAX_PRIORITY) {
1026 return -EINVAL;
1027 }
1028
1029 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
1030
1031 return 0;
1032 }
1033
1034 static int sdma_request_channel(struct sdma_channel *sdmac)
1035 {
1036 struct sdma_engine *sdma = sdmac->sdma;
1037 int channel = sdmac->channel;
1038 int ret = -EBUSY;
1039
1040 sdmac->bd = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys,
1041 GFP_KERNEL);
1042 if (!sdmac->bd) {
1043 ret = -ENOMEM;
1044 goto out;
1045 }
1046
1047 sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
1048 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1049
1050 sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
1051 return 0;
1052 out:
1053
1054 return ret;
1055 }
1056
1057 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
1058 {
1059 unsigned long flags;
1060 struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
1061 dma_cookie_t cookie;
1062
1063 spin_lock_irqsave(&sdmac->lock, flags);
1064
1065 cookie = dma_cookie_assign(tx);
1066
1067 spin_unlock_irqrestore(&sdmac->lock, flags);
1068
1069 return cookie;
1070 }
1071
1072 static int sdma_alloc_chan_resources(struct dma_chan *chan)
1073 {
1074 struct sdma_channel *sdmac = to_sdma_chan(chan);
1075 struct imx_dma_data *data = chan->private;
1076 int prio, ret;
1077
1078 if (!data)
1079 return -EINVAL;
1080
1081 switch (data->priority) {
1082 case DMA_PRIO_HIGH:
1083 prio = 3;
1084 break;
1085 case DMA_PRIO_MEDIUM:
1086 prio = 2;
1087 break;
1088 case DMA_PRIO_LOW:
1089 default:
1090 prio = 1;
1091 break;
1092 }
1093
1094 sdmac->peripheral_type = data->peripheral_type;
1095 sdmac->event_id0 = data->dma_request;
1096 sdmac->event_id1 = data->dma_request2;
1097
1098 ret = clk_enable(sdmac->sdma->clk_ipg);
1099 if (ret)
1100 return ret;
1101 ret = clk_enable(sdmac->sdma->clk_ahb);
1102 if (ret)
1103 goto disable_clk_ipg;
1104
1105 ret = sdma_request_channel(sdmac);
1106 if (ret)
1107 goto disable_clk_ahb;
1108
1109 ret = sdma_set_channel_priority(sdmac, prio);
1110 if (ret)
1111 goto disable_clk_ahb;
1112
1113 dma_async_tx_descriptor_init(&sdmac->desc, chan);
1114 sdmac->desc.tx_submit = sdma_tx_submit;
1115 /* txd.flags will be overwritten in prep funcs */
1116 sdmac->desc.flags = DMA_CTRL_ACK;
1117
1118 return 0;
1119
1120 disable_clk_ahb:
1121 clk_disable(sdmac->sdma->clk_ahb);
1122 disable_clk_ipg:
1123 clk_disable(sdmac->sdma->clk_ipg);
1124 return ret;
1125 }
1126
1127 static void sdma_free_chan_resources(struct dma_chan *chan)
1128 {
1129 struct sdma_channel *sdmac = to_sdma_chan(chan);
1130 struct sdma_engine *sdma = sdmac->sdma;
1131
1132 sdma_disable_channel(chan);
1133
1134 if (sdmac->event_id0)
1135 sdma_event_disable(sdmac, sdmac->event_id0);
1136 if (sdmac->event_id1)
1137 sdma_event_disable(sdmac, sdmac->event_id1);
1138
1139 sdmac->event_id0 = 0;
1140 sdmac->event_id1 = 0;
1141
1142 sdma_set_channel_priority(sdmac, 0);
1143
1144 dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
1145
1146 clk_disable(sdma->clk_ipg);
1147 clk_disable(sdma->clk_ahb);
1148 }
1149
1150 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
1151 struct dma_chan *chan, struct scatterlist *sgl,
1152 unsigned int sg_len, enum dma_transfer_direction direction,
1153 unsigned long flags, void *context)
1154 {
1155 struct sdma_channel *sdmac = to_sdma_chan(chan);
1156 struct sdma_engine *sdma = sdmac->sdma;
1157 int ret, i, count;
1158 int channel = sdmac->channel;
1159 struct scatterlist *sg;
1160
1161 if (sdmac->status == DMA_IN_PROGRESS)
1162 return NULL;
1163 sdmac->status = DMA_IN_PROGRESS;
1164
1165 sdmac->flags = 0;
1166
1167 sdmac->buf_tail = 0;
1168
1169 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1170 sg_len, channel);
1171
1172 sdmac->direction = direction;
1173 ret = sdma_load_context(sdmac);
1174 if (ret)
1175 goto err_out;
1176
1177 if (sg_len > NUM_BD) {
1178 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1179 channel, sg_len, NUM_BD);
1180 ret = -EINVAL;
1181 goto err_out;
1182 }
1183
1184 sdmac->chn_count = 0;
1185 for_each_sg(sgl, sg, sg_len, i) {
1186 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1187 int param;
1188
1189 bd->buffer_addr = sg->dma_address;
1190
1191 count = sg_dma_len(sg);
1192
1193 if (count > 0xffff) {
1194 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1195 channel, count, 0xffff);
1196 ret = -EINVAL;
1197 goto err_out;
1198 }
1199
1200 bd->mode.count = count;
1201 sdmac->chn_count += count;
1202
1203 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
1204 ret = -EINVAL;
1205 goto err_out;
1206 }
1207
1208 switch (sdmac->word_size) {
1209 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1210 bd->mode.command = 0;
1211 if (count & 3 || sg->dma_address & 3)
1212 return NULL;
1213 break;
1214 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1215 bd->mode.command = 2;
1216 if (count & 1 || sg->dma_address & 1)
1217 return NULL;
1218 break;
1219 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1220 bd->mode.command = 1;
1221 break;
1222 default:
1223 return NULL;
1224 }
1225
1226 param = BD_DONE | BD_EXTD | BD_CONT;
1227
1228 if (i + 1 == sg_len) {
1229 param |= BD_INTR;
1230 param |= BD_LAST;
1231 param &= ~BD_CONT;
1232 }
1233
1234 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1235 i, count, (u64)sg->dma_address,
1236 param & BD_WRAP ? "wrap" : "",
1237 param & BD_INTR ? " intr" : "");
1238
1239 bd->mode.status = param;
1240 }
1241
1242 sdmac->num_bd = sg_len;
1243 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1244
1245 return &sdmac->desc;
1246 err_out:
1247 sdmac->status = DMA_ERROR;
1248 return NULL;
1249 }
1250
1251 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1252 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1253 size_t period_len, enum dma_transfer_direction direction,
1254 unsigned long flags)
1255 {
1256 struct sdma_channel *sdmac = to_sdma_chan(chan);
1257 struct sdma_engine *sdma = sdmac->sdma;
1258 int num_periods = buf_len / period_len;
1259 int channel = sdmac->channel;
1260 int ret, i = 0, buf = 0;
1261
1262 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1263
1264 if (sdmac->status == DMA_IN_PROGRESS)
1265 return NULL;
1266
1267 sdmac->status = DMA_IN_PROGRESS;
1268
1269 sdmac->buf_tail = 0;
1270 sdmac->period_len = period_len;
1271
1272 sdmac->flags |= IMX_DMA_SG_LOOP;
1273 sdmac->direction = direction;
1274 ret = sdma_load_context(sdmac);
1275 if (ret)
1276 goto err_out;
1277
1278 if (num_periods > NUM_BD) {
1279 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1280 channel, num_periods, NUM_BD);
1281 goto err_out;
1282 }
1283
1284 if (period_len > 0xffff) {
1285 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1286 channel, period_len, 0xffff);
1287 goto err_out;
1288 }
1289
1290 while (buf < buf_len) {
1291 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1292 int param;
1293
1294 bd->buffer_addr = dma_addr;
1295
1296 bd->mode.count = period_len;
1297
1298 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1299 goto err_out;
1300 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1301 bd->mode.command = 0;
1302 else
1303 bd->mode.command = sdmac->word_size;
1304
1305 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1306 if (i + 1 == num_periods)
1307 param |= BD_WRAP;
1308
1309 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1310 i, period_len, (u64)dma_addr,
1311 param & BD_WRAP ? "wrap" : "",
1312 param & BD_INTR ? " intr" : "");
1313
1314 bd->mode.status = param;
1315
1316 dma_addr += period_len;
1317 buf += period_len;
1318
1319 i++;
1320 }
1321
1322 sdmac->num_bd = num_periods;
1323 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1324
1325 return &sdmac->desc;
1326 err_out:
1327 sdmac->status = DMA_ERROR;
1328 return NULL;
1329 }
1330
1331 static int sdma_config(struct dma_chan *chan,
1332 struct dma_slave_config *dmaengine_cfg)
1333 {
1334 struct sdma_channel *sdmac = to_sdma_chan(chan);
1335
1336 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1337 sdmac->per_address = dmaengine_cfg->src_addr;
1338 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1339 dmaengine_cfg->src_addr_width;
1340 sdmac->word_size = dmaengine_cfg->src_addr_width;
1341 } else if (dmaengine_cfg->direction == DMA_DEV_TO_DEV) {
1342 sdmac->per_address2 = dmaengine_cfg->src_addr;
1343 sdmac->per_address = dmaengine_cfg->dst_addr;
1344 sdmac->watermark_level = dmaengine_cfg->src_maxburst &
1345 SDMA_WATERMARK_LEVEL_LWML;
1346 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) &
1347 SDMA_WATERMARK_LEVEL_HWML;
1348 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1349 } else {
1350 sdmac->per_address = dmaengine_cfg->dst_addr;
1351 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1352 dmaengine_cfg->dst_addr_width;
1353 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1354 }
1355 sdmac->direction = dmaengine_cfg->direction;
1356 return sdma_config_channel(chan);
1357 }
1358
1359 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1360 dma_cookie_t cookie,
1361 struct dma_tx_state *txstate)
1362 {
1363 struct sdma_channel *sdmac = to_sdma_chan(chan);
1364 u32 residue;
1365
1366 if (sdmac->flags & IMX_DMA_SG_LOOP)
1367 residue = (sdmac->num_bd - sdmac->buf_tail) *
1368 sdmac->period_len - sdmac->chn_real_count;
1369 else
1370 residue = sdmac->chn_count - sdmac->chn_real_count;
1371
1372 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1373 residue);
1374
1375 return sdmac->status;
1376 }
1377
1378 static void sdma_issue_pending(struct dma_chan *chan)
1379 {
1380 struct sdma_channel *sdmac = to_sdma_chan(chan);
1381 struct sdma_engine *sdma = sdmac->sdma;
1382
1383 if (sdmac->status == DMA_IN_PROGRESS)
1384 sdma_enable_channel(sdma, sdmac->channel);
1385 }
1386
1387 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1388 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
1389 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41
1390
1391 static void sdma_add_scripts(struct sdma_engine *sdma,
1392 const struct sdma_script_start_addrs *addr)
1393 {
1394 s32 *addr_arr = (u32 *)addr;
1395 s32 *saddr_arr = (u32 *)sdma->script_addrs;
1396 int i;
1397
1398 /* use the default firmware in ROM if missing external firmware */
1399 if (!sdma->script_number)
1400 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1401
1402 for (i = 0; i < sdma->script_number; i++)
1403 if (addr_arr[i] > 0)
1404 saddr_arr[i] = addr_arr[i];
1405 }
1406
1407 static void sdma_load_firmware(const struct firmware *fw, void *context)
1408 {
1409 struct sdma_engine *sdma = context;
1410 const struct sdma_firmware_header *header;
1411 const struct sdma_script_start_addrs *addr;
1412 unsigned short *ram_code;
1413
1414 if (!fw) {
1415 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
1416 /* In this case we just use the ROM firmware. */
1417 return;
1418 }
1419
1420 if (fw->size < sizeof(*header))
1421 goto err_firmware;
1422
1423 header = (struct sdma_firmware_header *)fw->data;
1424
1425 if (header->magic != SDMA_FIRMWARE_MAGIC)
1426 goto err_firmware;
1427 if (header->ram_code_start + header->ram_code_size > fw->size)
1428 goto err_firmware;
1429 switch (header->version_major) {
1430 case 1:
1431 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1432 break;
1433 case 2:
1434 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1435 break;
1436 case 3:
1437 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
1438 break;
1439 default:
1440 dev_err(sdma->dev, "unknown firmware version\n");
1441 goto err_firmware;
1442 }
1443
1444 addr = (void *)header + header->script_addrs_start;
1445 ram_code = (void *)header + header->ram_code_start;
1446
1447 clk_enable(sdma->clk_ipg);
1448 clk_enable(sdma->clk_ahb);
1449 /* download the RAM image for SDMA */
1450 sdma_load_script(sdma, ram_code,
1451 header->ram_code_size,
1452 addr->ram_code_start_addr);
1453 clk_disable(sdma->clk_ipg);
1454 clk_disable(sdma->clk_ahb);
1455
1456 sdma_add_scripts(sdma, addr);
1457
1458 dev_info(sdma->dev, "loaded firmware %d.%d\n",
1459 header->version_major,
1460 header->version_minor);
1461
1462 err_firmware:
1463 release_firmware(fw);
1464 }
1465
1466 #define EVENT_REMAP_CELLS 3
1467
1468 static int sdma_event_remap(struct sdma_engine *sdma)
1469 {
1470 struct device_node *np = sdma->dev->of_node;
1471 struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0);
1472 struct property *event_remap;
1473 struct regmap *gpr;
1474 char propname[] = "fsl,sdma-event-remap";
1475 u32 reg, val, shift, num_map, i;
1476 int ret = 0;
1477
1478 if (IS_ERR(np) || IS_ERR(gpr_np))
1479 goto out;
1480
1481 event_remap = of_find_property(np, propname, NULL);
1482 num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0;
1483 if (!num_map) {
1484 dev_dbg(sdma->dev, "no event needs to be remapped\n");
1485 goto out;
1486 } else if (num_map % EVENT_REMAP_CELLS) {
1487 dev_err(sdma->dev, "the property %s must modulo %d\n",
1488 propname, EVENT_REMAP_CELLS);
1489 ret = -EINVAL;
1490 goto out;
1491 }
1492
1493 gpr = syscon_node_to_regmap(gpr_np);
1494 if (IS_ERR(gpr)) {
1495 dev_err(sdma->dev, "failed to get gpr regmap\n");
1496 ret = PTR_ERR(gpr);
1497 goto out;
1498 }
1499
1500 for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) {
1501 ret = of_property_read_u32_index(np, propname, i, &reg);
1502 if (ret) {
1503 dev_err(sdma->dev, "failed to read property %s index %d\n",
1504 propname, i);
1505 goto out;
1506 }
1507
1508 ret = of_property_read_u32_index(np, propname, i + 1, &shift);
1509 if (ret) {
1510 dev_err(sdma->dev, "failed to read property %s index %d\n",
1511 propname, i + 1);
1512 goto out;
1513 }
1514
1515 ret = of_property_read_u32_index(np, propname, i + 2, &val);
1516 if (ret) {
1517 dev_err(sdma->dev, "failed to read property %s index %d\n",
1518 propname, i + 2);
1519 goto out;
1520 }
1521
1522 regmap_update_bits(gpr, reg, BIT(shift), val << shift);
1523 }
1524
1525 out:
1526 if (!IS_ERR(gpr_np))
1527 of_node_put(gpr_np);
1528
1529 return ret;
1530 }
1531
1532 static int sdma_get_firmware(struct sdma_engine *sdma,
1533 const char *fw_name)
1534 {
1535 int ret;
1536
1537 ret = request_firmware_nowait(THIS_MODULE,
1538 FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1539 GFP_KERNEL, sdma, sdma_load_firmware);
1540
1541 return ret;
1542 }
1543
1544 static int sdma_init(struct sdma_engine *sdma)
1545 {
1546 int i, ret;
1547 dma_addr_t ccb_phys;
1548
1549 ret = clk_enable(sdma->clk_ipg);
1550 if (ret)
1551 return ret;
1552 ret = clk_enable(sdma->clk_ahb);
1553 if (ret)
1554 goto disable_clk_ipg;
1555
1556 /* Be sure SDMA has not started yet */
1557 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1558
1559 sdma->channel_control = dma_alloc_coherent(NULL,
1560 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1561 sizeof(struct sdma_context_data),
1562 &ccb_phys, GFP_KERNEL);
1563
1564 if (!sdma->channel_control) {
1565 ret = -ENOMEM;
1566 goto err_dma_alloc;
1567 }
1568
1569 sdma->context = (void *)sdma->channel_control +
1570 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1571 sdma->context_phys = ccb_phys +
1572 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1573
1574 /* Zero-out the CCB structures array just allocated */
1575 memset(sdma->channel_control, 0,
1576 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1577
1578 /* disable all channels */
1579 for (i = 0; i < sdma->drvdata->num_events; i++)
1580 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1581
1582 /* All channels have priority 0 */
1583 for (i = 0; i < MAX_DMA_CHANNELS; i++)
1584 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1585
1586 ret = sdma_request_channel(&sdma->channel[0]);
1587 if (ret)
1588 goto err_dma_alloc;
1589
1590 sdma_config_ownership(&sdma->channel[0], false, true, false);
1591
1592 /* Set Command Channel (Channel Zero) */
1593 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1594
1595 /* Set bits of CONFIG register but with static context switching */
1596 /* FIXME: Check whether to set ACR bit depending on clock ratios */
1597 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1598
1599 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1600
1601 /* Initializes channel's priorities */
1602 sdma_set_channel_priority(&sdma->channel[0], 7);
1603
1604 clk_disable(sdma->clk_ipg);
1605 clk_disable(sdma->clk_ahb);
1606
1607 return 0;
1608
1609 err_dma_alloc:
1610 clk_disable(sdma->clk_ahb);
1611 disable_clk_ipg:
1612 clk_disable(sdma->clk_ipg);
1613 dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1614 return ret;
1615 }
1616
1617 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
1618 {
1619 struct sdma_channel *sdmac = to_sdma_chan(chan);
1620 struct imx_dma_data *data = fn_param;
1621
1622 if (!imx_dma_is_general_purpose(chan))
1623 return false;
1624
1625 sdmac->data = *data;
1626 chan->private = &sdmac->data;
1627
1628 return true;
1629 }
1630
1631 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
1632 struct of_dma *ofdma)
1633 {
1634 struct sdma_engine *sdma = ofdma->of_dma_data;
1635 dma_cap_mask_t mask = sdma->dma_device.cap_mask;
1636 struct imx_dma_data data;
1637
1638 if (dma_spec->args_count != 3)
1639 return NULL;
1640
1641 data.dma_request = dma_spec->args[0];
1642 data.peripheral_type = dma_spec->args[1];
1643 data.priority = dma_spec->args[2];
1644 /*
1645 * init dma_request2 to zero, which is not used by the dts.
1646 * For P2P, dma_request2 is init from dma_request_channel(),
1647 * chan->private will point to the imx_dma_data, and in
1648 * device_alloc_chan_resources(), imx_dma_data.dma_request2 will
1649 * be set to sdmac->event_id1.
1650 */
1651 data.dma_request2 = 0;
1652
1653 return dma_request_channel(mask, sdma_filter_fn, &data);
1654 }
1655
1656 static int sdma_probe(struct platform_device *pdev)
1657 {
1658 const struct of_device_id *of_id =
1659 of_match_device(sdma_dt_ids, &pdev->dev);
1660 struct device_node *np = pdev->dev.of_node;
1661 struct device_node *spba_bus;
1662 const char *fw_name;
1663 int ret;
1664 int irq;
1665 struct resource *iores;
1666 struct resource spba_res;
1667 struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1668 int i;
1669 struct sdma_engine *sdma;
1670 s32 *saddr_arr;
1671 const struct sdma_driver_data *drvdata = NULL;
1672
1673 if (of_id)
1674 drvdata = of_id->data;
1675 else if (pdev->id_entry)
1676 drvdata = (void *)pdev->id_entry->driver_data;
1677
1678 if (!drvdata) {
1679 dev_err(&pdev->dev, "unable to find driver data\n");
1680 return -EINVAL;
1681 }
1682
1683 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1684 if (ret)
1685 return ret;
1686
1687 sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL);
1688 if (!sdma)
1689 return -ENOMEM;
1690
1691 spin_lock_init(&sdma->channel_0_lock);
1692
1693 sdma->dev = &pdev->dev;
1694 sdma->drvdata = drvdata;
1695
1696 irq = platform_get_irq(pdev, 0);
1697 if (irq < 0)
1698 return irq;
1699
1700 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1701 sdma->regs = devm_ioremap_resource(&pdev->dev, iores);
1702 if (IS_ERR(sdma->regs))
1703 return PTR_ERR(sdma->regs);
1704
1705 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1706 if (IS_ERR(sdma->clk_ipg))
1707 return PTR_ERR(sdma->clk_ipg);
1708
1709 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1710 if (IS_ERR(sdma->clk_ahb))
1711 return PTR_ERR(sdma->clk_ahb);
1712
1713 clk_prepare(sdma->clk_ipg);
1714 clk_prepare(sdma->clk_ahb);
1715
1716 ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma",
1717 sdma);
1718 if (ret)
1719 return ret;
1720
1721 sdma->irq = irq;
1722
1723 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1724 if (!sdma->script_addrs)
1725 return -ENOMEM;
1726
1727 /* initially no scripts available */
1728 saddr_arr = (s32 *)sdma->script_addrs;
1729 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1730 saddr_arr[i] = -EINVAL;
1731
1732 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1733 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1734
1735 INIT_LIST_HEAD(&sdma->dma_device.channels);
1736 /* Initialize channel parameters */
1737 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1738 struct sdma_channel *sdmac = &sdma->channel[i];
1739
1740 sdmac->sdma = sdma;
1741 spin_lock_init(&sdmac->lock);
1742
1743 sdmac->chan.device = &sdma->dma_device;
1744 dma_cookie_init(&sdmac->chan);
1745 sdmac->channel = i;
1746
1747 tasklet_init(&sdmac->tasklet, mxc_sdma_handle_channel_normal,
1748 (unsigned long) sdmac);
1749 /*
1750 * Add the channel to the DMAC list. Do not add channel 0 though
1751 * because we need it internally in the SDMA driver. This also means
1752 * that channel 0 in dmaengine counting matches sdma channel 1.
1753 */
1754 if (i)
1755 list_add_tail(&sdmac->chan.device_node,
1756 &sdma->dma_device.channels);
1757 }
1758
1759 ret = sdma_init(sdma);
1760 if (ret)
1761 goto err_init;
1762
1763 ret = sdma_event_remap(sdma);
1764 if (ret)
1765 goto err_init;
1766
1767 if (sdma->drvdata->script_addrs)
1768 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
1769 if (pdata && pdata->script_addrs)
1770 sdma_add_scripts(sdma, pdata->script_addrs);
1771
1772 if (pdata) {
1773 ret = sdma_get_firmware(sdma, pdata->fw_name);
1774 if (ret)
1775 dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
1776 } else {
1777 /*
1778 * Because that device tree does not encode ROM script address,
1779 * the RAM script in firmware is mandatory for device tree
1780 * probe, otherwise it fails.
1781 */
1782 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1783 &fw_name);
1784 if (ret)
1785 dev_warn(&pdev->dev, "failed to get firmware name\n");
1786 else {
1787 ret = sdma_get_firmware(sdma, fw_name);
1788 if (ret)
1789 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
1790 }
1791 }
1792
1793 sdma->dma_device.dev = &pdev->dev;
1794
1795 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1796 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1797 sdma->dma_device.device_tx_status = sdma_tx_status;
1798 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1799 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1800 sdma->dma_device.device_config = sdma_config;
1801 sdma->dma_device.device_terminate_all = sdma_disable_channel;
1802 sdma->dma_device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1803 sdma->dma_device.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1804 sdma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1805 sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1806 sdma->dma_device.device_issue_pending = sdma_issue_pending;
1807 sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1808 dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1809
1810 platform_set_drvdata(pdev, sdma);
1811
1812 ret = dma_async_device_register(&sdma->dma_device);
1813 if (ret) {
1814 dev_err(&pdev->dev, "unable to register\n");
1815 goto err_init;
1816 }
1817
1818 if (np) {
1819 ret = of_dma_controller_register(np, sdma_xlate, sdma);
1820 if (ret) {
1821 dev_err(&pdev->dev, "failed to register controller\n");
1822 goto err_register;
1823 }
1824
1825 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus");
1826 ret = of_address_to_resource(spba_bus, 0, &spba_res);
1827 if (!ret) {
1828 sdma->spba_start_addr = spba_res.start;
1829 sdma->spba_end_addr = spba_res.end;
1830 }
1831 of_node_put(spba_bus);
1832 }
1833
1834 return 0;
1835
1836 err_register:
1837 dma_async_device_unregister(&sdma->dma_device);
1838 err_init:
1839 kfree(sdma->script_addrs);
1840 return ret;
1841 }
1842
1843 static int sdma_remove(struct platform_device *pdev)
1844 {
1845 struct sdma_engine *sdma = platform_get_drvdata(pdev);
1846 int i;
1847
1848 devm_free_irq(&pdev->dev, sdma->irq, sdma);
1849 dma_async_device_unregister(&sdma->dma_device);
1850 kfree(sdma->script_addrs);
1851 /* Kill the tasklet */
1852 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1853 struct sdma_channel *sdmac = &sdma->channel[i];
1854
1855 tasklet_kill(&sdmac->tasklet);
1856 }
1857
1858 platform_set_drvdata(pdev, NULL);
1859 return 0;
1860 }
1861
1862 static struct platform_driver sdma_driver = {
1863 .driver = {
1864 .name = "imx-sdma",
1865 .of_match_table = sdma_dt_ids,
1866 },
1867 .id_table = sdma_devtypes,
1868 .remove = sdma_remove,
1869 .probe = sdma_probe,
1870 };
1871
1872 module_platform_driver(sdma_driver);
1873
1874 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1875 MODULE_DESCRIPTION("i.MX SDMA driver");
1876 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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