2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
31 #include <linux/seq_file.h>
32 #include <linux/atomic.h>
33 #include <linux/wait.h>
34 #include <linux/kref.h>
35 #include <linux/slab.h>
36 #include <linux/firmware.h>
39 #include "amdgpu_trace.h"
43 * Fences mark an event in the GPUs pipeline and are used
44 * for GPU/CPU synchronization. When the fence is written,
45 * it is expected that all buffers associated with that fence
46 * are no longer in use by the associated ring on the GPU and
47 * that the the relevant GPU caches have been flushed.
54 struct amdgpu_ring
*ring
;
57 static struct kmem_cache
*amdgpu_fence_slab
;
58 static atomic_t amdgpu_fence_slab_ref
= ATOMIC_INIT(0);
63 static const struct fence_ops amdgpu_fence_ops
;
64 static inline struct amdgpu_fence
*to_amdgpu_fence(struct fence
*f
)
66 struct amdgpu_fence
*__f
= container_of(f
, struct amdgpu_fence
, base
);
68 if (__f
->base
.ops
== &amdgpu_fence_ops
)
75 * amdgpu_fence_write - write a fence value
77 * @ring: ring the fence is associated with
78 * @seq: sequence number to write
80 * Writes a fence value to memory (all asics).
82 static void amdgpu_fence_write(struct amdgpu_ring
*ring
, u32 seq
)
84 struct amdgpu_fence_driver
*drv
= &ring
->fence_drv
;
87 *drv
->cpu_addr
= cpu_to_le32(seq
);
91 * amdgpu_fence_read - read a fence value
93 * @ring: ring the fence is associated with
95 * Reads a fence value from memory (all asics).
96 * Returns the value of the fence read from memory.
98 static u32
amdgpu_fence_read(struct amdgpu_ring
*ring
)
100 struct amdgpu_fence_driver
*drv
= &ring
->fence_drv
;
104 seq
= le32_to_cpu(*drv
->cpu_addr
);
106 seq
= atomic_read(&drv
->last_seq
);
112 * amdgpu_fence_emit - emit a fence on the requested ring
114 * @ring: ring the fence is associated with
115 * @f: resulting fence object
117 * Emits a fence command on the requested ring (all asics).
118 * Returns 0 on success, -ENOMEM on failure.
120 int amdgpu_fence_emit(struct amdgpu_ring
*ring
, struct fence
**f
)
122 struct amdgpu_device
*adev
= ring
->adev
;
123 struct amdgpu_fence
*fence
;
127 fence
= kmem_cache_alloc(amdgpu_fence_slab
, GFP_KERNEL
);
131 seq
= ++ring
->fence_drv
.sync_seq
;
133 fence_init(&fence
->base
, &amdgpu_fence_ops
,
134 &ring
->fence_drv
.lock
,
135 adev
->fence_context
+ ring
->idx
,
137 amdgpu_ring_emit_fence(ring
, ring
->fence_drv
.gpu_addr
,
138 seq
, AMDGPU_FENCE_FLAG_INT
);
140 ptr
= &ring
->fence_drv
.fences
[seq
& ring
->fence_drv
.num_fences_mask
];
141 /* This function can't be called concurrently anyway, otherwise
142 * emitting the fence would mess up the hardware ring buffer.
144 BUG_ON(rcu_dereference_protected(*ptr
, 1));
146 rcu_assign_pointer(*ptr
, fence_get(&fence
->base
));
154 * amdgpu_fence_schedule_fallback - schedule fallback check
156 * @ring: pointer to struct amdgpu_ring
158 * Start a timer as fallback to our interrupts.
160 static void amdgpu_fence_schedule_fallback(struct amdgpu_ring
*ring
)
162 mod_timer(&ring
->fence_drv
.fallback_timer
,
163 jiffies
+ AMDGPU_FENCE_JIFFIES_TIMEOUT
);
167 * amdgpu_fence_process - check for fence activity
169 * @ring: pointer to struct amdgpu_ring
171 * Checks the current fence value and calculates the last
172 * signalled fence value. Wakes the fence queue if the
173 * sequence number has increased.
175 void amdgpu_fence_process(struct amdgpu_ring
*ring
)
177 struct amdgpu_fence_driver
*drv
= &ring
->fence_drv
;
178 uint32_t seq
, last_seq
;
182 last_seq
= atomic_read(&ring
->fence_drv
.last_seq
);
183 seq
= amdgpu_fence_read(ring
);
185 } while (atomic_cmpxchg(&drv
->last_seq
, last_seq
, seq
) != last_seq
);
187 if (seq
!= ring
->fence_drv
.sync_seq
)
188 amdgpu_fence_schedule_fallback(ring
);
190 while (last_seq
!= seq
) {
191 struct fence
*fence
, **ptr
;
193 ptr
= &drv
->fences
[++last_seq
& drv
->num_fences_mask
];
195 /* There is always exactly one thread signaling this fence slot */
196 fence
= rcu_dereference_protected(*ptr
, 1);
197 rcu_assign_pointer(*ptr
, NULL
);
201 r
= fence_signal(fence
);
203 FENCE_TRACE(fence
, "signaled from irq context\n");
212 * amdgpu_fence_fallback - fallback for hardware interrupts
214 * @work: delayed work item
216 * Checks for fence activity.
218 static void amdgpu_fence_fallback(unsigned long arg
)
220 struct amdgpu_ring
*ring
= (void *)arg
;
222 amdgpu_fence_process(ring
);
226 * amdgpu_fence_wait_empty - wait for all fences to signal
228 * @adev: amdgpu device pointer
229 * @ring: ring index the fence is associated with
231 * Wait for all fences on the requested ring to signal (all asics).
232 * Returns 0 if the fences have passed, error for all other cases.
234 int amdgpu_fence_wait_empty(struct amdgpu_ring
*ring
)
236 uint64_t seq
= ACCESS_ONCE(ring
->fence_drv
.sync_seq
);
237 struct fence
*fence
, **ptr
;
243 ptr
= &ring
->fence_drv
.fences
[seq
& ring
->fence_drv
.num_fences_mask
];
245 fence
= rcu_dereference(*ptr
);
246 if (!fence
|| !fence_get_rcu(fence
)) {
252 r
= fence_wait(fence
, false);
258 * amdgpu_fence_count_emitted - get the count of emitted fences
260 * @ring: ring the fence is associated with
262 * Get the number of fences emitted on the requested ring (all asics).
263 * Returns the number of emitted fences on the ring. Used by the
264 * dynpm code to ring track activity.
266 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring
*ring
)
270 /* We are not protected by ring lock when reading the last sequence
271 * but it's ok to report slightly wrong fence count here.
273 amdgpu_fence_process(ring
);
274 emitted
= 0x100000000ull
;
275 emitted
-= atomic_read(&ring
->fence_drv
.last_seq
);
276 emitted
+= ACCESS_ONCE(ring
->fence_drv
.sync_seq
);
277 return lower_32_bits(emitted
);
281 * amdgpu_fence_driver_start_ring - make the fence driver
282 * ready for use on the requested ring.
284 * @ring: ring to start the fence driver on
285 * @irq_src: interrupt source to use for this ring
286 * @irq_type: interrupt type to use for this ring
288 * Make the fence driver ready for processing (all asics).
289 * Not all asics have all rings, so each asic will only
290 * start the fence driver on the rings it has.
291 * Returns 0 for success, errors for failure.
293 int amdgpu_fence_driver_start_ring(struct amdgpu_ring
*ring
,
294 struct amdgpu_irq_src
*irq_src
,
297 struct amdgpu_device
*adev
= ring
->adev
;
300 if (ring
!= &adev
->uvd
.ring
) {
301 ring
->fence_drv
.cpu_addr
= &adev
->wb
.wb
[ring
->fence_offs
];
302 ring
->fence_drv
.gpu_addr
= adev
->wb
.gpu_addr
+ (ring
->fence_offs
* 4);
304 /* put fence directly behind firmware */
305 index
= ALIGN(adev
->uvd
.fw
->size
, 8);
306 ring
->fence_drv
.cpu_addr
= adev
->uvd
.cpu_addr
+ index
;
307 ring
->fence_drv
.gpu_addr
= adev
->uvd
.gpu_addr
+ index
;
309 amdgpu_fence_write(ring
, atomic_read(&ring
->fence_drv
.last_seq
));
310 amdgpu_irq_get(adev
, irq_src
, irq_type
);
312 ring
->fence_drv
.irq_src
= irq_src
;
313 ring
->fence_drv
.irq_type
= irq_type
;
314 ring
->fence_drv
.initialized
= true;
316 dev_info(adev
->dev
, "fence driver on ring %d use gpu addr 0x%016llx, "
317 "cpu addr 0x%p\n", ring
->idx
,
318 ring
->fence_drv
.gpu_addr
, ring
->fence_drv
.cpu_addr
);
323 * amdgpu_fence_driver_init_ring - init the fence driver
324 * for the requested ring.
326 * @ring: ring to init the fence driver on
327 * @num_hw_submission: number of entries on the hardware queue
329 * Init the fence driver for the requested ring (all asics).
330 * Helper function for amdgpu_fence_driver_init().
332 int amdgpu_fence_driver_init_ring(struct amdgpu_ring
*ring
,
333 unsigned num_hw_submission
)
338 /* Check that num_hw_submission is a power of two */
339 if ((num_hw_submission
& (num_hw_submission
- 1)) != 0)
342 ring
->fence_drv
.cpu_addr
= NULL
;
343 ring
->fence_drv
.gpu_addr
= 0;
344 ring
->fence_drv
.sync_seq
= 0;
345 atomic_set(&ring
->fence_drv
.last_seq
, 0);
346 ring
->fence_drv
.initialized
= false;
348 setup_timer(&ring
->fence_drv
.fallback_timer
, amdgpu_fence_fallback
,
349 (unsigned long)ring
);
351 ring
->fence_drv
.num_fences_mask
= num_hw_submission
- 1;
352 spin_lock_init(&ring
->fence_drv
.lock
);
353 ring
->fence_drv
.fences
= kcalloc(num_hw_submission
, sizeof(void *),
355 if (!ring
->fence_drv
.fences
)
358 timeout
= msecs_to_jiffies(amdgpu_lockup_timeout
);
362 * Delayed workqueue cannot use it directly,
363 * so the scheduler will not use delayed workqueue if
364 * MAX_SCHEDULE_TIMEOUT is set.
365 * Currently keep it simple and silly.
367 timeout
= MAX_SCHEDULE_TIMEOUT
;
369 r
= amd_sched_init(&ring
->sched
, &amdgpu_sched_ops
,
371 timeout
, ring
->name
);
373 DRM_ERROR("Failed to create scheduler on ring %s.\n",
382 * amdgpu_fence_driver_init - init the fence driver
383 * for all possible rings.
385 * @adev: amdgpu device pointer
387 * Init the fence driver for all possible rings (all asics).
388 * Not all asics have all rings, so each asic will only
389 * start the fence driver on the rings it has using
390 * amdgpu_fence_driver_start_ring().
391 * Returns 0 for success.
393 int amdgpu_fence_driver_init(struct amdgpu_device
*adev
)
395 if (atomic_inc_return(&amdgpu_fence_slab_ref
) == 1) {
396 amdgpu_fence_slab
= kmem_cache_create(
397 "amdgpu_fence", sizeof(struct amdgpu_fence
), 0,
398 SLAB_HWCACHE_ALIGN
, NULL
);
399 if (!amdgpu_fence_slab
)
402 if (amdgpu_debugfs_fence_init(adev
))
403 dev_err(adev
->dev
, "fence debugfs file creation failed\n");
409 * amdgpu_fence_driver_fini - tear down the fence driver
410 * for all possible rings.
412 * @adev: amdgpu device pointer
414 * Tear down the fence driver for all possible rings (all asics).
416 void amdgpu_fence_driver_fini(struct amdgpu_device
*adev
)
421 for (i
= 0; i
< AMDGPU_MAX_RINGS
; i
++) {
422 struct amdgpu_ring
*ring
= adev
->rings
[i
];
424 if (!ring
|| !ring
->fence_drv
.initialized
)
426 r
= amdgpu_fence_wait_empty(ring
);
428 /* no need to trigger GPU reset as we are unloading */
429 amdgpu_fence_driver_force_completion(adev
);
431 amdgpu_irq_put(adev
, ring
->fence_drv
.irq_src
,
432 ring
->fence_drv
.irq_type
);
433 amd_sched_fini(&ring
->sched
);
434 del_timer_sync(&ring
->fence_drv
.fallback_timer
);
435 for (j
= 0; j
<= ring
->fence_drv
.num_fences_mask
; ++j
)
436 fence_put(ring
->fence_drv
.fences
[i
]);
437 kfree(ring
->fence_drv
.fences
);
438 ring
->fence_drv
.initialized
= false;
441 if (atomic_dec_and_test(&amdgpu_fence_slab_ref
))
442 kmem_cache_destroy(amdgpu_fence_slab
);
446 * amdgpu_fence_driver_suspend - suspend the fence driver
447 * for all possible rings.
449 * @adev: amdgpu device pointer
451 * Suspend the fence driver for all possible rings (all asics).
453 void amdgpu_fence_driver_suspend(struct amdgpu_device
*adev
)
457 for (i
= 0; i
< AMDGPU_MAX_RINGS
; i
++) {
458 struct amdgpu_ring
*ring
= adev
->rings
[i
];
459 if (!ring
|| !ring
->fence_drv
.initialized
)
462 /* wait for gpu to finish processing current batch */
463 r
= amdgpu_fence_wait_empty(ring
);
465 /* delay GPU reset to resume */
466 amdgpu_fence_driver_force_completion(adev
);
469 /* disable the interrupt */
470 amdgpu_irq_put(adev
, ring
->fence_drv
.irq_src
,
471 ring
->fence_drv
.irq_type
);
476 * amdgpu_fence_driver_resume - resume the fence driver
477 * for all possible rings.
479 * @adev: amdgpu device pointer
481 * Resume the fence driver for all possible rings (all asics).
482 * Not all asics have all rings, so each asic will only
483 * start the fence driver on the rings it has using
484 * amdgpu_fence_driver_start_ring().
485 * Returns 0 for success.
487 void amdgpu_fence_driver_resume(struct amdgpu_device
*adev
)
491 for (i
= 0; i
< AMDGPU_MAX_RINGS
; i
++) {
492 struct amdgpu_ring
*ring
= adev
->rings
[i
];
493 if (!ring
|| !ring
->fence_drv
.initialized
)
496 /* enable the interrupt */
497 amdgpu_irq_get(adev
, ring
->fence_drv
.irq_src
,
498 ring
->fence_drv
.irq_type
);
503 * amdgpu_fence_driver_force_completion - force all fence waiter to complete
505 * @adev: amdgpu device pointer
507 * In case of GPU reset failure make sure no process keep waiting on fence
508 * that will never complete.
510 void amdgpu_fence_driver_force_completion(struct amdgpu_device
*adev
)
514 for (i
= 0; i
< AMDGPU_MAX_RINGS
; i
++) {
515 struct amdgpu_ring
*ring
= adev
->rings
[i
];
516 if (!ring
|| !ring
->fence_drv
.initialized
)
519 amdgpu_fence_write(ring
, ring
->fence_drv
.sync_seq
);
524 * Common fence implementation
527 static const char *amdgpu_fence_get_driver_name(struct fence
*fence
)
532 static const char *amdgpu_fence_get_timeline_name(struct fence
*f
)
534 struct amdgpu_fence
*fence
= to_amdgpu_fence(f
);
535 return (const char *)fence
->ring
->name
;
539 * amdgpu_fence_enable_signaling - enable signalling on fence
542 * This function is called with fence_queue lock held, and adds a callback
543 * to fence_queue that checks if this fence is signaled, and if so it
544 * signals the fence and removes itself.
546 static bool amdgpu_fence_enable_signaling(struct fence
*f
)
548 struct amdgpu_fence
*fence
= to_amdgpu_fence(f
);
549 struct amdgpu_ring
*ring
= fence
->ring
;
551 if (!timer_pending(&ring
->fence_drv
.fallback_timer
))
552 amdgpu_fence_schedule_fallback(ring
);
554 FENCE_TRACE(&fence
->base
, "armed on ring %i!\n", ring
->idx
);
560 * amdgpu_fence_free - free up the fence memory
562 * @rcu: RCU callback head
564 * Free up the fence memory after the RCU grace period.
566 static void amdgpu_fence_free(struct rcu_head
*rcu
)
568 struct fence
*f
= container_of(rcu
, struct fence
, rcu
);
569 struct amdgpu_fence
*fence
= to_amdgpu_fence(f
);
570 kmem_cache_free(amdgpu_fence_slab
, fence
);
574 * amdgpu_fence_release - callback that fence can be freed
578 * This function is called when the reference count becomes zero.
579 * It just RCU schedules freeing up the fence.
581 static void amdgpu_fence_release(struct fence
*f
)
583 call_rcu(&f
->rcu
, amdgpu_fence_free
);
586 static const struct fence_ops amdgpu_fence_ops
= {
587 .get_driver_name
= amdgpu_fence_get_driver_name
,
588 .get_timeline_name
= amdgpu_fence_get_timeline_name
,
589 .enable_signaling
= amdgpu_fence_enable_signaling
,
590 .wait
= fence_default_wait
,
591 .release
= amdgpu_fence_release
,
597 #if defined(CONFIG_DEBUG_FS)
598 static int amdgpu_debugfs_fence_info(struct seq_file
*m
, void *data
)
600 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
601 struct drm_device
*dev
= node
->minor
->dev
;
602 struct amdgpu_device
*adev
= dev
->dev_private
;
605 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
) {
606 struct amdgpu_ring
*ring
= adev
->rings
[i
];
607 if (!ring
|| !ring
->fence_drv
.initialized
)
610 amdgpu_fence_process(ring
);
612 seq_printf(m
, "--- ring %d (%s) ---\n", i
, ring
->name
);
613 seq_printf(m
, "Last signaled fence 0x%08x\n",
614 atomic_read(&ring
->fence_drv
.last_seq
));
615 seq_printf(m
, "Last emitted 0x%08x\n",
616 ring
->fence_drv
.sync_seq
);
622 * amdgpu_debugfs_gpu_reset - manually trigger a gpu reset
624 * Manually trigger a gpu reset at the next fence wait.
626 static int amdgpu_debugfs_gpu_reset(struct seq_file
*m
, void *data
)
628 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
629 struct drm_device
*dev
= node
->minor
->dev
;
630 struct amdgpu_device
*adev
= dev
->dev_private
;
632 seq_printf(m
, "gpu reset\n");
633 amdgpu_gpu_reset(adev
);
638 static struct drm_info_list amdgpu_debugfs_fence_list
[] = {
639 {"amdgpu_fence_info", &amdgpu_debugfs_fence_info
, 0, NULL
},
640 {"amdgpu_gpu_reset", &amdgpu_debugfs_gpu_reset
, 0, NULL
}
644 int amdgpu_debugfs_fence_init(struct amdgpu_device
*adev
)
646 #if defined(CONFIG_DEBUG_FS)
647 return amdgpu_debugfs_add_files(adev
, amdgpu_debugfs_fence_list
, 2);