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i2c: designware: Prevent runtime suspend during adapter registration
[deliverable/linux.git] / drivers / i2c / busses / i2c-designware-core.c
1 /*
2 * Synopsys DesignWare I2C adapter driver (master only).
3 *
4 * Based on the TI DAVINCI I2C adapter driver.
5 *
6 * Copyright (C) 2006 Texas Instruments.
7 * Copyright (C) 2007 MontaVista Software Inc.
8 * Copyright (C) 2009 Provigent Ltd.
9 *
10 * ----------------------------------------------------------------------------
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 * ----------------------------------------------------------------------------
22 *
23 */
24 #include <linux/export.h>
25 #include <linux/errno.h>
26 #include <linux/err.h>
27 #include <linux/i2c.h>
28 #include <linux/interrupt.h>
29 #include <linux/io.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/delay.h>
32 #include <linux/module.h>
33 #include "i2c-designware-core.h"
34
35 /*
36 * Registers offset
37 */
38 #define DW_IC_CON 0x0
39 #define DW_IC_TAR 0x4
40 #define DW_IC_DATA_CMD 0x10
41 #define DW_IC_SS_SCL_HCNT 0x14
42 #define DW_IC_SS_SCL_LCNT 0x18
43 #define DW_IC_FS_SCL_HCNT 0x1c
44 #define DW_IC_FS_SCL_LCNT 0x20
45 #define DW_IC_INTR_STAT 0x2c
46 #define DW_IC_INTR_MASK 0x30
47 #define DW_IC_RAW_INTR_STAT 0x34
48 #define DW_IC_RX_TL 0x38
49 #define DW_IC_TX_TL 0x3c
50 #define DW_IC_CLR_INTR 0x40
51 #define DW_IC_CLR_RX_UNDER 0x44
52 #define DW_IC_CLR_RX_OVER 0x48
53 #define DW_IC_CLR_TX_OVER 0x4c
54 #define DW_IC_CLR_RD_REQ 0x50
55 #define DW_IC_CLR_TX_ABRT 0x54
56 #define DW_IC_CLR_RX_DONE 0x58
57 #define DW_IC_CLR_ACTIVITY 0x5c
58 #define DW_IC_CLR_STOP_DET 0x60
59 #define DW_IC_CLR_START_DET 0x64
60 #define DW_IC_CLR_GEN_CALL 0x68
61 #define DW_IC_ENABLE 0x6c
62 #define DW_IC_STATUS 0x70
63 #define DW_IC_TXFLR 0x74
64 #define DW_IC_RXFLR 0x78
65 #define DW_IC_SDA_HOLD 0x7c
66 #define DW_IC_TX_ABRT_SOURCE 0x80
67 #define DW_IC_ENABLE_STATUS 0x9c
68 #define DW_IC_COMP_PARAM_1 0xf4
69 #define DW_IC_COMP_VERSION 0xf8
70 #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A
71 #define DW_IC_COMP_TYPE 0xfc
72 #define DW_IC_COMP_TYPE_VALUE 0x44570140
73
74 #define DW_IC_INTR_RX_UNDER 0x001
75 #define DW_IC_INTR_RX_OVER 0x002
76 #define DW_IC_INTR_RX_FULL 0x004
77 #define DW_IC_INTR_TX_OVER 0x008
78 #define DW_IC_INTR_TX_EMPTY 0x010
79 #define DW_IC_INTR_RD_REQ 0x020
80 #define DW_IC_INTR_TX_ABRT 0x040
81 #define DW_IC_INTR_RX_DONE 0x080
82 #define DW_IC_INTR_ACTIVITY 0x100
83 #define DW_IC_INTR_STOP_DET 0x200
84 #define DW_IC_INTR_START_DET 0x400
85 #define DW_IC_INTR_GEN_CALL 0x800
86
87 #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
88 DW_IC_INTR_TX_EMPTY | \
89 DW_IC_INTR_TX_ABRT | \
90 DW_IC_INTR_STOP_DET)
91
92 #define DW_IC_STATUS_ACTIVITY 0x1
93
94 #define DW_IC_ERR_TX_ABRT 0x1
95
96 #define DW_IC_TAR_10BITADDR_MASTER BIT(12)
97
98 /*
99 * status codes
100 */
101 #define STATUS_IDLE 0x0
102 #define STATUS_WRITE_IN_PROGRESS 0x1
103 #define STATUS_READ_IN_PROGRESS 0x2
104
105 #define TIMEOUT 20 /* ms */
106
107 /*
108 * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
109 *
110 * only expected abort codes are listed here
111 * refer to the datasheet for the full list
112 */
113 #define ABRT_7B_ADDR_NOACK 0
114 #define ABRT_10ADDR1_NOACK 1
115 #define ABRT_10ADDR2_NOACK 2
116 #define ABRT_TXDATA_NOACK 3
117 #define ABRT_GCALL_NOACK 4
118 #define ABRT_GCALL_READ 5
119 #define ABRT_SBYTE_ACKDET 7
120 #define ABRT_SBYTE_NORSTRT 9
121 #define ABRT_10B_RD_NORSTRT 10
122 #define ABRT_MASTER_DIS 11
123 #define ARB_LOST 12
124
125 #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK)
126 #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK)
127 #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK)
128 #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK)
129 #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK)
130 #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ)
131 #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET)
132 #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT)
133 #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT)
134 #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS)
135 #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST)
136
137 #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
138 DW_IC_TX_ABRT_10ADDR1_NOACK | \
139 DW_IC_TX_ABRT_10ADDR2_NOACK | \
140 DW_IC_TX_ABRT_TXDATA_NOACK | \
141 DW_IC_TX_ABRT_GCALL_NOACK)
142
143 static char *abort_sources[] = {
144 [ABRT_7B_ADDR_NOACK] =
145 "slave address not acknowledged (7bit mode)",
146 [ABRT_10ADDR1_NOACK] =
147 "first address byte not acknowledged (10bit mode)",
148 [ABRT_10ADDR2_NOACK] =
149 "second address byte not acknowledged (10bit mode)",
150 [ABRT_TXDATA_NOACK] =
151 "data not acknowledged",
152 [ABRT_GCALL_NOACK] =
153 "no acknowledgement for a general call",
154 [ABRT_GCALL_READ] =
155 "read after general call",
156 [ABRT_SBYTE_ACKDET] =
157 "start byte acknowledged",
158 [ABRT_SBYTE_NORSTRT] =
159 "trying to send start byte when restart is disabled",
160 [ABRT_10B_RD_NORSTRT] =
161 "trying to read when restart is disabled (10bit mode)",
162 [ABRT_MASTER_DIS] =
163 "trying to use disabled adapter",
164 [ARB_LOST] =
165 "lost arbitration",
166 };
167
168 static u32 dw_readl(struct dw_i2c_dev *dev, int offset)
169 {
170 u32 value;
171
172 if (dev->accessor_flags & ACCESS_16BIT)
173 value = readw_relaxed(dev->base + offset) |
174 (readw_relaxed(dev->base + offset + 2) << 16);
175 else
176 value = readl_relaxed(dev->base + offset);
177
178 if (dev->accessor_flags & ACCESS_SWAP)
179 return swab32(value);
180 else
181 return value;
182 }
183
184 static void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
185 {
186 if (dev->accessor_flags & ACCESS_SWAP)
187 b = swab32(b);
188
189 if (dev->accessor_flags & ACCESS_16BIT) {
190 writew_relaxed((u16)b, dev->base + offset);
191 writew_relaxed((u16)(b >> 16), dev->base + offset + 2);
192 } else {
193 writel_relaxed(b, dev->base + offset);
194 }
195 }
196
197 static u32
198 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
199 {
200 /*
201 * DesignWare I2C core doesn't seem to have solid strategy to meet
202 * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
203 * will result in violation of the tHD;STA spec.
204 */
205 if (cond)
206 /*
207 * Conditional expression:
208 *
209 * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
210 *
211 * This is based on the DW manuals, and represents an ideal
212 * configuration. The resulting I2C bus speed will be
213 * faster than any of the others.
214 *
215 * If your hardware is free from tHD;STA issue, try this one.
216 */
217 return (ic_clk * tSYMBOL + 500000) / 1000000 - 8 + offset;
218 else
219 /*
220 * Conditional expression:
221 *
222 * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
223 *
224 * This is just experimental rule; the tHD;STA period turned
225 * out to be proportinal to (_HCNT + 3). With this setting,
226 * we could meet both tHIGH and tHD;STA timing specs.
227 *
228 * If unsure, you'd better to take this alternative.
229 *
230 * The reason why we need to take into account "tf" here,
231 * is the same as described in i2c_dw_scl_lcnt().
232 */
233 return (ic_clk * (tSYMBOL + tf) + 500000) / 1000000
234 - 3 + offset;
235 }
236
237 static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
238 {
239 /*
240 * Conditional expression:
241 *
242 * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
243 *
244 * DW I2C core starts counting the SCL CNTs for the LOW period
245 * of the SCL clock (tLOW) as soon as it pulls the SCL line.
246 * In order to meet the tLOW timing spec, we need to take into
247 * account the fall time of SCL signal (tf). Default tf value
248 * should be 0.3 us, for safety.
249 */
250 return ((ic_clk * (tLOW + tf) + 500000) / 1000000) - 1 + offset;
251 }
252
253 static void __i2c_dw_enable(struct dw_i2c_dev *dev, bool enable)
254 {
255 int timeout = 100;
256
257 do {
258 dw_writel(dev, enable, DW_IC_ENABLE);
259 if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == enable)
260 return;
261
262 /*
263 * Wait 10 times the signaling period of the highest I2C
264 * transfer supported by the driver (for 400KHz this is
265 * 25us) as described in the DesignWare I2C databook.
266 */
267 usleep_range(25, 250);
268 } while (timeout--);
269
270 dev_warn(dev->dev, "timeout in %sabling adapter\n",
271 enable ? "en" : "dis");
272 }
273
274 static unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev)
275 {
276 /*
277 * Clock is not necessary if we got LCNT/HCNT values directly from
278 * the platform code.
279 */
280 if (WARN_ON_ONCE(!dev->get_clk_rate_khz))
281 return 0;
282 return dev->get_clk_rate_khz(dev);
283 }
284
285 /**
286 * i2c_dw_init() - initialize the designware i2c master hardware
287 * @dev: device private data
288 *
289 * This functions configures and enables the I2C master.
290 * This function is called during I2C init function, and in case of timeout at
291 * run time.
292 */
293 int i2c_dw_init(struct dw_i2c_dev *dev)
294 {
295 u32 hcnt, lcnt;
296 u32 reg;
297 u32 sda_falling_time, scl_falling_time;
298 int ret;
299
300 if (dev->acquire_lock) {
301 ret = dev->acquire_lock(dev);
302 if (ret) {
303 dev_err(dev->dev, "couldn't acquire bus ownership\n");
304 return ret;
305 }
306 }
307
308 reg = dw_readl(dev, DW_IC_COMP_TYPE);
309 if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
310 /* Configure register endianess access */
311 dev->accessor_flags |= ACCESS_SWAP;
312 } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
313 /* Configure register access mode 16bit */
314 dev->accessor_flags |= ACCESS_16BIT;
315 } else if (reg != DW_IC_COMP_TYPE_VALUE) {
316 dev_err(dev->dev, "Unknown Synopsys component type: "
317 "0x%08x\n", reg);
318 if (dev->release_lock)
319 dev->release_lock(dev);
320 return -ENODEV;
321 }
322
323 /* Disable the adapter */
324 __i2c_dw_enable(dev, false);
325
326 /* set standard and fast speed deviders for high/low periods */
327
328 sda_falling_time = dev->sda_falling_time ?: 300; /* ns */
329 scl_falling_time = dev->scl_falling_time ?: 300; /* ns */
330
331 /* Set SCL timing parameters for standard-mode */
332 if (dev->ss_hcnt && dev->ss_lcnt) {
333 hcnt = dev->ss_hcnt;
334 lcnt = dev->ss_lcnt;
335 } else {
336 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
337 4000, /* tHD;STA = tHIGH = 4.0 us */
338 sda_falling_time,
339 0, /* 0: DW default, 1: Ideal */
340 0); /* No offset */
341 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
342 4700, /* tLOW = 4.7 us */
343 scl_falling_time,
344 0); /* No offset */
345 }
346 dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
347 dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
348 dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
349
350 /* Set SCL timing parameters for fast-mode */
351 if (dev->fs_hcnt && dev->fs_lcnt) {
352 hcnt = dev->fs_hcnt;
353 lcnt = dev->fs_lcnt;
354 } else {
355 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
356 600, /* tHD;STA = tHIGH = 0.6 us */
357 sda_falling_time,
358 0, /* 0: DW default, 1: Ideal */
359 0); /* No offset */
360 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
361 1300, /* tLOW = 1.3 us */
362 scl_falling_time,
363 0); /* No offset */
364 }
365 dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
366 dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
367 dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
368
369 /* Configure SDA Hold Time if required */
370 if (dev->sda_hold_time) {
371 reg = dw_readl(dev, DW_IC_COMP_VERSION);
372 if (reg >= DW_IC_SDA_HOLD_MIN_VERS)
373 dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
374 else
375 dev_warn(dev->dev,
376 "Hardware too old to adjust SDA hold time.");
377 }
378
379 /* Configure Tx/Rx FIFO threshold levels */
380 dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL);
381 dw_writel(dev, 0, DW_IC_RX_TL);
382
383 /* configure the i2c master */
384 dw_writel(dev, dev->master_cfg , DW_IC_CON);
385
386 if (dev->release_lock)
387 dev->release_lock(dev);
388 return 0;
389 }
390 EXPORT_SYMBOL_GPL(i2c_dw_init);
391
392 /*
393 * Waiting for bus not busy
394 */
395 static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
396 {
397 int timeout = TIMEOUT;
398
399 while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
400 if (timeout <= 0) {
401 dev_warn(dev->dev, "timeout waiting for bus ready\n");
402 return -ETIMEDOUT;
403 }
404 timeout--;
405 usleep_range(1000, 1100);
406 }
407
408 return 0;
409 }
410
411 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
412 {
413 struct i2c_msg *msgs = dev->msgs;
414 u32 ic_con, ic_tar = 0;
415
416 /* Disable the adapter */
417 __i2c_dw_enable(dev, false);
418
419 /* if the slave address is ten bit address, enable 10BITADDR */
420 ic_con = dw_readl(dev, DW_IC_CON);
421 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
422 ic_con |= DW_IC_CON_10BITADDR_MASTER;
423 /*
424 * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
425 * mode has to be enabled via bit 12 of IC_TAR register.
426 * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
427 * detected from registers.
428 */
429 ic_tar = DW_IC_TAR_10BITADDR_MASTER;
430 } else {
431 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
432 }
433
434 dw_writel(dev, ic_con, DW_IC_CON);
435
436 /*
437 * Set the slave (target) address and enable 10-bit addressing mode
438 * if applicable.
439 */
440 dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
441
442 /* enforce disabled interrupts (due to HW issues) */
443 i2c_dw_disable_int(dev);
444
445 /* Enable the adapter */
446 __i2c_dw_enable(dev, true);
447
448 /* Clear and enable interrupts */
449 dw_readl(dev, DW_IC_CLR_INTR);
450 dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK);
451 }
452
453 /*
454 * Initiate (and continue) low level master read/write transaction.
455 * This function is only called from i2c_dw_isr, and pumping i2c_msg
456 * messages into the tx buffer. Even if the size of i2c_msg data is
457 * longer than the size of the tx buffer, it handles everything.
458 */
459 static void
460 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
461 {
462 struct i2c_msg *msgs = dev->msgs;
463 u32 intr_mask;
464 int tx_limit, rx_limit;
465 u32 addr = msgs[dev->msg_write_idx].addr;
466 u32 buf_len = dev->tx_buf_len;
467 u8 *buf = dev->tx_buf;
468 bool need_restart = false;
469
470 intr_mask = DW_IC_INTR_DEFAULT_MASK;
471
472 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
473 /*
474 * if target address has changed, we need to
475 * reprogram the target address in the i2c
476 * adapter when we are done with this transfer
477 */
478 if (msgs[dev->msg_write_idx].addr != addr) {
479 dev_err(dev->dev,
480 "%s: invalid target address\n", __func__);
481 dev->msg_err = -EINVAL;
482 break;
483 }
484
485 if (msgs[dev->msg_write_idx].len == 0) {
486 dev_err(dev->dev,
487 "%s: invalid message length\n", __func__);
488 dev->msg_err = -EINVAL;
489 break;
490 }
491
492 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
493 /* new i2c_msg */
494 buf = msgs[dev->msg_write_idx].buf;
495 buf_len = msgs[dev->msg_write_idx].len;
496
497 /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
498 * IC_RESTART_EN are set, we must manually
499 * set restart bit between messages.
500 */
501 if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
502 (dev->msg_write_idx > 0))
503 need_restart = true;
504 }
505
506 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
507 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
508
509 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
510 u32 cmd = 0;
511
512 /*
513 * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
514 * manually set the stop bit. However, it cannot be
515 * detected from the registers so we set it always
516 * when writing/reading the last byte.
517 */
518 if (dev->msg_write_idx == dev->msgs_num - 1 &&
519 buf_len == 1)
520 cmd |= BIT(9);
521
522 if (need_restart) {
523 cmd |= BIT(10);
524 need_restart = false;
525 }
526
527 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
528
529 /* avoid rx buffer overrun */
530 if (rx_limit - dev->rx_outstanding <= 0)
531 break;
532
533 dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
534 rx_limit--;
535 dev->rx_outstanding++;
536 } else
537 dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
538 tx_limit--; buf_len--;
539 }
540
541 dev->tx_buf = buf;
542 dev->tx_buf_len = buf_len;
543
544 if (buf_len > 0) {
545 /* more bytes to be written */
546 dev->status |= STATUS_WRITE_IN_PROGRESS;
547 break;
548 } else
549 dev->status &= ~STATUS_WRITE_IN_PROGRESS;
550 }
551
552 /*
553 * If i2c_msg index search is completed, we don't need TX_EMPTY
554 * interrupt any more.
555 */
556 if (dev->msg_write_idx == dev->msgs_num)
557 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
558
559 if (dev->msg_err)
560 intr_mask = 0;
561
562 dw_writel(dev, intr_mask, DW_IC_INTR_MASK);
563 }
564
565 static void
566 i2c_dw_read(struct dw_i2c_dev *dev)
567 {
568 struct i2c_msg *msgs = dev->msgs;
569 int rx_valid;
570
571 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
572 u32 len;
573 u8 *buf;
574
575 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
576 continue;
577
578 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
579 len = msgs[dev->msg_read_idx].len;
580 buf = msgs[dev->msg_read_idx].buf;
581 } else {
582 len = dev->rx_buf_len;
583 buf = dev->rx_buf;
584 }
585
586 rx_valid = dw_readl(dev, DW_IC_RXFLR);
587
588 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
589 *buf++ = dw_readl(dev, DW_IC_DATA_CMD);
590 dev->rx_outstanding--;
591 }
592
593 if (len > 0) {
594 dev->status |= STATUS_READ_IN_PROGRESS;
595 dev->rx_buf_len = len;
596 dev->rx_buf = buf;
597 return;
598 } else
599 dev->status &= ~STATUS_READ_IN_PROGRESS;
600 }
601 }
602
603 static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
604 {
605 unsigned long abort_source = dev->abort_source;
606 int i;
607
608 if (abort_source & DW_IC_TX_ABRT_NOACK) {
609 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
610 dev_dbg(dev->dev,
611 "%s: %s\n", __func__, abort_sources[i]);
612 return -EREMOTEIO;
613 }
614
615 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
616 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
617
618 if (abort_source & DW_IC_TX_ARB_LOST)
619 return -EAGAIN;
620 else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
621 return -EINVAL; /* wrong msgs[] data */
622 else
623 return -EIO;
624 }
625
626 /*
627 * Prepare controller for a transaction and call i2c_dw_xfer_msg
628 */
629 static int
630 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
631 {
632 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
633 int ret;
634
635 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
636
637 pm_runtime_get_sync(dev->dev);
638
639 reinit_completion(&dev->cmd_complete);
640 dev->msgs = msgs;
641 dev->msgs_num = num;
642 dev->cmd_err = 0;
643 dev->msg_write_idx = 0;
644 dev->msg_read_idx = 0;
645 dev->msg_err = 0;
646 dev->status = STATUS_IDLE;
647 dev->abort_source = 0;
648 dev->rx_outstanding = 0;
649
650 if (dev->acquire_lock) {
651 ret = dev->acquire_lock(dev);
652 if (ret) {
653 dev_err(dev->dev, "couldn't acquire bus ownership\n");
654 goto done_nolock;
655 }
656 }
657
658 ret = i2c_dw_wait_bus_not_busy(dev);
659 if (ret < 0)
660 goto done;
661
662 /* start the transfers */
663 i2c_dw_xfer_init(dev);
664
665 /* wait for tx to complete */
666 if (!wait_for_completion_timeout(&dev->cmd_complete, HZ)) {
667 dev_err(dev->dev, "controller timed out\n");
668 /* i2c_dw_init implicitly disables the adapter */
669 i2c_dw_init(dev);
670 ret = -ETIMEDOUT;
671 goto done;
672 }
673
674 /*
675 * We must disable the adapter before returning and signaling the end
676 * of the current transfer. Otherwise the hardware might continue
677 * generating interrupts which in turn causes a race condition with
678 * the following transfer. Needs some more investigation if the
679 * additional interrupts are a hardware bug or this driver doesn't
680 * handle them correctly yet.
681 */
682 __i2c_dw_enable(dev, false);
683
684 if (dev->msg_err) {
685 ret = dev->msg_err;
686 goto done;
687 }
688
689 /* no error */
690 if (likely(!dev->cmd_err)) {
691 ret = num;
692 goto done;
693 }
694
695 /* We have an error */
696 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
697 ret = i2c_dw_handle_tx_abort(dev);
698 goto done;
699 }
700 ret = -EIO;
701
702 done:
703 if (dev->release_lock)
704 dev->release_lock(dev);
705
706 done_nolock:
707 pm_runtime_mark_last_busy(dev->dev);
708 pm_runtime_put_autosuspend(dev->dev);
709
710 return ret;
711 }
712
713 static u32 i2c_dw_func(struct i2c_adapter *adap)
714 {
715 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
716 return dev->functionality;
717 }
718
719 static struct i2c_algorithm i2c_dw_algo = {
720 .master_xfer = i2c_dw_xfer,
721 .functionality = i2c_dw_func,
722 };
723
724 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
725 {
726 u32 stat;
727
728 /*
729 * The IC_INTR_STAT register just indicates "enabled" interrupts.
730 * Ths unmasked raw version of interrupt status bits are available
731 * in the IC_RAW_INTR_STAT register.
732 *
733 * That is,
734 * stat = dw_readl(IC_INTR_STAT);
735 * equals to,
736 * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
737 *
738 * The raw version might be useful for debugging purposes.
739 */
740 stat = dw_readl(dev, DW_IC_INTR_STAT);
741
742 /*
743 * Do not use the IC_CLR_INTR register to clear interrupts, or
744 * you'll miss some interrupts, triggered during the period from
745 * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
746 *
747 * Instead, use the separately-prepared IC_CLR_* registers.
748 */
749 if (stat & DW_IC_INTR_RX_UNDER)
750 dw_readl(dev, DW_IC_CLR_RX_UNDER);
751 if (stat & DW_IC_INTR_RX_OVER)
752 dw_readl(dev, DW_IC_CLR_RX_OVER);
753 if (stat & DW_IC_INTR_TX_OVER)
754 dw_readl(dev, DW_IC_CLR_TX_OVER);
755 if (stat & DW_IC_INTR_RD_REQ)
756 dw_readl(dev, DW_IC_CLR_RD_REQ);
757 if (stat & DW_IC_INTR_TX_ABRT) {
758 /*
759 * The IC_TX_ABRT_SOURCE register is cleared whenever
760 * the IC_CLR_TX_ABRT is read. Preserve it beforehand.
761 */
762 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
763 dw_readl(dev, DW_IC_CLR_TX_ABRT);
764 }
765 if (stat & DW_IC_INTR_RX_DONE)
766 dw_readl(dev, DW_IC_CLR_RX_DONE);
767 if (stat & DW_IC_INTR_ACTIVITY)
768 dw_readl(dev, DW_IC_CLR_ACTIVITY);
769 if (stat & DW_IC_INTR_STOP_DET)
770 dw_readl(dev, DW_IC_CLR_STOP_DET);
771 if (stat & DW_IC_INTR_START_DET)
772 dw_readl(dev, DW_IC_CLR_START_DET);
773 if (stat & DW_IC_INTR_GEN_CALL)
774 dw_readl(dev, DW_IC_CLR_GEN_CALL);
775
776 return stat;
777 }
778
779 /*
780 * Interrupt service routine. This gets called whenever an I2C interrupt
781 * occurs.
782 */
783 static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
784 {
785 struct dw_i2c_dev *dev = dev_id;
786 u32 stat, enabled;
787
788 enabled = dw_readl(dev, DW_IC_ENABLE);
789 stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
790 dev_dbg(dev->dev, "%s: enabled=%#x stat=%#x\n", __func__, enabled, stat);
791 if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
792 return IRQ_NONE;
793
794 stat = i2c_dw_read_clear_intrbits(dev);
795
796 if (stat & DW_IC_INTR_TX_ABRT) {
797 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
798 dev->status = STATUS_IDLE;
799
800 /*
801 * Anytime TX_ABRT is set, the contents of the tx/rx
802 * buffers are flushed. Make sure to skip them.
803 */
804 dw_writel(dev, 0, DW_IC_INTR_MASK);
805 goto tx_aborted;
806 }
807
808 if (stat & DW_IC_INTR_RX_FULL)
809 i2c_dw_read(dev);
810
811 if (stat & DW_IC_INTR_TX_EMPTY)
812 i2c_dw_xfer_msg(dev);
813
814 /*
815 * No need to modify or disable the interrupt mask here.
816 * i2c_dw_xfer_msg() will take care of it according to
817 * the current transmit status.
818 */
819
820 tx_aborted:
821 if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
822 complete(&dev->cmd_complete);
823 else if (unlikely(dev->accessor_flags & ACCESS_INTR_MASK)) {
824 /* workaround to trigger pending interrupt */
825 stat = dw_readl(dev, DW_IC_INTR_MASK);
826 i2c_dw_disable_int(dev);
827 dw_writel(dev, stat, DW_IC_INTR_MASK);
828 }
829
830 return IRQ_HANDLED;
831 }
832
833 void i2c_dw_disable(struct dw_i2c_dev *dev)
834 {
835 /* Disable controller */
836 __i2c_dw_enable(dev, false);
837
838 /* Disable all interupts */
839 dw_writel(dev, 0, DW_IC_INTR_MASK);
840 dw_readl(dev, DW_IC_CLR_INTR);
841 }
842 EXPORT_SYMBOL_GPL(i2c_dw_disable);
843
844 void i2c_dw_disable_int(struct dw_i2c_dev *dev)
845 {
846 dw_writel(dev, 0, DW_IC_INTR_MASK);
847 }
848 EXPORT_SYMBOL_GPL(i2c_dw_disable_int);
849
850 u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev)
851 {
852 return dw_readl(dev, DW_IC_COMP_PARAM_1);
853 }
854 EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param);
855
856 int i2c_dw_probe(struct dw_i2c_dev *dev)
857 {
858 struct i2c_adapter *adap = &dev->adapter;
859 int r;
860
861 init_completion(&dev->cmd_complete);
862
863 r = i2c_dw_init(dev);
864 if (r)
865 return r;
866
867 snprintf(adap->name, sizeof(adap->name),
868 "Synopsys DesignWare I2C adapter");
869 adap->retries = 3;
870 adap->algo = &i2c_dw_algo;
871 adap->dev.parent = dev->dev;
872 i2c_set_adapdata(adap, dev);
873
874 i2c_dw_disable_int(dev);
875 r = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr,
876 IRQF_SHARED | IRQF_COND_SUSPEND,
877 dev_name(dev->dev), dev);
878 if (r) {
879 dev_err(dev->dev, "failure requesting irq %i: %d\n",
880 dev->irq, r);
881 return r;
882 }
883
884 /*
885 * Increment PM usage count during adapter registration in order to
886 * avoid possible spurious runtime suspend when adapter device is
887 * registered to the device core and immediate resume in case bus has
888 * registered I2C slaves that do I2C transfers in their probe.
889 */
890 pm_runtime_get_noresume(dev->dev);
891 r = i2c_add_numbered_adapter(adap);
892 if (r)
893 dev_err(dev->dev, "failure adding adapter: %d\n", r);
894 pm_runtime_put_noidle(dev->dev);
895
896 return r;
897 }
898 EXPORT_SYMBOL_GPL(i2c_dw_probe);
899
900 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
901 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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