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iio: imu: mpu6050: add calibration offset support
[deliverable/linux.git] / drivers / iio / imu / inv_mpu6050 / inv_mpu_core.c
1 /*
2 * Copyright (C) 2012 Invensense, Inc.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/i2c.h>
17 #include <linux/err.h>
18 #include <linux/delay.h>
19 #include <linux/sysfs.h>
20 #include <linux/jiffies.h>
21 #include <linux/irq.h>
22 #include <linux/interrupt.h>
23 #include <linux/kfifo.h>
24 #include <linux/spinlock.h>
25 #include <linux/iio/iio.h>
26 #include <linux/i2c-mux.h>
27 #include <linux/acpi.h>
28 #include "inv_mpu_iio.h"
29
30 /*
31 * this is the gyro scale translated from dynamic range plus/minus
32 * {250, 500, 1000, 2000} to rad/s
33 */
34 static const int gyro_scale_6050[] = {133090, 266181, 532362, 1064724};
35
36 /*
37 * this is the accel scale translated from dynamic range plus/minus
38 * {2, 4, 8, 16} to m/s^2
39 */
40 static const int accel_scale[] = {598, 1196, 2392, 4785};
41
42 static const struct inv_mpu6050_reg_map reg_set_6050 = {
43 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
44 .lpf = INV_MPU6050_REG_CONFIG,
45 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
46 .fifo_en = INV_MPU6050_REG_FIFO_EN,
47 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
48 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
49 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
50 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
51 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
52 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
53 .temperature = INV_MPU6050_REG_TEMPERATURE,
54 .int_enable = INV_MPU6050_REG_INT_ENABLE,
55 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
56 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
57 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
58 .accl_offset = INV_MPU6050_REG_ACCEL_OFFSET,
59 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
60 };
61
62 static const struct inv_mpu6050_chip_config chip_config_6050 = {
63 .fsr = INV_MPU6050_FSR_2000DPS,
64 .lpf = INV_MPU6050_FILTER_20HZ,
65 .fifo_rate = INV_MPU6050_INIT_FIFO_RATE,
66 .gyro_fifo_enable = false,
67 .accl_fifo_enable = false,
68 .accl_fs = INV_MPU6050_FS_02G,
69 };
70
71 static const struct inv_mpu6050_hw hw_info[INV_NUM_PARTS] = {
72 {
73 .num_reg = 117,
74 .name = "MPU6050",
75 .reg = &reg_set_6050,
76 .config = &chip_config_6050,
77 },
78 };
79
80 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask)
81 {
82 unsigned int d, mgmt_1;
83 int result;
84 /*
85 * switch clock needs to be careful. Only when gyro is on, can
86 * clock source be switched to gyro. Otherwise, it must be set to
87 * internal clock
88 */
89 if (mask == INV_MPU6050_BIT_PWR_GYRO_STBY) {
90 result = regmap_read(st->map, st->reg->pwr_mgmt_1, &mgmt_1);
91 if (result)
92 return result;
93
94 mgmt_1 &= ~INV_MPU6050_BIT_CLK_MASK;
95 }
96
97 if ((mask == INV_MPU6050_BIT_PWR_GYRO_STBY) && (!en)) {
98 /*
99 * turning off gyro requires switch to internal clock first.
100 * Then turn off gyro engine
101 */
102 mgmt_1 |= INV_CLK_INTERNAL;
103 result = regmap_write(st->map, st->reg->pwr_mgmt_1, mgmt_1);
104 if (result)
105 return result;
106 }
107
108 result = regmap_read(st->map, st->reg->pwr_mgmt_2, &d);
109 if (result)
110 return result;
111 if (en)
112 d &= ~mask;
113 else
114 d |= mask;
115 result = regmap_write(st->map, st->reg->pwr_mgmt_2, d);
116 if (result)
117 return result;
118
119 if (en) {
120 /* Wait for output stabilize */
121 msleep(INV_MPU6050_TEMP_UP_TIME);
122 if (mask == INV_MPU6050_BIT_PWR_GYRO_STBY) {
123 /* switch internal clock to PLL */
124 mgmt_1 |= INV_CLK_PLL;
125 result = regmap_write(st->map,
126 st->reg->pwr_mgmt_1, mgmt_1);
127 if (result)
128 return result;
129 }
130 }
131
132 return 0;
133 }
134
135 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on)
136 {
137 int result = 0;
138
139 if (power_on) {
140 /* Already under indio-dev->mlock mutex */
141 if (!st->powerup_count)
142 result = regmap_write(st->map, st->reg->pwr_mgmt_1, 0);
143 if (!result)
144 st->powerup_count++;
145 } else {
146 st->powerup_count--;
147 if (!st->powerup_count)
148 result = regmap_write(st->map, st->reg->pwr_mgmt_1,
149 INV_MPU6050_BIT_SLEEP);
150 }
151
152 if (result)
153 return result;
154
155 if (power_on)
156 usleep_range(INV_MPU6050_REG_UP_TIME_MIN,
157 INV_MPU6050_REG_UP_TIME_MAX);
158
159 return 0;
160 }
161 EXPORT_SYMBOL_GPL(inv_mpu6050_set_power_itg);
162
163 /**
164 * inv_mpu6050_init_config() - Initialize hardware, disable FIFO.
165 *
166 * Initial configuration:
167 * FSR: ± 2000DPS
168 * DLPF: 20Hz
169 * FIFO rate: 50Hz
170 * Clock source: Gyro PLL
171 */
172 static int inv_mpu6050_init_config(struct iio_dev *indio_dev)
173 {
174 int result;
175 u8 d;
176 struct inv_mpu6050_state *st = iio_priv(indio_dev);
177
178 result = inv_mpu6050_set_power_itg(st, true);
179 if (result)
180 return result;
181 d = (INV_MPU6050_FSR_2000DPS << INV_MPU6050_GYRO_CONFIG_FSR_SHIFT);
182 result = regmap_write(st->map, st->reg->gyro_config, d);
183 if (result)
184 return result;
185
186 d = INV_MPU6050_FILTER_20HZ;
187 result = regmap_write(st->map, st->reg->lpf, d);
188 if (result)
189 return result;
190
191 d = INV_MPU6050_ONE_K_HZ / INV_MPU6050_INIT_FIFO_RATE - 1;
192 result = regmap_write(st->map, st->reg->sample_rate_div, d);
193 if (result)
194 return result;
195
196 d = (INV_MPU6050_FS_02G << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT);
197 result = regmap_write(st->map, st->reg->accl_config, d);
198 if (result)
199 return result;
200
201 memcpy(&st->chip_config, hw_info[st->chip_type].config,
202 sizeof(struct inv_mpu6050_chip_config));
203 result = inv_mpu6050_set_power_itg(st, false);
204
205 return result;
206 }
207
208 static int inv_mpu6050_sensor_set(struct inv_mpu6050_state *st, int reg,
209 int axis, int val)
210 {
211 int ind, result;
212 __be16 d = cpu_to_be16(val);
213
214 ind = (axis - IIO_MOD_X) * 2;
215 result = regmap_bulk_write(st->map, reg + ind, (u8 *)&d, 2);
216 if (result)
217 return -EINVAL;
218
219 return 0;
220 }
221
222 static int inv_mpu6050_sensor_show(struct inv_mpu6050_state *st, int reg,
223 int axis, int *val)
224 {
225 int ind, result;
226 __be16 d;
227
228 ind = (axis - IIO_MOD_X) * 2;
229 result = regmap_bulk_read(st->map, reg + ind, (u8 *)&d, 2);
230 if (result)
231 return -EINVAL;
232 *val = (short)be16_to_cpup(&d);
233
234 return IIO_VAL_INT;
235 }
236
237 static int
238 inv_mpu6050_read_raw(struct iio_dev *indio_dev,
239 struct iio_chan_spec const *chan,
240 int *val, int *val2, long mask)
241 {
242 struct inv_mpu6050_state *st = iio_priv(indio_dev);
243 int ret = 0;
244
245 switch (mask) {
246 case IIO_CHAN_INFO_RAW:
247 {
248 int result;
249
250 ret = IIO_VAL_INT;
251 result = 0;
252 mutex_lock(&indio_dev->mlock);
253 if (!st->chip_config.enable) {
254 result = inv_mpu6050_set_power_itg(st, true);
255 if (result)
256 goto error_read_raw;
257 }
258 /* when enable is on, power is already on */
259 switch (chan->type) {
260 case IIO_ANGL_VEL:
261 if (!st->chip_config.gyro_fifo_enable ||
262 !st->chip_config.enable) {
263 result = inv_mpu6050_switch_engine(st, true,
264 INV_MPU6050_BIT_PWR_GYRO_STBY);
265 if (result)
266 goto error_read_raw;
267 }
268 ret = inv_mpu6050_sensor_show(st, st->reg->raw_gyro,
269 chan->channel2, val);
270 if (!st->chip_config.gyro_fifo_enable ||
271 !st->chip_config.enable) {
272 result = inv_mpu6050_switch_engine(st, false,
273 INV_MPU6050_BIT_PWR_GYRO_STBY);
274 if (result)
275 goto error_read_raw;
276 }
277 break;
278 case IIO_ACCEL:
279 if (!st->chip_config.accl_fifo_enable ||
280 !st->chip_config.enable) {
281 result = inv_mpu6050_switch_engine(st, true,
282 INV_MPU6050_BIT_PWR_ACCL_STBY);
283 if (result)
284 goto error_read_raw;
285 }
286 ret = inv_mpu6050_sensor_show(st, st->reg->raw_accl,
287 chan->channel2, val);
288 if (!st->chip_config.accl_fifo_enable ||
289 !st->chip_config.enable) {
290 result = inv_mpu6050_switch_engine(st, false,
291 INV_MPU6050_BIT_PWR_ACCL_STBY);
292 if (result)
293 goto error_read_raw;
294 }
295 break;
296 case IIO_TEMP:
297 /* wait for stablization */
298 msleep(INV_MPU6050_SENSOR_UP_TIME);
299 ret = inv_mpu6050_sensor_show(st, st->reg->temperature,
300 IIO_MOD_X, val);
301 break;
302 default:
303 ret = -EINVAL;
304 break;
305 }
306 error_read_raw:
307 if (!st->chip_config.enable)
308 result |= inv_mpu6050_set_power_itg(st, false);
309 mutex_unlock(&indio_dev->mlock);
310 if (result)
311 return result;
312
313 return ret;
314 }
315 case IIO_CHAN_INFO_SCALE:
316 switch (chan->type) {
317 case IIO_ANGL_VEL:
318 *val = 0;
319 *val2 = gyro_scale_6050[st->chip_config.fsr];
320
321 return IIO_VAL_INT_PLUS_NANO;
322 case IIO_ACCEL:
323 *val = 0;
324 *val2 = accel_scale[st->chip_config.accl_fs];
325
326 return IIO_VAL_INT_PLUS_MICRO;
327 case IIO_TEMP:
328 *val = 0;
329 *val2 = INV_MPU6050_TEMP_SCALE;
330
331 return IIO_VAL_INT_PLUS_MICRO;
332 default:
333 return -EINVAL;
334 }
335 case IIO_CHAN_INFO_OFFSET:
336 switch (chan->type) {
337 case IIO_TEMP:
338 *val = INV_MPU6050_TEMP_OFFSET;
339
340 return IIO_VAL_INT;
341 default:
342 return -EINVAL;
343 }
344 case IIO_CHAN_INFO_CALIBBIAS:
345 switch (chan->type) {
346 case IIO_ANGL_VEL:
347 ret = inv_mpu6050_sensor_show(st, st->reg->gyro_offset,
348 chan->channel2, val);
349 return IIO_VAL_INT;
350 case IIO_ACCEL:
351 ret = inv_mpu6050_sensor_show(st, st->reg->accl_offset,
352 chan->channel2, val);
353 return IIO_VAL_INT;
354
355 default:
356 return -EINVAL;
357 }
358 default:
359 return -EINVAL;
360 }
361 }
362
363 static int inv_mpu6050_write_gyro_scale(struct inv_mpu6050_state *st, int val)
364 {
365 int result, i;
366 u8 d;
367
368 for (i = 0; i < ARRAY_SIZE(gyro_scale_6050); ++i) {
369 if (gyro_scale_6050[i] == val) {
370 d = (i << INV_MPU6050_GYRO_CONFIG_FSR_SHIFT);
371 result = regmap_write(st->map, st->reg->gyro_config, d);
372 if (result)
373 return result;
374
375 st->chip_config.fsr = i;
376 return 0;
377 }
378 }
379
380 return -EINVAL;
381 }
382
383 static int inv_write_raw_get_fmt(struct iio_dev *indio_dev,
384 struct iio_chan_spec const *chan, long mask)
385 {
386 switch (mask) {
387 case IIO_CHAN_INFO_SCALE:
388 switch (chan->type) {
389 case IIO_ANGL_VEL:
390 return IIO_VAL_INT_PLUS_NANO;
391 default:
392 return IIO_VAL_INT_PLUS_MICRO;
393 }
394 default:
395 return IIO_VAL_INT_PLUS_MICRO;
396 }
397
398 return -EINVAL;
399 }
400
401 static int inv_mpu6050_write_accel_scale(struct inv_mpu6050_state *st, int val)
402 {
403 int result, i;
404 u8 d;
405
406 for (i = 0; i < ARRAY_SIZE(accel_scale); ++i) {
407 if (accel_scale[i] == val) {
408 d = (i << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT);
409 result = regmap_write(st->map, st->reg->accl_config, d);
410 if (result)
411 return result;
412
413 st->chip_config.accl_fs = i;
414 return 0;
415 }
416 }
417
418 return -EINVAL;
419 }
420
421 static int inv_mpu6050_write_raw(struct iio_dev *indio_dev,
422 struct iio_chan_spec const *chan,
423 int val, int val2, long mask)
424 {
425 struct inv_mpu6050_state *st = iio_priv(indio_dev);
426 int result;
427
428 mutex_lock(&indio_dev->mlock);
429 /*
430 * we should only update scale when the chip is disabled, i.e.
431 * not running
432 */
433 if (st->chip_config.enable) {
434 result = -EBUSY;
435 goto error_write_raw;
436 }
437 result = inv_mpu6050_set_power_itg(st, true);
438 if (result)
439 goto error_write_raw;
440
441 switch (mask) {
442 case IIO_CHAN_INFO_SCALE:
443 switch (chan->type) {
444 case IIO_ANGL_VEL:
445 result = inv_mpu6050_write_gyro_scale(st, val2);
446 break;
447 case IIO_ACCEL:
448 result = inv_mpu6050_write_accel_scale(st, val2);
449 break;
450 default:
451 result = -EINVAL;
452 break;
453 }
454 break;
455 case IIO_CHAN_INFO_CALIBBIAS:
456 switch (chan->type) {
457 case IIO_ANGL_VEL:
458 result = inv_mpu6050_sensor_set(st,
459 st->reg->gyro_offset,
460 chan->channel2, val);
461 break;
462 case IIO_ACCEL:
463 result = inv_mpu6050_sensor_set(st,
464 st->reg->accl_offset,
465 chan->channel2, val);
466 break;
467 default:
468 result = -EINVAL;
469 }
470 default:
471 result = -EINVAL;
472 break;
473 }
474
475 error_write_raw:
476 result |= inv_mpu6050_set_power_itg(st, false);
477 mutex_unlock(&indio_dev->mlock);
478
479 return result;
480 }
481
482 /**
483 * inv_mpu6050_set_lpf() - set low pass filer based on fifo rate.
484 *
485 * Based on the Nyquist principle, the sampling rate must
486 * exceed twice of the bandwidth of the signal, or there
487 * would be alising. This function basically search for the
488 * correct low pass parameters based on the fifo rate, e.g,
489 * sampling frequency.
490 */
491 static int inv_mpu6050_set_lpf(struct inv_mpu6050_state *st, int rate)
492 {
493 const int hz[] = {188, 98, 42, 20, 10, 5};
494 const int d[] = {INV_MPU6050_FILTER_188HZ, INV_MPU6050_FILTER_98HZ,
495 INV_MPU6050_FILTER_42HZ, INV_MPU6050_FILTER_20HZ,
496 INV_MPU6050_FILTER_10HZ, INV_MPU6050_FILTER_5HZ};
497 int i, h, result;
498 u8 data;
499
500 h = (rate >> 1);
501 i = 0;
502 while ((h < hz[i]) && (i < ARRAY_SIZE(d) - 1))
503 i++;
504 data = d[i];
505 result = regmap_write(st->map, st->reg->lpf, data);
506 if (result)
507 return result;
508 st->chip_config.lpf = data;
509
510 return 0;
511 }
512
513 /**
514 * inv_mpu6050_fifo_rate_store() - Set fifo rate.
515 */
516 static ssize_t
517 inv_mpu6050_fifo_rate_store(struct device *dev, struct device_attribute *attr,
518 const char *buf, size_t count)
519 {
520 s32 fifo_rate;
521 u8 d;
522 int result;
523 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
524 struct inv_mpu6050_state *st = iio_priv(indio_dev);
525
526 if (kstrtoint(buf, 10, &fifo_rate))
527 return -EINVAL;
528 if (fifo_rate < INV_MPU6050_MIN_FIFO_RATE ||
529 fifo_rate > INV_MPU6050_MAX_FIFO_RATE)
530 return -EINVAL;
531 if (fifo_rate == st->chip_config.fifo_rate)
532 return count;
533
534 mutex_lock(&indio_dev->mlock);
535 if (st->chip_config.enable) {
536 result = -EBUSY;
537 goto fifo_rate_fail;
538 }
539 result = inv_mpu6050_set_power_itg(st, true);
540 if (result)
541 goto fifo_rate_fail;
542
543 d = INV_MPU6050_ONE_K_HZ / fifo_rate - 1;
544 result = regmap_write(st->map, st->reg->sample_rate_div, d);
545 if (result)
546 goto fifo_rate_fail;
547 st->chip_config.fifo_rate = fifo_rate;
548
549 result = inv_mpu6050_set_lpf(st, fifo_rate);
550 if (result)
551 goto fifo_rate_fail;
552
553 fifo_rate_fail:
554 result |= inv_mpu6050_set_power_itg(st, false);
555 mutex_unlock(&indio_dev->mlock);
556 if (result)
557 return result;
558
559 return count;
560 }
561
562 /**
563 * inv_fifo_rate_show() - Get the current sampling rate.
564 */
565 static ssize_t
566 inv_fifo_rate_show(struct device *dev, struct device_attribute *attr,
567 char *buf)
568 {
569 struct inv_mpu6050_state *st = iio_priv(dev_to_iio_dev(dev));
570
571 return sprintf(buf, "%d\n", st->chip_config.fifo_rate);
572 }
573
574 /**
575 * inv_attr_show() - calling this function will show current
576 * parameters.
577 */
578 static ssize_t inv_attr_show(struct device *dev, struct device_attribute *attr,
579 char *buf)
580 {
581 struct inv_mpu6050_state *st = iio_priv(dev_to_iio_dev(dev));
582 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
583 s8 *m;
584
585 switch (this_attr->address) {
586 /*
587 * In MPU6050, the two matrix are the same because gyro and accel
588 * are integrated in one chip
589 */
590 case ATTR_GYRO_MATRIX:
591 case ATTR_ACCL_MATRIX:
592 m = st->plat_data.orientation;
593
594 return sprintf(buf, "%d, %d, %d; %d, %d, %d; %d, %d, %d\n",
595 m[0], m[1], m[2], m[3], m[4], m[5], m[6], m[7], m[8]);
596 default:
597 return -EINVAL;
598 }
599 }
600
601 /**
602 * inv_mpu6050_validate_trigger() - validate_trigger callback for invensense
603 * MPU6050 device.
604 * @indio_dev: The IIO device
605 * @trig: The new trigger
606 *
607 * Returns: 0 if the 'trig' matches the trigger registered by the MPU6050
608 * device, -EINVAL otherwise.
609 */
610 static int inv_mpu6050_validate_trigger(struct iio_dev *indio_dev,
611 struct iio_trigger *trig)
612 {
613 struct inv_mpu6050_state *st = iio_priv(indio_dev);
614
615 if (st->trig != trig)
616 return -EINVAL;
617
618 return 0;
619 }
620
621 #define INV_MPU6050_CHAN(_type, _channel2, _index) \
622 { \
623 .type = _type, \
624 .modified = 1, \
625 .channel2 = _channel2, \
626 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
627 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
628 BIT(IIO_CHAN_INFO_CALIBBIAS), \
629 .scan_index = _index, \
630 .scan_type = { \
631 .sign = 's', \
632 .realbits = 16, \
633 .storagebits = 16, \
634 .shift = 0, \
635 .endianness = IIO_BE, \
636 }, \
637 }
638
639 static const struct iio_chan_spec inv_mpu_channels[] = {
640 IIO_CHAN_SOFT_TIMESTAMP(INV_MPU6050_SCAN_TIMESTAMP),
641 /*
642 * Note that temperature should only be via polled reading only,
643 * not the final scan elements output.
644 */
645 {
646 .type = IIO_TEMP,
647 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW)
648 | BIT(IIO_CHAN_INFO_OFFSET)
649 | BIT(IIO_CHAN_INFO_SCALE),
650 .scan_index = -1,
651 },
652 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_MPU6050_SCAN_GYRO_X),
653 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_MPU6050_SCAN_GYRO_Y),
654 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_MPU6050_SCAN_GYRO_Z),
655
656 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_MPU6050_SCAN_ACCL_X),
657 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_MPU6050_SCAN_ACCL_Y),
658 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),
659 };
660
661 /* constant IIO attribute */
662 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("10 20 50 100 200 500");
663 static IIO_CONST_ATTR(in_anglvel_scale_available,
664 "0.000133090 0.000266181 0.000532362 0.001064724");
665 static IIO_CONST_ATTR(in_accel_scale_available,
666 "0.000598 0.001196 0.002392 0.004785");
667 static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR, inv_fifo_rate_show,
668 inv_mpu6050_fifo_rate_store);
669 static IIO_DEVICE_ATTR(in_gyro_matrix, S_IRUGO, inv_attr_show, NULL,
670 ATTR_GYRO_MATRIX);
671 static IIO_DEVICE_ATTR(in_accel_matrix, S_IRUGO, inv_attr_show, NULL,
672 ATTR_ACCL_MATRIX);
673
674 static struct attribute *inv_attributes[] = {
675 &iio_dev_attr_in_gyro_matrix.dev_attr.attr,
676 &iio_dev_attr_in_accel_matrix.dev_attr.attr,
677 &iio_dev_attr_sampling_frequency.dev_attr.attr,
678 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
679 &iio_const_attr_in_accel_scale_available.dev_attr.attr,
680 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr,
681 NULL,
682 };
683
684 static const struct attribute_group inv_attribute_group = {
685 .attrs = inv_attributes
686 };
687
688 static const struct iio_info mpu_info = {
689 .driver_module = THIS_MODULE,
690 .read_raw = &inv_mpu6050_read_raw,
691 .write_raw = &inv_mpu6050_write_raw,
692 .write_raw_get_fmt = &inv_write_raw_get_fmt,
693 .attrs = &inv_attribute_group,
694 .validate_trigger = inv_mpu6050_validate_trigger,
695 };
696
697 /**
698 * inv_check_and_setup_chip() - check and setup chip.
699 */
700 static int inv_check_and_setup_chip(struct inv_mpu6050_state *st)
701 {
702 int result;
703
704 st->chip_type = INV_MPU6050;
705 st->hw = &hw_info[st->chip_type];
706 st->reg = hw_info[st->chip_type].reg;
707
708 /* reset to make sure previous state are not there */
709 result = regmap_write(st->map, st->reg->pwr_mgmt_1,
710 INV_MPU6050_BIT_H_RESET);
711 if (result)
712 return result;
713 msleep(INV_MPU6050_POWER_UP_TIME);
714 /*
715 * toggle power state. After reset, the sleep bit could be on
716 * or off depending on the OTP settings. Toggling power would
717 * make it in a definite state as well as making the hardware
718 * state align with the software state
719 */
720 result = inv_mpu6050_set_power_itg(st, false);
721 if (result)
722 return result;
723 result = inv_mpu6050_set_power_itg(st, true);
724 if (result)
725 return result;
726
727 result = inv_mpu6050_switch_engine(st, false,
728 INV_MPU6050_BIT_PWR_ACCL_STBY);
729 if (result)
730 return result;
731 result = inv_mpu6050_switch_engine(st, false,
732 INV_MPU6050_BIT_PWR_GYRO_STBY);
733 if (result)
734 return result;
735
736 return 0;
737 }
738
739 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
740 int (*inv_mpu_bus_setup)(struct iio_dev *))
741 {
742 struct inv_mpu6050_state *st;
743 struct iio_dev *indio_dev;
744 struct inv_mpu6050_platform_data *pdata;
745 struct device *dev = regmap_get_device(regmap);
746 int result;
747
748 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
749 if (!indio_dev)
750 return -ENOMEM;
751
752 st = iio_priv(indio_dev);
753 st->powerup_count = 0;
754 st->irq = irq;
755 st->map = regmap;
756 pdata = dev_get_platdata(dev);
757 if (pdata)
758 st->plat_data = *pdata;
759 /* power is turned on inside check chip type*/
760 result = inv_check_and_setup_chip(st);
761 if (result)
762 return result;
763
764 if (inv_mpu_bus_setup)
765 inv_mpu_bus_setup(indio_dev);
766
767 result = inv_mpu6050_init_config(indio_dev);
768 if (result) {
769 dev_err(dev, "Could not initialize device.\n");
770 return result;
771 }
772
773 dev_set_drvdata(dev, indio_dev);
774 indio_dev->dev.parent = dev;
775 /* name will be NULL when enumerated via ACPI */
776 if (name)
777 indio_dev->name = name;
778 else
779 indio_dev->name = dev_name(dev);
780 indio_dev->channels = inv_mpu_channels;
781 indio_dev->num_channels = ARRAY_SIZE(inv_mpu_channels);
782
783 indio_dev->info = &mpu_info;
784 indio_dev->modes = INDIO_BUFFER_TRIGGERED;
785
786 result = iio_triggered_buffer_setup(indio_dev,
787 inv_mpu6050_irq_handler,
788 inv_mpu6050_read_fifo,
789 NULL);
790 if (result) {
791 dev_err(dev, "configure buffer fail %d\n", result);
792 return result;
793 }
794 result = inv_mpu6050_probe_trigger(indio_dev);
795 if (result) {
796 dev_err(dev, "trigger probe fail %d\n", result);
797 goto out_unreg_ring;
798 }
799
800 INIT_KFIFO(st->timestamps);
801 spin_lock_init(&st->time_stamp_lock);
802 result = iio_device_register(indio_dev);
803 if (result) {
804 dev_err(dev, "IIO register fail %d\n", result);
805 goto out_remove_trigger;
806 }
807
808 return 0;
809
810 out_remove_trigger:
811 inv_mpu6050_remove_trigger(st);
812 out_unreg_ring:
813 iio_triggered_buffer_cleanup(indio_dev);
814 return result;
815 }
816 EXPORT_SYMBOL_GPL(inv_mpu_core_probe);
817
818 int inv_mpu_core_remove(struct device *dev)
819 {
820 struct iio_dev *indio_dev = dev_get_drvdata(dev);
821
822 iio_device_unregister(indio_dev);
823 inv_mpu6050_remove_trigger(iio_priv(indio_dev));
824 iio_triggered_buffer_cleanup(indio_dev);
825
826 return 0;
827 }
828 EXPORT_SYMBOL_GPL(inv_mpu_core_remove);
829
830 #ifdef CONFIG_PM_SLEEP
831
832 static int inv_mpu_resume(struct device *dev)
833 {
834 return inv_mpu6050_set_power_itg(iio_priv(dev_get_drvdata(dev)), true);
835 }
836
837 static int inv_mpu_suspend(struct device *dev)
838 {
839 return inv_mpu6050_set_power_itg(iio_priv(dev_get_drvdata(dev)), false);
840 }
841 #endif /* CONFIG_PM_SLEEP */
842
843 SIMPLE_DEV_PM_OPS(inv_mpu_pmops, inv_mpu_suspend, inv_mpu_resume);
844 EXPORT_SYMBOL_GPL(inv_mpu_pmops);
845
846 MODULE_AUTHOR("Invensense Corporation");
847 MODULE_DESCRIPTION("Invensense device MPU6050 driver");
848 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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