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RDMA/ocrdma: Fix compiler warning
[deliverable/linux.git] / drivers / infiniband / hw / ocrdma / ocrdma_hw.c
1 /*******************************************************************
2 * This file is part of the Emulex RoCE Device Driver for *
3 * RoCE (RDMA over Converged Ethernet) CNA Adapters. *
4 * Copyright (C) 2008-2012 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *
20 * Contact Information:
21 * linux-drivers@emulex.com
22 *
23 * Emulex
24 * 3333 Susan Street
25 * Costa Mesa, CA 92626
26 *******************************************************************/
27
28 #include <linux/sched.h>
29 #include <linux/interrupt.h>
30 #include <linux/log2.h>
31 #include <linux/dma-mapping.h>
32
33 #include <rdma/ib_verbs.h>
34 #include <rdma/ib_user_verbs.h>
35 #include <rdma/ib_addr.h>
36
37 #include "ocrdma.h"
38 #include "ocrdma_hw.h"
39 #include "ocrdma_verbs.h"
40 #include "ocrdma_ah.h"
41
42 enum mbx_status {
43 OCRDMA_MBX_STATUS_FAILED = 1,
44 OCRDMA_MBX_STATUS_ILLEGAL_FIELD = 3,
45 OCRDMA_MBX_STATUS_OOR = 100,
46 OCRDMA_MBX_STATUS_INVALID_PD = 101,
47 OCRDMA_MBX_STATUS_PD_INUSE = 102,
48 OCRDMA_MBX_STATUS_INVALID_CQ = 103,
49 OCRDMA_MBX_STATUS_INVALID_QP = 104,
50 OCRDMA_MBX_STATUS_INVALID_LKEY = 105,
51 OCRDMA_MBX_STATUS_ORD_EXCEEDS = 106,
52 OCRDMA_MBX_STATUS_IRD_EXCEEDS = 107,
53 OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS = 108,
54 OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS = 109,
55 OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS = 110,
56 OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS = 111,
57 OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS = 112,
58 OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE = 113,
59 OCRDMA_MBX_STATUS_MW_BOUND = 114,
60 OCRDMA_MBX_STATUS_INVALID_VA = 115,
61 OCRDMA_MBX_STATUS_INVALID_LENGTH = 116,
62 OCRDMA_MBX_STATUS_INVALID_FBO = 117,
63 OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS = 118,
64 OCRDMA_MBX_STATUS_INVALID_PBE_SIZE = 119,
65 OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY = 120,
66 OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT = 121,
67 OCRDMA_MBX_STATUS_INVALID_SRQ_ID = 129,
68 OCRDMA_MBX_STATUS_SRQ_ERROR = 133,
69 OCRDMA_MBX_STATUS_RQE_EXCEEDS = 134,
70 OCRDMA_MBX_STATUS_MTU_EXCEEDS = 135,
71 OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS = 136,
72 OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS = 137,
73 OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS = 138,
74 OCRDMA_MBX_STATUS_QP_BOUND = 130,
75 OCRDMA_MBX_STATUS_INVALID_CHANGE = 139,
76 OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP = 140,
77 OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER = 141,
78 OCRDMA_MBX_STATUS_MW_STILL_BOUND = 142,
79 OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID = 143,
80 OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS = 144
81 };
82
83 enum additional_status {
84 OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES = 22
85 };
86
87 enum cqe_status {
88 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 1,
89 OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER = 2,
90 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 3,
91 OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING = 4,
92 OCRDMA_MBX_CQE_STATUS_DMA_FAILED = 5
93 };
94
95 static inline void *ocrdma_get_eqe(struct ocrdma_eq *eq)
96 {
97 return eq->q.va + (eq->q.tail * sizeof(struct ocrdma_eqe));
98 }
99
100 static inline void ocrdma_eq_inc_tail(struct ocrdma_eq *eq)
101 {
102 eq->q.tail = (eq->q.tail + 1) & (OCRDMA_EQ_LEN - 1);
103 }
104
105 static inline void *ocrdma_get_mcqe(struct ocrdma_dev *dev)
106 {
107 struct ocrdma_mcqe *cqe = (struct ocrdma_mcqe *)
108 (dev->mq.cq.va + (dev->mq.cq.tail * sizeof(struct ocrdma_mcqe)));
109
110 if (!(le32_to_cpu(cqe->valid_ae_cmpl_cons) & OCRDMA_MCQE_VALID_MASK))
111 return NULL;
112 return cqe;
113 }
114
115 static inline void ocrdma_mcq_inc_tail(struct ocrdma_dev *dev)
116 {
117 dev->mq.cq.tail = (dev->mq.cq.tail + 1) & (OCRDMA_MQ_CQ_LEN - 1);
118 }
119
120 static inline struct ocrdma_mqe *ocrdma_get_mqe(struct ocrdma_dev *dev)
121 {
122 return dev->mq.sq.va + (dev->mq.sq.head * sizeof(struct ocrdma_mqe));
123 }
124
125 static inline void ocrdma_mq_inc_head(struct ocrdma_dev *dev)
126 {
127 dev->mq.sq.head = (dev->mq.sq.head + 1) & (OCRDMA_MQ_LEN - 1);
128 }
129
130 static inline void *ocrdma_get_mqe_rsp(struct ocrdma_dev *dev)
131 {
132 return dev->mq.sq.va + (dev->mqe_ctx.tag * sizeof(struct ocrdma_mqe));
133 }
134
135 enum ib_qp_state get_ibqp_state(enum ocrdma_qp_state qps)
136 {
137 switch (qps) {
138 case OCRDMA_QPS_RST:
139 return IB_QPS_RESET;
140 case OCRDMA_QPS_INIT:
141 return IB_QPS_INIT;
142 case OCRDMA_QPS_RTR:
143 return IB_QPS_RTR;
144 case OCRDMA_QPS_RTS:
145 return IB_QPS_RTS;
146 case OCRDMA_QPS_SQD:
147 case OCRDMA_QPS_SQ_DRAINING:
148 return IB_QPS_SQD;
149 case OCRDMA_QPS_SQE:
150 return IB_QPS_SQE;
151 case OCRDMA_QPS_ERR:
152 return IB_QPS_ERR;
153 }
154 return IB_QPS_ERR;
155 }
156
157 static enum ocrdma_qp_state get_ocrdma_qp_state(enum ib_qp_state qps)
158 {
159 switch (qps) {
160 case IB_QPS_RESET:
161 return OCRDMA_QPS_RST;
162 case IB_QPS_INIT:
163 return OCRDMA_QPS_INIT;
164 case IB_QPS_RTR:
165 return OCRDMA_QPS_RTR;
166 case IB_QPS_RTS:
167 return OCRDMA_QPS_RTS;
168 case IB_QPS_SQD:
169 return OCRDMA_QPS_SQD;
170 case IB_QPS_SQE:
171 return OCRDMA_QPS_SQE;
172 case IB_QPS_ERR:
173 return OCRDMA_QPS_ERR;
174 }
175 return OCRDMA_QPS_ERR;
176 }
177
178 static int ocrdma_get_mbx_errno(u32 status)
179 {
180 int err_num;
181 u8 mbox_status = (status & OCRDMA_MBX_RSP_STATUS_MASK) >>
182 OCRDMA_MBX_RSP_STATUS_SHIFT;
183 u8 add_status = (status & OCRDMA_MBX_RSP_ASTATUS_MASK) >>
184 OCRDMA_MBX_RSP_ASTATUS_SHIFT;
185
186 switch (mbox_status) {
187 case OCRDMA_MBX_STATUS_OOR:
188 case OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS:
189 err_num = -EAGAIN;
190 break;
191
192 case OCRDMA_MBX_STATUS_INVALID_PD:
193 case OCRDMA_MBX_STATUS_INVALID_CQ:
194 case OCRDMA_MBX_STATUS_INVALID_SRQ_ID:
195 case OCRDMA_MBX_STATUS_INVALID_QP:
196 case OCRDMA_MBX_STATUS_INVALID_CHANGE:
197 case OCRDMA_MBX_STATUS_MTU_EXCEEDS:
198 case OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER:
199 case OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID:
200 case OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS:
201 case OCRDMA_MBX_STATUS_ILLEGAL_FIELD:
202 case OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY:
203 case OCRDMA_MBX_STATUS_INVALID_LKEY:
204 case OCRDMA_MBX_STATUS_INVALID_VA:
205 case OCRDMA_MBX_STATUS_INVALID_LENGTH:
206 case OCRDMA_MBX_STATUS_INVALID_FBO:
207 case OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS:
208 case OCRDMA_MBX_STATUS_INVALID_PBE_SIZE:
209 case OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP:
210 case OCRDMA_MBX_STATUS_SRQ_ERROR:
211 case OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS:
212 err_num = -EINVAL;
213 break;
214
215 case OCRDMA_MBX_STATUS_PD_INUSE:
216 case OCRDMA_MBX_STATUS_QP_BOUND:
217 case OCRDMA_MBX_STATUS_MW_STILL_BOUND:
218 case OCRDMA_MBX_STATUS_MW_BOUND:
219 err_num = -EBUSY;
220 break;
221
222 case OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS:
223 case OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS:
224 case OCRDMA_MBX_STATUS_RQE_EXCEEDS:
225 case OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS:
226 case OCRDMA_MBX_STATUS_ORD_EXCEEDS:
227 case OCRDMA_MBX_STATUS_IRD_EXCEEDS:
228 case OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS:
229 case OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS:
230 case OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS:
231 err_num = -ENOBUFS;
232 break;
233
234 case OCRDMA_MBX_STATUS_FAILED:
235 switch (add_status) {
236 case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES:
237 err_num = -EAGAIN;
238 break;
239 }
240 default:
241 err_num = -EFAULT;
242 }
243 return err_num;
244 }
245
246 static int ocrdma_get_mbx_cqe_errno(u16 cqe_status)
247 {
248 int err_num = -EINVAL;
249
250 switch (cqe_status) {
251 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES:
252 err_num = -EPERM;
253 break;
254 case OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER:
255 err_num = -EINVAL;
256 break;
257 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES:
258 case OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING:
259 err_num = -EINVAL;
260 break;
261 case OCRDMA_MBX_CQE_STATUS_DMA_FAILED:
262 default:
263 err_num = -EINVAL;
264 break;
265 }
266 return err_num;
267 }
268
269 void ocrdma_ring_cq_db(struct ocrdma_dev *dev, u16 cq_id, bool armed,
270 bool solicited, u16 cqe_popped)
271 {
272 u32 val = cq_id & OCRDMA_DB_CQ_RING_ID_MASK;
273
274 val |= ((cq_id & OCRDMA_DB_CQ_RING_ID_EXT_MASK) <<
275 OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT);
276
277 if (armed)
278 val |= (1 << OCRDMA_DB_CQ_REARM_SHIFT);
279 if (solicited)
280 val |= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT);
281 val |= (cqe_popped << OCRDMA_DB_CQ_NUM_POPPED_SHIFT);
282 iowrite32(val, dev->nic_info.db + OCRDMA_DB_CQ_OFFSET);
283 }
284
285 static void ocrdma_ring_mq_db(struct ocrdma_dev *dev)
286 {
287 u32 val = 0;
288
289 val |= dev->mq.sq.id & OCRDMA_MQ_ID_MASK;
290 val |= 1 << OCRDMA_MQ_NUM_MQE_SHIFT;
291 iowrite32(val, dev->nic_info.db + OCRDMA_DB_MQ_OFFSET);
292 }
293
294 static void ocrdma_ring_eq_db(struct ocrdma_dev *dev, u16 eq_id,
295 bool arm, bool clear_int, u16 num_eqe)
296 {
297 u32 val = 0;
298
299 val |= eq_id & OCRDMA_EQ_ID_MASK;
300 val |= ((eq_id & OCRDMA_EQ_ID_EXT_MASK) << OCRDMA_EQ_ID_EXT_MASK_SHIFT);
301 if (arm)
302 val |= (1 << OCRDMA_REARM_SHIFT);
303 if (clear_int)
304 val |= (1 << OCRDMA_EQ_CLR_SHIFT);
305 val |= (1 << OCRDMA_EQ_TYPE_SHIFT);
306 val |= (num_eqe << OCRDMA_NUM_EQE_SHIFT);
307 iowrite32(val, dev->nic_info.db + OCRDMA_DB_EQ_OFFSET);
308 }
309
310 static void ocrdma_init_mch(struct ocrdma_mbx_hdr *cmd_hdr,
311 u8 opcode, u8 subsys, u32 cmd_len)
312 {
313 cmd_hdr->subsys_op = (opcode | (subsys << OCRDMA_MCH_SUBSYS_SHIFT));
314 cmd_hdr->timeout = 20; /* seconds */
315 cmd_hdr->cmd_len = cmd_len - sizeof(struct ocrdma_mbx_hdr);
316 }
317
318 static void *ocrdma_init_emb_mqe(u8 opcode, u32 cmd_len)
319 {
320 struct ocrdma_mqe *mqe;
321
322 mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
323 if (!mqe)
324 return NULL;
325 mqe->hdr.spcl_sge_cnt_emb |=
326 (OCRDMA_MQE_EMBEDDED << OCRDMA_MQE_HDR_EMB_SHIFT) &
327 OCRDMA_MQE_HDR_EMB_MASK;
328 mqe->hdr.pyld_len = cmd_len - sizeof(struct ocrdma_mqe_hdr);
329
330 ocrdma_init_mch(&mqe->u.emb_req.mch, opcode, OCRDMA_SUBSYS_ROCE,
331 mqe->hdr.pyld_len);
332 return mqe;
333 }
334
335 static void ocrdma_free_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q)
336 {
337 dma_free_coherent(&dev->nic_info.pdev->dev, q->size, q->va, q->dma);
338 }
339
340 static int ocrdma_alloc_q(struct ocrdma_dev *dev,
341 struct ocrdma_queue_info *q, u16 len, u16 entry_size)
342 {
343 memset(q, 0, sizeof(*q));
344 q->len = len;
345 q->entry_size = entry_size;
346 q->size = len * entry_size;
347 q->va = dma_alloc_coherent(&dev->nic_info.pdev->dev, q->size,
348 &q->dma, GFP_KERNEL);
349 if (!q->va)
350 return -ENOMEM;
351 memset(q->va, 0, q->size);
352 return 0;
353 }
354
355 static void ocrdma_build_q_pages(struct ocrdma_pa *q_pa, int cnt,
356 dma_addr_t host_pa, int hw_page_size)
357 {
358 int i;
359
360 for (i = 0; i < cnt; i++) {
361 q_pa[i].lo = (u32) (host_pa & 0xffffffff);
362 q_pa[i].hi = (u32) upper_32_bits(host_pa);
363 host_pa += hw_page_size;
364 }
365 }
366
367 static int ocrdma_mbx_delete_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q,
368 int queue_type)
369 {
370 u8 opcode = 0;
371 int status;
372 struct ocrdma_delete_q_req *cmd = dev->mbx_cmd;
373
374 switch (queue_type) {
375 case QTYPE_MCCQ:
376 opcode = OCRDMA_CMD_DELETE_MQ;
377 break;
378 case QTYPE_CQ:
379 opcode = OCRDMA_CMD_DELETE_CQ;
380 break;
381 case QTYPE_EQ:
382 opcode = OCRDMA_CMD_DELETE_EQ;
383 break;
384 default:
385 BUG();
386 }
387 memset(cmd, 0, sizeof(*cmd));
388 ocrdma_init_mch(&cmd->req, opcode, OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
389 cmd->id = q->id;
390
391 status = be_roce_mcc_cmd(dev->nic_info.netdev,
392 cmd, sizeof(*cmd), NULL, NULL);
393 if (!status)
394 q->created = false;
395 return status;
396 }
397
398 static int ocrdma_mbx_create_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
399 {
400 int status;
401 struct ocrdma_create_eq_req *cmd = dev->mbx_cmd;
402 struct ocrdma_create_eq_rsp *rsp = dev->mbx_cmd;
403
404 memset(cmd, 0, sizeof(*cmd));
405 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_EQ, OCRDMA_SUBSYS_COMMON,
406 sizeof(*cmd));
407
408 cmd->req.rsvd_version = 2;
409 cmd->num_pages = 4;
410 cmd->valid = OCRDMA_CREATE_EQ_VALID;
411 cmd->cnt = 4 << OCRDMA_CREATE_EQ_CNT_SHIFT;
412
413 ocrdma_build_q_pages(&cmd->pa[0], cmd->num_pages, eq->q.dma,
414 PAGE_SIZE_4K);
415 status = be_roce_mcc_cmd(dev->nic_info.netdev, cmd, sizeof(*cmd), NULL,
416 NULL);
417 if (!status) {
418 eq->q.id = rsp->vector_eqid & 0xffff;
419 eq->vector = (rsp->vector_eqid >> 16) & 0xffff;
420 eq->q.created = true;
421 }
422 return status;
423 }
424
425 static int ocrdma_create_eq(struct ocrdma_dev *dev,
426 struct ocrdma_eq *eq, u16 q_len)
427 {
428 int status;
429
430 status = ocrdma_alloc_q(dev, &eq->q, OCRDMA_EQ_LEN,
431 sizeof(struct ocrdma_eqe));
432 if (status)
433 return status;
434
435 status = ocrdma_mbx_create_eq(dev, eq);
436 if (status)
437 goto mbx_err;
438 eq->dev = dev;
439 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
440
441 return 0;
442 mbx_err:
443 ocrdma_free_q(dev, &eq->q);
444 return status;
445 }
446
447 static int ocrdma_get_irq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
448 {
449 int irq;
450
451 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
452 irq = dev->nic_info.pdev->irq;
453 else
454 irq = dev->nic_info.msix.vector_list[eq->vector];
455 return irq;
456 }
457
458 static void _ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
459 {
460 if (eq->q.created) {
461 ocrdma_mbx_delete_q(dev, &eq->q, QTYPE_EQ);
462 ocrdma_free_q(dev, &eq->q);
463 }
464 }
465
466 static void ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
467 {
468 int irq;
469
470 /* disarm EQ so that interrupts are not generated
471 * during freeing and EQ delete is in progress.
472 */
473 ocrdma_ring_eq_db(dev, eq->q.id, false, false, 0);
474
475 irq = ocrdma_get_irq(dev, eq);
476 free_irq(irq, eq);
477 _ocrdma_destroy_eq(dev, eq);
478 }
479
480 static void ocrdma_destroy_eqs(struct ocrdma_dev *dev)
481 {
482 int i;
483
484 for (i = 0; i < dev->eq_cnt; i++)
485 ocrdma_destroy_eq(dev, &dev->eq_tbl[i]);
486 }
487
488 static int ocrdma_mbx_mq_cq_create(struct ocrdma_dev *dev,
489 struct ocrdma_queue_info *cq,
490 struct ocrdma_queue_info *eq)
491 {
492 struct ocrdma_create_cq_cmd *cmd = dev->mbx_cmd;
493 struct ocrdma_create_cq_cmd_rsp *rsp = dev->mbx_cmd;
494 int status;
495
496 memset(cmd, 0, sizeof(*cmd));
497 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_CQ,
498 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
499
500 cmd->req.rsvd_version = OCRDMA_CREATE_CQ_VER2;
501 cmd->pgsz_pgcnt = (cq->size / OCRDMA_MIN_Q_PAGE_SIZE) <<
502 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
503 cmd->pgsz_pgcnt |= PAGES_4K_SPANNED(cq->va, cq->size);
504
505 cmd->ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
506 cmd->eqn = eq->id;
507 cmd->cqe_count = cq->size / sizeof(struct ocrdma_mcqe);
508
509 ocrdma_build_q_pages(&cmd->pa[0], cq->size / OCRDMA_MIN_Q_PAGE_SIZE,
510 cq->dma, PAGE_SIZE_4K);
511 status = be_roce_mcc_cmd(dev->nic_info.netdev,
512 cmd, sizeof(*cmd), NULL, NULL);
513 if (!status) {
514 cq->id = (u16) (rsp->cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
515 cq->created = true;
516 }
517 return status;
518 }
519
520 static u32 ocrdma_encoded_q_len(int q_len)
521 {
522 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
523
524 if (len_encoded == 16)
525 len_encoded = 0;
526 return len_encoded;
527 }
528
529 static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev,
530 struct ocrdma_queue_info *mq,
531 struct ocrdma_queue_info *cq)
532 {
533 int num_pages, status;
534 struct ocrdma_create_mq_req *cmd = dev->mbx_cmd;
535 struct ocrdma_create_mq_rsp *rsp = dev->mbx_cmd;
536 struct ocrdma_pa *pa;
537
538 memset(cmd, 0, sizeof(*cmd));
539 num_pages = PAGES_4K_SPANNED(mq->va, mq->size);
540
541 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ_EXT,
542 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
543 cmd->req.rsvd_version = 1;
544 cmd->cqid_pages = num_pages;
545 cmd->cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT);
546 cmd->async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
547
548 cmd->async_event_bitmap = Bit(OCRDMA_ASYNC_GRP5_EVE_CODE);
549 cmd->async_event_bitmap |= Bit(OCRDMA_ASYNC_RDMA_EVE_CODE);
550
551 cmd->async_cqid_ringsize = cq->id;
552 cmd->async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<
553 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT);
554 cmd->valid = OCRDMA_CREATE_MQ_VALID;
555 pa = &cmd->pa[0];
556
557 ocrdma_build_q_pages(pa, num_pages, mq->dma, PAGE_SIZE_4K);
558 status = be_roce_mcc_cmd(dev->nic_info.netdev,
559 cmd, sizeof(*cmd), NULL, NULL);
560 if (!status) {
561 mq->id = rsp->id;
562 mq->created = true;
563 }
564 return status;
565 }
566
567 static int ocrdma_create_mq(struct ocrdma_dev *dev)
568 {
569 int status;
570
571 /* Alloc completion queue for Mailbox queue */
572 status = ocrdma_alloc_q(dev, &dev->mq.cq, OCRDMA_MQ_CQ_LEN,
573 sizeof(struct ocrdma_mcqe));
574 if (status)
575 goto alloc_err;
576
577 status = ocrdma_mbx_mq_cq_create(dev, &dev->mq.cq, &dev->eq_tbl[0].q);
578 if (status)
579 goto mbx_cq_free;
580
581 memset(&dev->mqe_ctx, 0, sizeof(dev->mqe_ctx));
582 init_waitqueue_head(&dev->mqe_ctx.cmd_wait);
583 mutex_init(&dev->mqe_ctx.lock);
584
585 /* Alloc Mailbox queue */
586 status = ocrdma_alloc_q(dev, &dev->mq.sq, OCRDMA_MQ_LEN,
587 sizeof(struct ocrdma_mqe));
588 if (status)
589 goto mbx_cq_destroy;
590 status = ocrdma_mbx_create_mq(dev, &dev->mq.sq, &dev->mq.cq);
591 if (status)
592 goto mbx_q_free;
593 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, 0);
594 return 0;
595
596 mbx_q_free:
597 ocrdma_free_q(dev, &dev->mq.sq);
598 mbx_cq_destroy:
599 ocrdma_mbx_delete_q(dev, &dev->mq.cq, QTYPE_CQ);
600 mbx_cq_free:
601 ocrdma_free_q(dev, &dev->mq.cq);
602 alloc_err:
603 return status;
604 }
605
606 static void ocrdma_destroy_mq(struct ocrdma_dev *dev)
607 {
608 struct ocrdma_queue_info *mbxq, *cq;
609
610 /* mqe_ctx lock synchronizes with any other pending cmds. */
611 mutex_lock(&dev->mqe_ctx.lock);
612 mbxq = &dev->mq.sq;
613 if (mbxq->created) {
614 ocrdma_mbx_delete_q(dev, mbxq, QTYPE_MCCQ);
615 ocrdma_free_q(dev, mbxq);
616 }
617 mutex_unlock(&dev->mqe_ctx.lock);
618
619 cq = &dev->mq.cq;
620 if (cq->created) {
621 ocrdma_mbx_delete_q(dev, cq, QTYPE_CQ);
622 ocrdma_free_q(dev, cq);
623 }
624 }
625
626 static void ocrdma_process_qpcat_error(struct ocrdma_dev *dev,
627 struct ocrdma_qp *qp)
628 {
629 enum ib_qp_state new_ib_qps = IB_QPS_ERR;
630 enum ib_qp_state old_ib_qps;
631
632 if (qp == NULL)
633 BUG();
634 ocrdma_qp_state_change(qp, new_ib_qps, &old_ib_qps);
635 }
636
637 static void ocrdma_dispatch_ibevent(struct ocrdma_dev *dev,
638 struct ocrdma_ae_mcqe *cqe)
639 {
640 struct ocrdma_qp *qp = NULL;
641 struct ocrdma_cq *cq = NULL;
642 struct ib_event ib_evt;
643 int cq_event = 0;
644 int qp_event = 1;
645 int srq_event = 0;
646 int dev_event = 0;
647 int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
648 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
649
650 if (cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPVALID)
651 qp = dev->qp_tbl[cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPID_MASK];
652 if (cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQVALID)
653 cq = dev->cq_tbl[cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQID_MASK];
654
655 ib_evt.device = &dev->ibdev;
656
657 switch (type) {
658 case OCRDMA_CQ_ERROR:
659 ib_evt.element.cq = &cq->ibcq;
660 ib_evt.event = IB_EVENT_CQ_ERR;
661 cq_event = 1;
662 qp_event = 0;
663 break;
664 case OCRDMA_CQ_OVERRUN_ERROR:
665 ib_evt.element.cq = &cq->ibcq;
666 ib_evt.event = IB_EVENT_CQ_ERR;
667 break;
668 case OCRDMA_CQ_QPCAT_ERROR:
669 ib_evt.element.qp = &qp->ibqp;
670 ib_evt.event = IB_EVENT_QP_FATAL;
671 ocrdma_process_qpcat_error(dev, qp);
672 break;
673 case OCRDMA_QP_ACCESS_ERROR:
674 ib_evt.element.qp = &qp->ibqp;
675 ib_evt.event = IB_EVENT_QP_ACCESS_ERR;
676 break;
677 case OCRDMA_QP_COMM_EST_EVENT:
678 ib_evt.element.qp = &qp->ibqp;
679 ib_evt.event = IB_EVENT_COMM_EST;
680 break;
681 case OCRDMA_SQ_DRAINED_EVENT:
682 ib_evt.element.qp = &qp->ibqp;
683 ib_evt.event = IB_EVENT_SQ_DRAINED;
684 break;
685 case OCRDMA_DEVICE_FATAL_EVENT:
686 ib_evt.element.port_num = 1;
687 ib_evt.event = IB_EVENT_DEVICE_FATAL;
688 qp_event = 0;
689 dev_event = 1;
690 break;
691 case OCRDMA_SRQCAT_ERROR:
692 ib_evt.element.srq = &qp->srq->ibsrq;
693 ib_evt.event = IB_EVENT_SRQ_ERR;
694 srq_event = 1;
695 qp_event = 0;
696 break;
697 case OCRDMA_SRQ_LIMIT_EVENT:
698 ib_evt.element.srq = &qp->srq->ibsrq;
699 ib_evt.event = IB_EVENT_SRQ_LIMIT_REACHED;
700 srq_event = 1;
701 qp_event = 0;
702 break;
703 case OCRDMA_QP_LAST_WQE_EVENT:
704 ib_evt.element.qp = &qp->ibqp;
705 ib_evt.event = IB_EVENT_QP_LAST_WQE_REACHED;
706 break;
707 default:
708 cq_event = 0;
709 qp_event = 0;
710 srq_event = 0;
711 dev_event = 0;
712 pr_err("%s() unknown type=0x%x\n", __func__, type);
713 break;
714 }
715
716 if (qp_event) {
717 if (qp->ibqp.event_handler)
718 qp->ibqp.event_handler(&ib_evt, qp->ibqp.qp_context);
719 } else if (cq_event) {
720 if (cq->ibcq.event_handler)
721 cq->ibcq.event_handler(&ib_evt, cq->ibcq.cq_context);
722 } else if (srq_event) {
723 if (qp->srq->ibsrq.event_handler)
724 qp->srq->ibsrq.event_handler(&ib_evt,
725 qp->srq->ibsrq.
726 srq_context);
727 } else if (dev_event) {
728 ib_dispatch_event(&ib_evt);
729 }
730
731 }
732
733 static void ocrdma_process_grp5_aync(struct ocrdma_dev *dev,
734 struct ocrdma_ae_mcqe *cqe)
735 {
736 struct ocrdma_ae_pvid_mcqe *evt;
737 int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
738 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
739
740 switch (type) {
741 case OCRDMA_ASYNC_EVENT_PVID_STATE:
742 evt = (struct ocrdma_ae_pvid_mcqe *)cqe;
743 if ((evt->tag_enabled & OCRDMA_AE_PVID_MCQE_ENABLED_MASK) >>
744 OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT)
745 dev->pvid = ((evt->tag_enabled &
746 OCRDMA_AE_PVID_MCQE_TAG_MASK) >>
747 OCRDMA_AE_PVID_MCQE_TAG_SHIFT);
748 break;
749 default:
750 /* Not interested evts. */
751 break;
752 }
753 }
754
755
756 static void ocrdma_process_acqe(struct ocrdma_dev *dev, void *ae_cqe)
757 {
758 /* async CQE processing */
759 struct ocrdma_ae_mcqe *cqe = ae_cqe;
760 u32 evt_code = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_CODE_MASK) >>
761 OCRDMA_AE_MCQE_EVENT_CODE_SHIFT;
762
763 if (evt_code == OCRDMA_ASYNC_RDMA_EVE_CODE)
764 ocrdma_dispatch_ibevent(dev, cqe);
765 else if (evt_code == OCRDMA_ASYNC_GRP5_EVE_CODE)
766 ocrdma_process_grp5_aync(dev, cqe);
767 else
768 pr_err("%s(%d) invalid evt code=0x%x\n", __func__,
769 dev->id, evt_code);
770 }
771
772 static void ocrdma_process_mcqe(struct ocrdma_dev *dev, struct ocrdma_mcqe *cqe)
773 {
774 if (dev->mqe_ctx.tag == cqe->tag_lo && dev->mqe_ctx.cmd_done == false) {
775 dev->mqe_ctx.cqe_status = (cqe->status &
776 OCRDMA_MCQE_STATUS_MASK) >> OCRDMA_MCQE_STATUS_SHIFT;
777 dev->mqe_ctx.ext_status =
778 (cqe->status & OCRDMA_MCQE_ESTATUS_MASK)
779 >> OCRDMA_MCQE_ESTATUS_SHIFT;
780 dev->mqe_ctx.cmd_done = true;
781 wake_up(&dev->mqe_ctx.cmd_wait);
782 } else
783 pr_err("%s() cqe for invalid tag0x%x.expected=0x%x\n",
784 __func__, cqe->tag_lo, dev->mqe_ctx.tag);
785 }
786
787 static int ocrdma_mq_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
788 {
789 u16 cqe_popped = 0;
790 struct ocrdma_mcqe *cqe;
791
792 while (1) {
793 cqe = ocrdma_get_mcqe(dev);
794 if (cqe == NULL)
795 break;
796 ocrdma_le32_to_cpu(cqe, sizeof(*cqe));
797 cqe_popped += 1;
798 if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_AE_MASK)
799 ocrdma_process_acqe(dev, cqe);
800 else if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_CMPL_MASK)
801 ocrdma_process_mcqe(dev, cqe);
802 else
803 pr_err("%s() cqe->compl is not set.\n", __func__);
804 memset(cqe, 0, sizeof(struct ocrdma_mcqe));
805 ocrdma_mcq_inc_tail(dev);
806 }
807 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, cqe_popped);
808 return 0;
809 }
810
811 static void ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
812 struct ocrdma_cq *cq)
813 {
814 unsigned long flags;
815 struct ocrdma_qp *qp;
816 bool buddy_cq_found = false;
817 /* Go through list of QPs in error state which are using this CQ
818 * and invoke its callback handler to trigger CQE processing for
819 * error/flushed CQE. It is rare to find more than few entries in
820 * this list as most consumers stops after getting error CQE.
821 * List is traversed only once when a matching buddy cq found for a QP.
822 */
823 spin_lock_irqsave(&dev->flush_q_lock, flags);
824 list_for_each_entry(qp, &cq->sq_head, sq_entry) {
825 if (qp->srq)
826 continue;
827 /* if wq and rq share the same cq, than comp_handler
828 * is already invoked.
829 */
830 if (qp->sq_cq == qp->rq_cq)
831 continue;
832 /* if completion came on sq, rq's cq is buddy cq.
833 * if completion came on rq, sq's cq is buddy cq.
834 */
835 if (qp->sq_cq == cq)
836 cq = qp->rq_cq;
837 else
838 cq = qp->sq_cq;
839 buddy_cq_found = true;
840 break;
841 }
842 spin_unlock_irqrestore(&dev->flush_q_lock, flags);
843 if (buddy_cq_found == false)
844 return;
845 if (cq->ibcq.comp_handler) {
846 spin_lock_irqsave(&cq->comp_handler_lock, flags);
847 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
848 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
849 }
850 }
851
852 static void ocrdma_qp_cq_handler(struct ocrdma_dev *dev, u16 cq_idx)
853 {
854 unsigned long flags;
855 struct ocrdma_cq *cq;
856
857 if (cq_idx >= OCRDMA_MAX_CQ)
858 BUG();
859
860 cq = dev->cq_tbl[cq_idx];
861 if (cq == NULL) {
862 pr_err("%s%d invalid id=0x%x\n", __func__, dev->id, cq_idx);
863 return;
864 }
865 spin_lock_irqsave(&cq->cq_lock, flags);
866 cq->armed = false;
867 cq->solicited = false;
868 spin_unlock_irqrestore(&cq->cq_lock, flags);
869
870 ocrdma_ring_cq_db(dev, cq->id, false, false, 0);
871
872 if (cq->ibcq.comp_handler) {
873 spin_lock_irqsave(&cq->comp_handler_lock, flags);
874 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
875 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
876 }
877 ocrdma_qp_buddy_cq_handler(dev, cq);
878 }
879
880 static void ocrdma_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
881 {
882 /* process the MQ-CQE. */
883 if (cq_id == dev->mq.cq.id)
884 ocrdma_mq_cq_handler(dev, cq_id);
885 else
886 ocrdma_qp_cq_handler(dev, cq_id);
887 }
888
889 static irqreturn_t ocrdma_irq_handler(int irq, void *handle)
890 {
891 struct ocrdma_eq *eq = handle;
892 struct ocrdma_dev *dev = eq->dev;
893 struct ocrdma_eqe eqe;
894 struct ocrdma_eqe *ptr;
895 u16 eqe_popped = 0;
896 u16 cq_id;
897 while (1) {
898 ptr = ocrdma_get_eqe(eq);
899 eqe = *ptr;
900 ocrdma_le32_to_cpu(&eqe, sizeof(eqe));
901 if ((eqe.id_valid & OCRDMA_EQE_VALID_MASK) == 0)
902 break;
903 eqe_popped += 1;
904 ptr->id_valid = 0;
905 /* check whether its CQE or not. */
906 if ((eqe.id_valid & OCRDMA_EQE_FOR_CQE_MASK) == 0) {
907 cq_id = eqe.id_valid >> OCRDMA_EQE_RESOURCE_ID_SHIFT;
908 ocrdma_cq_handler(dev, cq_id);
909 }
910 ocrdma_eq_inc_tail(eq);
911 }
912 ocrdma_ring_eq_db(dev, eq->q.id, true, true, eqe_popped);
913 /* Ring EQ doorbell with num_popped to 0 to enable interrupts again. */
914 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
915 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
916 return IRQ_HANDLED;
917 }
918
919 static void ocrdma_post_mqe(struct ocrdma_dev *dev, struct ocrdma_mqe *cmd)
920 {
921 struct ocrdma_mqe *mqe;
922
923 dev->mqe_ctx.tag = dev->mq.sq.head;
924 dev->mqe_ctx.cmd_done = false;
925 mqe = ocrdma_get_mqe(dev);
926 cmd->hdr.tag_lo = dev->mq.sq.head;
927 ocrdma_copy_cpu_to_le32(mqe, cmd, sizeof(*mqe));
928 /* make sure descriptor is written before ringing doorbell */
929 wmb();
930 ocrdma_mq_inc_head(dev);
931 ocrdma_ring_mq_db(dev);
932 }
933
934 static int ocrdma_wait_mqe_cmpl(struct ocrdma_dev *dev)
935 {
936 long status;
937 /* 30 sec timeout */
938 status = wait_event_timeout(dev->mqe_ctx.cmd_wait,
939 (dev->mqe_ctx.cmd_done != false),
940 msecs_to_jiffies(30000));
941 if (status)
942 return 0;
943 else
944 return -1;
945 }
946
947 /* issue a mailbox command on the MQ */
948 static int ocrdma_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe)
949 {
950 int status = 0;
951 u16 cqe_status, ext_status;
952 struct ocrdma_mqe *rsp;
953
954 mutex_lock(&dev->mqe_ctx.lock);
955 ocrdma_post_mqe(dev, mqe);
956 status = ocrdma_wait_mqe_cmpl(dev);
957 if (status)
958 goto mbx_err;
959 cqe_status = dev->mqe_ctx.cqe_status;
960 ext_status = dev->mqe_ctx.ext_status;
961 rsp = ocrdma_get_mqe_rsp(dev);
962 ocrdma_copy_le32_to_cpu(mqe, rsp, (sizeof(*mqe)));
963 if (cqe_status || ext_status) {
964 pr_err("%s() opcode=0x%x, cqe_status=0x%x, ext_status=0x%x\n",
965 __func__,
966 (rsp->u.rsp.subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
967 OCRDMA_MBX_RSP_OPCODE_SHIFT, cqe_status, ext_status);
968 status = ocrdma_get_mbx_cqe_errno(cqe_status);
969 goto mbx_err;
970 }
971 if (mqe->u.rsp.status & OCRDMA_MBX_RSP_STATUS_MASK)
972 status = ocrdma_get_mbx_errno(mqe->u.rsp.status);
973 mbx_err:
974 mutex_unlock(&dev->mqe_ctx.lock);
975 return status;
976 }
977
978 static void ocrdma_get_attr(struct ocrdma_dev *dev,
979 struct ocrdma_dev_attr *attr,
980 struct ocrdma_mbx_query_config *rsp)
981 {
982 attr->max_pd =
983 (rsp->max_pd_ca_ack_delay & OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK) >>
984 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT;
985 attr->max_qp =
986 (rsp->qp_srq_cq_ird_ord & OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK) >>
987 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT;
988 attr->max_send_sge = ((rsp->max_write_send_sge &
989 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
990 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT);
991 attr->max_recv_sge = (rsp->max_write_send_sge &
992 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
993 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT;
994 attr->max_srq_sge = (rsp->max_srq_rqe_sge &
995 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK) >>
996 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET;
997 attr->max_rdma_sge = (rsp->max_write_send_sge &
998 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK) >>
999 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT;
1000 attr->max_ord_per_qp = (rsp->max_ird_ord_per_qp &
1001 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK) >>
1002 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT;
1003 attr->max_srq =
1004 (rsp->max_srq_rpir_qps & OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK) >>
1005 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET;
1006 attr->max_ird_per_qp = (rsp->max_ird_ord_per_qp &
1007 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK) >>
1008 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT;
1009 attr->cq_overflow_detect = (rsp->qp_srq_cq_ird_ord &
1010 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK) >>
1011 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT;
1012 attr->srq_supported = (rsp->qp_srq_cq_ird_ord &
1013 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK) >>
1014 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT;
1015 attr->local_ca_ack_delay = (rsp->max_pd_ca_ack_delay &
1016 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK) >>
1017 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT;
1018 attr->max_mr = rsp->max_mr;
1019 attr->max_mr_size = ~0ull;
1020 attr->max_fmr = 0;
1021 attr->max_pages_per_frmr = rsp->max_pages_per_frmr;
1022 attr->max_num_mr_pbl = rsp->max_num_mr_pbl;
1023 attr->max_cqe = rsp->max_cq_cqes_per_cq &
1024 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK;
1025 attr->max_cq = (rsp->max_cq_cqes_per_cq &
1026 OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK) >>
1027 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET;
1028 attr->wqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1029 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK) >>
1030 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET) *
1031 OCRDMA_WQE_STRIDE;
1032 attr->rqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1033 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK) >>
1034 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET) *
1035 OCRDMA_WQE_STRIDE;
1036 attr->max_inline_data =
1037 attr->wqe_size - (sizeof(struct ocrdma_hdr_wqe) +
1038 sizeof(struct ocrdma_sge));
1039 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY) {
1040 attr->ird = 1;
1041 attr->ird_page_size = OCRDMA_MIN_Q_PAGE_SIZE;
1042 attr->num_ird_pages = MAX_OCRDMA_IRD_PAGES;
1043 }
1044 dev->attr.max_wqe = rsp->max_wqes_rqes_per_q >>
1045 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET;
1046 dev->attr.max_rqe = rsp->max_wqes_rqes_per_q &
1047 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK;
1048 }
1049
1050 static int ocrdma_check_fw_config(struct ocrdma_dev *dev,
1051 struct ocrdma_fw_conf_rsp *conf)
1052 {
1053 u32 fn_mode;
1054
1055 fn_mode = conf->fn_mode & OCRDMA_FN_MODE_RDMA;
1056 if (fn_mode != OCRDMA_FN_MODE_RDMA)
1057 return -EINVAL;
1058 dev->base_eqid = conf->base_eqid;
1059 dev->max_eq = conf->max_eq;
1060 return 0;
1061 }
1062
1063 /* can be issued only during init time. */
1064 static int ocrdma_mbx_query_fw_ver(struct ocrdma_dev *dev)
1065 {
1066 int status = -ENOMEM;
1067 struct ocrdma_mqe *cmd;
1068 struct ocrdma_fw_ver_rsp *rsp;
1069
1070 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_VER, sizeof(*cmd));
1071 if (!cmd)
1072 return -ENOMEM;
1073 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1074 OCRDMA_CMD_GET_FW_VER,
1075 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1076
1077 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1078 if (status)
1079 goto mbx_err;
1080 rsp = (struct ocrdma_fw_ver_rsp *)cmd;
1081 memset(&dev->attr.fw_ver[0], 0, sizeof(dev->attr.fw_ver));
1082 memcpy(&dev->attr.fw_ver[0], &rsp->running_ver[0],
1083 sizeof(rsp->running_ver));
1084 ocrdma_le32_to_cpu(dev->attr.fw_ver, sizeof(rsp->running_ver));
1085 mbx_err:
1086 kfree(cmd);
1087 return status;
1088 }
1089
1090 /* can be issued only during init time. */
1091 static int ocrdma_mbx_query_fw_config(struct ocrdma_dev *dev)
1092 {
1093 int status = -ENOMEM;
1094 struct ocrdma_mqe *cmd;
1095 struct ocrdma_fw_conf_rsp *rsp;
1096
1097 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_CONFIG, sizeof(*cmd));
1098 if (!cmd)
1099 return -ENOMEM;
1100 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1101 OCRDMA_CMD_GET_FW_CONFIG,
1102 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1103 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1104 if (status)
1105 goto mbx_err;
1106 rsp = (struct ocrdma_fw_conf_rsp *)cmd;
1107 status = ocrdma_check_fw_config(dev, rsp);
1108 mbx_err:
1109 kfree(cmd);
1110 return status;
1111 }
1112
1113 static int ocrdma_mbx_query_dev(struct ocrdma_dev *dev)
1114 {
1115 int status = -ENOMEM;
1116 struct ocrdma_mbx_query_config *rsp;
1117 struct ocrdma_mqe *cmd;
1118
1119 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_CONFIG, sizeof(*cmd));
1120 if (!cmd)
1121 return status;
1122 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1123 if (status)
1124 goto mbx_err;
1125 rsp = (struct ocrdma_mbx_query_config *)cmd;
1126 ocrdma_get_attr(dev, &dev->attr, rsp);
1127 mbx_err:
1128 kfree(cmd);
1129 return status;
1130 }
1131
1132 int ocrdma_mbx_get_link_speed(struct ocrdma_dev *dev, u8 *lnk_speed)
1133 {
1134 int status = -ENOMEM;
1135 struct ocrdma_get_link_speed_rsp *rsp;
1136 struct ocrdma_mqe *cmd;
1137
1138 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1139 sizeof(*cmd));
1140 if (!cmd)
1141 return status;
1142 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1143 OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1144 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1145
1146 ((struct ocrdma_mbx_hdr *)cmd->u.cmd)->rsvd_version = 0x1;
1147
1148 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1149 if (status)
1150 goto mbx_err;
1151
1152 rsp = (struct ocrdma_get_link_speed_rsp *)cmd;
1153 *lnk_speed = rsp->phys_port_speed;
1154
1155 mbx_err:
1156 kfree(cmd);
1157 return status;
1158 }
1159
1160 int ocrdma_mbx_alloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1161 {
1162 int status = -ENOMEM;
1163 struct ocrdma_alloc_pd *cmd;
1164 struct ocrdma_alloc_pd_rsp *rsp;
1165
1166 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD, sizeof(*cmd));
1167 if (!cmd)
1168 return status;
1169 if (pd->dpp_enabled)
1170 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1171 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1172 if (status)
1173 goto mbx_err;
1174 rsp = (struct ocrdma_alloc_pd_rsp *)cmd;
1175 pd->id = rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_PDID_MASK;
1176 if (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) {
1177 pd->dpp_enabled = true;
1178 pd->dpp_page = rsp->dpp_page_pdid >>
1179 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1180 } else {
1181 pd->dpp_enabled = false;
1182 pd->num_dpp_qp = 0;
1183 }
1184 mbx_err:
1185 kfree(cmd);
1186 return status;
1187 }
1188
1189 int ocrdma_mbx_dealloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1190 {
1191 int status = -ENOMEM;
1192 struct ocrdma_dealloc_pd *cmd;
1193
1194 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD, sizeof(*cmd));
1195 if (!cmd)
1196 return status;
1197 cmd->id = pd->id;
1198 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1199 kfree(cmd);
1200 return status;
1201 }
1202
1203 static int ocrdma_build_q_conf(u32 *num_entries, int entry_size,
1204 int *num_pages, int *page_size)
1205 {
1206 int i;
1207 int mem_size;
1208
1209 *num_entries = roundup_pow_of_two(*num_entries);
1210 mem_size = *num_entries * entry_size;
1211 /* find the possible lowest possible multiplier */
1212 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1213 if (mem_size <= (OCRDMA_Q_PAGE_BASE_SIZE << i))
1214 break;
1215 }
1216 if (i >= OCRDMA_MAX_Q_PAGE_SIZE_CNT)
1217 return -EINVAL;
1218 mem_size = roundup(mem_size,
1219 ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES));
1220 *num_pages =
1221 mem_size / ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1222 *page_size = ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1223 *num_entries = mem_size / entry_size;
1224 return 0;
1225 }
1226
1227 static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev)
1228 {
1229 int i ;
1230 int status = 0;
1231 int max_ah;
1232 struct ocrdma_create_ah_tbl *cmd;
1233 struct ocrdma_create_ah_tbl_rsp *rsp;
1234 struct pci_dev *pdev = dev->nic_info.pdev;
1235 dma_addr_t pa;
1236 struct ocrdma_pbe *pbes;
1237
1238 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_AH_TBL, sizeof(*cmd));
1239 if (!cmd)
1240 return status;
1241
1242 max_ah = OCRDMA_MAX_AH;
1243 dev->av_tbl.size = sizeof(struct ocrdma_av) * max_ah;
1244
1245 /* number of PBEs in PBL */
1246 cmd->ah_conf = (OCRDMA_AH_TBL_PAGES <<
1247 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT) &
1248 OCRDMA_CREATE_AH_NUM_PAGES_MASK;
1249
1250 /* page size */
1251 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1252 if (PAGE_SIZE == (OCRDMA_MIN_Q_PAGE_SIZE << i))
1253 break;
1254 }
1255 cmd->ah_conf |= (i << OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT) &
1256 OCRDMA_CREATE_AH_PAGE_SIZE_MASK;
1257
1258 /* ah_entry size */
1259 cmd->ah_conf |= (sizeof(struct ocrdma_av) <<
1260 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT) &
1261 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK;
1262
1263 dev->av_tbl.pbl.va = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1264 &dev->av_tbl.pbl.pa,
1265 GFP_KERNEL);
1266 if (dev->av_tbl.pbl.va == NULL)
1267 goto mem_err;
1268
1269 dev->av_tbl.va = dma_alloc_coherent(&pdev->dev, dev->av_tbl.size,
1270 &pa, GFP_KERNEL);
1271 if (dev->av_tbl.va == NULL)
1272 goto mem_err_ah;
1273 dev->av_tbl.pa = pa;
1274 dev->av_tbl.num_ah = max_ah;
1275 memset(dev->av_tbl.va, 0, dev->av_tbl.size);
1276
1277 pbes = (struct ocrdma_pbe *)dev->av_tbl.pbl.va;
1278 for (i = 0; i < dev->av_tbl.size / OCRDMA_MIN_Q_PAGE_SIZE; i++) {
1279 pbes[i].pa_lo = (u32) (pa & 0xffffffff);
1280 pbes[i].pa_hi = (u32) upper_32_bits(pa);
1281 pa += PAGE_SIZE;
1282 }
1283 cmd->tbl_addr[0].lo = (u32)(dev->av_tbl.pbl.pa & 0xFFFFFFFF);
1284 cmd->tbl_addr[0].hi = (u32)upper_32_bits(dev->av_tbl.pbl.pa);
1285 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1286 if (status)
1287 goto mbx_err;
1288 rsp = (struct ocrdma_create_ah_tbl_rsp *)cmd;
1289 dev->av_tbl.ahid = rsp->ahid & 0xFFFF;
1290 kfree(cmd);
1291 return 0;
1292
1293 mbx_err:
1294 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1295 dev->av_tbl.pa);
1296 dev->av_tbl.va = NULL;
1297 mem_err_ah:
1298 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1299 dev->av_tbl.pbl.pa);
1300 dev->av_tbl.pbl.va = NULL;
1301 dev->av_tbl.size = 0;
1302 mem_err:
1303 kfree(cmd);
1304 return status;
1305 }
1306
1307 static void ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev *dev)
1308 {
1309 struct ocrdma_delete_ah_tbl *cmd;
1310 struct pci_dev *pdev = dev->nic_info.pdev;
1311
1312 if (dev->av_tbl.va == NULL)
1313 return;
1314
1315 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_AH_TBL, sizeof(*cmd));
1316 if (!cmd)
1317 return;
1318 cmd->ahid = dev->av_tbl.ahid;
1319
1320 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1321 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1322 dev->av_tbl.pa);
1323 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1324 dev->av_tbl.pbl.pa);
1325 kfree(cmd);
1326 }
1327
1328 /* Multiple CQs uses the EQ. This routine returns least used
1329 * EQ to associate with CQ. This will distributes the interrupt
1330 * processing and CPU load to associated EQ, vector and so to that CPU.
1331 */
1332 static u16 ocrdma_bind_eq(struct ocrdma_dev *dev)
1333 {
1334 int i, selected_eq = 0, cq_cnt = 0;
1335 u16 eq_id;
1336
1337 mutex_lock(&dev->dev_lock);
1338 cq_cnt = dev->eq_tbl[0].cq_cnt;
1339 eq_id = dev->eq_tbl[0].q.id;
1340 /* find the EQ which is has the least number of
1341 * CQs associated with it.
1342 */
1343 for (i = 0; i < dev->eq_cnt; i++) {
1344 if (dev->eq_tbl[i].cq_cnt < cq_cnt) {
1345 cq_cnt = dev->eq_tbl[i].cq_cnt;
1346 eq_id = dev->eq_tbl[i].q.id;
1347 selected_eq = i;
1348 }
1349 }
1350 dev->eq_tbl[selected_eq].cq_cnt += 1;
1351 mutex_unlock(&dev->dev_lock);
1352 return eq_id;
1353 }
1354
1355 static void ocrdma_unbind_eq(struct ocrdma_dev *dev, u16 eq_id)
1356 {
1357 int i;
1358
1359 mutex_lock(&dev->dev_lock);
1360 for (i = 0; i < dev->eq_cnt; i++) {
1361 if (dev->eq_tbl[i].q.id != eq_id)
1362 continue;
1363 dev->eq_tbl[i].cq_cnt -= 1;
1364 break;
1365 }
1366 mutex_unlock(&dev->dev_lock);
1367 }
1368
1369 int ocrdma_mbx_create_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
1370 int entries, int dpp_cq, u16 pd_id)
1371 {
1372 int status = -ENOMEM; int max_hw_cqe;
1373 struct pci_dev *pdev = dev->nic_info.pdev;
1374 struct ocrdma_create_cq *cmd;
1375 struct ocrdma_create_cq_rsp *rsp;
1376 u32 hw_pages, cqe_size, page_size, cqe_count;
1377
1378 if (entries > dev->attr.max_cqe) {
1379 pr_err("%s(%d) max_cqe=0x%x, requester_cqe=0x%x\n",
1380 __func__, dev->id, dev->attr.max_cqe, entries);
1381 return -EINVAL;
1382 }
1383 if (dpp_cq && (dev->nic_info.dev_family != OCRDMA_GEN2_FAMILY))
1384 return -EINVAL;
1385
1386 if (dpp_cq) {
1387 cq->max_hw_cqe = 1;
1388 max_hw_cqe = 1;
1389 cqe_size = OCRDMA_DPP_CQE_SIZE;
1390 hw_pages = 1;
1391 } else {
1392 cq->max_hw_cqe = dev->attr.max_cqe;
1393 max_hw_cqe = dev->attr.max_cqe;
1394 cqe_size = sizeof(struct ocrdma_cqe);
1395 hw_pages = OCRDMA_CREATE_CQ_MAX_PAGES;
1396 }
1397
1398 cq->len = roundup(max_hw_cqe * cqe_size, OCRDMA_MIN_Q_PAGE_SIZE);
1399
1400 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_CQ, sizeof(*cmd));
1401 if (!cmd)
1402 return -ENOMEM;
1403 ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_CREATE_CQ,
1404 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1405 cq->va = dma_alloc_coherent(&pdev->dev, cq->len, &cq->pa, GFP_KERNEL);
1406 if (!cq->va) {
1407 status = -ENOMEM;
1408 goto mem_err;
1409 }
1410 memset(cq->va, 0, cq->len);
1411 page_size = cq->len / hw_pages;
1412 cmd->cmd.pgsz_pgcnt = (page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1413 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
1414 cmd->cmd.pgsz_pgcnt |= hw_pages;
1415 cmd->cmd.ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1416
1417 cq->eqn = ocrdma_bind_eq(dev);
1418 cmd->cmd.req.rsvd_version = OCRDMA_CREATE_CQ_VER3;
1419 cqe_count = cq->len / cqe_size;
1420 if (cqe_count > 1024) {
1421 /* Set cnt to 3 to indicate more than 1024 cq entries */
1422 cmd->cmd.ev_cnt_flags |= (0x3 << OCRDMA_CREATE_CQ_CNT_SHIFT);
1423 } else {
1424 u8 count = 0;
1425 switch (cqe_count) {
1426 case 256:
1427 count = 0;
1428 break;
1429 case 512:
1430 count = 1;
1431 break;
1432 case 1024:
1433 count = 2;
1434 break;
1435 default:
1436 goto mbx_err;
1437 }
1438 cmd->cmd.ev_cnt_flags |= (count << OCRDMA_CREATE_CQ_CNT_SHIFT);
1439 }
1440 /* shared eq between all the consumer cqs. */
1441 cmd->cmd.eqn = cq->eqn;
1442 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY) {
1443 if (dpp_cq)
1444 cmd->cmd.pgsz_pgcnt |= OCRDMA_CREATE_CQ_DPP <<
1445 OCRDMA_CREATE_CQ_TYPE_SHIFT;
1446 cq->phase_change = false;
1447 cmd->cmd.cqe_count = (cq->len / cqe_size);
1448 } else {
1449 cmd->cmd.cqe_count = (cq->len / cqe_size) - 1;
1450 cmd->cmd.ev_cnt_flags |= OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID;
1451 cq->phase_change = true;
1452 }
1453
1454 cmd->cmd.pd_id = pd_id; /* valid only for v3 */
1455 ocrdma_build_q_pages(&cmd->cmd.pa[0], hw_pages, cq->pa, page_size);
1456 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1457 if (status)
1458 goto mbx_err;
1459
1460 rsp = (struct ocrdma_create_cq_rsp *)cmd;
1461 cq->id = (u16) (rsp->rsp.cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
1462 kfree(cmd);
1463 return 0;
1464 mbx_err:
1465 ocrdma_unbind_eq(dev, cq->eqn);
1466 dma_free_coherent(&pdev->dev, cq->len, cq->va, cq->pa);
1467 mem_err:
1468 kfree(cmd);
1469 return status;
1470 }
1471
1472 int ocrdma_mbx_destroy_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq)
1473 {
1474 int status = -ENOMEM;
1475 struct ocrdma_destroy_cq *cmd;
1476
1477 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_CQ, sizeof(*cmd));
1478 if (!cmd)
1479 return status;
1480 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_DELETE_CQ,
1481 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1482
1483 cmd->bypass_flush_qid |=
1484 (cq->id << OCRDMA_DESTROY_CQ_QID_SHIFT) &
1485 OCRDMA_DESTROY_CQ_QID_MASK;
1486
1487 ocrdma_unbind_eq(dev, cq->eqn);
1488 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1489 if (status)
1490 goto mbx_err;
1491 dma_free_coherent(&dev->nic_info.pdev->dev, cq->len, cq->va, cq->pa);
1492 mbx_err:
1493 kfree(cmd);
1494 return status;
1495 }
1496
1497 int ocrdma_mbx_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1498 u32 pdid, int addr_check)
1499 {
1500 int status = -ENOMEM;
1501 struct ocrdma_alloc_lkey *cmd;
1502 struct ocrdma_alloc_lkey_rsp *rsp;
1503
1504 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_LKEY, sizeof(*cmd));
1505 if (!cmd)
1506 return status;
1507 cmd->pdid = pdid;
1508 cmd->pbl_sz_flags |= addr_check;
1509 cmd->pbl_sz_flags |= (hwmr->fr_mr << OCRDMA_ALLOC_LKEY_FMR_SHIFT);
1510 cmd->pbl_sz_flags |=
1511 (hwmr->remote_wr << OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT);
1512 cmd->pbl_sz_flags |=
1513 (hwmr->remote_rd << OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT);
1514 cmd->pbl_sz_flags |=
1515 (hwmr->local_wr << OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT);
1516 cmd->pbl_sz_flags |=
1517 (hwmr->remote_atomic << OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT);
1518 cmd->pbl_sz_flags |=
1519 (hwmr->num_pbls << OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT);
1520
1521 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1522 if (status)
1523 goto mbx_err;
1524 rsp = (struct ocrdma_alloc_lkey_rsp *)cmd;
1525 hwmr->lkey = rsp->lrkey;
1526 mbx_err:
1527 kfree(cmd);
1528 return status;
1529 }
1530
1531 int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey)
1532 {
1533 int status = -ENOMEM;
1534 struct ocrdma_dealloc_lkey *cmd;
1535
1536 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd));
1537 if (!cmd)
1538 return -ENOMEM;
1539 cmd->lkey = lkey;
1540 cmd->rsvd_frmr = fr_mr ? 1 : 0;
1541 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1542 if (status)
1543 goto mbx_err;
1544 mbx_err:
1545 kfree(cmd);
1546 return status;
1547 }
1548
1549 static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1550 u32 pdid, u32 pbl_cnt, u32 pbe_size, u32 last)
1551 {
1552 int status = -ENOMEM;
1553 int i;
1554 struct ocrdma_reg_nsmr *cmd;
1555 struct ocrdma_reg_nsmr_rsp *rsp;
1556
1557 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR, sizeof(*cmd));
1558 if (!cmd)
1559 return -ENOMEM;
1560 cmd->num_pbl_pdid =
1561 pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT);
1562 cmd->fr_mr = hwmr->fr_mr;
1563
1564 cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr <<
1565 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT);
1566 cmd->flags_hpage_pbe_sz |= (hwmr->remote_rd <<
1567 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT);
1568 cmd->flags_hpage_pbe_sz |= (hwmr->local_wr <<
1569 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT);
1570 cmd->flags_hpage_pbe_sz |= (hwmr->remote_atomic <<
1571 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT);
1572 cmd->flags_hpage_pbe_sz |= (hwmr->mw_bind <<
1573 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT);
1574 cmd->flags_hpage_pbe_sz |= (last << OCRDMA_REG_NSMR_LAST_SHIFT);
1575
1576 cmd->flags_hpage_pbe_sz |= (hwmr->pbe_size / OCRDMA_MIN_HPAGE_SIZE);
1577 cmd->flags_hpage_pbe_sz |= (hwmr->pbl_size / OCRDMA_MIN_HPAGE_SIZE) <<
1578 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT;
1579 cmd->totlen_low = hwmr->len;
1580 cmd->totlen_high = upper_32_bits(hwmr->len);
1581 cmd->fbo_low = (u32) (hwmr->fbo & 0xffffffff);
1582 cmd->fbo_high = (u32) upper_32_bits(hwmr->fbo);
1583 cmd->va_loaddr = (u32) hwmr->va;
1584 cmd->va_hiaddr = (u32) upper_32_bits(hwmr->va);
1585
1586 for (i = 0; i < pbl_cnt; i++) {
1587 cmd->pbl[i].lo = (u32) (hwmr->pbl_table[i].pa & 0xffffffff);
1588 cmd->pbl[i].hi = upper_32_bits(hwmr->pbl_table[i].pa);
1589 }
1590 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1591 if (status)
1592 goto mbx_err;
1593 rsp = (struct ocrdma_reg_nsmr_rsp *)cmd;
1594 hwmr->lkey = rsp->lrkey;
1595 mbx_err:
1596 kfree(cmd);
1597 return status;
1598 }
1599
1600 static int ocrdma_mbx_reg_mr_cont(struct ocrdma_dev *dev,
1601 struct ocrdma_hw_mr *hwmr, u32 pbl_cnt,
1602 u32 pbl_offset, u32 last)
1603 {
1604 int status = -ENOMEM;
1605 int i;
1606 struct ocrdma_reg_nsmr_cont *cmd;
1607
1608 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR_CONT, sizeof(*cmd));
1609 if (!cmd)
1610 return -ENOMEM;
1611 cmd->lrkey = hwmr->lkey;
1612 cmd->num_pbl_offset = (pbl_cnt << OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT) |
1613 (pbl_offset & OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK);
1614 cmd->last = last << OCRDMA_REG_NSMR_CONT_LAST_SHIFT;
1615
1616 for (i = 0; i < pbl_cnt; i++) {
1617 cmd->pbl[i].lo =
1618 (u32) (hwmr->pbl_table[i + pbl_offset].pa & 0xffffffff);
1619 cmd->pbl[i].hi =
1620 upper_32_bits(hwmr->pbl_table[i + pbl_offset].pa);
1621 }
1622 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1623 if (status)
1624 goto mbx_err;
1625 mbx_err:
1626 kfree(cmd);
1627 return status;
1628 }
1629
1630 int ocrdma_reg_mr(struct ocrdma_dev *dev,
1631 struct ocrdma_hw_mr *hwmr, u32 pdid, int acc)
1632 {
1633 int status;
1634 u32 last = 0;
1635 u32 cur_pbl_cnt, pbl_offset;
1636 u32 pending_pbl_cnt = hwmr->num_pbls;
1637
1638 pbl_offset = 0;
1639 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1640 if (cur_pbl_cnt == pending_pbl_cnt)
1641 last = 1;
1642
1643 status = ocrdma_mbx_reg_mr(dev, hwmr, pdid,
1644 cur_pbl_cnt, hwmr->pbe_size, last);
1645 if (status) {
1646 pr_err("%s() status=%d\n", __func__, status);
1647 return status;
1648 }
1649 /* if there is no more pbls to register then exit. */
1650 if (last)
1651 return 0;
1652
1653 while (!last) {
1654 pbl_offset += cur_pbl_cnt;
1655 pending_pbl_cnt -= cur_pbl_cnt;
1656 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1657 /* if we reach the end of the pbls, then need to set the last
1658 * bit, indicating no more pbls to register for this memory key.
1659 */
1660 if (cur_pbl_cnt == pending_pbl_cnt)
1661 last = 1;
1662
1663 status = ocrdma_mbx_reg_mr_cont(dev, hwmr, cur_pbl_cnt,
1664 pbl_offset, last);
1665 if (status)
1666 break;
1667 }
1668 if (status)
1669 pr_err("%s() err. status=%d\n", __func__, status);
1670
1671 return status;
1672 }
1673
1674 bool ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1675 {
1676 struct ocrdma_qp *tmp;
1677 bool found = false;
1678 list_for_each_entry(tmp, &cq->sq_head, sq_entry) {
1679 if (qp == tmp) {
1680 found = true;
1681 break;
1682 }
1683 }
1684 return found;
1685 }
1686
1687 bool ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1688 {
1689 struct ocrdma_qp *tmp;
1690 bool found = false;
1691 list_for_each_entry(tmp, &cq->rq_head, rq_entry) {
1692 if (qp == tmp) {
1693 found = true;
1694 break;
1695 }
1696 }
1697 return found;
1698 }
1699
1700 void ocrdma_flush_qp(struct ocrdma_qp *qp)
1701 {
1702 bool found;
1703 unsigned long flags;
1704
1705 spin_lock_irqsave(&qp->dev->flush_q_lock, flags);
1706 found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
1707 if (!found)
1708 list_add_tail(&qp->sq_entry, &qp->sq_cq->sq_head);
1709 if (!qp->srq) {
1710 found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
1711 if (!found)
1712 list_add_tail(&qp->rq_entry, &qp->rq_cq->rq_head);
1713 }
1714 spin_unlock_irqrestore(&qp->dev->flush_q_lock, flags);
1715 }
1716
1717 static void ocrdma_init_hwq_ptr(struct ocrdma_qp *qp)
1718 {
1719 qp->sq.head = 0;
1720 qp->sq.tail = 0;
1721 qp->rq.head = 0;
1722 qp->rq.tail = 0;
1723 }
1724
1725 int ocrdma_qp_state_change(struct ocrdma_qp *qp, enum ib_qp_state new_ib_state,
1726 enum ib_qp_state *old_ib_state)
1727 {
1728 unsigned long flags;
1729 int status = 0;
1730 enum ocrdma_qp_state new_state;
1731 new_state = get_ocrdma_qp_state(new_ib_state);
1732
1733 /* sync with wqe and rqe posting */
1734 spin_lock_irqsave(&qp->q_lock, flags);
1735
1736 if (old_ib_state)
1737 *old_ib_state = get_ibqp_state(qp->state);
1738 if (new_state == qp->state) {
1739 spin_unlock_irqrestore(&qp->q_lock, flags);
1740 return 1;
1741 }
1742
1743
1744 if (new_state == OCRDMA_QPS_INIT) {
1745 ocrdma_init_hwq_ptr(qp);
1746 ocrdma_del_flush_qp(qp);
1747 } else if (new_state == OCRDMA_QPS_ERR) {
1748 ocrdma_flush_qp(qp);
1749 }
1750
1751 qp->state = new_state;
1752
1753 spin_unlock_irqrestore(&qp->q_lock, flags);
1754 return status;
1755 }
1756
1757 static u32 ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp *qp)
1758 {
1759 u32 flags = 0;
1760 if (qp->cap_flags & OCRDMA_QP_INB_RD)
1761 flags |= OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK;
1762 if (qp->cap_flags & OCRDMA_QP_INB_WR)
1763 flags |= OCRDMA_CREATE_QP_REQ_INB_WREN_MASK;
1764 if (qp->cap_flags & OCRDMA_QP_MW_BIND)
1765 flags |= OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK;
1766 if (qp->cap_flags & OCRDMA_QP_LKEY0)
1767 flags |= OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK;
1768 if (qp->cap_flags & OCRDMA_QP_FAST_REG)
1769 flags |= OCRDMA_CREATE_QP_REQ_FMR_EN_MASK;
1770 return flags;
1771 }
1772
1773 static int ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req *cmd,
1774 struct ib_qp_init_attr *attrs,
1775 struct ocrdma_qp *qp)
1776 {
1777 int status;
1778 u32 len, hw_pages, hw_page_size;
1779 dma_addr_t pa;
1780 struct ocrdma_dev *dev = qp->dev;
1781 struct pci_dev *pdev = dev->nic_info.pdev;
1782 u32 max_wqe_allocated;
1783 u32 max_sges = attrs->cap.max_send_sge;
1784
1785 /* QP1 may exceed 127 */
1786 max_wqe_allocated = min_t(u32, attrs->cap.max_send_wr + 1,
1787 dev->attr.max_wqe);
1788
1789 status = ocrdma_build_q_conf(&max_wqe_allocated,
1790 dev->attr.wqe_size, &hw_pages, &hw_page_size);
1791 if (status) {
1792 pr_err("%s() req. max_send_wr=0x%x\n", __func__,
1793 max_wqe_allocated);
1794 return -EINVAL;
1795 }
1796 qp->sq.max_cnt = max_wqe_allocated;
1797 len = (hw_pages * hw_page_size);
1798
1799 qp->sq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
1800 if (!qp->sq.va)
1801 return -EINVAL;
1802 memset(qp->sq.va, 0, len);
1803 qp->sq.len = len;
1804 qp->sq.pa = pa;
1805 qp->sq.entry_size = dev->attr.wqe_size;
1806 ocrdma_build_q_pages(&cmd->wq_addr[0], hw_pages, pa, hw_page_size);
1807
1808 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
1809 << OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT);
1810 cmd->num_wq_rq_pages |= (hw_pages <<
1811 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT) &
1812 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK;
1813 cmd->max_sge_send_write |= (max_sges <<
1814 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT) &
1815 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK;
1816 cmd->max_sge_send_write |= (max_sges <<
1817 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT) &
1818 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK;
1819 cmd->max_wqe_rqe |= (ilog2(qp->sq.max_cnt) <<
1820 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT) &
1821 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK;
1822 cmd->wqe_rqe_size |= (dev->attr.wqe_size <<
1823 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT) &
1824 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK;
1825 return 0;
1826 }
1827
1828 static int ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req *cmd,
1829 struct ib_qp_init_attr *attrs,
1830 struct ocrdma_qp *qp)
1831 {
1832 int status;
1833 u32 len, hw_pages, hw_page_size;
1834 dma_addr_t pa = 0;
1835 struct ocrdma_dev *dev = qp->dev;
1836 struct pci_dev *pdev = dev->nic_info.pdev;
1837 u32 max_rqe_allocated = attrs->cap.max_recv_wr + 1;
1838
1839 status = ocrdma_build_q_conf(&max_rqe_allocated, dev->attr.rqe_size,
1840 &hw_pages, &hw_page_size);
1841 if (status) {
1842 pr_err("%s() req. max_recv_wr=0x%x\n", __func__,
1843 attrs->cap.max_recv_wr + 1);
1844 return status;
1845 }
1846 qp->rq.max_cnt = max_rqe_allocated;
1847 len = (hw_pages * hw_page_size);
1848
1849 qp->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
1850 if (!qp->rq.va)
1851 return -ENOMEM;
1852 memset(qp->rq.va, 0, len);
1853 qp->rq.pa = pa;
1854 qp->rq.len = len;
1855 qp->rq.entry_size = dev->attr.rqe_size;
1856
1857 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
1858 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1859 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT);
1860 cmd->num_wq_rq_pages |=
1861 (hw_pages << OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT) &
1862 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK;
1863 cmd->max_sge_recv_flags |= (attrs->cap.max_recv_sge <<
1864 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT) &
1865 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK;
1866 cmd->max_wqe_rqe |= (ilog2(qp->rq.max_cnt) <<
1867 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT) &
1868 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK;
1869 cmd->wqe_rqe_size |= (dev->attr.rqe_size <<
1870 OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT) &
1871 OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK;
1872 return 0;
1873 }
1874
1875 static void ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req *cmd,
1876 struct ocrdma_pd *pd,
1877 struct ocrdma_qp *qp,
1878 u8 enable_dpp_cq, u16 dpp_cq_id)
1879 {
1880 pd->num_dpp_qp--;
1881 qp->dpp_enabled = true;
1882 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
1883 if (!enable_dpp_cq)
1884 return;
1885 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
1886 cmd->dpp_credits_cqid = dpp_cq_id;
1887 cmd->dpp_credits_cqid |= OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT <<
1888 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT;
1889 }
1890
1891 static int ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req *cmd,
1892 struct ocrdma_qp *qp)
1893 {
1894 struct ocrdma_dev *dev = qp->dev;
1895 struct pci_dev *pdev = dev->nic_info.pdev;
1896 dma_addr_t pa = 0;
1897 int ird_page_size = dev->attr.ird_page_size;
1898 int ird_q_len = dev->attr.num_ird_pages * ird_page_size;
1899 struct ocrdma_hdr_wqe *rqe;
1900 int i = 0;
1901
1902 if (dev->attr.ird == 0)
1903 return 0;
1904
1905 qp->ird_q_va = dma_alloc_coherent(&pdev->dev, ird_q_len,
1906 &pa, GFP_KERNEL);
1907 if (!qp->ird_q_va)
1908 return -ENOMEM;
1909 memset(qp->ird_q_va, 0, ird_q_len);
1910 ocrdma_build_q_pages(&cmd->ird_addr[0], dev->attr.num_ird_pages,
1911 pa, ird_page_size);
1912 for (; i < ird_q_len / dev->attr.rqe_size; i++) {
1913 rqe = (struct ocrdma_hdr_wqe *)(qp->ird_q_va +
1914 (i * dev->attr.rqe_size));
1915 rqe->cw = 0;
1916 rqe->cw |= 2;
1917 rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
1918 rqe->cw |= (8 << OCRDMA_WQE_SIZE_SHIFT);
1919 rqe->cw |= (8 << OCRDMA_WQE_NXT_WQE_SIZE_SHIFT);
1920 }
1921 return 0;
1922 }
1923
1924 static void ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp *rsp,
1925 struct ocrdma_qp *qp,
1926 struct ib_qp_init_attr *attrs,
1927 u16 *dpp_offset, u16 *dpp_credit_lmt)
1928 {
1929 u32 max_wqe_allocated, max_rqe_allocated;
1930 qp->id = rsp->qp_id & OCRDMA_CREATE_QP_RSP_QP_ID_MASK;
1931 qp->rq.dbid = rsp->sq_rq_id & OCRDMA_CREATE_QP_RSP_RQ_ID_MASK;
1932 qp->sq.dbid = rsp->sq_rq_id >> OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT;
1933 qp->max_ird = rsp->max_ord_ird & OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK;
1934 qp->max_ord = (rsp->max_ord_ird >> OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT);
1935 qp->dpp_enabled = false;
1936 if (rsp->dpp_response & OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK) {
1937 qp->dpp_enabled = true;
1938 *dpp_credit_lmt = (rsp->dpp_response &
1939 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK) >>
1940 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT;
1941 *dpp_offset = (rsp->dpp_response &
1942 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK) >>
1943 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT;
1944 }
1945 max_wqe_allocated =
1946 rsp->max_wqe_rqe >> OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT;
1947 max_wqe_allocated = 1 << max_wqe_allocated;
1948 max_rqe_allocated = 1 << ((u16)rsp->max_wqe_rqe);
1949
1950 qp->sq.max_cnt = max_wqe_allocated;
1951 qp->sq.max_wqe_idx = max_wqe_allocated - 1;
1952
1953 if (!attrs->srq) {
1954 qp->rq.max_cnt = max_rqe_allocated;
1955 qp->rq.max_wqe_idx = max_rqe_allocated - 1;
1956 }
1957 }
1958
1959 int ocrdma_mbx_create_qp(struct ocrdma_qp *qp, struct ib_qp_init_attr *attrs,
1960 u8 enable_dpp_cq, u16 dpp_cq_id, u16 *dpp_offset,
1961 u16 *dpp_credit_lmt)
1962 {
1963 int status = -ENOMEM;
1964 u32 flags = 0;
1965 struct ocrdma_dev *dev = qp->dev;
1966 struct ocrdma_pd *pd = qp->pd;
1967 struct pci_dev *pdev = dev->nic_info.pdev;
1968 struct ocrdma_cq *cq;
1969 struct ocrdma_create_qp_req *cmd;
1970 struct ocrdma_create_qp_rsp *rsp;
1971 int qptype;
1972
1973 switch (attrs->qp_type) {
1974 case IB_QPT_GSI:
1975 qptype = OCRDMA_QPT_GSI;
1976 break;
1977 case IB_QPT_RC:
1978 qptype = OCRDMA_QPT_RC;
1979 break;
1980 case IB_QPT_UD:
1981 qptype = OCRDMA_QPT_UD;
1982 break;
1983 default:
1984 return -EINVAL;
1985 }
1986
1987 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_QP, sizeof(*cmd));
1988 if (!cmd)
1989 return status;
1990 cmd->type_pgsz_pdn |= (qptype << OCRDMA_CREATE_QP_REQ_QPT_SHIFT) &
1991 OCRDMA_CREATE_QP_REQ_QPT_MASK;
1992 status = ocrdma_set_create_qp_sq_cmd(cmd, attrs, qp);
1993 if (status)
1994 goto sq_err;
1995
1996 if (attrs->srq) {
1997 struct ocrdma_srq *srq = get_ocrdma_srq(attrs->srq);
1998 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK;
1999 cmd->rq_addr[0].lo = srq->id;
2000 qp->srq = srq;
2001 } else {
2002 status = ocrdma_set_create_qp_rq_cmd(cmd, attrs, qp);
2003 if (status)
2004 goto rq_err;
2005 }
2006
2007 status = ocrdma_set_create_qp_ird_cmd(cmd, qp);
2008 if (status)
2009 goto mbx_err;
2010
2011 cmd->type_pgsz_pdn |= (pd->id << OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT) &
2012 OCRDMA_CREATE_QP_REQ_PD_ID_MASK;
2013
2014 flags = ocrdma_set_create_qp_mbx_access_flags(qp);
2015
2016 cmd->max_sge_recv_flags |= flags;
2017 cmd->max_ord_ird |= (dev->attr.max_ord_per_qp <<
2018 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT) &
2019 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK;
2020 cmd->max_ord_ird |= (dev->attr.max_ird_per_qp <<
2021 OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT) &
2022 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK;
2023 cq = get_ocrdma_cq(attrs->send_cq);
2024 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT) &
2025 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK;
2026 qp->sq_cq = cq;
2027 cq = get_ocrdma_cq(attrs->recv_cq);
2028 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT) &
2029 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK;
2030 qp->rq_cq = cq;
2031
2032 if (pd->dpp_enabled && attrs->cap.max_inline_data && pd->num_dpp_qp &&
2033 (attrs->cap.max_inline_data <= dev->attr.max_inline_data)) {
2034 ocrdma_set_create_qp_dpp_cmd(cmd, pd, qp, enable_dpp_cq,
2035 dpp_cq_id);
2036 }
2037
2038 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2039 if (status)
2040 goto mbx_err;
2041 rsp = (struct ocrdma_create_qp_rsp *)cmd;
2042 ocrdma_get_create_qp_rsp(rsp, qp, attrs, dpp_offset, dpp_credit_lmt);
2043 qp->state = OCRDMA_QPS_RST;
2044 kfree(cmd);
2045 return 0;
2046 mbx_err:
2047 if (qp->rq.va)
2048 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2049 rq_err:
2050 pr_err("%s(%d) rq_err\n", __func__, dev->id);
2051 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2052 sq_err:
2053 pr_err("%s(%d) sq_err\n", __func__, dev->id);
2054 kfree(cmd);
2055 return status;
2056 }
2057
2058 int ocrdma_mbx_query_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2059 struct ocrdma_qp_params *param)
2060 {
2061 int status = -ENOMEM;
2062 struct ocrdma_query_qp *cmd;
2063 struct ocrdma_query_qp_rsp *rsp;
2064
2065 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_QP, sizeof(*cmd));
2066 if (!cmd)
2067 return status;
2068 cmd->qp_id = qp->id;
2069 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2070 if (status)
2071 goto mbx_err;
2072 rsp = (struct ocrdma_query_qp_rsp *)cmd;
2073 memcpy(param, &rsp->params, sizeof(struct ocrdma_qp_params));
2074 mbx_err:
2075 kfree(cmd);
2076 return status;
2077 }
2078
2079 static int ocrdma_set_av_params(struct ocrdma_qp *qp,
2080 struct ocrdma_modify_qp *cmd,
2081 struct ib_qp_attr *attrs)
2082 {
2083 int status;
2084 struct ib_ah_attr *ah_attr = &attrs->ah_attr;
2085 union ib_gid sgid, zgid;
2086 u32 vlan_id;
2087 u8 mac_addr[6];
2088
2089 if ((ah_attr->ah_flags & IB_AH_GRH) == 0)
2090 return -EINVAL;
2091 cmd->params.tclass_sq_psn |=
2092 (ah_attr->grh.traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT);
2093 cmd->params.rnt_rc_sl_fl |=
2094 (ah_attr->grh.flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK);
2095 cmd->params.rnt_rc_sl_fl |= (ah_attr->sl << OCRDMA_QP_PARAMS_SL_SHIFT);
2096 cmd->params.hop_lmt_rq_psn |=
2097 (ah_attr->grh.hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT);
2098 cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID;
2099 memcpy(&cmd->params.dgid[0], &ah_attr->grh.dgid.raw[0],
2100 sizeof(cmd->params.dgid));
2101 status = ocrdma_query_gid(&qp->dev->ibdev, 1,
2102 ah_attr->grh.sgid_index, &sgid);
2103 if (status)
2104 return status;
2105
2106 memset(&zgid, 0, sizeof(zgid));
2107 if (!memcmp(&sgid, &zgid, sizeof(zgid)))
2108 return -EINVAL;
2109
2110 qp->sgid_idx = ah_attr->grh.sgid_index;
2111 memcpy(&cmd->params.sgid[0], &sgid.raw[0], sizeof(cmd->params.sgid));
2112 ocrdma_resolve_dmac(qp->dev, ah_attr, &mac_addr[0]);
2113 cmd->params.dmac_b0_to_b3 = mac_addr[0] | (mac_addr[1] << 8) |
2114 (mac_addr[2] << 16) | (mac_addr[3] << 24);
2115 /* convert them to LE format. */
2116 ocrdma_cpu_to_le32(&cmd->params.dgid[0], sizeof(cmd->params.dgid));
2117 ocrdma_cpu_to_le32(&cmd->params.sgid[0], sizeof(cmd->params.sgid));
2118 cmd->params.vlan_dmac_b4_to_b5 = mac_addr[4] | (mac_addr[5] << 8);
2119 vlan_id = ah_attr->vlan_id;
2120 if (vlan_id && (vlan_id < 0x1000)) {
2121 cmd->params.vlan_dmac_b4_to_b5 |=
2122 vlan_id << OCRDMA_QP_PARAMS_VLAN_SHIFT;
2123 cmd->flags |= OCRDMA_QP_PARA_VLAN_EN_VALID;
2124 }
2125 return 0;
2126 }
2127
2128 static int ocrdma_set_qp_params(struct ocrdma_qp *qp,
2129 struct ocrdma_modify_qp *cmd,
2130 struct ib_qp_attr *attrs, int attr_mask)
2131 {
2132 int status = 0;
2133
2134 if (attr_mask & IB_QP_PKEY_INDEX) {
2135 cmd->params.path_mtu_pkey_indx |= (attrs->pkey_index &
2136 OCRDMA_QP_PARAMS_PKEY_INDEX_MASK);
2137 cmd->flags |= OCRDMA_QP_PARA_PKEY_VALID;
2138 }
2139 if (attr_mask & IB_QP_QKEY) {
2140 qp->qkey = attrs->qkey;
2141 cmd->params.qkey = attrs->qkey;
2142 cmd->flags |= OCRDMA_QP_PARA_QKEY_VALID;
2143 }
2144 if (attr_mask & IB_QP_AV) {
2145 status = ocrdma_set_av_params(qp, cmd, attrs);
2146 if (status)
2147 return status;
2148 } else if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_UD) {
2149 /* set the default mac address for UD, GSI QPs */
2150 cmd->params.dmac_b0_to_b3 = qp->dev->nic_info.mac_addr[0] |
2151 (qp->dev->nic_info.mac_addr[1] << 8) |
2152 (qp->dev->nic_info.mac_addr[2] << 16) |
2153 (qp->dev->nic_info.mac_addr[3] << 24);
2154 cmd->params.vlan_dmac_b4_to_b5 = qp->dev->nic_info.mac_addr[4] |
2155 (qp->dev->nic_info.mac_addr[5] << 8);
2156 }
2157 if ((attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) &&
2158 attrs->en_sqd_async_notify) {
2159 cmd->params.max_sge_recv_flags |=
2160 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC;
2161 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2162 }
2163 if (attr_mask & IB_QP_DEST_QPN) {
2164 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->dest_qp_num &
2165 OCRDMA_QP_PARAMS_DEST_QPN_MASK);
2166 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2167 }
2168 if (attr_mask & IB_QP_PATH_MTU) {
2169 if (attrs->path_mtu < IB_MTU_256 ||
2170 attrs->path_mtu > IB_MTU_4096) {
2171 status = -EINVAL;
2172 goto pmtu_err;
2173 }
2174 cmd->params.path_mtu_pkey_indx |=
2175 (ib_mtu_enum_to_int(attrs->path_mtu) <<
2176 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT) &
2177 OCRDMA_QP_PARAMS_PATH_MTU_MASK;
2178 cmd->flags |= OCRDMA_QP_PARA_PMTU_VALID;
2179 }
2180 if (attr_mask & IB_QP_TIMEOUT) {
2181 cmd->params.ack_to_rnr_rtc_dest_qpn |= attrs->timeout <<
2182 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
2183 cmd->flags |= OCRDMA_QP_PARA_ACK_TO_VALID;
2184 }
2185 if (attr_mask & IB_QP_RETRY_CNT) {
2186 cmd->params.rnt_rc_sl_fl |= (attrs->retry_cnt <<
2187 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT) &
2188 OCRDMA_QP_PARAMS_RETRY_CNT_MASK;
2189 cmd->flags |= OCRDMA_QP_PARA_RETRY_CNT_VALID;
2190 }
2191 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2192 cmd->params.rnt_rc_sl_fl |= (attrs->min_rnr_timer <<
2193 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT) &
2194 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK;
2195 cmd->flags |= OCRDMA_QP_PARA_RNT_VALID;
2196 }
2197 if (attr_mask & IB_QP_RNR_RETRY) {
2198 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->rnr_retry <<
2199 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT)
2200 & OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK;
2201 cmd->flags |= OCRDMA_QP_PARA_RRC_VALID;
2202 }
2203 if (attr_mask & IB_QP_SQ_PSN) {
2204 cmd->params.tclass_sq_psn |= (attrs->sq_psn & 0x00ffffff);
2205 cmd->flags |= OCRDMA_QP_PARA_SQPSN_VALID;
2206 }
2207 if (attr_mask & IB_QP_RQ_PSN) {
2208 cmd->params.hop_lmt_rq_psn |= (attrs->rq_psn & 0x00ffffff);
2209 cmd->flags |= OCRDMA_QP_PARA_RQPSN_VALID;
2210 }
2211 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2212 if (attrs->max_rd_atomic > qp->dev->attr.max_ord_per_qp) {
2213 status = -EINVAL;
2214 goto pmtu_err;
2215 }
2216 qp->max_ord = attrs->max_rd_atomic;
2217 cmd->flags |= OCRDMA_QP_PARA_MAX_ORD_VALID;
2218 }
2219 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2220 if (attrs->max_dest_rd_atomic > qp->dev->attr.max_ird_per_qp) {
2221 status = -EINVAL;
2222 goto pmtu_err;
2223 }
2224 qp->max_ird = attrs->max_dest_rd_atomic;
2225 cmd->flags |= OCRDMA_QP_PARA_MAX_IRD_VALID;
2226 }
2227 cmd->params.max_ord_ird = (qp->max_ord <<
2228 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT) |
2229 (qp->max_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK);
2230 pmtu_err:
2231 return status;
2232 }
2233
2234 int ocrdma_mbx_modify_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2235 struct ib_qp_attr *attrs, int attr_mask)
2236 {
2237 int status = -ENOMEM;
2238 struct ocrdma_modify_qp *cmd;
2239
2240 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_QP, sizeof(*cmd));
2241 if (!cmd)
2242 return status;
2243
2244 cmd->params.id = qp->id;
2245 cmd->flags = 0;
2246 if (attr_mask & IB_QP_STATE) {
2247 cmd->params.max_sge_recv_flags |=
2248 (get_ocrdma_qp_state(attrs->qp_state) <<
2249 OCRDMA_QP_PARAMS_STATE_SHIFT) &
2250 OCRDMA_QP_PARAMS_STATE_MASK;
2251 cmd->flags |= OCRDMA_QP_PARA_QPS_VALID;
2252 } else {
2253 cmd->params.max_sge_recv_flags |=
2254 (qp->state << OCRDMA_QP_PARAMS_STATE_SHIFT) &
2255 OCRDMA_QP_PARAMS_STATE_MASK;
2256 }
2257
2258 status = ocrdma_set_qp_params(qp, cmd, attrs, attr_mask);
2259 if (status)
2260 goto mbx_err;
2261 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2262 if (status)
2263 goto mbx_err;
2264
2265 mbx_err:
2266 kfree(cmd);
2267 return status;
2268 }
2269
2270 int ocrdma_mbx_destroy_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
2271 {
2272 int status = -ENOMEM;
2273 struct ocrdma_destroy_qp *cmd;
2274 struct pci_dev *pdev = dev->nic_info.pdev;
2275
2276 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_QP, sizeof(*cmd));
2277 if (!cmd)
2278 return status;
2279 cmd->qp_id = qp->id;
2280 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2281 if (status)
2282 goto mbx_err;
2283
2284 mbx_err:
2285 kfree(cmd);
2286 if (qp->sq.va)
2287 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2288 if (!qp->srq && qp->rq.va)
2289 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2290 if (qp->dpp_enabled)
2291 qp->pd->num_dpp_qp++;
2292 return status;
2293 }
2294
2295 int ocrdma_mbx_create_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
2296 struct ib_srq_init_attr *srq_attr,
2297 struct ocrdma_pd *pd)
2298 {
2299 int status = -ENOMEM;
2300 int hw_pages, hw_page_size;
2301 int len;
2302 struct ocrdma_create_srq_rsp *rsp;
2303 struct ocrdma_create_srq *cmd;
2304 dma_addr_t pa;
2305 struct pci_dev *pdev = dev->nic_info.pdev;
2306 u32 max_rqe_allocated;
2307
2308 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2309 if (!cmd)
2310 return status;
2311
2312 cmd->pgsz_pdid = pd->id & OCRDMA_CREATE_SRQ_PD_ID_MASK;
2313 max_rqe_allocated = srq_attr->attr.max_wr + 1;
2314 status = ocrdma_build_q_conf(&max_rqe_allocated,
2315 dev->attr.rqe_size,
2316 &hw_pages, &hw_page_size);
2317 if (status) {
2318 pr_err("%s() req. max_wr=0x%x\n", __func__,
2319 srq_attr->attr.max_wr);
2320 status = -EINVAL;
2321 goto ret;
2322 }
2323 len = hw_pages * hw_page_size;
2324 srq->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2325 if (!srq->rq.va) {
2326 status = -ENOMEM;
2327 goto ret;
2328 }
2329 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2330
2331 srq->rq.entry_size = dev->attr.rqe_size;
2332 srq->rq.pa = pa;
2333 srq->rq.len = len;
2334 srq->rq.max_cnt = max_rqe_allocated;
2335
2336 cmd->max_sge_rqe = ilog2(max_rqe_allocated);
2337 cmd->max_sge_rqe |= srq_attr->attr.max_sge <<
2338 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT;
2339
2340 cmd->pgsz_pdid |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2341 << OCRDMA_CREATE_SRQ_PG_SZ_SHIFT);
2342 cmd->pages_rqe_sz |= (dev->attr.rqe_size
2343 << OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT)
2344 & OCRDMA_CREATE_SRQ_RQE_SIZE_MASK;
2345 cmd->pages_rqe_sz |= hw_pages << OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT;
2346
2347 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2348 if (status)
2349 goto mbx_err;
2350 rsp = (struct ocrdma_create_srq_rsp *)cmd;
2351 srq->id = rsp->id;
2352 srq->rq.dbid = rsp->id;
2353 max_rqe_allocated = ((rsp->max_sge_rqe_allocated &
2354 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK) >>
2355 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT);
2356 max_rqe_allocated = (1 << max_rqe_allocated);
2357 srq->rq.max_cnt = max_rqe_allocated;
2358 srq->rq.max_wqe_idx = max_rqe_allocated - 1;
2359 srq->rq.max_sges = (rsp->max_sge_rqe_allocated &
2360 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK) >>
2361 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT;
2362 goto ret;
2363 mbx_err:
2364 dma_free_coherent(&pdev->dev, srq->rq.len, srq->rq.va, pa);
2365 ret:
2366 kfree(cmd);
2367 return status;
2368 }
2369
2370 int ocrdma_mbx_modify_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2371 {
2372 int status = -ENOMEM;
2373 struct ocrdma_modify_srq *cmd;
2374 struct ocrdma_pd *pd = srq->pd;
2375 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2376
2377 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_SRQ, sizeof(*cmd));
2378 if (!cmd)
2379 return status;
2380 cmd->id = srq->id;
2381 cmd->limit_max_rqe |= srq_attr->srq_limit <<
2382 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT;
2383 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2384 kfree(cmd);
2385 return status;
2386 }
2387
2388 int ocrdma_mbx_query_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2389 {
2390 int status = -ENOMEM;
2391 struct ocrdma_query_srq *cmd;
2392 struct ocrdma_dev *dev = get_ocrdma_dev(srq->ibsrq.device);
2393
2394 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_SRQ, sizeof(*cmd));
2395 if (!cmd)
2396 return status;
2397 cmd->id = srq->rq.dbid;
2398 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2399 if (status == 0) {
2400 struct ocrdma_query_srq_rsp *rsp =
2401 (struct ocrdma_query_srq_rsp *)cmd;
2402 srq_attr->max_sge =
2403 rsp->srq_lmt_max_sge &
2404 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK;
2405 srq_attr->max_wr =
2406 rsp->max_rqe_pdid >> OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT;
2407 srq_attr->srq_limit = rsp->srq_lmt_max_sge >>
2408 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT;
2409 }
2410 kfree(cmd);
2411 return status;
2412 }
2413
2414 int ocrdma_mbx_destroy_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq)
2415 {
2416 int status = -ENOMEM;
2417 struct ocrdma_destroy_srq *cmd;
2418 struct pci_dev *pdev = dev->nic_info.pdev;
2419 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_SRQ, sizeof(*cmd));
2420 if (!cmd)
2421 return status;
2422 cmd->id = srq->id;
2423 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2424 if (srq->rq.va)
2425 dma_free_coherent(&pdev->dev, srq->rq.len,
2426 srq->rq.va, srq->rq.pa);
2427 kfree(cmd);
2428 return status;
2429 }
2430
2431 int ocrdma_alloc_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2432 {
2433 int i;
2434 int status = -EINVAL;
2435 struct ocrdma_av *av;
2436 unsigned long flags;
2437
2438 av = dev->av_tbl.va;
2439 spin_lock_irqsave(&dev->av_tbl.lock, flags);
2440 for (i = 0; i < dev->av_tbl.num_ah; i++) {
2441 if (av->valid == 0) {
2442 av->valid = OCRDMA_AV_VALID;
2443 ah->av = av;
2444 ah->id = i;
2445 status = 0;
2446 break;
2447 }
2448 av++;
2449 }
2450 if (i == dev->av_tbl.num_ah)
2451 status = -EAGAIN;
2452 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2453 return status;
2454 }
2455
2456 int ocrdma_free_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2457 {
2458 unsigned long flags;
2459 spin_lock_irqsave(&dev->av_tbl.lock, flags);
2460 ah->av->valid = 0;
2461 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2462 return 0;
2463 }
2464
2465 static int ocrdma_create_eqs(struct ocrdma_dev *dev)
2466 {
2467 int num_eq, i, status = 0;
2468 int irq;
2469 unsigned long flags = 0;
2470
2471 num_eq = dev->nic_info.msix.num_vectors -
2472 dev->nic_info.msix.start_vector;
2473 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) {
2474 num_eq = 1;
2475 flags = IRQF_SHARED;
2476 } else {
2477 num_eq = min_t(u32, num_eq, num_online_cpus());
2478 }
2479
2480 if (!num_eq)
2481 return -EINVAL;
2482
2483 dev->eq_tbl = kzalloc(sizeof(struct ocrdma_eq) * num_eq, GFP_KERNEL);
2484 if (!dev->eq_tbl)
2485 return -ENOMEM;
2486
2487 for (i = 0; i < num_eq; i++) {
2488 status = ocrdma_create_eq(dev, &dev->eq_tbl[i],
2489 OCRDMA_EQ_LEN);
2490 if (status) {
2491 status = -EINVAL;
2492 break;
2493 }
2494 sprintf(dev->eq_tbl[i].irq_name, "ocrdma%d-%d",
2495 dev->id, i);
2496 irq = ocrdma_get_irq(dev, &dev->eq_tbl[i]);
2497 status = request_irq(irq, ocrdma_irq_handler, flags,
2498 dev->eq_tbl[i].irq_name,
2499 &dev->eq_tbl[i]);
2500 if (status)
2501 goto done;
2502 dev->eq_cnt += 1;
2503 }
2504 /* one eq is sufficient for data path to work */
2505 return 0;
2506 done:
2507 ocrdma_destroy_eqs(dev);
2508 return status;
2509 }
2510
2511 int ocrdma_init_hw(struct ocrdma_dev *dev)
2512 {
2513 int status;
2514
2515 /* create the eqs */
2516 status = ocrdma_create_eqs(dev);
2517 if (status)
2518 goto qpeq_err;
2519 status = ocrdma_create_mq(dev);
2520 if (status)
2521 goto mq_err;
2522 status = ocrdma_mbx_query_fw_config(dev);
2523 if (status)
2524 goto conf_err;
2525 status = ocrdma_mbx_query_dev(dev);
2526 if (status)
2527 goto conf_err;
2528 status = ocrdma_mbx_query_fw_ver(dev);
2529 if (status)
2530 goto conf_err;
2531 status = ocrdma_mbx_create_ah_tbl(dev);
2532 if (status)
2533 goto conf_err;
2534 return 0;
2535
2536 conf_err:
2537 ocrdma_destroy_mq(dev);
2538 mq_err:
2539 ocrdma_destroy_eqs(dev);
2540 qpeq_err:
2541 pr_err("%s() status=%d\n", __func__, status);
2542 return status;
2543 }
2544
2545 void ocrdma_cleanup_hw(struct ocrdma_dev *dev)
2546 {
2547 ocrdma_mbx_delete_ah_tbl(dev);
2548
2549 /* cleanup the eqs */
2550 ocrdma_destroy_eqs(dev);
2551
2552 /* cleanup the control path */
2553 ocrdma_destroy_mq(dev);
2554 }
Linux kernel - Deliverables
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