drivers/misc/cxl/irq.c

   1 /*
   2  * Copyright 2014 IBM Corp.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9
  10 #include <linux/interrupt.h>
  11 #include <linux/workqueue.h>
  12 #include <linux/sched.h>
  13 #include <linux/wait.h>
  14 #include <linux/slab.h>
  15 #include <linux/pid.h>
  16 #include <asm/cputable.h>
  17 #include <misc/cxl-base.h>
  18
  19 #include "cxl.h"
  20 #include "trace.h"
  21
  22 static int afu_irq_range_start(void)
  23 {
  24         if (cpu_has_feature(CPU_FTR_HVMODE))
  25                 return 1;
  26         return 0;
  27 }
  28
  29 static irqreturn_t schedule_cxl_fault(struct cxl_context *ctx, u64 dsisr, u64 dar)
  30 {
  31         ctx->dsisr = dsisr;
  32         ctx->dar = dar;
  33         schedule_work(&ctx->fault_work);
  34         return IRQ_HANDLED;
  35 }
  36
  37 irqreturn_t cxl_irq(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info)
  38 {
  39         u64 dsisr, dar;
  40
  41         dsisr = irq_info->dsisr;
  42         dar = irq_info->dar;
  43
  44         trace_cxl_psl_irq(ctx, irq, dsisr, dar);
  45
  46         pr_devel("CXL interrupt %i for afu pe: %i DSISR: %#llx DAR: %#llx\n", irq, ctx->pe, dsisr, dar);
  47
  48         if (dsisr & CXL_PSL_DSISR_An_DS) {
  49                 /*
  50                  * We don't inherently need to sleep to handle this, but we do
  51                  * need to get a ref to the task's mm, which we can't do from
  52                  * irq context without the potential for a deadlock since it
  53                  * takes the task_lock. An alternate option would be to keep a
  54                  * reference to the task's mm the entire time it has cxl open,
  55                  * but to do that we need to solve the issue where we hold a
  56                  * ref to the mm, but the mm can hold a ref to the fd after an
  57                  * mmap preventing anything from being cleaned up.
  58                  */
  59                 pr_devel("Scheduling segment miss handling for later pe: %i\n", ctx->pe);
  60                 return schedule_cxl_fault(ctx, dsisr, dar);
  61         }
  62
  63         if (dsisr & CXL_PSL_DSISR_An_M)
  64                 pr_devel("CXL interrupt: PTE not found\n");
  65         if (dsisr & CXL_PSL_DSISR_An_P)
  66                 pr_devel("CXL interrupt: Storage protection violation\n");
  67         if (dsisr & CXL_PSL_DSISR_An_A)
  68                 pr_devel("CXL interrupt: AFU lock access to write through or cache inhibited storage\n");
  69         if (dsisr & CXL_PSL_DSISR_An_S)
  70                 pr_devel("CXL interrupt: Access was afu_wr or afu_zero\n");
  71         if (dsisr & CXL_PSL_DSISR_An_K)
  72                 pr_devel("CXL interrupt: Access not permitted by virtual page class key protection\n");
  73
  74         if (dsisr & CXL_PSL_DSISR_An_DM) {
  75                 /*
  76                  * In some cases we might be able to handle the fault
  77                  * immediately if hash_page would succeed, but we still need
  78                  * the task's mm, which as above we can't get without a lock
  79                  */
  80                 pr_devel("Scheduling page fault handling for later pe: %i\n", ctx->pe);
  81                 return schedule_cxl_fault(ctx, dsisr, dar);
  82         }
  83         if (dsisr & CXL_PSL_DSISR_An_ST)
  84                 WARN(1, "CXL interrupt: Segment Table PTE not found\n");
  85         if (dsisr & CXL_PSL_DSISR_An_UR)
  86                 pr_devel("CXL interrupt: AURP PTE not found\n");
  87         if (dsisr & CXL_PSL_DSISR_An_PE)
  88                 return cxl_ops->handle_psl_slice_error(ctx, dsisr,
  89                                                 irq_info->errstat);
  90         if (dsisr & CXL_PSL_DSISR_An_AE) {
  91                 pr_devel("CXL interrupt: AFU Error 0x%016llx\n", irq_info->afu_err);
  92
  93                 if (ctx->pending_afu_err) {
  94                         /*
  95                          * This shouldn't happen - the PSL treats these errors
  96                          * as fatal and will have reset the AFU, so there's not
  97                          * much point buffering multiple AFU errors.
  98                          * OTOH if we DO ever see a storm of these come in it's
  99                          * probably best that we log them somewhere:
 100                          */
 101                         dev_err_ratelimited(&ctx->afu->dev, "CXL AFU Error "
 102                                             "undelivered to pe %i: 0x%016llx\n",
 103                                             ctx->pe, irq_info->afu_err);
 104                 } else {
 105                         spin_lock(&ctx->lock);
 106                         ctx->afu_err = irq_info->afu_err;
 107                         ctx->pending_afu_err = 1;
 108                         spin_unlock(&ctx->lock);
 109
 110                         wake_up_all(&ctx->wq);
 111                 }
 112
 113                 cxl_ops->ack_irq(ctx, CXL_PSL_TFC_An_A, 0);
 114                 return IRQ_HANDLED;
 115         }
 116         if (dsisr & CXL_PSL_DSISR_An_OC)
 117                 pr_devel("CXL interrupt: OS Context Warning\n");
 118
 119         WARN(1, "Unhandled CXL PSL IRQ\n");
 120         return IRQ_HANDLED;
 121 }
 122
 123 static irqreturn_t cxl_irq_afu(int irq, void *data)
 124 {
 125         struct cxl_context *ctx = data;
 126         irq_hw_number_t hwirq = irqd_to_hwirq(irq_get_irq_data(irq));
 127         int irq_off, afu_irq = 0;
 128         __u16 range;
 129         int r;
 130
 131         /*
 132          * Look for the interrupt number.
 133          * On bare-metal, we know range 0 only contains the PSL
 134          * interrupt so we could start counting at range 1 and initialize
 135          * afu_irq at 1.
 136          * In a guest, range 0 also contains AFU interrupts, so it must
 137          * be counted for. Therefore we initialize afu_irq at 0 to take into
 138          * account the PSL interrupt.
 139          *
 140          * For code-readability, it just seems easier to go over all
 141          * the ranges on bare-metal and guest. The end result is the same.
 142          */
 143         for (r = 0; r < CXL_IRQ_RANGES; r++) {
 144                 irq_off = hwirq - ctx->irqs.offset[r];
 145                 range = ctx->irqs.range[r];
 146                 if (irq_off >= 0 && irq_off < range) {
 147                         afu_irq += irq_off;
 148                         break;
 149                 }
 150                 afu_irq += range;
 151         }
 152         if (unlikely(r >= CXL_IRQ_RANGES)) {
 153                 WARN(1, "Received AFU IRQ out of range for pe %i (virq %i hwirq %lx)\n",
 154                      ctx->pe, irq, hwirq);
 155                 return IRQ_HANDLED;
 156         }
 157
 158         trace_cxl_afu_irq(ctx, afu_irq, irq, hwirq);
 159         pr_devel("Received AFU interrupt %i for pe: %i (virq %i hwirq %lx)\n",
 160                afu_irq, ctx->pe, irq, hwirq);
 161
 162         if (unlikely(!ctx->irq_bitmap)) {
 163                 WARN(1, "Received AFU IRQ for context with no IRQ bitmap\n");
 164                 return IRQ_HANDLED;
 165         }
 166         spin_lock(&ctx->lock);
 167         set_bit(afu_irq - 1, ctx->irq_bitmap);
 168         ctx->pending_irq = true;
 169         spin_unlock(&ctx->lock);
 170
 171         wake_up_all(&ctx->wq);
 172
 173         return IRQ_HANDLED;
 174 }
 175
 176 unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq,
 177                          irq_handler_t handler, void *cookie, const char *name)
 178 {
 179         unsigned int virq;
 180         int result;
 181
 182         /* IRQ Domain? */
 183         virq = irq_create_mapping(NULL, hwirq);
 184         if (!virq) {
 185                 dev_warn(&adapter->dev, "cxl_map_irq: irq_create_mapping failed\n");
 186                 return 0;
 187         }
 188
 189         if (cxl_ops->setup_irq)
 190                 cxl_ops->setup_irq(adapter, hwirq, virq);
 191
 192         pr_devel("hwirq %#lx mapped to virq %u\n", hwirq, virq);
 193
 194         result = request_irq(virq, handler, 0, name, cookie);
 195         if (result) {
 196                 dev_warn(&adapter->dev, "cxl_map_irq: request_irq failed: %i\n", result);
 197                 return 0;
 198         }
 199
 200         return virq;
 201 }
 202
 203 void cxl_unmap_irq(unsigned int virq, void *cookie)
 204 {
 205         free_irq(virq, cookie);
 206         irq_dispose_mapping(virq);
 207 }
 208
 209 int cxl_register_one_irq(struct cxl *adapter,
 210                         irq_handler_t handler,
 211                         void *cookie,
 212                         irq_hw_number_t *dest_hwirq,
 213                         unsigned int *dest_virq,
 214                         const char *name)
 215 {
 216         int hwirq, virq;
 217
 218         if ((hwirq = cxl_ops->alloc_one_irq(adapter)) < 0)
 219                 return hwirq;
 220
 221         if (!(virq = cxl_map_irq(adapter, hwirq, handler, cookie, name)))
 222                 goto err;
 223
 224         *dest_hwirq = hwirq;
 225         *dest_virq = virq;
 226
 227         return 0;
 228
 229 err:
 230         cxl_ops->release_one_irq(adapter, hwirq);
 231         return -ENOMEM;
 232 }
 233
 234 void afu_irq_name_free(struct cxl_context *ctx)
 235 {
 236         struct cxl_irq_name *irq_name, *tmp;
 237
 238         list_for_each_entry_safe(irq_name, tmp, &ctx->irq_names, list) {
 239                 kfree(irq_name->name);
 240                 list_del(&irq_name->list);
 241                 kfree(irq_name);
 242         }
 243 }
 244
 245 int afu_allocate_irqs(struct cxl_context *ctx, u32 count)
 246 {
 247         int rc, r, i, j = 1;
 248         struct cxl_irq_name *irq_name;
 249         int alloc_count;
 250
 251         /*
 252          * In native mode, range 0 is reserved for the multiplexed
 253          * PSL interrupt. It has been allocated when the AFU was initialized.
 254          *
 255          * In a guest, the PSL interrupt is not mutliplexed, but per-context,
 256          * and is the first interrupt from range 0. It still needs to be
 257          * allocated, so bump the count by one.
 258          */
 259         if (cpu_has_feature(CPU_FTR_HVMODE))
 260                 alloc_count = count;
 261         else
 262                 alloc_count = count + 1;
 263
 264         /* Initialize the list head to hold irq names */
 265         INIT_LIST_HEAD(&ctx->irq_names);
 266
 267         if ((rc = cxl_ops->alloc_irq_ranges(&ctx->irqs, ctx->afu->adapter,
 268                                                         alloc_count)))
 269                 return rc;
 270
 271         if (cpu_has_feature(CPU_FTR_HVMODE)) {
 272                 /* Multiplexed PSL Interrupt */
 273                 ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq;
 274                 ctx->irqs.range[0] = 1;
 275         }
 276
 277         ctx->irq_count = count;
 278         ctx->irq_bitmap = kcalloc(BITS_TO_LONGS(count),
 279                                   sizeof(*ctx->irq_bitmap), GFP_KERNEL);
 280         if (!ctx->irq_bitmap)
 281                 goto out;
 282
 283         /*
 284          * Allocate names first.  If any fail, bail out before allocating
 285          * actual hardware IRQs.
 286          */
 287         for (r = afu_irq_range_start(); r < CXL_IRQ_RANGES; r++) {
 288                 for (i = 0; i < ctx->irqs.range[r]; i++) {
 289                         irq_name = kmalloc(sizeof(struct cxl_irq_name),
 290                                            GFP_KERNEL);
 291                         if (!irq_name)
 292                                 goto out;
 293                         irq_name->name = kasprintf(GFP_KERNEL, "cxl-%s-pe%i-%i",
 294                                                    dev_name(&ctx->afu->dev),
 295                                                    ctx->pe, j);
 296                         if (!irq_name->name) {
 297                                 kfree(irq_name);
 298                                 goto out;
 299                         }
 300                         /* Add to tail so next look get the correct order */
 301                         list_add_tail(&irq_name->list, &ctx->irq_names);
 302                         j++;
 303                 }
 304         }
 305         return 0;
 306
 307 out:
 308         cxl_ops->release_irq_ranges(&ctx->irqs, ctx->afu->adapter);
 309         afu_irq_name_free(ctx);
 310         return -ENOMEM;
 311 }
 312
 313 static void afu_register_hwirqs(struct cxl_context *ctx)
 314 {
 315         irq_hw_number_t hwirq;
 316         struct cxl_irq_name *irq_name;
 317         int r, i;
 318         irqreturn_t (*handler)(int irq, void *data);
 319
 320         /* We've allocated all memory now, so let's do the irq allocations */
 321         irq_name = list_first_entry(&ctx->irq_names, struct cxl_irq_name, list);
 322         for (r = afu_irq_range_start(); r < CXL_IRQ_RANGES; r++) {
 323                 hwirq = ctx->irqs.offset[r];
 324                 for (i = 0; i < ctx->irqs.range[r]; hwirq++, i++) {
 325                         if (r == 0 && i == 0)
 326                                 /*
 327                                  * The very first interrupt of range 0 is
 328                                  * always the PSL interrupt, but we only
 329                                  * need to connect a handler for guests,
 330                                  * because there's one PSL interrupt per
 331                                  * context.
 332                                  * On bare-metal, the PSL interrupt is
 333                                  * multiplexed and was setup when the AFU
 334                                  * was configured.
 335                                  */
 336                                 handler = cxl_ops->psl_interrupt;
 337                         else
 338                                 handler = cxl_irq_afu;
 339                         cxl_map_irq(ctx->afu->adapter, hwirq, handler, ctx,
 340                                 irq_name->name);
 341                         irq_name = list_next_entry(irq_name, list);
 342                 }
 343         }
 344 }
 345
 346 int afu_register_irqs(struct cxl_context *ctx, u32 count)
 347 {
 348         int rc;
 349
 350         rc = afu_allocate_irqs(ctx, count);
 351         if (rc)
 352                 return rc;
 353
 354         afu_register_hwirqs(ctx);
 355         return 0;
 356 }
 357
 358 void afu_release_irqs(struct cxl_context *ctx, void *cookie)
 359 {
 360         irq_hw_number_t hwirq;
 361         unsigned int virq;
 362         int r, i;
 363
 364         for (r = afu_irq_range_start(); r < CXL_IRQ_RANGES; r++) {
 365                 hwirq = ctx->irqs.offset[r];
 366                 for (i = 0; i < ctx->irqs.range[r]; hwirq++, i++) {
 367                         virq = irq_find_mapping(NULL, hwirq);
 368                         if (virq)
 369                                 cxl_unmap_irq(virq, cookie);
 370                 }
 371         }
 372
 373         afu_irq_name_free(ctx);
 374         cxl_ops->release_irq_ranges(&ctx->irqs, ctx->afu->adapter);
 375
 376         ctx->irq_count = 0;
 377 }