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net: bnx2x: include irq.h for irqreturn_t definitions
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_cmn.h
1 /* bnx2x_cmn.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17 #ifndef BNX2X_CMN_H
18 #define BNX2X_CMN_H
19
20 #include <linux/types.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/irq.h>
25
26 #include "bnx2x.h"
27 #include "bnx2x_sriov.h"
28
29 /* This is used as a replacement for an MCP if it's not present */
30 extern int bnx2x_load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */
31 extern int bnx2x_num_queues;
32
33 /************************ Macros ********************************/
34 #define BNX2X_PCI_FREE(x, y, size) \
35 do { \
36 if (x) { \
37 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \
38 x = NULL; \
39 y = 0; \
40 } \
41 } while (0)
42
43 #define BNX2X_FREE(x) \
44 do { \
45 if (x) { \
46 kfree((void *)x); \
47 x = NULL; \
48 } \
49 } while (0)
50
51 #define BNX2X_PCI_ALLOC(y, size) \
52 ({ \
53 void *x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
54 if (x) \
55 DP(NETIF_MSG_HW, \
56 "BNX2X_PCI_ALLOC: Physical %Lx Virtual %p\n", \
57 (unsigned long long)(*y), x); \
58 x; \
59 })
60 #define BNX2X_PCI_FALLOC(y, size) \
61 ({ \
62 void *x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
63 if (x) { \
64 memset(x, 0xff, size); \
65 DP(NETIF_MSG_HW, \
66 "BNX2X_PCI_FALLOC: Physical %Lx Virtual %p\n", \
67 (unsigned long long)(*y), x); \
68 } \
69 x; \
70 })
71
72 /*********************** Interfaces ****************************
73 * Functions that need to be implemented by each driver version
74 */
75 /* Init */
76
77 /**
78 * bnx2x_send_unload_req - request unload mode from the MCP.
79 *
80 * @bp: driver handle
81 * @unload_mode: requested function's unload mode
82 *
83 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
84 */
85 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode);
86
87 /**
88 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
89 *
90 * @bp: driver handle
91 * @keep_link: true iff link should be kept up
92 */
93 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link);
94
95 /**
96 * bnx2x_config_rss_pf - configure RSS parameters in a PF.
97 *
98 * @bp: driver handle
99 * @rss_obj: RSS object to use
100 * @ind_table: indirection table to configure
101 * @config_hash: re-configure RSS hash keys configuration
102 * @enable: enabled or disabled configuration
103 */
104 int bnx2x_rss(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
105 bool config_hash, bool enable);
106
107 /**
108 * bnx2x__init_func_obj - init function object
109 *
110 * @bp: driver handle
111 *
112 * Initializes the Function Object with the appropriate
113 * parameters which include a function slow path driver
114 * interface.
115 */
116 void bnx2x__init_func_obj(struct bnx2x *bp);
117
118 /**
119 * bnx2x_setup_queue - setup eth queue.
120 *
121 * @bp: driver handle
122 * @fp: pointer to the fastpath structure
123 * @leading: boolean
124 *
125 */
126 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
127 bool leading);
128
129 /**
130 * bnx2x_setup_leading - bring up a leading eth queue.
131 *
132 * @bp: driver handle
133 */
134 int bnx2x_setup_leading(struct bnx2x *bp);
135
136 /**
137 * bnx2x_fw_command - send the MCP a request
138 *
139 * @bp: driver handle
140 * @command: request
141 * @param: request's parameter
142 *
143 * block until there is a reply
144 */
145 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param);
146
147 /**
148 * bnx2x_initial_phy_init - initialize link parameters structure variables.
149 *
150 * @bp: driver handle
151 * @load_mode: current mode
152 */
153 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode);
154
155 /**
156 * bnx2x_link_set - configure hw according to link parameters structure.
157 *
158 * @bp: driver handle
159 */
160 void bnx2x_link_set(struct bnx2x *bp);
161
162 /**
163 * bnx2x_force_link_reset - Forces link reset, and put the PHY
164 * in reset as well.
165 *
166 * @bp: driver handle
167 */
168 void bnx2x_force_link_reset(struct bnx2x *bp);
169
170 /**
171 * bnx2x_link_test - query link status.
172 *
173 * @bp: driver handle
174 * @is_serdes: bool
175 *
176 * Returns 0 if link is UP.
177 */
178 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes);
179
180 /**
181 * bnx2x_drv_pulse - write driver pulse to shmem
182 *
183 * @bp: driver handle
184 *
185 * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox
186 * in the shmem.
187 */
188 void bnx2x_drv_pulse(struct bnx2x *bp);
189
190 /**
191 * bnx2x_igu_ack_sb - update IGU with current SB value
192 *
193 * @bp: driver handle
194 * @igu_sb_id: SB id
195 * @segment: SB segment
196 * @index: SB index
197 * @op: SB operation
198 * @update: is HW update required
199 */
200 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
201 u16 index, u8 op, u8 update);
202
203 /* Disable transactions from chip to host */
204 void bnx2x_pf_disable(struct bnx2x *bp);
205 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);
206
207 /**
208 * bnx2x__link_status_update - handles link status change.
209 *
210 * @bp: driver handle
211 */
212 void bnx2x__link_status_update(struct bnx2x *bp);
213
214 /**
215 * bnx2x_link_report - report link status to upper layer.
216 *
217 * @bp: driver handle
218 */
219 void bnx2x_link_report(struct bnx2x *bp);
220
221 /* None-atomic version of bnx2x_link_report() */
222 void __bnx2x_link_report(struct bnx2x *bp);
223
224 /**
225 * bnx2x_get_mf_speed - calculate MF speed.
226 *
227 * @bp: driver handle
228 *
229 * Takes into account current linespeed and MF configuration.
230 */
231 u16 bnx2x_get_mf_speed(struct bnx2x *bp);
232
233 /**
234 * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler
235 *
236 * @irq: irq number
237 * @dev_instance: private instance
238 */
239 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance);
240
241 /**
242 * bnx2x_interrupt - non MSI-X interrupt handler
243 *
244 * @irq: irq number
245 * @dev_instance: private instance
246 */
247 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance);
248
249 /**
250 * bnx2x_cnic_notify - send command to cnic driver
251 *
252 * @bp: driver handle
253 * @cmd: command
254 */
255 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd);
256
257 /**
258 * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information
259 *
260 * @bp: driver handle
261 */
262 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp);
263
264 /**
265 * bnx2x_setup_cnic_info - provides cnic with updated info
266 *
267 * @bp: driver handle
268 */
269 void bnx2x_setup_cnic_info(struct bnx2x *bp);
270
271 /**
272 * bnx2x_int_enable - enable HW interrupts.
273 *
274 * @bp: driver handle
275 */
276 void bnx2x_int_enable(struct bnx2x *bp);
277
278 /**
279 * bnx2x_int_disable_sync - disable interrupts.
280 *
281 * @bp: driver handle
282 * @disable_hw: true, disable HW interrupts.
283 *
284 * This function ensures that there are no
285 * ISRs or SP DPCs (sp_task) are running after it returns.
286 */
287 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw);
288
289 /**
290 * bnx2x_nic_init_cnic - init driver internals for cnic.
291 *
292 * @bp: driver handle
293 * @load_code: COMMON, PORT or FUNCTION
294 *
295 * Initializes:
296 * - rings
297 * - status blocks
298 * - etc.
299 */
300 void bnx2x_nic_init_cnic(struct bnx2x *bp);
301
302 /**
303 * bnx2x_preirq_nic_init - init driver internals.
304 *
305 * @bp: driver handle
306 *
307 * Initializes:
308 * - fastpath object
309 * - fastpath rings
310 * etc.
311 */
312 void bnx2x_pre_irq_nic_init(struct bnx2x *bp);
313
314 /**
315 * bnx2x_postirq_nic_init - init driver internals.
316 *
317 * @bp: driver handle
318 * @load_code: COMMON, PORT or FUNCTION
319 *
320 * Initializes:
321 * - status blocks
322 * - slowpath rings
323 * - etc.
324 */
325 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code);
326 /**
327 * bnx2x_alloc_mem_cnic - allocate driver's memory for cnic.
328 *
329 * @bp: driver handle
330 */
331 int bnx2x_alloc_mem_cnic(struct bnx2x *bp);
332 /**
333 * bnx2x_alloc_mem - allocate driver's memory.
334 *
335 * @bp: driver handle
336 */
337 int bnx2x_alloc_mem(struct bnx2x *bp);
338
339 /**
340 * bnx2x_free_mem_cnic - release driver's memory for cnic.
341 *
342 * @bp: driver handle
343 */
344 void bnx2x_free_mem_cnic(struct bnx2x *bp);
345 /**
346 * bnx2x_free_mem - release driver's memory.
347 *
348 * @bp: driver handle
349 */
350 void bnx2x_free_mem(struct bnx2x *bp);
351
352 /**
353 * bnx2x_set_num_queues - set number of queues according to mode.
354 *
355 * @bp: driver handle
356 */
357 void bnx2x_set_num_queues(struct bnx2x *bp);
358
359 /**
360 * bnx2x_chip_cleanup - cleanup chip internals.
361 *
362 * @bp: driver handle
363 * @unload_mode: COMMON, PORT, FUNCTION
364 * @keep_link: true iff link should be kept up.
365 *
366 * - Cleanup MAC configuration.
367 * - Closes clients.
368 * - etc.
369 */
370 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link);
371
372 /**
373 * bnx2x_acquire_hw_lock - acquire HW lock.
374 *
375 * @bp: driver handle
376 * @resource: resource bit which was locked
377 */
378 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource);
379
380 /**
381 * bnx2x_release_hw_lock - release HW lock.
382 *
383 * @bp: driver handle
384 * @resource: resource bit which was locked
385 */
386 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource);
387
388 /**
389 * bnx2x_release_leader_lock - release recovery leader lock
390 *
391 * @bp: driver handle
392 */
393 int bnx2x_release_leader_lock(struct bnx2x *bp);
394
395 /**
396 * bnx2x_set_eth_mac - configure eth MAC address in the HW
397 *
398 * @bp: driver handle
399 * @set: set or clear
400 *
401 * Configures according to the value in netdev->dev_addr.
402 */
403 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set);
404
405 /**
406 * bnx2x_set_rx_mode - set MAC filtering configurations.
407 *
408 * @dev: netdevice
409 *
410 * called with netif_tx_lock from dev_mcast.c
411 * If bp->state is OPEN, should be called with
412 * netif_addr_lock_bh()
413 */
414 void bnx2x_set_rx_mode_inner(struct bnx2x *bp);
415
416 /* Parity errors related */
417 void bnx2x_set_pf_load(struct bnx2x *bp);
418 bool bnx2x_clear_pf_load(struct bnx2x *bp);
419 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print);
420 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine);
421 void bnx2x_set_reset_in_progress(struct bnx2x *bp);
422 void bnx2x_set_reset_global(struct bnx2x *bp);
423 void bnx2x_disable_close_the_gate(struct bnx2x *bp);
424 int bnx2x_init_hw_func_cnic(struct bnx2x *bp);
425
426 /**
427 * bnx2x_sp_event - handle ramrods completion.
428 *
429 * @fp: fastpath handle for the event
430 * @rr_cqe: eth_rx_cqe
431 */
432 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe);
433
434 /**
435 * bnx2x_ilt_set_info - prepare ILT configurations.
436 *
437 * @bp: driver handle
438 */
439 void bnx2x_ilt_set_info(struct bnx2x *bp);
440
441 /**
442 * bnx2x_ilt_set_cnic_info - prepare ILT configurations for SRC
443 * and TM.
444 *
445 * @bp: driver handle
446 */
447 void bnx2x_ilt_set_info_cnic(struct bnx2x *bp);
448
449 /**
450 * bnx2x_dcbx_init - initialize dcbx protocol.
451 *
452 * @bp: driver handle
453 */
454 void bnx2x_dcbx_init(struct bnx2x *bp, bool update_shmem);
455
456 /**
457 * bnx2x_set_power_state - set power state to the requested value.
458 *
459 * @bp: driver handle
460 * @state: required state D0 or D3hot
461 *
462 * Currently only D0 and D3hot are supported.
463 */
464 int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state);
465
466 /**
467 * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW.
468 *
469 * @bp: driver handle
470 * @value: new value
471 */
472 void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value);
473 /* Error handling */
474 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl);
475
476 /* dev_close main block */
477 int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link);
478
479 /* dev_open main block */
480 int bnx2x_nic_load(struct bnx2x *bp, int load_mode);
481
482 /* hard_xmit callback */
483 netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev);
484
485 /* setup_tc callback */
486 int bnx2x_setup_tc(struct net_device *dev, u8 num_tc);
487
488 int bnx2x_get_vf_config(struct net_device *dev, int vf,
489 struct ifla_vf_info *ivi);
490 int bnx2x_set_vf_mac(struct net_device *dev, int queue, u8 *mac);
491 int bnx2x_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos);
492
493 /* select_queue callback */
494 u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb,
495 void *accel_priv, select_queue_fallback_t fallback);
496
497 static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
498 struct bnx2x_fastpath *fp,
499 u16 bd_prod, u16 rx_comp_prod,
500 u16 rx_sge_prod)
501 {
502 struct ustorm_eth_rx_producers rx_prods = {0};
503 u32 i;
504
505 /* Update producers */
506 rx_prods.bd_prod = bd_prod;
507 rx_prods.cqe_prod = rx_comp_prod;
508 rx_prods.sge_prod = rx_sge_prod;
509
510 /* Make sure that the BD and SGE data is updated before updating the
511 * producers since FW might read the BD/SGE right after the producer
512 * is updated.
513 * This is only applicable for weak-ordered memory model archs such
514 * as IA-64. The following barrier is also mandatory since FW will
515 * assumes BDs must have buffers.
516 */
517 wmb();
518
519 for (i = 0; i < sizeof(rx_prods)/4; i++)
520 REG_WR(bp, fp->ustorm_rx_prods_offset + i*4,
521 ((u32 *)&rx_prods)[i]);
522
523 mmiowb(); /* keep prod updates ordered */
524
525 DP(NETIF_MSG_RX_STATUS,
526 "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n",
527 fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
528 }
529
530 /* reload helper */
531 int bnx2x_reload_if_running(struct net_device *dev);
532
533 int bnx2x_change_mac_addr(struct net_device *dev, void *p);
534
535 /* NAPI poll Tx part */
536 int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata);
537
538 /* suspend/resume callbacks */
539 int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state);
540 int bnx2x_resume(struct pci_dev *pdev);
541
542 /* Release IRQ vectors */
543 void bnx2x_free_irq(struct bnx2x *bp);
544
545 void bnx2x_free_fp_mem(struct bnx2x *bp);
546 void bnx2x_init_rx_rings(struct bnx2x *bp);
547 void bnx2x_init_rx_rings_cnic(struct bnx2x *bp);
548 void bnx2x_free_skbs(struct bnx2x *bp);
549 void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw);
550 void bnx2x_netif_start(struct bnx2x *bp);
551 int bnx2x_load_cnic(struct bnx2x *bp);
552
553 /**
554 * bnx2x_enable_msix - set msix configuration.
555 *
556 * @bp: driver handle
557 *
558 * fills msix_table, requests vectors, updates num_queues
559 * according to number of available vectors.
560 */
561 int bnx2x_enable_msix(struct bnx2x *bp);
562
563 /**
564 * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly
565 *
566 * @bp: driver handle
567 */
568 int bnx2x_enable_msi(struct bnx2x *bp);
569
570 /**
571 * bnx2x_low_latency_recv - LL callback
572 *
573 * @napi: napi structure
574 */
575 int bnx2x_low_latency_recv(struct napi_struct *napi);
576
577 /**
578 * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure
579 *
580 * @bp: driver handle
581 */
582 int bnx2x_alloc_mem_bp(struct bnx2x *bp);
583
584 /**
585 * bnx2x_free_mem_bp - release memories outsize main driver structure
586 *
587 * @bp: driver handle
588 */
589 void bnx2x_free_mem_bp(struct bnx2x *bp);
590
591 /**
592 * bnx2x_change_mtu - change mtu netdev callback
593 *
594 * @dev: net device
595 * @new_mtu: requested mtu
596 *
597 */
598 int bnx2x_change_mtu(struct net_device *dev, int new_mtu);
599
600 #ifdef NETDEV_FCOE_WWNN
601 /**
602 * bnx2x_fcoe_get_wwn - return the requested WWN value for this port
603 *
604 * @dev: net_device
605 * @wwn: output buffer
606 * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port)
607 *
608 */
609 int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type);
610 #endif
611
612 netdev_features_t bnx2x_fix_features(struct net_device *dev,
613 netdev_features_t features);
614 int bnx2x_set_features(struct net_device *dev, netdev_features_t features);
615
616 /**
617 * bnx2x_tx_timeout - tx timeout netdev callback
618 *
619 * @dev: net device
620 */
621 void bnx2x_tx_timeout(struct net_device *dev);
622
623 /*********************** Inlines **********************************/
624 /*********************** Fast path ********************************/
625 static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
626 {
627 barrier(); /* status block is written to by the chip */
628 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
629 }
630
631 static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id,
632 u8 segment, u16 index, u8 op,
633 u8 update, u32 igu_addr)
634 {
635 struct igu_regular cmd_data = {0};
636
637 cmd_data.sb_id_and_flags =
638 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
639 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
640 (update << IGU_REGULAR_BUPDATE_SHIFT) |
641 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
642
643 DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n",
644 cmd_data.sb_id_and_flags, igu_addr);
645 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags);
646
647 /* Make sure that ACK is written */
648 mmiowb();
649 barrier();
650 }
651
652 static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id,
653 u8 storm, u16 index, u8 op, u8 update)
654 {
655 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
656 COMMAND_REG_INT_ACK);
657 struct igu_ack_register igu_ack;
658
659 igu_ack.status_block_index = index;
660 igu_ack.sb_id_and_flags =
661 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
662 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
663 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
664 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
665
666 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
667
668 /* Make sure that ACK is written */
669 mmiowb();
670 barrier();
671 }
672
673 static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm,
674 u16 index, u8 op, u8 update)
675 {
676 if (bp->common.int_block == INT_BLOCK_HC)
677 bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update);
678 else {
679 u8 segment;
680
681 if (CHIP_INT_MODE_IS_BC(bp))
682 segment = storm;
683 else if (igu_sb_id != bp->igu_dsb_id)
684 segment = IGU_SEG_ACCESS_DEF;
685 else if (storm == ATTENTION_ID)
686 segment = IGU_SEG_ACCESS_ATTN;
687 else
688 segment = IGU_SEG_ACCESS_DEF;
689 bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update);
690 }
691 }
692
693 static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp)
694 {
695 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
696 COMMAND_REG_SIMD_MASK);
697 u32 result = REG_RD(bp, hc_addr);
698
699 barrier();
700 return result;
701 }
702
703 static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp)
704 {
705 u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
706 u32 result = REG_RD(bp, igu_addr);
707
708 DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n",
709 result, igu_addr);
710
711 barrier();
712 return result;
713 }
714
715 static inline u16 bnx2x_ack_int(struct bnx2x *bp)
716 {
717 barrier();
718 if (bp->common.int_block == INT_BLOCK_HC)
719 return bnx2x_hc_ack_int(bp);
720 else
721 return bnx2x_igu_ack_int(bp);
722 }
723
724 static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata)
725 {
726 /* Tell compiler that consumer and producer can change */
727 barrier();
728 return txdata->tx_pkt_prod != txdata->tx_pkt_cons;
729 }
730
731 static inline u16 bnx2x_tx_avail(struct bnx2x *bp,
732 struct bnx2x_fp_txdata *txdata)
733 {
734 s16 used;
735 u16 prod;
736 u16 cons;
737
738 prod = txdata->tx_bd_prod;
739 cons = txdata->tx_bd_cons;
740
741 used = SUB_S16(prod, cons);
742
743 #ifdef BNX2X_STOP_ON_ERROR
744 WARN_ON(used < 0);
745 WARN_ON(used > txdata->tx_ring_size);
746 WARN_ON((txdata->tx_ring_size - used) > MAX_TX_AVAIL);
747 #endif
748
749 return (s16)(txdata->tx_ring_size) - used;
750 }
751
752 static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata)
753 {
754 u16 hw_cons;
755
756 /* Tell compiler that status block fields can change */
757 barrier();
758 hw_cons = le16_to_cpu(*txdata->tx_cons_sb);
759 return hw_cons != txdata->tx_pkt_cons;
760 }
761
762 static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
763 {
764 u8 cos;
765 for_each_cos_in_tx_queue(fp, cos)
766 if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos]))
767 return true;
768 return false;
769 }
770
771 #define BNX2X_IS_CQE_COMPLETED(cqe_fp) (cqe_fp->marker == 0x0)
772 #define BNX2X_SEED_CQE(cqe_fp) (cqe_fp->marker = 0xFFFFFFFF)
773 static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
774 {
775 u16 cons;
776 union eth_rx_cqe *cqe;
777 struct eth_fast_path_rx_cqe *cqe_fp;
778
779 cons = RCQ_BD(fp->rx_comp_cons);
780 cqe = &fp->rx_comp_ring[cons];
781 cqe_fp = &cqe->fast_path_cqe;
782 return BNX2X_IS_CQE_COMPLETED(cqe_fp);
783 }
784
785 /**
786 * bnx2x_tx_disable - disables tx from stack point of view
787 *
788 * @bp: driver handle
789 */
790 static inline void bnx2x_tx_disable(struct bnx2x *bp)
791 {
792 netif_tx_disable(bp->dev);
793 netif_carrier_off(bp->dev);
794 }
795
796 static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
797 struct bnx2x_fastpath *fp, u16 index)
798 {
799 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
800 struct page *page = sw_buf->page;
801 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
802
803 /* Skip "next page" elements */
804 if (!page)
805 return;
806
807 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping),
808 SGE_PAGES, DMA_FROM_DEVICE);
809 __free_pages(page, PAGES_PER_SGE_SHIFT);
810
811 sw_buf->page = NULL;
812 sge->addr_hi = 0;
813 sge->addr_lo = 0;
814 }
815
816 static inline void bnx2x_del_all_napi_cnic(struct bnx2x *bp)
817 {
818 int i;
819
820 for_each_rx_queue_cnic(bp, i) {
821 napi_hash_del(&bnx2x_fp(bp, i, napi));
822 netif_napi_del(&bnx2x_fp(bp, i, napi));
823 }
824 }
825
826 static inline void bnx2x_del_all_napi(struct bnx2x *bp)
827 {
828 int i;
829
830 for_each_eth_queue(bp, i) {
831 napi_hash_del(&bnx2x_fp(bp, i, napi));
832 netif_napi_del(&bnx2x_fp(bp, i, napi));
833 }
834 }
835
836 int bnx2x_set_int_mode(struct bnx2x *bp);
837
838 static inline void bnx2x_disable_msi(struct bnx2x *bp)
839 {
840 if (bp->flags & USING_MSIX_FLAG) {
841 pci_disable_msix(bp->pdev);
842 bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG);
843 } else if (bp->flags & USING_MSI_FLAG) {
844 pci_disable_msi(bp->pdev);
845 bp->flags &= ~USING_MSI_FLAG;
846 }
847 }
848
849 static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
850 {
851 int i, j;
852
853 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
854 int idx = RX_SGE_CNT * i - 1;
855
856 for (j = 0; j < 2; j++) {
857 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx);
858 idx--;
859 }
860 }
861 }
862
863 static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
864 {
865 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
866 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask));
867
868 /* Clear the two last indices in the page to 1:
869 these are the indices that correspond to the "next" element,
870 hence will never be indicated and should be removed from
871 the calculations. */
872 bnx2x_clear_sge_mask_next_elems(fp);
873 }
874
875 /* note that we are not allocating a new buffer,
876 * we are just moving one from cons to prod
877 * we are not creating a new mapping,
878 * so there is no need to check for dma_mapping_error().
879 */
880 static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp,
881 u16 cons, u16 prod)
882 {
883 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
884 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
885 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
886 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
887
888 dma_unmap_addr_set(prod_rx_buf, mapping,
889 dma_unmap_addr(cons_rx_buf, mapping));
890 prod_rx_buf->data = cons_rx_buf->data;
891 *prod_bd = *cons_bd;
892 }
893
894 /************************* Init ******************************************/
895
896 /* returns func by VN for current port */
897 static inline int func_by_vn(struct bnx2x *bp, int vn)
898 {
899 return 2 * vn + BP_PORT(bp);
900 }
901
902 static inline int bnx2x_config_rss_eth(struct bnx2x *bp, bool config_hash)
903 {
904 return bnx2x_rss(bp, &bp->rss_conf_obj, config_hash, true);
905 }
906
907 /**
908 * bnx2x_func_start - init function
909 *
910 * @bp: driver handle
911 *
912 * Must be called before sending CLIENT_SETUP for the first client.
913 */
914 static inline int bnx2x_func_start(struct bnx2x *bp)
915 {
916 struct bnx2x_func_state_params func_params = {NULL};
917 struct bnx2x_func_start_params *start_params =
918 &func_params.params.start;
919
920 /* Prepare parameters for function state transitions */
921 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
922
923 func_params.f_obj = &bp->func_obj;
924 func_params.cmd = BNX2X_F_CMD_START;
925
926 /* Function parameters */
927 start_params->mf_mode = bp->mf_mode;
928 start_params->sd_vlan_tag = bp->mf_ov;
929
930 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp))
931 start_params->network_cos_mode = STATIC_COS;
932 else /* CHIP_IS_E1X */
933 start_params->network_cos_mode = FW_WRR;
934
935 start_params->gre_tunnel_mode = L2GRE_TUNNEL;
936 start_params->gre_tunnel_rss = GRE_INNER_HEADERS_RSS;
937
938 return bnx2x_func_state_change(bp, &func_params);
939 }
940
941 /**
942 * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format
943 *
944 * @fw_hi: pointer to upper part
945 * @fw_mid: pointer to middle part
946 * @fw_lo: pointer to lower part
947 * @mac: pointer to MAC address
948 */
949 static inline void bnx2x_set_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid,
950 __le16 *fw_lo, u8 *mac)
951 {
952 ((u8 *)fw_hi)[0] = mac[1];
953 ((u8 *)fw_hi)[1] = mac[0];
954 ((u8 *)fw_mid)[0] = mac[3];
955 ((u8 *)fw_mid)[1] = mac[2];
956 ((u8 *)fw_lo)[0] = mac[5];
957 ((u8 *)fw_lo)[1] = mac[4];
958 }
959
960 static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
961 struct bnx2x_fastpath *fp, int last)
962 {
963 int i;
964
965 if (fp->disable_tpa)
966 return;
967
968 for (i = 0; i < last; i++)
969 bnx2x_free_rx_sge(bp, fp, i);
970 }
971
972 static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp)
973 {
974 int i;
975
976 for (i = 1; i <= NUM_RX_RINGS; i++) {
977 struct eth_rx_bd *rx_bd;
978
979 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
980 rx_bd->addr_hi =
981 cpu_to_le32(U64_HI(fp->rx_desc_mapping +
982 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
983 rx_bd->addr_lo =
984 cpu_to_le32(U64_LO(fp->rx_desc_mapping +
985 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
986 }
987 }
988
989 /* Statistics ID are global per chip/path, while Client IDs for E1x are per
990 * port.
991 */
992 static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp)
993 {
994 struct bnx2x *bp = fp->bp;
995 if (!CHIP_IS_E1x(bp)) {
996 /* there are special statistics counters for FCoE 136..140 */
997 if (IS_FCOE_FP(fp))
998 return bp->cnic_base_cl_id + (bp->pf_num >> 1);
999 return fp->cl_id;
1000 }
1001 return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x;
1002 }
1003
1004 static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp,
1005 bnx2x_obj_type obj_type)
1006 {
1007 struct bnx2x *bp = fp->bp;
1008
1009 /* Configure classification DBs */
1010 bnx2x_init_mac_obj(bp, &bnx2x_sp_obj(bp, fp).mac_obj, fp->cl_id,
1011 fp->cid, BP_FUNC(bp), bnx2x_sp(bp, mac_rdata),
1012 bnx2x_sp_mapping(bp, mac_rdata),
1013 BNX2X_FILTER_MAC_PENDING,
1014 &bp->sp_state, obj_type,
1015 &bp->macs_pool);
1016 }
1017
1018 /**
1019 * bnx2x_get_path_func_num - get number of active functions
1020 *
1021 * @bp: driver handle
1022 *
1023 * Calculates the number of active (not hidden) functions on the
1024 * current path.
1025 */
1026 static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp)
1027 {
1028 u8 func_num = 0, i;
1029
1030 /* 57710 has only one function per-port */
1031 if (CHIP_IS_E1(bp))
1032 return 1;
1033
1034 /* Calculate a number of functions enabled on the current
1035 * PATH/PORT.
1036 */
1037 if (CHIP_REV_IS_SLOW(bp)) {
1038 if (IS_MF(bp))
1039 func_num = 4;
1040 else
1041 func_num = 2;
1042 } else {
1043 for (i = 0; i < E1H_FUNC_MAX / 2; i++) {
1044 u32 func_config =
1045 MF_CFG_RD(bp,
1046 func_mf_config[BP_PORT(bp) + 2 * i].
1047 config);
1048 func_num +=
1049 ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1);
1050 }
1051 }
1052
1053 WARN_ON(!func_num);
1054
1055 return func_num;
1056 }
1057
1058 static inline void bnx2x_init_bp_objs(struct bnx2x *bp)
1059 {
1060 /* RX_MODE controlling object */
1061 bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj);
1062
1063 /* multicast configuration controlling object */
1064 bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid,
1065 BP_FUNC(bp), BP_FUNC(bp),
1066 bnx2x_sp(bp, mcast_rdata),
1067 bnx2x_sp_mapping(bp, mcast_rdata),
1068 BNX2X_FILTER_MCAST_PENDING, &bp->sp_state,
1069 BNX2X_OBJ_TYPE_RX);
1070
1071 /* Setup CAM credit pools */
1072 bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp),
1073 bnx2x_get_path_func_num(bp));
1074
1075 bnx2x_init_vlan_credit_pool(bp, &bp->vlans_pool, BP_ABS_FUNC(bp)>>1,
1076 bnx2x_get_path_func_num(bp));
1077
1078 /* RSS configuration object */
1079 bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id,
1080 bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp),
1081 bnx2x_sp(bp, rss_rdata),
1082 bnx2x_sp_mapping(bp, rss_rdata),
1083 BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state,
1084 BNX2X_OBJ_TYPE_RX);
1085 }
1086
1087 static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
1088 {
1089 if (CHIP_IS_E1x(fp->bp))
1090 return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H;
1091 else
1092 return fp->cl_id;
1093 }
1094
1095 static inline void bnx2x_init_txdata(struct bnx2x *bp,
1096 struct bnx2x_fp_txdata *txdata, u32 cid,
1097 int txq_index, __le16 *tx_cons_sb,
1098 struct bnx2x_fastpath *fp)
1099 {
1100 txdata->cid = cid;
1101 txdata->txq_index = txq_index;
1102 txdata->tx_cons_sb = tx_cons_sb;
1103 txdata->parent_fp = fp;
1104 txdata->tx_ring_size = IS_FCOE_FP(fp) ? MAX_TX_AVAIL : bp->tx_ring_size;
1105
1106 DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n",
1107 txdata->cid, txdata->txq_index);
1108 }
1109
1110 static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx)
1111 {
1112 return bp->cnic_base_cl_id + cl_idx +
1113 (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX;
1114 }
1115
1116 static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp)
1117 {
1118 /* the 'first' id is allocated for the cnic */
1119 return bp->base_fw_ndsb;
1120 }
1121
1122 static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp)
1123 {
1124 return bp->igu_base_sb;
1125 }
1126
1127 static inline int bnx2x_clean_tx_queue(struct bnx2x *bp,
1128 struct bnx2x_fp_txdata *txdata)
1129 {
1130 int cnt = 1000;
1131
1132 while (bnx2x_has_tx_work_unload(txdata)) {
1133 if (!cnt) {
1134 BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n",
1135 txdata->txq_index, txdata->tx_pkt_prod,
1136 txdata->tx_pkt_cons);
1137 #ifdef BNX2X_STOP_ON_ERROR
1138 bnx2x_panic();
1139 return -EBUSY;
1140 #else
1141 break;
1142 #endif
1143 }
1144 cnt--;
1145 usleep_range(1000, 2000);
1146 }
1147
1148 return 0;
1149 }
1150
1151 int bnx2x_get_link_cfg_idx(struct bnx2x *bp);
1152
1153 static inline void __storm_memset_struct(struct bnx2x *bp,
1154 u32 addr, size_t size, u32 *data)
1155 {
1156 int i;
1157 for (i = 0; i < size/4; i++)
1158 REG_WR(bp, addr + (i * 4), data[i]);
1159 }
1160
1161 /**
1162 * bnx2x_wait_sp_comp - wait for the outstanding SP commands.
1163 *
1164 * @bp: driver handle
1165 * @mask: bits that need to be cleared
1166 */
1167 static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask)
1168 {
1169 int tout = 5000; /* Wait for 5 secs tops */
1170
1171 while (tout--) {
1172 smp_mb();
1173 netif_addr_lock_bh(bp->dev);
1174 if (!(bp->sp_state & mask)) {
1175 netif_addr_unlock_bh(bp->dev);
1176 return true;
1177 }
1178 netif_addr_unlock_bh(bp->dev);
1179
1180 usleep_range(1000, 2000);
1181 }
1182
1183 smp_mb();
1184
1185 netif_addr_lock_bh(bp->dev);
1186 if (bp->sp_state & mask) {
1187 BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n",
1188 bp->sp_state, mask);
1189 netif_addr_unlock_bh(bp->dev);
1190 return false;
1191 }
1192 netif_addr_unlock_bh(bp->dev);
1193
1194 return true;
1195 }
1196
1197 /**
1198 * bnx2x_set_ctx_validation - set CDU context validation values
1199 *
1200 * @bp: driver handle
1201 * @cxt: context of the connection on the host memory
1202 * @cid: SW CID of the connection to be configured
1203 */
1204 void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt,
1205 u32 cid);
1206
1207 void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id,
1208 u8 sb_index, u8 disable, u16 usec);
1209 void bnx2x_acquire_phy_lock(struct bnx2x *bp);
1210 void bnx2x_release_phy_lock(struct bnx2x *bp);
1211
1212 /**
1213 * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration.
1214 *
1215 * @bp: driver handle
1216 * @mf_cfg: MF configuration
1217 *
1218 */
1219 static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg)
1220 {
1221 u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
1222 FUNC_MF_CFG_MAX_BW_SHIFT;
1223 if (!max_cfg) {
1224 DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL,
1225 "Max BW configured to 0 - using 100 instead\n");
1226 max_cfg = 100;
1227 }
1228 return max_cfg;
1229 }
1230
1231 /* checks if HW supports GRO for given MTU */
1232 static inline bool bnx2x_mtu_allows_gro(int mtu)
1233 {
1234 /* gro frags per page */
1235 int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE);
1236
1237 /*
1238 * 1. Number of frags should not grow above MAX_SKB_FRAGS
1239 * 2. Frag must fit the page
1240 */
1241 return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS;
1242 }
1243
1244 /**
1245 * bnx2x_get_iscsi_info - update iSCSI params according to licensing info.
1246 *
1247 * @bp: driver handle
1248 *
1249 */
1250 void bnx2x_get_iscsi_info(struct bnx2x *bp);
1251
1252 /**
1253 * bnx2x_link_sync_notify - send notification to other functions.
1254 *
1255 * @bp: driver handle
1256 *
1257 */
1258 static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
1259 {
1260 int func;
1261 int vn;
1262
1263 /* Set the attention towards other drivers on the same port */
1264 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
1265 if (vn == BP_VN(bp))
1266 continue;
1267
1268 func = func_by_vn(bp, vn);
1269 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
1270 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
1271 }
1272 }
1273
1274 /**
1275 * bnx2x_update_drv_flags - update flags in shmem
1276 *
1277 * @bp: driver handle
1278 * @flags: flags to update
1279 * @set: set or clear
1280 *
1281 */
1282 static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set)
1283 {
1284 if (SHMEM2_HAS(bp, drv_flags)) {
1285 u32 drv_flags;
1286 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS);
1287 drv_flags = SHMEM2_RD(bp, drv_flags);
1288
1289 if (set)
1290 SET_FLAGS(drv_flags, flags);
1291 else
1292 RESET_FLAGS(drv_flags, flags);
1293
1294 SHMEM2_WR(bp, drv_flags, drv_flags);
1295 DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags);
1296 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS);
1297 }
1298 }
1299
1300 static inline bool bnx2x_is_valid_ether_addr(struct bnx2x *bp, u8 *addr)
1301 {
1302 if (is_valid_ether_addr(addr) ||
1303 (is_zero_ether_addr(addr) &&
1304 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))))
1305 return true;
1306
1307 return false;
1308 }
1309
1310 /**
1311 * bnx2x_fill_fw_str - Fill buffer with FW version string
1312 *
1313 * @bp: driver handle
1314 * @buf: character buffer to fill with the fw name
1315 * @buf_len: length of the above buffer
1316 *
1317 */
1318 void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len);
1319
1320 int bnx2x_drain_tx_queues(struct bnx2x *bp);
1321 void bnx2x_squeeze_objects(struct bnx2x *bp);
1322
1323 void bnx2x_schedule_sp_rtnl(struct bnx2x*, enum sp_rtnl_flag,
1324 u32 verbose);
1325
1326 #endif /* BNX2X_CMN_H */
Linux kernel - Deliverables
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