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[media] media-device: fix builds when USB or PCI is compiled as module
[deliverable/linux.git] / drivers / net / ethernet / cadence / macb.c
1 /*
2 * Cadence MACB/GEM Ethernet Controller driver
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/circ_buf.h>
18 #include <linux/slab.h>
19 #include <linux/init.h>
20 #include <linux/io.h>
21 #include <linux/gpio.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/interrupt.h>
24 #include <linux/netdevice.h>
25 #include <linux/etherdevice.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/platform_data/macb.h>
28 #include <linux/platform_device.h>
29 #include <linux/phy.h>
30 #include <linux/of.h>
31 #include <linux/of_device.h>
32 #include <linux/of_gpio.h>
33 #include <linux/of_mdio.h>
34 #include <linux/of_net.h>
35
36 #include "macb.h"
37
38 #define MACB_RX_BUFFER_SIZE 128
39 #define RX_BUFFER_MULTIPLE 64 /* bytes */
40 #define RX_RING_SIZE 512 /* must be power of 2 */
41 #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
42
43 #define TX_RING_SIZE 128 /* must be power of 2 */
44 #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
45
46 /* level of occupied TX descriptors under which we wake up TX process */
47 #define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
48
49 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
50 | MACB_BIT(ISR_ROVR))
51 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
52 | MACB_BIT(ISR_RLE) \
53 | MACB_BIT(TXERR))
54 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
55
56 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1))
57 #define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1))
58
59 #define GEM_MTU_MIN_SIZE 68
60
61 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
62 #define MACB_WOL_ENABLED (0x1 << 1)
63
64 /*
65 * Graceful stop timeouts in us. We should allow up to
66 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
67 */
68 #define MACB_HALT_TIMEOUT 1230
69
70 /* Ring buffer accessors */
71 static unsigned int macb_tx_ring_wrap(unsigned int index)
72 {
73 return index & (TX_RING_SIZE - 1);
74 }
75
76 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
77 unsigned int index)
78 {
79 return &queue->tx_ring[macb_tx_ring_wrap(index)];
80 }
81
82 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
83 unsigned int index)
84 {
85 return &queue->tx_skb[macb_tx_ring_wrap(index)];
86 }
87
88 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
89 {
90 dma_addr_t offset;
91
92 offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
93
94 return queue->tx_ring_dma + offset;
95 }
96
97 static unsigned int macb_rx_ring_wrap(unsigned int index)
98 {
99 return index & (RX_RING_SIZE - 1);
100 }
101
102 static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
103 {
104 return &bp->rx_ring[macb_rx_ring_wrap(index)];
105 }
106
107 static void *macb_rx_buffer(struct macb *bp, unsigned int index)
108 {
109 return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
110 }
111
112 /* I/O accessors */
113 static u32 hw_readl_native(struct macb *bp, int offset)
114 {
115 return __raw_readl(bp->regs + offset);
116 }
117
118 static void hw_writel_native(struct macb *bp, int offset, u32 value)
119 {
120 __raw_writel(value, bp->regs + offset);
121 }
122
123 static u32 hw_readl(struct macb *bp, int offset)
124 {
125 return readl_relaxed(bp->regs + offset);
126 }
127
128 static void hw_writel(struct macb *bp, int offset, u32 value)
129 {
130 writel_relaxed(value, bp->regs + offset);
131 }
132
133 /*
134 * Find the CPU endianness by using the loopback bit of NCR register. When the
135 * CPU is in big endian we need to program swaped mode for management
136 * descriptor access.
137 */
138 static bool hw_is_native_io(void __iomem *addr)
139 {
140 u32 value = MACB_BIT(LLB);
141
142 __raw_writel(value, addr + MACB_NCR);
143 value = __raw_readl(addr + MACB_NCR);
144
145 /* Write 0 back to disable everything */
146 __raw_writel(0, addr + MACB_NCR);
147
148 return value == MACB_BIT(LLB);
149 }
150
151 static bool hw_is_gem(void __iomem *addr, bool native_io)
152 {
153 u32 id;
154
155 if (native_io)
156 id = __raw_readl(addr + MACB_MID);
157 else
158 id = readl_relaxed(addr + MACB_MID);
159
160 return MACB_BFEXT(IDNUM, id) >= 0x2;
161 }
162
163 static void macb_set_hwaddr(struct macb *bp)
164 {
165 u32 bottom;
166 u16 top;
167
168 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
169 macb_or_gem_writel(bp, SA1B, bottom);
170 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
171 macb_or_gem_writel(bp, SA1T, top);
172
173 /* Clear unused address register sets */
174 macb_or_gem_writel(bp, SA2B, 0);
175 macb_or_gem_writel(bp, SA2T, 0);
176 macb_or_gem_writel(bp, SA3B, 0);
177 macb_or_gem_writel(bp, SA3T, 0);
178 macb_or_gem_writel(bp, SA4B, 0);
179 macb_or_gem_writel(bp, SA4T, 0);
180 }
181
182 static void macb_get_hwaddr(struct macb *bp)
183 {
184 struct macb_platform_data *pdata;
185 u32 bottom;
186 u16 top;
187 u8 addr[6];
188 int i;
189
190 pdata = dev_get_platdata(&bp->pdev->dev);
191
192 /* Check all 4 address register for vaild address */
193 for (i = 0; i < 4; i++) {
194 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
195 top = macb_or_gem_readl(bp, SA1T + i * 8);
196
197 if (pdata && pdata->rev_eth_addr) {
198 addr[5] = bottom & 0xff;
199 addr[4] = (bottom >> 8) & 0xff;
200 addr[3] = (bottom >> 16) & 0xff;
201 addr[2] = (bottom >> 24) & 0xff;
202 addr[1] = top & 0xff;
203 addr[0] = (top & 0xff00) >> 8;
204 } else {
205 addr[0] = bottom & 0xff;
206 addr[1] = (bottom >> 8) & 0xff;
207 addr[2] = (bottom >> 16) & 0xff;
208 addr[3] = (bottom >> 24) & 0xff;
209 addr[4] = top & 0xff;
210 addr[5] = (top >> 8) & 0xff;
211 }
212
213 if (is_valid_ether_addr(addr)) {
214 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
215 return;
216 }
217 }
218
219 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
220 eth_hw_addr_random(bp->dev);
221 }
222
223 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
224 {
225 struct macb *bp = bus->priv;
226 int value;
227
228 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
229 | MACB_BF(RW, MACB_MAN_READ)
230 | MACB_BF(PHYA, mii_id)
231 | MACB_BF(REGA, regnum)
232 | MACB_BF(CODE, MACB_MAN_CODE)));
233
234 /* wait for end of transfer */
235 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
236 cpu_relax();
237
238 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
239
240 return value;
241 }
242
243 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
244 u16 value)
245 {
246 struct macb *bp = bus->priv;
247
248 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
249 | MACB_BF(RW, MACB_MAN_WRITE)
250 | MACB_BF(PHYA, mii_id)
251 | MACB_BF(REGA, regnum)
252 | MACB_BF(CODE, MACB_MAN_CODE)
253 | MACB_BF(DATA, value)));
254
255 /* wait for end of transfer */
256 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
257 cpu_relax();
258
259 return 0;
260 }
261
262 /**
263 * macb_set_tx_clk() - Set a clock to a new frequency
264 * @clk Pointer to the clock to change
265 * @rate New frequency in Hz
266 * @dev Pointer to the struct net_device
267 */
268 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
269 {
270 long ferr, rate, rate_rounded;
271
272 if (!clk)
273 return;
274
275 switch (speed) {
276 case SPEED_10:
277 rate = 2500000;
278 break;
279 case SPEED_100:
280 rate = 25000000;
281 break;
282 case SPEED_1000:
283 rate = 125000000;
284 break;
285 default:
286 return;
287 }
288
289 rate_rounded = clk_round_rate(clk, rate);
290 if (rate_rounded < 0)
291 return;
292
293 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
294 * is not satisfied.
295 */
296 ferr = abs(rate_rounded - rate);
297 ferr = DIV_ROUND_UP(ferr, rate / 100000);
298 if (ferr > 5)
299 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
300 rate);
301
302 if (clk_set_rate(clk, rate_rounded))
303 netdev_err(dev, "adjusting tx_clk failed.\n");
304 }
305
306 static void macb_handle_link_change(struct net_device *dev)
307 {
308 struct macb *bp = netdev_priv(dev);
309 struct phy_device *phydev = bp->phy_dev;
310 unsigned long flags;
311 int status_change = 0;
312
313 spin_lock_irqsave(&bp->lock, flags);
314
315 if (phydev->link) {
316 if ((bp->speed != phydev->speed) ||
317 (bp->duplex != phydev->duplex)) {
318 u32 reg;
319
320 reg = macb_readl(bp, NCFGR);
321 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
322 if (macb_is_gem(bp))
323 reg &= ~GEM_BIT(GBE);
324
325 if (phydev->duplex)
326 reg |= MACB_BIT(FD);
327 if (phydev->speed == SPEED_100)
328 reg |= MACB_BIT(SPD);
329 if (phydev->speed == SPEED_1000 &&
330 bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
331 reg |= GEM_BIT(GBE);
332
333 macb_or_gem_writel(bp, NCFGR, reg);
334
335 bp->speed = phydev->speed;
336 bp->duplex = phydev->duplex;
337 status_change = 1;
338 }
339 }
340
341 if (phydev->link != bp->link) {
342 if (!phydev->link) {
343 bp->speed = 0;
344 bp->duplex = -1;
345 }
346 bp->link = phydev->link;
347
348 status_change = 1;
349 }
350
351 spin_unlock_irqrestore(&bp->lock, flags);
352
353 if (status_change) {
354 if (phydev->link) {
355 /* Update the TX clock rate if and only if the link is
356 * up and there has been a link change.
357 */
358 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
359
360 netif_carrier_on(dev);
361 netdev_info(dev, "link up (%d/%s)\n",
362 phydev->speed,
363 phydev->duplex == DUPLEX_FULL ?
364 "Full" : "Half");
365 } else {
366 netif_carrier_off(dev);
367 netdev_info(dev, "link down\n");
368 }
369 }
370 }
371
372 /* based on au1000_eth. c*/
373 static int macb_mii_probe(struct net_device *dev)
374 {
375 struct macb *bp = netdev_priv(dev);
376 struct macb_platform_data *pdata;
377 struct phy_device *phydev;
378 int phy_irq;
379 int ret;
380
381 phydev = phy_find_first(bp->mii_bus);
382 if (!phydev) {
383 netdev_err(dev, "no PHY found\n");
384 return -ENXIO;
385 }
386
387 pdata = dev_get_platdata(&bp->pdev->dev);
388 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
389 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int");
390 if (!ret) {
391 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
392 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
393 }
394 }
395
396 /* attach the mac to the phy */
397 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
398 bp->phy_interface);
399 if (ret) {
400 netdev_err(dev, "Could not attach to PHY\n");
401 return ret;
402 }
403
404 /* mask with MAC supported features */
405 if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
406 phydev->supported &= PHY_GBIT_FEATURES;
407 else
408 phydev->supported &= PHY_BASIC_FEATURES;
409
410 if (bp->caps & MACB_CAPS_NO_GIGABIT_HALF)
411 phydev->supported &= ~SUPPORTED_1000baseT_Half;
412
413 phydev->advertising = phydev->supported;
414
415 bp->link = 0;
416 bp->speed = 0;
417 bp->duplex = -1;
418 bp->phy_dev = phydev;
419
420 return 0;
421 }
422
423 static int macb_mii_init(struct macb *bp)
424 {
425 struct macb_platform_data *pdata;
426 struct device_node *np;
427 int err = -ENXIO, i;
428
429 /* Enable management port */
430 macb_writel(bp, NCR, MACB_BIT(MPE));
431
432 bp->mii_bus = mdiobus_alloc();
433 if (bp->mii_bus == NULL) {
434 err = -ENOMEM;
435 goto err_out;
436 }
437
438 bp->mii_bus->name = "MACB_mii_bus";
439 bp->mii_bus->read = &macb_mdio_read;
440 bp->mii_bus->write = &macb_mdio_write;
441 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
442 bp->pdev->name, bp->pdev->id);
443 bp->mii_bus->priv = bp;
444 bp->mii_bus->parent = &bp->dev->dev;
445 pdata = dev_get_platdata(&bp->pdev->dev);
446
447 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
448
449 np = bp->pdev->dev.of_node;
450 if (np) {
451 /* try dt phy registration */
452 err = of_mdiobus_register(bp->mii_bus, np);
453
454 /* fallback to standard phy registration if no phy were
455 found during dt phy registration */
456 if (!err && !phy_find_first(bp->mii_bus)) {
457 for (i = 0; i < PHY_MAX_ADDR; i++) {
458 struct phy_device *phydev;
459
460 phydev = mdiobus_scan(bp->mii_bus, i);
461 if (IS_ERR(phydev)) {
462 err = PTR_ERR(phydev);
463 break;
464 }
465 }
466
467 if (err)
468 goto err_out_unregister_bus;
469 }
470 } else {
471 if (pdata)
472 bp->mii_bus->phy_mask = pdata->phy_mask;
473
474 err = mdiobus_register(bp->mii_bus);
475 }
476
477 if (err)
478 goto err_out_free_mdiobus;
479
480 err = macb_mii_probe(bp->dev);
481 if (err)
482 goto err_out_unregister_bus;
483
484 return 0;
485
486 err_out_unregister_bus:
487 mdiobus_unregister(bp->mii_bus);
488 err_out_free_mdiobus:
489 mdiobus_free(bp->mii_bus);
490 err_out:
491 return err;
492 }
493
494 static void macb_update_stats(struct macb *bp)
495 {
496 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
497 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
498 int offset = MACB_PFR;
499
500 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
501
502 for(; p < end; p++, offset += 4)
503 *p += bp->macb_reg_readl(bp, offset);
504 }
505
506 static int macb_halt_tx(struct macb *bp)
507 {
508 unsigned long halt_time, timeout;
509 u32 status;
510
511 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
512
513 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
514 do {
515 halt_time = jiffies;
516 status = macb_readl(bp, TSR);
517 if (!(status & MACB_BIT(TGO)))
518 return 0;
519
520 usleep_range(10, 250);
521 } while (time_before(halt_time, timeout));
522
523 return -ETIMEDOUT;
524 }
525
526 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
527 {
528 if (tx_skb->mapping) {
529 if (tx_skb->mapped_as_page)
530 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
531 tx_skb->size, DMA_TO_DEVICE);
532 else
533 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
534 tx_skb->size, DMA_TO_DEVICE);
535 tx_skb->mapping = 0;
536 }
537
538 if (tx_skb->skb) {
539 dev_kfree_skb_any(tx_skb->skb);
540 tx_skb->skb = NULL;
541 }
542 }
543
544 static void macb_tx_error_task(struct work_struct *work)
545 {
546 struct macb_queue *queue = container_of(work, struct macb_queue,
547 tx_error_task);
548 struct macb *bp = queue->bp;
549 struct macb_tx_skb *tx_skb;
550 struct macb_dma_desc *desc;
551 struct sk_buff *skb;
552 unsigned int tail;
553 unsigned long flags;
554
555 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
556 (unsigned int)(queue - bp->queues),
557 queue->tx_tail, queue->tx_head);
558
559 /* Prevent the queue IRQ handlers from running: each of them may call
560 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
561 * As explained below, we have to halt the transmission before updating
562 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
563 * network engine about the macb/gem being halted.
564 */
565 spin_lock_irqsave(&bp->lock, flags);
566
567 /* Make sure nobody is trying to queue up new packets */
568 netif_tx_stop_all_queues(bp->dev);
569
570 /*
571 * Stop transmission now
572 * (in case we have just queued new packets)
573 * macb/gem must be halted to write TBQP register
574 */
575 if (macb_halt_tx(bp))
576 /* Just complain for now, reinitializing TX path can be good */
577 netdev_err(bp->dev, "BUG: halt tx timed out\n");
578
579 /*
580 * Treat frames in TX queue including the ones that caused the error.
581 * Free transmit buffers in upper layer.
582 */
583 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
584 u32 ctrl;
585
586 desc = macb_tx_desc(queue, tail);
587 ctrl = desc->ctrl;
588 tx_skb = macb_tx_skb(queue, tail);
589 skb = tx_skb->skb;
590
591 if (ctrl & MACB_BIT(TX_USED)) {
592 /* skb is set for the last buffer of the frame */
593 while (!skb) {
594 macb_tx_unmap(bp, tx_skb);
595 tail++;
596 tx_skb = macb_tx_skb(queue, tail);
597 skb = tx_skb->skb;
598 }
599
600 /* ctrl still refers to the first buffer descriptor
601 * since it's the only one written back by the hardware
602 */
603 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
604 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
605 macb_tx_ring_wrap(tail), skb->data);
606 bp->stats.tx_packets++;
607 bp->stats.tx_bytes += skb->len;
608 }
609 } else {
610 /*
611 * "Buffers exhausted mid-frame" errors may only happen
612 * if the driver is buggy, so complain loudly about those.
613 * Statistics are updated by hardware.
614 */
615 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
616 netdev_err(bp->dev,
617 "BUG: TX buffers exhausted mid-frame\n");
618
619 desc->ctrl = ctrl | MACB_BIT(TX_USED);
620 }
621
622 macb_tx_unmap(bp, tx_skb);
623 }
624
625 /* Set end of TX queue */
626 desc = macb_tx_desc(queue, 0);
627 desc->addr = 0;
628 desc->ctrl = MACB_BIT(TX_USED);
629
630 /* Make descriptor updates visible to hardware */
631 wmb();
632
633 /* Reinitialize the TX desc queue */
634 queue_writel(queue, TBQP, queue->tx_ring_dma);
635 /* Make TX ring reflect state of hardware */
636 queue->tx_head = 0;
637 queue->tx_tail = 0;
638
639 /* Housework before enabling TX IRQ */
640 macb_writel(bp, TSR, macb_readl(bp, TSR));
641 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
642
643 /* Now we are ready to start transmission again */
644 netif_tx_start_all_queues(bp->dev);
645 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
646
647 spin_unlock_irqrestore(&bp->lock, flags);
648 }
649
650 static void macb_tx_interrupt(struct macb_queue *queue)
651 {
652 unsigned int tail;
653 unsigned int head;
654 u32 status;
655 struct macb *bp = queue->bp;
656 u16 queue_index = queue - bp->queues;
657
658 status = macb_readl(bp, TSR);
659 macb_writel(bp, TSR, status);
660
661 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
662 queue_writel(queue, ISR, MACB_BIT(TCOMP));
663
664 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
665 (unsigned long)status);
666
667 head = queue->tx_head;
668 for (tail = queue->tx_tail; tail != head; tail++) {
669 struct macb_tx_skb *tx_skb;
670 struct sk_buff *skb;
671 struct macb_dma_desc *desc;
672 u32 ctrl;
673
674 desc = macb_tx_desc(queue, tail);
675
676 /* Make hw descriptor updates visible to CPU */
677 rmb();
678
679 ctrl = desc->ctrl;
680
681 /* TX_USED bit is only set by hardware on the very first buffer
682 * descriptor of the transmitted frame.
683 */
684 if (!(ctrl & MACB_BIT(TX_USED)))
685 break;
686
687 /* Process all buffers of the current transmitted frame */
688 for (;; tail++) {
689 tx_skb = macb_tx_skb(queue, tail);
690 skb = tx_skb->skb;
691
692 /* First, update TX stats if needed */
693 if (skb) {
694 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
695 macb_tx_ring_wrap(tail), skb->data);
696 bp->stats.tx_packets++;
697 bp->stats.tx_bytes += skb->len;
698 }
699
700 /* Now we can safely release resources */
701 macb_tx_unmap(bp, tx_skb);
702
703 /* skb is set only for the last buffer of the frame.
704 * WARNING: at this point skb has been freed by
705 * macb_tx_unmap().
706 */
707 if (skb)
708 break;
709 }
710 }
711
712 queue->tx_tail = tail;
713 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
714 CIRC_CNT(queue->tx_head, queue->tx_tail,
715 TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH)
716 netif_wake_subqueue(bp->dev, queue_index);
717 }
718
719 static void gem_rx_refill(struct macb *bp)
720 {
721 unsigned int entry;
722 struct sk_buff *skb;
723 dma_addr_t paddr;
724
725 while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, RX_RING_SIZE) > 0) {
726 entry = macb_rx_ring_wrap(bp->rx_prepared_head);
727
728 /* Make hw descriptor updates visible to CPU */
729 rmb();
730
731 bp->rx_prepared_head++;
732
733 if (bp->rx_skbuff[entry] == NULL) {
734 /* allocate sk_buff for this free entry in ring */
735 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
736 if (unlikely(skb == NULL)) {
737 netdev_err(bp->dev,
738 "Unable to allocate sk_buff\n");
739 break;
740 }
741
742 /* now fill corresponding descriptor entry */
743 paddr = dma_map_single(&bp->pdev->dev, skb->data,
744 bp->rx_buffer_size, DMA_FROM_DEVICE);
745 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
746 dev_kfree_skb(skb);
747 break;
748 }
749
750 bp->rx_skbuff[entry] = skb;
751
752 if (entry == RX_RING_SIZE - 1)
753 paddr |= MACB_BIT(RX_WRAP);
754 bp->rx_ring[entry].addr = paddr;
755 bp->rx_ring[entry].ctrl = 0;
756
757 /* properly align Ethernet header */
758 skb_reserve(skb, NET_IP_ALIGN);
759 } else {
760 bp->rx_ring[entry].addr &= ~MACB_BIT(RX_USED);
761 bp->rx_ring[entry].ctrl = 0;
762 }
763 }
764
765 /* Make descriptor updates visible to hardware */
766 wmb();
767
768 netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
769 bp->rx_prepared_head, bp->rx_tail);
770 }
771
772 /* Mark DMA descriptors from begin up to and not including end as unused */
773 static void discard_partial_frame(struct macb *bp, unsigned int begin,
774 unsigned int end)
775 {
776 unsigned int frag;
777
778 for (frag = begin; frag != end; frag++) {
779 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
780 desc->addr &= ~MACB_BIT(RX_USED);
781 }
782
783 /* Make descriptor updates visible to hardware */
784 wmb();
785
786 /*
787 * When this happens, the hardware stats registers for
788 * whatever caused this is updated, so we don't have to record
789 * anything.
790 */
791 }
792
793 static int gem_rx(struct macb *bp, int budget)
794 {
795 unsigned int len;
796 unsigned int entry;
797 struct sk_buff *skb;
798 struct macb_dma_desc *desc;
799 int count = 0;
800
801 while (count < budget) {
802 u32 addr, ctrl;
803
804 entry = macb_rx_ring_wrap(bp->rx_tail);
805 desc = &bp->rx_ring[entry];
806
807 /* Make hw descriptor updates visible to CPU */
808 rmb();
809
810 addr = desc->addr;
811 ctrl = desc->ctrl;
812
813 if (!(addr & MACB_BIT(RX_USED)))
814 break;
815
816 bp->rx_tail++;
817 count++;
818
819 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
820 netdev_err(bp->dev,
821 "not whole frame pointed by descriptor\n");
822 bp->stats.rx_dropped++;
823 break;
824 }
825 skb = bp->rx_skbuff[entry];
826 if (unlikely(!skb)) {
827 netdev_err(bp->dev,
828 "inconsistent Rx descriptor chain\n");
829 bp->stats.rx_dropped++;
830 break;
831 }
832 /* now everything is ready for receiving packet */
833 bp->rx_skbuff[entry] = NULL;
834 len = ctrl & bp->rx_frm_len_mask;
835
836 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
837
838 skb_put(skb, len);
839 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr));
840 dma_unmap_single(&bp->pdev->dev, addr,
841 bp->rx_buffer_size, DMA_FROM_DEVICE);
842
843 skb->protocol = eth_type_trans(skb, bp->dev);
844 skb_checksum_none_assert(skb);
845 if (bp->dev->features & NETIF_F_RXCSUM &&
846 !(bp->dev->flags & IFF_PROMISC) &&
847 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
848 skb->ip_summed = CHECKSUM_UNNECESSARY;
849
850 bp->stats.rx_packets++;
851 bp->stats.rx_bytes += skb->len;
852
853 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
854 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
855 skb->len, skb->csum);
856 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
857 skb_mac_header(skb), 16, true);
858 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
859 skb->data, 32, true);
860 #endif
861
862 netif_receive_skb(skb);
863 }
864
865 gem_rx_refill(bp);
866
867 return count;
868 }
869
870 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
871 unsigned int last_frag)
872 {
873 unsigned int len;
874 unsigned int frag;
875 unsigned int offset;
876 struct sk_buff *skb;
877 struct macb_dma_desc *desc;
878
879 desc = macb_rx_desc(bp, last_frag);
880 len = desc->ctrl & bp->rx_frm_len_mask;
881
882 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
883 macb_rx_ring_wrap(first_frag),
884 macb_rx_ring_wrap(last_frag), len);
885
886 /*
887 * The ethernet header starts NET_IP_ALIGN bytes into the
888 * first buffer. Since the header is 14 bytes, this makes the
889 * payload word-aligned.
890 *
891 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
892 * the two padding bytes into the skb so that we avoid hitting
893 * the slowpath in memcpy(), and pull them off afterwards.
894 */
895 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
896 if (!skb) {
897 bp->stats.rx_dropped++;
898 for (frag = first_frag; ; frag++) {
899 desc = macb_rx_desc(bp, frag);
900 desc->addr &= ~MACB_BIT(RX_USED);
901 if (frag == last_frag)
902 break;
903 }
904
905 /* Make descriptor updates visible to hardware */
906 wmb();
907
908 return 1;
909 }
910
911 offset = 0;
912 len += NET_IP_ALIGN;
913 skb_checksum_none_assert(skb);
914 skb_put(skb, len);
915
916 for (frag = first_frag; ; frag++) {
917 unsigned int frag_len = bp->rx_buffer_size;
918
919 if (offset + frag_len > len) {
920 BUG_ON(frag != last_frag);
921 frag_len = len - offset;
922 }
923 skb_copy_to_linear_data_offset(skb, offset,
924 macb_rx_buffer(bp, frag), frag_len);
925 offset += bp->rx_buffer_size;
926 desc = macb_rx_desc(bp, frag);
927 desc->addr &= ~MACB_BIT(RX_USED);
928
929 if (frag == last_frag)
930 break;
931 }
932
933 /* Make descriptor updates visible to hardware */
934 wmb();
935
936 __skb_pull(skb, NET_IP_ALIGN);
937 skb->protocol = eth_type_trans(skb, bp->dev);
938
939 bp->stats.rx_packets++;
940 bp->stats.rx_bytes += skb->len;
941 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
942 skb->len, skb->csum);
943 netif_receive_skb(skb);
944
945 return 0;
946 }
947
948 static int macb_rx(struct macb *bp, int budget)
949 {
950 int received = 0;
951 unsigned int tail;
952 int first_frag = -1;
953
954 for (tail = bp->rx_tail; budget > 0; tail++) {
955 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
956 u32 addr, ctrl;
957
958 /* Make hw descriptor updates visible to CPU */
959 rmb();
960
961 addr = desc->addr;
962 ctrl = desc->ctrl;
963
964 if (!(addr & MACB_BIT(RX_USED)))
965 break;
966
967 if (ctrl & MACB_BIT(RX_SOF)) {
968 if (first_frag != -1)
969 discard_partial_frame(bp, first_frag, tail);
970 first_frag = tail;
971 }
972
973 if (ctrl & MACB_BIT(RX_EOF)) {
974 int dropped;
975 BUG_ON(first_frag == -1);
976
977 dropped = macb_rx_frame(bp, first_frag, tail);
978 first_frag = -1;
979 if (!dropped) {
980 received++;
981 budget--;
982 }
983 }
984 }
985
986 if (first_frag != -1)
987 bp->rx_tail = first_frag;
988 else
989 bp->rx_tail = tail;
990
991 return received;
992 }
993
994 static int macb_poll(struct napi_struct *napi, int budget)
995 {
996 struct macb *bp = container_of(napi, struct macb, napi);
997 int work_done;
998 u32 status;
999
1000 status = macb_readl(bp, RSR);
1001 macb_writel(bp, RSR, status);
1002
1003 work_done = 0;
1004
1005 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
1006 (unsigned long)status, budget);
1007
1008 work_done = bp->macbgem_ops.mog_rx(bp, budget);
1009 if (work_done < budget) {
1010 napi_complete(napi);
1011
1012 /* Packets received while interrupts were disabled */
1013 status = macb_readl(bp, RSR);
1014 if (status) {
1015 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1016 macb_writel(bp, ISR, MACB_BIT(RCOMP));
1017 napi_reschedule(napi);
1018 } else {
1019 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
1020 }
1021 }
1022
1023 /* TODO: Handle errors */
1024
1025 return work_done;
1026 }
1027
1028 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1029 {
1030 struct macb_queue *queue = dev_id;
1031 struct macb *bp = queue->bp;
1032 struct net_device *dev = bp->dev;
1033 u32 status, ctrl;
1034
1035 status = queue_readl(queue, ISR);
1036
1037 if (unlikely(!status))
1038 return IRQ_NONE;
1039
1040 spin_lock(&bp->lock);
1041
1042 while (status) {
1043 /* close possible race with dev_close */
1044 if (unlikely(!netif_running(dev))) {
1045 queue_writel(queue, IDR, -1);
1046 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1047 queue_writel(queue, ISR, -1);
1048 break;
1049 }
1050
1051 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1052 (unsigned int)(queue - bp->queues),
1053 (unsigned long)status);
1054
1055 if (status & MACB_RX_INT_FLAGS) {
1056 /*
1057 * There's no point taking any more interrupts
1058 * until we have processed the buffers. The
1059 * scheduling call may fail if the poll routine
1060 * is already scheduled, so disable interrupts
1061 * now.
1062 */
1063 queue_writel(queue, IDR, MACB_RX_INT_FLAGS);
1064 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1065 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1066
1067 if (napi_schedule_prep(&bp->napi)) {
1068 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1069 __napi_schedule(&bp->napi);
1070 }
1071 }
1072
1073 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1074 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1075 schedule_work(&queue->tx_error_task);
1076
1077 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1078 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1079
1080 break;
1081 }
1082
1083 if (status & MACB_BIT(TCOMP))
1084 macb_tx_interrupt(queue);
1085
1086 /*
1087 * Link change detection isn't possible with RMII, so we'll
1088 * add that if/when we get our hands on a full-blown MII PHY.
1089 */
1090
1091 /* There is a hardware issue under heavy load where DMA can
1092 * stop, this causes endless "used buffer descriptor read"
1093 * interrupts but it can be cleared by re-enabling RX. See
1094 * the at91 manual, section 41.3.1 or the Zynq manual
1095 * section 16.7.4 for details.
1096 */
1097 if (status & MACB_BIT(RXUBR)) {
1098 ctrl = macb_readl(bp, NCR);
1099 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1100 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1101
1102 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1103 macb_writel(bp, ISR, MACB_BIT(RXUBR));
1104 }
1105
1106 if (status & MACB_BIT(ISR_ROVR)) {
1107 /* We missed at least one packet */
1108 if (macb_is_gem(bp))
1109 bp->hw_stats.gem.rx_overruns++;
1110 else
1111 bp->hw_stats.macb.rx_overruns++;
1112
1113 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1114 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1115 }
1116
1117 if (status & MACB_BIT(HRESP)) {
1118 /*
1119 * TODO: Reset the hardware, and maybe move the
1120 * netdev_err to a lower-priority context as well
1121 * (work queue?)
1122 */
1123 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1124
1125 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1126 queue_writel(queue, ISR, MACB_BIT(HRESP));
1127 }
1128
1129 status = queue_readl(queue, ISR);
1130 }
1131
1132 spin_unlock(&bp->lock);
1133
1134 return IRQ_HANDLED;
1135 }
1136
1137 #ifdef CONFIG_NET_POLL_CONTROLLER
1138 /*
1139 * Polling receive - used by netconsole and other diagnostic tools
1140 * to allow network i/o with interrupts disabled.
1141 */
1142 static void macb_poll_controller(struct net_device *dev)
1143 {
1144 struct macb *bp = netdev_priv(dev);
1145 struct macb_queue *queue;
1146 unsigned long flags;
1147 unsigned int q;
1148
1149 local_irq_save(flags);
1150 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1151 macb_interrupt(dev->irq, queue);
1152 local_irq_restore(flags);
1153 }
1154 #endif
1155
1156 static unsigned int macb_tx_map(struct macb *bp,
1157 struct macb_queue *queue,
1158 struct sk_buff *skb)
1159 {
1160 dma_addr_t mapping;
1161 unsigned int len, entry, i, tx_head = queue->tx_head;
1162 struct macb_tx_skb *tx_skb = NULL;
1163 struct macb_dma_desc *desc;
1164 unsigned int offset, size, count = 0;
1165 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1166 unsigned int eof = 1;
1167 u32 ctrl;
1168
1169 /* First, map non-paged data */
1170 len = skb_headlen(skb);
1171 offset = 0;
1172 while (len) {
1173 size = min(len, bp->max_tx_length);
1174 entry = macb_tx_ring_wrap(tx_head);
1175 tx_skb = &queue->tx_skb[entry];
1176
1177 mapping = dma_map_single(&bp->pdev->dev,
1178 skb->data + offset,
1179 size, DMA_TO_DEVICE);
1180 if (dma_mapping_error(&bp->pdev->dev, mapping))
1181 goto dma_error;
1182
1183 /* Save info to properly release resources */
1184 tx_skb->skb = NULL;
1185 tx_skb->mapping = mapping;
1186 tx_skb->size = size;
1187 tx_skb->mapped_as_page = false;
1188
1189 len -= size;
1190 offset += size;
1191 count++;
1192 tx_head++;
1193 }
1194
1195 /* Then, map paged data from fragments */
1196 for (f = 0; f < nr_frags; f++) {
1197 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1198
1199 len = skb_frag_size(frag);
1200 offset = 0;
1201 while (len) {
1202 size = min(len, bp->max_tx_length);
1203 entry = macb_tx_ring_wrap(tx_head);
1204 tx_skb = &queue->tx_skb[entry];
1205
1206 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1207 offset, size, DMA_TO_DEVICE);
1208 if (dma_mapping_error(&bp->pdev->dev, mapping))
1209 goto dma_error;
1210
1211 /* Save info to properly release resources */
1212 tx_skb->skb = NULL;
1213 tx_skb->mapping = mapping;
1214 tx_skb->size = size;
1215 tx_skb->mapped_as_page = true;
1216
1217 len -= size;
1218 offset += size;
1219 count++;
1220 tx_head++;
1221 }
1222 }
1223
1224 /* Should never happen */
1225 if (unlikely(tx_skb == NULL)) {
1226 netdev_err(bp->dev, "BUG! empty skb!\n");
1227 return 0;
1228 }
1229
1230 /* This is the last buffer of the frame: save socket buffer */
1231 tx_skb->skb = skb;
1232
1233 /* Update TX ring: update buffer descriptors in reverse order
1234 * to avoid race condition
1235 */
1236
1237 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1238 * to set the end of TX queue
1239 */
1240 i = tx_head;
1241 entry = macb_tx_ring_wrap(i);
1242 ctrl = MACB_BIT(TX_USED);
1243 desc = &queue->tx_ring[entry];
1244 desc->ctrl = ctrl;
1245
1246 do {
1247 i--;
1248 entry = macb_tx_ring_wrap(i);
1249 tx_skb = &queue->tx_skb[entry];
1250 desc = &queue->tx_ring[entry];
1251
1252 ctrl = (u32)tx_skb->size;
1253 if (eof) {
1254 ctrl |= MACB_BIT(TX_LAST);
1255 eof = 0;
1256 }
1257 if (unlikely(entry == (TX_RING_SIZE - 1)))
1258 ctrl |= MACB_BIT(TX_WRAP);
1259
1260 /* Set TX buffer descriptor */
1261 desc->addr = tx_skb->mapping;
1262 /* desc->addr must be visible to hardware before clearing
1263 * 'TX_USED' bit in desc->ctrl.
1264 */
1265 wmb();
1266 desc->ctrl = ctrl;
1267 } while (i != queue->tx_head);
1268
1269 queue->tx_head = tx_head;
1270
1271 return count;
1272
1273 dma_error:
1274 netdev_err(bp->dev, "TX DMA map failed\n");
1275
1276 for (i = queue->tx_head; i != tx_head; i++) {
1277 tx_skb = macb_tx_skb(queue, i);
1278
1279 macb_tx_unmap(bp, tx_skb);
1280 }
1281
1282 return 0;
1283 }
1284
1285 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1286 {
1287 u16 queue_index = skb_get_queue_mapping(skb);
1288 struct macb *bp = netdev_priv(dev);
1289 struct macb_queue *queue = &bp->queues[queue_index];
1290 unsigned long flags;
1291 unsigned int count, nr_frags, frag_size, f;
1292
1293 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1294 netdev_vdbg(bp->dev,
1295 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1296 queue_index, skb->len, skb->head, skb->data,
1297 skb_tail_pointer(skb), skb_end_pointer(skb));
1298 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1299 skb->data, 16, true);
1300 #endif
1301
1302 /* Count how many TX buffer descriptors are needed to send this
1303 * socket buffer: skb fragments of jumbo frames may need to be
1304 * splitted into many buffer descriptors.
1305 */
1306 count = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
1307 nr_frags = skb_shinfo(skb)->nr_frags;
1308 for (f = 0; f < nr_frags; f++) {
1309 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1310 count += DIV_ROUND_UP(frag_size, bp->max_tx_length);
1311 }
1312
1313 spin_lock_irqsave(&bp->lock, flags);
1314
1315 /* This is a hard error, log it. */
1316 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < count) {
1317 netif_stop_subqueue(dev, queue_index);
1318 spin_unlock_irqrestore(&bp->lock, flags);
1319 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1320 queue->tx_head, queue->tx_tail);
1321 return NETDEV_TX_BUSY;
1322 }
1323
1324 /* Map socket buffer for DMA transfer */
1325 if (!macb_tx_map(bp, queue, skb)) {
1326 dev_kfree_skb_any(skb);
1327 goto unlock;
1328 }
1329
1330 /* Make newly initialized descriptor visible to hardware */
1331 wmb();
1332
1333 skb_tx_timestamp(skb);
1334
1335 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1336
1337 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < 1)
1338 netif_stop_subqueue(dev, queue_index);
1339
1340 unlock:
1341 spin_unlock_irqrestore(&bp->lock, flags);
1342
1343 return NETDEV_TX_OK;
1344 }
1345
1346 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1347 {
1348 if (!macb_is_gem(bp)) {
1349 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1350 } else {
1351 bp->rx_buffer_size = size;
1352
1353 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1354 netdev_dbg(bp->dev,
1355 "RX buffer must be multiple of %d bytes, expanding\n",
1356 RX_BUFFER_MULTIPLE);
1357 bp->rx_buffer_size =
1358 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1359 }
1360 }
1361
1362 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n",
1363 bp->dev->mtu, bp->rx_buffer_size);
1364 }
1365
1366 static void gem_free_rx_buffers(struct macb *bp)
1367 {
1368 struct sk_buff *skb;
1369 struct macb_dma_desc *desc;
1370 dma_addr_t addr;
1371 int i;
1372
1373 if (!bp->rx_skbuff)
1374 return;
1375
1376 for (i = 0; i < RX_RING_SIZE; i++) {
1377 skb = bp->rx_skbuff[i];
1378
1379 if (skb == NULL)
1380 continue;
1381
1382 desc = &bp->rx_ring[i];
1383 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1384 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
1385 DMA_FROM_DEVICE);
1386 dev_kfree_skb_any(skb);
1387 skb = NULL;
1388 }
1389
1390 kfree(bp->rx_skbuff);
1391 bp->rx_skbuff = NULL;
1392 }
1393
1394 static void macb_free_rx_buffers(struct macb *bp)
1395 {
1396 if (bp->rx_buffers) {
1397 dma_free_coherent(&bp->pdev->dev,
1398 RX_RING_SIZE * bp->rx_buffer_size,
1399 bp->rx_buffers, bp->rx_buffers_dma);
1400 bp->rx_buffers = NULL;
1401 }
1402 }
1403
1404 static void macb_free_consistent(struct macb *bp)
1405 {
1406 struct macb_queue *queue;
1407 unsigned int q;
1408
1409 bp->macbgem_ops.mog_free_rx_buffers(bp);
1410 if (bp->rx_ring) {
1411 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
1412 bp->rx_ring, bp->rx_ring_dma);
1413 bp->rx_ring = NULL;
1414 }
1415
1416 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1417 kfree(queue->tx_skb);
1418 queue->tx_skb = NULL;
1419 if (queue->tx_ring) {
1420 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
1421 queue->tx_ring, queue->tx_ring_dma);
1422 queue->tx_ring = NULL;
1423 }
1424 }
1425 }
1426
1427 static int gem_alloc_rx_buffers(struct macb *bp)
1428 {
1429 int size;
1430
1431 size = RX_RING_SIZE * sizeof(struct sk_buff *);
1432 bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
1433 if (!bp->rx_skbuff)
1434 return -ENOMEM;
1435 else
1436 netdev_dbg(bp->dev,
1437 "Allocated %d RX struct sk_buff entries at %p\n",
1438 RX_RING_SIZE, bp->rx_skbuff);
1439 return 0;
1440 }
1441
1442 static int macb_alloc_rx_buffers(struct macb *bp)
1443 {
1444 int size;
1445
1446 size = RX_RING_SIZE * bp->rx_buffer_size;
1447 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1448 &bp->rx_buffers_dma, GFP_KERNEL);
1449 if (!bp->rx_buffers)
1450 return -ENOMEM;
1451 else
1452 netdev_dbg(bp->dev,
1453 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1454 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
1455 return 0;
1456 }
1457
1458 static int macb_alloc_consistent(struct macb *bp)
1459 {
1460 struct macb_queue *queue;
1461 unsigned int q;
1462 int size;
1463
1464 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1465 size = TX_RING_BYTES;
1466 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1467 &queue->tx_ring_dma,
1468 GFP_KERNEL);
1469 if (!queue->tx_ring)
1470 goto out_err;
1471 netdev_dbg(bp->dev,
1472 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
1473 q, size, (unsigned long)queue->tx_ring_dma,
1474 queue->tx_ring);
1475
1476 size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
1477 queue->tx_skb = kmalloc(size, GFP_KERNEL);
1478 if (!queue->tx_skb)
1479 goto out_err;
1480 }
1481
1482 size = RX_RING_BYTES;
1483 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1484 &bp->rx_ring_dma, GFP_KERNEL);
1485 if (!bp->rx_ring)
1486 goto out_err;
1487 netdev_dbg(bp->dev,
1488 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1489 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
1490
1491 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
1492 goto out_err;
1493
1494 return 0;
1495
1496 out_err:
1497 macb_free_consistent(bp);
1498 return -ENOMEM;
1499 }
1500
1501 static void gem_init_rings(struct macb *bp)
1502 {
1503 struct macb_queue *queue;
1504 unsigned int q;
1505 int i;
1506
1507 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1508 for (i = 0; i < TX_RING_SIZE; i++) {
1509 queue->tx_ring[i].addr = 0;
1510 queue->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1511 }
1512 queue->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1513 queue->tx_head = 0;
1514 queue->tx_tail = 0;
1515 }
1516
1517 bp->rx_tail = 0;
1518 bp->rx_prepared_head = 0;
1519
1520 gem_rx_refill(bp);
1521 }
1522
1523 static void macb_init_rings(struct macb *bp)
1524 {
1525 int i;
1526 dma_addr_t addr;
1527
1528 addr = bp->rx_buffers_dma;
1529 for (i = 0; i < RX_RING_SIZE; i++) {
1530 bp->rx_ring[i].addr = addr;
1531 bp->rx_ring[i].ctrl = 0;
1532 addr += bp->rx_buffer_size;
1533 }
1534 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
1535
1536 for (i = 0; i < TX_RING_SIZE; i++) {
1537 bp->queues[0].tx_ring[i].addr = 0;
1538 bp->queues[0].tx_ring[i].ctrl = MACB_BIT(TX_USED);
1539 }
1540 bp->queues[0].tx_head = 0;
1541 bp->queues[0].tx_tail = 0;
1542 bp->queues[0].tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1543
1544 bp->rx_tail = 0;
1545 }
1546
1547 static void macb_reset_hw(struct macb *bp)
1548 {
1549 struct macb_queue *queue;
1550 unsigned int q;
1551
1552 /*
1553 * Disable RX and TX (XXX: Should we halt the transmission
1554 * more gracefully?)
1555 */
1556 macb_writel(bp, NCR, 0);
1557
1558 /* Clear the stats registers (XXX: Update stats first?) */
1559 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
1560
1561 /* Clear all status flags */
1562 macb_writel(bp, TSR, -1);
1563 macb_writel(bp, RSR, -1);
1564
1565 /* Disable all interrupts */
1566 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1567 queue_writel(queue, IDR, -1);
1568 queue_readl(queue, ISR);
1569 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1570 queue_writel(queue, ISR, -1);
1571 }
1572 }
1573
1574 static u32 gem_mdc_clk_div(struct macb *bp)
1575 {
1576 u32 config;
1577 unsigned long pclk_hz = clk_get_rate(bp->pclk);
1578
1579 if (pclk_hz <= 20000000)
1580 config = GEM_BF(CLK, GEM_CLK_DIV8);
1581 else if (pclk_hz <= 40000000)
1582 config = GEM_BF(CLK, GEM_CLK_DIV16);
1583 else if (pclk_hz <= 80000000)
1584 config = GEM_BF(CLK, GEM_CLK_DIV32);
1585 else if (pclk_hz <= 120000000)
1586 config = GEM_BF(CLK, GEM_CLK_DIV48);
1587 else if (pclk_hz <= 160000000)
1588 config = GEM_BF(CLK, GEM_CLK_DIV64);
1589 else
1590 config = GEM_BF(CLK, GEM_CLK_DIV96);
1591
1592 return config;
1593 }
1594
1595 static u32 macb_mdc_clk_div(struct macb *bp)
1596 {
1597 u32 config;
1598 unsigned long pclk_hz;
1599
1600 if (macb_is_gem(bp))
1601 return gem_mdc_clk_div(bp);
1602
1603 pclk_hz = clk_get_rate(bp->pclk);
1604 if (pclk_hz <= 20000000)
1605 config = MACB_BF(CLK, MACB_CLK_DIV8);
1606 else if (pclk_hz <= 40000000)
1607 config = MACB_BF(CLK, MACB_CLK_DIV16);
1608 else if (pclk_hz <= 80000000)
1609 config = MACB_BF(CLK, MACB_CLK_DIV32);
1610 else
1611 config = MACB_BF(CLK, MACB_CLK_DIV64);
1612
1613 return config;
1614 }
1615
1616 /*
1617 * Get the DMA bus width field of the network configuration register that we
1618 * should program. We find the width from decoding the design configuration
1619 * register to find the maximum supported data bus width.
1620 */
1621 static u32 macb_dbw(struct macb *bp)
1622 {
1623 if (!macb_is_gem(bp))
1624 return 0;
1625
1626 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1627 case 4:
1628 return GEM_BF(DBW, GEM_DBW128);
1629 case 2:
1630 return GEM_BF(DBW, GEM_DBW64);
1631 case 1:
1632 default:
1633 return GEM_BF(DBW, GEM_DBW32);
1634 }
1635 }
1636
1637 /*
1638 * Configure the receive DMA engine
1639 * - use the correct receive buffer size
1640 * - set best burst length for DMA operations
1641 * (if not supported by FIFO, it will fallback to default)
1642 * - set both rx/tx packet buffers to full memory size
1643 * These are configurable parameters for GEM.
1644 */
1645 static void macb_configure_dma(struct macb *bp)
1646 {
1647 u32 dmacfg;
1648
1649 if (macb_is_gem(bp)) {
1650 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1651 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
1652 if (bp->dma_burst_length)
1653 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
1654 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
1655 dmacfg &= ~GEM_BIT(ENDIA_PKT);
1656
1657 if (bp->native_io)
1658 dmacfg &= ~GEM_BIT(ENDIA_DESC);
1659 else
1660 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
1661
1662 if (bp->dev->features & NETIF_F_HW_CSUM)
1663 dmacfg |= GEM_BIT(TXCOEN);
1664 else
1665 dmacfg &= ~GEM_BIT(TXCOEN);
1666 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
1667 dmacfg);
1668 gem_writel(bp, DMACFG, dmacfg);
1669 }
1670 }
1671
1672 static void macb_init_hw(struct macb *bp)
1673 {
1674 struct macb_queue *queue;
1675 unsigned int q;
1676
1677 u32 config;
1678
1679 macb_reset_hw(bp);
1680 macb_set_hwaddr(bp);
1681
1682 config = macb_mdc_clk_div(bp);
1683 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
1684 config |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
1685 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
1686 config |= MACB_BIT(PAE); /* PAuse Enable */
1687 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
1688 if (bp->caps & MACB_CAPS_JUMBO)
1689 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
1690 else
1691 config |= MACB_BIT(BIG); /* Receive oversized frames */
1692 if (bp->dev->flags & IFF_PROMISC)
1693 config |= MACB_BIT(CAF); /* Copy All Frames */
1694 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
1695 config |= GEM_BIT(RXCOEN);
1696 if (!(bp->dev->flags & IFF_BROADCAST))
1697 config |= MACB_BIT(NBC); /* No BroadCast */
1698 config |= macb_dbw(bp);
1699 macb_writel(bp, NCFGR, config);
1700 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
1701 gem_writel(bp, JML, bp->jumbo_max_len);
1702 bp->speed = SPEED_10;
1703 bp->duplex = DUPLEX_HALF;
1704 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
1705 if (bp->caps & MACB_CAPS_JUMBO)
1706 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
1707
1708 macb_configure_dma(bp);
1709
1710 /* Initialize TX and RX buffers */
1711 macb_writel(bp, RBQP, bp->rx_ring_dma);
1712 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1713 queue_writel(queue, TBQP, queue->tx_ring_dma);
1714
1715 /* Enable interrupts */
1716 queue_writel(queue, IER,
1717 MACB_RX_INT_FLAGS |
1718 MACB_TX_INT_FLAGS |
1719 MACB_BIT(HRESP));
1720 }
1721
1722 /* Enable TX and RX */
1723 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
1724 }
1725
1726 /*
1727 * The hash address register is 64 bits long and takes up two
1728 * locations in the memory map. The least significant bits are stored
1729 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1730 *
1731 * The unicast hash enable and the multicast hash enable bits in the
1732 * network configuration register enable the reception of hash matched
1733 * frames. The destination address is reduced to a 6 bit index into
1734 * the 64 bit hash register using the following hash function. The
1735 * hash function is an exclusive or of every sixth bit of the
1736 * destination address.
1737 *
1738 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1739 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1740 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1741 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1742 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1743 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1744 *
1745 * da[0] represents the least significant bit of the first byte
1746 * received, that is, the multicast/unicast indicator, and da[47]
1747 * represents the most significant bit of the last byte received. If
1748 * the hash index, hi[n], points to a bit that is set in the hash
1749 * register then the frame will be matched according to whether the
1750 * frame is multicast or unicast. A multicast match will be signalled
1751 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1752 * index points to a bit set in the hash register. A unicast match
1753 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1754 * and the hash index points to a bit set in the hash register. To
1755 * receive all multicast frames, the hash register should be set with
1756 * all ones and the multicast hash enable bit should be set in the
1757 * network configuration register.
1758 */
1759
1760 static inline int hash_bit_value(int bitnr, __u8 *addr)
1761 {
1762 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1763 return 1;
1764 return 0;
1765 }
1766
1767 /*
1768 * Return the hash index value for the specified address.
1769 */
1770 static int hash_get_index(__u8 *addr)
1771 {
1772 int i, j, bitval;
1773 int hash_index = 0;
1774
1775 for (j = 0; j < 6; j++) {
1776 for (i = 0, bitval = 0; i < 8; i++)
1777 bitval ^= hash_bit_value(i * 6 + j, addr);
1778
1779 hash_index |= (bitval << j);
1780 }
1781
1782 return hash_index;
1783 }
1784
1785 /*
1786 * Add multicast addresses to the internal multicast-hash table.
1787 */
1788 static void macb_sethashtable(struct net_device *dev)
1789 {
1790 struct netdev_hw_addr *ha;
1791 unsigned long mc_filter[2];
1792 unsigned int bitnr;
1793 struct macb *bp = netdev_priv(dev);
1794
1795 mc_filter[0] = mc_filter[1] = 0;
1796
1797 netdev_for_each_mc_addr(ha, dev) {
1798 bitnr = hash_get_index(ha->addr);
1799 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1800 }
1801
1802 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1803 macb_or_gem_writel(bp, HRT, mc_filter[1]);
1804 }
1805
1806 /*
1807 * Enable/Disable promiscuous and multicast modes.
1808 */
1809 static void macb_set_rx_mode(struct net_device *dev)
1810 {
1811 unsigned long cfg;
1812 struct macb *bp = netdev_priv(dev);
1813
1814 cfg = macb_readl(bp, NCFGR);
1815
1816 if (dev->flags & IFF_PROMISC) {
1817 /* Enable promiscuous mode */
1818 cfg |= MACB_BIT(CAF);
1819
1820 /* Disable RX checksum offload */
1821 if (macb_is_gem(bp))
1822 cfg &= ~GEM_BIT(RXCOEN);
1823 } else {
1824 /* Disable promiscuous mode */
1825 cfg &= ~MACB_BIT(CAF);
1826
1827 /* Enable RX checksum offload only if requested */
1828 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
1829 cfg |= GEM_BIT(RXCOEN);
1830 }
1831
1832 if (dev->flags & IFF_ALLMULTI) {
1833 /* Enable all multicast mode */
1834 macb_or_gem_writel(bp, HRB, -1);
1835 macb_or_gem_writel(bp, HRT, -1);
1836 cfg |= MACB_BIT(NCFGR_MTI);
1837 } else if (!netdev_mc_empty(dev)) {
1838 /* Enable specific multicasts */
1839 macb_sethashtable(dev);
1840 cfg |= MACB_BIT(NCFGR_MTI);
1841 } else if (dev->flags & (~IFF_ALLMULTI)) {
1842 /* Disable all multicast mode */
1843 macb_or_gem_writel(bp, HRB, 0);
1844 macb_or_gem_writel(bp, HRT, 0);
1845 cfg &= ~MACB_BIT(NCFGR_MTI);
1846 }
1847
1848 macb_writel(bp, NCFGR, cfg);
1849 }
1850
1851 static int macb_open(struct net_device *dev)
1852 {
1853 struct macb *bp = netdev_priv(dev);
1854 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
1855 int err;
1856
1857 netdev_dbg(bp->dev, "open\n");
1858
1859 /* carrier starts down */
1860 netif_carrier_off(dev);
1861
1862 /* if the phy is not yet register, retry later*/
1863 if (!bp->phy_dev)
1864 return -EAGAIN;
1865
1866 /* RX buffers initialization */
1867 macb_init_rx_buffer_size(bp, bufsz);
1868
1869 err = macb_alloc_consistent(bp);
1870 if (err) {
1871 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1872 err);
1873 return err;
1874 }
1875
1876 napi_enable(&bp->napi);
1877
1878 bp->macbgem_ops.mog_init_rings(bp);
1879 macb_init_hw(bp);
1880
1881 /* schedule a link state check */
1882 phy_start(bp->phy_dev);
1883
1884 netif_tx_start_all_queues(dev);
1885
1886 return 0;
1887 }
1888
1889 static int macb_close(struct net_device *dev)
1890 {
1891 struct macb *bp = netdev_priv(dev);
1892 unsigned long flags;
1893
1894 netif_tx_stop_all_queues(dev);
1895 napi_disable(&bp->napi);
1896
1897 if (bp->phy_dev)
1898 phy_stop(bp->phy_dev);
1899
1900 spin_lock_irqsave(&bp->lock, flags);
1901 macb_reset_hw(bp);
1902 netif_carrier_off(dev);
1903 spin_unlock_irqrestore(&bp->lock, flags);
1904
1905 macb_free_consistent(bp);
1906
1907 return 0;
1908 }
1909
1910 static int macb_change_mtu(struct net_device *dev, int new_mtu)
1911 {
1912 struct macb *bp = netdev_priv(dev);
1913 u32 max_mtu;
1914
1915 if (netif_running(dev))
1916 return -EBUSY;
1917
1918 max_mtu = ETH_DATA_LEN;
1919 if (bp->caps & MACB_CAPS_JUMBO)
1920 max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
1921
1922 if ((new_mtu > max_mtu) || (new_mtu < GEM_MTU_MIN_SIZE))
1923 return -EINVAL;
1924
1925 dev->mtu = new_mtu;
1926
1927 return 0;
1928 }
1929
1930 static void gem_update_stats(struct macb *bp)
1931 {
1932 unsigned int i;
1933 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1934
1935 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
1936 u32 offset = gem_statistics[i].offset;
1937 u64 val = bp->macb_reg_readl(bp, offset);
1938
1939 bp->ethtool_stats[i] += val;
1940 *p += val;
1941
1942 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
1943 /* Add GEM_OCTTXH, GEM_OCTRXH */
1944 val = bp->macb_reg_readl(bp, offset + 4);
1945 bp->ethtool_stats[i] += ((u64)val) << 32;
1946 *(++p) += val;
1947 }
1948 }
1949 }
1950
1951 static struct net_device_stats *gem_get_stats(struct macb *bp)
1952 {
1953 struct gem_stats *hwstat = &bp->hw_stats.gem;
1954 struct net_device_stats *nstat = &bp->stats;
1955
1956 gem_update_stats(bp);
1957
1958 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1959 hwstat->rx_alignment_errors +
1960 hwstat->rx_resource_errors +
1961 hwstat->rx_overruns +
1962 hwstat->rx_oversize_frames +
1963 hwstat->rx_jabbers +
1964 hwstat->rx_undersized_frames +
1965 hwstat->rx_length_field_frame_errors);
1966 nstat->tx_errors = (hwstat->tx_late_collisions +
1967 hwstat->tx_excessive_collisions +
1968 hwstat->tx_underrun +
1969 hwstat->tx_carrier_sense_errors);
1970 nstat->multicast = hwstat->rx_multicast_frames;
1971 nstat->collisions = (hwstat->tx_single_collision_frames +
1972 hwstat->tx_multiple_collision_frames +
1973 hwstat->tx_excessive_collisions);
1974 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1975 hwstat->rx_jabbers +
1976 hwstat->rx_undersized_frames +
1977 hwstat->rx_length_field_frame_errors);
1978 nstat->rx_over_errors = hwstat->rx_resource_errors;
1979 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1980 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1981 nstat->rx_fifo_errors = hwstat->rx_overruns;
1982 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1983 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1984 nstat->tx_fifo_errors = hwstat->tx_underrun;
1985
1986 return nstat;
1987 }
1988
1989 static void gem_get_ethtool_stats(struct net_device *dev,
1990 struct ethtool_stats *stats, u64 *data)
1991 {
1992 struct macb *bp;
1993
1994 bp = netdev_priv(dev);
1995 gem_update_stats(bp);
1996 memcpy(data, &bp->ethtool_stats, sizeof(u64) * GEM_STATS_LEN);
1997 }
1998
1999 static int gem_get_sset_count(struct net_device *dev, int sset)
2000 {
2001 switch (sset) {
2002 case ETH_SS_STATS:
2003 return GEM_STATS_LEN;
2004 default:
2005 return -EOPNOTSUPP;
2006 }
2007 }
2008
2009 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2010 {
2011 unsigned int i;
2012
2013 switch (sset) {
2014 case ETH_SS_STATS:
2015 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2016 memcpy(p, gem_statistics[i].stat_string,
2017 ETH_GSTRING_LEN);
2018 break;
2019 }
2020 }
2021
2022 static struct net_device_stats *macb_get_stats(struct net_device *dev)
2023 {
2024 struct macb *bp = netdev_priv(dev);
2025 struct net_device_stats *nstat = &bp->stats;
2026 struct macb_stats *hwstat = &bp->hw_stats.macb;
2027
2028 if (macb_is_gem(bp))
2029 return gem_get_stats(bp);
2030
2031 /* read stats from hardware */
2032 macb_update_stats(bp);
2033
2034 /* Convert HW stats into netdevice stats */
2035 nstat->rx_errors = (hwstat->rx_fcs_errors +
2036 hwstat->rx_align_errors +
2037 hwstat->rx_resource_errors +
2038 hwstat->rx_overruns +
2039 hwstat->rx_oversize_pkts +
2040 hwstat->rx_jabbers +
2041 hwstat->rx_undersize_pkts +
2042 hwstat->rx_length_mismatch);
2043 nstat->tx_errors = (hwstat->tx_late_cols +
2044 hwstat->tx_excessive_cols +
2045 hwstat->tx_underruns +
2046 hwstat->tx_carrier_errors +
2047 hwstat->sqe_test_errors);
2048 nstat->collisions = (hwstat->tx_single_cols +
2049 hwstat->tx_multiple_cols +
2050 hwstat->tx_excessive_cols);
2051 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2052 hwstat->rx_jabbers +
2053 hwstat->rx_undersize_pkts +
2054 hwstat->rx_length_mismatch);
2055 nstat->rx_over_errors = hwstat->rx_resource_errors +
2056 hwstat->rx_overruns;
2057 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2058 nstat->rx_frame_errors = hwstat->rx_align_errors;
2059 nstat->rx_fifo_errors = hwstat->rx_overruns;
2060 /* XXX: What does "missed" mean? */
2061 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2062 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2063 nstat->tx_fifo_errors = hwstat->tx_underruns;
2064 /* Don't know about heartbeat or window errors... */
2065
2066 return nstat;
2067 }
2068
2069 static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2070 {
2071 struct macb *bp = netdev_priv(dev);
2072 struct phy_device *phydev = bp->phy_dev;
2073
2074 if (!phydev)
2075 return -ENODEV;
2076
2077 return phy_ethtool_gset(phydev, cmd);
2078 }
2079
2080 static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2081 {
2082 struct macb *bp = netdev_priv(dev);
2083 struct phy_device *phydev = bp->phy_dev;
2084
2085 if (!phydev)
2086 return -ENODEV;
2087
2088 return phy_ethtool_sset(phydev, cmd);
2089 }
2090
2091 static int macb_get_regs_len(struct net_device *netdev)
2092 {
2093 return MACB_GREGS_NBR * sizeof(u32);
2094 }
2095
2096 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2097 void *p)
2098 {
2099 struct macb *bp = netdev_priv(dev);
2100 unsigned int tail, head;
2101 u32 *regs_buff = p;
2102
2103 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2104 | MACB_GREGS_VERSION;
2105
2106 tail = macb_tx_ring_wrap(bp->queues[0].tx_tail);
2107 head = macb_tx_ring_wrap(bp->queues[0].tx_head);
2108
2109 regs_buff[0] = macb_readl(bp, NCR);
2110 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2111 regs_buff[2] = macb_readl(bp, NSR);
2112 regs_buff[3] = macb_readl(bp, TSR);
2113 regs_buff[4] = macb_readl(bp, RBQP);
2114 regs_buff[5] = macb_readl(bp, TBQP);
2115 regs_buff[6] = macb_readl(bp, RSR);
2116 regs_buff[7] = macb_readl(bp, IMR);
2117
2118 regs_buff[8] = tail;
2119 regs_buff[9] = head;
2120 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2121 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
2122
2123 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
2124 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
2125 if (macb_is_gem(bp)) {
2126 regs_buff[13] = gem_readl(bp, DMACFG);
2127 }
2128 }
2129
2130 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2131 {
2132 struct macb *bp = netdev_priv(netdev);
2133
2134 wol->supported = 0;
2135 wol->wolopts = 0;
2136
2137 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
2138 wol->supported = WAKE_MAGIC;
2139
2140 if (bp->wol & MACB_WOL_ENABLED)
2141 wol->wolopts |= WAKE_MAGIC;
2142 }
2143 }
2144
2145 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2146 {
2147 struct macb *bp = netdev_priv(netdev);
2148
2149 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
2150 (wol->wolopts & ~WAKE_MAGIC))
2151 return -EOPNOTSUPP;
2152
2153 if (wol->wolopts & WAKE_MAGIC)
2154 bp->wol |= MACB_WOL_ENABLED;
2155 else
2156 bp->wol &= ~MACB_WOL_ENABLED;
2157
2158 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
2159
2160 return 0;
2161 }
2162
2163 static const struct ethtool_ops macb_ethtool_ops = {
2164 .get_settings = macb_get_settings,
2165 .set_settings = macb_set_settings,
2166 .get_regs_len = macb_get_regs_len,
2167 .get_regs = macb_get_regs,
2168 .get_link = ethtool_op_get_link,
2169 .get_ts_info = ethtool_op_get_ts_info,
2170 .get_wol = macb_get_wol,
2171 .set_wol = macb_set_wol,
2172 };
2173
2174 static const struct ethtool_ops gem_ethtool_ops = {
2175 .get_settings = macb_get_settings,
2176 .set_settings = macb_set_settings,
2177 .get_regs_len = macb_get_regs_len,
2178 .get_regs = macb_get_regs,
2179 .get_link = ethtool_op_get_link,
2180 .get_ts_info = ethtool_op_get_ts_info,
2181 .get_ethtool_stats = gem_get_ethtool_stats,
2182 .get_strings = gem_get_ethtool_strings,
2183 .get_sset_count = gem_get_sset_count,
2184 };
2185
2186 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2187 {
2188 struct macb *bp = netdev_priv(dev);
2189 struct phy_device *phydev = bp->phy_dev;
2190
2191 if (!netif_running(dev))
2192 return -EINVAL;
2193
2194 if (!phydev)
2195 return -ENODEV;
2196
2197 return phy_mii_ioctl(phydev, rq, cmd);
2198 }
2199
2200 static int macb_set_features(struct net_device *netdev,
2201 netdev_features_t features)
2202 {
2203 struct macb *bp = netdev_priv(netdev);
2204 netdev_features_t changed = features ^ netdev->features;
2205
2206 /* TX checksum offload */
2207 if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
2208 u32 dmacfg;
2209
2210 dmacfg = gem_readl(bp, DMACFG);
2211 if (features & NETIF_F_HW_CSUM)
2212 dmacfg |= GEM_BIT(TXCOEN);
2213 else
2214 dmacfg &= ~GEM_BIT(TXCOEN);
2215 gem_writel(bp, DMACFG, dmacfg);
2216 }
2217
2218 /* RX checksum offload */
2219 if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
2220 u32 netcfg;
2221
2222 netcfg = gem_readl(bp, NCFGR);
2223 if (features & NETIF_F_RXCSUM &&
2224 !(netdev->flags & IFF_PROMISC))
2225 netcfg |= GEM_BIT(RXCOEN);
2226 else
2227 netcfg &= ~GEM_BIT(RXCOEN);
2228 gem_writel(bp, NCFGR, netcfg);
2229 }
2230
2231 return 0;
2232 }
2233
2234 static const struct net_device_ops macb_netdev_ops = {
2235 .ndo_open = macb_open,
2236 .ndo_stop = macb_close,
2237 .ndo_start_xmit = macb_start_xmit,
2238 .ndo_set_rx_mode = macb_set_rx_mode,
2239 .ndo_get_stats = macb_get_stats,
2240 .ndo_do_ioctl = macb_ioctl,
2241 .ndo_validate_addr = eth_validate_addr,
2242 .ndo_change_mtu = macb_change_mtu,
2243 .ndo_set_mac_address = eth_mac_addr,
2244 #ifdef CONFIG_NET_POLL_CONTROLLER
2245 .ndo_poll_controller = macb_poll_controller,
2246 #endif
2247 .ndo_set_features = macb_set_features,
2248 };
2249
2250 /*
2251 * Configure peripheral capabilities according to device tree
2252 * and integration options used
2253 */
2254 static void macb_configure_caps(struct macb *bp, const struct macb_config *dt_conf)
2255 {
2256 u32 dcfg;
2257
2258 if (dt_conf)
2259 bp->caps = dt_conf->caps;
2260
2261 if (hw_is_gem(bp->regs, bp->native_io)) {
2262 bp->caps |= MACB_CAPS_MACB_IS_GEM;
2263
2264 dcfg = gem_readl(bp, DCFG1);
2265 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
2266 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
2267 dcfg = gem_readl(bp, DCFG2);
2268 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
2269 bp->caps |= MACB_CAPS_FIFO_MODE;
2270 }
2271
2272 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
2273 }
2274
2275 static void macb_probe_queues(void __iomem *mem,
2276 bool native_io,
2277 unsigned int *queue_mask,
2278 unsigned int *num_queues)
2279 {
2280 unsigned int hw_q;
2281
2282 *queue_mask = 0x1;
2283 *num_queues = 1;
2284
2285 /* is it macb or gem ?
2286 *
2287 * We need to read directly from the hardware here because
2288 * we are early in the probe process and don't have the
2289 * MACB_CAPS_MACB_IS_GEM flag positioned
2290 */
2291 if (!hw_is_gem(mem, native_io))
2292 return;
2293
2294 /* bit 0 is never set but queue 0 always exists */
2295 *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
2296
2297 *queue_mask |= 0x1;
2298
2299 for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
2300 if (*queue_mask & (1 << hw_q))
2301 (*num_queues)++;
2302 }
2303
2304 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
2305 struct clk **hclk, struct clk **tx_clk)
2306 {
2307 int err;
2308
2309 *pclk = devm_clk_get(&pdev->dev, "pclk");
2310 if (IS_ERR(*pclk)) {
2311 err = PTR_ERR(*pclk);
2312 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
2313 return err;
2314 }
2315
2316 *hclk = devm_clk_get(&pdev->dev, "hclk");
2317 if (IS_ERR(*hclk)) {
2318 err = PTR_ERR(*hclk);
2319 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
2320 return err;
2321 }
2322
2323 *tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
2324 if (IS_ERR(*tx_clk))
2325 *tx_clk = NULL;
2326
2327 err = clk_prepare_enable(*pclk);
2328 if (err) {
2329 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
2330 return err;
2331 }
2332
2333 err = clk_prepare_enable(*hclk);
2334 if (err) {
2335 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
2336 goto err_disable_pclk;
2337 }
2338
2339 err = clk_prepare_enable(*tx_clk);
2340 if (err) {
2341 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
2342 goto err_disable_hclk;
2343 }
2344
2345 return 0;
2346
2347 err_disable_hclk:
2348 clk_disable_unprepare(*hclk);
2349
2350 err_disable_pclk:
2351 clk_disable_unprepare(*pclk);
2352
2353 return err;
2354 }
2355
2356 static int macb_init(struct platform_device *pdev)
2357 {
2358 struct net_device *dev = platform_get_drvdata(pdev);
2359 unsigned int hw_q, q;
2360 struct macb *bp = netdev_priv(dev);
2361 struct macb_queue *queue;
2362 int err;
2363 u32 val;
2364
2365 /* set the queue register mapping once for all: queue0 has a special
2366 * register mapping but we don't want to test the queue index then
2367 * compute the corresponding register offset at run time.
2368 */
2369 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
2370 if (!(bp->queue_mask & (1 << hw_q)))
2371 continue;
2372
2373 queue = &bp->queues[q];
2374 queue->bp = bp;
2375 if (hw_q) {
2376 queue->ISR = GEM_ISR(hw_q - 1);
2377 queue->IER = GEM_IER(hw_q - 1);
2378 queue->IDR = GEM_IDR(hw_q - 1);
2379 queue->IMR = GEM_IMR(hw_q - 1);
2380 queue->TBQP = GEM_TBQP(hw_q - 1);
2381 } else {
2382 /* queue0 uses legacy registers */
2383 queue->ISR = MACB_ISR;
2384 queue->IER = MACB_IER;
2385 queue->IDR = MACB_IDR;
2386 queue->IMR = MACB_IMR;
2387 queue->TBQP = MACB_TBQP;
2388 }
2389
2390 /* get irq: here we use the linux queue index, not the hardware
2391 * queue index. the queue irq definitions in the device tree
2392 * must remove the optional gaps that could exist in the
2393 * hardware queue mask.
2394 */
2395 queue->irq = platform_get_irq(pdev, q);
2396 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
2397 IRQF_SHARED, dev->name, queue);
2398 if (err) {
2399 dev_err(&pdev->dev,
2400 "Unable to request IRQ %d (error %d)\n",
2401 queue->irq, err);
2402 return err;
2403 }
2404
2405 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
2406 q++;
2407 }
2408
2409 dev->netdev_ops = &macb_netdev_ops;
2410 netif_napi_add(dev, &bp->napi, macb_poll, 64);
2411
2412 /* setup appropriated routines according to adapter type */
2413 if (macb_is_gem(bp)) {
2414 bp->max_tx_length = GEM_MAX_TX_LEN;
2415 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
2416 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
2417 bp->macbgem_ops.mog_init_rings = gem_init_rings;
2418 bp->macbgem_ops.mog_rx = gem_rx;
2419 dev->ethtool_ops = &gem_ethtool_ops;
2420 } else {
2421 bp->max_tx_length = MACB_MAX_TX_LEN;
2422 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
2423 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
2424 bp->macbgem_ops.mog_init_rings = macb_init_rings;
2425 bp->macbgem_ops.mog_rx = macb_rx;
2426 dev->ethtool_ops = &macb_ethtool_ops;
2427 }
2428
2429 /* Set features */
2430 dev->hw_features = NETIF_F_SG;
2431 /* Checksum offload is only available on gem with packet buffer */
2432 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
2433 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
2434 if (bp->caps & MACB_CAPS_SG_DISABLED)
2435 dev->hw_features &= ~NETIF_F_SG;
2436 dev->features = dev->hw_features;
2437
2438 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
2439 val = 0;
2440 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
2441 val = GEM_BIT(RGMII);
2442 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
2443 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
2444 val = MACB_BIT(RMII);
2445 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
2446 val = MACB_BIT(MII);
2447
2448 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
2449 val |= MACB_BIT(CLKEN);
2450
2451 macb_or_gem_writel(bp, USRIO, val);
2452 }
2453
2454 /* Set MII management clock divider */
2455 val = macb_mdc_clk_div(bp);
2456 val |= macb_dbw(bp);
2457 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
2458 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
2459 macb_writel(bp, NCFGR, val);
2460
2461 return 0;
2462 }
2463
2464 #if defined(CONFIG_OF)
2465 /* 1518 rounded up */
2466 #define AT91ETHER_MAX_RBUFF_SZ 0x600
2467 /* max number of receive buffers */
2468 #define AT91ETHER_MAX_RX_DESCR 9
2469
2470 /* Initialize and start the Receiver and Transmit subsystems */
2471 static int at91ether_start(struct net_device *dev)
2472 {
2473 struct macb *lp = netdev_priv(dev);
2474 dma_addr_t addr;
2475 u32 ctl;
2476 int i;
2477
2478 lp->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
2479 (AT91ETHER_MAX_RX_DESCR *
2480 sizeof(struct macb_dma_desc)),
2481 &lp->rx_ring_dma, GFP_KERNEL);
2482 if (!lp->rx_ring)
2483 return -ENOMEM;
2484
2485 lp->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
2486 AT91ETHER_MAX_RX_DESCR *
2487 AT91ETHER_MAX_RBUFF_SZ,
2488 &lp->rx_buffers_dma, GFP_KERNEL);
2489 if (!lp->rx_buffers) {
2490 dma_free_coherent(&lp->pdev->dev,
2491 AT91ETHER_MAX_RX_DESCR *
2492 sizeof(struct macb_dma_desc),
2493 lp->rx_ring, lp->rx_ring_dma);
2494 lp->rx_ring = NULL;
2495 return -ENOMEM;
2496 }
2497
2498 addr = lp->rx_buffers_dma;
2499 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
2500 lp->rx_ring[i].addr = addr;
2501 lp->rx_ring[i].ctrl = 0;
2502 addr += AT91ETHER_MAX_RBUFF_SZ;
2503 }
2504
2505 /* Set the Wrap bit on the last descriptor */
2506 lp->rx_ring[AT91ETHER_MAX_RX_DESCR - 1].addr |= MACB_BIT(RX_WRAP);
2507
2508 /* Reset buffer index */
2509 lp->rx_tail = 0;
2510
2511 /* Program address of descriptor list in Rx Buffer Queue register */
2512 macb_writel(lp, RBQP, lp->rx_ring_dma);
2513
2514 /* Enable Receive and Transmit */
2515 ctl = macb_readl(lp, NCR);
2516 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
2517
2518 return 0;
2519 }
2520
2521 /* Open the ethernet interface */
2522 static int at91ether_open(struct net_device *dev)
2523 {
2524 struct macb *lp = netdev_priv(dev);
2525 u32 ctl;
2526 int ret;
2527
2528 /* Clear internal statistics */
2529 ctl = macb_readl(lp, NCR);
2530 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
2531
2532 macb_set_hwaddr(lp);
2533
2534 ret = at91ether_start(dev);
2535 if (ret)
2536 return ret;
2537
2538 /* Enable MAC interrupts */
2539 macb_writel(lp, IER, MACB_BIT(RCOMP) |
2540 MACB_BIT(RXUBR) |
2541 MACB_BIT(ISR_TUND) |
2542 MACB_BIT(ISR_RLE) |
2543 MACB_BIT(TCOMP) |
2544 MACB_BIT(ISR_ROVR) |
2545 MACB_BIT(HRESP));
2546
2547 /* schedule a link state check */
2548 phy_start(lp->phy_dev);
2549
2550 netif_start_queue(dev);
2551
2552 return 0;
2553 }
2554
2555 /* Close the interface */
2556 static int at91ether_close(struct net_device *dev)
2557 {
2558 struct macb *lp = netdev_priv(dev);
2559 u32 ctl;
2560
2561 /* Disable Receiver and Transmitter */
2562 ctl = macb_readl(lp, NCR);
2563 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
2564
2565 /* Disable MAC interrupts */
2566 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
2567 MACB_BIT(RXUBR) |
2568 MACB_BIT(ISR_TUND) |
2569 MACB_BIT(ISR_RLE) |
2570 MACB_BIT(TCOMP) |
2571 MACB_BIT(ISR_ROVR) |
2572 MACB_BIT(HRESP));
2573
2574 netif_stop_queue(dev);
2575
2576 dma_free_coherent(&lp->pdev->dev,
2577 AT91ETHER_MAX_RX_DESCR *
2578 sizeof(struct macb_dma_desc),
2579 lp->rx_ring, lp->rx_ring_dma);
2580 lp->rx_ring = NULL;
2581
2582 dma_free_coherent(&lp->pdev->dev,
2583 AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
2584 lp->rx_buffers, lp->rx_buffers_dma);
2585 lp->rx_buffers = NULL;
2586
2587 return 0;
2588 }
2589
2590 /* Transmit packet */
2591 static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
2592 {
2593 struct macb *lp = netdev_priv(dev);
2594
2595 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
2596 netif_stop_queue(dev);
2597
2598 /* Store packet information (to free when Tx completed) */
2599 lp->skb = skb;
2600 lp->skb_length = skb->len;
2601 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len,
2602 DMA_TO_DEVICE);
2603
2604 /* Set address of the data in the Transmit Address register */
2605 macb_writel(lp, TAR, lp->skb_physaddr);
2606 /* Set length of the packet in the Transmit Control register */
2607 macb_writel(lp, TCR, skb->len);
2608
2609 } else {
2610 netdev_err(dev, "%s called, but device is busy!\n", __func__);
2611 return NETDEV_TX_BUSY;
2612 }
2613
2614 return NETDEV_TX_OK;
2615 }
2616
2617 /* Extract received frame from buffer descriptors and sent to upper layers.
2618 * (Called from interrupt context)
2619 */
2620 static void at91ether_rx(struct net_device *dev)
2621 {
2622 struct macb *lp = netdev_priv(dev);
2623 unsigned char *p_recv;
2624 struct sk_buff *skb;
2625 unsigned int pktlen;
2626
2627 while (lp->rx_ring[lp->rx_tail].addr & MACB_BIT(RX_USED)) {
2628 p_recv = lp->rx_buffers + lp->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
2629 pktlen = MACB_BF(RX_FRMLEN, lp->rx_ring[lp->rx_tail].ctrl);
2630 skb = netdev_alloc_skb(dev, pktlen + 2);
2631 if (skb) {
2632 skb_reserve(skb, 2);
2633 memcpy(skb_put(skb, pktlen), p_recv, pktlen);
2634
2635 skb->protocol = eth_type_trans(skb, dev);
2636 lp->stats.rx_packets++;
2637 lp->stats.rx_bytes += pktlen;
2638 netif_rx(skb);
2639 } else {
2640 lp->stats.rx_dropped++;
2641 }
2642
2643 if (lp->rx_ring[lp->rx_tail].ctrl & MACB_BIT(RX_MHASH_MATCH))
2644 lp->stats.multicast++;
2645
2646 /* reset ownership bit */
2647 lp->rx_ring[lp->rx_tail].addr &= ~MACB_BIT(RX_USED);
2648
2649 /* wrap after last buffer */
2650 if (lp->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
2651 lp->rx_tail = 0;
2652 else
2653 lp->rx_tail++;
2654 }
2655 }
2656
2657 /* MAC interrupt handler */
2658 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
2659 {
2660 struct net_device *dev = dev_id;
2661 struct macb *lp = netdev_priv(dev);
2662 u32 intstatus, ctl;
2663
2664 /* MAC Interrupt Status register indicates what interrupts are pending.
2665 * It is automatically cleared once read.
2666 */
2667 intstatus = macb_readl(lp, ISR);
2668
2669 /* Receive complete */
2670 if (intstatus & MACB_BIT(RCOMP))
2671 at91ether_rx(dev);
2672
2673 /* Transmit complete */
2674 if (intstatus & MACB_BIT(TCOMP)) {
2675 /* The TCOM bit is set even if the transmission failed */
2676 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
2677 lp->stats.tx_errors++;
2678
2679 if (lp->skb) {
2680 dev_kfree_skb_irq(lp->skb);
2681 lp->skb = NULL;
2682 dma_unmap_single(NULL, lp->skb_physaddr,
2683 lp->skb_length, DMA_TO_DEVICE);
2684 lp->stats.tx_packets++;
2685 lp->stats.tx_bytes += lp->skb_length;
2686 }
2687 netif_wake_queue(dev);
2688 }
2689
2690 /* Work-around for EMAC Errata section 41.3.1 */
2691 if (intstatus & MACB_BIT(RXUBR)) {
2692 ctl = macb_readl(lp, NCR);
2693 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
2694 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
2695 }
2696
2697 if (intstatus & MACB_BIT(ISR_ROVR))
2698 netdev_err(dev, "ROVR error\n");
2699
2700 return IRQ_HANDLED;
2701 }
2702
2703 #ifdef CONFIG_NET_POLL_CONTROLLER
2704 static void at91ether_poll_controller(struct net_device *dev)
2705 {
2706 unsigned long flags;
2707
2708 local_irq_save(flags);
2709 at91ether_interrupt(dev->irq, dev);
2710 local_irq_restore(flags);
2711 }
2712 #endif
2713
2714 static const struct net_device_ops at91ether_netdev_ops = {
2715 .ndo_open = at91ether_open,
2716 .ndo_stop = at91ether_close,
2717 .ndo_start_xmit = at91ether_start_xmit,
2718 .ndo_get_stats = macb_get_stats,
2719 .ndo_set_rx_mode = macb_set_rx_mode,
2720 .ndo_set_mac_address = eth_mac_addr,
2721 .ndo_do_ioctl = macb_ioctl,
2722 .ndo_validate_addr = eth_validate_addr,
2723 .ndo_change_mtu = eth_change_mtu,
2724 #ifdef CONFIG_NET_POLL_CONTROLLER
2725 .ndo_poll_controller = at91ether_poll_controller,
2726 #endif
2727 };
2728
2729 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
2730 struct clk **hclk, struct clk **tx_clk)
2731 {
2732 int err;
2733
2734 *hclk = NULL;
2735 *tx_clk = NULL;
2736
2737 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
2738 if (IS_ERR(*pclk))
2739 return PTR_ERR(*pclk);
2740
2741 err = clk_prepare_enable(*pclk);
2742 if (err) {
2743 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
2744 return err;
2745 }
2746
2747 return 0;
2748 }
2749
2750 static int at91ether_init(struct platform_device *pdev)
2751 {
2752 struct net_device *dev = platform_get_drvdata(pdev);
2753 struct macb *bp = netdev_priv(dev);
2754 int err;
2755 u32 reg;
2756
2757 dev->netdev_ops = &at91ether_netdev_ops;
2758 dev->ethtool_ops = &macb_ethtool_ops;
2759
2760 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
2761 0, dev->name, dev);
2762 if (err)
2763 return err;
2764
2765 macb_writel(bp, NCR, 0);
2766
2767 reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
2768 if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
2769 reg |= MACB_BIT(RM9200_RMII);
2770
2771 macb_writel(bp, NCFGR, reg);
2772
2773 return 0;
2774 }
2775
2776 static const struct macb_config at91sam9260_config = {
2777 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
2778 .clk_init = macb_clk_init,
2779 .init = macb_init,
2780 };
2781
2782 static const struct macb_config pc302gem_config = {
2783 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
2784 .dma_burst_length = 16,
2785 .clk_init = macb_clk_init,
2786 .init = macb_init,
2787 };
2788
2789 static const struct macb_config sama5d2_config = {
2790 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
2791 .dma_burst_length = 16,
2792 .clk_init = macb_clk_init,
2793 .init = macb_init,
2794 };
2795
2796 static const struct macb_config sama5d3_config = {
2797 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
2798 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
2799 .dma_burst_length = 16,
2800 .clk_init = macb_clk_init,
2801 .init = macb_init,
2802 };
2803
2804 static const struct macb_config sama5d4_config = {
2805 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
2806 .dma_burst_length = 4,
2807 .clk_init = macb_clk_init,
2808 .init = macb_init,
2809 };
2810
2811 static const struct macb_config emac_config = {
2812 .clk_init = at91ether_clk_init,
2813 .init = at91ether_init,
2814 };
2815
2816 static const struct macb_config np4_config = {
2817 .caps = MACB_CAPS_USRIO_DISABLED,
2818 .clk_init = macb_clk_init,
2819 .init = macb_init,
2820 };
2821
2822 static const struct macb_config zynqmp_config = {
2823 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO,
2824 .dma_burst_length = 16,
2825 .clk_init = macb_clk_init,
2826 .init = macb_init,
2827 .jumbo_max_len = 10240,
2828 };
2829
2830 static const struct macb_config zynq_config = {
2831 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF,
2832 .dma_burst_length = 16,
2833 .clk_init = macb_clk_init,
2834 .init = macb_init,
2835 };
2836
2837 static const struct of_device_id macb_dt_ids[] = {
2838 { .compatible = "cdns,at32ap7000-macb" },
2839 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
2840 { .compatible = "cdns,macb" },
2841 { .compatible = "cdns,np4-macb", .data = &np4_config },
2842 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
2843 { .compatible = "cdns,gem", .data = &pc302gem_config },
2844 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
2845 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
2846 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
2847 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
2848 { .compatible = "cdns,emac", .data = &emac_config },
2849 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
2850 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
2851 { /* sentinel */ }
2852 };
2853 MODULE_DEVICE_TABLE(of, macb_dt_ids);
2854 #endif /* CONFIG_OF */
2855
2856 static int macb_probe(struct platform_device *pdev)
2857 {
2858 int (*clk_init)(struct platform_device *, struct clk **,
2859 struct clk **, struct clk **)
2860 = macb_clk_init;
2861 int (*init)(struct platform_device *) = macb_init;
2862 struct device_node *np = pdev->dev.of_node;
2863 struct device_node *phy_node;
2864 const struct macb_config *macb_config = NULL;
2865 struct clk *pclk, *hclk = NULL, *tx_clk = NULL;
2866 unsigned int queue_mask, num_queues;
2867 struct macb_platform_data *pdata;
2868 bool native_io;
2869 struct phy_device *phydev;
2870 struct net_device *dev;
2871 struct resource *regs;
2872 void __iomem *mem;
2873 const char *mac;
2874 struct macb *bp;
2875 int err;
2876
2877 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2878 mem = devm_ioremap_resource(&pdev->dev, regs);
2879 if (IS_ERR(mem))
2880 return PTR_ERR(mem);
2881
2882 if (np) {
2883 const struct of_device_id *match;
2884
2885 match = of_match_node(macb_dt_ids, np);
2886 if (match && match->data) {
2887 macb_config = match->data;
2888 clk_init = macb_config->clk_init;
2889 init = macb_config->init;
2890 }
2891 }
2892
2893 err = clk_init(pdev, &pclk, &hclk, &tx_clk);
2894 if (err)
2895 return err;
2896
2897 native_io = hw_is_native_io(mem);
2898
2899 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
2900 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
2901 if (!dev) {
2902 err = -ENOMEM;
2903 goto err_disable_clocks;
2904 }
2905
2906 dev->base_addr = regs->start;
2907
2908 SET_NETDEV_DEV(dev, &pdev->dev);
2909
2910 bp = netdev_priv(dev);
2911 bp->pdev = pdev;
2912 bp->dev = dev;
2913 bp->regs = mem;
2914 bp->native_io = native_io;
2915 if (native_io) {
2916 bp->macb_reg_readl = hw_readl_native;
2917 bp->macb_reg_writel = hw_writel_native;
2918 } else {
2919 bp->macb_reg_readl = hw_readl;
2920 bp->macb_reg_writel = hw_writel;
2921 }
2922 bp->num_queues = num_queues;
2923 bp->queue_mask = queue_mask;
2924 if (macb_config)
2925 bp->dma_burst_length = macb_config->dma_burst_length;
2926 bp->pclk = pclk;
2927 bp->hclk = hclk;
2928 bp->tx_clk = tx_clk;
2929 if (macb_config)
2930 bp->jumbo_max_len = macb_config->jumbo_max_len;
2931
2932 bp->wol = 0;
2933 if (of_get_property(np, "magic-packet", NULL))
2934 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
2935 device_init_wakeup(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
2936
2937 spin_lock_init(&bp->lock);
2938
2939 /* setup capabilities */
2940 macb_configure_caps(bp, macb_config);
2941
2942 platform_set_drvdata(pdev, dev);
2943
2944 dev->irq = platform_get_irq(pdev, 0);
2945 if (dev->irq < 0) {
2946 err = dev->irq;
2947 goto err_disable_clocks;
2948 }
2949
2950 mac = of_get_mac_address(np);
2951 if (mac)
2952 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
2953 else
2954 macb_get_hwaddr(bp);
2955
2956 /* Power up the PHY if there is a GPIO reset */
2957 phy_node = of_get_next_available_child(np, NULL);
2958 if (phy_node) {
2959 int gpio = of_get_named_gpio(phy_node, "reset-gpios", 0);
2960 if (gpio_is_valid(gpio))
2961 bp->reset_gpio = gpio_to_desc(gpio);
2962 gpiod_direction_output(bp->reset_gpio, 1);
2963 }
2964 of_node_put(phy_node);
2965
2966 err = of_get_phy_mode(np);
2967 if (err < 0) {
2968 pdata = dev_get_platdata(&pdev->dev);
2969 if (pdata && pdata->is_rmii)
2970 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
2971 else
2972 bp->phy_interface = PHY_INTERFACE_MODE_MII;
2973 } else {
2974 bp->phy_interface = err;
2975 }
2976
2977 /* IP specific init */
2978 err = init(pdev);
2979 if (err)
2980 goto err_out_free_netdev;
2981
2982 err = register_netdev(dev);
2983 if (err) {
2984 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
2985 goto err_out_unregister_netdev;
2986 }
2987
2988 err = macb_mii_init(bp);
2989 if (err)
2990 goto err_out_unregister_netdev;
2991
2992 netif_carrier_off(dev);
2993
2994 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
2995 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
2996 dev->base_addr, dev->irq, dev->dev_addr);
2997
2998 phydev = bp->phy_dev;
2999 phy_attached_info(phydev);
3000
3001 return 0;
3002
3003 err_out_unregister_netdev:
3004 unregister_netdev(dev);
3005
3006 err_out_free_netdev:
3007 free_netdev(dev);
3008
3009 err_disable_clocks:
3010 clk_disable_unprepare(tx_clk);
3011 clk_disable_unprepare(hclk);
3012 clk_disable_unprepare(pclk);
3013
3014 return err;
3015 }
3016
3017 static int macb_remove(struct platform_device *pdev)
3018 {
3019 struct net_device *dev;
3020 struct macb *bp;
3021
3022 dev = platform_get_drvdata(pdev);
3023
3024 if (dev) {
3025 bp = netdev_priv(dev);
3026 if (bp->phy_dev)
3027 phy_disconnect(bp->phy_dev);
3028 mdiobus_unregister(bp->mii_bus);
3029 mdiobus_free(bp->mii_bus);
3030
3031 /* Shutdown the PHY if there is a GPIO reset */
3032 gpiod_set_value(bp->reset_gpio, 0);
3033
3034 unregister_netdev(dev);
3035 clk_disable_unprepare(bp->tx_clk);
3036 clk_disable_unprepare(bp->hclk);
3037 clk_disable_unprepare(bp->pclk);
3038 free_netdev(dev);
3039 }
3040
3041 return 0;
3042 }
3043
3044 static int __maybe_unused macb_suspend(struct device *dev)
3045 {
3046 struct platform_device *pdev = to_platform_device(dev);
3047 struct net_device *netdev = platform_get_drvdata(pdev);
3048 struct macb *bp = netdev_priv(netdev);
3049
3050 netif_carrier_off(netdev);
3051 netif_device_detach(netdev);
3052
3053 if (bp->wol & MACB_WOL_ENABLED) {
3054 macb_writel(bp, IER, MACB_BIT(WOL));
3055 macb_writel(bp, WOL, MACB_BIT(MAG));
3056 enable_irq_wake(bp->queues[0].irq);
3057 } else {
3058 clk_disable_unprepare(bp->tx_clk);
3059 clk_disable_unprepare(bp->hclk);
3060 clk_disable_unprepare(bp->pclk);
3061 }
3062
3063 return 0;
3064 }
3065
3066 static int __maybe_unused macb_resume(struct device *dev)
3067 {
3068 struct platform_device *pdev = to_platform_device(dev);
3069 struct net_device *netdev = platform_get_drvdata(pdev);
3070 struct macb *bp = netdev_priv(netdev);
3071
3072 if (bp->wol & MACB_WOL_ENABLED) {
3073 macb_writel(bp, IDR, MACB_BIT(WOL));
3074 macb_writel(bp, WOL, 0);
3075 disable_irq_wake(bp->queues[0].irq);
3076 } else {
3077 clk_prepare_enable(bp->pclk);
3078 clk_prepare_enable(bp->hclk);
3079 clk_prepare_enable(bp->tx_clk);
3080 }
3081
3082 netif_device_attach(netdev);
3083
3084 return 0;
3085 }
3086
3087 static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
3088
3089 static struct platform_driver macb_driver = {
3090 .probe = macb_probe,
3091 .remove = macb_remove,
3092 .driver = {
3093 .name = "macb",
3094 .of_match_table = of_match_ptr(macb_dt_ids),
3095 .pm = &macb_pm_ops,
3096 },
3097 };
3098
3099 module_platform_driver(macb_driver);
3100
3101 MODULE_LICENSE("GPL");
3102 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
3103 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
3104 MODULE_ALIAS("platform:macb");
Linux kernel - Deliverables
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