2 * Cadence MACB/GEM Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/circ_buf.h>
18 #include <linux/slab.h>
19 #include <linux/init.h>
21 #include <linux/gpio.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/interrupt.h>
24 #include <linux/netdevice.h>
25 #include <linux/etherdevice.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/platform_data/macb.h>
28 #include <linux/platform_device.h>
29 #include <linux/phy.h>
31 #include <linux/of_device.h>
32 #include <linux/of_gpio.h>
33 #include <linux/of_mdio.h>
34 #include <linux/of_net.h>
38 #define MACB_RX_BUFFER_SIZE 128
39 #define RX_BUFFER_MULTIPLE 64 /* bytes */
40 #define RX_RING_SIZE 512 /* must be power of 2 */
41 #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
43 #define TX_RING_SIZE 128 /* must be power of 2 */
44 #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
46 /* level of occupied TX descriptors under which we wake up TX process */
47 #define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
49 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
51 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
54 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
56 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1))
57 #define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1))
59 #define GEM_MTU_MIN_SIZE 68
61 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
62 #define MACB_WOL_ENABLED (0x1 << 1)
65 * Graceful stop timeouts in us. We should allow up to
66 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
68 #define MACB_HALT_TIMEOUT 1230
70 /* Ring buffer accessors */
71 static unsigned int macb_tx_ring_wrap(unsigned int index
)
73 return index
& (TX_RING_SIZE
- 1);
76 static struct macb_dma_desc
*macb_tx_desc(struct macb_queue
*queue
,
79 return &queue
->tx_ring
[macb_tx_ring_wrap(index
)];
82 static struct macb_tx_skb
*macb_tx_skb(struct macb_queue
*queue
,
85 return &queue
->tx_skb
[macb_tx_ring_wrap(index
)];
88 static dma_addr_t
macb_tx_dma(struct macb_queue
*queue
, unsigned int index
)
92 offset
= macb_tx_ring_wrap(index
) * sizeof(struct macb_dma_desc
);
94 return queue
->tx_ring_dma
+ offset
;
97 static unsigned int macb_rx_ring_wrap(unsigned int index
)
99 return index
& (RX_RING_SIZE
- 1);
102 static struct macb_dma_desc
*macb_rx_desc(struct macb
*bp
, unsigned int index
)
104 return &bp
->rx_ring
[macb_rx_ring_wrap(index
)];
107 static void *macb_rx_buffer(struct macb
*bp
, unsigned int index
)
109 return bp
->rx_buffers
+ bp
->rx_buffer_size
* macb_rx_ring_wrap(index
);
113 static u32
hw_readl_native(struct macb
*bp
, int offset
)
115 return __raw_readl(bp
->regs
+ offset
);
118 static void hw_writel_native(struct macb
*bp
, int offset
, u32 value
)
120 __raw_writel(value
, bp
->regs
+ offset
);
123 static u32
hw_readl(struct macb
*bp
, int offset
)
125 return readl_relaxed(bp
->regs
+ offset
);
128 static void hw_writel(struct macb
*bp
, int offset
, u32 value
)
130 writel_relaxed(value
, bp
->regs
+ offset
);
134 * Find the CPU endianness by using the loopback bit of NCR register. When the
135 * CPU is in big endian we need to program swaped mode for management
138 static bool hw_is_native_io(void __iomem
*addr
)
140 u32 value
= MACB_BIT(LLB
);
142 __raw_writel(value
, addr
+ MACB_NCR
);
143 value
= __raw_readl(addr
+ MACB_NCR
);
145 /* Write 0 back to disable everything */
146 __raw_writel(0, addr
+ MACB_NCR
);
148 return value
== MACB_BIT(LLB
);
151 static bool hw_is_gem(void __iomem
*addr
, bool native_io
)
156 id
= __raw_readl(addr
+ MACB_MID
);
158 id
= readl_relaxed(addr
+ MACB_MID
);
160 return MACB_BFEXT(IDNUM
, id
) >= 0x2;
163 static void macb_set_hwaddr(struct macb
*bp
)
168 bottom
= cpu_to_le32(*((u32
*)bp
->dev
->dev_addr
));
169 macb_or_gem_writel(bp
, SA1B
, bottom
);
170 top
= cpu_to_le16(*((u16
*)(bp
->dev
->dev_addr
+ 4)));
171 macb_or_gem_writel(bp
, SA1T
, top
);
173 /* Clear unused address register sets */
174 macb_or_gem_writel(bp
, SA2B
, 0);
175 macb_or_gem_writel(bp
, SA2T
, 0);
176 macb_or_gem_writel(bp
, SA3B
, 0);
177 macb_or_gem_writel(bp
, SA3T
, 0);
178 macb_or_gem_writel(bp
, SA4B
, 0);
179 macb_or_gem_writel(bp
, SA4T
, 0);
182 static void macb_get_hwaddr(struct macb
*bp
)
184 struct macb_platform_data
*pdata
;
190 pdata
= dev_get_platdata(&bp
->pdev
->dev
);
192 /* Check all 4 address register for vaild address */
193 for (i
= 0; i
< 4; i
++) {
194 bottom
= macb_or_gem_readl(bp
, SA1B
+ i
* 8);
195 top
= macb_or_gem_readl(bp
, SA1T
+ i
* 8);
197 if (pdata
&& pdata
->rev_eth_addr
) {
198 addr
[5] = bottom
& 0xff;
199 addr
[4] = (bottom
>> 8) & 0xff;
200 addr
[3] = (bottom
>> 16) & 0xff;
201 addr
[2] = (bottom
>> 24) & 0xff;
202 addr
[1] = top
& 0xff;
203 addr
[0] = (top
& 0xff00) >> 8;
205 addr
[0] = bottom
& 0xff;
206 addr
[1] = (bottom
>> 8) & 0xff;
207 addr
[2] = (bottom
>> 16) & 0xff;
208 addr
[3] = (bottom
>> 24) & 0xff;
209 addr
[4] = top
& 0xff;
210 addr
[5] = (top
>> 8) & 0xff;
213 if (is_valid_ether_addr(addr
)) {
214 memcpy(bp
->dev
->dev_addr
, addr
, sizeof(addr
));
219 dev_info(&bp
->pdev
->dev
, "invalid hw address, using random\n");
220 eth_hw_addr_random(bp
->dev
);
223 static int macb_mdio_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
225 struct macb
*bp
= bus
->priv
;
228 macb_writel(bp
, MAN
, (MACB_BF(SOF
, MACB_MAN_SOF
)
229 | MACB_BF(RW
, MACB_MAN_READ
)
230 | MACB_BF(PHYA
, mii_id
)
231 | MACB_BF(REGA
, regnum
)
232 | MACB_BF(CODE
, MACB_MAN_CODE
)));
234 /* wait for end of transfer */
235 while (!MACB_BFEXT(IDLE
, macb_readl(bp
, NSR
)))
238 value
= MACB_BFEXT(DATA
, macb_readl(bp
, MAN
));
243 static int macb_mdio_write(struct mii_bus
*bus
, int mii_id
, int regnum
,
246 struct macb
*bp
= bus
->priv
;
248 macb_writel(bp
, MAN
, (MACB_BF(SOF
, MACB_MAN_SOF
)
249 | MACB_BF(RW
, MACB_MAN_WRITE
)
250 | MACB_BF(PHYA
, mii_id
)
251 | MACB_BF(REGA
, regnum
)
252 | MACB_BF(CODE
, MACB_MAN_CODE
)
253 | MACB_BF(DATA
, value
)));
255 /* wait for end of transfer */
256 while (!MACB_BFEXT(IDLE
, macb_readl(bp
, NSR
)))
263 * macb_set_tx_clk() - Set a clock to a new frequency
264 * @clk Pointer to the clock to change
265 * @rate New frequency in Hz
266 * @dev Pointer to the struct net_device
268 static void macb_set_tx_clk(struct clk
*clk
, int speed
, struct net_device
*dev
)
270 long ferr
, rate
, rate_rounded
;
289 rate_rounded
= clk_round_rate(clk
, rate
);
290 if (rate_rounded
< 0)
293 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
296 ferr
= abs(rate_rounded
- rate
);
297 ferr
= DIV_ROUND_UP(ferr
, rate
/ 100000);
299 netdev_warn(dev
, "unable to generate target frequency: %ld Hz\n",
302 if (clk_set_rate(clk
, rate_rounded
))
303 netdev_err(dev
, "adjusting tx_clk failed.\n");
306 static void macb_handle_link_change(struct net_device
*dev
)
308 struct macb
*bp
= netdev_priv(dev
);
309 struct phy_device
*phydev
= bp
->phy_dev
;
311 int status_change
= 0;
313 spin_lock_irqsave(&bp
->lock
, flags
);
316 if ((bp
->speed
!= phydev
->speed
) ||
317 (bp
->duplex
!= phydev
->duplex
)) {
320 reg
= macb_readl(bp
, NCFGR
);
321 reg
&= ~(MACB_BIT(SPD
) | MACB_BIT(FD
));
323 reg
&= ~GEM_BIT(GBE
);
327 if (phydev
->speed
== SPEED_100
)
328 reg
|= MACB_BIT(SPD
);
329 if (phydev
->speed
== SPEED_1000
&&
330 bp
->caps
& MACB_CAPS_GIGABIT_MODE_AVAILABLE
)
333 macb_or_gem_writel(bp
, NCFGR
, reg
);
335 bp
->speed
= phydev
->speed
;
336 bp
->duplex
= phydev
->duplex
;
341 if (phydev
->link
!= bp
->link
) {
346 bp
->link
= phydev
->link
;
351 spin_unlock_irqrestore(&bp
->lock
, flags
);
355 /* Update the TX clock rate if and only if the link is
356 * up and there has been a link change.
358 macb_set_tx_clk(bp
->tx_clk
, phydev
->speed
, dev
);
360 netif_carrier_on(dev
);
361 netdev_info(dev
, "link up (%d/%s)\n",
363 phydev
->duplex
== DUPLEX_FULL
?
366 netif_carrier_off(dev
);
367 netdev_info(dev
, "link down\n");
372 /* based on au1000_eth. c*/
373 static int macb_mii_probe(struct net_device
*dev
)
375 struct macb
*bp
= netdev_priv(dev
);
376 struct macb_platform_data
*pdata
;
377 struct phy_device
*phydev
;
381 phydev
= phy_find_first(bp
->mii_bus
);
383 netdev_err(dev
, "no PHY found\n");
387 pdata
= dev_get_platdata(&bp
->pdev
->dev
);
388 if (pdata
&& gpio_is_valid(pdata
->phy_irq_pin
)) {
389 ret
= devm_gpio_request(&bp
->pdev
->dev
, pdata
->phy_irq_pin
, "phy int");
391 phy_irq
= gpio_to_irq(pdata
->phy_irq_pin
);
392 phydev
->irq
= (phy_irq
< 0) ? PHY_POLL
: phy_irq
;
396 /* attach the mac to the phy */
397 ret
= phy_connect_direct(dev
, phydev
, &macb_handle_link_change
,
400 netdev_err(dev
, "Could not attach to PHY\n");
404 /* mask with MAC supported features */
405 if (macb_is_gem(bp
) && bp
->caps
& MACB_CAPS_GIGABIT_MODE_AVAILABLE
)
406 phydev
->supported
&= PHY_GBIT_FEATURES
;
408 phydev
->supported
&= PHY_BASIC_FEATURES
;
410 if (bp
->caps
& MACB_CAPS_NO_GIGABIT_HALF
)
411 phydev
->supported
&= ~SUPPORTED_1000baseT_Half
;
413 phydev
->advertising
= phydev
->supported
;
418 bp
->phy_dev
= phydev
;
423 static int macb_mii_init(struct macb
*bp
)
425 struct macb_platform_data
*pdata
;
426 struct device_node
*np
;
429 /* Enable management port */
430 macb_writel(bp
, NCR
, MACB_BIT(MPE
));
432 bp
->mii_bus
= mdiobus_alloc();
433 if (bp
->mii_bus
== NULL
) {
438 bp
->mii_bus
->name
= "MACB_mii_bus";
439 bp
->mii_bus
->read
= &macb_mdio_read
;
440 bp
->mii_bus
->write
= &macb_mdio_write
;
441 snprintf(bp
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%s-%x",
442 bp
->pdev
->name
, bp
->pdev
->id
);
443 bp
->mii_bus
->priv
= bp
;
444 bp
->mii_bus
->parent
= &bp
->dev
->dev
;
445 pdata
= dev_get_platdata(&bp
->pdev
->dev
);
447 dev_set_drvdata(&bp
->dev
->dev
, bp
->mii_bus
);
449 np
= bp
->pdev
->dev
.of_node
;
451 /* try dt phy registration */
452 err
= of_mdiobus_register(bp
->mii_bus
, np
);
454 /* fallback to standard phy registration if no phy were
455 found during dt phy registration */
456 if (!err
&& !phy_find_first(bp
->mii_bus
)) {
457 for (i
= 0; i
< PHY_MAX_ADDR
; i
++) {
458 struct phy_device
*phydev
;
460 phydev
= mdiobus_scan(bp
->mii_bus
, i
);
461 if (IS_ERR(phydev
) &&
462 PTR_ERR(phydev
) != -ENODEV
) {
463 err
= PTR_ERR(phydev
);
469 goto err_out_unregister_bus
;
473 bp
->mii_bus
->phy_mask
= pdata
->phy_mask
;
475 err
= mdiobus_register(bp
->mii_bus
);
479 goto err_out_free_mdiobus
;
481 err
= macb_mii_probe(bp
->dev
);
483 goto err_out_unregister_bus
;
487 err_out_unregister_bus
:
488 mdiobus_unregister(bp
->mii_bus
);
489 err_out_free_mdiobus
:
490 mdiobus_free(bp
->mii_bus
);
495 static void macb_update_stats(struct macb
*bp
)
497 u32
*p
= &bp
->hw_stats
.macb
.rx_pause_frames
;
498 u32
*end
= &bp
->hw_stats
.macb
.tx_pause_frames
+ 1;
499 int offset
= MACB_PFR
;
501 WARN_ON((unsigned long)(end
- p
- 1) != (MACB_TPF
- MACB_PFR
) / 4);
503 for(; p
< end
; p
++, offset
+= 4)
504 *p
+= bp
->macb_reg_readl(bp
, offset
);
507 static int macb_halt_tx(struct macb
*bp
)
509 unsigned long halt_time
, timeout
;
512 macb_writel(bp
, NCR
, macb_readl(bp
, NCR
) | MACB_BIT(THALT
));
514 timeout
= jiffies
+ usecs_to_jiffies(MACB_HALT_TIMEOUT
);
517 status
= macb_readl(bp
, TSR
);
518 if (!(status
& MACB_BIT(TGO
)))
521 usleep_range(10, 250);
522 } while (time_before(halt_time
, timeout
));
527 static void macb_tx_unmap(struct macb
*bp
, struct macb_tx_skb
*tx_skb
)
529 if (tx_skb
->mapping
) {
530 if (tx_skb
->mapped_as_page
)
531 dma_unmap_page(&bp
->pdev
->dev
, tx_skb
->mapping
,
532 tx_skb
->size
, DMA_TO_DEVICE
);
534 dma_unmap_single(&bp
->pdev
->dev
, tx_skb
->mapping
,
535 tx_skb
->size
, DMA_TO_DEVICE
);
540 dev_kfree_skb_any(tx_skb
->skb
);
545 static void macb_tx_error_task(struct work_struct
*work
)
547 struct macb_queue
*queue
= container_of(work
, struct macb_queue
,
549 struct macb
*bp
= queue
->bp
;
550 struct macb_tx_skb
*tx_skb
;
551 struct macb_dma_desc
*desc
;
556 netdev_vdbg(bp
->dev
, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
557 (unsigned int)(queue
- bp
->queues
),
558 queue
->tx_tail
, queue
->tx_head
);
560 /* Prevent the queue IRQ handlers from running: each of them may call
561 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
562 * As explained below, we have to halt the transmission before updating
563 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
564 * network engine about the macb/gem being halted.
566 spin_lock_irqsave(&bp
->lock
, flags
);
568 /* Make sure nobody is trying to queue up new packets */
569 netif_tx_stop_all_queues(bp
->dev
);
572 * Stop transmission now
573 * (in case we have just queued new packets)
574 * macb/gem must be halted to write TBQP register
576 if (macb_halt_tx(bp
))
577 /* Just complain for now, reinitializing TX path can be good */
578 netdev_err(bp
->dev
, "BUG: halt tx timed out\n");
581 * Treat frames in TX queue including the ones that caused the error.
582 * Free transmit buffers in upper layer.
584 for (tail
= queue
->tx_tail
; tail
!= queue
->tx_head
; tail
++) {
587 desc
= macb_tx_desc(queue
, tail
);
589 tx_skb
= macb_tx_skb(queue
, tail
);
592 if (ctrl
& MACB_BIT(TX_USED
)) {
593 /* skb is set for the last buffer of the frame */
595 macb_tx_unmap(bp
, tx_skb
);
597 tx_skb
= macb_tx_skb(queue
, tail
);
601 /* ctrl still refers to the first buffer descriptor
602 * since it's the only one written back by the hardware
604 if (!(ctrl
& MACB_BIT(TX_BUF_EXHAUSTED
))) {
605 netdev_vdbg(bp
->dev
, "txerr skb %u (data %p) TX complete\n",
606 macb_tx_ring_wrap(tail
), skb
->data
);
607 bp
->stats
.tx_packets
++;
608 bp
->stats
.tx_bytes
+= skb
->len
;
612 * "Buffers exhausted mid-frame" errors may only happen
613 * if the driver is buggy, so complain loudly about those.
614 * Statistics are updated by hardware.
616 if (ctrl
& MACB_BIT(TX_BUF_EXHAUSTED
))
618 "BUG: TX buffers exhausted mid-frame\n");
620 desc
->ctrl
= ctrl
| MACB_BIT(TX_USED
);
623 macb_tx_unmap(bp
, tx_skb
);
626 /* Set end of TX queue */
627 desc
= macb_tx_desc(queue
, 0);
629 desc
->ctrl
= MACB_BIT(TX_USED
);
631 /* Make descriptor updates visible to hardware */
634 /* Reinitialize the TX desc queue */
635 queue_writel(queue
, TBQP
, queue
->tx_ring_dma
);
636 /* Make TX ring reflect state of hardware */
640 /* Housework before enabling TX IRQ */
641 macb_writel(bp
, TSR
, macb_readl(bp
, TSR
));
642 queue_writel(queue
, IER
, MACB_TX_INT_FLAGS
);
644 /* Now we are ready to start transmission again */
645 netif_tx_start_all_queues(bp
->dev
);
646 macb_writel(bp
, NCR
, macb_readl(bp
, NCR
) | MACB_BIT(TSTART
));
648 spin_unlock_irqrestore(&bp
->lock
, flags
);
651 static void macb_tx_interrupt(struct macb_queue
*queue
)
656 struct macb
*bp
= queue
->bp
;
657 u16 queue_index
= queue
- bp
->queues
;
659 status
= macb_readl(bp
, TSR
);
660 macb_writel(bp
, TSR
, status
);
662 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
663 queue_writel(queue
, ISR
, MACB_BIT(TCOMP
));
665 netdev_vdbg(bp
->dev
, "macb_tx_interrupt status = 0x%03lx\n",
666 (unsigned long)status
);
668 head
= queue
->tx_head
;
669 for (tail
= queue
->tx_tail
; tail
!= head
; tail
++) {
670 struct macb_tx_skb
*tx_skb
;
672 struct macb_dma_desc
*desc
;
675 desc
= macb_tx_desc(queue
, tail
);
677 /* Make hw descriptor updates visible to CPU */
682 /* TX_USED bit is only set by hardware on the very first buffer
683 * descriptor of the transmitted frame.
685 if (!(ctrl
& MACB_BIT(TX_USED
)))
688 /* Process all buffers of the current transmitted frame */
690 tx_skb
= macb_tx_skb(queue
, tail
);
693 /* First, update TX stats if needed */
695 netdev_vdbg(bp
->dev
, "skb %u (data %p) TX complete\n",
696 macb_tx_ring_wrap(tail
), skb
->data
);
697 bp
->stats
.tx_packets
++;
698 bp
->stats
.tx_bytes
+= skb
->len
;
701 /* Now we can safely release resources */
702 macb_tx_unmap(bp
, tx_skb
);
704 /* skb is set only for the last buffer of the frame.
705 * WARNING: at this point skb has been freed by
713 queue
->tx_tail
= tail
;
714 if (__netif_subqueue_stopped(bp
->dev
, queue_index
) &&
715 CIRC_CNT(queue
->tx_head
, queue
->tx_tail
,
716 TX_RING_SIZE
) <= MACB_TX_WAKEUP_THRESH
)
717 netif_wake_subqueue(bp
->dev
, queue_index
);
720 static void gem_rx_refill(struct macb
*bp
)
726 while (CIRC_SPACE(bp
->rx_prepared_head
, bp
->rx_tail
, RX_RING_SIZE
) > 0) {
727 entry
= macb_rx_ring_wrap(bp
->rx_prepared_head
);
729 /* Make hw descriptor updates visible to CPU */
732 bp
->rx_prepared_head
++;
734 if (bp
->rx_skbuff
[entry
] == NULL
) {
735 /* allocate sk_buff for this free entry in ring */
736 skb
= netdev_alloc_skb(bp
->dev
, bp
->rx_buffer_size
);
737 if (unlikely(skb
== NULL
)) {
739 "Unable to allocate sk_buff\n");
743 /* now fill corresponding descriptor entry */
744 paddr
= dma_map_single(&bp
->pdev
->dev
, skb
->data
,
745 bp
->rx_buffer_size
, DMA_FROM_DEVICE
);
746 if (dma_mapping_error(&bp
->pdev
->dev
, paddr
)) {
751 bp
->rx_skbuff
[entry
] = skb
;
753 if (entry
== RX_RING_SIZE
- 1)
754 paddr
|= MACB_BIT(RX_WRAP
);
755 bp
->rx_ring
[entry
].addr
= paddr
;
756 bp
->rx_ring
[entry
].ctrl
= 0;
758 /* properly align Ethernet header */
759 skb_reserve(skb
, NET_IP_ALIGN
);
761 bp
->rx_ring
[entry
].addr
&= ~MACB_BIT(RX_USED
);
762 bp
->rx_ring
[entry
].ctrl
= 0;
766 /* Make descriptor updates visible to hardware */
769 netdev_vdbg(bp
->dev
, "rx ring: prepared head %d, tail %d\n",
770 bp
->rx_prepared_head
, bp
->rx_tail
);
773 /* Mark DMA descriptors from begin up to and not including end as unused */
774 static void discard_partial_frame(struct macb
*bp
, unsigned int begin
,
779 for (frag
= begin
; frag
!= end
; frag
++) {
780 struct macb_dma_desc
*desc
= macb_rx_desc(bp
, frag
);
781 desc
->addr
&= ~MACB_BIT(RX_USED
);
784 /* Make descriptor updates visible to hardware */
788 * When this happens, the hardware stats registers for
789 * whatever caused this is updated, so we don't have to record
794 static int gem_rx(struct macb
*bp
, int budget
)
799 struct macb_dma_desc
*desc
;
802 while (count
< budget
) {
805 entry
= macb_rx_ring_wrap(bp
->rx_tail
);
806 desc
= &bp
->rx_ring
[entry
];
808 /* Make hw descriptor updates visible to CPU */
814 if (!(addr
& MACB_BIT(RX_USED
)))
820 if (!(ctrl
& MACB_BIT(RX_SOF
) && ctrl
& MACB_BIT(RX_EOF
))) {
822 "not whole frame pointed by descriptor\n");
823 bp
->stats
.rx_dropped
++;
826 skb
= bp
->rx_skbuff
[entry
];
827 if (unlikely(!skb
)) {
829 "inconsistent Rx descriptor chain\n");
830 bp
->stats
.rx_dropped
++;
833 /* now everything is ready for receiving packet */
834 bp
->rx_skbuff
[entry
] = NULL
;
835 len
= ctrl
& bp
->rx_frm_len_mask
;
837 netdev_vdbg(bp
->dev
, "gem_rx %u (len %u)\n", entry
, len
);
840 addr
= MACB_BF(RX_WADDR
, MACB_BFEXT(RX_WADDR
, addr
));
841 dma_unmap_single(&bp
->pdev
->dev
, addr
,
842 bp
->rx_buffer_size
, DMA_FROM_DEVICE
);
844 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
845 skb_checksum_none_assert(skb
);
846 if (bp
->dev
->features
& NETIF_F_RXCSUM
&&
847 !(bp
->dev
->flags
& IFF_PROMISC
) &&
848 GEM_BFEXT(RX_CSUM
, ctrl
) & GEM_RX_CSUM_CHECKED_MASK
)
849 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
851 bp
->stats
.rx_packets
++;
852 bp
->stats
.rx_bytes
+= skb
->len
;
854 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
855 netdev_vdbg(bp
->dev
, "received skb of length %u, csum: %08x\n",
856 skb
->len
, skb
->csum
);
857 print_hex_dump(KERN_DEBUG
, " mac: ", DUMP_PREFIX_ADDRESS
, 16, 1,
858 skb_mac_header(skb
), 16, true);
859 print_hex_dump(KERN_DEBUG
, "data: ", DUMP_PREFIX_ADDRESS
, 16, 1,
860 skb
->data
, 32, true);
863 netif_receive_skb(skb
);
871 static int macb_rx_frame(struct macb
*bp
, unsigned int first_frag
,
872 unsigned int last_frag
)
878 struct macb_dma_desc
*desc
;
880 desc
= macb_rx_desc(bp
, last_frag
);
881 len
= desc
->ctrl
& bp
->rx_frm_len_mask
;
883 netdev_vdbg(bp
->dev
, "macb_rx_frame frags %u - %u (len %u)\n",
884 macb_rx_ring_wrap(first_frag
),
885 macb_rx_ring_wrap(last_frag
), len
);
888 * The ethernet header starts NET_IP_ALIGN bytes into the
889 * first buffer. Since the header is 14 bytes, this makes the
890 * payload word-aligned.
892 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
893 * the two padding bytes into the skb so that we avoid hitting
894 * the slowpath in memcpy(), and pull them off afterwards.
896 skb
= netdev_alloc_skb(bp
->dev
, len
+ NET_IP_ALIGN
);
898 bp
->stats
.rx_dropped
++;
899 for (frag
= first_frag
; ; frag
++) {
900 desc
= macb_rx_desc(bp
, frag
);
901 desc
->addr
&= ~MACB_BIT(RX_USED
);
902 if (frag
== last_frag
)
906 /* Make descriptor updates visible to hardware */
914 skb_checksum_none_assert(skb
);
917 for (frag
= first_frag
; ; frag
++) {
918 unsigned int frag_len
= bp
->rx_buffer_size
;
920 if (offset
+ frag_len
> len
) {
921 if (unlikely(frag
!= last_frag
)) {
922 dev_kfree_skb_any(skb
);
925 frag_len
= len
- offset
;
927 skb_copy_to_linear_data_offset(skb
, offset
,
928 macb_rx_buffer(bp
, frag
), frag_len
);
929 offset
+= bp
->rx_buffer_size
;
930 desc
= macb_rx_desc(bp
, frag
);
931 desc
->addr
&= ~MACB_BIT(RX_USED
);
933 if (frag
== last_frag
)
937 /* Make descriptor updates visible to hardware */
940 __skb_pull(skb
, NET_IP_ALIGN
);
941 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
943 bp
->stats
.rx_packets
++;
944 bp
->stats
.rx_bytes
+= skb
->len
;
945 netdev_vdbg(bp
->dev
, "received skb of length %u, csum: %08x\n",
946 skb
->len
, skb
->csum
);
947 netif_receive_skb(skb
);
952 static inline void macb_init_rx_ring(struct macb
*bp
)
957 addr
= bp
->rx_buffers_dma
;
958 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
959 bp
->rx_ring
[i
].addr
= addr
;
960 bp
->rx_ring
[i
].ctrl
= 0;
961 addr
+= bp
->rx_buffer_size
;
963 bp
->rx_ring
[RX_RING_SIZE
- 1].addr
|= MACB_BIT(RX_WRAP
);
966 static int macb_rx(struct macb
*bp
, int budget
)
968 bool reset_rx_queue
= false;
973 for (tail
= bp
->rx_tail
; budget
> 0; tail
++) {
974 struct macb_dma_desc
*desc
= macb_rx_desc(bp
, tail
);
977 /* Make hw descriptor updates visible to CPU */
983 if (!(addr
& MACB_BIT(RX_USED
)))
986 if (ctrl
& MACB_BIT(RX_SOF
)) {
987 if (first_frag
!= -1)
988 discard_partial_frame(bp
, first_frag
, tail
);
992 if (ctrl
& MACB_BIT(RX_EOF
)) {
995 if (unlikely(first_frag
== -1)) {
996 reset_rx_queue
= true;
1000 dropped
= macb_rx_frame(bp
, first_frag
, tail
);
1002 if (unlikely(dropped
< 0)) {
1003 reset_rx_queue
= true;
1013 if (unlikely(reset_rx_queue
)) {
1014 unsigned long flags
;
1017 netdev_err(bp
->dev
, "RX queue corruption: reset it\n");
1019 spin_lock_irqsave(&bp
->lock
, flags
);
1021 ctrl
= macb_readl(bp
, NCR
);
1022 macb_writel(bp
, NCR
, ctrl
& ~MACB_BIT(RE
));
1024 macb_init_rx_ring(bp
);
1025 macb_writel(bp
, RBQP
, bp
->rx_ring_dma
);
1027 macb_writel(bp
, NCR
, ctrl
| MACB_BIT(RE
));
1029 spin_unlock_irqrestore(&bp
->lock
, flags
);
1033 if (first_frag
!= -1)
1034 bp
->rx_tail
= first_frag
;
1041 static int macb_poll(struct napi_struct
*napi
, int budget
)
1043 struct macb
*bp
= container_of(napi
, struct macb
, napi
);
1047 status
= macb_readl(bp
, RSR
);
1048 macb_writel(bp
, RSR
, status
);
1052 netdev_vdbg(bp
->dev
, "poll: status = %08lx, budget = %d\n",
1053 (unsigned long)status
, budget
);
1055 work_done
= bp
->macbgem_ops
.mog_rx(bp
, budget
);
1056 if (work_done
< budget
) {
1057 napi_complete(napi
);
1059 /* Packets received while interrupts were disabled */
1060 status
= macb_readl(bp
, RSR
);
1062 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1063 macb_writel(bp
, ISR
, MACB_BIT(RCOMP
));
1064 napi_reschedule(napi
);
1066 macb_writel(bp
, IER
, MACB_RX_INT_FLAGS
);
1070 /* TODO: Handle errors */
1075 static irqreturn_t
macb_interrupt(int irq
, void *dev_id
)
1077 struct macb_queue
*queue
= dev_id
;
1078 struct macb
*bp
= queue
->bp
;
1079 struct net_device
*dev
= bp
->dev
;
1082 status
= queue_readl(queue
, ISR
);
1084 if (unlikely(!status
))
1087 spin_lock(&bp
->lock
);
1090 /* close possible race with dev_close */
1091 if (unlikely(!netif_running(dev
))) {
1092 queue_writel(queue
, IDR
, -1);
1093 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1094 queue_writel(queue
, ISR
, -1);
1098 netdev_vdbg(bp
->dev
, "queue = %u, isr = 0x%08lx\n",
1099 (unsigned int)(queue
- bp
->queues
),
1100 (unsigned long)status
);
1102 if (status
& MACB_RX_INT_FLAGS
) {
1104 * There's no point taking any more interrupts
1105 * until we have processed the buffers. The
1106 * scheduling call may fail if the poll routine
1107 * is already scheduled, so disable interrupts
1110 queue_writel(queue
, IDR
, MACB_RX_INT_FLAGS
);
1111 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1112 queue_writel(queue
, ISR
, MACB_BIT(RCOMP
));
1114 if (napi_schedule_prep(&bp
->napi
)) {
1115 netdev_vdbg(bp
->dev
, "scheduling RX softirq\n");
1116 __napi_schedule(&bp
->napi
);
1120 if (unlikely(status
& (MACB_TX_ERR_FLAGS
))) {
1121 queue_writel(queue
, IDR
, MACB_TX_INT_FLAGS
);
1122 schedule_work(&queue
->tx_error_task
);
1124 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1125 queue_writel(queue
, ISR
, MACB_TX_ERR_FLAGS
);
1130 if (status
& MACB_BIT(TCOMP
))
1131 macb_tx_interrupt(queue
);
1134 * Link change detection isn't possible with RMII, so we'll
1135 * add that if/when we get our hands on a full-blown MII PHY.
1138 /* There is a hardware issue under heavy load where DMA can
1139 * stop, this causes endless "used buffer descriptor read"
1140 * interrupts but it can be cleared by re-enabling RX. See
1141 * the at91 manual, section 41.3.1 or the Zynq manual
1142 * section 16.7.4 for details.
1144 if (status
& MACB_BIT(RXUBR
)) {
1145 ctrl
= macb_readl(bp
, NCR
);
1146 macb_writel(bp
, NCR
, ctrl
& ~MACB_BIT(RE
));
1147 macb_writel(bp
, NCR
, ctrl
| MACB_BIT(RE
));
1149 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1150 queue_writel(queue
, ISR
, MACB_BIT(RXUBR
));
1153 if (status
& MACB_BIT(ISR_ROVR
)) {
1154 /* We missed at least one packet */
1155 if (macb_is_gem(bp
))
1156 bp
->hw_stats
.gem
.rx_overruns
++;
1158 bp
->hw_stats
.macb
.rx_overruns
++;
1160 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1161 queue_writel(queue
, ISR
, MACB_BIT(ISR_ROVR
));
1164 if (status
& MACB_BIT(HRESP
)) {
1166 * TODO: Reset the hardware, and maybe move the
1167 * netdev_err to a lower-priority context as well
1170 netdev_err(dev
, "DMA bus error: HRESP not OK\n");
1172 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1173 queue_writel(queue
, ISR
, MACB_BIT(HRESP
));
1176 status
= queue_readl(queue
, ISR
);
1179 spin_unlock(&bp
->lock
);
1184 #ifdef CONFIG_NET_POLL_CONTROLLER
1186 * Polling receive - used by netconsole and other diagnostic tools
1187 * to allow network i/o with interrupts disabled.
1189 static void macb_poll_controller(struct net_device
*dev
)
1191 struct macb
*bp
= netdev_priv(dev
);
1192 struct macb_queue
*queue
;
1193 unsigned long flags
;
1196 local_irq_save(flags
);
1197 for (q
= 0, queue
= bp
->queues
; q
< bp
->num_queues
; ++q
, ++queue
)
1198 macb_interrupt(dev
->irq
, queue
);
1199 local_irq_restore(flags
);
1203 static unsigned int macb_tx_map(struct macb
*bp
,
1204 struct macb_queue
*queue
,
1205 struct sk_buff
*skb
)
1208 unsigned int len
, entry
, i
, tx_head
= queue
->tx_head
;
1209 struct macb_tx_skb
*tx_skb
= NULL
;
1210 struct macb_dma_desc
*desc
;
1211 unsigned int offset
, size
, count
= 0;
1212 unsigned int f
, nr_frags
= skb_shinfo(skb
)->nr_frags
;
1213 unsigned int eof
= 1;
1216 /* First, map non-paged data */
1217 len
= skb_headlen(skb
);
1220 size
= min(len
, bp
->max_tx_length
);
1221 entry
= macb_tx_ring_wrap(tx_head
);
1222 tx_skb
= &queue
->tx_skb
[entry
];
1224 mapping
= dma_map_single(&bp
->pdev
->dev
,
1226 size
, DMA_TO_DEVICE
);
1227 if (dma_mapping_error(&bp
->pdev
->dev
, mapping
))
1230 /* Save info to properly release resources */
1232 tx_skb
->mapping
= mapping
;
1233 tx_skb
->size
= size
;
1234 tx_skb
->mapped_as_page
= false;
1242 /* Then, map paged data from fragments */
1243 for (f
= 0; f
< nr_frags
; f
++) {
1244 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[f
];
1246 len
= skb_frag_size(frag
);
1249 size
= min(len
, bp
->max_tx_length
);
1250 entry
= macb_tx_ring_wrap(tx_head
);
1251 tx_skb
= &queue
->tx_skb
[entry
];
1253 mapping
= skb_frag_dma_map(&bp
->pdev
->dev
, frag
,
1254 offset
, size
, DMA_TO_DEVICE
);
1255 if (dma_mapping_error(&bp
->pdev
->dev
, mapping
))
1258 /* Save info to properly release resources */
1260 tx_skb
->mapping
= mapping
;
1261 tx_skb
->size
= size
;
1262 tx_skb
->mapped_as_page
= true;
1271 /* Should never happen */
1272 if (unlikely(tx_skb
== NULL
)) {
1273 netdev_err(bp
->dev
, "BUG! empty skb!\n");
1277 /* This is the last buffer of the frame: save socket buffer */
1280 /* Update TX ring: update buffer descriptors in reverse order
1281 * to avoid race condition
1284 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1285 * to set the end of TX queue
1288 entry
= macb_tx_ring_wrap(i
);
1289 ctrl
= MACB_BIT(TX_USED
);
1290 desc
= &queue
->tx_ring
[entry
];
1295 entry
= macb_tx_ring_wrap(i
);
1296 tx_skb
= &queue
->tx_skb
[entry
];
1297 desc
= &queue
->tx_ring
[entry
];
1299 ctrl
= (u32
)tx_skb
->size
;
1301 ctrl
|= MACB_BIT(TX_LAST
);
1304 if (unlikely(entry
== (TX_RING_SIZE
- 1)))
1305 ctrl
|= MACB_BIT(TX_WRAP
);
1307 /* Set TX buffer descriptor */
1308 desc
->addr
= tx_skb
->mapping
;
1309 /* desc->addr must be visible to hardware before clearing
1310 * 'TX_USED' bit in desc->ctrl.
1314 } while (i
!= queue
->tx_head
);
1316 queue
->tx_head
= tx_head
;
1321 netdev_err(bp
->dev
, "TX DMA map failed\n");
1323 for (i
= queue
->tx_head
; i
!= tx_head
; i
++) {
1324 tx_skb
= macb_tx_skb(queue
, i
);
1326 macb_tx_unmap(bp
, tx_skb
);
1332 static int macb_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1334 u16 queue_index
= skb_get_queue_mapping(skb
);
1335 struct macb
*bp
= netdev_priv(dev
);
1336 struct macb_queue
*queue
= &bp
->queues
[queue_index
];
1337 unsigned long flags
;
1338 unsigned int count
, nr_frags
, frag_size
, f
;
1340 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1341 netdev_vdbg(bp
->dev
,
1342 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1343 queue_index
, skb
->len
, skb
->head
, skb
->data
,
1344 skb_tail_pointer(skb
), skb_end_pointer(skb
));
1345 print_hex_dump(KERN_DEBUG
, "data: ", DUMP_PREFIX_OFFSET
, 16, 1,
1346 skb
->data
, 16, true);
1349 /* Count how many TX buffer descriptors are needed to send this
1350 * socket buffer: skb fragments of jumbo frames may need to be
1351 * splitted into many buffer descriptors.
1353 count
= DIV_ROUND_UP(skb_headlen(skb
), bp
->max_tx_length
);
1354 nr_frags
= skb_shinfo(skb
)->nr_frags
;
1355 for (f
= 0; f
< nr_frags
; f
++) {
1356 frag_size
= skb_frag_size(&skb_shinfo(skb
)->frags
[f
]);
1357 count
+= DIV_ROUND_UP(frag_size
, bp
->max_tx_length
);
1360 spin_lock_irqsave(&bp
->lock
, flags
);
1362 /* This is a hard error, log it. */
1363 if (CIRC_SPACE(queue
->tx_head
, queue
->tx_tail
, TX_RING_SIZE
) < count
) {
1364 netif_stop_subqueue(dev
, queue_index
);
1365 spin_unlock_irqrestore(&bp
->lock
, flags
);
1366 netdev_dbg(bp
->dev
, "tx_head = %u, tx_tail = %u\n",
1367 queue
->tx_head
, queue
->tx_tail
);
1368 return NETDEV_TX_BUSY
;
1371 /* Map socket buffer for DMA transfer */
1372 if (!macb_tx_map(bp
, queue
, skb
)) {
1373 dev_kfree_skb_any(skb
);
1377 /* Make newly initialized descriptor visible to hardware */
1380 skb_tx_timestamp(skb
);
1382 macb_writel(bp
, NCR
, macb_readl(bp
, NCR
) | MACB_BIT(TSTART
));
1384 if (CIRC_SPACE(queue
->tx_head
, queue
->tx_tail
, TX_RING_SIZE
) < 1)
1385 netif_stop_subqueue(dev
, queue_index
);
1388 spin_unlock_irqrestore(&bp
->lock
, flags
);
1390 return NETDEV_TX_OK
;
1393 static void macb_init_rx_buffer_size(struct macb
*bp
, size_t size
)
1395 if (!macb_is_gem(bp
)) {
1396 bp
->rx_buffer_size
= MACB_RX_BUFFER_SIZE
;
1398 bp
->rx_buffer_size
= size
;
1400 if (bp
->rx_buffer_size
% RX_BUFFER_MULTIPLE
) {
1402 "RX buffer must be multiple of %d bytes, expanding\n",
1403 RX_BUFFER_MULTIPLE
);
1404 bp
->rx_buffer_size
=
1405 roundup(bp
->rx_buffer_size
, RX_BUFFER_MULTIPLE
);
1409 netdev_dbg(bp
->dev
, "mtu [%u] rx_buffer_size [%Zu]\n",
1410 bp
->dev
->mtu
, bp
->rx_buffer_size
);
1413 static void gem_free_rx_buffers(struct macb
*bp
)
1415 struct sk_buff
*skb
;
1416 struct macb_dma_desc
*desc
;
1423 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
1424 skb
= bp
->rx_skbuff
[i
];
1429 desc
= &bp
->rx_ring
[i
];
1430 addr
= MACB_BF(RX_WADDR
, MACB_BFEXT(RX_WADDR
, desc
->addr
));
1431 dma_unmap_single(&bp
->pdev
->dev
, addr
, bp
->rx_buffer_size
,
1433 dev_kfree_skb_any(skb
);
1437 kfree(bp
->rx_skbuff
);
1438 bp
->rx_skbuff
= NULL
;
1441 static void macb_free_rx_buffers(struct macb
*bp
)
1443 if (bp
->rx_buffers
) {
1444 dma_free_coherent(&bp
->pdev
->dev
,
1445 RX_RING_SIZE
* bp
->rx_buffer_size
,
1446 bp
->rx_buffers
, bp
->rx_buffers_dma
);
1447 bp
->rx_buffers
= NULL
;
1451 static void macb_free_consistent(struct macb
*bp
)
1453 struct macb_queue
*queue
;
1456 bp
->macbgem_ops
.mog_free_rx_buffers(bp
);
1458 dma_free_coherent(&bp
->pdev
->dev
, RX_RING_BYTES
,
1459 bp
->rx_ring
, bp
->rx_ring_dma
);
1463 for (q
= 0, queue
= bp
->queues
; q
< bp
->num_queues
; ++q
, ++queue
) {
1464 kfree(queue
->tx_skb
);
1465 queue
->tx_skb
= NULL
;
1466 if (queue
->tx_ring
) {
1467 dma_free_coherent(&bp
->pdev
->dev
, TX_RING_BYTES
,
1468 queue
->tx_ring
, queue
->tx_ring_dma
);
1469 queue
->tx_ring
= NULL
;
1474 static int gem_alloc_rx_buffers(struct macb
*bp
)
1478 size
= RX_RING_SIZE
* sizeof(struct sk_buff
*);
1479 bp
->rx_skbuff
= kzalloc(size
, GFP_KERNEL
);
1484 "Allocated %d RX struct sk_buff entries at %p\n",
1485 RX_RING_SIZE
, bp
->rx_skbuff
);
1489 static int macb_alloc_rx_buffers(struct macb
*bp
)
1493 size
= RX_RING_SIZE
* bp
->rx_buffer_size
;
1494 bp
->rx_buffers
= dma_alloc_coherent(&bp
->pdev
->dev
, size
,
1495 &bp
->rx_buffers_dma
, GFP_KERNEL
);
1496 if (!bp
->rx_buffers
)
1500 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1501 size
, (unsigned long)bp
->rx_buffers_dma
, bp
->rx_buffers
);
1505 static int macb_alloc_consistent(struct macb
*bp
)
1507 struct macb_queue
*queue
;
1511 for (q
= 0, queue
= bp
->queues
; q
< bp
->num_queues
; ++q
, ++queue
) {
1512 size
= TX_RING_BYTES
;
1513 queue
->tx_ring
= dma_alloc_coherent(&bp
->pdev
->dev
, size
,
1514 &queue
->tx_ring_dma
,
1516 if (!queue
->tx_ring
)
1519 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
1520 q
, size
, (unsigned long)queue
->tx_ring_dma
,
1523 size
= TX_RING_SIZE
* sizeof(struct macb_tx_skb
);
1524 queue
->tx_skb
= kmalloc(size
, GFP_KERNEL
);
1529 size
= RX_RING_BYTES
;
1530 bp
->rx_ring
= dma_alloc_coherent(&bp
->pdev
->dev
, size
,
1531 &bp
->rx_ring_dma
, GFP_KERNEL
);
1535 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1536 size
, (unsigned long)bp
->rx_ring_dma
, bp
->rx_ring
);
1538 if (bp
->macbgem_ops
.mog_alloc_rx_buffers(bp
))
1544 macb_free_consistent(bp
);
1548 static void gem_init_rings(struct macb
*bp
)
1550 struct macb_queue
*queue
;
1554 for (q
= 0, queue
= bp
->queues
; q
< bp
->num_queues
; ++q
, ++queue
) {
1555 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
1556 queue
->tx_ring
[i
].addr
= 0;
1557 queue
->tx_ring
[i
].ctrl
= MACB_BIT(TX_USED
);
1559 queue
->tx_ring
[TX_RING_SIZE
- 1].ctrl
|= MACB_BIT(TX_WRAP
);
1565 bp
->rx_prepared_head
= 0;
1570 static void macb_init_rings(struct macb
*bp
)
1574 macb_init_rx_ring(bp
);
1576 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
1577 bp
->queues
[0].tx_ring
[i
].addr
= 0;
1578 bp
->queues
[0].tx_ring
[i
].ctrl
= MACB_BIT(TX_USED
);
1580 bp
->queues
[0].tx_head
= 0;
1581 bp
->queues
[0].tx_tail
= 0;
1582 bp
->queues
[0].tx_ring
[TX_RING_SIZE
- 1].ctrl
|= MACB_BIT(TX_WRAP
);
1587 static void macb_reset_hw(struct macb
*bp
)
1589 struct macb_queue
*queue
;
1593 * Disable RX and TX (XXX: Should we halt the transmission
1596 macb_writel(bp
, NCR
, 0);
1598 /* Clear the stats registers (XXX: Update stats first?) */
1599 macb_writel(bp
, NCR
, MACB_BIT(CLRSTAT
));
1601 /* Clear all status flags */
1602 macb_writel(bp
, TSR
, -1);
1603 macb_writel(bp
, RSR
, -1);
1605 /* Disable all interrupts */
1606 for (q
= 0, queue
= bp
->queues
; q
< bp
->num_queues
; ++q
, ++queue
) {
1607 queue_writel(queue
, IDR
, -1);
1608 queue_readl(queue
, ISR
);
1609 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1610 queue_writel(queue
, ISR
, -1);
1614 static u32
gem_mdc_clk_div(struct macb
*bp
)
1617 unsigned long pclk_hz
= clk_get_rate(bp
->pclk
);
1619 if (pclk_hz
<= 20000000)
1620 config
= GEM_BF(CLK
, GEM_CLK_DIV8
);
1621 else if (pclk_hz
<= 40000000)
1622 config
= GEM_BF(CLK
, GEM_CLK_DIV16
);
1623 else if (pclk_hz
<= 80000000)
1624 config
= GEM_BF(CLK
, GEM_CLK_DIV32
);
1625 else if (pclk_hz
<= 120000000)
1626 config
= GEM_BF(CLK
, GEM_CLK_DIV48
);
1627 else if (pclk_hz
<= 160000000)
1628 config
= GEM_BF(CLK
, GEM_CLK_DIV64
);
1630 config
= GEM_BF(CLK
, GEM_CLK_DIV96
);
1635 static u32
macb_mdc_clk_div(struct macb
*bp
)
1638 unsigned long pclk_hz
;
1640 if (macb_is_gem(bp
))
1641 return gem_mdc_clk_div(bp
);
1643 pclk_hz
= clk_get_rate(bp
->pclk
);
1644 if (pclk_hz
<= 20000000)
1645 config
= MACB_BF(CLK
, MACB_CLK_DIV8
);
1646 else if (pclk_hz
<= 40000000)
1647 config
= MACB_BF(CLK
, MACB_CLK_DIV16
);
1648 else if (pclk_hz
<= 80000000)
1649 config
= MACB_BF(CLK
, MACB_CLK_DIV32
);
1651 config
= MACB_BF(CLK
, MACB_CLK_DIV64
);
1657 * Get the DMA bus width field of the network configuration register that we
1658 * should program. We find the width from decoding the design configuration
1659 * register to find the maximum supported data bus width.
1661 static u32
macb_dbw(struct macb
*bp
)
1663 if (!macb_is_gem(bp
))
1666 switch (GEM_BFEXT(DBWDEF
, gem_readl(bp
, DCFG1
))) {
1668 return GEM_BF(DBW
, GEM_DBW128
);
1670 return GEM_BF(DBW
, GEM_DBW64
);
1673 return GEM_BF(DBW
, GEM_DBW32
);
1678 * Configure the receive DMA engine
1679 * - use the correct receive buffer size
1680 * - set best burst length for DMA operations
1681 * (if not supported by FIFO, it will fallback to default)
1682 * - set both rx/tx packet buffers to full memory size
1683 * These are configurable parameters for GEM.
1685 static void macb_configure_dma(struct macb
*bp
)
1689 if (macb_is_gem(bp
)) {
1690 dmacfg
= gem_readl(bp
, DMACFG
) & ~GEM_BF(RXBS
, -1L);
1691 dmacfg
|= GEM_BF(RXBS
, bp
->rx_buffer_size
/ RX_BUFFER_MULTIPLE
);
1692 if (bp
->dma_burst_length
)
1693 dmacfg
= GEM_BFINS(FBLDO
, bp
->dma_burst_length
, dmacfg
);
1694 dmacfg
|= GEM_BIT(TXPBMS
) | GEM_BF(RXBMS
, -1L);
1695 dmacfg
&= ~GEM_BIT(ENDIA_PKT
);
1698 dmacfg
&= ~GEM_BIT(ENDIA_DESC
);
1700 dmacfg
|= GEM_BIT(ENDIA_DESC
); /* CPU in big endian */
1702 if (bp
->dev
->features
& NETIF_F_HW_CSUM
)
1703 dmacfg
|= GEM_BIT(TXCOEN
);
1705 dmacfg
&= ~GEM_BIT(TXCOEN
);
1706 netdev_dbg(bp
->dev
, "Cadence configure DMA with 0x%08x\n",
1708 gem_writel(bp
, DMACFG
, dmacfg
);
1712 static void macb_init_hw(struct macb
*bp
)
1714 struct macb_queue
*queue
;
1720 macb_set_hwaddr(bp
);
1722 config
= macb_mdc_clk_div(bp
);
1723 if (bp
->phy_interface
== PHY_INTERFACE_MODE_SGMII
)
1724 config
|= GEM_BIT(SGMIIEN
) | GEM_BIT(PCSSEL
);
1725 config
|= MACB_BF(RBOF
, NET_IP_ALIGN
); /* Make eth data aligned */
1726 config
|= MACB_BIT(PAE
); /* PAuse Enable */
1727 config
|= MACB_BIT(DRFCS
); /* Discard Rx FCS */
1728 if (bp
->caps
& MACB_CAPS_JUMBO
)
1729 config
|= MACB_BIT(JFRAME
); /* Enable jumbo frames */
1731 config
|= MACB_BIT(BIG
); /* Receive oversized frames */
1732 if (bp
->dev
->flags
& IFF_PROMISC
)
1733 config
|= MACB_BIT(CAF
); /* Copy All Frames */
1734 else if (macb_is_gem(bp
) && bp
->dev
->features
& NETIF_F_RXCSUM
)
1735 config
|= GEM_BIT(RXCOEN
);
1736 if (!(bp
->dev
->flags
& IFF_BROADCAST
))
1737 config
|= MACB_BIT(NBC
); /* No BroadCast */
1738 config
|= macb_dbw(bp
);
1739 macb_writel(bp
, NCFGR
, config
);
1740 if ((bp
->caps
& MACB_CAPS_JUMBO
) && bp
->jumbo_max_len
)
1741 gem_writel(bp
, JML
, bp
->jumbo_max_len
);
1742 bp
->speed
= SPEED_10
;
1743 bp
->duplex
= DUPLEX_HALF
;
1744 bp
->rx_frm_len_mask
= MACB_RX_FRMLEN_MASK
;
1745 if (bp
->caps
& MACB_CAPS_JUMBO
)
1746 bp
->rx_frm_len_mask
= MACB_RX_JFRMLEN_MASK
;
1748 macb_configure_dma(bp
);
1750 /* Initialize TX and RX buffers */
1751 macb_writel(bp
, RBQP
, bp
->rx_ring_dma
);
1752 for (q
= 0, queue
= bp
->queues
; q
< bp
->num_queues
; ++q
, ++queue
) {
1753 queue_writel(queue
, TBQP
, queue
->tx_ring_dma
);
1755 /* Enable interrupts */
1756 queue_writel(queue
, IER
,
1762 /* Enable TX and RX */
1763 macb_writel(bp
, NCR
, MACB_BIT(RE
) | MACB_BIT(TE
) | MACB_BIT(MPE
));
1767 * The hash address register is 64 bits long and takes up two
1768 * locations in the memory map. The least significant bits are stored
1769 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1771 * The unicast hash enable and the multicast hash enable bits in the
1772 * network configuration register enable the reception of hash matched
1773 * frames. The destination address is reduced to a 6 bit index into
1774 * the 64 bit hash register using the following hash function. The
1775 * hash function is an exclusive or of every sixth bit of the
1776 * destination address.
1778 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1779 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1780 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1781 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1782 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1783 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1785 * da[0] represents the least significant bit of the first byte
1786 * received, that is, the multicast/unicast indicator, and da[47]
1787 * represents the most significant bit of the last byte received. If
1788 * the hash index, hi[n], points to a bit that is set in the hash
1789 * register then the frame will be matched according to whether the
1790 * frame is multicast or unicast. A multicast match will be signalled
1791 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1792 * index points to a bit set in the hash register. A unicast match
1793 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1794 * and the hash index points to a bit set in the hash register. To
1795 * receive all multicast frames, the hash register should be set with
1796 * all ones and the multicast hash enable bit should be set in the
1797 * network configuration register.
1800 static inline int hash_bit_value(int bitnr
, __u8
*addr
)
1802 if (addr
[bitnr
/ 8] & (1 << (bitnr
% 8)))
1808 * Return the hash index value for the specified address.
1810 static int hash_get_index(__u8
*addr
)
1815 for (j
= 0; j
< 6; j
++) {
1816 for (i
= 0, bitval
= 0; i
< 8; i
++)
1817 bitval
^= hash_bit_value(i
* 6 + j
, addr
);
1819 hash_index
|= (bitval
<< j
);
1826 * Add multicast addresses to the internal multicast-hash table.
1828 static void macb_sethashtable(struct net_device
*dev
)
1830 struct netdev_hw_addr
*ha
;
1831 unsigned long mc_filter
[2];
1833 struct macb
*bp
= netdev_priv(dev
);
1835 mc_filter
[0] = mc_filter
[1] = 0;
1837 netdev_for_each_mc_addr(ha
, dev
) {
1838 bitnr
= hash_get_index(ha
->addr
);
1839 mc_filter
[bitnr
>> 5] |= 1 << (bitnr
& 31);
1842 macb_or_gem_writel(bp
, HRB
, mc_filter
[0]);
1843 macb_or_gem_writel(bp
, HRT
, mc_filter
[1]);
1847 * Enable/Disable promiscuous and multicast modes.
1849 static void macb_set_rx_mode(struct net_device
*dev
)
1852 struct macb
*bp
= netdev_priv(dev
);
1854 cfg
= macb_readl(bp
, NCFGR
);
1856 if (dev
->flags
& IFF_PROMISC
) {
1857 /* Enable promiscuous mode */
1858 cfg
|= MACB_BIT(CAF
);
1860 /* Disable RX checksum offload */
1861 if (macb_is_gem(bp
))
1862 cfg
&= ~GEM_BIT(RXCOEN
);
1864 /* Disable promiscuous mode */
1865 cfg
&= ~MACB_BIT(CAF
);
1867 /* Enable RX checksum offload only if requested */
1868 if (macb_is_gem(bp
) && dev
->features
& NETIF_F_RXCSUM
)
1869 cfg
|= GEM_BIT(RXCOEN
);
1872 if (dev
->flags
& IFF_ALLMULTI
) {
1873 /* Enable all multicast mode */
1874 macb_or_gem_writel(bp
, HRB
, -1);
1875 macb_or_gem_writel(bp
, HRT
, -1);
1876 cfg
|= MACB_BIT(NCFGR_MTI
);
1877 } else if (!netdev_mc_empty(dev
)) {
1878 /* Enable specific multicasts */
1879 macb_sethashtable(dev
);
1880 cfg
|= MACB_BIT(NCFGR_MTI
);
1881 } else if (dev
->flags
& (~IFF_ALLMULTI
)) {
1882 /* Disable all multicast mode */
1883 macb_or_gem_writel(bp
, HRB
, 0);
1884 macb_or_gem_writel(bp
, HRT
, 0);
1885 cfg
&= ~MACB_BIT(NCFGR_MTI
);
1888 macb_writel(bp
, NCFGR
, cfg
);
1891 static int macb_open(struct net_device
*dev
)
1893 struct macb
*bp
= netdev_priv(dev
);
1894 size_t bufsz
= dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ NET_IP_ALIGN
;
1897 netdev_dbg(bp
->dev
, "open\n");
1899 /* carrier starts down */
1900 netif_carrier_off(dev
);
1902 /* if the phy is not yet register, retry later*/
1906 /* RX buffers initialization */
1907 macb_init_rx_buffer_size(bp
, bufsz
);
1909 err
= macb_alloc_consistent(bp
);
1911 netdev_err(dev
, "Unable to allocate DMA memory (error %d)\n",
1916 napi_enable(&bp
->napi
);
1918 bp
->macbgem_ops
.mog_init_rings(bp
);
1921 /* schedule a link state check */
1922 phy_start(bp
->phy_dev
);
1924 netif_tx_start_all_queues(dev
);
1929 static int macb_close(struct net_device
*dev
)
1931 struct macb
*bp
= netdev_priv(dev
);
1932 unsigned long flags
;
1934 netif_tx_stop_all_queues(dev
);
1935 napi_disable(&bp
->napi
);
1938 phy_stop(bp
->phy_dev
);
1940 spin_lock_irqsave(&bp
->lock
, flags
);
1942 netif_carrier_off(dev
);
1943 spin_unlock_irqrestore(&bp
->lock
, flags
);
1945 macb_free_consistent(bp
);
1950 static int macb_change_mtu(struct net_device
*dev
, int new_mtu
)
1952 struct macb
*bp
= netdev_priv(dev
);
1955 if (netif_running(dev
))
1958 max_mtu
= ETH_DATA_LEN
;
1959 if (bp
->caps
& MACB_CAPS_JUMBO
)
1960 max_mtu
= gem_readl(bp
, JML
) - ETH_HLEN
- ETH_FCS_LEN
;
1962 if ((new_mtu
> max_mtu
) || (new_mtu
< GEM_MTU_MIN_SIZE
))
1970 static void gem_update_stats(struct macb
*bp
)
1973 u32
*p
= &bp
->hw_stats
.gem
.tx_octets_31_0
;
1975 for (i
= 0; i
< GEM_STATS_LEN
; ++i
, ++p
) {
1976 u32 offset
= gem_statistics
[i
].offset
;
1977 u64 val
= bp
->macb_reg_readl(bp
, offset
);
1979 bp
->ethtool_stats
[i
] += val
;
1982 if (offset
== GEM_OCTTXL
|| offset
== GEM_OCTRXL
) {
1983 /* Add GEM_OCTTXH, GEM_OCTRXH */
1984 val
= bp
->macb_reg_readl(bp
, offset
+ 4);
1985 bp
->ethtool_stats
[i
] += ((u64
)val
) << 32;
1991 static struct net_device_stats
*gem_get_stats(struct macb
*bp
)
1993 struct gem_stats
*hwstat
= &bp
->hw_stats
.gem
;
1994 struct net_device_stats
*nstat
= &bp
->stats
;
1996 gem_update_stats(bp
);
1998 nstat
->rx_errors
= (hwstat
->rx_frame_check_sequence_errors
+
1999 hwstat
->rx_alignment_errors
+
2000 hwstat
->rx_resource_errors
+
2001 hwstat
->rx_overruns
+
2002 hwstat
->rx_oversize_frames
+
2003 hwstat
->rx_jabbers
+
2004 hwstat
->rx_undersized_frames
+
2005 hwstat
->rx_length_field_frame_errors
);
2006 nstat
->tx_errors
= (hwstat
->tx_late_collisions
+
2007 hwstat
->tx_excessive_collisions
+
2008 hwstat
->tx_underrun
+
2009 hwstat
->tx_carrier_sense_errors
);
2010 nstat
->multicast
= hwstat
->rx_multicast_frames
;
2011 nstat
->collisions
= (hwstat
->tx_single_collision_frames
+
2012 hwstat
->tx_multiple_collision_frames
+
2013 hwstat
->tx_excessive_collisions
);
2014 nstat
->rx_length_errors
= (hwstat
->rx_oversize_frames
+
2015 hwstat
->rx_jabbers
+
2016 hwstat
->rx_undersized_frames
+
2017 hwstat
->rx_length_field_frame_errors
);
2018 nstat
->rx_over_errors
= hwstat
->rx_resource_errors
;
2019 nstat
->rx_crc_errors
= hwstat
->rx_frame_check_sequence_errors
;
2020 nstat
->rx_frame_errors
= hwstat
->rx_alignment_errors
;
2021 nstat
->rx_fifo_errors
= hwstat
->rx_overruns
;
2022 nstat
->tx_aborted_errors
= hwstat
->tx_excessive_collisions
;
2023 nstat
->tx_carrier_errors
= hwstat
->tx_carrier_sense_errors
;
2024 nstat
->tx_fifo_errors
= hwstat
->tx_underrun
;
2029 static void gem_get_ethtool_stats(struct net_device
*dev
,
2030 struct ethtool_stats
*stats
, u64
*data
)
2034 bp
= netdev_priv(dev
);
2035 gem_update_stats(bp
);
2036 memcpy(data
, &bp
->ethtool_stats
, sizeof(u64
) * GEM_STATS_LEN
);
2039 static int gem_get_sset_count(struct net_device
*dev
, int sset
)
2043 return GEM_STATS_LEN
;
2049 static void gem_get_ethtool_strings(struct net_device
*dev
, u32 sset
, u8
*p
)
2055 for (i
= 0; i
< GEM_STATS_LEN
; i
++, p
+= ETH_GSTRING_LEN
)
2056 memcpy(p
, gem_statistics
[i
].stat_string
,
2062 static struct net_device_stats
*macb_get_stats(struct net_device
*dev
)
2064 struct macb
*bp
= netdev_priv(dev
);
2065 struct net_device_stats
*nstat
= &bp
->stats
;
2066 struct macb_stats
*hwstat
= &bp
->hw_stats
.macb
;
2068 if (macb_is_gem(bp
))
2069 return gem_get_stats(bp
);
2071 /* read stats from hardware */
2072 macb_update_stats(bp
);
2074 /* Convert HW stats into netdevice stats */
2075 nstat
->rx_errors
= (hwstat
->rx_fcs_errors
+
2076 hwstat
->rx_align_errors
+
2077 hwstat
->rx_resource_errors
+
2078 hwstat
->rx_overruns
+
2079 hwstat
->rx_oversize_pkts
+
2080 hwstat
->rx_jabbers
+
2081 hwstat
->rx_undersize_pkts
+
2082 hwstat
->rx_length_mismatch
);
2083 nstat
->tx_errors
= (hwstat
->tx_late_cols
+
2084 hwstat
->tx_excessive_cols
+
2085 hwstat
->tx_underruns
+
2086 hwstat
->tx_carrier_errors
+
2087 hwstat
->sqe_test_errors
);
2088 nstat
->collisions
= (hwstat
->tx_single_cols
+
2089 hwstat
->tx_multiple_cols
+
2090 hwstat
->tx_excessive_cols
);
2091 nstat
->rx_length_errors
= (hwstat
->rx_oversize_pkts
+
2092 hwstat
->rx_jabbers
+
2093 hwstat
->rx_undersize_pkts
+
2094 hwstat
->rx_length_mismatch
);
2095 nstat
->rx_over_errors
= hwstat
->rx_resource_errors
+
2096 hwstat
->rx_overruns
;
2097 nstat
->rx_crc_errors
= hwstat
->rx_fcs_errors
;
2098 nstat
->rx_frame_errors
= hwstat
->rx_align_errors
;
2099 nstat
->rx_fifo_errors
= hwstat
->rx_overruns
;
2100 /* XXX: What does "missed" mean? */
2101 nstat
->tx_aborted_errors
= hwstat
->tx_excessive_cols
;
2102 nstat
->tx_carrier_errors
= hwstat
->tx_carrier_errors
;
2103 nstat
->tx_fifo_errors
= hwstat
->tx_underruns
;
2104 /* Don't know about heartbeat or window errors... */
2109 static int macb_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
2111 struct macb
*bp
= netdev_priv(dev
);
2112 struct phy_device
*phydev
= bp
->phy_dev
;
2117 return phy_ethtool_gset(phydev
, cmd
);
2120 static int macb_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
2122 struct macb
*bp
= netdev_priv(dev
);
2123 struct phy_device
*phydev
= bp
->phy_dev
;
2128 return phy_ethtool_sset(phydev
, cmd
);
2131 static int macb_get_regs_len(struct net_device
*netdev
)
2133 return MACB_GREGS_NBR
* sizeof(u32
);
2136 static void macb_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
2139 struct macb
*bp
= netdev_priv(dev
);
2140 unsigned int tail
, head
;
2143 regs
->version
= (macb_readl(bp
, MID
) & ((1 << MACB_REV_SIZE
) - 1))
2144 | MACB_GREGS_VERSION
;
2146 tail
= macb_tx_ring_wrap(bp
->queues
[0].tx_tail
);
2147 head
= macb_tx_ring_wrap(bp
->queues
[0].tx_head
);
2149 regs_buff
[0] = macb_readl(bp
, NCR
);
2150 regs_buff
[1] = macb_or_gem_readl(bp
, NCFGR
);
2151 regs_buff
[2] = macb_readl(bp
, NSR
);
2152 regs_buff
[3] = macb_readl(bp
, TSR
);
2153 regs_buff
[4] = macb_readl(bp
, RBQP
);
2154 regs_buff
[5] = macb_readl(bp
, TBQP
);
2155 regs_buff
[6] = macb_readl(bp
, RSR
);
2156 regs_buff
[7] = macb_readl(bp
, IMR
);
2158 regs_buff
[8] = tail
;
2159 regs_buff
[9] = head
;
2160 regs_buff
[10] = macb_tx_dma(&bp
->queues
[0], tail
);
2161 regs_buff
[11] = macb_tx_dma(&bp
->queues
[0], head
);
2163 if (!(bp
->caps
& MACB_CAPS_USRIO_DISABLED
))
2164 regs_buff
[12] = macb_or_gem_readl(bp
, USRIO
);
2165 if (macb_is_gem(bp
)) {
2166 regs_buff
[13] = gem_readl(bp
, DMACFG
);
2170 static void macb_get_wol(struct net_device
*netdev
, struct ethtool_wolinfo
*wol
)
2172 struct macb
*bp
= netdev_priv(netdev
);
2177 if (bp
->wol
& MACB_WOL_HAS_MAGIC_PACKET
) {
2178 wol
->supported
= WAKE_MAGIC
;
2180 if (bp
->wol
& MACB_WOL_ENABLED
)
2181 wol
->wolopts
|= WAKE_MAGIC
;
2185 static int macb_set_wol(struct net_device
*netdev
, struct ethtool_wolinfo
*wol
)
2187 struct macb
*bp
= netdev_priv(netdev
);
2189 if (!(bp
->wol
& MACB_WOL_HAS_MAGIC_PACKET
) ||
2190 (wol
->wolopts
& ~WAKE_MAGIC
))
2193 if (wol
->wolopts
& WAKE_MAGIC
)
2194 bp
->wol
|= MACB_WOL_ENABLED
;
2196 bp
->wol
&= ~MACB_WOL_ENABLED
;
2198 device_set_wakeup_enable(&bp
->pdev
->dev
, bp
->wol
& MACB_WOL_ENABLED
);
2203 static const struct ethtool_ops macb_ethtool_ops
= {
2204 .get_settings
= macb_get_settings
,
2205 .set_settings
= macb_set_settings
,
2206 .get_regs_len
= macb_get_regs_len
,
2207 .get_regs
= macb_get_regs
,
2208 .get_link
= ethtool_op_get_link
,
2209 .get_ts_info
= ethtool_op_get_ts_info
,
2210 .get_wol
= macb_get_wol
,
2211 .set_wol
= macb_set_wol
,
2214 static const struct ethtool_ops gem_ethtool_ops
= {
2215 .get_settings
= macb_get_settings
,
2216 .set_settings
= macb_set_settings
,
2217 .get_regs_len
= macb_get_regs_len
,
2218 .get_regs
= macb_get_regs
,
2219 .get_link
= ethtool_op_get_link
,
2220 .get_ts_info
= ethtool_op_get_ts_info
,
2221 .get_ethtool_stats
= gem_get_ethtool_stats
,
2222 .get_strings
= gem_get_ethtool_strings
,
2223 .get_sset_count
= gem_get_sset_count
,
2226 static int macb_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
2228 struct macb
*bp
= netdev_priv(dev
);
2229 struct phy_device
*phydev
= bp
->phy_dev
;
2231 if (!netif_running(dev
))
2237 return phy_mii_ioctl(phydev
, rq
, cmd
);
2240 static int macb_set_features(struct net_device
*netdev
,
2241 netdev_features_t features
)
2243 struct macb
*bp
= netdev_priv(netdev
);
2244 netdev_features_t changed
= features
^ netdev
->features
;
2246 /* TX checksum offload */
2247 if ((changed
& NETIF_F_HW_CSUM
) && macb_is_gem(bp
)) {
2250 dmacfg
= gem_readl(bp
, DMACFG
);
2251 if (features
& NETIF_F_HW_CSUM
)
2252 dmacfg
|= GEM_BIT(TXCOEN
);
2254 dmacfg
&= ~GEM_BIT(TXCOEN
);
2255 gem_writel(bp
, DMACFG
, dmacfg
);
2258 /* RX checksum offload */
2259 if ((changed
& NETIF_F_RXCSUM
) && macb_is_gem(bp
)) {
2262 netcfg
= gem_readl(bp
, NCFGR
);
2263 if (features
& NETIF_F_RXCSUM
&&
2264 !(netdev
->flags
& IFF_PROMISC
))
2265 netcfg
|= GEM_BIT(RXCOEN
);
2267 netcfg
&= ~GEM_BIT(RXCOEN
);
2268 gem_writel(bp
, NCFGR
, netcfg
);
2274 static const struct net_device_ops macb_netdev_ops
= {
2275 .ndo_open
= macb_open
,
2276 .ndo_stop
= macb_close
,
2277 .ndo_start_xmit
= macb_start_xmit
,
2278 .ndo_set_rx_mode
= macb_set_rx_mode
,
2279 .ndo_get_stats
= macb_get_stats
,
2280 .ndo_do_ioctl
= macb_ioctl
,
2281 .ndo_validate_addr
= eth_validate_addr
,
2282 .ndo_change_mtu
= macb_change_mtu
,
2283 .ndo_set_mac_address
= eth_mac_addr
,
2284 #ifdef CONFIG_NET_POLL_CONTROLLER
2285 .ndo_poll_controller
= macb_poll_controller
,
2287 .ndo_set_features
= macb_set_features
,
2291 * Configure peripheral capabilities according to device tree
2292 * and integration options used
2294 static void macb_configure_caps(struct macb
*bp
, const struct macb_config
*dt_conf
)
2299 bp
->caps
= dt_conf
->caps
;
2301 if (hw_is_gem(bp
->regs
, bp
->native_io
)) {
2302 bp
->caps
|= MACB_CAPS_MACB_IS_GEM
;
2304 dcfg
= gem_readl(bp
, DCFG1
);
2305 if (GEM_BFEXT(IRQCOR
, dcfg
) == 0)
2306 bp
->caps
|= MACB_CAPS_ISR_CLEAR_ON_WRITE
;
2307 dcfg
= gem_readl(bp
, DCFG2
);
2308 if ((dcfg
& (GEM_BIT(RX_PKT_BUFF
) | GEM_BIT(TX_PKT_BUFF
))) == 0)
2309 bp
->caps
|= MACB_CAPS_FIFO_MODE
;
2312 dev_dbg(&bp
->pdev
->dev
, "Cadence caps 0x%08x\n", bp
->caps
);
2315 static void macb_probe_queues(void __iomem
*mem
,
2317 unsigned int *queue_mask
,
2318 unsigned int *num_queues
)
2325 /* is it macb or gem ?
2327 * We need to read directly from the hardware here because
2328 * we are early in the probe process and don't have the
2329 * MACB_CAPS_MACB_IS_GEM flag positioned
2331 if (!hw_is_gem(mem
, native_io
))
2334 /* bit 0 is never set but queue 0 always exists */
2335 *queue_mask
= readl_relaxed(mem
+ GEM_DCFG6
) & 0xff;
2339 for (hw_q
= 1; hw_q
< MACB_MAX_QUEUES
; ++hw_q
)
2340 if (*queue_mask
& (1 << hw_q
))
2344 static int macb_clk_init(struct platform_device
*pdev
, struct clk
**pclk
,
2345 struct clk
**hclk
, struct clk
**tx_clk
)
2349 *pclk
= devm_clk_get(&pdev
->dev
, "pclk");
2350 if (IS_ERR(*pclk
)) {
2351 err
= PTR_ERR(*pclk
);
2352 dev_err(&pdev
->dev
, "failed to get macb_clk (%u)\n", err
);
2356 *hclk
= devm_clk_get(&pdev
->dev
, "hclk");
2357 if (IS_ERR(*hclk
)) {
2358 err
= PTR_ERR(*hclk
);
2359 dev_err(&pdev
->dev
, "failed to get hclk (%u)\n", err
);
2363 *tx_clk
= devm_clk_get(&pdev
->dev
, "tx_clk");
2364 if (IS_ERR(*tx_clk
))
2367 err
= clk_prepare_enable(*pclk
);
2369 dev_err(&pdev
->dev
, "failed to enable pclk (%u)\n", err
);
2373 err
= clk_prepare_enable(*hclk
);
2375 dev_err(&pdev
->dev
, "failed to enable hclk (%u)\n", err
);
2376 goto err_disable_pclk
;
2379 err
= clk_prepare_enable(*tx_clk
);
2381 dev_err(&pdev
->dev
, "failed to enable tx_clk (%u)\n", err
);
2382 goto err_disable_hclk
;
2388 clk_disable_unprepare(*hclk
);
2391 clk_disable_unprepare(*pclk
);
2396 static int macb_init(struct platform_device
*pdev
)
2398 struct net_device
*dev
= platform_get_drvdata(pdev
);
2399 unsigned int hw_q
, q
;
2400 struct macb
*bp
= netdev_priv(dev
);
2401 struct macb_queue
*queue
;
2405 /* set the queue register mapping once for all: queue0 has a special
2406 * register mapping but we don't want to test the queue index then
2407 * compute the corresponding register offset at run time.
2409 for (hw_q
= 0, q
= 0; hw_q
< MACB_MAX_QUEUES
; ++hw_q
) {
2410 if (!(bp
->queue_mask
& (1 << hw_q
)))
2413 queue
= &bp
->queues
[q
];
2416 queue
->ISR
= GEM_ISR(hw_q
- 1);
2417 queue
->IER
= GEM_IER(hw_q
- 1);
2418 queue
->IDR
= GEM_IDR(hw_q
- 1);
2419 queue
->IMR
= GEM_IMR(hw_q
- 1);
2420 queue
->TBQP
= GEM_TBQP(hw_q
- 1);
2422 /* queue0 uses legacy registers */
2423 queue
->ISR
= MACB_ISR
;
2424 queue
->IER
= MACB_IER
;
2425 queue
->IDR
= MACB_IDR
;
2426 queue
->IMR
= MACB_IMR
;
2427 queue
->TBQP
= MACB_TBQP
;
2430 /* get irq: here we use the linux queue index, not the hardware
2431 * queue index. the queue irq definitions in the device tree
2432 * must remove the optional gaps that could exist in the
2433 * hardware queue mask.
2435 queue
->irq
= platform_get_irq(pdev
, q
);
2436 err
= devm_request_irq(&pdev
->dev
, queue
->irq
, macb_interrupt
,
2437 IRQF_SHARED
, dev
->name
, queue
);
2440 "Unable to request IRQ %d (error %d)\n",
2445 INIT_WORK(&queue
->tx_error_task
, macb_tx_error_task
);
2449 dev
->netdev_ops
= &macb_netdev_ops
;
2450 netif_napi_add(dev
, &bp
->napi
, macb_poll
, 64);
2452 /* setup appropriated routines according to adapter type */
2453 if (macb_is_gem(bp
)) {
2454 bp
->max_tx_length
= GEM_MAX_TX_LEN
;
2455 bp
->macbgem_ops
.mog_alloc_rx_buffers
= gem_alloc_rx_buffers
;
2456 bp
->macbgem_ops
.mog_free_rx_buffers
= gem_free_rx_buffers
;
2457 bp
->macbgem_ops
.mog_init_rings
= gem_init_rings
;
2458 bp
->macbgem_ops
.mog_rx
= gem_rx
;
2459 dev
->ethtool_ops
= &gem_ethtool_ops
;
2461 bp
->max_tx_length
= MACB_MAX_TX_LEN
;
2462 bp
->macbgem_ops
.mog_alloc_rx_buffers
= macb_alloc_rx_buffers
;
2463 bp
->macbgem_ops
.mog_free_rx_buffers
= macb_free_rx_buffers
;
2464 bp
->macbgem_ops
.mog_init_rings
= macb_init_rings
;
2465 bp
->macbgem_ops
.mog_rx
= macb_rx
;
2466 dev
->ethtool_ops
= &macb_ethtool_ops
;
2470 dev
->hw_features
= NETIF_F_SG
;
2471 /* Checksum offload is only available on gem with packet buffer */
2472 if (macb_is_gem(bp
) && !(bp
->caps
& MACB_CAPS_FIFO_MODE
))
2473 dev
->hw_features
|= NETIF_F_HW_CSUM
| NETIF_F_RXCSUM
;
2474 if (bp
->caps
& MACB_CAPS_SG_DISABLED
)
2475 dev
->hw_features
&= ~NETIF_F_SG
;
2476 dev
->features
= dev
->hw_features
;
2478 if (!(bp
->caps
& MACB_CAPS_USRIO_DISABLED
)) {
2480 if (bp
->phy_interface
== PHY_INTERFACE_MODE_RGMII
)
2481 val
= GEM_BIT(RGMII
);
2482 else if (bp
->phy_interface
== PHY_INTERFACE_MODE_RMII
&&
2483 (bp
->caps
& MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII
))
2484 val
= MACB_BIT(RMII
);
2485 else if (!(bp
->caps
& MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII
))
2486 val
= MACB_BIT(MII
);
2488 if (bp
->caps
& MACB_CAPS_USRIO_HAS_CLKEN
)
2489 val
|= MACB_BIT(CLKEN
);
2491 macb_or_gem_writel(bp
, USRIO
, val
);
2494 /* Set MII management clock divider */
2495 val
= macb_mdc_clk_div(bp
);
2496 val
|= macb_dbw(bp
);
2497 if (bp
->phy_interface
== PHY_INTERFACE_MODE_SGMII
)
2498 val
|= GEM_BIT(SGMIIEN
) | GEM_BIT(PCSSEL
);
2499 macb_writel(bp
, NCFGR
, val
);
2504 #if defined(CONFIG_OF)
2505 /* 1518 rounded up */
2506 #define AT91ETHER_MAX_RBUFF_SZ 0x600
2507 /* max number of receive buffers */
2508 #define AT91ETHER_MAX_RX_DESCR 9
2510 /* Initialize and start the Receiver and Transmit subsystems */
2511 static int at91ether_start(struct net_device
*dev
)
2513 struct macb
*lp
= netdev_priv(dev
);
2518 lp
->rx_ring
= dma_alloc_coherent(&lp
->pdev
->dev
,
2519 (AT91ETHER_MAX_RX_DESCR
*
2520 sizeof(struct macb_dma_desc
)),
2521 &lp
->rx_ring_dma
, GFP_KERNEL
);
2525 lp
->rx_buffers
= dma_alloc_coherent(&lp
->pdev
->dev
,
2526 AT91ETHER_MAX_RX_DESCR
*
2527 AT91ETHER_MAX_RBUFF_SZ
,
2528 &lp
->rx_buffers_dma
, GFP_KERNEL
);
2529 if (!lp
->rx_buffers
) {
2530 dma_free_coherent(&lp
->pdev
->dev
,
2531 AT91ETHER_MAX_RX_DESCR
*
2532 sizeof(struct macb_dma_desc
),
2533 lp
->rx_ring
, lp
->rx_ring_dma
);
2538 addr
= lp
->rx_buffers_dma
;
2539 for (i
= 0; i
< AT91ETHER_MAX_RX_DESCR
; i
++) {
2540 lp
->rx_ring
[i
].addr
= addr
;
2541 lp
->rx_ring
[i
].ctrl
= 0;
2542 addr
+= AT91ETHER_MAX_RBUFF_SZ
;
2545 /* Set the Wrap bit on the last descriptor */
2546 lp
->rx_ring
[AT91ETHER_MAX_RX_DESCR
- 1].addr
|= MACB_BIT(RX_WRAP
);
2548 /* Reset buffer index */
2551 /* Program address of descriptor list in Rx Buffer Queue register */
2552 macb_writel(lp
, RBQP
, lp
->rx_ring_dma
);
2554 /* Enable Receive and Transmit */
2555 ctl
= macb_readl(lp
, NCR
);
2556 macb_writel(lp
, NCR
, ctl
| MACB_BIT(RE
) | MACB_BIT(TE
));
2561 /* Open the ethernet interface */
2562 static int at91ether_open(struct net_device
*dev
)
2564 struct macb
*lp
= netdev_priv(dev
);
2568 /* Clear internal statistics */
2569 ctl
= macb_readl(lp
, NCR
);
2570 macb_writel(lp
, NCR
, ctl
| MACB_BIT(CLRSTAT
));
2572 macb_set_hwaddr(lp
);
2574 ret
= at91ether_start(dev
);
2578 /* Enable MAC interrupts */
2579 macb_writel(lp
, IER
, MACB_BIT(RCOMP
) |
2581 MACB_BIT(ISR_TUND
) |
2584 MACB_BIT(ISR_ROVR
) |
2587 /* schedule a link state check */
2588 phy_start(lp
->phy_dev
);
2590 netif_start_queue(dev
);
2595 /* Close the interface */
2596 static int at91ether_close(struct net_device
*dev
)
2598 struct macb
*lp
= netdev_priv(dev
);
2601 /* Disable Receiver and Transmitter */
2602 ctl
= macb_readl(lp
, NCR
);
2603 macb_writel(lp
, NCR
, ctl
& ~(MACB_BIT(TE
) | MACB_BIT(RE
)));
2605 /* Disable MAC interrupts */
2606 macb_writel(lp
, IDR
, MACB_BIT(RCOMP
) |
2608 MACB_BIT(ISR_TUND
) |
2611 MACB_BIT(ISR_ROVR
) |
2614 netif_stop_queue(dev
);
2616 dma_free_coherent(&lp
->pdev
->dev
,
2617 AT91ETHER_MAX_RX_DESCR
*
2618 sizeof(struct macb_dma_desc
),
2619 lp
->rx_ring
, lp
->rx_ring_dma
);
2622 dma_free_coherent(&lp
->pdev
->dev
,
2623 AT91ETHER_MAX_RX_DESCR
* AT91ETHER_MAX_RBUFF_SZ
,
2624 lp
->rx_buffers
, lp
->rx_buffers_dma
);
2625 lp
->rx_buffers
= NULL
;
2630 /* Transmit packet */
2631 static int at91ether_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2633 struct macb
*lp
= netdev_priv(dev
);
2635 if (macb_readl(lp
, TSR
) & MACB_BIT(RM9200_BNQ
)) {
2636 netif_stop_queue(dev
);
2638 /* Store packet information (to free when Tx completed) */
2640 lp
->skb_length
= skb
->len
;
2641 lp
->skb_physaddr
= dma_map_single(NULL
, skb
->data
, skb
->len
,
2644 /* Set address of the data in the Transmit Address register */
2645 macb_writel(lp
, TAR
, lp
->skb_physaddr
);
2646 /* Set length of the packet in the Transmit Control register */
2647 macb_writel(lp
, TCR
, skb
->len
);
2650 netdev_err(dev
, "%s called, but device is busy!\n", __func__
);
2651 return NETDEV_TX_BUSY
;
2654 return NETDEV_TX_OK
;
2657 /* Extract received frame from buffer descriptors and sent to upper layers.
2658 * (Called from interrupt context)
2660 static void at91ether_rx(struct net_device
*dev
)
2662 struct macb
*lp
= netdev_priv(dev
);
2663 unsigned char *p_recv
;
2664 struct sk_buff
*skb
;
2665 unsigned int pktlen
;
2667 while (lp
->rx_ring
[lp
->rx_tail
].addr
& MACB_BIT(RX_USED
)) {
2668 p_recv
= lp
->rx_buffers
+ lp
->rx_tail
* AT91ETHER_MAX_RBUFF_SZ
;
2669 pktlen
= MACB_BF(RX_FRMLEN
, lp
->rx_ring
[lp
->rx_tail
].ctrl
);
2670 skb
= netdev_alloc_skb(dev
, pktlen
+ 2);
2672 skb_reserve(skb
, 2);
2673 memcpy(skb_put(skb
, pktlen
), p_recv
, pktlen
);
2675 skb
->protocol
= eth_type_trans(skb
, dev
);
2676 lp
->stats
.rx_packets
++;
2677 lp
->stats
.rx_bytes
+= pktlen
;
2680 lp
->stats
.rx_dropped
++;
2683 if (lp
->rx_ring
[lp
->rx_tail
].ctrl
& MACB_BIT(RX_MHASH_MATCH
))
2684 lp
->stats
.multicast
++;
2686 /* reset ownership bit */
2687 lp
->rx_ring
[lp
->rx_tail
].addr
&= ~MACB_BIT(RX_USED
);
2689 /* wrap after last buffer */
2690 if (lp
->rx_tail
== AT91ETHER_MAX_RX_DESCR
- 1)
2697 /* MAC interrupt handler */
2698 static irqreturn_t
at91ether_interrupt(int irq
, void *dev_id
)
2700 struct net_device
*dev
= dev_id
;
2701 struct macb
*lp
= netdev_priv(dev
);
2704 /* MAC Interrupt Status register indicates what interrupts are pending.
2705 * It is automatically cleared once read.
2707 intstatus
= macb_readl(lp
, ISR
);
2709 /* Receive complete */
2710 if (intstatus
& MACB_BIT(RCOMP
))
2713 /* Transmit complete */
2714 if (intstatus
& MACB_BIT(TCOMP
)) {
2715 /* The TCOM bit is set even if the transmission failed */
2716 if (intstatus
& (MACB_BIT(ISR_TUND
) | MACB_BIT(ISR_RLE
)))
2717 lp
->stats
.tx_errors
++;
2720 dev_kfree_skb_irq(lp
->skb
);
2722 dma_unmap_single(NULL
, lp
->skb_physaddr
,
2723 lp
->skb_length
, DMA_TO_DEVICE
);
2724 lp
->stats
.tx_packets
++;
2725 lp
->stats
.tx_bytes
+= lp
->skb_length
;
2727 netif_wake_queue(dev
);
2730 /* Work-around for EMAC Errata section 41.3.1 */
2731 if (intstatus
& MACB_BIT(RXUBR
)) {
2732 ctl
= macb_readl(lp
, NCR
);
2733 macb_writel(lp
, NCR
, ctl
& ~MACB_BIT(RE
));
2734 macb_writel(lp
, NCR
, ctl
| MACB_BIT(RE
));
2737 if (intstatus
& MACB_BIT(ISR_ROVR
))
2738 netdev_err(dev
, "ROVR error\n");
2743 #ifdef CONFIG_NET_POLL_CONTROLLER
2744 static void at91ether_poll_controller(struct net_device
*dev
)
2746 unsigned long flags
;
2748 local_irq_save(flags
);
2749 at91ether_interrupt(dev
->irq
, dev
);
2750 local_irq_restore(flags
);
2754 static const struct net_device_ops at91ether_netdev_ops
= {
2755 .ndo_open
= at91ether_open
,
2756 .ndo_stop
= at91ether_close
,
2757 .ndo_start_xmit
= at91ether_start_xmit
,
2758 .ndo_get_stats
= macb_get_stats
,
2759 .ndo_set_rx_mode
= macb_set_rx_mode
,
2760 .ndo_set_mac_address
= eth_mac_addr
,
2761 .ndo_do_ioctl
= macb_ioctl
,
2762 .ndo_validate_addr
= eth_validate_addr
,
2763 .ndo_change_mtu
= eth_change_mtu
,
2764 #ifdef CONFIG_NET_POLL_CONTROLLER
2765 .ndo_poll_controller
= at91ether_poll_controller
,
2769 static int at91ether_clk_init(struct platform_device
*pdev
, struct clk
**pclk
,
2770 struct clk
**hclk
, struct clk
**tx_clk
)
2777 *pclk
= devm_clk_get(&pdev
->dev
, "ether_clk");
2779 return PTR_ERR(*pclk
);
2781 err
= clk_prepare_enable(*pclk
);
2783 dev_err(&pdev
->dev
, "failed to enable pclk (%u)\n", err
);
2790 static int at91ether_init(struct platform_device
*pdev
)
2792 struct net_device
*dev
= platform_get_drvdata(pdev
);
2793 struct macb
*bp
= netdev_priv(dev
);
2797 dev
->netdev_ops
= &at91ether_netdev_ops
;
2798 dev
->ethtool_ops
= &macb_ethtool_ops
;
2800 err
= devm_request_irq(&pdev
->dev
, dev
->irq
, at91ether_interrupt
,
2805 macb_writel(bp
, NCR
, 0);
2807 reg
= MACB_BF(CLK
, MACB_CLK_DIV32
) | MACB_BIT(BIG
);
2808 if (bp
->phy_interface
== PHY_INTERFACE_MODE_RMII
)
2809 reg
|= MACB_BIT(RM9200_RMII
);
2811 macb_writel(bp
, NCFGR
, reg
);
2816 static const struct macb_config at91sam9260_config
= {
2817 .caps
= MACB_CAPS_USRIO_HAS_CLKEN
| MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII
,
2818 .clk_init
= macb_clk_init
,
2822 static const struct macb_config pc302gem_config
= {
2823 .caps
= MACB_CAPS_SG_DISABLED
| MACB_CAPS_GIGABIT_MODE_AVAILABLE
,
2824 .dma_burst_length
= 16,
2825 .clk_init
= macb_clk_init
,
2829 static const struct macb_config sama5d2_config
= {
2830 .caps
= MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII
,
2831 .dma_burst_length
= 16,
2832 .clk_init
= macb_clk_init
,
2836 static const struct macb_config sama5d3_config
= {
2837 .caps
= MACB_CAPS_SG_DISABLED
| MACB_CAPS_GIGABIT_MODE_AVAILABLE
2838 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII
,
2839 .dma_burst_length
= 16,
2840 .clk_init
= macb_clk_init
,
2844 static const struct macb_config sama5d4_config
= {
2845 .caps
= MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII
,
2846 .dma_burst_length
= 4,
2847 .clk_init
= macb_clk_init
,
2851 static const struct macb_config emac_config
= {
2852 .clk_init
= at91ether_clk_init
,
2853 .init
= at91ether_init
,
2856 static const struct macb_config np4_config
= {
2857 .caps
= MACB_CAPS_USRIO_DISABLED
,
2858 .clk_init
= macb_clk_init
,
2862 static const struct macb_config zynqmp_config
= {
2863 .caps
= MACB_CAPS_GIGABIT_MODE_AVAILABLE
| MACB_CAPS_JUMBO
,
2864 .dma_burst_length
= 16,
2865 .clk_init
= macb_clk_init
,
2867 .jumbo_max_len
= 10240,
2870 static const struct macb_config zynq_config
= {
2871 .caps
= MACB_CAPS_GIGABIT_MODE_AVAILABLE
| MACB_CAPS_NO_GIGABIT_HALF
,
2872 .dma_burst_length
= 16,
2873 .clk_init
= macb_clk_init
,
2877 static const struct of_device_id macb_dt_ids
[] = {
2878 { .compatible
= "cdns,at32ap7000-macb" },
2879 { .compatible
= "cdns,at91sam9260-macb", .data
= &at91sam9260_config
},
2880 { .compatible
= "cdns,macb" },
2881 { .compatible
= "cdns,np4-macb", .data
= &np4_config
},
2882 { .compatible
= "cdns,pc302-gem", .data
= &pc302gem_config
},
2883 { .compatible
= "cdns,gem", .data
= &pc302gem_config
},
2884 { .compatible
= "atmel,sama5d2-gem", .data
= &sama5d2_config
},
2885 { .compatible
= "atmel,sama5d3-gem", .data
= &sama5d3_config
},
2886 { .compatible
= "atmel,sama5d4-gem", .data
= &sama5d4_config
},
2887 { .compatible
= "cdns,at91rm9200-emac", .data
= &emac_config
},
2888 { .compatible
= "cdns,emac", .data
= &emac_config
},
2889 { .compatible
= "cdns,zynqmp-gem", .data
= &zynqmp_config
},
2890 { .compatible
= "cdns,zynq-gem", .data
= &zynq_config
},
2893 MODULE_DEVICE_TABLE(of
, macb_dt_ids
);
2894 #endif /* CONFIG_OF */
2896 static int macb_probe(struct platform_device
*pdev
)
2898 int (*clk_init
)(struct platform_device
*, struct clk
**,
2899 struct clk
**, struct clk
**)
2901 int (*init
)(struct platform_device
*) = macb_init
;
2902 struct device_node
*np
= pdev
->dev
.of_node
;
2903 struct device_node
*phy_node
;
2904 const struct macb_config
*macb_config
= NULL
;
2905 struct clk
*pclk
, *hclk
= NULL
, *tx_clk
= NULL
;
2906 unsigned int queue_mask
, num_queues
;
2907 struct macb_platform_data
*pdata
;
2909 struct phy_device
*phydev
;
2910 struct net_device
*dev
;
2911 struct resource
*regs
;
2917 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2918 mem
= devm_ioremap_resource(&pdev
->dev
, regs
);
2920 return PTR_ERR(mem
);
2923 const struct of_device_id
*match
;
2925 match
= of_match_node(macb_dt_ids
, np
);
2926 if (match
&& match
->data
) {
2927 macb_config
= match
->data
;
2928 clk_init
= macb_config
->clk_init
;
2929 init
= macb_config
->init
;
2933 err
= clk_init(pdev
, &pclk
, &hclk
, &tx_clk
);
2937 native_io
= hw_is_native_io(mem
);
2939 macb_probe_queues(mem
, native_io
, &queue_mask
, &num_queues
);
2940 dev
= alloc_etherdev_mq(sizeof(*bp
), num_queues
);
2943 goto err_disable_clocks
;
2946 dev
->base_addr
= regs
->start
;
2948 SET_NETDEV_DEV(dev
, &pdev
->dev
);
2950 bp
= netdev_priv(dev
);
2954 bp
->native_io
= native_io
;
2956 bp
->macb_reg_readl
= hw_readl_native
;
2957 bp
->macb_reg_writel
= hw_writel_native
;
2959 bp
->macb_reg_readl
= hw_readl
;
2960 bp
->macb_reg_writel
= hw_writel
;
2962 bp
->num_queues
= num_queues
;
2963 bp
->queue_mask
= queue_mask
;
2965 bp
->dma_burst_length
= macb_config
->dma_burst_length
;
2968 bp
->tx_clk
= tx_clk
;
2970 bp
->jumbo_max_len
= macb_config
->jumbo_max_len
;
2973 if (of_get_property(np
, "magic-packet", NULL
))
2974 bp
->wol
|= MACB_WOL_HAS_MAGIC_PACKET
;
2975 device_init_wakeup(&pdev
->dev
, bp
->wol
& MACB_WOL_HAS_MAGIC_PACKET
);
2977 spin_lock_init(&bp
->lock
);
2979 /* setup capabilities */
2980 macb_configure_caps(bp
, macb_config
);
2982 platform_set_drvdata(pdev
, dev
);
2984 dev
->irq
= platform_get_irq(pdev
, 0);
2987 goto err_disable_clocks
;
2990 mac
= of_get_mac_address(np
);
2992 memcpy(bp
->dev
->dev_addr
, mac
, ETH_ALEN
);
2994 macb_get_hwaddr(bp
);
2996 /* Power up the PHY if there is a GPIO reset */
2997 phy_node
= of_get_next_available_child(np
, NULL
);
2999 int gpio
= of_get_named_gpio(phy_node
, "reset-gpios", 0);
3000 if (gpio_is_valid(gpio
)) {
3001 bp
->reset_gpio
= gpio_to_desc(gpio
);
3002 gpiod_direction_output(bp
->reset_gpio
, 1);
3005 of_node_put(phy_node
);
3007 err
= of_get_phy_mode(np
);
3009 pdata
= dev_get_platdata(&pdev
->dev
);
3010 if (pdata
&& pdata
->is_rmii
)
3011 bp
->phy_interface
= PHY_INTERFACE_MODE_RMII
;
3013 bp
->phy_interface
= PHY_INTERFACE_MODE_MII
;
3015 bp
->phy_interface
= err
;
3018 /* IP specific init */
3021 goto err_out_free_netdev
;
3023 err
= register_netdev(dev
);
3025 dev_err(&pdev
->dev
, "Cannot register net device, aborting.\n");
3026 goto err_out_unregister_netdev
;
3029 err
= macb_mii_init(bp
);
3031 goto err_out_unregister_netdev
;
3033 netif_carrier_off(dev
);
3035 netdev_info(dev
, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
3036 macb_is_gem(bp
) ? "GEM" : "MACB", macb_readl(bp
, MID
),
3037 dev
->base_addr
, dev
->irq
, dev
->dev_addr
);
3039 phydev
= bp
->phy_dev
;
3040 phy_attached_info(phydev
);
3044 err_out_unregister_netdev
:
3045 unregister_netdev(dev
);
3047 err_out_free_netdev
:
3051 clk_disable_unprepare(tx_clk
);
3052 clk_disable_unprepare(hclk
);
3053 clk_disable_unprepare(pclk
);
3058 static int macb_remove(struct platform_device
*pdev
)
3060 struct net_device
*dev
;
3063 dev
= platform_get_drvdata(pdev
);
3066 bp
= netdev_priv(dev
);
3068 phy_disconnect(bp
->phy_dev
);
3069 mdiobus_unregister(bp
->mii_bus
);
3070 mdiobus_free(bp
->mii_bus
);
3072 /* Shutdown the PHY if there is a GPIO reset */
3074 gpiod_set_value(bp
->reset_gpio
, 0);
3076 unregister_netdev(dev
);
3077 clk_disable_unprepare(bp
->tx_clk
);
3078 clk_disable_unprepare(bp
->hclk
);
3079 clk_disable_unprepare(bp
->pclk
);
3086 static int __maybe_unused
macb_suspend(struct device
*dev
)
3088 struct platform_device
*pdev
= to_platform_device(dev
);
3089 struct net_device
*netdev
= platform_get_drvdata(pdev
);
3090 struct macb
*bp
= netdev_priv(netdev
);
3092 netif_carrier_off(netdev
);
3093 netif_device_detach(netdev
);
3095 if (bp
->wol
& MACB_WOL_ENABLED
) {
3096 macb_writel(bp
, IER
, MACB_BIT(WOL
));
3097 macb_writel(bp
, WOL
, MACB_BIT(MAG
));
3098 enable_irq_wake(bp
->queues
[0].irq
);
3100 clk_disable_unprepare(bp
->tx_clk
);
3101 clk_disable_unprepare(bp
->hclk
);
3102 clk_disable_unprepare(bp
->pclk
);
3108 static int __maybe_unused
macb_resume(struct device
*dev
)
3110 struct platform_device
*pdev
= to_platform_device(dev
);
3111 struct net_device
*netdev
= platform_get_drvdata(pdev
);
3112 struct macb
*bp
= netdev_priv(netdev
);
3114 if (bp
->wol
& MACB_WOL_ENABLED
) {
3115 macb_writel(bp
, IDR
, MACB_BIT(WOL
));
3116 macb_writel(bp
, WOL
, 0);
3117 disable_irq_wake(bp
->queues
[0].irq
);
3119 clk_prepare_enable(bp
->pclk
);
3120 clk_prepare_enable(bp
->hclk
);
3121 clk_prepare_enable(bp
->tx_clk
);
3124 netif_device_attach(netdev
);
3129 static SIMPLE_DEV_PM_OPS(macb_pm_ops
, macb_suspend
, macb_resume
);
3131 static struct platform_driver macb_driver
= {
3132 .probe
= macb_probe
,
3133 .remove
= macb_remove
,
3136 .of_match_table
= of_match_ptr(macb_dt_ids
),
3141 module_platform_driver(macb_driver
);
3143 MODULE_LICENSE("GPL");
3144 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
3145 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
3146 MODULE_ALIAS("platform:macb");