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b8023a7484e0086657f026053804fef7b37cfa04
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
1 /*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/mlx5/flow_table.h>
34 #include "en.h"
35
36 struct mlx5e_rq_param {
37 u32 rqc[MLX5_ST_SZ_DW(rqc)];
38 struct mlx5_wq_param wq;
39 };
40
41 struct mlx5e_sq_param {
42 u32 sqc[MLX5_ST_SZ_DW(sqc)];
43 struct mlx5_wq_param wq;
44 u16 max_inline;
45 };
46
47 struct mlx5e_cq_param {
48 u32 cqc[MLX5_ST_SZ_DW(cqc)];
49 struct mlx5_wq_param wq;
50 u16 eq_ix;
51 };
52
53 struct mlx5e_channel_param {
54 struct mlx5e_rq_param rq;
55 struct mlx5e_sq_param sq;
56 struct mlx5e_cq_param rx_cq;
57 struct mlx5e_cq_param tx_cq;
58 };
59
60 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
61 {
62 struct mlx5_core_dev *mdev = priv->mdev;
63 u8 port_state;
64
65 port_state = mlx5_query_vport_state(mdev,
66 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT);
67
68 if (port_state == VPORT_STATE_UP)
69 netif_carrier_on(priv->netdev);
70 else
71 netif_carrier_off(priv->netdev);
72 }
73
74 static void mlx5e_update_carrier_work(struct work_struct *work)
75 {
76 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
77 update_carrier_work);
78
79 mutex_lock(&priv->state_lock);
80 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
81 mlx5e_update_carrier(priv);
82 mutex_unlock(&priv->state_lock);
83 }
84
85 void mlx5e_update_stats(struct mlx5e_priv *priv)
86 {
87 struct mlx5_core_dev *mdev = priv->mdev;
88 struct mlx5e_vport_stats *s = &priv->stats.vport;
89 struct mlx5e_rq_stats *rq_stats;
90 struct mlx5e_sq_stats *sq_stats;
91 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
92 u32 *out;
93 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
94 u64 tx_offload_none;
95 int i, j;
96
97 out = mlx5_vzalloc(outlen);
98 if (!out)
99 return;
100
101 /* Collect firts the SW counters and then HW for consistency */
102 s->tso_packets = 0;
103 s->tso_bytes = 0;
104 s->tx_queue_stopped = 0;
105 s->tx_queue_wake = 0;
106 s->tx_queue_dropped = 0;
107 tx_offload_none = 0;
108 s->lro_packets = 0;
109 s->lro_bytes = 0;
110 s->rx_csum_none = 0;
111 s->rx_wqe_err = 0;
112 for (i = 0; i < priv->params.num_channels; i++) {
113 rq_stats = &priv->channel[i]->rq.stats;
114
115 s->lro_packets += rq_stats->lro_packets;
116 s->lro_bytes += rq_stats->lro_bytes;
117 s->rx_csum_none += rq_stats->csum_none;
118 s->rx_wqe_err += rq_stats->wqe_err;
119
120 for (j = 0; j < priv->params.num_tc; j++) {
121 sq_stats = &priv->channel[i]->sq[j].stats;
122
123 s->tso_packets += sq_stats->tso_packets;
124 s->tso_bytes += sq_stats->tso_bytes;
125 s->tx_queue_stopped += sq_stats->stopped;
126 s->tx_queue_wake += sq_stats->wake;
127 s->tx_queue_dropped += sq_stats->dropped;
128 tx_offload_none += sq_stats->csum_offload_none;
129 }
130 }
131
132 /* HW counters */
133 memset(in, 0, sizeof(in));
134
135 MLX5_SET(query_vport_counter_in, in, opcode,
136 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
137 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
138 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
139
140 memset(out, 0, outlen);
141
142 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
143 goto free_out;
144
145 #define MLX5_GET_CTR(p, x) \
146 MLX5_GET64(query_vport_counter_out, p, x)
147
148 s->rx_error_packets =
149 MLX5_GET_CTR(out, received_errors.packets);
150 s->rx_error_bytes =
151 MLX5_GET_CTR(out, received_errors.octets);
152 s->tx_error_packets =
153 MLX5_GET_CTR(out, transmit_errors.packets);
154 s->tx_error_bytes =
155 MLX5_GET_CTR(out, transmit_errors.octets);
156
157 s->rx_unicast_packets =
158 MLX5_GET_CTR(out, received_eth_unicast.packets);
159 s->rx_unicast_bytes =
160 MLX5_GET_CTR(out, received_eth_unicast.octets);
161 s->tx_unicast_packets =
162 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
163 s->tx_unicast_bytes =
164 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
165
166 s->rx_multicast_packets =
167 MLX5_GET_CTR(out, received_eth_multicast.packets);
168 s->rx_multicast_bytes =
169 MLX5_GET_CTR(out, received_eth_multicast.octets);
170 s->tx_multicast_packets =
171 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
172 s->tx_multicast_bytes =
173 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
174
175 s->rx_broadcast_packets =
176 MLX5_GET_CTR(out, received_eth_broadcast.packets);
177 s->rx_broadcast_bytes =
178 MLX5_GET_CTR(out, received_eth_broadcast.octets);
179 s->tx_broadcast_packets =
180 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
181 s->tx_broadcast_bytes =
182 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
183
184 s->rx_packets =
185 s->rx_unicast_packets +
186 s->rx_multicast_packets +
187 s->rx_broadcast_packets;
188 s->rx_bytes =
189 s->rx_unicast_bytes +
190 s->rx_multicast_bytes +
191 s->rx_broadcast_bytes;
192 s->tx_packets =
193 s->tx_unicast_packets +
194 s->tx_multicast_packets +
195 s->tx_broadcast_packets;
196 s->tx_bytes =
197 s->tx_unicast_bytes +
198 s->tx_multicast_bytes +
199 s->tx_broadcast_bytes;
200
201 /* Update calculated offload counters */
202 s->tx_csum_offload = s->tx_packets - tx_offload_none;
203 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
204
205 free_out:
206 kvfree(out);
207 }
208
209 static void mlx5e_update_stats_work(struct work_struct *work)
210 {
211 struct delayed_work *dwork = to_delayed_work(work);
212 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
213 update_stats_work);
214 mutex_lock(&priv->state_lock);
215 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
216 mlx5e_update_stats(priv);
217 schedule_delayed_work(dwork,
218 msecs_to_jiffies(
219 MLX5E_UPDATE_STATS_INTERVAL));
220 }
221 mutex_unlock(&priv->state_lock);
222 }
223
224 static void __mlx5e_async_event(struct mlx5e_priv *priv,
225 enum mlx5_dev_event event)
226 {
227 switch (event) {
228 case MLX5_DEV_EVENT_PORT_UP:
229 case MLX5_DEV_EVENT_PORT_DOWN:
230 schedule_work(&priv->update_carrier_work);
231 break;
232
233 default:
234 break;
235 }
236 }
237
238 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
239 enum mlx5_dev_event event, unsigned long param)
240 {
241 struct mlx5e_priv *priv = vpriv;
242
243 spin_lock(&priv->async_events_spinlock);
244 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
245 __mlx5e_async_event(priv, event);
246 spin_unlock(&priv->async_events_spinlock);
247 }
248
249 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
250 {
251 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
252 }
253
254 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
255 {
256 spin_lock_irq(&priv->async_events_spinlock);
257 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
258 spin_unlock_irq(&priv->async_events_spinlock);
259 }
260
261 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
262 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
263
264 static int mlx5e_create_rq(struct mlx5e_channel *c,
265 struct mlx5e_rq_param *param,
266 struct mlx5e_rq *rq)
267 {
268 struct mlx5e_priv *priv = c->priv;
269 struct mlx5_core_dev *mdev = priv->mdev;
270 void *rqc = param->rqc;
271 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
272 int wq_sz;
273 int err;
274 int i;
275
276 param->wq.db_numa_node = cpu_to_node(c->cpu);
277
278 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
279 &rq->wq_ctrl);
280 if (err)
281 return err;
282
283 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
284
285 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
286 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
287 cpu_to_node(c->cpu));
288 if (!rq->skb) {
289 err = -ENOMEM;
290 goto err_rq_wq_destroy;
291 }
292
293 rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
294 MLX5E_SW2HW_MTU(priv->netdev->mtu);
295 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
296
297 for (i = 0; i < wq_sz; i++) {
298 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
299 u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
300
301 wqe->data.lkey = c->mkey_be;
302 wqe->data.byte_count =
303 cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
304 }
305
306 rq->pdev = c->pdev;
307 rq->netdev = c->netdev;
308 rq->channel = c;
309 rq->ix = c->ix;
310 rq->priv = c->priv;
311
312 return 0;
313
314 err_rq_wq_destroy:
315 mlx5_wq_destroy(&rq->wq_ctrl);
316
317 return err;
318 }
319
320 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
321 {
322 kfree(rq->skb);
323 mlx5_wq_destroy(&rq->wq_ctrl);
324 }
325
326 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
327 {
328 struct mlx5e_priv *priv = rq->priv;
329 struct mlx5_core_dev *mdev = priv->mdev;
330
331 void *in;
332 void *rqc;
333 void *wq;
334 int inlen;
335 int err;
336
337 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
338 sizeof(u64) * rq->wq_ctrl.buf.npages;
339 in = mlx5_vzalloc(inlen);
340 if (!in)
341 return -ENOMEM;
342
343 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
344 wq = MLX5_ADDR_OF(rqc, rqc, wq);
345
346 memcpy(rqc, param->rqc, sizeof(param->rqc));
347
348 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
349 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
350 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
351 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
352 MLX5_ADAPTER_PAGE_SHIFT);
353 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
354
355 mlx5_fill_page_array(&rq->wq_ctrl.buf,
356 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
357
358 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
359
360 kvfree(in);
361
362 return err;
363 }
364
365 static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
366 {
367 struct mlx5e_channel *c = rq->channel;
368 struct mlx5e_priv *priv = c->priv;
369 struct mlx5_core_dev *mdev = priv->mdev;
370
371 void *in;
372 void *rqc;
373 int inlen;
374 int err;
375
376 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
377 in = mlx5_vzalloc(inlen);
378 if (!in)
379 return -ENOMEM;
380
381 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
382
383 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
384 MLX5_SET(rqc, rqc, state, next_state);
385
386 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
387
388 kvfree(in);
389
390 return err;
391 }
392
393 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
394 {
395 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
396 }
397
398 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
399 {
400 struct mlx5e_channel *c = rq->channel;
401 struct mlx5e_priv *priv = c->priv;
402 struct mlx5_wq_ll *wq = &rq->wq;
403 int i;
404
405 for (i = 0; i < 1000; i++) {
406 if (wq->cur_sz >= priv->params.min_rx_wqes)
407 return 0;
408
409 msleep(20);
410 }
411
412 return -ETIMEDOUT;
413 }
414
415 static int mlx5e_open_rq(struct mlx5e_channel *c,
416 struct mlx5e_rq_param *param,
417 struct mlx5e_rq *rq)
418 {
419 int err;
420
421 err = mlx5e_create_rq(c, param, rq);
422 if (err)
423 return err;
424
425 err = mlx5e_enable_rq(rq, param);
426 if (err)
427 goto err_destroy_rq;
428
429 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
430 if (err)
431 goto err_disable_rq;
432
433 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
434 mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */
435
436 return 0;
437
438 err_disable_rq:
439 mlx5e_disable_rq(rq);
440 err_destroy_rq:
441 mlx5e_destroy_rq(rq);
442
443 return err;
444 }
445
446 static void mlx5e_close_rq(struct mlx5e_rq *rq)
447 {
448 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
449 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
450
451 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
452 while (!mlx5_wq_ll_is_empty(&rq->wq))
453 msleep(20);
454
455 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
456 napi_synchronize(&rq->channel->napi);
457
458 mlx5e_disable_rq(rq);
459 mlx5e_destroy_rq(rq);
460 }
461
462 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
463 {
464 kfree(sq->dma_fifo);
465 kfree(sq->skb);
466 }
467
468 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
469 {
470 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
471 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
472
473 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
474 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
475 numa);
476
477 if (!sq->skb || !sq->dma_fifo) {
478 mlx5e_free_sq_db(sq);
479 return -ENOMEM;
480 }
481
482 sq->dma_fifo_mask = df_sz - 1;
483
484 return 0;
485 }
486
487 static int mlx5e_create_sq(struct mlx5e_channel *c,
488 int tc,
489 struct mlx5e_sq_param *param,
490 struct mlx5e_sq *sq)
491 {
492 struct mlx5e_priv *priv = c->priv;
493 struct mlx5_core_dev *mdev = priv->mdev;
494
495 void *sqc = param->sqc;
496 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
497 int txq_ix;
498 int err;
499
500 err = mlx5_alloc_map_uar(mdev, &sq->uar);
501 if (err)
502 return err;
503
504 param->wq.db_numa_node = cpu_to_node(c->cpu);
505
506 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
507 &sq->wq_ctrl);
508 if (err)
509 goto err_unmap_free_uar;
510
511 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
512 sq->uar_map = sq->uar.map;
513 sq->uar_bf_map = sq->uar.bf_map;
514 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
515 sq->max_inline = param->max_inline;
516
517 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
518 if (err)
519 goto err_sq_wq_destroy;
520
521 txq_ix = c->ix + tc * priv->params.num_channels;
522 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
523
524 sq->pdev = c->pdev;
525 sq->mkey_be = c->mkey_be;
526 sq->channel = c;
527 sq->tc = tc;
528 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
529 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
530 priv->txq_to_sq_map[txq_ix] = sq;
531
532 return 0;
533
534 err_sq_wq_destroy:
535 mlx5_wq_destroy(&sq->wq_ctrl);
536
537 err_unmap_free_uar:
538 mlx5_unmap_free_uar(mdev, &sq->uar);
539
540 return err;
541 }
542
543 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
544 {
545 struct mlx5e_channel *c = sq->channel;
546 struct mlx5e_priv *priv = c->priv;
547
548 mlx5e_free_sq_db(sq);
549 mlx5_wq_destroy(&sq->wq_ctrl);
550 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
551 }
552
553 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
554 {
555 struct mlx5e_channel *c = sq->channel;
556 struct mlx5e_priv *priv = c->priv;
557 struct mlx5_core_dev *mdev = priv->mdev;
558
559 void *in;
560 void *sqc;
561 void *wq;
562 int inlen;
563 int err;
564
565 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
566 sizeof(u64) * sq->wq_ctrl.buf.npages;
567 in = mlx5_vzalloc(inlen);
568 if (!in)
569 return -ENOMEM;
570
571 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
572 wq = MLX5_ADDR_OF(sqc, sqc, wq);
573
574 memcpy(sqc, param->sqc, sizeof(param->sqc));
575
576 MLX5_SET(sqc, sqc, tis_num_0, priv->tisn[sq->tc]);
577 MLX5_SET(sqc, sqc, cqn, c->sq[sq->tc].cq.mcq.cqn);
578 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
579 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
580 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
581
582 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
583 MLX5_SET(wq, wq, uar_page, sq->uar.index);
584 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
585 MLX5_ADAPTER_PAGE_SHIFT);
586 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
587
588 mlx5_fill_page_array(&sq->wq_ctrl.buf,
589 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
590
591 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
592
593 kvfree(in);
594
595 return err;
596 }
597
598 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
599 {
600 struct mlx5e_channel *c = sq->channel;
601 struct mlx5e_priv *priv = c->priv;
602 struct mlx5_core_dev *mdev = priv->mdev;
603
604 void *in;
605 void *sqc;
606 int inlen;
607 int err;
608
609 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
610 in = mlx5_vzalloc(inlen);
611 if (!in)
612 return -ENOMEM;
613
614 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
615
616 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
617 MLX5_SET(sqc, sqc, state, next_state);
618
619 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
620
621 kvfree(in);
622
623 return err;
624 }
625
626 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
627 {
628 struct mlx5e_channel *c = sq->channel;
629 struct mlx5e_priv *priv = c->priv;
630 struct mlx5_core_dev *mdev = priv->mdev;
631
632 mlx5_core_destroy_sq(mdev, sq->sqn);
633 }
634
635 static int mlx5e_open_sq(struct mlx5e_channel *c,
636 int tc,
637 struct mlx5e_sq_param *param,
638 struct mlx5e_sq *sq)
639 {
640 int err;
641
642 err = mlx5e_create_sq(c, tc, param, sq);
643 if (err)
644 return err;
645
646 err = mlx5e_enable_sq(sq, param);
647 if (err)
648 goto err_destroy_sq;
649
650 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
651 if (err)
652 goto err_disable_sq;
653
654 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
655 netdev_tx_reset_queue(sq->txq);
656 netif_tx_start_queue(sq->txq);
657
658 return 0;
659
660 err_disable_sq:
661 mlx5e_disable_sq(sq);
662 err_destroy_sq:
663 mlx5e_destroy_sq(sq);
664
665 return err;
666 }
667
668 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
669 {
670 __netif_tx_lock_bh(txq);
671 netif_tx_stop_queue(txq);
672 __netif_tx_unlock_bh(txq);
673 }
674
675 static void mlx5e_close_sq(struct mlx5e_sq *sq)
676 {
677 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
678 napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
679 netif_tx_disable_queue(sq->txq);
680
681 /* ensure hw is notified of all pending wqes */
682 if (mlx5e_sq_has_room_for(sq, 1))
683 mlx5e_send_nop(sq, true);
684
685 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
686 while (sq->cc != sq->pc) /* wait till sq is empty */
687 msleep(20);
688
689 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
690 napi_synchronize(&sq->channel->napi);
691
692 mlx5e_disable_sq(sq);
693 mlx5e_destroy_sq(sq);
694 }
695
696 static int mlx5e_create_cq(struct mlx5e_channel *c,
697 struct mlx5e_cq_param *param,
698 struct mlx5e_cq *cq)
699 {
700 struct mlx5e_priv *priv = c->priv;
701 struct mlx5_core_dev *mdev = priv->mdev;
702 struct mlx5_core_cq *mcq = &cq->mcq;
703 int eqn_not_used;
704 int irqn;
705 int err;
706 u32 i;
707
708 param->wq.buf_numa_node = cpu_to_node(c->cpu);
709 param->wq.db_numa_node = cpu_to_node(c->cpu);
710 param->eq_ix = c->ix;
711
712 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
713 &cq->wq_ctrl);
714 if (err)
715 return err;
716
717 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
718
719 cq->napi = &c->napi;
720
721 mcq->cqe_sz = 64;
722 mcq->set_ci_db = cq->wq_ctrl.db.db;
723 mcq->arm_db = cq->wq_ctrl.db.db + 1;
724 *mcq->set_ci_db = 0;
725 *mcq->arm_db = 0;
726 mcq->vector = param->eq_ix;
727 mcq->comp = mlx5e_completion_event;
728 mcq->event = mlx5e_cq_error_event;
729 mcq->irqn = irqn;
730 mcq->uar = &priv->cq_uar;
731
732 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
733 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
734
735 cqe->op_own = 0xf1;
736 }
737
738 cq->channel = c;
739 cq->priv = priv;
740
741 return 0;
742 }
743
744 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
745 {
746 mlx5_wq_destroy(&cq->wq_ctrl);
747 }
748
749 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
750 {
751 struct mlx5e_priv *priv = cq->priv;
752 struct mlx5_core_dev *mdev = priv->mdev;
753 struct mlx5_core_cq *mcq = &cq->mcq;
754
755 void *in;
756 void *cqc;
757 int inlen;
758 int irqn_not_used;
759 int eqn;
760 int err;
761
762 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
763 sizeof(u64) * cq->wq_ctrl.buf.npages;
764 in = mlx5_vzalloc(inlen);
765 if (!in)
766 return -ENOMEM;
767
768 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
769
770 memcpy(cqc, param->cqc, sizeof(param->cqc));
771
772 mlx5_fill_page_array(&cq->wq_ctrl.buf,
773 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
774
775 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
776
777 MLX5_SET(cqc, cqc, c_eqn, eqn);
778 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
779 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
780 MLX5_ADAPTER_PAGE_SHIFT);
781 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
782
783 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
784
785 kvfree(in);
786
787 if (err)
788 return err;
789
790 mlx5e_cq_arm(cq);
791
792 return 0;
793 }
794
795 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
796 {
797 struct mlx5e_priv *priv = cq->priv;
798 struct mlx5_core_dev *mdev = priv->mdev;
799
800 mlx5_core_destroy_cq(mdev, &cq->mcq);
801 }
802
803 static int mlx5e_open_cq(struct mlx5e_channel *c,
804 struct mlx5e_cq_param *param,
805 struct mlx5e_cq *cq,
806 u16 moderation_usecs,
807 u16 moderation_frames)
808 {
809 int err;
810 struct mlx5e_priv *priv = c->priv;
811 struct mlx5_core_dev *mdev = priv->mdev;
812
813 err = mlx5e_create_cq(c, param, cq);
814 if (err)
815 return err;
816
817 err = mlx5e_enable_cq(cq, param);
818 if (err)
819 goto err_destroy_cq;
820
821 err = mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
822 moderation_usecs,
823 moderation_frames);
824 if (err)
825 goto err_destroy_cq;
826
827 return 0;
828
829 err_destroy_cq:
830 mlx5e_destroy_cq(cq);
831
832 return err;
833 }
834
835 static void mlx5e_close_cq(struct mlx5e_cq *cq)
836 {
837 mlx5e_disable_cq(cq);
838 mlx5e_destroy_cq(cq);
839 }
840
841 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
842 {
843 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
844 }
845
846 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
847 struct mlx5e_channel_param *cparam)
848 {
849 struct mlx5e_priv *priv = c->priv;
850 int err;
851 int tc;
852
853 for (tc = 0; tc < c->num_tc; tc++) {
854 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
855 priv->params.tx_cq_moderation_usec,
856 priv->params.tx_cq_moderation_pkts);
857 if (err)
858 goto err_close_tx_cqs;
859 }
860
861 return 0;
862
863 err_close_tx_cqs:
864 for (tc--; tc >= 0; tc--)
865 mlx5e_close_cq(&c->sq[tc].cq);
866
867 return err;
868 }
869
870 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
871 {
872 int tc;
873
874 for (tc = 0; tc < c->num_tc; tc++)
875 mlx5e_close_cq(&c->sq[tc].cq);
876 }
877
878 static int mlx5e_open_sqs(struct mlx5e_channel *c,
879 struct mlx5e_channel_param *cparam)
880 {
881 int err;
882 int tc;
883
884 for (tc = 0; tc < c->num_tc; tc++) {
885 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
886 if (err)
887 goto err_close_sqs;
888 }
889
890 return 0;
891
892 err_close_sqs:
893 for (tc--; tc >= 0; tc--)
894 mlx5e_close_sq(&c->sq[tc]);
895
896 return err;
897 }
898
899 static void mlx5e_close_sqs(struct mlx5e_channel *c)
900 {
901 int tc;
902
903 for (tc = 0; tc < c->num_tc; tc++)
904 mlx5e_close_sq(&c->sq[tc]);
905 }
906
907 static void mlx5e_build_tc_to_txq_map(struct mlx5e_channel *c,
908 int num_channels)
909 {
910 int i;
911
912 for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
913 c->tc_to_txq_map[i] = c->ix + i * num_channels;
914 }
915
916 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
917 struct mlx5e_channel_param *cparam,
918 struct mlx5e_channel **cp)
919 {
920 struct net_device *netdev = priv->netdev;
921 int cpu = mlx5e_get_cpu(priv, ix);
922 struct mlx5e_channel *c;
923 int err;
924
925 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
926 if (!c)
927 return -ENOMEM;
928
929 c->priv = priv;
930 c->ix = ix;
931 c->cpu = cpu;
932 c->pdev = &priv->mdev->pdev->dev;
933 c->netdev = priv->netdev;
934 c->mkey_be = cpu_to_be32(priv->mr.key);
935 c->num_tc = priv->params.num_tc;
936
937 mlx5e_build_tc_to_txq_map(c, priv->params.num_channels);
938
939 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
940
941 err = mlx5e_open_tx_cqs(c, cparam);
942 if (err)
943 goto err_napi_del;
944
945 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
946 priv->params.rx_cq_moderation_usec,
947 priv->params.rx_cq_moderation_pkts);
948 if (err)
949 goto err_close_tx_cqs;
950
951 napi_enable(&c->napi);
952
953 err = mlx5e_open_sqs(c, cparam);
954 if (err)
955 goto err_disable_napi;
956
957 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
958 if (err)
959 goto err_close_sqs;
960
961 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
962 *cp = c;
963
964 return 0;
965
966 err_close_sqs:
967 mlx5e_close_sqs(c);
968
969 err_disable_napi:
970 napi_disable(&c->napi);
971 mlx5e_close_cq(&c->rq.cq);
972
973 err_close_tx_cqs:
974 mlx5e_close_tx_cqs(c);
975
976 err_napi_del:
977 netif_napi_del(&c->napi);
978 kfree(c);
979
980 return err;
981 }
982
983 static void mlx5e_close_channel(struct mlx5e_channel *c)
984 {
985 mlx5e_close_rq(&c->rq);
986 mlx5e_close_sqs(c);
987 napi_disable(&c->napi);
988 mlx5e_close_cq(&c->rq.cq);
989 mlx5e_close_tx_cqs(c);
990 netif_napi_del(&c->napi);
991 kfree(c);
992 }
993
994 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
995 struct mlx5e_rq_param *param)
996 {
997 void *rqc = param->rqc;
998 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
999
1000 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1001 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1002 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1003 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1004 MLX5_SET(wq, wq, pd, priv->pdn);
1005
1006 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1007 param->wq.linear = 1;
1008 }
1009
1010 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1011 struct mlx5e_sq_param *param)
1012 {
1013 void *sqc = param->sqc;
1014 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1015
1016 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1017 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1018 MLX5_SET(wq, wq, pd, priv->pdn);
1019
1020 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1021 param->max_inline = priv->params.tx_max_inline;
1022 }
1023
1024 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1025 struct mlx5e_cq_param *param)
1026 {
1027 void *cqc = param->cqc;
1028
1029 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1030 }
1031
1032 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1033 struct mlx5e_cq_param *param)
1034 {
1035 void *cqc = param->cqc;
1036
1037 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1038
1039 mlx5e_build_common_cq_param(priv, param);
1040 }
1041
1042 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1043 struct mlx5e_cq_param *param)
1044 {
1045 void *cqc = param->cqc;
1046
1047 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1048
1049 mlx5e_build_common_cq_param(priv, param);
1050 }
1051
1052 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1053 struct mlx5e_channel_param *cparam)
1054 {
1055 memset(cparam, 0, sizeof(*cparam));
1056
1057 mlx5e_build_rq_param(priv, &cparam->rq);
1058 mlx5e_build_sq_param(priv, &cparam->sq);
1059 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1060 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1061 }
1062
1063 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1064 {
1065 struct mlx5e_channel_param cparam;
1066 int nch = priv->params.num_channels;
1067 int err = -ENOMEM;
1068 int i;
1069 int j;
1070
1071 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1072 GFP_KERNEL);
1073
1074 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1075 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1076
1077 if (!priv->channel || !priv->txq_to_sq_map)
1078 goto err_free_txq_to_sq_map;
1079
1080 mlx5e_build_channel_param(priv, &cparam);
1081 for (i = 0; i < nch; i++) {
1082 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1083 if (err)
1084 goto err_close_channels;
1085 }
1086
1087 for (j = 0; j < nch; j++) {
1088 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1089 if (err)
1090 goto err_close_channels;
1091 }
1092
1093 return 0;
1094
1095 err_close_channels:
1096 for (i--; i >= 0; i--)
1097 mlx5e_close_channel(priv->channel[i]);
1098
1099 err_free_txq_to_sq_map:
1100 kfree(priv->txq_to_sq_map);
1101 kfree(priv->channel);
1102
1103 return err;
1104 }
1105
1106 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1107 {
1108 int i;
1109
1110 for (i = 0; i < priv->params.num_channels; i++)
1111 mlx5e_close_channel(priv->channel[i]);
1112
1113 kfree(priv->txq_to_sq_map);
1114 kfree(priv->channel);
1115 }
1116
1117 static int mlx5e_rx_hash_fn(int hfunc)
1118 {
1119 return (hfunc == ETH_RSS_HASH_TOP) ?
1120 MLX5_RX_HASH_FN_TOEPLITZ :
1121 MLX5_RX_HASH_FN_INVERTED_XOR8;
1122 }
1123
1124 static int mlx5e_bits_invert(unsigned long a, int size)
1125 {
1126 int inv = 0;
1127 int i;
1128
1129 for (i = 0; i < size; i++)
1130 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1131
1132 return inv;
1133 }
1134
1135 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1136 enum mlx5e_rqt_ix rqt_ix)
1137 {
1138 int i;
1139 int log_sz;
1140
1141 switch (rqt_ix) {
1142 case MLX5E_INDIRECTION_RQT:
1143 log_sz = priv->params.rx_hash_log_tbl_sz;
1144 for (i = 0; i < (1 << log_sz); i++) {
1145 int ix = i;
1146
1147 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1148 ix = mlx5e_bits_invert(i, log_sz);
1149
1150 ix = ix % priv->params.num_channels;
1151 MLX5_SET(rqtc, rqtc, rq_num[i],
1152 test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1153 priv->channel[ix]->rq.rqn :
1154 priv->drop_rq.rqn);
1155 }
1156
1157 break;
1158
1159 default: /* MLX5E_SINGLE_RQ_RQT */
1160 MLX5_SET(rqtc, rqtc, rq_num[0],
1161 test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1162 priv->channel[0]->rq.rqn :
1163 priv->drop_rq.rqn);
1164
1165 break;
1166 }
1167 }
1168
1169 static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1170 {
1171 struct mlx5_core_dev *mdev = priv->mdev;
1172 u32 *in;
1173 void *rqtc;
1174 int inlen;
1175 int log_sz;
1176 int sz;
1177 int err;
1178
1179 log_sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 0 :
1180 priv->params.rx_hash_log_tbl_sz;
1181 sz = 1 << log_sz;
1182
1183 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1184 in = mlx5_vzalloc(inlen);
1185 if (!in)
1186 return -ENOMEM;
1187
1188 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1189
1190 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1191 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1192
1193 mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1194
1195 err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
1196
1197 kvfree(in);
1198
1199 return err;
1200 }
1201
1202 static int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1203 {
1204 struct mlx5_core_dev *mdev = priv->mdev;
1205 u32 *in;
1206 void *rqtc;
1207 int inlen;
1208 int log_sz;
1209 int sz;
1210 int err;
1211
1212 log_sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 0 :
1213 priv->params.rx_hash_log_tbl_sz;
1214 sz = 1 << log_sz;
1215
1216 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1217 in = mlx5_vzalloc(inlen);
1218 if (!in)
1219 return -ENOMEM;
1220
1221 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1222
1223 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1224
1225 mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1226
1227 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1228
1229 err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen);
1230
1231 kvfree(in);
1232
1233 return err;
1234 }
1235
1236 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1237 {
1238 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
1239 }
1240
1241 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1242 {
1243 mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
1244 mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1245 }
1246
1247 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1248 {
1249 if (!priv->params.lro_en)
1250 return;
1251
1252 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1253
1254 MLX5_SET(tirc, tirc, lro_enable_mask,
1255 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1256 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1257 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1258 (priv->params.lro_wqe_sz -
1259 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1260 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1261 MLX5_CAP_ETH(priv->mdev,
1262 lro_timer_supported_periods[3]));
1263 }
1264
1265 static int mlx5e_modify_tir_lro(struct mlx5e_priv *priv, int tt)
1266 {
1267 struct mlx5_core_dev *mdev = priv->mdev;
1268
1269 void *in;
1270 void *tirc;
1271 int inlen;
1272 int err;
1273
1274 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1275 in = mlx5_vzalloc(inlen);
1276 if (!in)
1277 return -ENOMEM;
1278
1279 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1280 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1281
1282 mlx5e_build_tir_ctx_lro(tirc, priv);
1283
1284 err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen);
1285
1286 kvfree(in);
1287
1288 return err;
1289 }
1290
1291 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1292 {
1293 struct mlx5e_priv *priv = netdev_priv(netdev);
1294 struct mlx5_core_dev *mdev = priv->mdev;
1295 int hw_mtu;
1296 int err;
1297
1298 err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1299 if (err)
1300 return err;
1301
1302 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1303
1304 if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1305 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1306 __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1307
1308 netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1309 return 0;
1310 }
1311
1312 int mlx5e_open_locked(struct net_device *netdev)
1313 {
1314 struct mlx5e_priv *priv = netdev_priv(netdev);
1315 int num_txqs;
1316 int err;
1317
1318 set_bit(MLX5E_STATE_OPENED, &priv->state);
1319
1320 num_txqs = priv->params.num_channels * priv->params.num_tc;
1321 netif_set_real_num_tx_queues(netdev, num_txqs);
1322 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1323
1324 err = mlx5e_set_dev_port_mtu(netdev);
1325 if (err)
1326 return err;
1327
1328 err = mlx5e_open_channels(priv);
1329 if (err) {
1330 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1331 __func__, err);
1332 return err;
1333 }
1334
1335 mlx5e_update_carrier(priv);
1336 mlx5e_redirect_rqts(priv);
1337
1338 schedule_delayed_work(&priv->update_stats_work, 0);
1339
1340 return 0;
1341 }
1342
1343 static int mlx5e_open(struct net_device *netdev)
1344 {
1345 struct mlx5e_priv *priv = netdev_priv(netdev);
1346 int err;
1347
1348 mutex_lock(&priv->state_lock);
1349 err = mlx5e_open_locked(netdev);
1350 mutex_unlock(&priv->state_lock);
1351
1352 return err;
1353 }
1354
1355 int mlx5e_close_locked(struct net_device *netdev)
1356 {
1357 struct mlx5e_priv *priv = netdev_priv(netdev);
1358
1359 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1360
1361 mlx5e_redirect_rqts(priv);
1362 netif_carrier_off(priv->netdev);
1363 mlx5e_close_channels(priv);
1364
1365 return 0;
1366 }
1367
1368 static int mlx5e_close(struct net_device *netdev)
1369 {
1370 struct mlx5e_priv *priv = netdev_priv(netdev);
1371 int err;
1372
1373 mutex_lock(&priv->state_lock);
1374 err = mlx5e_close_locked(netdev);
1375 mutex_unlock(&priv->state_lock);
1376
1377 return err;
1378 }
1379
1380 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1381 struct mlx5e_rq *rq,
1382 struct mlx5e_rq_param *param)
1383 {
1384 struct mlx5_core_dev *mdev = priv->mdev;
1385 void *rqc = param->rqc;
1386 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1387 int err;
1388
1389 param->wq.db_numa_node = param->wq.buf_numa_node;
1390
1391 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1392 &rq->wq_ctrl);
1393 if (err)
1394 return err;
1395
1396 rq->priv = priv;
1397
1398 return 0;
1399 }
1400
1401 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1402 struct mlx5e_cq *cq,
1403 struct mlx5e_cq_param *param)
1404 {
1405 struct mlx5_core_dev *mdev = priv->mdev;
1406 struct mlx5_core_cq *mcq = &cq->mcq;
1407 int eqn_not_used;
1408 int irqn;
1409 int err;
1410
1411 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1412 &cq->wq_ctrl);
1413 if (err)
1414 return err;
1415
1416 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1417
1418 mcq->cqe_sz = 64;
1419 mcq->set_ci_db = cq->wq_ctrl.db.db;
1420 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1421 *mcq->set_ci_db = 0;
1422 *mcq->arm_db = 0;
1423 mcq->vector = param->eq_ix;
1424 mcq->comp = mlx5e_completion_event;
1425 mcq->event = mlx5e_cq_error_event;
1426 mcq->irqn = irqn;
1427 mcq->uar = &priv->cq_uar;
1428
1429 cq->priv = priv;
1430
1431 return 0;
1432 }
1433
1434 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1435 {
1436 struct mlx5e_cq_param cq_param;
1437 struct mlx5e_rq_param rq_param;
1438 struct mlx5e_rq *rq = &priv->drop_rq;
1439 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1440 int err;
1441
1442 memset(&cq_param, 0, sizeof(cq_param));
1443 memset(&rq_param, 0, sizeof(rq_param));
1444 mlx5e_build_rx_cq_param(priv, &cq_param);
1445 mlx5e_build_rq_param(priv, &rq_param);
1446
1447 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1448 if (err)
1449 return err;
1450
1451 err = mlx5e_enable_cq(cq, &cq_param);
1452 if (err)
1453 goto err_destroy_cq;
1454
1455 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1456 if (err)
1457 goto err_disable_cq;
1458
1459 err = mlx5e_enable_rq(rq, &rq_param);
1460 if (err)
1461 goto err_destroy_rq;
1462
1463 return 0;
1464
1465 err_destroy_rq:
1466 mlx5e_destroy_rq(&priv->drop_rq);
1467
1468 err_disable_cq:
1469 mlx5e_disable_cq(&priv->drop_rq.cq);
1470
1471 err_destroy_cq:
1472 mlx5e_destroy_cq(&priv->drop_rq.cq);
1473
1474 return err;
1475 }
1476
1477 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1478 {
1479 mlx5e_disable_rq(&priv->drop_rq);
1480 mlx5e_destroy_rq(&priv->drop_rq);
1481 mlx5e_disable_cq(&priv->drop_rq.cq);
1482 mlx5e_destroy_cq(&priv->drop_rq.cq);
1483 }
1484
1485 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1486 {
1487 struct mlx5_core_dev *mdev = priv->mdev;
1488 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1489 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1490
1491 memset(in, 0, sizeof(in));
1492
1493 MLX5_SET(tisc, tisc, prio, tc);
1494 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1495
1496 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1497 }
1498
1499 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1500 {
1501 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1502 }
1503
1504 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1505 {
1506 int err;
1507 int tc;
1508
1509 for (tc = 0; tc < priv->params.num_tc; tc++) {
1510 err = mlx5e_create_tis(priv, tc);
1511 if (err)
1512 goto err_close_tises;
1513 }
1514
1515 return 0;
1516
1517 err_close_tises:
1518 for (tc--; tc >= 0; tc--)
1519 mlx5e_destroy_tis(priv, tc);
1520
1521 return err;
1522 }
1523
1524 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1525 {
1526 int tc;
1527
1528 for (tc = 0; tc < priv->params.num_tc; tc++)
1529 mlx5e_destroy_tis(priv, tc);
1530 }
1531
1532 static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1533 {
1534 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1535
1536 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1537
1538 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1539 MLX5_HASH_FIELD_SEL_DST_IP)
1540
1541 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
1542 MLX5_HASH_FIELD_SEL_DST_IP |\
1543 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1544 MLX5_HASH_FIELD_SEL_L4_DPORT)
1545
1546 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1547 MLX5_HASH_FIELD_SEL_DST_IP |\
1548 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1549
1550 mlx5e_build_tir_ctx_lro(tirc, priv);
1551
1552 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1553
1554 switch (tt) {
1555 case MLX5E_TT_ANY:
1556 MLX5_SET(tirc, tirc, indirect_table,
1557 priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1558 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
1559 break;
1560 default:
1561 MLX5_SET(tirc, tirc, indirect_table,
1562 priv->rqtn[MLX5E_INDIRECTION_RQT]);
1563 MLX5_SET(tirc, tirc, rx_hash_fn,
1564 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1565 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1566 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1567 rx_hash_toeplitz_key);
1568 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1569 rx_hash_toeplitz_key);
1570
1571 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1572 netdev_rss_key_fill(rss_key, len);
1573 }
1574 break;
1575 }
1576
1577 switch (tt) {
1578 case MLX5E_TT_IPV4_TCP:
1579 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1580 MLX5_L3_PROT_TYPE_IPV4);
1581 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1582 MLX5_L4_PROT_TYPE_TCP);
1583 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1584 MLX5_HASH_IP_L4PORTS);
1585 break;
1586
1587 case MLX5E_TT_IPV6_TCP:
1588 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1589 MLX5_L3_PROT_TYPE_IPV6);
1590 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1591 MLX5_L4_PROT_TYPE_TCP);
1592 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1593 MLX5_HASH_IP_L4PORTS);
1594 break;
1595
1596 case MLX5E_TT_IPV4_UDP:
1597 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1598 MLX5_L3_PROT_TYPE_IPV4);
1599 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1600 MLX5_L4_PROT_TYPE_UDP);
1601 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1602 MLX5_HASH_IP_L4PORTS);
1603 break;
1604
1605 case MLX5E_TT_IPV6_UDP:
1606 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1607 MLX5_L3_PROT_TYPE_IPV6);
1608 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1609 MLX5_L4_PROT_TYPE_UDP);
1610 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1611 MLX5_HASH_IP_L4PORTS);
1612 break;
1613
1614 case MLX5E_TT_IPV4_IPSEC_AH:
1615 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1616 MLX5_L3_PROT_TYPE_IPV4);
1617 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1618 MLX5_HASH_IP_IPSEC_SPI);
1619 break;
1620
1621 case MLX5E_TT_IPV6_IPSEC_AH:
1622 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1623 MLX5_L3_PROT_TYPE_IPV6);
1624 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1625 MLX5_HASH_IP_IPSEC_SPI);
1626 break;
1627
1628 case MLX5E_TT_IPV4_IPSEC_ESP:
1629 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1630 MLX5_L3_PROT_TYPE_IPV4);
1631 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1632 MLX5_HASH_IP_IPSEC_SPI);
1633 break;
1634
1635 case MLX5E_TT_IPV6_IPSEC_ESP:
1636 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1637 MLX5_L3_PROT_TYPE_IPV6);
1638 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1639 MLX5_HASH_IP_IPSEC_SPI);
1640 break;
1641
1642 case MLX5E_TT_IPV4:
1643 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1644 MLX5_L3_PROT_TYPE_IPV4);
1645 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1646 MLX5_HASH_IP);
1647 break;
1648
1649 case MLX5E_TT_IPV6:
1650 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1651 MLX5_L3_PROT_TYPE_IPV6);
1652 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1653 MLX5_HASH_IP);
1654 break;
1655 }
1656 }
1657
1658 static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt)
1659 {
1660 struct mlx5_core_dev *mdev = priv->mdev;
1661 u32 *in;
1662 void *tirc;
1663 int inlen;
1664 int err;
1665
1666 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1667 in = mlx5_vzalloc(inlen);
1668 if (!in)
1669 return -ENOMEM;
1670
1671 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1672
1673 mlx5e_build_tir_ctx(priv, tirc, tt);
1674
1675 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
1676
1677 kvfree(in);
1678
1679 return err;
1680 }
1681
1682 static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt)
1683 {
1684 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
1685 }
1686
1687 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
1688 {
1689 int err;
1690 int i;
1691
1692 for (i = 0; i < MLX5E_NUM_TT; i++) {
1693 err = mlx5e_create_tir(priv, i);
1694 if (err)
1695 goto err_destroy_tirs;
1696 }
1697
1698 return 0;
1699
1700 err_destroy_tirs:
1701 for (i--; i >= 0; i--)
1702 mlx5e_destroy_tir(priv, i);
1703
1704 return err;
1705 }
1706
1707 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
1708 {
1709 int i;
1710
1711 for (i = 0; i < MLX5E_NUM_TT; i++)
1712 mlx5e_destroy_tir(priv, i);
1713 }
1714
1715 static struct rtnl_link_stats64 *
1716 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1717 {
1718 struct mlx5e_priv *priv = netdev_priv(dev);
1719 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1720
1721 stats->rx_packets = vstats->rx_packets;
1722 stats->rx_bytes = vstats->rx_bytes;
1723 stats->tx_packets = vstats->tx_packets;
1724 stats->tx_bytes = vstats->tx_bytes;
1725 stats->multicast = vstats->rx_multicast_packets +
1726 vstats->tx_multicast_packets;
1727 stats->tx_errors = vstats->tx_error_packets;
1728 stats->rx_errors = vstats->rx_error_packets;
1729 stats->tx_dropped = vstats->tx_queue_dropped;
1730 stats->rx_crc_errors = 0;
1731 stats->rx_length_errors = 0;
1732
1733 return stats;
1734 }
1735
1736 static void mlx5e_set_rx_mode(struct net_device *dev)
1737 {
1738 struct mlx5e_priv *priv = netdev_priv(dev);
1739
1740 schedule_work(&priv->set_rx_mode_work);
1741 }
1742
1743 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
1744 {
1745 struct mlx5e_priv *priv = netdev_priv(netdev);
1746 struct sockaddr *saddr = addr;
1747
1748 if (!is_valid_ether_addr(saddr->sa_data))
1749 return -EADDRNOTAVAIL;
1750
1751 netif_addr_lock_bh(netdev);
1752 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1753 netif_addr_unlock_bh(netdev);
1754
1755 schedule_work(&priv->set_rx_mode_work);
1756
1757 return 0;
1758 }
1759
1760 static int mlx5e_set_features(struct net_device *netdev,
1761 netdev_features_t features)
1762 {
1763 struct mlx5e_priv *priv = netdev_priv(netdev);
1764 int err = 0;
1765 netdev_features_t changes = features ^ netdev->features;
1766
1767 mutex_lock(&priv->state_lock);
1768
1769 if (changes & NETIF_F_LRO) {
1770 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1771
1772 if (was_opened)
1773 mlx5e_close_locked(priv->netdev);
1774
1775 priv->params.lro_en = !!(features & NETIF_F_LRO);
1776 mlx5e_modify_tir_lro(priv, MLX5E_TT_IPV4_TCP);
1777 mlx5e_modify_tir_lro(priv, MLX5E_TT_IPV6_TCP);
1778
1779 if (was_opened)
1780 err = mlx5e_open_locked(priv->netdev);
1781 }
1782
1783 mutex_unlock(&priv->state_lock);
1784
1785 if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
1786 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1787 mlx5e_enable_vlan_filter(priv);
1788 else
1789 mlx5e_disable_vlan_filter(priv);
1790 }
1791
1792 return 0;
1793 }
1794
1795 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
1796 {
1797 struct mlx5e_priv *priv = netdev_priv(netdev);
1798 struct mlx5_core_dev *mdev = priv->mdev;
1799 bool was_opened;
1800 int max_mtu;
1801 int err = 0;
1802
1803 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
1804
1805 if (new_mtu > max_mtu) {
1806 netdev_err(netdev,
1807 "%s: Bad MTU (%d) > (%d) Max\n",
1808 __func__, new_mtu, max_mtu);
1809 return -EINVAL;
1810 }
1811
1812 mutex_lock(&priv->state_lock);
1813
1814 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1815 if (was_opened)
1816 mlx5e_close_locked(netdev);
1817
1818 netdev->mtu = new_mtu;
1819
1820 if (was_opened)
1821 err = mlx5e_open_locked(netdev);
1822
1823 mutex_unlock(&priv->state_lock);
1824
1825 return err;
1826 }
1827
1828 static struct net_device_ops mlx5e_netdev_ops = {
1829 .ndo_open = mlx5e_open,
1830 .ndo_stop = mlx5e_close,
1831 .ndo_start_xmit = mlx5e_xmit,
1832 .ndo_get_stats64 = mlx5e_get_stats,
1833 .ndo_set_rx_mode = mlx5e_set_rx_mode,
1834 .ndo_set_mac_address = mlx5e_set_mac,
1835 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
1836 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
1837 .ndo_set_features = mlx5e_set_features,
1838 .ndo_change_mtu = mlx5e_change_mtu,
1839 };
1840
1841 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
1842 {
1843 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1844 return -ENOTSUPP;
1845 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
1846 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
1847 !MLX5_CAP_ETH(mdev, csum_cap) ||
1848 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
1849 !MLX5_CAP_ETH(mdev, vlan_cap) ||
1850 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
1851 MLX5_CAP_FLOWTABLE(mdev,
1852 flow_table_properties_nic_receive.max_ft_level)
1853 < 3) {
1854 mlx5_core_warn(mdev,
1855 "Not creating net device, some required device capabilities are missing\n");
1856 return -ENOTSUPP;
1857 }
1858 return 0;
1859 }
1860
1861 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
1862 {
1863 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1864
1865 return bf_buf_size -
1866 sizeof(struct mlx5e_tx_wqe) +
1867 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
1868 }
1869
1870 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
1871 struct net_device *netdev,
1872 int num_comp_vectors)
1873 {
1874 struct mlx5e_priv *priv = netdev_priv(netdev);
1875
1876 priv->params.log_sq_size =
1877 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
1878 priv->params.log_rq_size =
1879 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
1880 priv->params.rx_cq_moderation_usec =
1881 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
1882 priv->params.rx_cq_moderation_pkts =
1883 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
1884 priv->params.tx_cq_moderation_usec =
1885 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
1886 priv->params.tx_cq_moderation_pkts =
1887 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
1888 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
1889 priv->params.min_rx_wqes =
1890 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
1891 priv->params.rx_hash_log_tbl_sz =
1892 (order_base_2(num_comp_vectors) >
1893 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
1894 order_base_2(num_comp_vectors) :
1895 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
1896 priv->params.num_tc = 1;
1897 priv->params.default_vlan_prio = 0;
1898 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
1899
1900 priv->params.lro_en = false && !!MLX5_CAP_ETH(priv->mdev, lro_cap);
1901 priv->params.lro_wqe_sz =
1902 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
1903
1904 priv->mdev = mdev;
1905 priv->netdev = netdev;
1906 priv->params.num_channels = num_comp_vectors;
1907 priv->default_vlan_prio = priv->params.default_vlan_prio;
1908
1909 spin_lock_init(&priv->async_events_spinlock);
1910 mutex_init(&priv->state_lock);
1911
1912 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
1913 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
1914 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
1915 }
1916
1917 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
1918 {
1919 struct mlx5e_priv *priv = netdev_priv(netdev);
1920
1921 mlx5_query_nic_vport_mac_address(priv->mdev, netdev->dev_addr);
1922 }
1923
1924 static void mlx5e_build_netdev(struct net_device *netdev)
1925 {
1926 struct mlx5e_priv *priv = netdev_priv(netdev);
1927 struct mlx5_core_dev *mdev = priv->mdev;
1928
1929 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
1930
1931 if (priv->params.num_tc > 1)
1932 mlx5e_netdev_ops.ndo_select_queue = mlx5e_select_queue;
1933
1934 netdev->netdev_ops = &mlx5e_netdev_ops;
1935 netdev->watchdog_timeo = 15 * HZ;
1936
1937 netdev->ethtool_ops = &mlx5e_ethtool_ops;
1938
1939 netdev->vlan_features |= NETIF_F_SG;
1940 netdev->vlan_features |= NETIF_F_IP_CSUM;
1941 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
1942 netdev->vlan_features |= NETIF_F_GRO;
1943 netdev->vlan_features |= NETIF_F_TSO;
1944 netdev->vlan_features |= NETIF_F_TSO6;
1945 netdev->vlan_features |= NETIF_F_RXCSUM;
1946 netdev->vlan_features |= NETIF_F_RXHASH;
1947
1948 if (!!MLX5_CAP_ETH(mdev, lro_cap))
1949 netdev->vlan_features |= NETIF_F_LRO;
1950
1951 netdev->hw_features = netdev->vlan_features;
1952 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1953 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1954
1955 netdev->features = netdev->hw_features;
1956 if (!priv->params.lro_en)
1957 netdev->features &= ~NETIF_F_LRO;
1958
1959 netdev->features |= NETIF_F_HIGHDMA;
1960
1961 netdev->priv_flags |= IFF_UNICAST_FLT;
1962
1963 mlx5e_set_netdev_dev_addr(netdev);
1964 }
1965
1966 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
1967 struct mlx5_core_mr *mr)
1968 {
1969 struct mlx5_core_dev *mdev = priv->mdev;
1970 struct mlx5_create_mkey_mbox_in *in;
1971 int err;
1972
1973 in = mlx5_vzalloc(sizeof(*in));
1974 if (!in)
1975 return -ENOMEM;
1976
1977 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
1978 MLX5_PERM_LOCAL_READ |
1979 MLX5_ACCESS_MODE_PA;
1980 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
1981 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
1982
1983 err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
1984 NULL);
1985
1986 kvfree(in);
1987
1988 return err;
1989 }
1990
1991 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
1992 {
1993 struct net_device *netdev;
1994 struct mlx5e_priv *priv;
1995 int ncv = mdev->priv.eq_table.num_comp_vectors;
1996 int err;
1997
1998 if (mlx5e_check_required_hca_cap(mdev))
1999 return NULL;
2000
2001 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), ncv, ncv);
2002 if (!netdev) {
2003 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2004 return NULL;
2005 }
2006
2007 mlx5e_build_netdev_priv(mdev, netdev, ncv);
2008 mlx5e_build_netdev(netdev);
2009
2010 netif_carrier_off(netdev);
2011
2012 priv = netdev_priv(netdev);
2013
2014 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
2015 if (err) {
2016 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
2017 goto err_free_netdev;
2018 }
2019
2020 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2021 if (err) {
2022 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
2023 goto err_unmap_free_uar;
2024 }
2025
2026 err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
2027 if (err) {
2028 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
2029 goto err_dealloc_pd;
2030 }
2031
2032 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
2033 if (err) {
2034 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
2035 goto err_dealloc_transport_domain;
2036 }
2037
2038 err = mlx5e_create_tises(priv);
2039 if (err) {
2040 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
2041 goto err_destroy_mkey;
2042 }
2043
2044 err = mlx5e_open_drop_rq(priv);
2045 if (err) {
2046 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
2047 goto err_destroy_tises;
2048 }
2049
2050 err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT);
2051 if (err) {
2052 mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err);
2053 goto err_close_drop_rq;
2054 }
2055
2056 err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2057 if (err) {
2058 mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err);
2059 goto err_destroy_rqt_indir;
2060 }
2061
2062 err = mlx5e_create_tirs(priv);
2063 if (err) {
2064 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
2065 goto err_destroy_rqt_single;
2066 }
2067
2068 err = mlx5e_create_flow_tables(priv);
2069 if (err) {
2070 mlx5_core_warn(mdev, "create flow tables failed, %d\n", err);
2071 goto err_destroy_tirs;
2072 }
2073
2074 mlx5e_init_eth_addr(priv);
2075
2076 err = register_netdev(netdev);
2077 if (err) {
2078 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
2079 goto err_destroy_flow_tables;
2080 }
2081
2082 mlx5e_enable_async_events(priv);
2083 schedule_work(&priv->set_rx_mode_work);
2084
2085 return priv;
2086
2087 err_destroy_flow_tables:
2088 mlx5e_destroy_flow_tables(priv);
2089
2090 err_destroy_tirs:
2091 mlx5e_destroy_tirs(priv);
2092
2093 err_destroy_rqt_single:
2094 mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2095
2096 err_destroy_rqt_indir:
2097 mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2098
2099 err_close_drop_rq:
2100 mlx5e_close_drop_rq(priv);
2101
2102 err_destroy_tises:
2103 mlx5e_destroy_tises(priv);
2104
2105 err_destroy_mkey:
2106 mlx5_core_destroy_mkey(mdev, &priv->mr);
2107
2108 err_dealloc_transport_domain:
2109 mlx5_dealloc_transport_domain(mdev, priv->tdn);
2110
2111 err_dealloc_pd:
2112 mlx5_core_dealloc_pd(mdev, priv->pdn);
2113
2114 err_unmap_free_uar:
2115 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2116
2117 err_free_netdev:
2118 free_netdev(netdev);
2119
2120 return NULL;
2121 }
2122
2123 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2124 {
2125 struct mlx5e_priv *priv = vpriv;
2126 struct net_device *netdev = priv->netdev;
2127
2128 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
2129
2130 schedule_work(&priv->set_rx_mode_work);
2131 mlx5e_disable_async_events(priv);
2132 flush_scheduled_work();
2133 unregister_netdev(netdev);
2134 mlx5e_destroy_flow_tables(priv);
2135 mlx5e_destroy_tirs(priv);
2136 mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2137 mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2138 mlx5e_close_drop_rq(priv);
2139 mlx5e_destroy_tises(priv);
2140 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
2141 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
2142 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2143 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
2144 free_netdev(netdev);
2145 }
2146
2147 static void *mlx5e_get_netdev(void *vpriv)
2148 {
2149 struct mlx5e_priv *priv = vpriv;
2150
2151 return priv->netdev;
2152 }
2153
2154 static struct mlx5_interface mlx5e_interface = {
2155 .add = mlx5e_create_netdev,
2156 .remove = mlx5e_destroy_netdev,
2157 .event = mlx5e_async_event,
2158 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
2159 .get_dev = mlx5e_get_netdev,
2160 };
2161
2162 void mlx5e_init(void)
2163 {
2164 mlx5_register_interface(&mlx5e_interface);
2165 }
2166
2167 void mlx5e_cleanup(void)
2168 {
2169 mlx5_unregister_interface(&mlx5e_interface);
2170 }
Linux kernel - Deliverables
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