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Merge tag 'pm+acpi-4.6-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael...
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include "en.h"
38 #include "en_tc.h"
39 #include "eswitch.h"
40 #include "vxlan.h"
41
42 struct mlx5e_rq_param {
43 u32 rqc[MLX5_ST_SZ_DW(rqc)];
44 struct mlx5_wq_param wq;
45 };
46
47 struct mlx5e_sq_param {
48 u32 sqc[MLX5_ST_SZ_DW(sqc)];
49 struct mlx5_wq_param wq;
50 u16 max_inline;
51 };
52
53 struct mlx5e_cq_param {
54 u32 cqc[MLX5_ST_SZ_DW(cqc)];
55 struct mlx5_wq_param wq;
56 u16 eq_ix;
57 };
58
59 struct mlx5e_channel_param {
60 struct mlx5e_rq_param rq;
61 struct mlx5e_sq_param sq;
62 struct mlx5e_cq_param rx_cq;
63 struct mlx5e_cq_param tx_cq;
64 };
65
66 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
67 {
68 struct mlx5_core_dev *mdev = priv->mdev;
69 u8 port_state;
70
71 port_state = mlx5_query_vport_state(mdev,
72 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
73
74 if (port_state == VPORT_STATE_UP)
75 netif_carrier_on(priv->netdev);
76 else
77 netif_carrier_off(priv->netdev);
78 }
79
80 static void mlx5e_update_carrier_work(struct work_struct *work)
81 {
82 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
83 update_carrier_work);
84
85 mutex_lock(&priv->state_lock);
86 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
87 mlx5e_update_carrier(priv);
88 mutex_unlock(&priv->state_lock);
89 }
90
91 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
92 {
93 struct mlx5_core_dev *mdev = priv->mdev;
94 struct mlx5e_pport_stats *s = &priv->stats.pport;
95 u32 *in;
96 u32 *out;
97 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
98
99 in = mlx5_vzalloc(sz);
100 out = mlx5_vzalloc(sz);
101 if (!in || !out)
102 goto free_out;
103
104 MLX5_SET(ppcnt_reg, in, local_port, 1);
105
106 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
107 mlx5_core_access_reg(mdev, in, sz, out,
108 sz, MLX5_REG_PPCNT, 0, 0);
109 memcpy(s->IEEE_802_3_counters,
110 MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
111 sizeof(s->IEEE_802_3_counters));
112
113 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
114 mlx5_core_access_reg(mdev, in, sz, out,
115 sz, MLX5_REG_PPCNT, 0, 0);
116 memcpy(s->RFC_2863_counters,
117 MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
118 sizeof(s->RFC_2863_counters));
119
120 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
121 mlx5_core_access_reg(mdev, in, sz, out,
122 sz, MLX5_REG_PPCNT, 0, 0);
123 memcpy(s->RFC_2819_counters,
124 MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
125 sizeof(s->RFC_2819_counters));
126
127 free_out:
128 kvfree(in);
129 kvfree(out);
130 }
131
132 void mlx5e_update_stats(struct mlx5e_priv *priv)
133 {
134 struct mlx5_core_dev *mdev = priv->mdev;
135 struct mlx5e_vport_stats *s = &priv->stats.vport;
136 struct mlx5e_rq_stats *rq_stats;
137 struct mlx5e_sq_stats *sq_stats;
138 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
139 u32 *out;
140 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
141 u64 tx_offload_none;
142 int i, j;
143
144 out = mlx5_vzalloc(outlen);
145 if (!out)
146 return;
147
148 /* Collect firts the SW counters and then HW for consistency */
149 s->rx_packets = 0;
150 s->rx_bytes = 0;
151 s->tx_packets = 0;
152 s->tx_bytes = 0;
153 s->tso_packets = 0;
154 s->tso_bytes = 0;
155 s->tso_inner_packets = 0;
156 s->tso_inner_bytes = 0;
157 s->tx_queue_stopped = 0;
158 s->tx_queue_wake = 0;
159 s->tx_queue_dropped = 0;
160 s->tx_csum_inner = 0;
161 tx_offload_none = 0;
162 s->lro_packets = 0;
163 s->lro_bytes = 0;
164 s->rx_csum_none = 0;
165 s->rx_csum_sw = 0;
166 s->rx_wqe_err = 0;
167 for (i = 0; i < priv->params.num_channels; i++) {
168 rq_stats = &priv->channel[i]->rq.stats;
169
170 s->rx_packets += rq_stats->packets;
171 s->rx_bytes += rq_stats->bytes;
172 s->lro_packets += rq_stats->lro_packets;
173 s->lro_bytes += rq_stats->lro_bytes;
174 s->rx_csum_none += rq_stats->csum_none;
175 s->rx_csum_sw += rq_stats->csum_sw;
176 s->rx_wqe_err += rq_stats->wqe_err;
177
178 for (j = 0; j < priv->params.num_tc; j++) {
179 sq_stats = &priv->channel[i]->sq[j].stats;
180
181 s->tx_packets += sq_stats->packets;
182 s->tx_bytes += sq_stats->bytes;
183 s->tso_packets += sq_stats->tso_packets;
184 s->tso_bytes += sq_stats->tso_bytes;
185 s->tso_inner_packets += sq_stats->tso_inner_packets;
186 s->tso_inner_bytes += sq_stats->tso_inner_bytes;
187 s->tx_queue_stopped += sq_stats->stopped;
188 s->tx_queue_wake += sq_stats->wake;
189 s->tx_queue_dropped += sq_stats->dropped;
190 s->tx_csum_inner += sq_stats->csum_offload_inner;
191 tx_offload_none += sq_stats->csum_offload_none;
192 }
193 }
194
195 /* HW counters */
196 memset(in, 0, sizeof(in));
197
198 MLX5_SET(query_vport_counter_in, in, opcode,
199 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
200 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
201 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
202
203 memset(out, 0, outlen);
204
205 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
206 goto free_out;
207
208 #define MLX5_GET_CTR(p, x) \
209 MLX5_GET64(query_vport_counter_out, p, x)
210
211 s->rx_error_packets =
212 MLX5_GET_CTR(out, received_errors.packets);
213 s->rx_error_bytes =
214 MLX5_GET_CTR(out, received_errors.octets);
215 s->tx_error_packets =
216 MLX5_GET_CTR(out, transmit_errors.packets);
217 s->tx_error_bytes =
218 MLX5_GET_CTR(out, transmit_errors.octets);
219
220 s->rx_unicast_packets =
221 MLX5_GET_CTR(out, received_eth_unicast.packets);
222 s->rx_unicast_bytes =
223 MLX5_GET_CTR(out, received_eth_unicast.octets);
224 s->tx_unicast_packets =
225 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
226 s->tx_unicast_bytes =
227 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
228
229 s->rx_multicast_packets =
230 MLX5_GET_CTR(out, received_eth_multicast.packets);
231 s->rx_multicast_bytes =
232 MLX5_GET_CTR(out, received_eth_multicast.octets);
233 s->tx_multicast_packets =
234 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
235 s->tx_multicast_bytes =
236 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
237
238 s->rx_broadcast_packets =
239 MLX5_GET_CTR(out, received_eth_broadcast.packets);
240 s->rx_broadcast_bytes =
241 MLX5_GET_CTR(out, received_eth_broadcast.octets);
242 s->tx_broadcast_packets =
243 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
244 s->tx_broadcast_bytes =
245 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
246
247 /* Update calculated offload counters */
248 s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner;
249 s->rx_csum_good = s->rx_packets - s->rx_csum_none -
250 s->rx_csum_sw;
251
252 mlx5e_update_pport_counters(priv);
253 free_out:
254 kvfree(out);
255 }
256
257 static void mlx5e_update_stats_work(struct work_struct *work)
258 {
259 struct delayed_work *dwork = to_delayed_work(work);
260 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
261 update_stats_work);
262 mutex_lock(&priv->state_lock);
263 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
264 mlx5e_update_stats(priv);
265 schedule_delayed_work(dwork,
266 msecs_to_jiffies(
267 MLX5E_UPDATE_STATS_INTERVAL));
268 }
269 mutex_unlock(&priv->state_lock);
270 }
271
272 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
273 enum mlx5_dev_event event, unsigned long param)
274 {
275 struct mlx5e_priv *priv = vpriv;
276
277 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
278 return;
279
280 switch (event) {
281 case MLX5_DEV_EVENT_PORT_UP:
282 case MLX5_DEV_EVENT_PORT_DOWN:
283 schedule_work(&priv->update_carrier_work);
284 break;
285
286 default:
287 break;
288 }
289 }
290
291 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
292 {
293 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
294 }
295
296 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
297 {
298 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
299 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
300 }
301
302 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
303 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
304
305 static int mlx5e_create_rq(struct mlx5e_channel *c,
306 struct mlx5e_rq_param *param,
307 struct mlx5e_rq *rq)
308 {
309 struct mlx5e_priv *priv = c->priv;
310 struct mlx5_core_dev *mdev = priv->mdev;
311 void *rqc = param->rqc;
312 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
313 int wq_sz;
314 int err;
315 int i;
316
317 param->wq.db_numa_node = cpu_to_node(c->cpu);
318
319 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
320 &rq->wq_ctrl);
321 if (err)
322 return err;
323
324 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
325
326 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
327 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
328 cpu_to_node(c->cpu));
329 if (!rq->skb) {
330 err = -ENOMEM;
331 goto err_rq_wq_destroy;
332 }
333
334 rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
335 MLX5E_SW2HW_MTU(priv->netdev->mtu);
336 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
337
338 for (i = 0; i < wq_sz; i++) {
339 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
340 u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
341
342 wqe->data.lkey = c->mkey_be;
343 wqe->data.byte_count =
344 cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
345 }
346
347 rq->pdev = c->pdev;
348 rq->netdev = c->netdev;
349 rq->tstamp = &priv->tstamp;
350 rq->channel = c;
351 rq->ix = c->ix;
352 rq->priv = c->priv;
353
354 return 0;
355
356 err_rq_wq_destroy:
357 mlx5_wq_destroy(&rq->wq_ctrl);
358
359 return err;
360 }
361
362 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
363 {
364 kfree(rq->skb);
365 mlx5_wq_destroy(&rq->wq_ctrl);
366 }
367
368 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
369 {
370 struct mlx5e_priv *priv = rq->priv;
371 struct mlx5_core_dev *mdev = priv->mdev;
372
373 void *in;
374 void *rqc;
375 void *wq;
376 int inlen;
377 int err;
378
379 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
380 sizeof(u64) * rq->wq_ctrl.buf.npages;
381 in = mlx5_vzalloc(inlen);
382 if (!in)
383 return -ENOMEM;
384
385 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
386 wq = MLX5_ADDR_OF(rqc, rqc, wq);
387
388 memcpy(rqc, param->rqc, sizeof(param->rqc));
389
390 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
391 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
392 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
393 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
394 MLX5_ADAPTER_PAGE_SHIFT);
395 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
396
397 mlx5_fill_page_array(&rq->wq_ctrl.buf,
398 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
399
400 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
401
402 kvfree(in);
403
404 return err;
405 }
406
407 static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
408 {
409 struct mlx5e_channel *c = rq->channel;
410 struct mlx5e_priv *priv = c->priv;
411 struct mlx5_core_dev *mdev = priv->mdev;
412
413 void *in;
414 void *rqc;
415 int inlen;
416 int err;
417
418 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
419 in = mlx5_vzalloc(inlen);
420 if (!in)
421 return -ENOMEM;
422
423 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
424
425 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
426 MLX5_SET(rqc, rqc, state, next_state);
427
428 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
429
430 kvfree(in);
431
432 return err;
433 }
434
435 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
436 {
437 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
438 }
439
440 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
441 {
442 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
443 struct mlx5e_channel *c = rq->channel;
444 struct mlx5e_priv *priv = c->priv;
445 struct mlx5_wq_ll *wq = &rq->wq;
446
447 while (time_before(jiffies, exp_time)) {
448 if (wq->cur_sz >= priv->params.min_rx_wqes)
449 return 0;
450
451 msleep(20);
452 }
453
454 return -ETIMEDOUT;
455 }
456
457 static int mlx5e_open_rq(struct mlx5e_channel *c,
458 struct mlx5e_rq_param *param,
459 struct mlx5e_rq *rq)
460 {
461 int err;
462
463 err = mlx5e_create_rq(c, param, rq);
464 if (err)
465 return err;
466
467 err = mlx5e_enable_rq(rq, param);
468 if (err)
469 goto err_destroy_rq;
470
471 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
472 if (err)
473 goto err_disable_rq;
474
475 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
476 mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */
477
478 return 0;
479
480 err_disable_rq:
481 mlx5e_disable_rq(rq);
482 err_destroy_rq:
483 mlx5e_destroy_rq(rq);
484
485 return err;
486 }
487
488 static void mlx5e_close_rq(struct mlx5e_rq *rq)
489 {
490 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
491 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
492
493 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
494 while (!mlx5_wq_ll_is_empty(&rq->wq))
495 msleep(20);
496
497 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
498 napi_synchronize(&rq->channel->napi);
499
500 mlx5e_disable_rq(rq);
501 mlx5e_destroy_rq(rq);
502 }
503
504 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
505 {
506 kfree(sq->wqe_info);
507 kfree(sq->dma_fifo);
508 kfree(sq->skb);
509 }
510
511 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
512 {
513 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
514 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
515
516 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
517 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
518 numa);
519 sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
520 numa);
521
522 if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
523 mlx5e_free_sq_db(sq);
524 return -ENOMEM;
525 }
526
527 sq->dma_fifo_mask = df_sz - 1;
528
529 return 0;
530 }
531
532 static int mlx5e_create_sq(struct mlx5e_channel *c,
533 int tc,
534 struct mlx5e_sq_param *param,
535 struct mlx5e_sq *sq)
536 {
537 struct mlx5e_priv *priv = c->priv;
538 struct mlx5_core_dev *mdev = priv->mdev;
539
540 void *sqc = param->sqc;
541 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
542 int txq_ix;
543 int err;
544
545 err = mlx5_alloc_map_uar(mdev, &sq->uar, true);
546 if (err)
547 return err;
548
549 param->wq.db_numa_node = cpu_to_node(c->cpu);
550
551 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
552 &sq->wq_ctrl);
553 if (err)
554 goto err_unmap_free_uar;
555
556 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
557 if (sq->uar.bf_map) {
558 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
559 sq->uar_map = sq->uar.bf_map;
560 } else {
561 sq->uar_map = sq->uar.map;
562 }
563 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
564 sq->max_inline = param->max_inline;
565
566 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
567 if (err)
568 goto err_sq_wq_destroy;
569
570 txq_ix = c->ix + tc * priv->params.num_channels;
571 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
572
573 sq->pdev = c->pdev;
574 sq->tstamp = &priv->tstamp;
575 sq->mkey_be = c->mkey_be;
576 sq->channel = c;
577 sq->tc = tc;
578 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
579 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
580 priv->txq_to_sq_map[txq_ix] = sq;
581
582 return 0;
583
584 err_sq_wq_destroy:
585 mlx5_wq_destroy(&sq->wq_ctrl);
586
587 err_unmap_free_uar:
588 mlx5_unmap_free_uar(mdev, &sq->uar);
589
590 return err;
591 }
592
593 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
594 {
595 struct mlx5e_channel *c = sq->channel;
596 struct mlx5e_priv *priv = c->priv;
597
598 mlx5e_free_sq_db(sq);
599 mlx5_wq_destroy(&sq->wq_ctrl);
600 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
601 }
602
603 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
604 {
605 struct mlx5e_channel *c = sq->channel;
606 struct mlx5e_priv *priv = c->priv;
607 struct mlx5_core_dev *mdev = priv->mdev;
608
609 void *in;
610 void *sqc;
611 void *wq;
612 int inlen;
613 int err;
614
615 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
616 sizeof(u64) * sq->wq_ctrl.buf.npages;
617 in = mlx5_vzalloc(inlen);
618 if (!in)
619 return -ENOMEM;
620
621 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
622 wq = MLX5_ADDR_OF(sqc, sqc, wq);
623
624 memcpy(sqc, param->sqc, sizeof(param->sqc));
625
626 MLX5_SET(sqc, sqc, tis_num_0, priv->tisn[sq->tc]);
627 MLX5_SET(sqc, sqc, cqn, c->sq[sq->tc].cq.mcq.cqn);
628 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
629 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
630 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
631
632 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
633 MLX5_SET(wq, wq, uar_page, sq->uar.index);
634 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
635 MLX5_ADAPTER_PAGE_SHIFT);
636 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
637
638 mlx5_fill_page_array(&sq->wq_ctrl.buf,
639 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
640
641 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
642
643 kvfree(in);
644
645 return err;
646 }
647
648 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
649 {
650 struct mlx5e_channel *c = sq->channel;
651 struct mlx5e_priv *priv = c->priv;
652 struct mlx5_core_dev *mdev = priv->mdev;
653
654 void *in;
655 void *sqc;
656 int inlen;
657 int err;
658
659 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
660 in = mlx5_vzalloc(inlen);
661 if (!in)
662 return -ENOMEM;
663
664 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
665
666 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
667 MLX5_SET(sqc, sqc, state, next_state);
668
669 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
670
671 kvfree(in);
672
673 return err;
674 }
675
676 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
677 {
678 struct mlx5e_channel *c = sq->channel;
679 struct mlx5e_priv *priv = c->priv;
680 struct mlx5_core_dev *mdev = priv->mdev;
681
682 mlx5_core_destroy_sq(mdev, sq->sqn);
683 }
684
685 static int mlx5e_open_sq(struct mlx5e_channel *c,
686 int tc,
687 struct mlx5e_sq_param *param,
688 struct mlx5e_sq *sq)
689 {
690 int err;
691
692 err = mlx5e_create_sq(c, tc, param, sq);
693 if (err)
694 return err;
695
696 err = mlx5e_enable_sq(sq, param);
697 if (err)
698 goto err_destroy_sq;
699
700 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
701 if (err)
702 goto err_disable_sq;
703
704 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
705 netdev_tx_reset_queue(sq->txq);
706 netif_tx_start_queue(sq->txq);
707
708 return 0;
709
710 err_disable_sq:
711 mlx5e_disable_sq(sq);
712 err_destroy_sq:
713 mlx5e_destroy_sq(sq);
714
715 return err;
716 }
717
718 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
719 {
720 __netif_tx_lock_bh(txq);
721 netif_tx_stop_queue(txq);
722 __netif_tx_unlock_bh(txq);
723 }
724
725 static void mlx5e_close_sq(struct mlx5e_sq *sq)
726 {
727 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
728 napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
729 netif_tx_disable_queue(sq->txq);
730
731 /* ensure hw is notified of all pending wqes */
732 if (mlx5e_sq_has_room_for(sq, 1))
733 mlx5e_send_nop(sq, true);
734
735 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
736 while (sq->cc != sq->pc) /* wait till sq is empty */
737 msleep(20);
738
739 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
740 napi_synchronize(&sq->channel->napi);
741
742 mlx5e_disable_sq(sq);
743 mlx5e_destroy_sq(sq);
744 }
745
746 static int mlx5e_create_cq(struct mlx5e_channel *c,
747 struct mlx5e_cq_param *param,
748 struct mlx5e_cq *cq)
749 {
750 struct mlx5e_priv *priv = c->priv;
751 struct mlx5_core_dev *mdev = priv->mdev;
752 struct mlx5_core_cq *mcq = &cq->mcq;
753 int eqn_not_used;
754 unsigned int irqn;
755 int err;
756 u32 i;
757
758 param->wq.buf_numa_node = cpu_to_node(c->cpu);
759 param->wq.db_numa_node = cpu_to_node(c->cpu);
760 param->eq_ix = c->ix;
761
762 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
763 &cq->wq_ctrl);
764 if (err)
765 return err;
766
767 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
768
769 cq->napi = &c->napi;
770
771 mcq->cqe_sz = 64;
772 mcq->set_ci_db = cq->wq_ctrl.db.db;
773 mcq->arm_db = cq->wq_ctrl.db.db + 1;
774 *mcq->set_ci_db = 0;
775 *mcq->arm_db = 0;
776 mcq->vector = param->eq_ix;
777 mcq->comp = mlx5e_completion_event;
778 mcq->event = mlx5e_cq_error_event;
779 mcq->irqn = irqn;
780 mcq->uar = &priv->cq_uar;
781
782 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
783 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
784
785 cqe->op_own = 0xf1;
786 }
787
788 cq->channel = c;
789 cq->priv = priv;
790
791 return 0;
792 }
793
794 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
795 {
796 mlx5_wq_destroy(&cq->wq_ctrl);
797 }
798
799 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
800 {
801 struct mlx5e_priv *priv = cq->priv;
802 struct mlx5_core_dev *mdev = priv->mdev;
803 struct mlx5_core_cq *mcq = &cq->mcq;
804
805 void *in;
806 void *cqc;
807 int inlen;
808 unsigned int irqn_not_used;
809 int eqn;
810 int err;
811
812 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
813 sizeof(u64) * cq->wq_ctrl.buf.npages;
814 in = mlx5_vzalloc(inlen);
815 if (!in)
816 return -ENOMEM;
817
818 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
819
820 memcpy(cqc, param->cqc, sizeof(param->cqc));
821
822 mlx5_fill_page_array(&cq->wq_ctrl.buf,
823 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
824
825 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
826
827 MLX5_SET(cqc, cqc, c_eqn, eqn);
828 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
829 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
830 MLX5_ADAPTER_PAGE_SHIFT);
831 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
832
833 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
834
835 kvfree(in);
836
837 if (err)
838 return err;
839
840 mlx5e_cq_arm(cq);
841
842 return 0;
843 }
844
845 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
846 {
847 struct mlx5e_priv *priv = cq->priv;
848 struct mlx5_core_dev *mdev = priv->mdev;
849
850 mlx5_core_destroy_cq(mdev, &cq->mcq);
851 }
852
853 static int mlx5e_open_cq(struct mlx5e_channel *c,
854 struct mlx5e_cq_param *param,
855 struct mlx5e_cq *cq,
856 u16 moderation_usecs,
857 u16 moderation_frames)
858 {
859 int err;
860 struct mlx5e_priv *priv = c->priv;
861 struct mlx5_core_dev *mdev = priv->mdev;
862
863 err = mlx5e_create_cq(c, param, cq);
864 if (err)
865 return err;
866
867 err = mlx5e_enable_cq(cq, param);
868 if (err)
869 goto err_destroy_cq;
870
871 if (MLX5_CAP_GEN(mdev, cq_moderation))
872 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
873 moderation_usecs,
874 moderation_frames);
875 return 0;
876
877 err_destroy_cq:
878 mlx5e_destroy_cq(cq);
879
880 return err;
881 }
882
883 static void mlx5e_close_cq(struct mlx5e_cq *cq)
884 {
885 mlx5e_disable_cq(cq);
886 mlx5e_destroy_cq(cq);
887 }
888
889 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
890 {
891 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
892 }
893
894 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
895 struct mlx5e_channel_param *cparam)
896 {
897 struct mlx5e_priv *priv = c->priv;
898 int err;
899 int tc;
900
901 for (tc = 0; tc < c->num_tc; tc++) {
902 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
903 priv->params.tx_cq_moderation_usec,
904 priv->params.tx_cq_moderation_pkts);
905 if (err)
906 goto err_close_tx_cqs;
907 }
908
909 return 0;
910
911 err_close_tx_cqs:
912 for (tc--; tc >= 0; tc--)
913 mlx5e_close_cq(&c->sq[tc].cq);
914
915 return err;
916 }
917
918 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
919 {
920 int tc;
921
922 for (tc = 0; tc < c->num_tc; tc++)
923 mlx5e_close_cq(&c->sq[tc].cq);
924 }
925
926 static int mlx5e_open_sqs(struct mlx5e_channel *c,
927 struct mlx5e_channel_param *cparam)
928 {
929 int err;
930 int tc;
931
932 for (tc = 0; tc < c->num_tc; tc++) {
933 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
934 if (err)
935 goto err_close_sqs;
936 }
937
938 return 0;
939
940 err_close_sqs:
941 for (tc--; tc >= 0; tc--)
942 mlx5e_close_sq(&c->sq[tc]);
943
944 return err;
945 }
946
947 static void mlx5e_close_sqs(struct mlx5e_channel *c)
948 {
949 int tc;
950
951 for (tc = 0; tc < c->num_tc; tc++)
952 mlx5e_close_sq(&c->sq[tc]);
953 }
954
955 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
956 {
957 int i;
958
959 for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
960 priv->channeltc_to_txq_map[ix][i] =
961 ix + i * priv->params.num_channels;
962 }
963
964 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
965 struct mlx5e_channel_param *cparam,
966 struct mlx5e_channel **cp)
967 {
968 struct net_device *netdev = priv->netdev;
969 int cpu = mlx5e_get_cpu(priv, ix);
970 struct mlx5e_channel *c;
971 int err;
972
973 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
974 if (!c)
975 return -ENOMEM;
976
977 c->priv = priv;
978 c->ix = ix;
979 c->cpu = cpu;
980 c->pdev = &priv->mdev->pdev->dev;
981 c->netdev = priv->netdev;
982 c->mkey_be = cpu_to_be32(priv->mkey.key);
983 c->num_tc = priv->params.num_tc;
984
985 mlx5e_build_channeltc_to_txq_map(priv, ix);
986
987 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
988
989 err = mlx5e_open_tx_cqs(c, cparam);
990 if (err)
991 goto err_napi_del;
992
993 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
994 priv->params.rx_cq_moderation_usec,
995 priv->params.rx_cq_moderation_pkts);
996 if (err)
997 goto err_close_tx_cqs;
998
999 napi_enable(&c->napi);
1000
1001 err = mlx5e_open_sqs(c, cparam);
1002 if (err)
1003 goto err_disable_napi;
1004
1005 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1006 if (err)
1007 goto err_close_sqs;
1008
1009 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1010 *cp = c;
1011
1012 return 0;
1013
1014 err_close_sqs:
1015 mlx5e_close_sqs(c);
1016
1017 err_disable_napi:
1018 napi_disable(&c->napi);
1019 mlx5e_close_cq(&c->rq.cq);
1020
1021 err_close_tx_cqs:
1022 mlx5e_close_tx_cqs(c);
1023
1024 err_napi_del:
1025 netif_napi_del(&c->napi);
1026 napi_hash_del(&c->napi);
1027 kfree(c);
1028
1029 return err;
1030 }
1031
1032 static void mlx5e_close_channel(struct mlx5e_channel *c)
1033 {
1034 mlx5e_close_rq(&c->rq);
1035 mlx5e_close_sqs(c);
1036 napi_disable(&c->napi);
1037 mlx5e_close_cq(&c->rq.cq);
1038 mlx5e_close_tx_cqs(c);
1039 netif_napi_del(&c->napi);
1040
1041 napi_hash_del(&c->napi);
1042 synchronize_rcu();
1043
1044 kfree(c);
1045 }
1046
1047 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1048 struct mlx5e_rq_param *param)
1049 {
1050 void *rqc = param->rqc;
1051 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1052
1053 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1054 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1055 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1056 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1057 MLX5_SET(wq, wq, pd, priv->pdn);
1058
1059 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1060 param->wq.linear = 1;
1061 }
1062
1063 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1064 {
1065 void *rqc = param->rqc;
1066 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1067
1068 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1069 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1070 }
1071
1072 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1073 struct mlx5e_sq_param *param)
1074 {
1075 void *sqc = param->sqc;
1076 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1077
1078 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1079 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1080 MLX5_SET(wq, wq, pd, priv->pdn);
1081
1082 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1083 param->max_inline = priv->params.tx_max_inline;
1084 }
1085
1086 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1087 struct mlx5e_cq_param *param)
1088 {
1089 void *cqc = param->cqc;
1090
1091 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1092 }
1093
1094 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1095 struct mlx5e_cq_param *param)
1096 {
1097 void *cqc = param->cqc;
1098
1099 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1100
1101 mlx5e_build_common_cq_param(priv, param);
1102 }
1103
1104 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1105 struct mlx5e_cq_param *param)
1106 {
1107 void *cqc = param->cqc;
1108
1109 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1110
1111 mlx5e_build_common_cq_param(priv, param);
1112 }
1113
1114 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1115 struct mlx5e_channel_param *cparam)
1116 {
1117 memset(cparam, 0, sizeof(*cparam));
1118
1119 mlx5e_build_rq_param(priv, &cparam->rq);
1120 mlx5e_build_sq_param(priv, &cparam->sq);
1121 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1122 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1123 }
1124
1125 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1126 {
1127 struct mlx5e_channel_param cparam;
1128 int nch = priv->params.num_channels;
1129 int err = -ENOMEM;
1130 int i;
1131 int j;
1132
1133 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1134 GFP_KERNEL);
1135
1136 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1137 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1138
1139 if (!priv->channel || !priv->txq_to_sq_map)
1140 goto err_free_txq_to_sq_map;
1141
1142 mlx5e_build_channel_param(priv, &cparam);
1143 for (i = 0; i < nch; i++) {
1144 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1145 if (err)
1146 goto err_close_channels;
1147 }
1148
1149 for (j = 0; j < nch; j++) {
1150 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1151 if (err)
1152 goto err_close_channels;
1153 }
1154
1155 return 0;
1156
1157 err_close_channels:
1158 for (i--; i >= 0; i--)
1159 mlx5e_close_channel(priv->channel[i]);
1160
1161 err_free_txq_to_sq_map:
1162 kfree(priv->txq_to_sq_map);
1163 kfree(priv->channel);
1164
1165 return err;
1166 }
1167
1168 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1169 {
1170 int i;
1171
1172 for (i = 0; i < priv->params.num_channels; i++)
1173 mlx5e_close_channel(priv->channel[i]);
1174
1175 kfree(priv->txq_to_sq_map);
1176 kfree(priv->channel);
1177 }
1178
1179 static int mlx5e_rx_hash_fn(int hfunc)
1180 {
1181 return (hfunc == ETH_RSS_HASH_TOP) ?
1182 MLX5_RX_HASH_FN_TOEPLITZ :
1183 MLX5_RX_HASH_FN_INVERTED_XOR8;
1184 }
1185
1186 static int mlx5e_bits_invert(unsigned long a, int size)
1187 {
1188 int inv = 0;
1189 int i;
1190
1191 for (i = 0; i < size; i++)
1192 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1193
1194 return inv;
1195 }
1196
1197 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1198 {
1199 int i;
1200
1201 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1202 int ix = i;
1203
1204 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1205 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1206
1207 ix = priv->params.indirection_rqt[ix];
1208 MLX5_SET(rqtc, rqtc, rq_num[i],
1209 test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1210 priv->channel[ix]->rq.rqn :
1211 priv->drop_rq.rqn);
1212 }
1213 }
1214
1215 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1216 enum mlx5e_rqt_ix rqt_ix)
1217 {
1218
1219 switch (rqt_ix) {
1220 case MLX5E_INDIRECTION_RQT:
1221 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1222
1223 break;
1224
1225 default: /* MLX5E_SINGLE_RQ_RQT */
1226 MLX5_SET(rqtc, rqtc, rq_num[0],
1227 test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1228 priv->channel[0]->rq.rqn :
1229 priv->drop_rq.rqn);
1230
1231 break;
1232 }
1233 }
1234
1235 static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1236 {
1237 struct mlx5_core_dev *mdev = priv->mdev;
1238 u32 *in;
1239 void *rqtc;
1240 int inlen;
1241 int sz;
1242 int err;
1243
1244 sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1245
1246 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1247 in = mlx5_vzalloc(inlen);
1248 if (!in)
1249 return -ENOMEM;
1250
1251 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1252
1253 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1254 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1255
1256 mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1257
1258 err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
1259
1260 kvfree(in);
1261
1262 return err;
1263 }
1264
1265 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1266 {
1267 struct mlx5_core_dev *mdev = priv->mdev;
1268 u32 *in;
1269 void *rqtc;
1270 int inlen;
1271 int sz;
1272 int err;
1273
1274 sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1275
1276 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1277 in = mlx5_vzalloc(inlen);
1278 if (!in)
1279 return -ENOMEM;
1280
1281 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1282
1283 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1284
1285 mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1286
1287 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1288
1289 err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen);
1290
1291 kvfree(in);
1292
1293 return err;
1294 }
1295
1296 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1297 {
1298 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
1299 }
1300
1301 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1302 {
1303 mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
1304 mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1305 }
1306
1307 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1308 {
1309 if (!priv->params.lro_en)
1310 return;
1311
1312 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1313
1314 MLX5_SET(tirc, tirc, lro_enable_mask,
1315 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1316 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1317 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1318 (priv->params.lro_wqe_sz -
1319 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1320 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1321 MLX5_CAP_ETH(priv->mdev,
1322 lro_timer_supported_periods[2]));
1323 }
1324
1325 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1326 {
1327 MLX5_SET(tirc, tirc, rx_hash_fn,
1328 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1329 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1330 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1331 rx_hash_toeplitz_key);
1332 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1333 rx_hash_toeplitz_key);
1334
1335 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1336 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1337 }
1338 }
1339
1340 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1341 {
1342 struct mlx5_core_dev *mdev = priv->mdev;
1343
1344 void *in;
1345 void *tirc;
1346 int inlen;
1347 int err;
1348 int tt;
1349
1350 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1351 in = mlx5_vzalloc(inlen);
1352 if (!in)
1353 return -ENOMEM;
1354
1355 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1356 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1357
1358 mlx5e_build_tir_ctx_lro(tirc, priv);
1359
1360 for (tt = 0; tt < MLX5E_NUM_TT; tt++) {
1361 err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen);
1362 if (err)
1363 break;
1364 }
1365
1366 kvfree(in);
1367
1368 return err;
1369 }
1370
1371 static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev *mdev,
1372 u32 tirn)
1373 {
1374 void *in;
1375 int inlen;
1376 int err;
1377
1378 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1379 in = mlx5_vzalloc(inlen);
1380 if (!in)
1381 return -ENOMEM;
1382
1383 MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1384
1385 err = mlx5_core_modify_tir(mdev, tirn, in, inlen);
1386
1387 kvfree(in);
1388
1389 return err;
1390 }
1391
1392 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1393 {
1394 int err;
1395 int i;
1396
1397 for (i = 0; i < MLX5E_NUM_TT; i++) {
1398 err = mlx5e_refresh_tir_self_loopback_enable(priv->mdev,
1399 priv->tirn[i]);
1400 if (err)
1401 return err;
1402 }
1403
1404 return 0;
1405 }
1406
1407 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1408 {
1409 struct mlx5e_priv *priv = netdev_priv(netdev);
1410 struct mlx5_core_dev *mdev = priv->mdev;
1411 int hw_mtu;
1412 int err;
1413
1414 err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1415 if (err)
1416 return err;
1417
1418 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1419
1420 if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1421 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1422 __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1423
1424 netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1425 return 0;
1426 }
1427
1428 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1429 {
1430 struct mlx5e_priv *priv = netdev_priv(netdev);
1431 int nch = priv->params.num_channels;
1432 int ntc = priv->params.num_tc;
1433 int tc;
1434
1435 netdev_reset_tc(netdev);
1436
1437 if (ntc == 1)
1438 return;
1439
1440 netdev_set_num_tc(netdev, ntc);
1441
1442 for (tc = 0; tc < ntc; tc++)
1443 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1444 }
1445
1446 int mlx5e_open_locked(struct net_device *netdev)
1447 {
1448 struct mlx5e_priv *priv = netdev_priv(netdev);
1449 int num_txqs;
1450 int err;
1451
1452 set_bit(MLX5E_STATE_OPENED, &priv->state);
1453
1454 mlx5e_netdev_set_tcs(netdev);
1455
1456 num_txqs = priv->params.num_channels * priv->params.num_tc;
1457 netif_set_real_num_tx_queues(netdev, num_txqs);
1458 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1459
1460 err = mlx5e_set_dev_port_mtu(netdev);
1461 if (err)
1462 goto err_clear_state_opened_flag;
1463
1464 err = mlx5e_open_channels(priv);
1465 if (err) {
1466 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1467 __func__, err);
1468 goto err_clear_state_opened_flag;
1469 }
1470
1471 err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1472 if (err) {
1473 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1474 __func__, err);
1475 goto err_close_channels;
1476 }
1477
1478 mlx5e_redirect_rqts(priv);
1479 mlx5e_update_carrier(priv);
1480 mlx5e_timestamp_init(priv);
1481
1482 schedule_delayed_work(&priv->update_stats_work, 0);
1483
1484 return 0;
1485
1486 err_close_channels:
1487 mlx5e_close_channels(priv);
1488 err_clear_state_opened_flag:
1489 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1490 return err;
1491 }
1492
1493 static int mlx5e_open(struct net_device *netdev)
1494 {
1495 struct mlx5e_priv *priv = netdev_priv(netdev);
1496 int err;
1497
1498 mutex_lock(&priv->state_lock);
1499 err = mlx5e_open_locked(netdev);
1500 mutex_unlock(&priv->state_lock);
1501
1502 return err;
1503 }
1504
1505 int mlx5e_close_locked(struct net_device *netdev)
1506 {
1507 struct mlx5e_priv *priv = netdev_priv(netdev);
1508
1509 /* May already be CLOSED in case a previous configuration operation
1510 * (e.g RX/TX queue size change) that involves close&open failed.
1511 */
1512 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1513 return 0;
1514
1515 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1516
1517 mlx5e_timestamp_cleanup(priv);
1518 netif_carrier_off(priv->netdev);
1519 mlx5e_redirect_rqts(priv);
1520 mlx5e_close_channels(priv);
1521
1522 return 0;
1523 }
1524
1525 static int mlx5e_close(struct net_device *netdev)
1526 {
1527 struct mlx5e_priv *priv = netdev_priv(netdev);
1528 int err;
1529
1530 mutex_lock(&priv->state_lock);
1531 err = mlx5e_close_locked(netdev);
1532 mutex_unlock(&priv->state_lock);
1533
1534 return err;
1535 }
1536
1537 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1538 struct mlx5e_rq *rq,
1539 struct mlx5e_rq_param *param)
1540 {
1541 struct mlx5_core_dev *mdev = priv->mdev;
1542 void *rqc = param->rqc;
1543 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1544 int err;
1545
1546 param->wq.db_numa_node = param->wq.buf_numa_node;
1547
1548 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1549 &rq->wq_ctrl);
1550 if (err)
1551 return err;
1552
1553 rq->priv = priv;
1554
1555 return 0;
1556 }
1557
1558 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1559 struct mlx5e_cq *cq,
1560 struct mlx5e_cq_param *param)
1561 {
1562 struct mlx5_core_dev *mdev = priv->mdev;
1563 struct mlx5_core_cq *mcq = &cq->mcq;
1564 int eqn_not_used;
1565 unsigned int irqn;
1566 int err;
1567
1568 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1569 &cq->wq_ctrl);
1570 if (err)
1571 return err;
1572
1573 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1574
1575 mcq->cqe_sz = 64;
1576 mcq->set_ci_db = cq->wq_ctrl.db.db;
1577 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1578 *mcq->set_ci_db = 0;
1579 *mcq->arm_db = 0;
1580 mcq->vector = param->eq_ix;
1581 mcq->comp = mlx5e_completion_event;
1582 mcq->event = mlx5e_cq_error_event;
1583 mcq->irqn = irqn;
1584 mcq->uar = &priv->cq_uar;
1585
1586 cq->priv = priv;
1587
1588 return 0;
1589 }
1590
1591 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1592 {
1593 struct mlx5e_cq_param cq_param;
1594 struct mlx5e_rq_param rq_param;
1595 struct mlx5e_rq *rq = &priv->drop_rq;
1596 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1597 int err;
1598
1599 memset(&cq_param, 0, sizeof(cq_param));
1600 memset(&rq_param, 0, sizeof(rq_param));
1601 mlx5e_build_drop_rq_param(&rq_param);
1602
1603 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1604 if (err)
1605 return err;
1606
1607 err = mlx5e_enable_cq(cq, &cq_param);
1608 if (err)
1609 goto err_destroy_cq;
1610
1611 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1612 if (err)
1613 goto err_disable_cq;
1614
1615 err = mlx5e_enable_rq(rq, &rq_param);
1616 if (err)
1617 goto err_destroy_rq;
1618
1619 return 0;
1620
1621 err_destroy_rq:
1622 mlx5e_destroy_rq(&priv->drop_rq);
1623
1624 err_disable_cq:
1625 mlx5e_disable_cq(&priv->drop_rq.cq);
1626
1627 err_destroy_cq:
1628 mlx5e_destroy_cq(&priv->drop_rq.cq);
1629
1630 return err;
1631 }
1632
1633 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1634 {
1635 mlx5e_disable_rq(&priv->drop_rq);
1636 mlx5e_destroy_rq(&priv->drop_rq);
1637 mlx5e_disable_cq(&priv->drop_rq.cq);
1638 mlx5e_destroy_cq(&priv->drop_rq.cq);
1639 }
1640
1641 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1642 {
1643 struct mlx5_core_dev *mdev = priv->mdev;
1644 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1645 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1646
1647 memset(in, 0, sizeof(in));
1648
1649 MLX5_SET(tisc, tisc, prio, tc << 1);
1650 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1651
1652 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1653 }
1654
1655 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1656 {
1657 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1658 }
1659
1660 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1661 {
1662 int err;
1663 int tc;
1664
1665 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
1666 err = mlx5e_create_tis(priv, tc);
1667 if (err)
1668 goto err_close_tises;
1669 }
1670
1671 return 0;
1672
1673 err_close_tises:
1674 for (tc--; tc >= 0; tc--)
1675 mlx5e_destroy_tis(priv, tc);
1676
1677 return err;
1678 }
1679
1680 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1681 {
1682 int tc;
1683
1684 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
1685 mlx5e_destroy_tis(priv, tc);
1686 }
1687
1688 static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1689 {
1690 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1691
1692 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1693
1694 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1695 MLX5_HASH_FIELD_SEL_DST_IP)
1696
1697 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
1698 MLX5_HASH_FIELD_SEL_DST_IP |\
1699 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1700 MLX5_HASH_FIELD_SEL_L4_DPORT)
1701
1702 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1703 MLX5_HASH_FIELD_SEL_DST_IP |\
1704 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1705
1706 mlx5e_build_tir_ctx_lro(tirc, priv);
1707
1708 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1709
1710 switch (tt) {
1711 case MLX5E_TT_ANY:
1712 MLX5_SET(tirc, tirc, indirect_table,
1713 priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1714 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
1715 break;
1716 default:
1717 MLX5_SET(tirc, tirc, indirect_table,
1718 priv->rqtn[MLX5E_INDIRECTION_RQT]);
1719 mlx5e_build_tir_ctx_hash(tirc, priv);
1720 break;
1721 }
1722
1723 switch (tt) {
1724 case MLX5E_TT_IPV4_TCP:
1725 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1726 MLX5_L3_PROT_TYPE_IPV4);
1727 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1728 MLX5_L4_PROT_TYPE_TCP);
1729 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1730 MLX5_HASH_IP_L4PORTS);
1731 break;
1732
1733 case MLX5E_TT_IPV6_TCP:
1734 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1735 MLX5_L3_PROT_TYPE_IPV6);
1736 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1737 MLX5_L4_PROT_TYPE_TCP);
1738 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1739 MLX5_HASH_IP_L4PORTS);
1740 break;
1741
1742 case MLX5E_TT_IPV4_UDP:
1743 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1744 MLX5_L3_PROT_TYPE_IPV4);
1745 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1746 MLX5_L4_PROT_TYPE_UDP);
1747 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1748 MLX5_HASH_IP_L4PORTS);
1749 break;
1750
1751 case MLX5E_TT_IPV6_UDP:
1752 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1753 MLX5_L3_PROT_TYPE_IPV6);
1754 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1755 MLX5_L4_PROT_TYPE_UDP);
1756 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1757 MLX5_HASH_IP_L4PORTS);
1758 break;
1759
1760 case MLX5E_TT_IPV4_IPSEC_AH:
1761 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1762 MLX5_L3_PROT_TYPE_IPV4);
1763 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1764 MLX5_HASH_IP_IPSEC_SPI);
1765 break;
1766
1767 case MLX5E_TT_IPV6_IPSEC_AH:
1768 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1769 MLX5_L3_PROT_TYPE_IPV6);
1770 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1771 MLX5_HASH_IP_IPSEC_SPI);
1772 break;
1773
1774 case MLX5E_TT_IPV4_IPSEC_ESP:
1775 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1776 MLX5_L3_PROT_TYPE_IPV4);
1777 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1778 MLX5_HASH_IP_IPSEC_SPI);
1779 break;
1780
1781 case MLX5E_TT_IPV6_IPSEC_ESP:
1782 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1783 MLX5_L3_PROT_TYPE_IPV6);
1784 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1785 MLX5_HASH_IP_IPSEC_SPI);
1786 break;
1787
1788 case MLX5E_TT_IPV4:
1789 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1790 MLX5_L3_PROT_TYPE_IPV4);
1791 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1792 MLX5_HASH_IP);
1793 break;
1794
1795 case MLX5E_TT_IPV6:
1796 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1797 MLX5_L3_PROT_TYPE_IPV6);
1798 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1799 MLX5_HASH_IP);
1800 break;
1801 }
1802 }
1803
1804 static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt)
1805 {
1806 struct mlx5_core_dev *mdev = priv->mdev;
1807 u32 *in;
1808 void *tirc;
1809 int inlen;
1810 int err;
1811
1812 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1813 in = mlx5_vzalloc(inlen);
1814 if (!in)
1815 return -ENOMEM;
1816
1817 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1818
1819 mlx5e_build_tir_ctx(priv, tirc, tt);
1820
1821 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
1822
1823 kvfree(in);
1824
1825 return err;
1826 }
1827
1828 static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt)
1829 {
1830 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
1831 }
1832
1833 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
1834 {
1835 int err;
1836 int i;
1837
1838 for (i = 0; i < MLX5E_NUM_TT; i++) {
1839 err = mlx5e_create_tir(priv, i);
1840 if (err)
1841 goto err_destroy_tirs;
1842 }
1843
1844 return 0;
1845
1846 err_destroy_tirs:
1847 for (i--; i >= 0; i--)
1848 mlx5e_destroy_tir(priv, i);
1849
1850 return err;
1851 }
1852
1853 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
1854 {
1855 int i;
1856
1857 for (i = 0; i < MLX5E_NUM_TT; i++)
1858 mlx5e_destroy_tir(priv, i);
1859 }
1860
1861 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
1862 {
1863 struct mlx5e_priv *priv = netdev_priv(netdev);
1864 bool was_opened;
1865 int err = 0;
1866
1867 if (tc && tc != MLX5E_MAX_NUM_TC)
1868 return -EINVAL;
1869
1870 mutex_lock(&priv->state_lock);
1871
1872 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1873 if (was_opened)
1874 mlx5e_close_locked(priv->netdev);
1875
1876 priv->params.num_tc = tc ? tc : 1;
1877
1878 if (was_opened)
1879 err = mlx5e_open_locked(priv->netdev);
1880
1881 mutex_unlock(&priv->state_lock);
1882
1883 return err;
1884 }
1885
1886 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
1887 __be16 proto, struct tc_to_netdev *tc)
1888 {
1889 struct mlx5e_priv *priv = netdev_priv(dev);
1890
1891 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
1892 goto mqprio;
1893
1894 switch (tc->type) {
1895 case TC_SETUP_CLSFLOWER:
1896 switch (tc->cls_flower->command) {
1897 case TC_CLSFLOWER_REPLACE:
1898 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
1899 case TC_CLSFLOWER_DESTROY:
1900 return mlx5e_delete_flower(priv, tc->cls_flower);
1901 }
1902 default:
1903 return -EOPNOTSUPP;
1904 }
1905
1906 mqprio:
1907 if (tc->type != TC_SETUP_MQPRIO)
1908 return -EINVAL;
1909
1910 return mlx5e_setup_tc(dev, tc->tc);
1911 }
1912
1913 static struct rtnl_link_stats64 *
1914 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1915 {
1916 struct mlx5e_priv *priv = netdev_priv(dev);
1917 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1918
1919 stats->rx_packets = vstats->rx_packets;
1920 stats->rx_bytes = vstats->rx_bytes;
1921 stats->tx_packets = vstats->tx_packets;
1922 stats->tx_bytes = vstats->tx_bytes;
1923 stats->multicast = vstats->rx_multicast_packets +
1924 vstats->tx_multicast_packets;
1925 stats->tx_errors = vstats->tx_error_packets;
1926 stats->rx_errors = vstats->rx_error_packets;
1927 stats->tx_dropped = vstats->tx_queue_dropped;
1928 stats->rx_crc_errors = 0;
1929 stats->rx_length_errors = 0;
1930
1931 return stats;
1932 }
1933
1934 static void mlx5e_set_rx_mode(struct net_device *dev)
1935 {
1936 struct mlx5e_priv *priv = netdev_priv(dev);
1937
1938 schedule_work(&priv->set_rx_mode_work);
1939 }
1940
1941 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
1942 {
1943 struct mlx5e_priv *priv = netdev_priv(netdev);
1944 struct sockaddr *saddr = addr;
1945
1946 if (!is_valid_ether_addr(saddr->sa_data))
1947 return -EADDRNOTAVAIL;
1948
1949 netif_addr_lock_bh(netdev);
1950 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1951 netif_addr_unlock_bh(netdev);
1952
1953 schedule_work(&priv->set_rx_mode_work);
1954
1955 return 0;
1956 }
1957
1958 static int mlx5e_set_features(struct net_device *netdev,
1959 netdev_features_t features)
1960 {
1961 struct mlx5e_priv *priv = netdev_priv(netdev);
1962 int err = 0;
1963 netdev_features_t changes = features ^ netdev->features;
1964
1965 mutex_lock(&priv->state_lock);
1966
1967 if (changes & NETIF_F_LRO) {
1968 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1969
1970 if (was_opened)
1971 mlx5e_close_locked(priv->netdev);
1972
1973 priv->params.lro_en = !!(features & NETIF_F_LRO);
1974 err = mlx5e_modify_tirs_lro(priv);
1975 if (err)
1976 mlx5_core_warn(priv->mdev, "lro modify failed, %d\n",
1977 err);
1978
1979 if (was_opened)
1980 err = mlx5e_open_locked(priv->netdev);
1981 }
1982
1983 mutex_unlock(&priv->state_lock);
1984
1985 if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
1986 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1987 mlx5e_enable_vlan_filter(priv);
1988 else
1989 mlx5e_disable_vlan_filter(priv);
1990 }
1991
1992 if ((changes & NETIF_F_HW_TC) && !(features & NETIF_F_HW_TC) &&
1993 mlx5e_tc_num_filters(priv)) {
1994 netdev_err(netdev,
1995 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1996 return -EINVAL;
1997 }
1998
1999 return err;
2000 }
2001
2002 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2003 {
2004 struct mlx5e_priv *priv = netdev_priv(netdev);
2005 struct mlx5_core_dev *mdev = priv->mdev;
2006 bool was_opened;
2007 int max_mtu;
2008 int err = 0;
2009
2010 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2011
2012 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2013
2014 if (new_mtu > max_mtu) {
2015 netdev_err(netdev,
2016 "%s: Bad MTU (%d) > (%d) Max\n",
2017 __func__, new_mtu, max_mtu);
2018 return -EINVAL;
2019 }
2020
2021 mutex_lock(&priv->state_lock);
2022
2023 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2024 if (was_opened)
2025 mlx5e_close_locked(netdev);
2026
2027 netdev->mtu = new_mtu;
2028
2029 if (was_opened)
2030 err = mlx5e_open_locked(netdev);
2031
2032 mutex_unlock(&priv->state_lock);
2033
2034 return err;
2035 }
2036
2037 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2038 {
2039 switch (cmd) {
2040 case SIOCSHWTSTAMP:
2041 return mlx5e_hwstamp_set(dev, ifr);
2042 case SIOCGHWTSTAMP:
2043 return mlx5e_hwstamp_get(dev, ifr);
2044 default:
2045 return -EOPNOTSUPP;
2046 }
2047 }
2048
2049 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2050 {
2051 struct mlx5e_priv *priv = netdev_priv(dev);
2052 struct mlx5_core_dev *mdev = priv->mdev;
2053
2054 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2055 }
2056
2057 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2058 {
2059 struct mlx5e_priv *priv = netdev_priv(dev);
2060 struct mlx5_core_dev *mdev = priv->mdev;
2061
2062 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2063 vlan, qos);
2064 }
2065
2066 static int mlx5_vport_link2ifla(u8 esw_link)
2067 {
2068 switch (esw_link) {
2069 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2070 return IFLA_VF_LINK_STATE_DISABLE;
2071 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2072 return IFLA_VF_LINK_STATE_ENABLE;
2073 }
2074 return IFLA_VF_LINK_STATE_AUTO;
2075 }
2076
2077 static int mlx5_ifla_link2vport(u8 ifla_link)
2078 {
2079 switch (ifla_link) {
2080 case IFLA_VF_LINK_STATE_DISABLE:
2081 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2082 case IFLA_VF_LINK_STATE_ENABLE:
2083 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2084 }
2085 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2086 }
2087
2088 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2089 int link_state)
2090 {
2091 struct mlx5e_priv *priv = netdev_priv(dev);
2092 struct mlx5_core_dev *mdev = priv->mdev;
2093
2094 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2095 mlx5_ifla_link2vport(link_state));
2096 }
2097
2098 static int mlx5e_get_vf_config(struct net_device *dev,
2099 int vf, struct ifla_vf_info *ivi)
2100 {
2101 struct mlx5e_priv *priv = netdev_priv(dev);
2102 struct mlx5_core_dev *mdev = priv->mdev;
2103 int err;
2104
2105 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2106 if (err)
2107 return err;
2108 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2109 return 0;
2110 }
2111
2112 static int mlx5e_get_vf_stats(struct net_device *dev,
2113 int vf, struct ifla_vf_stats *vf_stats)
2114 {
2115 struct mlx5e_priv *priv = netdev_priv(dev);
2116 struct mlx5_core_dev *mdev = priv->mdev;
2117
2118 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2119 vf_stats);
2120 }
2121
2122 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2123 sa_family_t sa_family, __be16 port)
2124 {
2125 struct mlx5e_priv *priv = netdev_priv(netdev);
2126
2127 if (!mlx5e_vxlan_allowed(priv->mdev))
2128 return;
2129
2130 mlx5e_vxlan_add_port(priv, be16_to_cpu(port));
2131 }
2132
2133 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2134 sa_family_t sa_family, __be16 port)
2135 {
2136 struct mlx5e_priv *priv = netdev_priv(netdev);
2137
2138 if (!mlx5e_vxlan_allowed(priv->mdev))
2139 return;
2140
2141 mlx5e_vxlan_del_port(priv, be16_to_cpu(port));
2142 }
2143
2144 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2145 struct sk_buff *skb,
2146 netdev_features_t features)
2147 {
2148 struct udphdr *udph;
2149 u16 proto;
2150 u16 port = 0;
2151
2152 switch (vlan_get_protocol(skb)) {
2153 case htons(ETH_P_IP):
2154 proto = ip_hdr(skb)->protocol;
2155 break;
2156 case htons(ETH_P_IPV6):
2157 proto = ipv6_hdr(skb)->nexthdr;
2158 break;
2159 default:
2160 goto out;
2161 }
2162
2163 if (proto == IPPROTO_UDP) {
2164 udph = udp_hdr(skb);
2165 port = be16_to_cpu(udph->dest);
2166 }
2167
2168 /* Verify if UDP port is being offloaded by HW */
2169 if (port && mlx5e_vxlan_lookup_port(priv, port))
2170 return features;
2171
2172 out:
2173 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2174 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2175 }
2176
2177 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2178 struct net_device *netdev,
2179 netdev_features_t features)
2180 {
2181 struct mlx5e_priv *priv = netdev_priv(netdev);
2182
2183 features = vlan_features_check(skb, features);
2184 features = vxlan_features_check(skb, features);
2185
2186 /* Validate if the tunneled packet is being offloaded by HW */
2187 if (skb->encapsulation &&
2188 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2189 return mlx5e_vxlan_features_check(priv, skb, features);
2190
2191 return features;
2192 }
2193
2194 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2195 .ndo_open = mlx5e_open,
2196 .ndo_stop = mlx5e_close,
2197 .ndo_start_xmit = mlx5e_xmit,
2198 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2199 .ndo_select_queue = mlx5e_select_queue,
2200 .ndo_get_stats64 = mlx5e_get_stats,
2201 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2202 .ndo_set_mac_address = mlx5e_set_mac,
2203 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2204 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2205 .ndo_set_features = mlx5e_set_features,
2206 .ndo_change_mtu = mlx5e_change_mtu,
2207 .ndo_do_ioctl = mlx5e_ioctl,
2208 };
2209
2210 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2211 .ndo_open = mlx5e_open,
2212 .ndo_stop = mlx5e_close,
2213 .ndo_start_xmit = mlx5e_xmit,
2214 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2215 .ndo_select_queue = mlx5e_select_queue,
2216 .ndo_get_stats64 = mlx5e_get_stats,
2217 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2218 .ndo_set_mac_address = mlx5e_set_mac,
2219 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2220 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2221 .ndo_set_features = mlx5e_set_features,
2222 .ndo_change_mtu = mlx5e_change_mtu,
2223 .ndo_do_ioctl = mlx5e_ioctl,
2224 .ndo_add_vxlan_port = mlx5e_add_vxlan_port,
2225 .ndo_del_vxlan_port = mlx5e_del_vxlan_port,
2226 .ndo_features_check = mlx5e_features_check,
2227 .ndo_set_vf_mac = mlx5e_set_vf_mac,
2228 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
2229 .ndo_get_vf_config = mlx5e_get_vf_config,
2230 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
2231 .ndo_get_vf_stats = mlx5e_get_vf_stats,
2232 };
2233
2234 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2235 {
2236 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2237 return -ENOTSUPP;
2238 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2239 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2240 !MLX5_CAP_ETH(mdev, csum_cap) ||
2241 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2242 !MLX5_CAP_ETH(mdev, vlan_cap) ||
2243 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2244 MLX5_CAP_FLOWTABLE(mdev,
2245 flow_table_properties_nic_receive.max_ft_level)
2246 < 3) {
2247 mlx5_core_warn(mdev,
2248 "Not creating net device, some required device capabilities are missing\n");
2249 return -ENOTSUPP;
2250 }
2251 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2252 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2253 if (!MLX5_CAP_GEN(mdev, cq_moderation))
2254 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2255
2256 return 0;
2257 }
2258
2259 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2260 {
2261 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2262
2263 return bf_buf_size -
2264 sizeof(struct mlx5e_tx_wqe) +
2265 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2266 }
2267
2268 #ifdef CONFIG_MLX5_CORE_EN_DCB
2269 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2270 {
2271 int i;
2272
2273 priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2274 for (i = 0; i < priv->params.ets.ets_cap; i++) {
2275 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2276 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2277 priv->params.ets.prio_tc[i] = i;
2278 }
2279
2280 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2281 priv->params.ets.prio_tc[0] = 1;
2282 priv->params.ets.prio_tc[1] = 0;
2283 }
2284 #endif
2285
2286 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
2287 int num_channels)
2288 {
2289 int i;
2290
2291 for (i = 0; i < len; i++)
2292 indirection_rqt[i] = i % num_channels;
2293 }
2294
2295 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2296 struct net_device *netdev,
2297 int num_channels)
2298 {
2299 struct mlx5e_priv *priv = netdev_priv(netdev);
2300
2301 priv->params.log_sq_size =
2302 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2303 priv->params.log_rq_size =
2304 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2305 priv->params.rx_cq_moderation_usec =
2306 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2307 priv->params.rx_cq_moderation_pkts =
2308 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2309 priv->params.tx_cq_moderation_usec =
2310 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2311 priv->params.tx_cq_moderation_pkts =
2312 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2313 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
2314 priv->params.min_rx_wqes =
2315 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2316 priv->params.num_tc = 1;
2317 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
2318
2319 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2320 sizeof(priv->params.toeplitz_hash_key));
2321
2322 mlx5e_build_default_indir_rqt(priv->params.indirection_rqt,
2323 MLX5E_INDIR_RQT_SIZE, num_channels);
2324
2325 priv->params.lro_wqe_sz =
2326 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2327
2328 priv->mdev = mdev;
2329 priv->netdev = netdev;
2330 priv->params.num_channels = num_channels;
2331
2332 #ifdef CONFIG_MLX5_CORE_EN_DCB
2333 mlx5e_ets_init(priv);
2334 #endif
2335
2336 mutex_init(&priv->state_lock);
2337
2338 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2339 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2340 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2341 }
2342
2343 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2344 {
2345 struct mlx5e_priv *priv = netdev_priv(netdev);
2346
2347 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2348 if (is_zero_ether_addr(netdev->dev_addr) &&
2349 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2350 eth_hw_addr_random(netdev);
2351 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2352 }
2353 }
2354
2355 static void mlx5e_build_netdev(struct net_device *netdev)
2356 {
2357 struct mlx5e_priv *priv = netdev_priv(netdev);
2358 struct mlx5_core_dev *mdev = priv->mdev;
2359
2360 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2361
2362 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2363 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2364 #ifdef CONFIG_MLX5_CORE_EN_DCB
2365 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2366 #endif
2367 } else {
2368 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
2369 }
2370
2371 netdev->watchdog_timeo = 15 * HZ;
2372
2373 netdev->ethtool_ops = &mlx5e_ethtool_ops;
2374
2375 netdev->vlan_features |= NETIF_F_SG;
2376 netdev->vlan_features |= NETIF_F_IP_CSUM;
2377 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
2378 netdev->vlan_features |= NETIF_F_GRO;
2379 netdev->vlan_features |= NETIF_F_TSO;
2380 netdev->vlan_features |= NETIF_F_TSO6;
2381 netdev->vlan_features |= NETIF_F_RXCSUM;
2382 netdev->vlan_features |= NETIF_F_RXHASH;
2383
2384 if (!!MLX5_CAP_ETH(mdev, lro_cap))
2385 netdev->vlan_features |= NETIF_F_LRO;
2386
2387 netdev->hw_features = netdev->vlan_features;
2388 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
2389 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2390 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2391
2392 if (mlx5e_vxlan_allowed(mdev)) {
2393 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL;
2394 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2395 netdev->hw_enc_features |= NETIF_F_RXCSUM;
2396 netdev->hw_enc_features |= NETIF_F_TSO;
2397 netdev->hw_enc_features |= NETIF_F_TSO6;
2398 netdev->hw_enc_features |= NETIF_F_RXHASH;
2399 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2400 }
2401
2402 netdev->features = netdev->hw_features;
2403 if (!priv->params.lro_en)
2404 netdev->features &= ~NETIF_F_LRO;
2405
2406 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
2407 if (FT_CAP(flow_modify_en) &&
2408 FT_CAP(modify_root) &&
2409 FT_CAP(identified_miss_table_mode) &&
2410 FT_CAP(flow_table_modify))
2411 priv->netdev->hw_features |= NETIF_F_HW_TC;
2412
2413 netdev->features |= NETIF_F_HIGHDMA;
2414
2415 netdev->priv_flags |= IFF_UNICAST_FLT;
2416
2417 mlx5e_set_netdev_dev_addr(netdev);
2418 }
2419
2420 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2421 struct mlx5_core_mkey *mkey)
2422 {
2423 struct mlx5_core_dev *mdev = priv->mdev;
2424 struct mlx5_create_mkey_mbox_in *in;
2425 int err;
2426
2427 in = mlx5_vzalloc(sizeof(*in));
2428 if (!in)
2429 return -ENOMEM;
2430
2431 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2432 MLX5_PERM_LOCAL_READ |
2433 MLX5_ACCESS_MODE_PA;
2434 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2435 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2436
2437 err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
2438 NULL);
2439
2440 kvfree(in);
2441
2442 return err;
2443 }
2444
2445 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2446 {
2447 struct net_device *netdev;
2448 struct mlx5e_priv *priv;
2449 int nch = mlx5e_get_max_num_channels(mdev);
2450 int err;
2451
2452 if (mlx5e_check_required_hca_cap(mdev))
2453 return NULL;
2454
2455 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
2456 nch * MLX5E_MAX_NUM_TC,
2457 nch);
2458 if (!netdev) {
2459 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2460 return NULL;
2461 }
2462
2463 mlx5e_build_netdev_priv(mdev, netdev, nch);
2464 mlx5e_build_netdev(netdev);
2465
2466 netif_carrier_off(netdev);
2467
2468 priv = netdev_priv(netdev);
2469
2470 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
2471 if (err) {
2472 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
2473 goto err_free_netdev;
2474 }
2475
2476 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2477 if (err) {
2478 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
2479 goto err_unmap_free_uar;
2480 }
2481
2482 err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
2483 if (err) {
2484 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
2485 goto err_dealloc_pd;
2486 }
2487
2488 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
2489 if (err) {
2490 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
2491 goto err_dealloc_transport_domain;
2492 }
2493
2494 err = mlx5e_create_tises(priv);
2495 if (err) {
2496 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
2497 goto err_destroy_mkey;
2498 }
2499
2500 err = mlx5e_open_drop_rq(priv);
2501 if (err) {
2502 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
2503 goto err_destroy_tises;
2504 }
2505
2506 err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT);
2507 if (err) {
2508 mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err);
2509 goto err_close_drop_rq;
2510 }
2511
2512 err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2513 if (err) {
2514 mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err);
2515 goto err_destroy_rqt_indir;
2516 }
2517
2518 err = mlx5e_create_tirs(priv);
2519 if (err) {
2520 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
2521 goto err_destroy_rqt_single;
2522 }
2523
2524 err = mlx5e_create_flow_tables(priv);
2525 if (err) {
2526 mlx5_core_warn(mdev, "create flow tables failed, %d\n", err);
2527 goto err_destroy_tirs;
2528 }
2529
2530 mlx5e_init_eth_addr(priv);
2531
2532 mlx5e_vxlan_init(priv);
2533
2534 err = mlx5e_tc_init(priv);
2535 if (err)
2536 goto err_destroy_flow_tables;
2537
2538 #ifdef CONFIG_MLX5_CORE_EN_DCB
2539 mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
2540 #endif
2541
2542 err = register_netdev(netdev);
2543 if (err) {
2544 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
2545 goto err_tc_cleanup;
2546 }
2547
2548 if (mlx5e_vxlan_allowed(mdev))
2549 vxlan_get_rx_port(netdev);
2550
2551 mlx5e_enable_async_events(priv);
2552 schedule_work(&priv->set_rx_mode_work);
2553
2554 return priv;
2555
2556 err_tc_cleanup:
2557 mlx5e_tc_cleanup(priv);
2558
2559 err_destroy_flow_tables:
2560 mlx5e_destroy_flow_tables(priv);
2561
2562 err_destroy_tirs:
2563 mlx5e_destroy_tirs(priv);
2564
2565 err_destroy_rqt_single:
2566 mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2567
2568 err_destroy_rqt_indir:
2569 mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2570
2571 err_close_drop_rq:
2572 mlx5e_close_drop_rq(priv);
2573
2574 err_destroy_tises:
2575 mlx5e_destroy_tises(priv);
2576
2577 err_destroy_mkey:
2578 mlx5_core_destroy_mkey(mdev, &priv->mkey);
2579
2580 err_dealloc_transport_domain:
2581 mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
2582
2583 err_dealloc_pd:
2584 mlx5_core_dealloc_pd(mdev, priv->pdn);
2585
2586 err_unmap_free_uar:
2587 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2588
2589 err_free_netdev:
2590 free_netdev(netdev);
2591
2592 return NULL;
2593 }
2594
2595 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2596 {
2597 struct mlx5e_priv *priv = vpriv;
2598 struct net_device *netdev = priv->netdev;
2599
2600 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
2601
2602 schedule_work(&priv->set_rx_mode_work);
2603 mlx5e_disable_async_events(priv);
2604 flush_scheduled_work();
2605 unregister_netdev(netdev);
2606 mlx5e_tc_cleanup(priv);
2607 mlx5e_vxlan_cleanup(priv);
2608 mlx5e_destroy_flow_tables(priv);
2609 mlx5e_destroy_tirs(priv);
2610 mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2611 mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2612 mlx5e_close_drop_rq(priv);
2613 mlx5e_destroy_tises(priv);
2614 mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
2615 mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
2616 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2617 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
2618 free_netdev(netdev);
2619 }
2620
2621 static void *mlx5e_get_netdev(void *vpriv)
2622 {
2623 struct mlx5e_priv *priv = vpriv;
2624
2625 return priv->netdev;
2626 }
2627
2628 static struct mlx5_interface mlx5e_interface = {
2629 .add = mlx5e_create_netdev,
2630 .remove = mlx5e_destroy_netdev,
2631 .event = mlx5e_async_event,
2632 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
2633 .get_dev = mlx5e_get_netdev,
2634 };
2635
2636 void mlx5e_init(void)
2637 {
2638 mlx5_register_interface(&mlx5e_interface);
2639 }
2640
2641 void mlx5e_cleanup(void)
2642 {
2643 mlx5_unregister_interface(&mlx5e_interface);
2644 }
Linux kernel - Deliverables
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