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sh_eth: remove EDMAC_BIG_ENDIAN
[deliverable/linux.git] / drivers / net / ethernet / renesas / sh_eth.c
1 /* SuperH Ethernet device driver
2 *
3 * Copyright (C) 2014 Renesas Electronics Corporation
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2014 Cogent Embedded, Inc.
7 * Copyright (C) 2014 Codethink Limited
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 */
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/etherdevice.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/mdio-bitbang.h>
31 #include <linux/netdevice.h>
32 #include <linux/of.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_net.h>
36 #include <linux/phy.h>
37 #include <linux/cache.h>
38 #include <linux/io.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/slab.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <linux/clk.h>
44 #include <linux/sh_eth.h>
45 #include <linux/of_mdio.h>
46
47 #include "sh_eth.h"
48
49 #define SH_ETH_DEF_MSG_ENABLE \
50 (NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_RX_ERR| \
53 NETIF_MSG_TX_ERR)
54
55 #define SH_ETH_OFFSET_INVALID ((u16)~0)
56
57 #define SH_ETH_OFFSET_DEFAULTS \
58 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
59
60 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
61 SH_ETH_OFFSET_DEFAULTS,
62
63 [EDSR] = 0x0000,
64 [EDMR] = 0x0400,
65 [EDTRR] = 0x0408,
66 [EDRRR] = 0x0410,
67 [EESR] = 0x0428,
68 [EESIPR] = 0x0430,
69 [TDLAR] = 0x0010,
70 [TDFAR] = 0x0014,
71 [TDFXR] = 0x0018,
72 [TDFFR] = 0x001c,
73 [RDLAR] = 0x0030,
74 [RDFAR] = 0x0034,
75 [RDFXR] = 0x0038,
76 [RDFFR] = 0x003c,
77 [TRSCER] = 0x0438,
78 [RMFCR] = 0x0440,
79 [TFTR] = 0x0448,
80 [FDR] = 0x0450,
81 [RMCR] = 0x0458,
82 [RPADIR] = 0x0460,
83 [FCFTR] = 0x0468,
84 [CSMR] = 0x04E4,
85
86 [ECMR] = 0x0500,
87 [ECSR] = 0x0510,
88 [ECSIPR] = 0x0518,
89 [PIR] = 0x0520,
90 [PSR] = 0x0528,
91 [PIPR] = 0x052c,
92 [RFLR] = 0x0508,
93 [APR] = 0x0554,
94 [MPR] = 0x0558,
95 [PFTCR] = 0x055c,
96 [PFRCR] = 0x0560,
97 [TPAUSER] = 0x0564,
98 [GECMR] = 0x05b0,
99 [BCULR] = 0x05b4,
100 [MAHR] = 0x05c0,
101 [MALR] = 0x05c8,
102 [TROCR] = 0x0700,
103 [CDCR] = 0x0708,
104 [LCCR] = 0x0710,
105 [CEFCR] = 0x0740,
106 [FRECR] = 0x0748,
107 [TSFRCR] = 0x0750,
108 [TLFRCR] = 0x0758,
109 [RFCR] = 0x0760,
110 [CERCR] = 0x0768,
111 [CEECR] = 0x0770,
112 [MAFCR] = 0x0778,
113 [RMII_MII] = 0x0790,
114
115 [ARSTR] = 0x0000,
116 [TSU_CTRST] = 0x0004,
117 [TSU_FWEN0] = 0x0010,
118 [TSU_FWEN1] = 0x0014,
119 [TSU_FCM] = 0x0018,
120 [TSU_BSYSL0] = 0x0020,
121 [TSU_BSYSL1] = 0x0024,
122 [TSU_PRISL0] = 0x0028,
123 [TSU_PRISL1] = 0x002c,
124 [TSU_FWSL0] = 0x0030,
125 [TSU_FWSL1] = 0x0034,
126 [TSU_FWSLC] = 0x0038,
127 [TSU_QTAG0] = 0x0040,
128 [TSU_QTAG1] = 0x0044,
129 [TSU_FWSR] = 0x0050,
130 [TSU_FWINMK] = 0x0054,
131 [TSU_ADQT0] = 0x0048,
132 [TSU_ADQT1] = 0x004c,
133 [TSU_VTAG0] = 0x0058,
134 [TSU_VTAG1] = 0x005c,
135 [TSU_ADSBSY] = 0x0060,
136 [TSU_TEN] = 0x0064,
137 [TSU_POST1] = 0x0070,
138 [TSU_POST2] = 0x0074,
139 [TSU_POST3] = 0x0078,
140 [TSU_POST4] = 0x007c,
141 [TSU_ADRH0] = 0x0100,
142
143 [TXNLCR0] = 0x0080,
144 [TXALCR0] = 0x0084,
145 [RXNLCR0] = 0x0088,
146 [RXALCR0] = 0x008c,
147 [FWNLCR0] = 0x0090,
148 [FWALCR0] = 0x0094,
149 [TXNLCR1] = 0x00a0,
150 [TXALCR1] = 0x00a0,
151 [RXNLCR1] = 0x00a8,
152 [RXALCR1] = 0x00ac,
153 [FWNLCR1] = 0x00b0,
154 [FWALCR1] = 0x00b4,
155 };
156
157 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
158 SH_ETH_OFFSET_DEFAULTS,
159
160 [EDSR] = 0x0000,
161 [EDMR] = 0x0400,
162 [EDTRR] = 0x0408,
163 [EDRRR] = 0x0410,
164 [EESR] = 0x0428,
165 [EESIPR] = 0x0430,
166 [TDLAR] = 0x0010,
167 [TDFAR] = 0x0014,
168 [TDFXR] = 0x0018,
169 [TDFFR] = 0x001c,
170 [RDLAR] = 0x0030,
171 [RDFAR] = 0x0034,
172 [RDFXR] = 0x0038,
173 [RDFFR] = 0x003c,
174 [TRSCER] = 0x0438,
175 [RMFCR] = 0x0440,
176 [TFTR] = 0x0448,
177 [FDR] = 0x0450,
178 [RMCR] = 0x0458,
179 [RPADIR] = 0x0460,
180 [FCFTR] = 0x0468,
181 [CSMR] = 0x04E4,
182
183 [ECMR] = 0x0500,
184 [RFLR] = 0x0508,
185 [ECSR] = 0x0510,
186 [ECSIPR] = 0x0518,
187 [PIR] = 0x0520,
188 [APR] = 0x0554,
189 [MPR] = 0x0558,
190 [PFTCR] = 0x055c,
191 [PFRCR] = 0x0560,
192 [TPAUSER] = 0x0564,
193 [MAHR] = 0x05c0,
194 [MALR] = 0x05c8,
195 [CEFCR] = 0x0740,
196 [FRECR] = 0x0748,
197 [TSFRCR] = 0x0750,
198 [TLFRCR] = 0x0758,
199 [RFCR] = 0x0760,
200 [MAFCR] = 0x0778,
201
202 [ARSTR] = 0x0000,
203 [TSU_CTRST] = 0x0004,
204 [TSU_VTAG0] = 0x0058,
205 [TSU_ADSBSY] = 0x0060,
206 [TSU_TEN] = 0x0064,
207 [TSU_ADRH0] = 0x0100,
208
209 [TXNLCR0] = 0x0080,
210 [TXALCR0] = 0x0084,
211 [RXNLCR0] = 0x0088,
212 [RXALCR0] = 0x008C,
213 };
214
215 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
216 SH_ETH_OFFSET_DEFAULTS,
217
218 [ECMR] = 0x0300,
219 [RFLR] = 0x0308,
220 [ECSR] = 0x0310,
221 [ECSIPR] = 0x0318,
222 [PIR] = 0x0320,
223 [PSR] = 0x0328,
224 [RDMLR] = 0x0340,
225 [IPGR] = 0x0350,
226 [APR] = 0x0354,
227 [MPR] = 0x0358,
228 [RFCF] = 0x0360,
229 [TPAUSER] = 0x0364,
230 [TPAUSECR] = 0x0368,
231 [MAHR] = 0x03c0,
232 [MALR] = 0x03c8,
233 [TROCR] = 0x03d0,
234 [CDCR] = 0x03d4,
235 [LCCR] = 0x03d8,
236 [CNDCR] = 0x03dc,
237 [CEFCR] = 0x03e4,
238 [FRECR] = 0x03e8,
239 [TSFRCR] = 0x03ec,
240 [TLFRCR] = 0x03f0,
241 [RFCR] = 0x03f4,
242 [MAFCR] = 0x03f8,
243
244 [EDMR] = 0x0200,
245 [EDTRR] = 0x0208,
246 [EDRRR] = 0x0210,
247 [TDLAR] = 0x0218,
248 [RDLAR] = 0x0220,
249 [EESR] = 0x0228,
250 [EESIPR] = 0x0230,
251 [TRSCER] = 0x0238,
252 [RMFCR] = 0x0240,
253 [TFTR] = 0x0248,
254 [FDR] = 0x0250,
255 [RMCR] = 0x0258,
256 [TFUCR] = 0x0264,
257 [RFOCR] = 0x0268,
258 [RMIIMODE] = 0x026c,
259 [FCFTR] = 0x0270,
260 [TRIMD] = 0x027c,
261 };
262
263 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
264 SH_ETH_OFFSET_DEFAULTS,
265
266 [ECMR] = 0x0100,
267 [RFLR] = 0x0108,
268 [ECSR] = 0x0110,
269 [ECSIPR] = 0x0118,
270 [PIR] = 0x0120,
271 [PSR] = 0x0128,
272 [RDMLR] = 0x0140,
273 [IPGR] = 0x0150,
274 [APR] = 0x0154,
275 [MPR] = 0x0158,
276 [TPAUSER] = 0x0164,
277 [RFCF] = 0x0160,
278 [TPAUSECR] = 0x0168,
279 [BCFRR] = 0x016c,
280 [MAHR] = 0x01c0,
281 [MALR] = 0x01c8,
282 [TROCR] = 0x01d0,
283 [CDCR] = 0x01d4,
284 [LCCR] = 0x01d8,
285 [CNDCR] = 0x01dc,
286 [CEFCR] = 0x01e4,
287 [FRECR] = 0x01e8,
288 [TSFRCR] = 0x01ec,
289 [TLFRCR] = 0x01f0,
290 [RFCR] = 0x01f4,
291 [MAFCR] = 0x01f8,
292 [RTRATE] = 0x01fc,
293
294 [EDMR] = 0x0000,
295 [EDTRR] = 0x0008,
296 [EDRRR] = 0x0010,
297 [TDLAR] = 0x0018,
298 [RDLAR] = 0x0020,
299 [EESR] = 0x0028,
300 [EESIPR] = 0x0030,
301 [TRSCER] = 0x0038,
302 [RMFCR] = 0x0040,
303 [TFTR] = 0x0048,
304 [FDR] = 0x0050,
305 [RMCR] = 0x0058,
306 [TFUCR] = 0x0064,
307 [RFOCR] = 0x0068,
308 [FCFTR] = 0x0070,
309 [RPADIR] = 0x0078,
310 [TRIMD] = 0x007c,
311 [RBWAR] = 0x00c8,
312 [RDFAR] = 0x00cc,
313 [TBRAR] = 0x00d4,
314 [TDFAR] = 0x00d8,
315 };
316
317 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
318 SH_ETH_OFFSET_DEFAULTS,
319
320 [EDMR] = 0x0000,
321 [EDTRR] = 0x0004,
322 [EDRRR] = 0x0008,
323 [TDLAR] = 0x000c,
324 [RDLAR] = 0x0010,
325 [EESR] = 0x0014,
326 [EESIPR] = 0x0018,
327 [TRSCER] = 0x001c,
328 [RMFCR] = 0x0020,
329 [TFTR] = 0x0024,
330 [FDR] = 0x0028,
331 [RMCR] = 0x002c,
332 [EDOCR] = 0x0030,
333 [FCFTR] = 0x0034,
334 [RPADIR] = 0x0038,
335 [TRIMD] = 0x003c,
336 [RBWAR] = 0x0040,
337 [RDFAR] = 0x0044,
338 [TBRAR] = 0x004c,
339 [TDFAR] = 0x0050,
340
341 [ECMR] = 0x0160,
342 [ECSR] = 0x0164,
343 [ECSIPR] = 0x0168,
344 [PIR] = 0x016c,
345 [MAHR] = 0x0170,
346 [MALR] = 0x0174,
347 [RFLR] = 0x0178,
348 [PSR] = 0x017c,
349 [TROCR] = 0x0180,
350 [CDCR] = 0x0184,
351 [LCCR] = 0x0188,
352 [CNDCR] = 0x018c,
353 [CEFCR] = 0x0194,
354 [FRECR] = 0x0198,
355 [TSFRCR] = 0x019c,
356 [TLFRCR] = 0x01a0,
357 [RFCR] = 0x01a4,
358 [MAFCR] = 0x01a8,
359 [IPGR] = 0x01b4,
360 [APR] = 0x01b8,
361 [MPR] = 0x01bc,
362 [TPAUSER] = 0x01c4,
363 [BCFR] = 0x01cc,
364
365 [ARSTR] = 0x0000,
366 [TSU_CTRST] = 0x0004,
367 [TSU_FWEN0] = 0x0010,
368 [TSU_FWEN1] = 0x0014,
369 [TSU_FCM] = 0x0018,
370 [TSU_BSYSL0] = 0x0020,
371 [TSU_BSYSL1] = 0x0024,
372 [TSU_PRISL0] = 0x0028,
373 [TSU_PRISL1] = 0x002c,
374 [TSU_FWSL0] = 0x0030,
375 [TSU_FWSL1] = 0x0034,
376 [TSU_FWSLC] = 0x0038,
377 [TSU_QTAGM0] = 0x0040,
378 [TSU_QTAGM1] = 0x0044,
379 [TSU_ADQT0] = 0x0048,
380 [TSU_ADQT1] = 0x004c,
381 [TSU_FWSR] = 0x0050,
382 [TSU_FWINMK] = 0x0054,
383 [TSU_ADSBSY] = 0x0060,
384 [TSU_TEN] = 0x0064,
385 [TSU_POST1] = 0x0070,
386 [TSU_POST2] = 0x0074,
387 [TSU_POST3] = 0x0078,
388 [TSU_POST4] = 0x007c,
389
390 [TXNLCR0] = 0x0080,
391 [TXALCR0] = 0x0084,
392 [RXNLCR0] = 0x0088,
393 [RXALCR0] = 0x008c,
394 [FWNLCR0] = 0x0090,
395 [FWALCR0] = 0x0094,
396 [TXNLCR1] = 0x00a0,
397 [TXALCR1] = 0x00a0,
398 [RXNLCR1] = 0x00a8,
399 [RXALCR1] = 0x00ac,
400 [FWNLCR1] = 0x00b0,
401 [FWALCR1] = 0x00b4,
402
403 [TSU_ADRH0] = 0x0100,
404 };
405
406 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
407 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
408
409 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
410 {
411 struct sh_eth_private *mdp = netdev_priv(ndev);
412 u16 offset = mdp->reg_offset[enum_index];
413
414 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
415 return;
416
417 iowrite32(data, mdp->addr + offset);
418 }
419
420 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
421 {
422 struct sh_eth_private *mdp = netdev_priv(ndev);
423 u16 offset = mdp->reg_offset[enum_index];
424
425 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
426 return ~0U;
427
428 return ioread32(mdp->addr + offset);
429 }
430
431 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
432 {
433 return mdp->reg_offset == sh_eth_offset_gigabit;
434 }
435
436 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
437 {
438 return mdp->reg_offset == sh_eth_offset_fast_rz;
439 }
440
441 static void sh_eth_select_mii(struct net_device *ndev)
442 {
443 u32 value = 0x0;
444 struct sh_eth_private *mdp = netdev_priv(ndev);
445
446 switch (mdp->phy_interface) {
447 case PHY_INTERFACE_MODE_GMII:
448 value = 0x2;
449 break;
450 case PHY_INTERFACE_MODE_MII:
451 value = 0x1;
452 break;
453 case PHY_INTERFACE_MODE_RMII:
454 value = 0x0;
455 break;
456 default:
457 netdev_warn(ndev,
458 "PHY interface mode was not setup. Set to MII.\n");
459 value = 0x1;
460 break;
461 }
462
463 sh_eth_write(ndev, value, RMII_MII);
464 }
465
466 static void sh_eth_set_duplex(struct net_device *ndev)
467 {
468 struct sh_eth_private *mdp = netdev_priv(ndev);
469
470 if (mdp->duplex) /* Full */
471 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
472 else /* Half */
473 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
474 }
475
476 static void sh_eth_chip_reset(struct net_device *ndev)
477 {
478 struct sh_eth_private *mdp = netdev_priv(ndev);
479
480 /* reset device */
481 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
482 mdelay(1);
483 }
484
485 static void sh_eth_set_rate_gether(struct net_device *ndev)
486 {
487 struct sh_eth_private *mdp = netdev_priv(ndev);
488
489 switch (mdp->speed) {
490 case 10: /* 10BASE */
491 sh_eth_write(ndev, GECMR_10, GECMR);
492 break;
493 case 100:/* 100BASE */
494 sh_eth_write(ndev, GECMR_100, GECMR);
495 break;
496 case 1000: /* 1000BASE */
497 sh_eth_write(ndev, GECMR_1000, GECMR);
498 break;
499 default:
500 break;
501 }
502 }
503
504 #ifdef CONFIG_OF
505 /* R7S72100 */
506 static struct sh_eth_cpu_data r7s72100_data = {
507 .chip_reset = sh_eth_chip_reset,
508 .set_duplex = sh_eth_set_duplex,
509
510 .register_type = SH_ETH_REG_FAST_RZ,
511
512 .ecsr_value = ECSR_ICD,
513 .ecsipr_value = ECSIPR_ICDIP,
514 .eesipr_value = 0xff7f009f,
515
516 .tx_check = EESR_TC1 | EESR_FTC,
517 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
518 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
519 EESR_TDE | EESR_ECI,
520 .fdr_value = 0x0000070f,
521
522 .no_psr = 1,
523 .apr = 1,
524 .mpr = 1,
525 .tpauser = 1,
526 .hw_swap = 1,
527 .rpadir = 1,
528 .rpadir_value = 2 << 16,
529 .no_trimd = 1,
530 .no_ade = 1,
531 .hw_crc = 1,
532 .tsu = 1,
533 .shift_rd0 = 1,
534 };
535
536 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
537 {
538 struct sh_eth_private *mdp = netdev_priv(ndev);
539
540 /* reset device */
541 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
542 mdelay(1);
543
544 sh_eth_select_mii(ndev);
545 }
546
547 /* R8A7740 */
548 static struct sh_eth_cpu_data r8a7740_data = {
549 .chip_reset = sh_eth_chip_reset_r8a7740,
550 .set_duplex = sh_eth_set_duplex,
551 .set_rate = sh_eth_set_rate_gether,
552
553 .register_type = SH_ETH_REG_GIGABIT,
554
555 .ecsr_value = ECSR_ICD | ECSR_MPD,
556 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
557 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
558
559 .tx_check = EESR_TC1 | EESR_FTC,
560 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
561 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
562 EESR_TDE | EESR_ECI,
563 .fdr_value = 0x0000070f,
564
565 .apr = 1,
566 .mpr = 1,
567 .tpauser = 1,
568 .bculr = 1,
569 .hw_swap = 1,
570 .rpadir = 1,
571 .rpadir_value = 2 << 16,
572 .no_trimd = 1,
573 .no_ade = 1,
574 .tsu = 1,
575 .select_mii = 1,
576 .shift_rd0 = 1,
577 };
578
579 /* There is CPU dependent code */
580 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
581 {
582 struct sh_eth_private *mdp = netdev_priv(ndev);
583
584 switch (mdp->speed) {
585 case 10: /* 10BASE */
586 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
587 break;
588 case 100:/* 100BASE */
589 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
590 break;
591 default:
592 break;
593 }
594 }
595
596 /* R8A7778/9 */
597 static struct sh_eth_cpu_data r8a777x_data = {
598 .set_duplex = sh_eth_set_duplex,
599 .set_rate = sh_eth_set_rate_r8a777x,
600
601 .register_type = SH_ETH_REG_FAST_RCAR,
602
603 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
604 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
605 .eesipr_value = 0x01ff009f,
606
607 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
608 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
609 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
610 EESR_ECI,
611 .fdr_value = 0x00000f0f,
612
613 .apr = 1,
614 .mpr = 1,
615 .tpauser = 1,
616 .hw_swap = 1,
617 };
618
619 /* R8A7790/1 */
620 static struct sh_eth_cpu_data r8a779x_data = {
621 .set_duplex = sh_eth_set_duplex,
622 .set_rate = sh_eth_set_rate_r8a777x,
623
624 .register_type = SH_ETH_REG_FAST_RCAR,
625
626 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
627 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
628 .eesipr_value = 0x01ff009f,
629
630 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
631 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
632 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
633 EESR_ECI,
634 .fdr_value = 0x00000f0f,
635
636 .trscer_err_mask = DESC_I_RINT8,
637
638 .apr = 1,
639 .mpr = 1,
640 .tpauser = 1,
641 .hw_swap = 1,
642 .rmiimode = 1,
643 };
644 #endif /* CONFIG_OF */
645
646 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
647 {
648 struct sh_eth_private *mdp = netdev_priv(ndev);
649
650 switch (mdp->speed) {
651 case 10: /* 10BASE */
652 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
653 break;
654 case 100:/* 100BASE */
655 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
656 break;
657 default:
658 break;
659 }
660 }
661
662 /* SH7724 */
663 static struct sh_eth_cpu_data sh7724_data = {
664 .set_duplex = sh_eth_set_duplex,
665 .set_rate = sh_eth_set_rate_sh7724,
666
667 .register_type = SH_ETH_REG_FAST_SH4,
668
669 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
670 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
671 .eesipr_value = 0x01ff009f,
672
673 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
674 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
675 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
676 EESR_ECI,
677
678 .apr = 1,
679 .mpr = 1,
680 .tpauser = 1,
681 .hw_swap = 1,
682 .rpadir = 1,
683 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
684 };
685
686 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
687 {
688 struct sh_eth_private *mdp = netdev_priv(ndev);
689
690 switch (mdp->speed) {
691 case 10: /* 10BASE */
692 sh_eth_write(ndev, 0, RTRATE);
693 break;
694 case 100:/* 100BASE */
695 sh_eth_write(ndev, 1, RTRATE);
696 break;
697 default:
698 break;
699 }
700 }
701
702 /* SH7757 */
703 static struct sh_eth_cpu_data sh7757_data = {
704 .set_duplex = sh_eth_set_duplex,
705 .set_rate = sh_eth_set_rate_sh7757,
706
707 .register_type = SH_ETH_REG_FAST_SH4,
708
709 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
710
711 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
712 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
713 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
714 EESR_ECI,
715
716 .irq_flags = IRQF_SHARED,
717 .apr = 1,
718 .mpr = 1,
719 .tpauser = 1,
720 .hw_swap = 1,
721 .no_ade = 1,
722 .rpadir = 1,
723 .rpadir_value = 2 << 16,
724 .rtrate = 1,
725 };
726
727 #define SH_GIGA_ETH_BASE 0xfee00000UL
728 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
729 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
730 static void sh_eth_chip_reset_giga(struct net_device *ndev)
731 {
732 int i;
733 u32 mahr[2], malr[2];
734
735 /* save MAHR and MALR */
736 for (i = 0; i < 2; i++) {
737 malr[i] = ioread32((void *)GIGA_MALR(i));
738 mahr[i] = ioread32((void *)GIGA_MAHR(i));
739 }
740
741 /* reset device */
742 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
743 mdelay(1);
744
745 /* restore MAHR and MALR */
746 for (i = 0; i < 2; i++) {
747 iowrite32(malr[i], (void *)GIGA_MALR(i));
748 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
749 }
750 }
751
752 static void sh_eth_set_rate_giga(struct net_device *ndev)
753 {
754 struct sh_eth_private *mdp = netdev_priv(ndev);
755
756 switch (mdp->speed) {
757 case 10: /* 10BASE */
758 sh_eth_write(ndev, 0x00000000, GECMR);
759 break;
760 case 100:/* 100BASE */
761 sh_eth_write(ndev, 0x00000010, GECMR);
762 break;
763 case 1000: /* 1000BASE */
764 sh_eth_write(ndev, 0x00000020, GECMR);
765 break;
766 default:
767 break;
768 }
769 }
770
771 /* SH7757(GETHERC) */
772 static struct sh_eth_cpu_data sh7757_data_giga = {
773 .chip_reset = sh_eth_chip_reset_giga,
774 .set_duplex = sh_eth_set_duplex,
775 .set_rate = sh_eth_set_rate_giga,
776
777 .register_type = SH_ETH_REG_GIGABIT,
778
779 .ecsr_value = ECSR_ICD | ECSR_MPD,
780 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
781 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
782
783 .tx_check = EESR_TC1 | EESR_FTC,
784 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
785 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
786 EESR_TDE | EESR_ECI,
787 .fdr_value = 0x0000072f,
788
789 .irq_flags = IRQF_SHARED,
790 .apr = 1,
791 .mpr = 1,
792 .tpauser = 1,
793 .bculr = 1,
794 .hw_swap = 1,
795 .rpadir = 1,
796 .rpadir_value = 2 << 16,
797 .no_trimd = 1,
798 .no_ade = 1,
799 .tsu = 1,
800 };
801
802 /* SH7734 */
803 static struct sh_eth_cpu_data sh7734_data = {
804 .chip_reset = sh_eth_chip_reset,
805 .set_duplex = sh_eth_set_duplex,
806 .set_rate = sh_eth_set_rate_gether,
807
808 .register_type = SH_ETH_REG_GIGABIT,
809
810 .ecsr_value = ECSR_ICD | ECSR_MPD,
811 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
812 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
813
814 .tx_check = EESR_TC1 | EESR_FTC,
815 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
816 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
817 EESR_TDE | EESR_ECI,
818
819 .apr = 1,
820 .mpr = 1,
821 .tpauser = 1,
822 .bculr = 1,
823 .hw_swap = 1,
824 .no_trimd = 1,
825 .no_ade = 1,
826 .tsu = 1,
827 .hw_crc = 1,
828 .select_mii = 1,
829 };
830
831 /* SH7763 */
832 static struct sh_eth_cpu_data sh7763_data = {
833 .chip_reset = sh_eth_chip_reset,
834 .set_duplex = sh_eth_set_duplex,
835 .set_rate = sh_eth_set_rate_gether,
836
837 .register_type = SH_ETH_REG_GIGABIT,
838
839 .ecsr_value = ECSR_ICD | ECSR_MPD,
840 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
841 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
842
843 .tx_check = EESR_TC1 | EESR_FTC,
844 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
845 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
846 EESR_ECI,
847
848 .apr = 1,
849 .mpr = 1,
850 .tpauser = 1,
851 .bculr = 1,
852 .hw_swap = 1,
853 .no_trimd = 1,
854 .no_ade = 1,
855 .tsu = 1,
856 .irq_flags = IRQF_SHARED,
857 };
858
859 static struct sh_eth_cpu_data sh7619_data = {
860 .register_type = SH_ETH_REG_FAST_SH3_SH2,
861
862 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
863
864 .apr = 1,
865 .mpr = 1,
866 .tpauser = 1,
867 .hw_swap = 1,
868 };
869
870 static struct sh_eth_cpu_data sh771x_data = {
871 .register_type = SH_ETH_REG_FAST_SH3_SH2,
872
873 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
874 .tsu = 1,
875 };
876
877 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
878 {
879 if (!cd->ecsr_value)
880 cd->ecsr_value = DEFAULT_ECSR_INIT;
881
882 if (!cd->ecsipr_value)
883 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
884
885 if (!cd->fcftr_value)
886 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
887 DEFAULT_FIFO_F_D_RFD;
888
889 if (!cd->fdr_value)
890 cd->fdr_value = DEFAULT_FDR_INIT;
891
892 if (!cd->tx_check)
893 cd->tx_check = DEFAULT_TX_CHECK;
894
895 if (!cd->eesr_err_check)
896 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
897
898 if (!cd->trscer_err_mask)
899 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
900 }
901
902 static int sh_eth_check_reset(struct net_device *ndev)
903 {
904 int ret = 0;
905 int cnt = 100;
906
907 while (cnt > 0) {
908 if (!(sh_eth_read(ndev, EDMR) & 0x3))
909 break;
910 mdelay(1);
911 cnt--;
912 }
913 if (cnt <= 0) {
914 netdev_err(ndev, "Device reset failed\n");
915 ret = -ETIMEDOUT;
916 }
917 return ret;
918 }
919
920 static int sh_eth_reset(struct net_device *ndev)
921 {
922 struct sh_eth_private *mdp = netdev_priv(ndev);
923 int ret = 0;
924
925 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
926 sh_eth_write(ndev, EDSR_ENALL, EDSR);
927 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
928 EDMR);
929
930 ret = sh_eth_check_reset(ndev);
931 if (ret)
932 return ret;
933
934 /* Table Init */
935 sh_eth_write(ndev, 0x0, TDLAR);
936 sh_eth_write(ndev, 0x0, TDFAR);
937 sh_eth_write(ndev, 0x0, TDFXR);
938 sh_eth_write(ndev, 0x0, TDFFR);
939 sh_eth_write(ndev, 0x0, RDLAR);
940 sh_eth_write(ndev, 0x0, RDFAR);
941 sh_eth_write(ndev, 0x0, RDFXR);
942 sh_eth_write(ndev, 0x0, RDFFR);
943
944 /* Reset HW CRC register */
945 if (mdp->cd->hw_crc)
946 sh_eth_write(ndev, 0x0, CSMR);
947
948 /* Select MII mode */
949 if (mdp->cd->select_mii)
950 sh_eth_select_mii(ndev);
951 } else {
952 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
953 EDMR);
954 mdelay(3);
955 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
956 EDMR);
957 }
958
959 return ret;
960 }
961
962 static void sh_eth_set_receive_align(struct sk_buff *skb)
963 {
964 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
965
966 if (reserve)
967 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
968 }
969
970
971 /* CPU <-> EDMAC endian convert */
972 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
973 {
974 return cpu_to_le32(x);
975 }
976
977 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
978 {
979 return le32_to_cpu(x);
980 }
981
982 /* Program the hardware MAC address from dev->dev_addr. */
983 static void update_mac_address(struct net_device *ndev)
984 {
985 sh_eth_write(ndev,
986 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
987 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
988 sh_eth_write(ndev,
989 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
990 }
991
992 /* Get MAC address from SuperH MAC address register
993 *
994 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
995 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
996 * When you want use this device, you must set MAC address in bootloader.
997 *
998 */
999 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
1000 {
1001 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
1002 memcpy(ndev->dev_addr, mac, ETH_ALEN);
1003 } else {
1004 u32 mahr = sh_eth_read(ndev, MAHR);
1005 u32 malr = sh_eth_read(ndev, MALR);
1006
1007 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
1008 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
1009 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
1010 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
1011 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
1012 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
1013 }
1014 }
1015
1016 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
1017 {
1018 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
1019 return EDTRR_TRNS_GETHER;
1020 else
1021 return EDTRR_TRNS_ETHER;
1022 }
1023
1024 struct bb_info {
1025 void (*set_gate)(void *addr);
1026 struct mdiobb_ctrl ctrl;
1027 void *addr;
1028 };
1029
1030 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1031 {
1032 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1033 u32 pir;
1034
1035 if (bitbang->set_gate)
1036 bitbang->set_gate(bitbang->addr);
1037
1038 pir = ioread32(bitbang->addr);
1039 if (set)
1040 pir |= mask;
1041 else
1042 pir &= ~mask;
1043 iowrite32(pir, bitbang->addr);
1044 }
1045
1046 /* Data I/O pin control */
1047 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1048 {
1049 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1050 }
1051
1052 /* Set bit data*/
1053 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1054 {
1055 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1056 }
1057
1058 /* Get bit data*/
1059 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1060 {
1061 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1062
1063 if (bitbang->set_gate)
1064 bitbang->set_gate(bitbang->addr);
1065
1066 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1067 }
1068
1069 /* MDC pin control */
1070 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1071 {
1072 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1073 }
1074
1075 /* mdio bus control struct */
1076 static struct mdiobb_ops bb_ops = {
1077 .owner = THIS_MODULE,
1078 .set_mdc = sh_mdc_ctrl,
1079 .set_mdio_dir = sh_mmd_ctrl,
1080 .set_mdio_data = sh_set_mdio,
1081 .get_mdio_data = sh_get_mdio,
1082 };
1083
1084 /* free skb and descriptor buffer */
1085 static void sh_eth_ring_free(struct net_device *ndev)
1086 {
1087 struct sh_eth_private *mdp = netdev_priv(ndev);
1088 int ringsize, i;
1089
1090 /* Free Rx skb ringbuffer */
1091 if (mdp->rx_skbuff) {
1092 for (i = 0; i < mdp->num_rx_ring; i++)
1093 dev_kfree_skb(mdp->rx_skbuff[i]);
1094 }
1095 kfree(mdp->rx_skbuff);
1096 mdp->rx_skbuff = NULL;
1097
1098 /* Free Tx skb ringbuffer */
1099 if (mdp->tx_skbuff) {
1100 for (i = 0; i < mdp->num_tx_ring; i++)
1101 dev_kfree_skb(mdp->tx_skbuff[i]);
1102 }
1103 kfree(mdp->tx_skbuff);
1104 mdp->tx_skbuff = NULL;
1105
1106 if (mdp->rx_ring) {
1107 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1108 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1109 mdp->rx_desc_dma);
1110 mdp->rx_ring = NULL;
1111 }
1112
1113 if (mdp->tx_ring) {
1114 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1115 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1116 mdp->tx_desc_dma);
1117 mdp->tx_ring = NULL;
1118 }
1119 }
1120
1121 /* format skb and descriptor buffer */
1122 static void sh_eth_ring_format(struct net_device *ndev)
1123 {
1124 struct sh_eth_private *mdp = netdev_priv(ndev);
1125 int i;
1126 struct sk_buff *skb;
1127 struct sh_eth_rxdesc *rxdesc = NULL;
1128 struct sh_eth_txdesc *txdesc = NULL;
1129 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1130 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1131 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1132 dma_addr_t dma_addr;
1133 u32 buf_len;
1134
1135 mdp->cur_rx = 0;
1136 mdp->cur_tx = 0;
1137 mdp->dirty_rx = 0;
1138 mdp->dirty_tx = 0;
1139
1140 memset(mdp->rx_ring, 0, rx_ringsize);
1141
1142 /* build Rx ring buffer */
1143 for (i = 0; i < mdp->num_rx_ring; i++) {
1144 /* skb */
1145 mdp->rx_skbuff[i] = NULL;
1146 skb = netdev_alloc_skb(ndev, skbuff_size);
1147 if (skb == NULL)
1148 break;
1149 sh_eth_set_receive_align(skb);
1150
1151 /* RX descriptor */
1152 rxdesc = &mdp->rx_ring[i];
1153 /* The size of the buffer is a multiple of 32 bytes. */
1154 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1155 rxdesc->len = cpu_to_edmac(mdp, buf_len << 16);
1156 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
1157 DMA_FROM_DEVICE);
1158 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1159 kfree_skb(skb);
1160 break;
1161 }
1162 mdp->rx_skbuff[i] = skb;
1163 rxdesc->addr = cpu_to_edmac(mdp, dma_addr);
1164 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1165
1166 /* Rx descriptor address set */
1167 if (i == 0) {
1168 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1169 if (sh_eth_is_gether(mdp) ||
1170 sh_eth_is_rz_fast_ether(mdp))
1171 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1172 }
1173 }
1174
1175 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1176
1177 /* Mark the last entry as wrapping the ring. */
1178 rxdesc->status |= cpu_to_edmac(mdp, RD_RDLE);
1179
1180 memset(mdp->tx_ring, 0, tx_ringsize);
1181
1182 /* build Tx ring buffer */
1183 for (i = 0; i < mdp->num_tx_ring; i++) {
1184 mdp->tx_skbuff[i] = NULL;
1185 txdesc = &mdp->tx_ring[i];
1186 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1187 txdesc->len = cpu_to_edmac(mdp, 0);
1188 if (i == 0) {
1189 /* Tx descriptor address set */
1190 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1191 if (sh_eth_is_gether(mdp) ||
1192 sh_eth_is_rz_fast_ether(mdp))
1193 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1194 }
1195 }
1196
1197 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1198 }
1199
1200 /* Get skb and descriptor buffer */
1201 static int sh_eth_ring_init(struct net_device *ndev)
1202 {
1203 struct sh_eth_private *mdp = netdev_priv(ndev);
1204 int rx_ringsize, tx_ringsize;
1205
1206 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1207 * card needs room to do 8 byte alignment, +2 so we can reserve
1208 * the first 2 bytes, and +16 gets room for the status word from the
1209 * card.
1210 */
1211 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1212 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1213 if (mdp->cd->rpadir)
1214 mdp->rx_buf_sz += NET_IP_ALIGN;
1215
1216 /* Allocate RX and TX skb rings */
1217 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1218 GFP_KERNEL);
1219 if (!mdp->rx_skbuff)
1220 return -ENOMEM;
1221
1222 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1223 GFP_KERNEL);
1224 if (!mdp->tx_skbuff)
1225 goto ring_free;
1226
1227 /* Allocate all Rx descriptors. */
1228 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1229 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1230 GFP_KERNEL);
1231 if (!mdp->rx_ring)
1232 goto ring_free;
1233
1234 mdp->dirty_rx = 0;
1235
1236 /* Allocate all Tx descriptors. */
1237 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1238 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1239 GFP_KERNEL);
1240 if (!mdp->tx_ring)
1241 goto ring_free;
1242 return 0;
1243
1244 ring_free:
1245 /* Free Rx and Tx skb ring buffer and DMA buffer */
1246 sh_eth_ring_free(ndev);
1247
1248 return -ENOMEM;
1249 }
1250
1251 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1252 {
1253 int ret = 0;
1254 struct sh_eth_private *mdp = netdev_priv(ndev);
1255 u32 val;
1256
1257 /* Soft Reset */
1258 ret = sh_eth_reset(ndev);
1259 if (ret)
1260 return ret;
1261
1262 if (mdp->cd->rmiimode)
1263 sh_eth_write(ndev, 0x1, RMIIMODE);
1264
1265 /* Descriptor format */
1266 sh_eth_ring_format(ndev);
1267 if (mdp->cd->rpadir)
1268 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1269
1270 /* all sh_eth int mask */
1271 sh_eth_write(ndev, 0, EESIPR);
1272
1273 #if defined(__LITTLE_ENDIAN)
1274 if (mdp->cd->hw_swap)
1275 sh_eth_write(ndev, EDMR_EL, EDMR);
1276 else
1277 #endif
1278 sh_eth_write(ndev, 0, EDMR);
1279
1280 /* FIFO size set */
1281 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1282 sh_eth_write(ndev, 0, TFTR);
1283
1284 /* Frame recv control (enable multiple-packets per rx irq) */
1285 sh_eth_write(ndev, RMCR_RNC, RMCR);
1286
1287 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1288
1289 if (mdp->cd->bculr)
1290 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
1291
1292 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1293
1294 if (!mdp->cd->no_trimd)
1295 sh_eth_write(ndev, 0, TRIMD);
1296
1297 /* Recv frame limit set register */
1298 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1299 RFLR);
1300
1301 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1302 if (start) {
1303 mdp->irq_enabled = true;
1304 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1305 }
1306
1307 /* PAUSE Prohibition */
1308 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1309 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1310
1311 sh_eth_write(ndev, val, ECMR);
1312
1313 if (mdp->cd->set_rate)
1314 mdp->cd->set_rate(ndev);
1315
1316 /* E-MAC Status Register clear */
1317 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1318
1319 /* E-MAC Interrupt Enable register */
1320 if (start)
1321 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1322
1323 /* Set MAC address */
1324 update_mac_address(ndev);
1325
1326 /* mask reset */
1327 if (mdp->cd->apr)
1328 sh_eth_write(ndev, APR_AP, APR);
1329 if (mdp->cd->mpr)
1330 sh_eth_write(ndev, MPR_MP, MPR);
1331 if (mdp->cd->tpauser)
1332 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1333
1334 if (start) {
1335 /* Setting the Rx mode will start the Rx process. */
1336 sh_eth_write(ndev, EDRRR_R, EDRRR);
1337
1338 netif_start_queue(ndev);
1339 }
1340
1341 return ret;
1342 }
1343
1344 static void sh_eth_dev_exit(struct net_device *ndev)
1345 {
1346 struct sh_eth_private *mdp = netdev_priv(ndev);
1347 int i;
1348
1349 /* Deactivate all TX descriptors, so DMA should stop at next
1350 * packet boundary if it's currently running
1351 */
1352 for (i = 0; i < mdp->num_tx_ring; i++)
1353 mdp->tx_ring[i].status &= ~cpu_to_edmac(mdp, TD_TACT);
1354
1355 /* Disable TX FIFO egress to MAC */
1356 sh_eth_rcv_snd_disable(ndev);
1357
1358 /* Stop RX DMA at next packet boundary */
1359 sh_eth_write(ndev, 0, EDRRR);
1360
1361 /* Aside from TX DMA, we can't tell when the hardware is
1362 * really stopped, so we need to reset to make sure.
1363 * Before doing that, wait for long enough to *probably*
1364 * finish transmitting the last packet and poll stats.
1365 */
1366 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1367 sh_eth_get_stats(ndev);
1368 sh_eth_reset(ndev);
1369
1370 /* Set MAC address again */
1371 update_mac_address(ndev);
1372 }
1373
1374 /* free Tx skb function */
1375 static int sh_eth_txfree(struct net_device *ndev)
1376 {
1377 struct sh_eth_private *mdp = netdev_priv(ndev);
1378 struct sh_eth_txdesc *txdesc;
1379 int free_num = 0;
1380 int entry = 0;
1381
1382 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1383 entry = mdp->dirty_tx % mdp->num_tx_ring;
1384 txdesc = &mdp->tx_ring[entry];
1385 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1386 break;
1387 /* TACT bit must be checked before all the following reads */
1388 dma_rmb();
1389 netif_info(mdp, tx_done, ndev,
1390 "tx entry %d status 0x%08x\n",
1391 entry, edmac_to_cpu(mdp, txdesc->status));
1392 /* Free the original skb. */
1393 if (mdp->tx_skbuff[entry]) {
1394 dma_unmap_single(&ndev->dev,
1395 edmac_to_cpu(mdp, txdesc->addr),
1396 edmac_to_cpu(mdp, txdesc->len) >> 16,
1397 DMA_TO_DEVICE);
1398 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1399 mdp->tx_skbuff[entry] = NULL;
1400 free_num++;
1401 }
1402 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1403 if (entry >= mdp->num_tx_ring - 1)
1404 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1405
1406 ndev->stats.tx_packets++;
1407 ndev->stats.tx_bytes += edmac_to_cpu(mdp, txdesc->len) >> 16;
1408 }
1409 return free_num;
1410 }
1411
1412 /* Packet receive function */
1413 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1414 {
1415 struct sh_eth_private *mdp = netdev_priv(ndev);
1416 struct sh_eth_rxdesc *rxdesc;
1417
1418 int entry = mdp->cur_rx % mdp->num_rx_ring;
1419 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1420 int limit;
1421 struct sk_buff *skb;
1422 u16 pkt_len = 0;
1423 u32 desc_status;
1424 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1425 dma_addr_t dma_addr;
1426 u32 buf_len;
1427
1428 boguscnt = min(boguscnt, *quota);
1429 limit = boguscnt;
1430 rxdesc = &mdp->rx_ring[entry];
1431 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1432 /* RACT bit must be checked before all the following reads */
1433 dma_rmb();
1434 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1435 pkt_len = edmac_to_cpu(mdp, rxdesc->len) & RD_RFL;
1436
1437 if (--boguscnt < 0)
1438 break;
1439
1440 netif_info(mdp, rx_status, ndev,
1441 "rx entry %d status 0x%08x len %d\n",
1442 entry, desc_status, pkt_len);
1443
1444 if (!(desc_status & RDFEND))
1445 ndev->stats.rx_length_errors++;
1446
1447 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1448 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1449 * bit 0. However, in case of the R8A7740 and R7S72100
1450 * the RFS bits are from bit 25 to bit 16. So, the
1451 * driver needs right shifting by 16.
1452 */
1453 if (mdp->cd->shift_rd0)
1454 desc_status >>= 16;
1455
1456 skb = mdp->rx_skbuff[entry];
1457 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1458 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1459 ndev->stats.rx_errors++;
1460 if (desc_status & RD_RFS1)
1461 ndev->stats.rx_crc_errors++;
1462 if (desc_status & RD_RFS2)
1463 ndev->stats.rx_frame_errors++;
1464 if (desc_status & RD_RFS3)
1465 ndev->stats.rx_length_errors++;
1466 if (desc_status & RD_RFS4)
1467 ndev->stats.rx_length_errors++;
1468 if (desc_status & RD_RFS6)
1469 ndev->stats.rx_missed_errors++;
1470 if (desc_status & RD_RFS10)
1471 ndev->stats.rx_over_errors++;
1472 } else if (skb) {
1473 dma_addr = edmac_to_cpu(mdp, rxdesc->addr);
1474 if (!mdp->cd->hw_swap)
1475 sh_eth_soft_swap(
1476 phys_to_virt(ALIGN(dma_addr, 4)),
1477 pkt_len + 2);
1478 mdp->rx_skbuff[entry] = NULL;
1479 if (mdp->cd->rpadir)
1480 skb_reserve(skb, NET_IP_ALIGN);
1481 dma_unmap_single(&ndev->dev, dma_addr,
1482 ALIGN(mdp->rx_buf_sz, 32),
1483 DMA_FROM_DEVICE);
1484 skb_put(skb, pkt_len);
1485 skb->protocol = eth_type_trans(skb, ndev);
1486 netif_receive_skb(skb);
1487 ndev->stats.rx_packets++;
1488 ndev->stats.rx_bytes += pkt_len;
1489 if (desc_status & RD_RFS8)
1490 ndev->stats.multicast++;
1491 }
1492 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1493 rxdesc = &mdp->rx_ring[entry];
1494 }
1495
1496 /* Refill the Rx ring buffers. */
1497 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1498 entry = mdp->dirty_rx % mdp->num_rx_ring;
1499 rxdesc = &mdp->rx_ring[entry];
1500 /* The size of the buffer is 32 byte boundary. */
1501 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1502 rxdesc->len = cpu_to_edmac(mdp, buf_len << 16);
1503
1504 if (mdp->rx_skbuff[entry] == NULL) {
1505 skb = netdev_alloc_skb(ndev, skbuff_size);
1506 if (skb == NULL)
1507 break; /* Better luck next round. */
1508 sh_eth_set_receive_align(skb);
1509 dma_addr = dma_map_single(&ndev->dev, skb->data,
1510 buf_len, DMA_FROM_DEVICE);
1511 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1512 kfree_skb(skb);
1513 break;
1514 }
1515 mdp->rx_skbuff[entry] = skb;
1516
1517 skb_checksum_none_assert(skb);
1518 rxdesc->addr = cpu_to_edmac(mdp, dma_addr);
1519 }
1520 dma_wmb(); /* RACT bit must be set after all the above writes */
1521 if (entry >= mdp->num_rx_ring - 1)
1522 rxdesc->status |=
1523 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDLE);
1524 else
1525 rxdesc->status |=
1526 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1527 }
1528
1529 /* Restart Rx engine if stopped. */
1530 /* If we don't need to check status, don't. -KDU */
1531 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1532 /* fix the values for the next receiving if RDE is set */
1533 if (intr_status & EESR_RDE &&
1534 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
1535 u32 count = (sh_eth_read(ndev, RDFAR) -
1536 sh_eth_read(ndev, RDLAR)) >> 4;
1537
1538 mdp->cur_rx = count;
1539 mdp->dirty_rx = count;
1540 }
1541 sh_eth_write(ndev, EDRRR_R, EDRRR);
1542 }
1543
1544 *quota -= limit - boguscnt - 1;
1545
1546 return *quota <= 0;
1547 }
1548
1549 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1550 {
1551 /* disable tx and rx */
1552 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1553 ~(ECMR_RE | ECMR_TE), ECMR);
1554 }
1555
1556 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1557 {
1558 /* enable tx and rx */
1559 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1560 (ECMR_RE | ECMR_TE), ECMR);
1561 }
1562
1563 /* error control function */
1564 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1565 {
1566 struct sh_eth_private *mdp = netdev_priv(ndev);
1567 u32 felic_stat;
1568 u32 link_stat;
1569 u32 mask;
1570
1571 if (intr_status & EESR_ECI) {
1572 felic_stat = sh_eth_read(ndev, ECSR);
1573 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1574 if (felic_stat & ECSR_ICD)
1575 ndev->stats.tx_carrier_errors++;
1576 if (felic_stat & ECSR_LCHNG) {
1577 /* Link Changed */
1578 if (mdp->cd->no_psr || mdp->no_ether_link) {
1579 goto ignore_link;
1580 } else {
1581 link_stat = (sh_eth_read(ndev, PSR));
1582 if (mdp->ether_link_active_low)
1583 link_stat = ~link_stat;
1584 }
1585 if (!(link_stat & PHY_ST_LINK)) {
1586 sh_eth_rcv_snd_disable(ndev);
1587 } else {
1588 /* Link Up */
1589 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1590 ~DMAC_M_ECI, EESIPR);
1591 /* clear int */
1592 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1593 ECSR);
1594 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1595 DMAC_M_ECI, EESIPR);
1596 /* enable tx and rx */
1597 sh_eth_rcv_snd_enable(ndev);
1598 }
1599 }
1600 }
1601
1602 ignore_link:
1603 if (intr_status & EESR_TWB) {
1604 /* Unused write back interrupt */
1605 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1606 ndev->stats.tx_aborted_errors++;
1607 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1608 }
1609 }
1610
1611 if (intr_status & EESR_RABT) {
1612 /* Receive Abort int */
1613 if (intr_status & EESR_RFRMER) {
1614 /* Receive Frame Overflow int */
1615 ndev->stats.rx_frame_errors++;
1616 }
1617 }
1618
1619 if (intr_status & EESR_TDE) {
1620 /* Transmit Descriptor Empty int */
1621 ndev->stats.tx_fifo_errors++;
1622 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1623 }
1624
1625 if (intr_status & EESR_TFE) {
1626 /* FIFO under flow */
1627 ndev->stats.tx_fifo_errors++;
1628 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1629 }
1630
1631 if (intr_status & EESR_RDE) {
1632 /* Receive Descriptor Empty int */
1633 ndev->stats.rx_over_errors++;
1634 }
1635
1636 if (intr_status & EESR_RFE) {
1637 /* Receive FIFO Overflow int */
1638 ndev->stats.rx_fifo_errors++;
1639 }
1640
1641 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1642 /* Address Error */
1643 ndev->stats.tx_fifo_errors++;
1644 netif_err(mdp, tx_err, ndev, "Address Error\n");
1645 }
1646
1647 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1648 if (mdp->cd->no_ade)
1649 mask &= ~EESR_ADE;
1650 if (intr_status & mask) {
1651 /* Tx error */
1652 u32 edtrr = sh_eth_read(ndev, EDTRR);
1653
1654 /* dmesg */
1655 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1656 intr_status, mdp->cur_tx, mdp->dirty_tx,
1657 (u32)ndev->state, edtrr);
1658 /* dirty buffer free */
1659 sh_eth_txfree(ndev);
1660
1661 /* SH7712 BUG */
1662 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1663 /* tx dma start */
1664 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1665 }
1666 /* wakeup */
1667 netif_wake_queue(ndev);
1668 }
1669 }
1670
1671 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1672 {
1673 struct net_device *ndev = netdev;
1674 struct sh_eth_private *mdp = netdev_priv(ndev);
1675 struct sh_eth_cpu_data *cd = mdp->cd;
1676 irqreturn_t ret = IRQ_NONE;
1677 u32 intr_status, intr_enable;
1678
1679 spin_lock(&mdp->lock);
1680
1681 /* Get interrupt status */
1682 intr_status = sh_eth_read(ndev, EESR);
1683 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1684 * enabled since it's the one that comes thru regardless of the mask,
1685 * and we need to fully handle it in sh_eth_error() in order to quench
1686 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1687 */
1688 intr_enable = sh_eth_read(ndev, EESIPR);
1689 intr_status &= intr_enable | DMAC_M_ECI;
1690 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1691 ret = IRQ_HANDLED;
1692 else
1693 goto out;
1694
1695 if (!likely(mdp->irq_enabled)) {
1696 sh_eth_write(ndev, 0, EESIPR);
1697 goto out;
1698 }
1699
1700 if (intr_status & EESR_RX_CHECK) {
1701 if (napi_schedule_prep(&mdp->napi)) {
1702 /* Mask Rx interrupts */
1703 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1704 EESIPR);
1705 __napi_schedule(&mdp->napi);
1706 } else {
1707 netdev_warn(ndev,
1708 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1709 intr_status, intr_enable);
1710 }
1711 }
1712
1713 /* Tx Check */
1714 if (intr_status & cd->tx_check) {
1715 /* Clear Tx interrupts */
1716 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1717
1718 sh_eth_txfree(ndev);
1719 netif_wake_queue(ndev);
1720 }
1721
1722 if (intr_status & cd->eesr_err_check) {
1723 /* Clear error interrupts */
1724 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1725
1726 sh_eth_error(ndev, intr_status);
1727 }
1728
1729 out:
1730 spin_unlock(&mdp->lock);
1731
1732 return ret;
1733 }
1734
1735 static int sh_eth_poll(struct napi_struct *napi, int budget)
1736 {
1737 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1738 napi);
1739 struct net_device *ndev = napi->dev;
1740 int quota = budget;
1741 u32 intr_status;
1742
1743 for (;;) {
1744 intr_status = sh_eth_read(ndev, EESR);
1745 if (!(intr_status & EESR_RX_CHECK))
1746 break;
1747 /* Clear Rx interrupts */
1748 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1749
1750 if (sh_eth_rx(ndev, intr_status, &quota))
1751 goto out;
1752 }
1753
1754 napi_complete(napi);
1755
1756 /* Reenable Rx interrupts */
1757 if (mdp->irq_enabled)
1758 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1759 out:
1760 return budget - quota;
1761 }
1762
1763 /* PHY state control function */
1764 static void sh_eth_adjust_link(struct net_device *ndev)
1765 {
1766 struct sh_eth_private *mdp = netdev_priv(ndev);
1767 struct phy_device *phydev = mdp->phydev;
1768 int new_state = 0;
1769
1770 if (phydev->link) {
1771 if (phydev->duplex != mdp->duplex) {
1772 new_state = 1;
1773 mdp->duplex = phydev->duplex;
1774 if (mdp->cd->set_duplex)
1775 mdp->cd->set_duplex(ndev);
1776 }
1777
1778 if (phydev->speed != mdp->speed) {
1779 new_state = 1;
1780 mdp->speed = phydev->speed;
1781 if (mdp->cd->set_rate)
1782 mdp->cd->set_rate(ndev);
1783 }
1784 if (!mdp->link) {
1785 sh_eth_write(ndev,
1786 sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1787 ECMR);
1788 new_state = 1;
1789 mdp->link = phydev->link;
1790 if (mdp->cd->no_psr || mdp->no_ether_link)
1791 sh_eth_rcv_snd_enable(ndev);
1792 }
1793 } else if (mdp->link) {
1794 new_state = 1;
1795 mdp->link = 0;
1796 mdp->speed = 0;
1797 mdp->duplex = -1;
1798 if (mdp->cd->no_psr || mdp->no_ether_link)
1799 sh_eth_rcv_snd_disable(ndev);
1800 }
1801
1802 if (new_state && netif_msg_link(mdp))
1803 phy_print_status(phydev);
1804 }
1805
1806 /* PHY init function */
1807 static int sh_eth_phy_init(struct net_device *ndev)
1808 {
1809 struct device_node *np = ndev->dev.parent->of_node;
1810 struct sh_eth_private *mdp = netdev_priv(ndev);
1811 struct phy_device *phydev = NULL;
1812
1813 mdp->link = 0;
1814 mdp->speed = 0;
1815 mdp->duplex = -1;
1816
1817 /* Try connect to PHY */
1818 if (np) {
1819 struct device_node *pn;
1820
1821 pn = of_parse_phandle(np, "phy-handle", 0);
1822 phydev = of_phy_connect(ndev, pn,
1823 sh_eth_adjust_link, 0,
1824 mdp->phy_interface);
1825
1826 if (!phydev)
1827 phydev = ERR_PTR(-ENOENT);
1828 } else {
1829 char phy_id[MII_BUS_ID_SIZE + 3];
1830
1831 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1832 mdp->mii_bus->id, mdp->phy_id);
1833
1834 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1835 mdp->phy_interface);
1836 }
1837
1838 if (IS_ERR(phydev)) {
1839 netdev_err(ndev, "failed to connect PHY\n");
1840 return PTR_ERR(phydev);
1841 }
1842
1843 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1844 phydev->addr, phydev->irq, phydev->drv->name);
1845
1846 mdp->phydev = phydev;
1847
1848 return 0;
1849 }
1850
1851 /* PHY control start function */
1852 static int sh_eth_phy_start(struct net_device *ndev)
1853 {
1854 struct sh_eth_private *mdp = netdev_priv(ndev);
1855 int ret;
1856
1857 ret = sh_eth_phy_init(ndev);
1858 if (ret)
1859 return ret;
1860
1861 phy_start(mdp->phydev);
1862
1863 return 0;
1864 }
1865
1866 static int sh_eth_get_settings(struct net_device *ndev,
1867 struct ethtool_cmd *ecmd)
1868 {
1869 struct sh_eth_private *mdp = netdev_priv(ndev);
1870 unsigned long flags;
1871 int ret;
1872
1873 if (!mdp->phydev)
1874 return -ENODEV;
1875
1876 spin_lock_irqsave(&mdp->lock, flags);
1877 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1878 spin_unlock_irqrestore(&mdp->lock, flags);
1879
1880 return ret;
1881 }
1882
1883 static int sh_eth_set_settings(struct net_device *ndev,
1884 struct ethtool_cmd *ecmd)
1885 {
1886 struct sh_eth_private *mdp = netdev_priv(ndev);
1887 unsigned long flags;
1888 int ret;
1889
1890 if (!mdp->phydev)
1891 return -ENODEV;
1892
1893 spin_lock_irqsave(&mdp->lock, flags);
1894
1895 /* disable tx and rx */
1896 sh_eth_rcv_snd_disable(ndev);
1897
1898 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1899 if (ret)
1900 goto error_exit;
1901
1902 if (ecmd->duplex == DUPLEX_FULL)
1903 mdp->duplex = 1;
1904 else
1905 mdp->duplex = 0;
1906
1907 if (mdp->cd->set_duplex)
1908 mdp->cd->set_duplex(ndev);
1909
1910 error_exit:
1911 mdelay(1);
1912
1913 /* enable tx and rx */
1914 sh_eth_rcv_snd_enable(ndev);
1915
1916 spin_unlock_irqrestore(&mdp->lock, flags);
1917
1918 return ret;
1919 }
1920
1921 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1922 * version must be bumped as well. Just adding registers up to that
1923 * limit is fine, as long as the existing register indices don't
1924 * change.
1925 */
1926 #define SH_ETH_REG_DUMP_VERSION 1
1927 #define SH_ETH_REG_DUMP_MAX_REGS 256
1928
1929 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1930 {
1931 struct sh_eth_private *mdp = netdev_priv(ndev);
1932 struct sh_eth_cpu_data *cd = mdp->cd;
1933 u32 *valid_map;
1934 size_t len;
1935
1936 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1937
1938 /* Dump starts with a bitmap that tells ethtool which
1939 * registers are defined for this chip.
1940 */
1941 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1942 if (buf) {
1943 valid_map = buf;
1944 buf += len;
1945 } else {
1946 valid_map = NULL;
1947 }
1948
1949 /* Add a register to the dump, if it has a defined offset.
1950 * This automatically skips most undefined registers, but for
1951 * some it is also necessary to check a capability flag in
1952 * struct sh_eth_cpu_data.
1953 */
1954 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1955 #define add_reg_from(reg, read_expr) do { \
1956 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
1957 if (buf) { \
1958 mark_reg_valid(reg); \
1959 *buf++ = read_expr; \
1960 } \
1961 ++len; \
1962 } \
1963 } while (0)
1964 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1965 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
1966
1967 add_reg(EDSR);
1968 add_reg(EDMR);
1969 add_reg(EDTRR);
1970 add_reg(EDRRR);
1971 add_reg(EESR);
1972 add_reg(EESIPR);
1973 add_reg(TDLAR);
1974 add_reg(TDFAR);
1975 add_reg(TDFXR);
1976 add_reg(TDFFR);
1977 add_reg(RDLAR);
1978 add_reg(RDFAR);
1979 add_reg(RDFXR);
1980 add_reg(RDFFR);
1981 add_reg(TRSCER);
1982 add_reg(RMFCR);
1983 add_reg(TFTR);
1984 add_reg(FDR);
1985 add_reg(RMCR);
1986 add_reg(TFUCR);
1987 add_reg(RFOCR);
1988 if (cd->rmiimode)
1989 add_reg(RMIIMODE);
1990 add_reg(FCFTR);
1991 if (cd->rpadir)
1992 add_reg(RPADIR);
1993 if (!cd->no_trimd)
1994 add_reg(TRIMD);
1995 add_reg(ECMR);
1996 add_reg(ECSR);
1997 add_reg(ECSIPR);
1998 add_reg(PIR);
1999 if (!cd->no_psr)
2000 add_reg(PSR);
2001 add_reg(RDMLR);
2002 add_reg(RFLR);
2003 add_reg(IPGR);
2004 if (cd->apr)
2005 add_reg(APR);
2006 if (cd->mpr)
2007 add_reg(MPR);
2008 add_reg(RFCR);
2009 add_reg(RFCF);
2010 if (cd->tpauser)
2011 add_reg(TPAUSER);
2012 add_reg(TPAUSECR);
2013 add_reg(GECMR);
2014 if (cd->bculr)
2015 add_reg(BCULR);
2016 add_reg(MAHR);
2017 add_reg(MALR);
2018 add_reg(TROCR);
2019 add_reg(CDCR);
2020 add_reg(LCCR);
2021 add_reg(CNDCR);
2022 add_reg(CEFCR);
2023 add_reg(FRECR);
2024 add_reg(TSFRCR);
2025 add_reg(TLFRCR);
2026 add_reg(CERCR);
2027 add_reg(CEECR);
2028 add_reg(MAFCR);
2029 if (cd->rtrate)
2030 add_reg(RTRATE);
2031 if (cd->hw_crc)
2032 add_reg(CSMR);
2033 if (cd->select_mii)
2034 add_reg(RMII_MII);
2035 add_reg(ARSTR);
2036 if (cd->tsu) {
2037 add_tsu_reg(TSU_CTRST);
2038 add_tsu_reg(TSU_FWEN0);
2039 add_tsu_reg(TSU_FWEN1);
2040 add_tsu_reg(TSU_FCM);
2041 add_tsu_reg(TSU_BSYSL0);
2042 add_tsu_reg(TSU_BSYSL1);
2043 add_tsu_reg(TSU_PRISL0);
2044 add_tsu_reg(TSU_PRISL1);
2045 add_tsu_reg(TSU_FWSL0);
2046 add_tsu_reg(TSU_FWSL1);
2047 add_tsu_reg(TSU_FWSLC);
2048 add_tsu_reg(TSU_QTAG0);
2049 add_tsu_reg(TSU_QTAG1);
2050 add_tsu_reg(TSU_QTAGM0);
2051 add_tsu_reg(TSU_QTAGM1);
2052 add_tsu_reg(TSU_FWSR);
2053 add_tsu_reg(TSU_FWINMK);
2054 add_tsu_reg(TSU_ADQT0);
2055 add_tsu_reg(TSU_ADQT1);
2056 add_tsu_reg(TSU_VTAG0);
2057 add_tsu_reg(TSU_VTAG1);
2058 add_tsu_reg(TSU_ADSBSY);
2059 add_tsu_reg(TSU_TEN);
2060 add_tsu_reg(TSU_POST1);
2061 add_tsu_reg(TSU_POST2);
2062 add_tsu_reg(TSU_POST3);
2063 add_tsu_reg(TSU_POST4);
2064 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2065 /* This is the start of a table, not just a single
2066 * register.
2067 */
2068 if (buf) {
2069 unsigned int i;
2070
2071 mark_reg_valid(TSU_ADRH0);
2072 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2073 *buf++ = ioread32(
2074 mdp->tsu_addr +
2075 mdp->reg_offset[TSU_ADRH0] +
2076 i * 4);
2077 }
2078 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2079 }
2080 }
2081
2082 #undef mark_reg_valid
2083 #undef add_reg_from
2084 #undef add_reg
2085 #undef add_tsu_reg
2086
2087 return len * 4;
2088 }
2089
2090 static int sh_eth_get_regs_len(struct net_device *ndev)
2091 {
2092 return __sh_eth_get_regs(ndev, NULL);
2093 }
2094
2095 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2096 void *buf)
2097 {
2098 struct sh_eth_private *mdp = netdev_priv(ndev);
2099
2100 regs->version = SH_ETH_REG_DUMP_VERSION;
2101
2102 pm_runtime_get_sync(&mdp->pdev->dev);
2103 __sh_eth_get_regs(ndev, buf);
2104 pm_runtime_put_sync(&mdp->pdev->dev);
2105 }
2106
2107 static int sh_eth_nway_reset(struct net_device *ndev)
2108 {
2109 struct sh_eth_private *mdp = netdev_priv(ndev);
2110 unsigned long flags;
2111 int ret;
2112
2113 if (!mdp->phydev)
2114 return -ENODEV;
2115
2116 spin_lock_irqsave(&mdp->lock, flags);
2117 ret = phy_start_aneg(mdp->phydev);
2118 spin_unlock_irqrestore(&mdp->lock, flags);
2119
2120 return ret;
2121 }
2122
2123 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2124 {
2125 struct sh_eth_private *mdp = netdev_priv(ndev);
2126 return mdp->msg_enable;
2127 }
2128
2129 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2130 {
2131 struct sh_eth_private *mdp = netdev_priv(ndev);
2132 mdp->msg_enable = value;
2133 }
2134
2135 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2136 "rx_current", "tx_current",
2137 "rx_dirty", "tx_dirty",
2138 };
2139 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2140
2141 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2142 {
2143 switch (sset) {
2144 case ETH_SS_STATS:
2145 return SH_ETH_STATS_LEN;
2146 default:
2147 return -EOPNOTSUPP;
2148 }
2149 }
2150
2151 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2152 struct ethtool_stats *stats, u64 *data)
2153 {
2154 struct sh_eth_private *mdp = netdev_priv(ndev);
2155 int i = 0;
2156
2157 /* device-specific stats */
2158 data[i++] = mdp->cur_rx;
2159 data[i++] = mdp->cur_tx;
2160 data[i++] = mdp->dirty_rx;
2161 data[i++] = mdp->dirty_tx;
2162 }
2163
2164 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2165 {
2166 switch (stringset) {
2167 case ETH_SS_STATS:
2168 memcpy(data, *sh_eth_gstrings_stats,
2169 sizeof(sh_eth_gstrings_stats));
2170 break;
2171 }
2172 }
2173
2174 static void sh_eth_get_ringparam(struct net_device *ndev,
2175 struct ethtool_ringparam *ring)
2176 {
2177 struct sh_eth_private *mdp = netdev_priv(ndev);
2178
2179 ring->rx_max_pending = RX_RING_MAX;
2180 ring->tx_max_pending = TX_RING_MAX;
2181 ring->rx_pending = mdp->num_rx_ring;
2182 ring->tx_pending = mdp->num_tx_ring;
2183 }
2184
2185 static int sh_eth_set_ringparam(struct net_device *ndev,
2186 struct ethtool_ringparam *ring)
2187 {
2188 struct sh_eth_private *mdp = netdev_priv(ndev);
2189 int ret;
2190
2191 if (ring->tx_pending > TX_RING_MAX ||
2192 ring->rx_pending > RX_RING_MAX ||
2193 ring->tx_pending < TX_RING_MIN ||
2194 ring->rx_pending < RX_RING_MIN)
2195 return -EINVAL;
2196 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2197 return -EINVAL;
2198
2199 if (netif_running(ndev)) {
2200 netif_device_detach(ndev);
2201 netif_tx_disable(ndev);
2202
2203 /* Serialise with the interrupt handler and NAPI, then
2204 * disable interrupts. We have to clear the
2205 * irq_enabled flag first to ensure that interrupts
2206 * won't be re-enabled.
2207 */
2208 mdp->irq_enabled = false;
2209 synchronize_irq(ndev->irq);
2210 napi_synchronize(&mdp->napi);
2211 sh_eth_write(ndev, 0x0000, EESIPR);
2212
2213 sh_eth_dev_exit(ndev);
2214
2215 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2216 sh_eth_ring_free(ndev);
2217 }
2218
2219 /* Set new parameters */
2220 mdp->num_rx_ring = ring->rx_pending;
2221 mdp->num_tx_ring = ring->tx_pending;
2222
2223 if (netif_running(ndev)) {
2224 ret = sh_eth_ring_init(ndev);
2225 if (ret < 0) {
2226 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2227 __func__);
2228 return ret;
2229 }
2230 ret = sh_eth_dev_init(ndev, false);
2231 if (ret < 0) {
2232 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2233 __func__);
2234 return ret;
2235 }
2236
2237 mdp->irq_enabled = true;
2238 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2239 /* Setting the Rx mode will start the Rx process. */
2240 sh_eth_write(ndev, EDRRR_R, EDRRR);
2241 netif_device_attach(ndev);
2242 }
2243
2244 return 0;
2245 }
2246
2247 static const struct ethtool_ops sh_eth_ethtool_ops = {
2248 .get_settings = sh_eth_get_settings,
2249 .set_settings = sh_eth_set_settings,
2250 .get_regs_len = sh_eth_get_regs_len,
2251 .get_regs = sh_eth_get_regs,
2252 .nway_reset = sh_eth_nway_reset,
2253 .get_msglevel = sh_eth_get_msglevel,
2254 .set_msglevel = sh_eth_set_msglevel,
2255 .get_link = ethtool_op_get_link,
2256 .get_strings = sh_eth_get_strings,
2257 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2258 .get_sset_count = sh_eth_get_sset_count,
2259 .get_ringparam = sh_eth_get_ringparam,
2260 .set_ringparam = sh_eth_set_ringparam,
2261 };
2262
2263 /* network device open function */
2264 static int sh_eth_open(struct net_device *ndev)
2265 {
2266 int ret = 0;
2267 struct sh_eth_private *mdp = netdev_priv(ndev);
2268
2269 pm_runtime_get_sync(&mdp->pdev->dev);
2270
2271 napi_enable(&mdp->napi);
2272
2273 ret = request_irq(ndev->irq, sh_eth_interrupt,
2274 mdp->cd->irq_flags, ndev->name, ndev);
2275 if (ret) {
2276 netdev_err(ndev, "Can not assign IRQ number\n");
2277 goto out_napi_off;
2278 }
2279
2280 /* Descriptor set */
2281 ret = sh_eth_ring_init(ndev);
2282 if (ret)
2283 goto out_free_irq;
2284
2285 /* device init */
2286 ret = sh_eth_dev_init(ndev, true);
2287 if (ret)
2288 goto out_free_irq;
2289
2290 /* PHY control start*/
2291 ret = sh_eth_phy_start(ndev);
2292 if (ret)
2293 goto out_free_irq;
2294
2295 mdp->is_opened = 1;
2296
2297 return ret;
2298
2299 out_free_irq:
2300 free_irq(ndev->irq, ndev);
2301 out_napi_off:
2302 napi_disable(&mdp->napi);
2303 pm_runtime_put_sync(&mdp->pdev->dev);
2304 return ret;
2305 }
2306
2307 /* Timeout function */
2308 static void sh_eth_tx_timeout(struct net_device *ndev)
2309 {
2310 struct sh_eth_private *mdp = netdev_priv(ndev);
2311 struct sh_eth_rxdesc *rxdesc;
2312 int i;
2313
2314 netif_stop_queue(ndev);
2315
2316 netif_err(mdp, timer, ndev,
2317 "transmit timed out, status %8.8x, resetting...\n",
2318 sh_eth_read(ndev, EESR));
2319
2320 /* tx_errors count up */
2321 ndev->stats.tx_errors++;
2322
2323 /* Free all the skbuffs in the Rx queue. */
2324 for (i = 0; i < mdp->num_rx_ring; i++) {
2325 rxdesc = &mdp->rx_ring[i];
2326 rxdesc->status = cpu_to_edmac(mdp, 0);
2327 rxdesc->addr = cpu_to_edmac(mdp, 0xBADF00D0);
2328 dev_kfree_skb(mdp->rx_skbuff[i]);
2329 mdp->rx_skbuff[i] = NULL;
2330 }
2331 for (i = 0; i < mdp->num_tx_ring; i++) {
2332 dev_kfree_skb(mdp->tx_skbuff[i]);
2333 mdp->tx_skbuff[i] = NULL;
2334 }
2335
2336 /* device init */
2337 sh_eth_dev_init(ndev, true);
2338 }
2339
2340 /* Packet transmit function */
2341 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2342 {
2343 struct sh_eth_private *mdp = netdev_priv(ndev);
2344 struct sh_eth_txdesc *txdesc;
2345 dma_addr_t dma_addr;
2346 u32 entry;
2347 unsigned long flags;
2348
2349 spin_lock_irqsave(&mdp->lock, flags);
2350 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2351 if (!sh_eth_txfree(ndev)) {
2352 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2353 netif_stop_queue(ndev);
2354 spin_unlock_irqrestore(&mdp->lock, flags);
2355 return NETDEV_TX_BUSY;
2356 }
2357 }
2358 spin_unlock_irqrestore(&mdp->lock, flags);
2359
2360 if (skb_put_padto(skb, ETH_ZLEN))
2361 return NETDEV_TX_OK;
2362
2363 entry = mdp->cur_tx % mdp->num_tx_ring;
2364 mdp->tx_skbuff[entry] = skb;
2365 txdesc = &mdp->tx_ring[entry];
2366 /* soft swap. */
2367 if (!mdp->cd->hw_swap)
2368 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2369 dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2370 DMA_TO_DEVICE);
2371 if (dma_mapping_error(&ndev->dev, dma_addr)) {
2372 kfree_skb(skb);
2373 return NETDEV_TX_OK;
2374 }
2375 txdesc->addr = cpu_to_edmac(mdp, dma_addr);
2376 txdesc->len = cpu_to_edmac(mdp, skb->len << 16);
2377
2378 dma_wmb(); /* TACT bit must be set after all the above writes */
2379 if (entry >= mdp->num_tx_ring - 1)
2380 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2381 else
2382 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2383
2384 mdp->cur_tx++;
2385
2386 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2387 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2388
2389 return NETDEV_TX_OK;
2390 }
2391
2392 /* The statistics registers have write-clear behaviour, which means we
2393 * will lose any increment between the read and write. We mitigate
2394 * this by only clearing when we read a non-zero value, so we will
2395 * never falsely report a total of zero.
2396 */
2397 static void
2398 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2399 {
2400 u32 delta = sh_eth_read(ndev, reg);
2401
2402 if (delta) {
2403 *stat += delta;
2404 sh_eth_write(ndev, 0, reg);
2405 }
2406 }
2407
2408 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2409 {
2410 struct sh_eth_private *mdp = netdev_priv(ndev);
2411
2412 if (sh_eth_is_rz_fast_ether(mdp))
2413 return &ndev->stats;
2414
2415 if (!mdp->is_opened)
2416 return &ndev->stats;
2417
2418 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2419 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2420 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2421
2422 if (sh_eth_is_gether(mdp)) {
2423 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2424 CERCR);
2425 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2426 CEECR);
2427 } else {
2428 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2429 CNDCR);
2430 }
2431
2432 return &ndev->stats;
2433 }
2434
2435 /* device close function */
2436 static int sh_eth_close(struct net_device *ndev)
2437 {
2438 struct sh_eth_private *mdp = netdev_priv(ndev);
2439
2440 netif_stop_queue(ndev);
2441
2442 /* Serialise with the interrupt handler and NAPI, then disable
2443 * interrupts. We have to clear the irq_enabled flag first to
2444 * ensure that interrupts won't be re-enabled.
2445 */
2446 mdp->irq_enabled = false;
2447 synchronize_irq(ndev->irq);
2448 napi_disable(&mdp->napi);
2449 sh_eth_write(ndev, 0x0000, EESIPR);
2450
2451 sh_eth_dev_exit(ndev);
2452
2453 /* PHY Disconnect */
2454 if (mdp->phydev) {
2455 phy_stop(mdp->phydev);
2456 phy_disconnect(mdp->phydev);
2457 mdp->phydev = NULL;
2458 }
2459
2460 free_irq(ndev->irq, ndev);
2461
2462 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2463 sh_eth_ring_free(ndev);
2464
2465 pm_runtime_put_sync(&mdp->pdev->dev);
2466
2467 mdp->is_opened = 0;
2468
2469 return 0;
2470 }
2471
2472 /* ioctl to device function */
2473 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2474 {
2475 struct sh_eth_private *mdp = netdev_priv(ndev);
2476 struct phy_device *phydev = mdp->phydev;
2477
2478 if (!netif_running(ndev))
2479 return -EINVAL;
2480
2481 if (!phydev)
2482 return -ENODEV;
2483
2484 return phy_mii_ioctl(phydev, rq, cmd);
2485 }
2486
2487 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2488 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2489 int entry)
2490 {
2491 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2492 }
2493
2494 static u32 sh_eth_tsu_get_post_mask(int entry)
2495 {
2496 return 0x0f << (28 - ((entry % 8) * 4));
2497 }
2498
2499 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2500 {
2501 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2502 }
2503
2504 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2505 int entry)
2506 {
2507 struct sh_eth_private *mdp = netdev_priv(ndev);
2508 u32 tmp;
2509 void *reg_offset;
2510
2511 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2512 tmp = ioread32(reg_offset);
2513 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2514 }
2515
2516 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2517 int entry)
2518 {
2519 struct sh_eth_private *mdp = netdev_priv(ndev);
2520 u32 post_mask, ref_mask, tmp;
2521 void *reg_offset;
2522
2523 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2524 post_mask = sh_eth_tsu_get_post_mask(entry);
2525 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2526
2527 tmp = ioread32(reg_offset);
2528 iowrite32(tmp & ~post_mask, reg_offset);
2529
2530 /* If other port enables, the function returns "true" */
2531 return tmp & ref_mask;
2532 }
2533
2534 static int sh_eth_tsu_busy(struct net_device *ndev)
2535 {
2536 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2537 struct sh_eth_private *mdp = netdev_priv(ndev);
2538
2539 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2540 udelay(10);
2541 timeout--;
2542 if (timeout <= 0) {
2543 netdev_err(ndev, "%s: timeout\n", __func__);
2544 return -ETIMEDOUT;
2545 }
2546 }
2547
2548 return 0;
2549 }
2550
2551 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2552 const u8 *addr)
2553 {
2554 u32 val;
2555
2556 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2557 iowrite32(val, reg);
2558 if (sh_eth_tsu_busy(ndev) < 0)
2559 return -EBUSY;
2560
2561 val = addr[4] << 8 | addr[5];
2562 iowrite32(val, reg + 4);
2563 if (sh_eth_tsu_busy(ndev) < 0)
2564 return -EBUSY;
2565
2566 return 0;
2567 }
2568
2569 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2570 {
2571 u32 val;
2572
2573 val = ioread32(reg);
2574 addr[0] = (val >> 24) & 0xff;
2575 addr[1] = (val >> 16) & 0xff;
2576 addr[2] = (val >> 8) & 0xff;
2577 addr[3] = val & 0xff;
2578 val = ioread32(reg + 4);
2579 addr[4] = (val >> 8) & 0xff;
2580 addr[5] = val & 0xff;
2581 }
2582
2583
2584 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2585 {
2586 struct sh_eth_private *mdp = netdev_priv(ndev);
2587 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2588 int i;
2589 u8 c_addr[ETH_ALEN];
2590
2591 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2592 sh_eth_tsu_read_entry(reg_offset, c_addr);
2593 if (ether_addr_equal(addr, c_addr))
2594 return i;
2595 }
2596
2597 return -ENOENT;
2598 }
2599
2600 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2601 {
2602 u8 blank[ETH_ALEN];
2603 int entry;
2604
2605 memset(blank, 0, sizeof(blank));
2606 entry = sh_eth_tsu_find_entry(ndev, blank);
2607 return (entry < 0) ? -ENOMEM : entry;
2608 }
2609
2610 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2611 int entry)
2612 {
2613 struct sh_eth_private *mdp = netdev_priv(ndev);
2614 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2615 int ret;
2616 u8 blank[ETH_ALEN];
2617
2618 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2619 ~(1 << (31 - entry)), TSU_TEN);
2620
2621 memset(blank, 0, sizeof(blank));
2622 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2623 if (ret < 0)
2624 return ret;
2625 return 0;
2626 }
2627
2628 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2629 {
2630 struct sh_eth_private *mdp = netdev_priv(ndev);
2631 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2632 int i, ret;
2633
2634 if (!mdp->cd->tsu)
2635 return 0;
2636
2637 i = sh_eth_tsu_find_entry(ndev, addr);
2638 if (i < 0) {
2639 /* No entry found, create one */
2640 i = sh_eth_tsu_find_empty(ndev);
2641 if (i < 0)
2642 return -ENOMEM;
2643 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2644 if (ret < 0)
2645 return ret;
2646
2647 /* Enable the entry */
2648 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2649 (1 << (31 - i)), TSU_TEN);
2650 }
2651
2652 /* Entry found or created, enable POST */
2653 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2654
2655 return 0;
2656 }
2657
2658 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2659 {
2660 struct sh_eth_private *mdp = netdev_priv(ndev);
2661 int i, ret;
2662
2663 if (!mdp->cd->tsu)
2664 return 0;
2665
2666 i = sh_eth_tsu_find_entry(ndev, addr);
2667 if (i) {
2668 /* Entry found */
2669 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2670 goto done;
2671
2672 /* Disable the entry if both ports was disabled */
2673 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2674 if (ret < 0)
2675 return ret;
2676 }
2677 done:
2678 return 0;
2679 }
2680
2681 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2682 {
2683 struct sh_eth_private *mdp = netdev_priv(ndev);
2684 int i, ret;
2685
2686 if (!mdp->cd->tsu)
2687 return 0;
2688
2689 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2690 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2691 continue;
2692
2693 /* Disable the entry if both ports was disabled */
2694 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2695 if (ret < 0)
2696 return ret;
2697 }
2698
2699 return 0;
2700 }
2701
2702 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2703 {
2704 struct sh_eth_private *mdp = netdev_priv(ndev);
2705 u8 addr[ETH_ALEN];
2706 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2707 int i;
2708
2709 if (!mdp->cd->tsu)
2710 return;
2711
2712 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2713 sh_eth_tsu_read_entry(reg_offset, addr);
2714 if (is_multicast_ether_addr(addr))
2715 sh_eth_tsu_del_entry(ndev, addr);
2716 }
2717 }
2718
2719 /* Update promiscuous flag and multicast filter */
2720 static void sh_eth_set_rx_mode(struct net_device *ndev)
2721 {
2722 struct sh_eth_private *mdp = netdev_priv(ndev);
2723 u32 ecmr_bits;
2724 int mcast_all = 0;
2725 unsigned long flags;
2726
2727 spin_lock_irqsave(&mdp->lock, flags);
2728 /* Initial condition is MCT = 1, PRM = 0.
2729 * Depending on ndev->flags, set PRM or clear MCT
2730 */
2731 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2732 if (mdp->cd->tsu)
2733 ecmr_bits |= ECMR_MCT;
2734
2735 if (!(ndev->flags & IFF_MULTICAST)) {
2736 sh_eth_tsu_purge_mcast(ndev);
2737 mcast_all = 1;
2738 }
2739 if (ndev->flags & IFF_ALLMULTI) {
2740 sh_eth_tsu_purge_mcast(ndev);
2741 ecmr_bits &= ~ECMR_MCT;
2742 mcast_all = 1;
2743 }
2744
2745 if (ndev->flags & IFF_PROMISC) {
2746 sh_eth_tsu_purge_all(ndev);
2747 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2748 } else if (mdp->cd->tsu) {
2749 struct netdev_hw_addr *ha;
2750 netdev_for_each_mc_addr(ha, ndev) {
2751 if (mcast_all && is_multicast_ether_addr(ha->addr))
2752 continue;
2753
2754 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2755 if (!mcast_all) {
2756 sh_eth_tsu_purge_mcast(ndev);
2757 ecmr_bits &= ~ECMR_MCT;
2758 mcast_all = 1;
2759 }
2760 }
2761 }
2762 }
2763
2764 /* update the ethernet mode */
2765 sh_eth_write(ndev, ecmr_bits, ECMR);
2766
2767 spin_unlock_irqrestore(&mdp->lock, flags);
2768 }
2769
2770 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2771 {
2772 if (!mdp->port)
2773 return TSU_VTAG0;
2774 else
2775 return TSU_VTAG1;
2776 }
2777
2778 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2779 __be16 proto, u16 vid)
2780 {
2781 struct sh_eth_private *mdp = netdev_priv(ndev);
2782 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2783
2784 if (unlikely(!mdp->cd->tsu))
2785 return -EPERM;
2786
2787 /* No filtering if vid = 0 */
2788 if (!vid)
2789 return 0;
2790
2791 mdp->vlan_num_ids++;
2792
2793 /* The controller has one VLAN tag HW filter. So, if the filter is
2794 * already enabled, the driver disables it and the filte
2795 */
2796 if (mdp->vlan_num_ids > 1) {
2797 /* disable VLAN filter */
2798 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2799 return 0;
2800 }
2801
2802 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2803 vtag_reg_index);
2804
2805 return 0;
2806 }
2807
2808 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2809 __be16 proto, u16 vid)
2810 {
2811 struct sh_eth_private *mdp = netdev_priv(ndev);
2812 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2813
2814 if (unlikely(!mdp->cd->tsu))
2815 return -EPERM;
2816
2817 /* No filtering if vid = 0 */
2818 if (!vid)
2819 return 0;
2820
2821 mdp->vlan_num_ids--;
2822 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2823
2824 return 0;
2825 }
2826
2827 /* SuperH's TSU register init function */
2828 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2829 {
2830 if (sh_eth_is_rz_fast_ether(mdp)) {
2831 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2832 return;
2833 }
2834
2835 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2836 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2837 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2838 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2839 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2840 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2841 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2842 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2843 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2844 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2845 if (sh_eth_is_gether(mdp)) {
2846 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2847 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2848 } else {
2849 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2850 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2851 }
2852 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2853 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2854 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2855 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2856 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2857 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2858 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
2859 }
2860
2861 /* MDIO bus release function */
2862 static int sh_mdio_release(struct sh_eth_private *mdp)
2863 {
2864 /* unregister mdio bus */
2865 mdiobus_unregister(mdp->mii_bus);
2866
2867 /* free bitbang info */
2868 free_mdio_bitbang(mdp->mii_bus);
2869
2870 return 0;
2871 }
2872
2873 /* MDIO bus init function */
2874 static int sh_mdio_init(struct sh_eth_private *mdp,
2875 struct sh_eth_plat_data *pd)
2876 {
2877 int ret, i;
2878 struct bb_info *bitbang;
2879 struct platform_device *pdev = mdp->pdev;
2880 struct device *dev = &mdp->pdev->dev;
2881
2882 /* create bit control struct for PHY */
2883 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2884 if (!bitbang)
2885 return -ENOMEM;
2886
2887 /* bitbang init */
2888 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2889 bitbang->set_gate = pd->set_mdio_gate;
2890 bitbang->ctrl.ops = &bb_ops;
2891
2892 /* MII controller setting */
2893 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2894 if (!mdp->mii_bus)
2895 return -ENOMEM;
2896
2897 /* Hook up MII support for ethtool */
2898 mdp->mii_bus->name = "sh_mii";
2899 mdp->mii_bus->parent = dev;
2900 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2901 pdev->name, pdev->id);
2902
2903 /* PHY IRQ */
2904 mdp->mii_bus->irq = devm_kmalloc_array(dev, PHY_MAX_ADDR, sizeof(int),
2905 GFP_KERNEL);
2906 if (!mdp->mii_bus->irq) {
2907 ret = -ENOMEM;
2908 goto out_free_bus;
2909 }
2910
2911 /* register MDIO bus */
2912 if (dev->of_node) {
2913 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2914 } else {
2915 for (i = 0; i < PHY_MAX_ADDR; i++)
2916 mdp->mii_bus->irq[i] = PHY_POLL;
2917 if (pd->phy_irq > 0)
2918 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2919
2920 ret = mdiobus_register(mdp->mii_bus);
2921 }
2922
2923 if (ret)
2924 goto out_free_bus;
2925
2926 return 0;
2927
2928 out_free_bus:
2929 free_mdio_bitbang(mdp->mii_bus);
2930 return ret;
2931 }
2932
2933 static const u16 *sh_eth_get_register_offset(int register_type)
2934 {
2935 const u16 *reg_offset = NULL;
2936
2937 switch (register_type) {
2938 case SH_ETH_REG_GIGABIT:
2939 reg_offset = sh_eth_offset_gigabit;
2940 break;
2941 case SH_ETH_REG_FAST_RZ:
2942 reg_offset = sh_eth_offset_fast_rz;
2943 break;
2944 case SH_ETH_REG_FAST_RCAR:
2945 reg_offset = sh_eth_offset_fast_rcar;
2946 break;
2947 case SH_ETH_REG_FAST_SH4:
2948 reg_offset = sh_eth_offset_fast_sh4;
2949 break;
2950 case SH_ETH_REG_FAST_SH3_SH2:
2951 reg_offset = sh_eth_offset_fast_sh3_sh2;
2952 break;
2953 default:
2954 break;
2955 }
2956
2957 return reg_offset;
2958 }
2959
2960 static const struct net_device_ops sh_eth_netdev_ops = {
2961 .ndo_open = sh_eth_open,
2962 .ndo_stop = sh_eth_close,
2963 .ndo_start_xmit = sh_eth_start_xmit,
2964 .ndo_get_stats = sh_eth_get_stats,
2965 .ndo_set_rx_mode = sh_eth_set_rx_mode,
2966 .ndo_tx_timeout = sh_eth_tx_timeout,
2967 .ndo_do_ioctl = sh_eth_do_ioctl,
2968 .ndo_validate_addr = eth_validate_addr,
2969 .ndo_set_mac_address = eth_mac_addr,
2970 .ndo_change_mtu = eth_change_mtu,
2971 };
2972
2973 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2974 .ndo_open = sh_eth_open,
2975 .ndo_stop = sh_eth_close,
2976 .ndo_start_xmit = sh_eth_start_xmit,
2977 .ndo_get_stats = sh_eth_get_stats,
2978 .ndo_set_rx_mode = sh_eth_set_rx_mode,
2979 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2980 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2981 .ndo_tx_timeout = sh_eth_tx_timeout,
2982 .ndo_do_ioctl = sh_eth_do_ioctl,
2983 .ndo_validate_addr = eth_validate_addr,
2984 .ndo_set_mac_address = eth_mac_addr,
2985 .ndo_change_mtu = eth_change_mtu,
2986 };
2987
2988 #ifdef CONFIG_OF
2989 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2990 {
2991 struct device_node *np = dev->of_node;
2992 struct sh_eth_plat_data *pdata;
2993 const char *mac_addr;
2994
2995 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2996 if (!pdata)
2997 return NULL;
2998
2999 pdata->phy_interface = of_get_phy_mode(np);
3000
3001 mac_addr = of_get_mac_address(np);
3002 if (mac_addr)
3003 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3004
3005 pdata->no_ether_link =
3006 of_property_read_bool(np, "renesas,no-ether-link");
3007 pdata->ether_link_active_low =
3008 of_property_read_bool(np, "renesas,ether-link-active-low");
3009
3010 return pdata;
3011 }
3012
3013 static const struct of_device_id sh_eth_match_table[] = {
3014 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3015 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
3016 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
3017 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
3018 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
3019 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
3020 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
3021 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3022 { }
3023 };
3024 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3025 #else
3026 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3027 {
3028 return NULL;
3029 }
3030 #endif
3031
3032 static int sh_eth_drv_probe(struct platform_device *pdev)
3033 {
3034 int ret, devno = 0;
3035 struct resource *res;
3036 struct net_device *ndev = NULL;
3037 struct sh_eth_private *mdp = NULL;
3038 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3039 const struct platform_device_id *id = platform_get_device_id(pdev);
3040
3041 /* get base addr */
3042 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3043
3044 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3045 if (!ndev)
3046 return -ENOMEM;
3047
3048 pm_runtime_enable(&pdev->dev);
3049 pm_runtime_get_sync(&pdev->dev);
3050
3051 devno = pdev->id;
3052 if (devno < 0)
3053 devno = 0;
3054
3055 ndev->dma = -1;
3056 ret = platform_get_irq(pdev, 0);
3057 if (ret < 0)
3058 goto out_release;
3059 ndev->irq = ret;
3060
3061 SET_NETDEV_DEV(ndev, &pdev->dev);
3062
3063 mdp = netdev_priv(ndev);
3064 mdp->num_tx_ring = TX_RING_SIZE;
3065 mdp->num_rx_ring = RX_RING_SIZE;
3066 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3067 if (IS_ERR(mdp->addr)) {
3068 ret = PTR_ERR(mdp->addr);
3069 goto out_release;
3070 }
3071
3072 ndev->base_addr = res->start;
3073
3074 spin_lock_init(&mdp->lock);
3075 mdp->pdev = pdev;
3076
3077 if (pdev->dev.of_node)
3078 pd = sh_eth_parse_dt(&pdev->dev);
3079 if (!pd) {
3080 dev_err(&pdev->dev, "no platform data\n");
3081 ret = -EINVAL;
3082 goto out_release;
3083 }
3084
3085 /* get PHY ID */
3086 mdp->phy_id = pd->phy;
3087 mdp->phy_interface = pd->phy_interface;
3088 mdp->no_ether_link = pd->no_ether_link;
3089 mdp->ether_link_active_low = pd->ether_link_active_low;
3090
3091 /* set cpu data */
3092 if (id) {
3093 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3094 } else {
3095 const struct of_device_id *match;
3096
3097 match = of_match_device(of_match_ptr(sh_eth_match_table),
3098 &pdev->dev);
3099 mdp->cd = (struct sh_eth_cpu_data *)match->data;
3100 }
3101 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3102 if (!mdp->reg_offset) {
3103 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3104 mdp->cd->register_type);
3105 ret = -EINVAL;
3106 goto out_release;
3107 }
3108 sh_eth_set_default_cpu_data(mdp->cd);
3109
3110 /* set function */
3111 if (mdp->cd->tsu)
3112 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3113 else
3114 ndev->netdev_ops = &sh_eth_netdev_ops;
3115 ndev->ethtool_ops = &sh_eth_ethtool_ops;
3116 ndev->watchdog_timeo = TX_TIMEOUT;
3117
3118 /* debug message level */
3119 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3120
3121 /* read and set MAC address */
3122 read_mac_address(ndev, pd->mac_addr);
3123 if (!is_valid_ether_addr(ndev->dev_addr)) {
3124 dev_warn(&pdev->dev,
3125 "no valid MAC address supplied, using a random one.\n");
3126 eth_hw_addr_random(ndev);
3127 }
3128
3129 /* ioremap the TSU registers */
3130 if (mdp->cd->tsu) {
3131 struct resource *rtsu;
3132 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3133 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3134 if (IS_ERR(mdp->tsu_addr)) {
3135 ret = PTR_ERR(mdp->tsu_addr);
3136 goto out_release;
3137 }
3138 mdp->port = devno % 2;
3139 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3140 }
3141
3142 /* initialize first or needed device */
3143 if (!devno || pd->needs_init) {
3144 if (mdp->cd->chip_reset)
3145 mdp->cd->chip_reset(ndev);
3146
3147 if (mdp->cd->tsu) {
3148 /* TSU init (Init only)*/
3149 sh_eth_tsu_init(mdp);
3150 }
3151 }
3152
3153 if (mdp->cd->rmiimode)
3154 sh_eth_write(ndev, 0x1, RMIIMODE);
3155
3156 /* MDIO bus init */
3157 ret = sh_mdio_init(mdp, pd);
3158 if (ret) {
3159 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3160 goto out_release;
3161 }
3162
3163 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3164
3165 /* network device register */
3166 ret = register_netdev(ndev);
3167 if (ret)
3168 goto out_napi_del;
3169
3170 /* print device information */
3171 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3172 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3173
3174 pm_runtime_put(&pdev->dev);
3175 platform_set_drvdata(pdev, ndev);
3176
3177 return ret;
3178
3179 out_napi_del:
3180 netif_napi_del(&mdp->napi);
3181 sh_mdio_release(mdp);
3182
3183 out_release:
3184 /* net_dev free */
3185 if (ndev)
3186 free_netdev(ndev);
3187
3188 pm_runtime_put(&pdev->dev);
3189 pm_runtime_disable(&pdev->dev);
3190 return ret;
3191 }
3192
3193 static int sh_eth_drv_remove(struct platform_device *pdev)
3194 {
3195 struct net_device *ndev = platform_get_drvdata(pdev);
3196 struct sh_eth_private *mdp = netdev_priv(ndev);
3197
3198 unregister_netdev(ndev);
3199 netif_napi_del(&mdp->napi);
3200 sh_mdio_release(mdp);
3201 pm_runtime_disable(&pdev->dev);
3202 free_netdev(ndev);
3203
3204 return 0;
3205 }
3206
3207 #ifdef CONFIG_PM
3208 #ifdef CONFIG_PM_SLEEP
3209 static int sh_eth_suspend(struct device *dev)
3210 {
3211 struct net_device *ndev = dev_get_drvdata(dev);
3212 int ret = 0;
3213
3214 if (netif_running(ndev)) {
3215 netif_device_detach(ndev);
3216 ret = sh_eth_close(ndev);
3217 }
3218
3219 return ret;
3220 }
3221
3222 static int sh_eth_resume(struct device *dev)
3223 {
3224 struct net_device *ndev = dev_get_drvdata(dev);
3225 int ret = 0;
3226
3227 if (netif_running(ndev)) {
3228 ret = sh_eth_open(ndev);
3229 if (ret < 0)
3230 return ret;
3231 netif_device_attach(ndev);
3232 }
3233
3234 return ret;
3235 }
3236 #endif
3237
3238 static int sh_eth_runtime_nop(struct device *dev)
3239 {
3240 /* Runtime PM callback shared between ->runtime_suspend()
3241 * and ->runtime_resume(). Simply returns success.
3242 *
3243 * This driver re-initializes all registers after
3244 * pm_runtime_get_sync() anyway so there is no need
3245 * to save and restore registers here.
3246 */
3247 return 0;
3248 }
3249
3250 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3251 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3252 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3253 };
3254 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3255 #else
3256 #define SH_ETH_PM_OPS NULL
3257 #endif
3258
3259 static struct platform_device_id sh_eth_id_table[] = {
3260 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3261 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3262 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3263 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3264 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3265 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3266 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3267 { }
3268 };
3269 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3270
3271 static struct platform_driver sh_eth_driver = {
3272 .probe = sh_eth_drv_probe,
3273 .remove = sh_eth_drv_remove,
3274 .id_table = sh_eth_id_table,
3275 .driver = {
3276 .name = CARDNAME,
3277 .pm = SH_ETH_PM_OPS,
3278 .of_match_table = of_match_ptr(sh_eth_match_table),
3279 },
3280 };
3281
3282 module_platform_driver(sh_eth_driver);
3283
3284 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3285 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3286 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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