2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/cpu.h>
20 #include <linux/delay.h>
21 #include <linux/errno.h>
23 #include <linux/genhd.h>
24 #include <linux/hdreg.h>
25 #include <linux/idr.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
29 #include <linux/kdev_t.h>
30 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/mutex.h>
35 #include <linux/pci.h>
36 #include <linux/poison.h>
37 #include <linux/ptrace.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/t10-pi.h>
41 #include <linux/timer.h>
42 #include <linux/types.h>
43 #include <linux/io-64-nonatomic-lo-hi.h>
44 #include <asm/unaligned.h>
48 #define NVME_Q_DEPTH 1024
49 #define NVME_AQ_DEPTH 256
50 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
51 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
54 * We handle AEN commands ourselves and don't even let the
55 * block layer know about them.
57 #define NVME_NR_AEN_COMMANDS 1
58 #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
60 static int use_threaded_interrupts
;
61 module_param(use_threaded_interrupts
, int, 0);
63 static bool use_cmb_sqes
= true;
64 module_param(use_cmb_sqes
, bool, 0644);
65 MODULE_PARM_DESC(use_cmb_sqes
, "use controller's memory buffer for I/O SQes");
67 static struct workqueue_struct
*nvme_workq
;
72 static int nvme_reset(struct nvme_dev
*dev
);
73 static void nvme_process_cq(struct nvme_queue
*nvmeq
);
74 static void nvme_remove_dead_ctrl(struct nvme_dev
*dev
);
75 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
);
78 * Represents an NVM Express device. Each nvme_dev is a PCI function.
81 struct nvme_queue
**queues
;
82 struct blk_mq_tag_set tagset
;
83 struct blk_mq_tag_set admin_tagset
;
86 struct dma_pool
*prp_page_pool
;
87 struct dma_pool
*prp_small_pool
;
89 unsigned online_queues
;
93 struct msix_entry
*entry
;
95 struct work_struct reset_work
;
96 struct work_struct scan_work
;
97 struct work_struct remove_work
;
98 struct work_struct async_work
;
99 struct timer_list watchdog_timer
;
100 struct mutex shutdown_lock
;
103 dma_addr_t cmb_dma_addr
;
108 #define NVME_CTRL_RESETTING 0
110 struct nvme_ctrl ctrl
;
111 struct completion ioq_wait
;
114 static inline struct nvme_dev
*to_nvme_dev(struct nvme_ctrl
*ctrl
)
116 return container_of(ctrl
, struct nvme_dev
, ctrl
);
120 * An NVM Express queue. Each device has at least two (one for admin
121 * commands and one for I/O commands).
124 struct device
*q_dmadev
;
125 struct nvme_dev
*dev
;
126 char irqname
[24]; /* nvme4294967295-65535\0 */
128 struct nvme_command
*sq_cmds
;
129 struct nvme_command __iomem
*sq_cmds_io
;
130 volatile struct nvme_completion
*cqes
;
131 struct blk_mq_tags
**tags
;
132 dma_addr_t sq_dma_addr
;
133 dma_addr_t cq_dma_addr
;
146 * The nvme_iod describes the data in an I/O, including the list of PRP
147 * entries. You can't see it in this data structure because C doesn't let
148 * me express that. Use nvme_init_iod to ensure there's enough space
149 * allocated to store the PRP list.
152 struct nvme_queue
*nvmeq
;
154 int npages
; /* In the PRP list. 0 means small pool in use */
155 int nents
; /* Used in scatterlist */
156 int length
; /* Of data, in bytes */
157 dma_addr_t first_dma
;
158 struct scatterlist meta_sg
; /* metadata requires single contiguous buffer */
159 struct scatterlist
*sg
;
160 struct scatterlist inline_sg
[0];
164 * Check we didin't inadvertently grow the command struct
166 static inline void _nvme_check_size(void)
168 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
169 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
170 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
171 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
172 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
173 BUILD_BUG_ON(sizeof(struct nvme_format_cmd
) != 64);
174 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd
) != 64);
175 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
176 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != 4096);
177 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != 4096);
178 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
179 BUILD_BUG_ON(sizeof(struct nvme_smart_log
) != 512);
183 * Max size of iod being embedded in the request payload
185 #define NVME_INT_PAGES 2
186 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
189 * Will slightly overestimate the number of pages needed. This is OK
190 * as it only leads to a small amount of wasted memory for the lifetime of
193 static int nvme_npages(unsigned size
, struct nvme_dev
*dev
)
195 unsigned nprps
= DIV_ROUND_UP(size
+ dev
->ctrl
.page_size
,
196 dev
->ctrl
.page_size
);
197 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
200 static unsigned int nvme_iod_alloc_size(struct nvme_dev
*dev
,
201 unsigned int size
, unsigned int nseg
)
203 return sizeof(__le64
*) * nvme_npages(size
, dev
) +
204 sizeof(struct scatterlist
) * nseg
;
207 static unsigned int nvme_cmd_size(struct nvme_dev
*dev
)
209 return sizeof(struct nvme_iod
) +
210 nvme_iod_alloc_size(dev
, NVME_INT_BYTES(dev
), NVME_INT_PAGES
);
213 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
214 unsigned int hctx_idx
)
216 struct nvme_dev
*dev
= data
;
217 struct nvme_queue
*nvmeq
= dev
->queues
[0];
219 WARN_ON(hctx_idx
!= 0);
220 WARN_ON(dev
->admin_tagset
.tags
[0] != hctx
->tags
);
221 WARN_ON(nvmeq
->tags
);
223 hctx
->driver_data
= nvmeq
;
224 nvmeq
->tags
= &dev
->admin_tagset
.tags
[0];
228 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx
*hctx
, unsigned int hctx_idx
)
230 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
235 static int nvme_admin_init_request(void *data
, struct request
*req
,
236 unsigned int hctx_idx
, unsigned int rq_idx
,
237 unsigned int numa_node
)
239 struct nvme_dev
*dev
= data
;
240 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
241 struct nvme_queue
*nvmeq
= dev
->queues
[0];
248 static int nvme_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
249 unsigned int hctx_idx
)
251 struct nvme_dev
*dev
= data
;
252 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
255 nvmeq
->tags
= &dev
->tagset
.tags
[hctx_idx
];
257 WARN_ON(dev
->tagset
.tags
[hctx_idx
] != hctx
->tags
);
258 hctx
->driver_data
= nvmeq
;
262 static int nvme_init_request(void *data
, struct request
*req
,
263 unsigned int hctx_idx
, unsigned int rq_idx
,
264 unsigned int numa_node
)
266 struct nvme_dev
*dev
= data
;
267 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
268 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
275 static void nvme_complete_async_event(struct nvme_dev
*dev
,
276 struct nvme_completion
*cqe
)
278 u16 status
= le16_to_cpu(cqe
->status
) >> 1;
279 u32 result
= le32_to_cpu(cqe
->result
);
281 if (status
== NVME_SC_SUCCESS
|| status
== NVME_SC_ABORT_REQ
) {
282 ++dev
->ctrl
.event_limit
;
283 queue_work(nvme_workq
, &dev
->async_work
);
286 if (status
!= NVME_SC_SUCCESS
)
289 switch (result
& 0xff07) {
290 case NVME_AER_NOTICE_NS_CHANGED
:
291 dev_info(dev
->ctrl
.device
, "rescanning\n");
292 queue_work(nvme_workq
, &dev
->scan_work
);
294 dev_warn(dev
->ctrl
.device
, "async event result %08x\n", result
);
299 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
300 * @nvmeq: The queue to use
301 * @cmd: The command to send
303 * Safe to use from interrupt context
305 static void __nvme_submit_cmd(struct nvme_queue
*nvmeq
,
306 struct nvme_command
*cmd
)
308 u16 tail
= nvmeq
->sq_tail
;
310 if (nvmeq
->sq_cmds_io
)
311 memcpy_toio(&nvmeq
->sq_cmds_io
[tail
], cmd
, sizeof(*cmd
));
313 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
315 if (++tail
== nvmeq
->q_depth
)
317 writel(tail
, nvmeq
->q_db
);
318 nvmeq
->sq_tail
= tail
;
321 static __le64
**iod_list(struct request
*req
)
323 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
324 return (__le64
**)(iod
->sg
+ req
->nr_phys_segments
);
327 static int nvme_init_iod(struct request
*rq
, struct nvme_dev
*dev
)
329 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(rq
);
330 int nseg
= rq
->nr_phys_segments
;
333 if (rq
->cmd_flags
& REQ_DISCARD
)
334 size
= sizeof(struct nvme_dsm_range
);
336 size
= blk_rq_bytes(rq
);
338 if (nseg
> NVME_INT_PAGES
|| size
> NVME_INT_BYTES(dev
)) {
339 iod
->sg
= kmalloc(nvme_iod_alloc_size(dev
, size
, nseg
), GFP_ATOMIC
);
341 return BLK_MQ_RQ_QUEUE_BUSY
;
343 iod
->sg
= iod
->inline_sg
;
353 static void nvme_free_iod(struct nvme_dev
*dev
, struct request
*req
)
355 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
356 const int last_prp
= dev
->ctrl
.page_size
/ 8 - 1;
358 __le64
**list
= iod_list(req
);
359 dma_addr_t prp_dma
= iod
->first_dma
;
361 if (iod
->npages
== 0)
362 dma_pool_free(dev
->prp_small_pool
, list
[0], prp_dma
);
363 for (i
= 0; i
< iod
->npages
; i
++) {
364 __le64
*prp_list
= list
[i
];
365 dma_addr_t next_prp_dma
= le64_to_cpu(prp_list
[last_prp
]);
366 dma_pool_free(dev
->prp_page_pool
, prp_list
, prp_dma
);
367 prp_dma
= next_prp_dma
;
370 if (iod
->sg
!= iod
->inline_sg
)
374 #ifdef CONFIG_BLK_DEV_INTEGRITY
375 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
377 if (be32_to_cpu(pi
->ref_tag
) == v
)
378 pi
->ref_tag
= cpu_to_be32(p
);
381 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
383 if (be32_to_cpu(pi
->ref_tag
) == p
)
384 pi
->ref_tag
= cpu_to_be32(v
);
388 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
390 * The virtual start sector is the one that was originally submitted by the
391 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
392 * start sector may be different. Remap protection information to match the
393 * physical LBA on writes, and back to the original seed on reads.
395 * Type 0 and 3 do not have a ref tag, so no remapping required.
397 static void nvme_dif_remap(struct request
*req
,
398 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
400 struct nvme_ns
*ns
= req
->rq_disk
->private_data
;
401 struct bio_integrity_payload
*bip
;
402 struct t10_pi_tuple
*pi
;
404 u32 i
, nlb
, ts
, phys
, virt
;
406 if (!ns
->pi_type
|| ns
->pi_type
== NVME_NS_DPS_PI_TYPE3
)
409 bip
= bio_integrity(req
->bio
);
413 pmap
= kmap_atomic(bip
->bip_vec
->bv_page
) + bip
->bip_vec
->bv_offset
;
416 virt
= bip_get_seed(bip
);
417 phys
= nvme_block_nr(ns
, blk_rq_pos(req
));
418 nlb
= (blk_rq_bytes(req
) >> ns
->lba_shift
);
419 ts
= ns
->disk
->queue
->integrity
.tuple_size
;
421 for (i
= 0; i
< nlb
; i
++, virt
++, phys
++) {
422 pi
= (struct t10_pi_tuple
*)p
;
423 dif_swap(phys
, virt
, pi
);
428 #else /* CONFIG_BLK_DEV_INTEGRITY */
429 static void nvme_dif_remap(struct request
*req
,
430 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
433 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
436 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
441 static bool nvme_setup_prps(struct nvme_dev
*dev
, struct request
*req
,
444 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
445 struct dma_pool
*pool
;
446 int length
= total_len
;
447 struct scatterlist
*sg
= iod
->sg
;
448 int dma_len
= sg_dma_len(sg
);
449 u64 dma_addr
= sg_dma_address(sg
);
450 u32 page_size
= dev
->ctrl
.page_size
;
451 int offset
= dma_addr
& (page_size
- 1);
453 __le64
**list
= iod_list(req
);
457 length
-= (page_size
- offset
);
461 dma_len
-= (page_size
- offset
);
463 dma_addr
+= (page_size
- offset
);
466 dma_addr
= sg_dma_address(sg
);
467 dma_len
= sg_dma_len(sg
);
470 if (length
<= page_size
) {
471 iod
->first_dma
= dma_addr
;
475 nprps
= DIV_ROUND_UP(length
, page_size
);
476 if (nprps
<= (256 / 8)) {
477 pool
= dev
->prp_small_pool
;
480 pool
= dev
->prp_page_pool
;
484 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
486 iod
->first_dma
= dma_addr
;
491 iod
->first_dma
= prp_dma
;
494 if (i
== page_size
>> 3) {
495 __le64
*old_prp_list
= prp_list
;
496 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
499 list
[iod
->npages
++] = prp_list
;
500 prp_list
[0] = old_prp_list
[i
- 1];
501 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
504 prp_list
[i
++] = cpu_to_le64(dma_addr
);
505 dma_len
-= page_size
;
506 dma_addr
+= page_size
;
514 dma_addr
= sg_dma_address(sg
);
515 dma_len
= sg_dma_len(sg
);
521 static int nvme_map_data(struct nvme_dev
*dev
, struct request
*req
,
522 struct nvme_command
*cmnd
)
524 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
525 struct request_queue
*q
= req
->q
;
526 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
527 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
528 int ret
= BLK_MQ_RQ_QUEUE_ERROR
;
530 sg_init_table(iod
->sg
, req
->nr_phys_segments
);
531 iod
->nents
= blk_rq_map_sg(q
, req
, iod
->sg
);
535 ret
= BLK_MQ_RQ_QUEUE_BUSY
;
536 if (!dma_map_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
))
539 if (!nvme_setup_prps(dev
, req
, blk_rq_bytes(req
)))
542 ret
= BLK_MQ_RQ_QUEUE_ERROR
;
543 if (blk_integrity_rq(req
)) {
544 if (blk_rq_count_integrity_sg(q
, req
->bio
) != 1)
547 sg_init_table(&iod
->meta_sg
, 1);
548 if (blk_rq_map_integrity_sg(q
, req
->bio
, &iod
->meta_sg
) != 1)
551 if (rq_data_dir(req
))
552 nvme_dif_remap(req
, nvme_dif_prep
);
554 if (!dma_map_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
))
558 cmnd
->rw
.prp1
= cpu_to_le64(sg_dma_address(iod
->sg
));
559 cmnd
->rw
.prp2
= cpu_to_le64(iod
->first_dma
);
560 if (blk_integrity_rq(req
))
561 cmnd
->rw
.metadata
= cpu_to_le64(sg_dma_address(&iod
->meta_sg
));
562 return BLK_MQ_RQ_QUEUE_OK
;
565 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
570 static void nvme_unmap_data(struct nvme_dev
*dev
, struct request
*req
)
572 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
573 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
574 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
577 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
578 if (blk_integrity_rq(req
)) {
579 if (!rq_data_dir(req
))
580 nvme_dif_remap(req
, nvme_dif_complete
);
581 dma_unmap_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
);
585 nvme_free_iod(dev
, req
);
589 * We reuse the small pool to allocate the 16-byte range here as it is not
590 * worth having a special pool for these or additional cases to handle freeing
593 static int nvme_setup_discard(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
,
594 struct request
*req
, struct nvme_command
*cmnd
)
596 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
597 struct nvme_dsm_range
*range
;
599 range
= dma_pool_alloc(nvmeq
->dev
->prp_small_pool
, GFP_ATOMIC
,
602 return BLK_MQ_RQ_QUEUE_BUSY
;
603 iod_list(req
)[0] = (__le64
*)range
;
606 range
->cattr
= cpu_to_le32(0);
607 range
->nlb
= cpu_to_le32(blk_rq_bytes(req
) >> ns
->lba_shift
);
608 range
->slba
= cpu_to_le64(nvme_block_nr(ns
, blk_rq_pos(req
)));
610 memset(cmnd
, 0, sizeof(*cmnd
));
611 cmnd
->dsm
.opcode
= nvme_cmd_dsm
;
612 cmnd
->dsm
.nsid
= cpu_to_le32(ns
->ns_id
);
613 cmnd
->dsm
.prp1
= cpu_to_le64(iod
->first_dma
);
615 cmnd
->dsm
.attributes
= cpu_to_le32(NVME_DSMGMT_AD
);
616 return BLK_MQ_RQ_QUEUE_OK
;
620 * NOTE: ns is NULL when called on the admin queue.
622 static int nvme_queue_rq(struct blk_mq_hw_ctx
*hctx
,
623 const struct blk_mq_queue_data
*bd
)
625 struct nvme_ns
*ns
= hctx
->queue
->queuedata
;
626 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
627 struct nvme_dev
*dev
= nvmeq
->dev
;
628 struct request
*req
= bd
->rq
;
629 struct nvme_command cmnd
;
630 int ret
= BLK_MQ_RQ_QUEUE_OK
;
633 * If formated with metadata, require the block layer provide a buffer
634 * unless this namespace is formated such that the metadata can be
635 * stripped/generated by the controller with PRACT=1.
637 if (ns
&& ns
->ms
&& !blk_integrity_rq(req
)) {
638 if (!(ns
->pi_type
&& ns
->ms
== 8) &&
639 req
->cmd_type
!= REQ_TYPE_DRV_PRIV
) {
640 blk_mq_end_request(req
, -EFAULT
);
641 return BLK_MQ_RQ_QUEUE_OK
;
645 ret
= nvme_init_iod(req
, dev
);
649 if (req
->cmd_flags
& REQ_DISCARD
) {
650 ret
= nvme_setup_discard(nvmeq
, ns
, req
, &cmnd
);
652 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
)
653 memcpy(&cmnd
, req
->cmd
, sizeof(cmnd
));
654 else if (req
->cmd_flags
& REQ_FLUSH
)
655 nvme_setup_flush(ns
, &cmnd
);
657 nvme_setup_rw(ns
, req
, &cmnd
);
659 if (req
->nr_phys_segments
)
660 ret
= nvme_map_data(dev
, req
, &cmnd
);
666 cmnd
.common
.command_id
= req
->tag
;
667 blk_mq_start_request(req
);
669 spin_lock_irq(&nvmeq
->q_lock
);
670 __nvme_submit_cmd(nvmeq
, &cmnd
);
671 nvme_process_cq(nvmeq
);
672 spin_unlock_irq(&nvmeq
->q_lock
);
673 return BLK_MQ_RQ_QUEUE_OK
;
675 nvme_free_iod(dev
, req
);
679 static void nvme_complete_rq(struct request
*req
)
681 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
682 struct nvme_dev
*dev
= iod
->nvmeq
->dev
;
685 nvme_unmap_data(dev
, req
);
687 if (unlikely(req
->errors
)) {
688 if (nvme_req_needs_retry(req
, req
->errors
)) {
689 nvme_requeue_req(req
);
693 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
)
696 error
= nvme_error_status(req
->errors
);
699 if (unlikely(iod
->aborted
)) {
700 dev_warn(dev
->ctrl
.device
,
701 "completing aborted command with status: %04x\n",
705 blk_mq_end_request(req
, error
);
708 static void __nvme_process_cq(struct nvme_queue
*nvmeq
, unsigned int *tag
)
712 head
= nvmeq
->cq_head
;
713 phase
= nvmeq
->cq_phase
;
716 struct nvme_completion cqe
= nvmeq
->cqes
[head
];
717 u16 status
= le16_to_cpu(cqe
.status
);
720 if ((status
& 1) != phase
)
722 nvmeq
->sq_head
= le16_to_cpu(cqe
.sq_head
);
723 if (++head
== nvmeq
->q_depth
) {
728 if (tag
&& *tag
== cqe
.command_id
)
731 if (unlikely(cqe
.command_id
>= nvmeq
->q_depth
)) {
732 dev_warn(nvmeq
->dev
->ctrl
.device
,
733 "invalid id %d completed on queue %d\n",
734 cqe
.command_id
, le16_to_cpu(cqe
.sq_id
));
739 * AEN requests are special as they don't time out and can
740 * survive any kind of queue freeze and often don't respond to
741 * aborts. We don't even bother to allocate a struct request
742 * for them but rather special case them here.
744 if (unlikely(nvmeq
->qid
== 0 &&
745 cqe
.command_id
>= NVME_AQ_BLKMQ_DEPTH
)) {
746 nvme_complete_async_event(nvmeq
->dev
, &cqe
);
750 req
= blk_mq_tag_to_rq(*nvmeq
->tags
, cqe
.command_id
);
751 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
) {
752 u32 result
= le32_to_cpu(cqe
.result
);
753 req
->special
= (void *)(uintptr_t)result
;
755 blk_mq_complete_request(req
, status
>> 1);
759 /* If the controller ignores the cq head doorbell and continuously
760 * writes to the queue, it is theoretically possible to wrap around
761 * the queue twice and mistakenly return IRQ_NONE. Linux only
762 * requires that 0.1% of your interrupts are handled, so this isn't
765 if (head
== nvmeq
->cq_head
&& phase
== nvmeq
->cq_phase
)
768 if (likely(nvmeq
->cq_vector
>= 0))
769 writel(head
, nvmeq
->q_db
+ nvmeq
->dev
->db_stride
);
770 nvmeq
->cq_head
= head
;
771 nvmeq
->cq_phase
= phase
;
776 static void nvme_process_cq(struct nvme_queue
*nvmeq
)
778 __nvme_process_cq(nvmeq
, NULL
);
781 static irqreturn_t
nvme_irq(int irq
, void *data
)
784 struct nvme_queue
*nvmeq
= data
;
785 spin_lock(&nvmeq
->q_lock
);
786 nvme_process_cq(nvmeq
);
787 result
= nvmeq
->cqe_seen
? IRQ_HANDLED
: IRQ_NONE
;
789 spin_unlock(&nvmeq
->q_lock
);
793 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
795 struct nvme_queue
*nvmeq
= data
;
796 struct nvme_completion cqe
= nvmeq
->cqes
[nvmeq
->cq_head
];
797 if ((le16_to_cpu(cqe
.status
) & 1) != nvmeq
->cq_phase
)
799 return IRQ_WAKE_THREAD
;
802 static int nvme_poll(struct blk_mq_hw_ctx
*hctx
, unsigned int tag
)
804 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
806 if ((le16_to_cpu(nvmeq
->cqes
[nvmeq
->cq_head
].status
) & 1) ==
808 spin_lock_irq(&nvmeq
->q_lock
);
809 __nvme_process_cq(nvmeq
, &tag
);
810 spin_unlock_irq(&nvmeq
->q_lock
);
819 static void nvme_async_event_work(struct work_struct
*work
)
821 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, async_work
);
822 struct nvme_queue
*nvmeq
= dev
->queues
[0];
823 struct nvme_command c
;
825 memset(&c
, 0, sizeof(c
));
826 c
.common
.opcode
= nvme_admin_async_event
;
828 spin_lock_irq(&nvmeq
->q_lock
);
829 while (dev
->ctrl
.event_limit
> 0) {
830 c
.common
.command_id
= NVME_AQ_BLKMQ_DEPTH
+
831 --dev
->ctrl
.event_limit
;
832 __nvme_submit_cmd(nvmeq
, &c
);
834 spin_unlock_irq(&nvmeq
->q_lock
);
837 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
839 struct nvme_command c
;
841 memset(&c
, 0, sizeof(c
));
842 c
.delete_queue
.opcode
= opcode
;
843 c
.delete_queue
.qid
= cpu_to_le16(id
);
845 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
848 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
849 struct nvme_queue
*nvmeq
)
851 struct nvme_command c
;
852 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
855 * Note: we (ab)use the fact the the prp fields survive if no data
856 * is attached to the request.
858 memset(&c
, 0, sizeof(c
));
859 c
.create_cq
.opcode
= nvme_admin_create_cq
;
860 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
861 c
.create_cq
.cqid
= cpu_to_le16(qid
);
862 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
863 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
864 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
866 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
869 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
870 struct nvme_queue
*nvmeq
)
872 struct nvme_command c
;
873 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_SQ_PRIO_MEDIUM
;
876 * Note: we (ab)use the fact the the prp fields survive if no data
877 * is attached to the request.
879 memset(&c
, 0, sizeof(c
));
880 c
.create_sq
.opcode
= nvme_admin_create_sq
;
881 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
882 c
.create_sq
.sqid
= cpu_to_le16(qid
);
883 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
884 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
885 c
.create_sq
.cqid
= cpu_to_le16(qid
);
887 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
890 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
892 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
895 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
897 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
900 static void abort_endio(struct request
*req
, int error
)
902 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
903 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
904 u32 result
= (u32
)(uintptr_t)req
->special
;
905 u16 status
= req
->errors
;
907 dev_warn(nvmeq
->dev
->ctrl
.device
,
908 "Abort status:%x result:%x", status
, result
);
909 atomic_inc(&nvmeq
->dev
->ctrl
.abort_limit
);
911 blk_mq_free_request(req
);
914 static enum blk_eh_timer_return
nvme_timeout(struct request
*req
, bool reserved
)
916 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
917 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
918 struct nvme_dev
*dev
= nvmeq
->dev
;
919 struct request
*abort_req
;
920 struct nvme_command cmd
;
923 * Shutdown immediately if controller times out while starting. The
924 * reset work will see the pci device disabled when it gets the forced
925 * cancellation error. All outstanding requests are completed on
926 * shutdown, so we return BLK_EH_HANDLED.
928 if (test_bit(NVME_CTRL_RESETTING
, &dev
->flags
)) {
929 dev_warn(dev
->ctrl
.device
,
930 "I/O %d QID %d timeout, disable controller\n",
931 req
->tag
, nvmeq
->qid
);
932 nvme_dev_disable(dev
, false);
933 req
->errors
= NVME_SC_CANCELLED
;
934 return BLK_EH_HANDLED
;
938 * Shutdown the controller immediately and schedule a reset if the
939 * command was already aborted once before and still hasn't been
940 * returned to the driver, or if this is the admin queue.
942 if (!nvmeq
->qid
|| iod
->aborted
) {
943 dev_warn(dev
->ctrl
.device
,
944 "I/O %d QID %d timeout, reset controller\n",
945 req
->tag
, nvmeq
->qid
);
946 nvme_dev_disable(dev
, false);
947 queue_work(nvme_workq
, &dev
->reset_work
);
950 * Mark the request as handled, since the inline shutdown
951 * forces all outstanding requests to complete.
953 req
->errors
= NVME_SC_CANCELLED
;
954 return BLK_EH_HANDLED
;
959 if (atomic_dec_return(&dev
->ctrl
.abort_limit
) < 0) {
960 atomic_inc(&dev
->ctrl
.abort_limit
);
961 return BLK_EH_RESET_TIMER
;
964 memset(&cmd
, 0, sizeof(cmd
));
965 cmd
.abort
.opcode
= nvme_admin_abort_cmd
;
966 cmd
.abort
.cid
= req
->tag
;
967 cmd
.abort
.sqid
= cpu_to_le16(nvmeq
->qid
);
969 dev_warn(nvmeq
->dev
->ctrl
.device
,
970 "I/O %d QID %d timeout, aborting\n",
971 req
->tag
, nvmeq
->qid
);
973 abort_req
= nvme_alloc_request(dev
->ctrl
.admin_q
, &cmd
,
975 if (IS_ERR(abort_req
)) {
976 atomic_inc(&dev
->ctrl
.abort_limit
);
977 return BLK_EH_RESET_TIMER
;
980 abort_req
->timeout
= ADMIN_TIMEOUT
;
981 abort_req
->end_io_data
= NULL
;
982 blk_execute_rq_nowait(abort_req
->q
, NULL
, abort_req
, 0, abort_endio
);
985 * The aborted req will be completed on receiving the abort req.
986 * We enable the timer again. If hit twice, it'll cause a device reset,
987 * as the device then is in a faulty state.
989 return BLK_EH_RESET_TIMER
;
992 static void nvme_cancel_queue_ios(struct request
*req
, void *data
, bool reserved
)
994 struct nvme_queue
*nvmeq
= data
;
997 if (!blk_mq_request_started(req
))
1000 dev_warn(nvmeq
->dev
->ctrl
.device
,
1001 "Cancelling I/O %d QID %d\n", req
->tag
, nvmeq
->qid
);
1003 status
= NVME_SC_ABORT_REQ
;
1004 if (blk_queue_dying(req
->q
))
1005 status
|= NVME_SC_DNR
;
1006 blk_mq_complete_request(req
, status
);
1009 static void nvme_free_queue(struct nvme_queue
*nvmeq
)
1011 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
1012 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
1014 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
1015 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
1019 static void nvme_free_queues(struct nvme_dev
*dev
, int lowest
)
1023 for (i
= dev
->queue_count
- 1; i
>= lowest
; i
--) {
1024 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1026 dev
->queues
[i
] = NULL
;
1027 nvme_free_queue(nvmeq
);
1032 * nvme_suspend_queue - put queue into suspended state
1033 * @nvmeq - queue to suspend
1035 static int nvme_suspend_queue(struct nvme_queue
*nvmeq
)
1039 spin_lock_irq(&nvmeq
->q_lock
);
1040 if (nvmeq
->cq_vector
== -1) {
1041 spin_unlock_irq(&nvmeq
->q_lock
);
1044 vector
= nvmeq
->dev
->entry
[nvmeq
->cq_vector
].vector
;
1045 nvmeq
->dev
->online_queues
--;
1046 nvmeq
->cq_vector
= -1;
1047 spin_unlock_irq(&nvmeq
->q_lock
);
1049 if (!nvmeq
->qid
&& nvmeq
->dev
->ctrl
.admin_q
)
1050 blk_mq_stop_hw_queues(nvmeq
->dev
->ctrl
.admin_q
);
1052 irq_set_affinity_hint(vector
, NULL
);
1053 free_irq(vector
, nvmeq
);
1058 static void nvme_clear_queue(struct nvme_queue
*nvmeq
)
1060 spin_lock_irq(&nvmeq
->q_lock
);
1061 if (nvmeq
->tags
&& *nvmeq
->tags
)
1062 blk_mq_all_tag_busy_iter(*nvmeq
->tags
, nvme_cancel_queue_ios
, nvmeq
);
1063 spin_unlock_irq(&nvmeq
->q_lock
);
1066 static void nvme_disable_admin_queue(struct nvme_dev
*dev
, bool shutdown
)
1068 struct nvme_queue
*nvmeq
= dev
->queues
[0];
1072 if (nvme_suspend_queue(nvmeq
))
1076 nvme_shutdown_ctrl(&dev
->ctrl
);
1078 nvme_disable_ctrl(&dev
->ctrl
, lo_hi_readq(
1079 dev
->bar
+ NVME_REG_CAP
));
1081 spin_lock_irq(&nvmeq
->q_lock
);
1082 nvme_process_cq(nvmeq
);
1083 spin_unlock_irq(&nvmeq
->q_lock
);
1086 static int nvme_cmb_qdepth(struct nvme_dev
*dev
, int nr_io_queues
,
1089 int q_depth
= dev
->q_depth
;
1090 unsigned q_size_aligned
= roundup(q_depth
* entry_size
,
1091 dev
->ctrl
.page_size
);
1093 if (q_size_aligned
* nr_io_queues
> dev
->cmb_size
) {
1094 u64 mem_per_q
= div_u64(dev
->cmb_size
, nr_io_queues
);
1095 mem_per_q
= round_down(mem_per_q
, dev
->ctrl
.page_size
);
1096 q_depth
= div_u64(mem_per_q
, entry_size
);
1099 * Ensure the reduced q_depth is above some threshold where it
1100 * would be better to map queues in system memory with the
1110 static int nvme_alloc_sq_cmds(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1113 if (qid
&& dev
->cmb
&& use_cmb_sqes
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1114 unsigned offset
= (qid
- 1) * roundup(SQ_SIZE(depth
),
1115 dev
->ctrl
.page_size
);
1116 nvmeq
->sq_dma_addr
= dev
->cmb_dma_addr
+ offset
;
1117 nvmeq
->sq_cmds_io
= dev
->cmb
+ offset
;
1119 nvmeq
->sq_cmds
= dma_alloc_coherent(dev
->dev
, SQ_SIZE(depth
),
1120 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1121 if (!nvmeq
->sq_cmds
)
1128 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
1131 struct nvme_queue
*nvmeq
= kzalloc(sizeof(*nvmeq
), GFP_KERNEL
);
1135 nvmeq
->cqes
= dma_zalloc_coherent(dev
->dev
, CQ_SIZE(depth
),
1136 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1140 if (nvme_alloc_sq_cmds(dev
, nvmeq
, qid
, depth
))
1143 nvmeq
->q_dmadev
= dev
->dev
;
1145 snprintf(nvmeq
->irqname
, sizeof(nvmeq
->irqname
), "nvme%dq%d",
1146 dev
->ctrl
.instance
, qid
);
1147 spin_lock_init(&nvmeq
->q_lock
);
1149 nvmeq
->cq_phase
= 1;
1150 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1151 nvmeq
->q_depth
= depth
;
1153 nvmeq
->cq_vector
= -1;
1154 dev
->queues
[qid
] = nvmeq
;
1160 dma_free_coherent(dev
->dev
, CQ_SIZE(depth
), (void *)nvmeq
->cqes
,
1161 nvmeq
->cq_dma_addr
);
1167 static int queue_request_irq(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1170 if (use_threaded_interrupts
)
1171 return request_threaded_irq(dev
->entry
[nvmeq
->cq_vector
].vector
,
1172 nvme_irq_check
, nvme_irq
, IRQF_SHARED
,
1174 return request_irq(dev
->entry
[nvmeq
->cq_vector
].vector
, nvme_irq
,
1175 IRQF_SHARED
, name
, nvmeq
);
1178 static void nvme_init_queue(struct nvme_queue
*nvmeq
, u16 qid
)
1180 struct nvme_dev
*dev
= nvmeq
->dev
;
1182 spin_lock_irq(&nvmeq
->q_lock
);
1185 nvmeq
->cq_phase
= 1;
1186 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1187 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(nvmeq
->q_depth
));
1188 dev
->online_queues
++;
1189 spin_unlock_irq(&nvmeq
->q_lock
);
1192 static int nvme_create_queue(struct nvme_queue
*nvmeq
, int qid
)
1194 struct nvme_dev
*dev
= nvmeq
->dev
;
1197 nvmeq
->cq_vector
= qid
- 1;
1198 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
1202 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1206 result
= queue_request_irq(dev
, nvmeq
, nvmeq
->irqname
);
1210 nvme_init_queue(nvmeq
, qid
);
1214 adapter_delete_sq(dev
, qid
);
1216 adapter_delete_cq(dev
, qid
);
1220 static struct blk_mq_ops nvme_mq_admin_ops
= {
1221 .queue_rq
= nvme_queue_rq
,
1222 .complete
= nvme_complete_rq
,
1223 .map_queue
= blk_mq_map_queue
,
1224 .init_hctx
= nvme_admin_init_hctx
,
1225 .exit_hctx
= nvme_admin_exit_hctx
,
1226 .init_request
= nvme_admin_init_request
,
1227 .timeout
= nvme_timeout
,
1230 static struct blk_mq_ops nvme_mq_ops
= {
1231 .queue_rq
= nvme_queue_rq
,
1232 .complete
= nvme_complete_rq
,
1233 .map_queue
= blk_mq_map_queue
,
1234 .init_hctx
= nvme_init_hctx
,
1235 .init_request
= nvme_init_request
,
1236 .timeout
= nvme_timeout
,
1240 static void nvme_dev_remove_admin(struct nvme_dev
*dev
)
1242 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
)) {
1243 blk_cleanup_queue(dev
->ctrl
.admin_q
);
1244 blk_mq_free_tag_set(&dev
->admin_tagset
);
1248 static int nvme_alloc_admin_tags(struct nvme_dev
*dev
)
1250 if (!dev
->ctrl
.admin_q
) {
1251 dev
->admin_tagset
.ops
= &nvme_mq_admin_ops
;
1252 dev
->admin_tagset
.nr_hw_queues
= 1;
1255 * Subtract one to leave an empty queue entry for 'Full Queue'
1256 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1258 dev
->admin_tagset
.queue_depth
= NVME_AQ_BLKMQ_DEPTH
- 1;
1259 dev
->admin_tagset
.timeout
= ADMIN_TIMEOUT
;
1260 dev
->admin_tagset
.numa_node
= dev_to_node(dev
->dev
);
1261 dev
->admin_tagset
.cmd_size
= nvme_cmd_size(dev
);
1262 dev
->admin_tagset
.driver_data
= dev
;
1264 if (blk_mq_alloc_tag_set(&dev
->admin_tagset
))
1267 dev
->ctrl
.admin_q
= blk_mq_init_queue(&dev
->admin_tagset
);
1268 if (IS_ERR(dev
->ctrl
.admin_q
)) {
1269 blk_mq_free_tag_set(&dev
->admin_tagset
);
1272 if (!blk_get_queue(dev
->ctrl
.admin_q
)) {
1273 nvme_dev_remove_admin(dev
);
1274 dev
->ctrl
.admin_q
= NULL
;
1278 blk_mq_start_stopped_hw_queues(dev
->ctrl
.admin_q
, true);
1283 static int nvme_configure_admin_queue(struct nvme_dev
*dev
)
1287 u64 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1288 struct nvme_queue
*nvmeq
;
1290 dev
->subsystem
= readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 1) ?
1291 NVME_CAP_NSSRC(cap
) : 0;
1293 if (dev
->subsystem
&&
1294 (readl(dev
->bar
+ NVME_REG_CSTS
) & NVME_CSTS_NSSRO
))
1295 writel(NVME_CSTS_NSSRO
, dev
->bar
+ NVME_REG_CSTS
);
1297 result
= nvme_disable_ctrl(&dev
->ctrl
, cap
);
1301 nvmeq
= dev
->queues
[0];
1303 nvmeq
= nvme_alloc_queue(dev
, 0, NVME_AQ_DEPTH
);
1308 aqa
= nvmeq
->q_depth
- 1;
1311 writel(aqa
, dev
->bar
+ NVME_REG_AQA
);
1312 lo_hi_writeq(nvmeq
->sq_dma_addr
, dev
->bar
+ NVME_REG_ASQ
);
1313 lo_hi_writeq(nvmeq
->cq_dma_addr
, dev
->bar
+ NVME_REG_ACQ
);
1315 result
= nvme_enable_ctrl(&dev
->ctrl
, cap
);
1319 nvmeq
->cq_vector
= 0;
1320 result
= queue_request_irq(dev
, nvmeq
, nvmeq
->irqname
);
1322 nvmeq
->cq_vector
= -1;
1329 nvme_free_queues(dev
, 0);
1333 static void nvme_watchdog_timer(unsigned long data
)
1335 struct nvme_dev
*dev
= (struct nvme_dev
*)data
;
1336 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1339 * Skip controllers currently under reset.
1341 if (!work_pending(&dev
->reset_work
) && !work_busy(&dev
->reset_work
) &&
1342 ((csts
& NVME_CSTS_CFS
) ||
1343 (dev
->subsystem
&& (csts
& NVME_CSTS_NSSRO
)))) {
1344 if (queue_work(nvme_workq
, &dev
->reset_work
)) {
1346 "Failed status: 0x%x, reset controller.\n",
1352 mod_timer(&dev
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
1355 static int nvme_create_io_queues(struct nvme_dev
*dev
)
1360 for (i
= dev
->queue_count
; i
<= dev
->max_qid
; i
++) {
1361 if (!nvme_alloc_queue(dev
, i
, dev
->q_depth
)) {
1367 max
= min(dev
->max_qid
, dev
->queue_count
- 1);
1368 for (i
= dev
->online_queues
; i
<= max
; i
++) {
1369 ret
= nvme_create_queue(dev
->queues
[i
], i
);
1371 nvme_free_queues(dev
, i
);
1377 * Ignore failing Create SQ/CQ commands, we can continue with less
1378 * than the desired aount of queues, and even a controller without
1379 * I/O queues an still be used to issue admin commands. This might
1380 * be useful to upgrade a buggy firmware for example.
1382 return ret
>= 0 ? 0 : ret
;
1385 static void __iomem
*nvme_map_cmb(struct nvme_dev
*dev
)
1387 u64 szu
, size
, offset
;
1389 resource_size_t bar_size
;
1390 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1392 dma_addr_t dma_addr
;
1397 dev
->cmbsz
= readl(dev
->bar
+ NVME_REG_CMBSZ
);
1398 if (!(NVME_CMB_SZ(dev
->cmbsz
)))
1401 cmbloc
= readl(dev
->bar
+ NVME_REG_CMBLOC
);
1403 szu
= (u64
)1 << (12 + 4 * NVME_CMB_SZU(dev
->cmbsz
));
1404 size
= szu
* NVME_CMB_SZ(dev
->cmbsz
);
1405 offset
= szu
* NVME_CMB_OFST(cmbloc
);
1406 bar_size
= pci_resource_len(pdev
, NVME_CMB_BIR(cmbloc
));
1408 if (offset
> bar_size
)
1412 * Controllers may support a CMB size larger than their BAR,
1413 * for example, due to being behind a bridge. Reduce the CMB to
1414 * the reported size of the BAR
1416 if (size
> bar_size
- offset
)
1417 size
= bar_size
- offset
;
1419 dma_addr
= pci_resource_start(pdev
, NVME_CMB_BIR(cmbloc
)) + offset
;
1420 cmb
= ioremap_wc(dma_addr
, size
);
1424 dev
->cmb_dma_addr
= dma_addr
;
1425 dev
->cmb_size
= size
;
1429 static inline void nvme_release_cmb(struct nvme_dev
*dev
)
1437 static size_t db_bar_size(struct nvme_dev
*dev
, unsigned nr_io_queues
)
1439 return 4096 + ((nr_io_queues
+ 1) * 8 * dev
->db_stride
);
1442 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
1444 struct nvme_queue
*adminq
= dev
->queues
[0];
1445 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1446 int result
, i
, vecs
, nr_io_queues
, size
;
1448 nr_io_queues
= num_possible_cpus();
1449 result
= nvme_set_queue_count(&dev
->ctrl
, &nr_io_queues
);
1454 * Degraded controllers might return an error when setting the queue
1455 * count. We still want to be able to bring them online and offer
1456 * access to the admin queue, as that might be only way to fix them up.
1459 dev_err(dev
->ctrl
.device
,
1460 "Could not set queue count (%d)\n", result
);
1465 if (dev
->cmb
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1466 result
= nvme_cmb_qdepth(dev
, nr_io_queues
,
1467 sizeof(struct nvme_command
));
1469 dev
->q_depth
= result
;
1471 nvme_release_cmb(dev
);
1474 size
= db_bar_size(dev
, nr_io_queues
);
1478 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), size
);
1481 if (!--nr_io_queues
)
1483 size
= db_bar_size(dev
, nr_io_queues
);
1485 dev
->dbs
= dev
->bar
+ 4096;
1486 adminq
->q_db
= dev
->dbs
;
1489 /* Deregister the admin queue's interrupt */
1490 free_irq(dev
->entry
[0].vector
, adminq
);
1493 * If we enable msix early due to not intx, disable it again before
1494 * setting up the full range we need.
1497 pci_disable_msix(pdev
);
1499 for (i
= 0; i
< nr_io_queues
; i
++)
1500 dev
->entry
[i
].entry
= i
;
1501 vecs
= pci_enable_msix_range(pdev
, dev
->entry
, 1, nr_io_queues
);
1503 vecs
= pci_enable_msi_range(pdev
, 1, min(nr_io_queues
, 32));
1507 for (i
= 0; i
< vecs
; i
++)
1508 dev
->entry
[i
].vector
= i
+ pdev
->irq
;
1513 * Should investigate if there's a performance win from allocating
1514 * more queues than interrupt vectors; it might allow the submission
1515 * path to scale better, even if the receive path is limited by the
1516 * number of interrupts.
1518 nr_io_queues
= vecs
;
1519 dev
->max_qid
= nr_io_queues
;
1521 result
= queue_request_irq(dev
, adminq
, adminq
->irqname
);
1523 adminq
->cq_vector
= -1;
1526 return nvme_create_io_queues(dev
);
1529 nvme_free_queues(dev
, 1);
1533 static void nvme_set_irq_hints(struct nvme_dev
*dev
)
1535 struct nvme_queue
*nvmeq
;
1538 for (i
= 0; i
< dev
->online_queues
; i
++) {
1539 nvmeq
= dev
->queues
[i
];
1541 if (!nvmeq
->tags
|| !(*nvmeq
->tags
))
1544 irq_set_affinity_hint(dev
->entry
[nvmeq
->cq_vector
].vector
,
1545 blk_mq_tags_cpumask(*nvmeq
->tags
));
1549 static void nvme_dev_scan(struct work_struct
*work
)
1551 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, scan_work
);
1553 if (!dev
->tagset
.tags
)
1555 nvme_scan_namespaces(&dev
->ctrl
);
1556 nvme_set_irq_hints(dev
);
1559 static void nvme_del_queue_end(struct request
*req
, int error
)
1561 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1563 blk_mq_free_request(req
);
1564 complete(&nvmeq
->dev
->ioq_wait
);
1567 static void nvme_del_cq_end(struct request
*req
, int error
)
1569 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1572 unsigned long flags
;
1574 spin_lock_irqsave(&nvmeq
->q_lock
, flags
);
1575 nvme_process_cq(nvmeq
);
1576 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
1579 nvme_del_queue_end(req
, error
);
1582 static int nvme_delete_queue(struct nvme_queue
*nvmeq
, u8 opcode
)
1584 struct request_queue
*q
= nvmeq
->dev
->ctrl
.admin_q
;
1585 struct request
*req
;
1586 struct nvme_command cmd
;
1588 memset(&cmd
, 0, sizeof(cmd
));
1589 cmd
.delete_queue
.opcode
= opcode
;
1590 cmd
.delete_queue
.qid
= cpu_to_le16(nvmeq
->qid
);
1592 req
= nvme_alloc_request(q
, &cmd
, BLK_MQ_REQ_NOWAIT
);
1594 return PTR_ERR(req
);
1596 req
->timeout
= ADMIN_TIMEOUT
;
1597 req
->end_io_data
= nvmeq
;
1599 blk_execute_rq_nowait(q
, NULL
, req
, false,
1600 opcode
== nvme_admin_delete_cq
?
1601 nvme_del_cq_end
: nvme_del_queue_end
);
1605 static void nvme_disable_io_queues(struct nvme_dev
*dev
)
1608 unsigned long timeout
;
1609 u8 opcode
= nvme_admin_delete_sq
;
1611 for (pass
= 0; pass
< 2; pass
++) {
1612 int sent
= 0, i
= dev
->queue_count
- 1;
1614 reinit_completion(&dev
->ioq_wait
);
1616 timeout
= ADMIN_TIMEOUT
;
1617 for (; i
> 0; i
--) {
1618 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1621 nvme_suspend_queue(nvmeq
);
1622 if (nvme_delete_queue(nvmeq
, opcode
))
1627 timeout
= wait_for_completion_io_timeout(&dev
->ioq_wait
, timeout
);
1633 opcode
= nvme_admin_delete_cq
;
1638 * Return: error value if an error occurred setting up the queues or calling
1639 * Identify Device. 0 if these succeeded, even if adding some of the
1640 * namespaces failed. At the moment, these failures are silent. TBD which
1641 * failures should be reported.
1643 static int nvme_dev_add(struct nvme_dev
*dev
)
1645 if (!dev
->ctrl
.tagset
) {
1646 dev
->tagset
.ops
= &nvme_mq_ops
;
1647 dev
->tagset
.nr_hw_queues
= dev
->online_queues
- 1;
1648 dev
->tagset
.timeout
= NVME_IO_TIMEOUT
;
1649 dev
->tagset
.numa_node
= dev_to_node(dev
->dev
);
1650 dev
->tagset
.queue_depth
=
1651 min_t(int, dev
->q_depth
, BLK_MQ_MAX_DEPTH
) - 1;
1652 dev
->tagset
.cmd_size
= nvme_cmd_size(dev
);
1653 dev
->tagset
.flags
= BLK_MQ_F_SHOULD_MERGE
;
1654 dev
->tagset
.driver_data
= dev
;
1656 if (blk_mq_alloc_tag_set(&dev
->tagset
))
1658 dev
->ctrl
.tagset
= &dev
->tagset
;
1660 blk_mq_update_nr_hw_queues(&dev
->tagset
, dev
->online_queues
- 1);
1662 /* Free previously allocated queues that are no longer usable */
1663 nvme_free_queues(dev
, dev
->online_queues
);
1666 queue_work(nvme_workq
, &dev
->scan_work
);
1670 static int nvme_dev_map(struct nvme_dev
*dev
)
1673 int bars
, result
= -ENOMEM
;
1674 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1676 if (pci_enable_device_mem(pdev
))
1679 dev
->entry
[0].vector
= pdev
->irq
;
1680 pci_set_master(pdev
);
1681 bars
= pci_select_bars(pdev
, IORESOURCE_MEM
);
1685 if (pci_request_selected_regions(pdev
, bars
, "nvme"))
1688 if (dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(64)) &&
1689 dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(32)))
1692 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), 8192);
1696 if (readl(dev
->bar
+ NVME_REG_CSTS
) == -1) {
1702 * Some devices don't advertse INTx interrupts, pre-enable a single
1703 * MSIX vec for setup. We'll adjust this later.
1706 result
= pci_enable_msix(pdev
, dev
->entry
, 1);
1711 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1713 dev
->q_depth
= min_t(int, NVME_CAP_MQES(cap
) + 1, NVME_Q_DEPTH
);
1714 dev
->db_stride
= 1 << NVME_CAP_STRIDE(cap
);
1715 dev
->dbs
= dev
->bar
+ 4096;
1718 * Temporary fix for the Apple controller found in the MacBook8,1 and
1719 * some MacBook7,1 to avoid controller resets and data loss.
1721 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
&& pdev
->device
== 0x2001) {
1723 dev_warn(dev
->dev
, "detected Apple NVMe controller, set "
1724 "queue depth=%u to work around controller resets\n",
1728 if (readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 2))
1729 dev
->cmb
= nvme_map_cmb(dev
);
1731 pci_enable_pcie_error_reporting(pdev
);
1732 pci_save_state(pdev
);
1739 pci_release_regions(pdev
);
1741 pci_disable_device(pdev
);
1745 static void nvme_dev_unmap(struct nvme_dev
*dev
)
1747 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1749 if (pdev
->msi_enabled
)
1750 pci_disable_msi(pdev
);
1751 else if (pdev
->msix_enabled
)
1752 pci_disable_msix(pdev
);
1757 pci_release_regions(pdev
);
1760 if (pci_is_enabled(pdev
)) {
1761 pci_disable_pcie_error_reporting(pdev
);
1762 pci_disable_device(pdev
);
1766 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
)
1771 del_timer_sync(&dev
->watchdog_timer
);
1773 mutex_lock(&dev
->shutdown_lock
);
1775 nvme_stop_queues(&dev
->ctrl
);
1776 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1778 if (csts
& NVME_CSTS_CFS
|| !(csts
& NVME_CSTS_RDY
)) {
1779 for (i
= dev
->queue_count
- 1; i
>= 0; i
--) {
1780 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1781 nvme_suspend_queue(nvmeq
);
1784 nvme_disable_io_queues(dev
);
1785 nvme_disable_admin_queue(dev
, shutdown
);
1787 nvme_dev_unmap(dev
);
1789 for (i
= dev
->queue_count
- 1; i
>= 0; i
--)
1790 nvme_clear_queue(dev
->queues
[i
]);
1791 mutex_unlock(&dev
->shutdown_lock
);
1794 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
1796 dev
->prp_page_pool
= dma_pool_create("prp list page", dev
->dev
,
1797 PAGE_SIZE
, PAGE_SIZE
, 0);
1798 if (!dev
->prp_page_pool
)
1801 /* Optimisation for I/Os between 4k and 128k */
1802 dev
->prp_small_pool
= dma_pool_create("prp list 256", dev
->dev
,
1804 if (!dev
->prp_small_pool
) {
1805 dma_pool_destroy(dev
->prp_page_pool
);
1811 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
1813 dma_pool_destroy(dev
->prp_page_pool
);
1814 dma_pool_destroy(dev
->prp_small_pool
);
1817 static void nvme_pci_free_ctrl(struct nvme_ctrl
*ctrl
)
1819 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
1821 put_device(dev
->dev
);
1822 if (dev
->tagset
.tags
)
1823 blk_mq_free_tag_set(&dev
->tagset
);
1824 if (dev
->ctrl
.admin_q
)
1825 blk_put_queue(dev
->ctrl
.admin_q
);
1831 static void nvme_reset_work(struct work_struct
*work
)
1833 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, reset_work
);
1836 if (WARN_ON(test_bit(NVME_CTRL_RESETTING
, &dev
->flags
)))
1840 * If we're called to reset a live controller first shut it down before
1844 nvme_dev_disable(dev
, false);
1846 set_bit(NVME_CTRL_RESETTING
, &dev
->flags
);
1848 result
= nvme_dev_map(dev
);
1852 result
= nvme_configure_admin_queue(dev
);
1856 nvme_init_queue(dev
->queues
[0], 0);
1857 result
= nvme_alloc_admin_tags(dev
);
1861 result
= nvme_init_identify(&dev
->ctrl
);
1865 result
= nvme_setup_io_queues(dev
);
1869 dev
->ctrl
.event_limit
= NVME_NR_AEN_COMMANDS
;
1870 queue_work(nvme_workq
, &dev
->async_work
);
1872 mod_timer(&dev
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
1875 * Keep the controller around but remove all namespaces if we don't have
1876 * any working I/O queue.
1878 if (dev
->online_queues
< 2) {
1879 dev_warn(dev
->ctrl
.device
, "IO queues not created\n");
1880 nvme_remove_namespaces(&dev
->ctrl
);
1882 nvme_start_queues(&dev
->ctrl
);
1886 clear_bit(NVME_CTRL_RESETTING
, &dev
->flags
);
1890 nvme_dev_remove_admin(dev
);
1891 blk_put_queue(dev
->ctrl
.admin_q
);
1892 dev
->ctrl
.admin_q
= NULL
;
1893 dev
->queues
[0]->tags
= NULL
;
1895 nvme_disable_admin_queue(dev
, false);
1897 nvme_dev_unmap(dev
);
1899 nvme_remove_dead_ctrl(dev
);
1902 static void nvme_remove_dead_ctrl_work(struct work_struct
*work
)
1904 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, remove_work
);
1905 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1907 if (pci_get_drvdata(pdev
))
1908 pci_stop_and_remove_bus_device_locked(pdev
);
1909 nvme_put_ctrl(&dev
->ctrl
);
1912 static void nvme_remove_dead_ctrl(struct nvme_dev
*dev
)
1914 dev_warn(dev
->ctrl
.device
, "Removing after probe failure\n");
1915 kref_get(&dev
->ctrl
.kref
);
1916 if (!schedule_work(&dev
->remove_work
))
1917 nvme_put_ctrl(&dev
->ctrl
);
1920 static int nvme_reset(struct nvme_dev
*dev
)
1922 if (!dev
->ctrl
.admin_q
|| blk_queue_dying(dev
->ctrl
.admin_q
))
1925 if (!queue_work(nvme_workq
, &dev
->reset_work
))
1928 flush_work(&dev
->reset_work
);
1932 static int nvme_pci_reg_read32(struct nvme_ctrl
*ctrl
, u32 off
, u32
*val
)
1934 *val
= readl(to_nvme_dev(ctrl
)->bar
+ off
);
1938 static int nvme_pci_reg_write32(struct nvme_ctrl
*ctrl
, u32 off
, u32 val
)
1940 writel(val
, to_nvme_dev(ctrl
)->bar
+ off
);
1944 static int nvme_pci_reg_read64(struct nvme_ctrl
*ctrl
, u32 off
, u64
*val
)
1946 *val
= readq(to_nvme_dev(ctrl
)->bar
+ off
);
1950 static bool nvme_pci_io_incapable(struct nvme_ctrl
*ctrl
)
1952 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
1954 return !dev
->bar
|| dev
->online_queues
< 2;
1957 static int nvme_pci_reset_ctrl(struct nvme_ctrl
*ctrl
)
1959 return nvme_reset(to_nvme_dev(ctrl
));
1962 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops
= {
1963 .module
= THIS_MODULE
,
1964 .reg_read32
= nvme_pci_reg_read32
,
1965 .reg_write32
= nvme_pci_reg_write32
,
1966 .reg_read64
= nvme_pci_reg_read64
,
1967 .io_incapable
= nvme_pci_io_incapable
,
1968 .reset_ctrl
= nvme_pci_reset_ctrl
,
1969 .free_ctrl
= nvme_pci_free_ctrl
,
1972 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1974 int node
, result
= -ENOMEM
;
1975 struct nvme_dev
*dev
;
1977 node
= dev_to_node(&pdev
->dev
);
1978 if (node
== NUMA_NO_NODE
)
1979 set_dev_node(&pdev
->dev
, 0);
1981 dev
= kzalloc_node(sizeof(*dev
), GFP_KERNEL
, node
);
1984 dev
->entry
= kzalloc_node(num_possible_cpus() * sizeof(*dev
->entry
),
1988 dev
->queues
= kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
1993 dev
->dev
= get_device(&pdev
->dev
);
1994 pci_set_drvdata(pdev
, dev
);
1996 INIT_WORK(&dev
->scan_work
, nvme_dev_scan
);
1997 INIT_WORK(&dev
->reset_work
, nvme_reset_work
);
1998 INIT_WORK(&dev
->remove_work
, nvme_remove_dead_ctrl_work
);
1999 INIT_WORK(&dev
->async_work
, nvme_async_event_work
);
2000 setup_timer(&dev
->watchdog_timer
, nvme_watchdog_timer
,
2001 (unsigned long)dev
);
2002 mutex_init(&dev
->shutdown_lock
);
2003 init_completion(&dev
->ioq_wait
);
2005 result
= nvme_setup_prp_pools(dev
);
2009 result
= nvme_init_ctrl(&dev
->ctrl
, &pdev
->dev
, &nvme_pci_ctrl_ops
,
2014 dev_info(dev
->ctrl
.device
, "pci function %s\n", dev_name(&pdev
->dev
));
2016 queue_work(nvme_workq
, &dev
->reset_work
);
2020 nvme_release_prp_pools(dev
);
2022 put_device(dev
->dev
);
2030 static void nvme_reset_notify(struct pci_dev
*pdev
, bool prepare
)
2032 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2035 nvme_dev_disable(dev
, false);
2037 queue_work(nvme_workq
, &dev
->reset_work
);
2040 static void nvme_shutdown(struct pci_dev
*pdev
)
2042 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2043 nvme_dev_disable(dev
, true);
2046 static void nvme_remove(struct pci_dev
*pdev
)
2048 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2050 del_timer_sync(&dev
->watchdog_timer
);
2052 pci_set_drvdata(pdev
, NULL
);
2053 flush_work(&dev
->async_work
);
2054 flush_work(&dev
->reset_work
);
2055 flush_work(&dev
->scan_work
);
2056 nvme_remove_namespaces(&dev
->ctrl
);
2057 nvme_uninit_ctrl(&dev
->ctrl
);
2058 nvme_dev_disable(dev
, true);
2059 nvme_dev_remove_admin(dev
);
2060 nvme_free_queues(dev
, 0);
2061 nvme_release_cmb(dev
);
2062 nvme_release_prp_pools(dev
);
2063 nvme_put_ctrl(&dev
->ctrl
);
2066 #ifdef CONFIG_PM_SLEEP
2067 static int nvme_suspend(struct device
*dev
)
2069 struct pci_dev
*pdev
= to_pci_dev(dev
);
2070 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2072 nvme_dev_disable(ndev
, true);
2076 static int nvme_resume(struct device
*dev
)
2078 struct pci_dev
*pdev
= to_pci_dev(dev
);
2079 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2081 queue_work(nvme_workq
, &ndev
->reset_work
);
2086 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops
, nvme_suspend
, nvme_resume
);
2088 static pci_ers_result_t
nvme_error_detected(struct pci_dev
*pdev
,
2089 pci_channel_state_t state
)
2091 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2094 * A frozen channel requires a reset. When detected, this method will
2095 * shutdown the controller to quiesce. The controller will be restarted
2096 * after the slot reset through driver's slot_reset callback.
2098 dev_warn(dev
->ctrl
.device
, "error detected: state:%d\n", state
);
2100 case pci_channel_io_normal
:
2101 return PCI_ERS_RESULT_CAN_RECOVER
;
2102 case pci_channel_io_frozen
:
2103 nvme_dev_disable(dev
, false);
2104 return PCI_ERS_RESULT_NEED_RESET
;
2105 case pci_channel_io_perm_failure
:
2106 return PCI_ERS_RESULT_DISCONNECT
;
2108 return PCI_ERS_RESULT_NEED_RESET
;
2111 static pci_ers_result_t
nvme_slot_reset(struct pci_dev
*pdev
)
2113 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2115 dev_info(dev
->ctrl
.device
, "restart after slot reset\n");
2116 pci_restore_state(pdev
);
2117 queue_work(nvme_workq
, &dev
->reset_work
);
2118 return PCI_ERS_RESULT_RECOVERED
;
2121 static void nvme_error_resume(struct pci_dev
*pdev
)
2123 pci_cleanup_aer_uncorrect_error_status(pdev
);
2126 static const struct pci_error_handlers nvme_err_handler
= {
2127 .error_detected
= nvme_error_detected
,
2128 .slot_reset
= nvme_slot_reset
,
2129 .resume
= nvme_error_resume
,
2130 .reset_notify
= nvme_reset_notify
,
2133 /* Move to pci_ids.h later */
2134 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
2136 static const struct pci_device_id nvme_id_table
[] = {
2137 { PCI_VDEVICE(INTEL
, 0x0953),
2138 .driver_data
= NVME_QUIRK_STRIPE_SIZE
, },
2139 { PCI_VDEVICE(INTEL
, 0x5845), /* Qemu emulated controller */
2140 .driver_data
= NVME_QUIRK_IDENTIFY_CNS
, },
2141 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
2142 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2001) },
2145 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
2147 static struct pci_driver nvme_driver
= {
2149 .id_table
= nvme_id_table
,
2150 .probe
= nvme_probe
,
2151 .remove
= nvme_remove
,
2152 .shutdown
= nvme_shutdown
,
2154 .pm
= &nvme_dev_pm_ops
,
2156 .err_handler
= &nvme_err_handler
,
2159 static int __init
nvme_init(void)
2163 nvme_workq
= alloc_workqueue("nvme", WQ_UNBOUND
| WQ_MEM_RECLAIM
, 0);
2167 result
= pci_register_driver(&nvme_driver
);
2169 destroy_workqueue(nvme_workq
);
2173 static void __exit
nvme_exit(void)
2175 pci_unregister_driver(&nvme_driver
);
2176 destroy_workqueue(nvme_workq
);
2180 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2181 MODULE_LICENSE("GPL");
2182 MODULE_VERSION("1.0");
2183 module_init(nvme_init
);
2184 module_exit(nvme_exit
);