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rapidio/tsi721: add query_mport callback
[deliverable/linux.git] / drivers / rapidio / devices / tsi721.c
1 /*
2 * RapidIO mport driver for Tsi721 PCIExpress-to-SRIO bridge
3 *
4 * Copyright 2011 Integrated Device Technology, Inc.
5 * Alexandre Bounine <alexandre.bounine@idt.com>
6 * Chul Kim <chul.kim@idt.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23 #include <linux/io.h>
24 #include <linux/errno.h>
25 #include <linux/init.h>
26 #include <linux/ioport.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/rio.h>
31 #include <linux/rio_drv.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/interrupt.h>
34 #include <linux/kfifo.h>
35 #include <linux/delay.h>
36
37 #include "tsi721.h"
38
39 #define DEBUG_PW /* Inbound Port-Write debugging */
40
41 static void tsi721_omsg_handler(struct tsi721_device *priv, int ch);
42 static void tsi721_imsg_handler(struct tsi721_device *priv, int ch);
43
44 /**
45 * tsi721_lcread - read from local SREP config space
46 * @mport: RapidIO master port info
47 * @index: ID of RapdiIO interface
48 * @offset: Offset into configuration space
49 * @len: Length (in bytes) of the maintenance transaction
50 * @data: Value to be read into
51 *
52 * Generates a local SREP space read. Returns %0 on
53 * success or %-EINVAL on failure.
54 */
55 static int tsi721_lcread(struct rio_mport *mport, int index, u32 offset,
56 int len, u32 *data)
57 {
58 struct tsi721_device *priv = mport->priv;
59
60 if (len != sizeof(u32))
61 return -EINVAL; /* only 32-bit access is supported */
62
63 *data = ioread32(priv->regs + offset);
64
65 return 0;
66 }
67
68 /**
69 * tsi721_lcwrite - write into local SREP config space
70 * @mport: RapidIO master port info
71 * @index: ID of RapdiIO interface
72 * @offset: Offset into configuration space
73 * @len: Length (in bytes) of the maintenance transaction
74 * @data: Value to be written
75 *
76 * Generates a local write into SREP configuration space. Returns %0 on
77 * success or %-EINVAL on failure.
78 */
79 static int tsi721_lcwrite(struct rio_mport *mport, int index, u32 offset,
80 int len, u32 data)
81 {
82 struct tsi721_device *priv = mport->priv;
83
84 if (len != sizeof(u32))
85 return -EINVAL; /* only 32-bit access is supported */
86
87 iowrite32(data, priv->regs + offset);
88
89 return 0;
90 }
91
92 /**
93 * tsi721_maint_dma - Helper function to generate RapidIO maintenance
94 * transactions using designated Tsi721 DMA channel.
95 * @priv: pointer to tsi721 private data
96 * @sys_size: RapdiIO transport system size
97 * @destid: Destination ID of transaction
98 * @hopcount: Number of hops to target device
99 * @offset: Offset into configuration space
100 * @len: Length (in bytes) of the maintenance transaction
101 * @data: Location to be read from or write into
102 * @do_wr: Operation flag (1 == MAINT_WR)
103 *
104 * Generates a RapidIO maintenance transaction (Read or Write).
105 * Returns %0 on success and %-EINVAL or %-EFAULT on failure.
106 */
107 static int tsi721_maint_dma(struct tsi721_device *priv, u32 sys_size,
108 u16 destid, u8 hopcount, u32 offset, int len,
109 u32 *data, int do_wr)
110 {
111 void __iomem *regs = priv->regs + TSI721_DMAC_BASE(priv->mdma.ch_id);
112 struct tsi721_dma_desc *bd_ptr;
113 u32 rd_count, swr_ptr, ch_stat;
114 int i, err = 0;
115 u32 op = do_wr ? MAINT_WR : MAINT_RD;
116
117 if (offset > (RIO_MAINT_SPACE_SZ - len) || (len != sizeof(u32)))
118 return -EINVAL;
119
120 bd_ptr = priv->mdma.bd_base;
121
122 rd_count = ioread32(regs + TSI721_DMAC_DRDCNT);
123
124 /* Initialize DMA descriptor */
125 bd_ptr[0].type_id = cpu_to_le32((DTYPE2 << 29) | (op << 19) | destid);
126 bd_ptr[0].bcount = cpu_to_le32((sys_size << 26) | 0x04);
127 bd_ptr[0].raddr_lo = cpu_to_le32((hopcount << 24) | offset);
128 bd_ptr[0].raddr_hi = 0;
129 if (do_wr)
130 bd_ptr[0].data[0] = cpu_to_be32p(data);
131 else
132 bd_ptr[0].data[0] = 0xffffffff;
133
134 mb();
135
136 /* Start DMA operation */
137 iowrite32(rd_count + 2, regs + TSI721_DMAC_DWRCNT);
138 ioread32(regs + TSI721_DMAC_DWRCNT);
139 i = 0;
140
141 /* Wait until DMA transfer is finished */
142 while ((ch_stat = ioread32(regs + TSI721_DMAC_STS))
143 & TSI721_DMAC_STS_RUN) {
144 udelay(1);
145 if (++i >= 5000000) {
146 dev_dbg(&priv->pdev->dev,
147 "%s : DMA[%d] read timeout ch_status=%x\n",
148 __func__, priv->mdma.ch_id, ch_stat);
149 if (!do_wr)
150 *data = 0xffffffff;
151 err = -EIO;
152 goto err_out;
153 }
154 }
155
156 if (ch_stat & TSI721_DMAC_STS_ABORT) {
157 /* If DMA operation aborted due to error,
158 * reinitialize DMA channel
159 */
160 dev_dbg(&priv->pdev->dev, "%s : DMA ABORT ch_stat=%x\n",
161 __func__, ch_stat);
162 dev_dbg(&priv->pdev->dev, "OP=%d : destid=%x hc=%x off=%x\n",
163 do_wr ? MAINT_WR : MAINT_RD, destid, hopcount, offset);
164 iowrite32(TSI721_DMAC_INT_ALL, regs + TSI721_DMAC_INT);
165 iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL);
166 udelay(10);
167 iowrite32(0, regs + TSI721_DMAC_DWRCNT);
168 udelay(1);
169 if (!do_wr)
170 *data = 0xffffffff;
171 err = -EIO;
172 goto err_out;
173 }
174
175 if (!do_wr)
176 *data = be32_to_cpu(bd_ptr[0].data[0]);
177
178 /*
179 * Update descriptor status FIFO RD pointer.
180 * NOTE: Skipping check and clear FIFO entries because we are waiting
181 * for transfer to be completed.
182 */
183 swr_ptr = ioread32(regs + TSI721_DMAC_DSWP);
184 iowrite32(swr_ptr, regs + TSI721_DMAC_DSRP);
185 err_out:
186
187 return err;
188 }
189
190 /**
191 * tsi721_cread_dma - Generate a RapidIO maintenance read transaction
192 * using Tsi721 BDMA engine.
193 * @mport: RapidIO master port control structure
194 * @index: ID of RapdiIO interface
195 * @destid: Destination ID of transaction
196 * @hopcount: Number of hops to target device
197 * @offset: Offset into configuration space
198 * @len: Length (in bytes) of the maintenance transaction
199 * @val: Location to be read into
200 *
201 * Generates a RapidIO maintenance read transaction.
202 * Returns %0 on success and %-EINVAL or %-EFAULT on failure.
203 */
204 static int tsi721_cread_dma(struct rio_mport *mport, int index, u16 destid,
205 u8 hopcount, u32 offset, int len, u32 *data)
206 {
207 struct tsi721_device *priv = mport->priv;
208
209 return tsi721_maint_dma(priv, mport->sys_size, destid, hopcount,
210 offset, len, data, 0);
211 }
212
213 /**
214 * tsi721_cwrite_dma - Generate a RapidIO maintenance write transaction
215 * using Tsi721 BDMA engine
216 * @mport: RapidIO master port control structure
217 * @index: ID of RapdiIO interface
218 * @destid: Destination ID of transaction
219 * @hopcount: Number of hops to target device
220 * @offset: Offset into configuration space
221 * @len: Length (in bytes) of the maintenance transaction
222 * @val: Value to be written
223 *
224 * Generates a RapidIO maintenance write transaction.
225 * Returns %0 on success and %-EINVAL or %-EFAULT on failure.
226 */
227 static int tsi721_cwrite_dma(struct rio_mport *mport, int index, u16 destid,
228 u8 hopcount, u32 offset, int len, u32 data)
229 {
230 struct tsi721_device *priv = mport->priv;
231 u32 temp = data;
232
233 return tsi721_maint_dma(priv, mport->sys_size, destid, hopcount,
234 offset, len, &temp, 1);
235 }
236
237 /**
238 * tsi721_pw_handler - Tsi721 inbound port-write interrupt handler
239 * @mport: RapidIO master port structure
240 *
241 * Handles inbound port-write interrupts. Copies PW message from an internal
242 * buffer into PW message FIFO and schedules deferred routine to process
243 * queued messages.
244 */
245 static int
246 tsi721_pw_handler(struct rio_mport *mport)
247 {
248 struct tsi721_device *priv = mport->priv;
249 u32 pw_stat;
250 u32 pw_buf[TSI721_RIO_PW_MSG_SIZE/sizeof(u32)];
251
252
253 pw_stat = ioread32(priv->regs + TSI721_RIO_PW_RX_STAT);
254
255 if (pw_stat & TSI721_RIO_PW_RX_STAT_PW_VAL) {
256 pw_buf[0] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(0));
257 pw_buf[1] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(1));
258 pw_buf[2] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(2));
259 pw_buf[3] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(3));
260
261 /* Queue PW message (if there is room in FIFO),
262 * otherwise discard it.
263 */
264 spin_lock(&priv->pw_fifo_lock);
265 if (kfifo_avail(&priv->pw_fifo) >= TSI721_RIO_PW_MSG_SIZE)
266 kfifo_in(&priv->pw_fifo, pw_buf,
267 TSI721_RIO_PW_MSG_SIZE);
268 else
269 priv->pw_discard_count++;
270 spin_unlock(&priv->pw_fifo_lock);
271 }
272
273 /* Clear pending PW interrupts */
274 iowrite32(TSI721_RIO_PW_RX_STAT_PW_DISC | TSI721_RIO_PW_RX_STAT_PW_VAL,
275 priv->regs + TSI721_RIO_PW_RX_STAT);
276
277 schedule_work(&priv->pw_work);
278
279 return 0;
280 }
281
282 static void tsi721_pw_dpc(struct work_struct *work)
283 {
284 struct tsi721_device *priv = container_of(work, struct tsi721_device,
285 pw_work);
286 u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)]; /* Use full size PW message
287 buffer for RIO layer */
288
289 /*
290 * Process port-write messages
291 */
292 while (kfifo_out_spinlocked(&priv->pw_fifo, (unsigned char *)msg_buffer,
293 TSI721_RIO_PW_MSG_SIZE, &priv->pw_fifo_lock)) {
294 /* Process one message */
295 #ifdef DEBUG_PW
296 {
297 u32 i;
298 pr_debug("%s : Port-Write Message:", __func__);
299 for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); ) {
300 pr_debug("0x%02x: %08x %08x %08x %08x", i*4,
301 msg_buffer[i], msg_buffer[i + 1],
302 msg_buffer[i + 2], msg_buffer[i + 3]);
303 i += 4;
304 }
305 pr_debug("\n");
306 }
307 #endif
308 /* Pass the port-write message to RIO core for processing */
309 rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer);
310 }
311 }
312
313 /**
314 * tsi721_pw_enable - enable/disable port-write interface init
315 * @mport: Master port implementing the port write unit
316 * @enable: 1=enable; 0=disable port-write message handling
317 */
318 static int tsi721_pw_enable(struct rio_mport *mport, int enable)
319 {
320 struct tsi721_device *priv = mport->priv;
321 u32 rval;
322
323 rval = ioread32(priv->regs + TSI721_RIO_EM_INT_ENABLE);
324
325 if (enable)
326 rval |= TSI721_RIO_EM_INT_ENABLE_PW_RX;
327 else
328 rval &= ~TSI721_RIO_EM_INT_ENABLE_PW_RX;
329
330 /* Clear pending PW interrupts */
331 iowrite32(TSI721_RIO_PW_RX_STAT_PW_DISC | TSI721_RIO_PW_RX_STAT_PW_VAL,
332 priv->regs + TSI721_RIO_PW_RX_STAT);
333 /* Update enable bits */
334 iowrite32(rval, priv->regs + TSI721_RIO_EM_INT_ENABLE);
335
336 return 0;
337 }
338
339 /**
340 * tsi721_dsend - Send a RapidIO doorbell
341 * @mport: RapidIO master port info
342 * @index: ID of RapidIO interface
343 * @destid: Destination ID of target device
344 * @data: 16-bit info field of RapidIO doorbell
345 *
346 * Sends a RapidIO doorbell message. Always returns %0.
347 */
348 static int tsi721_dsend(struct rio_mport *mport, int index,
349 u16 destid, u16 data)
350 {
351 struct tsi721_device *priv = mport->priv;
352 u32 offset;
353
354 offset = (((mport->sys_size) ? RIO_TT_CODE_16 : RIO_TT_CODE_8) << 18) |
355 (destid << 2);
356
357 dev_dbg(&priv->pdev->dev,
358 "Send Doorbell 0x%04x to destID 0x%x\n", data, destid);
359 iowrite16be(data, priv->odb_base + offset);
360
361 return 0;
362 }
363
364 /**
365 * tsi721_dbell_handler - Tsi721 doorbell interrupt handler
366 * @mport: RapidIO master port structure
367 *
368 * Handles inbound doorbell interrupts. Copies doorbell entry from an internal
369 * buffer into DB message FIFO and schedules deferred routine to process
370 * queued DBs.
371 */
372 static int
373 tsi721_dbell_handler(struct rio_mport *mport)
374 {
375 struct tsi721_device *priv = mport->priv;
376 u32 regval;
377
378 /* Disable IDB interrupts */
379 regval = ioread32(priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
380 regval &= ~TSI721_SR_CHINT_IDBQRCV;
381 iowrite32(regval,
382 priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
383
384 schedule_work(&priv->idb_work);
385
386 return 0;
387 }
388
389 static void tsi721_db_dpc(struct work_struct *work)
390 {
391 struct tsi721_device *priv = container_of(work, struct tsi721_device,
392 idb_work);
393 struct rio_mport *mport;
394 struct rio_dbell *dbell;
395 int found = 0;
396 u32 wr_ptr, rd_ptr;
397 u64 *idb_entry;
398 u32 regval;
399 union {
400 u64 msg;
401 u8 bytes[8];
402 } idb;
403
404 /*
405 * Process queued inbound doorbells
406 */
407 mport = priv->mport;
408
409 wr_ptr = ioread32(priv->regs + TSI721_IDQ_WP(IDB_QUEUE)) % IDB_QSIZE;
410 rd_ptr = ioread32(priv->regs + TSI721_IDQ_RP(IDB_QUEUE)) % IDB_QSIZE;
411
412 while (wr_ptr != rd_ptr) {
413 idb_entry = (u64 *)(priv->idb_base +
414 (TSI721_IDB_ENTRY_SIZE * rd_ptr));
415 rd_ptr++;
416 rd_ptr %= IDB_QSIZE;
417 idb.msg = *idb_entry;
418 *idb_entry = 0;
419
420 /* Process one doorbell */
421 list_for_each_entry(dbell, &mport->dbells, node) {
422 if ((dbell->res->start <= DBELL_INF(idb.bytes)) &&
423 (dbell->res->end >= DBELL_INF(idb.bytes))) {
424 found = 1;
425 break;
426 }
427 }
428
429 if (found) {
430 dbell->dinb(mport, dbell->dev_id, DBELL_SID(idb.bytes),
431 DBELL_TID(idb.bytes), DBELL_INF(idb.bytes));
432 } else {
433 dev_dbg(&priv->pdev->dev,
434 "spurious inb doorbell, sid %2.2x tid %2.2x"
435 " info %4.4x\n", DBELL_SID(idb.bytes),
436 DBELL_TID(idb.bytes), DBELL_INF(idb.bytes));
437 }
438
439 wr_ptr = ioread32(priv->regs +
440 TSI721_IDQ_WP(IDB_QUEUE)) % IDB_QSIZE;
441 }
442
443 iowrite32(rd_ptr & (IDB_QSIZE - 1),
444 priv->regs + TSI721_IDQ_RP(IDB_QUEUE));
445
446 /* Re-enable IDB interrupts */
447 regval = ioread32(priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
448 regval |= TSI721_SR_CHINT_IDBQRCV;
449 iowrite32(regval,
450 priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
451
452 wr_ptr = ioread32(priv->regs + TSI721_IDQ_WP(IDB_QUEUE)) % IDB_QSIZE;
453 if (wr_ptr != rd_ptr)
454 schedule_work(&priv->idb_work);
455 }
456
457 /**
458 * tsi721_irqhandler - Tsi721 interrupt handler
459 * @irq: Linux interrupt number
460 * @ptr: Pointer to interrupt-specific data (mport structure)
461 *
462 * Handles Tsi721 interrupts signaled using MSI and INTA. Checks reported
463 * interrupt events and calls an event-specific handler(s).
464 */
465 static irqreturn_t tsi721_irqhandler(int irq, void *ptr)
466 {
467 struct rio_mport *mport = (struct rio_mport *)ptr;
468 struct tsi721_device *priv = mport->priv;
469 u32 dev_int;
470 u32 dev_ch_int;
471 u32 intval;
472 u32 ch_inte;
473
474 /* For MSI mode disable all device-level interrupts */
475 if (priv->flags & TSI721_USING_MSI)
476 iowrite32(0, priv->regs + TSI721_DEV_INTE);
477
478 dev_int = ioread32(priv->regs + TSI721_DEV_INT);
479 if (!dev_int)
480 return IRQ_NONE;
481
482 dev_ch_int = ioread32(priv->regs + TSI721_DEV_CHAN_INT);
483
484 if (dev_int & TSI721_DEV_INT_SR2PC_CH) {
485 /* Service SR2PC Channel interrupts */
486 if (dev_ch_int & TSI721_INT_SR2PC_CHAN(IDB_QUEUE)) {
487 /* Service Inbound Doorbell interrupt */
488 intval = ioread32(priv->regs +
489 TSI721_SR_CHINT(IDB_QUEUE));
490 if (intval & TSI721_SR_CHINT_IDBQRCV)
491 tsi721_dbell_handler(mport);
492 else
493 dev_info(&priv->pdev->dev,
494 "Unsupported SR_CH_INT %x\n", intval);
495
496 /* Clear interrupts */
497 iowrite32(intval,
498 priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
499 ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
500 }
501 }
502
503 if (dev_int & TSI721_DEV_INT_SMSG_CH) {
504 int ch;
505
506 /*
507 * Service channel interrupts from Messaging Engine
508 */
509
510 if (dev_ch_int & TSI721_INT_IMSG_CHAN_M) { /* Inbound Msg */
511 /* Disable signaled OB MSG Channel interrupts */
512 ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
513 ch_inte &= ~(dev_ch_int & TSI721_INT_IMSG_CHAN_M);
514 iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE);
515
516 /*
517 * Process Inbound Message interrupt for each MBOX
518 */
519 for (ch = 4; ch < RIO_MAX_MBOX + 4; ch++) {
520 if (!(dev_ch_int & TSI721_INT_IMSG_CHAN(ch)))
521 continue;
522 tsi721_imsg_handler(priv, ch);
523 }
524 }
525
526 if (dev_ch_int & TSI721_INT_OMSG_CHAN_M) { /* Outbound Msg */
527 /* Disable signaled OB MSG Channel interrupts */
528 ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
529 ch_inte &= ~(dev_ch_int & TSI721_INT_OMSG_CHAN_M);
530 iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE);
531
532 /*
533 * Process Outbound Message interrupts for each MBOX
534 */
535
536 for (ch = 0; ch < RIO_MAX_MBOX; ch++) {
537 if (!(dev_ch_int & TSI721_INT_OMSG_CHAN(ch)))
538 continue;
539 tsi721_omsg_handler(priv, ch);
540 }
541 }
542 }
543
544 if (dev_int & TSI721_DEV_INT_SRIO) {
545 /* Service SRIO MAC interrupts */
546 intval = ioread32(priv->regs + TSI721_RIO_EM_INT_STAT);
547 if (intval & TSI721_RIO_EM_INT_STAT_PW_RX)
548 tsi721_pw_handler(mport);
549 }
550
551 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
552 if (dev_int & TSI721_DEV_INT_BDMA_CH) {
553 int ch;
554
555 if (dev_ch_int & TSI721_INT_BDMA_CHAN_M) {
556 dev_dbg(&priv->pdev->dev,
557 "IRQ from DMA channel 0x%08x\n", dev_ch_int);
558
559 for (ch = 0; ch < TSI721_DMA_MAXCH; ch++) {
560 if (!(dev_ch_int & TSI721_INT_BDMA_CHAN(ch)))
561 continue;
562 tsi721_bdma_handler(&priv->bdma[ch]);
563 }
564 }
565 }
566 #endif
567
568 /* For MSI mode re-enable device-level interrupts */
569 if (priv->flags & TSI721_USING_MSI) {
570 dev_int = TSI721_DEV_INT_SR2PC_CH | TSI721_DEV_INT_SRIO |
571 TSI721_DEV_INT_SMSG_CH | TSI721_DEV_INT_BDMA_CH;
572 iowrite32(dev_int, priv->regs + TSI721_DEV_INTE);
573 }
574
575 return IRQ_HANDLED;
576 }
577
578 static void tsi721_interrupts_init(struct tsi721_device *priv)
579 {
580 u32 intr;
581
582 /* Enable IDB interrupts */
583 iowrite32(TSI721_SR_CHINT_ALL,
584 priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
585 iowrite32(TSI721_SR_CHINT_IDBQRCV,
586 priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
587
588 /* Enable SRIO MAC interrupts */
589 iowrite32(TSI721_RIO_EM_DEV_INT_EN_INT,
590 priv->regs + TSI721_RIO_EM_DEV_INT_EN);
591
592 /* Enable interrupts from channels in use */
593 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
594 intr = TSI721_INT_SR2PC_CHAN(IDB_QUEUE) |
595 (TSI721_INT_BDMA_CHAN_M &
596 ~TSI721_INT_BDMA_CHAN(TSI721_DMACH_MAINT));
597 #else
598 intr = TSI721_INT_SR2PC_CHAN(IDB_QUEUE);
599 #endif
600 iowrite32(intr, priv->regs + TSI721_DEV_CHAN_INTE);
601
602 if (priv->flags & TSI721_USING_MSIX)
603 intr = TSI721_DEV_INT_SRIO;
604 else
605 intr = TSI721_DEV_INT_SR2PC_CH | TSI721_DEV_INT_SRIO |
606 TSI721_DEV_INT_SMSG_CH | TSI721_DEV_INT_BDMA_CH;
607
608 iowrite32(intr, priv->regs + TSI721_DEV_INTE);
609 ioread32(priv->regs + TSI721_DEV_INTE);
610 }
611
612 #ifdef CONFIG_PCI_MSI
613 /**
614 * tsi721_omsg_msix - MSI-X interrupt handler for outbound messaging
615 * @irq: Linux interrupt number
616 * @ptr: Pointer to interrupt-specific data (mport structure)
617 *
618 * Handles outbound messaging interrupts signaled using MSI-X.
619 */
620 static irqreturn_t tsi721_omsg_msix(int irq, void *ptr)
621 {
622 struct tsi721_device *priv = ((struct rio_mport *)ptr)->priv;
623 int mbox;
624
625 mbox = (irq - priv->msix[TSI721_VECT_OMB0_DONE].vector) % RIO_MAX_MBOX;
626 tsi721_omsg_handler(priv, mbox);
627 return IRQ_HANDLED;
628 }
629
630 /**
631 * tsi721_imsg_msix - MSI-X interrupt handler for inbound messaging
632 * @irq: Linux interrupt number
633 * @ptr: Pointer to interrupt-specific data (mport structure)
634 *
635 * Handles inbound messaging interrupts signaled using MSI-X.
636 */
637 static irqreturn_t tsi721_imsg_msix(int irq, void *ptr)
638 {
639 struct tsi721_device *priv = ((struct rio_mport *)ptr)->priv;
640 int mbox;
641
642 mbox = (irq - priv->msix[TSI721_VECT_IMB0_RCV].vector) % RIO_MAX_MBOX;
643 tsi721_imsg_handler(priv, mbox + 4);
644 return IRQ_HANDLED;
645 }
646
647 /**
648 * tsi721_srio_msix - Tsi721 MSI-X SRIO MAC interrupt handler
649 * @irq: Linux interrupt number
650 * @ptr: Pointer to interrupt-specific data (mport structure)
651 *
652 * Handles Tsi721 interrupts from SRIO MAC.
653 */
654 static irqreturn_t tsi721_srio_msix(int irq, void *ptr)
655 {
656 struct tsi721_device *priv = ((struct rio_mport *)ptr)->priv;
657 u32 srio_int;
658
659 /* Service SRIO MAC interrupts */
660 srio_int = ioread32(priv->regs + TSI721_RIO_EM_INT_STAT);
661 if (srio_int & TSI721_RIO_EM_INT_STAT_PW_RX)
662 tsi721_pw_handler((struct rio_mport *)ptr);
663
664 return IRQ_HANDLED;
665 }
666
667 /**
668 * tsi721_sr2pc_ch_msix - Tsi721 MSI-X SR2PC Channel interrupt handler
669 * @irq: Linux interrupt number
670 * @ptr: Pointer to interrupt-specific data (mport structure)
671 *
672 * Handles Tsi721 interrupts from SR2PC Channel.
673 * NOTE: At this moment services only one SR2PC channel associated with inbound
674 * doorbells.
675 */
676 static irqreturn_t tsi721_sr2pc_ch_msix(int irq, void *ptr)
677 {
678 struct tsi721_device *priv = ((struct rio_mport *)ptr)->priv;
679 u32 sr_ch_int;
680
681 /* Service Inbound DB interrupt from SR2PC channel */
682 sr_ch_int = ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
683 if (sr_ch_int & TSI721_SR_CHINT_IDBQRCV)
684 tsi721_dbell_handler((struct rio_mport *)ptr);
685
686 /* Clear interrupts */
687 iowrite32(sr_ch_int, priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
688 /* Read back to ensure that interrupt was cleared */
689 sr_ch_int = ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
690
691 return IRQ_HANDLED;
692 }
693
694 /**
695 * tsi721_request_msix - register interrupt service for MSI-X mode.
696 * @mport: RapidIO master port structure
697 *
698 * Registers MSI-X interrupt service routines for interrupts that are active
699 * immediately after mport initialization. Messaging interrupt service routines
700 * should be registered during corresponding open requests.
701 */
702 static int tsi721_request_msix(struct rio_mport *mport)
703 {
704 struct tsi721_device *priv = mport->priv;
705 int err = 0;
706
707 err = request_irq(priv->msix[TSI721_VECT_IDB].vector,
708 tsi721_sr2pc_ch_msix, 0,
709 priv->msix[TSI721_VECT_IDB].irq_name, (void *)mport);
710 if (err)
711 goto out;
712
713 err = request_irq(priv->msix[TSI721_VECT_PWRX].vector,
714 tsi721_srio_msix, 0,
715 priv->msix[TSI721_VECT_PWRX].irq_name, (void *)mport);
716 if (err)
717 free_irq(
718 priv->msix[TSI721_VECT_IDB].vector,
719 (void *)mport);
720 out:
721 return err;
722 }
723
724 /**
725 * tsi721_enable_msix - Attempts to enable MSI-X support for Tsi721.
726 * @priv: pointer to tsi721 private data
727 *
728 * Configures MSI-X support for Tsi721. Supports only an exact number
729 * of requested vectors.
730 */
731 static int tsi721_enable_msix(struct tsi721_device *priv)
732 {
733 struct msix_entry entries[TSI721_VECT_MAX];
734 int err;
735 int i;
736
737 entries[TSI721_VECT_IDB].entry = TSI721_MSIX_SR2PC_IDBQ_RCV(IDB_QUEUE);
738 entries[TSI721_VECT_PWRX].entry = TSI721_MSIX_SRIO_MAC_INT;
739
740 /*
741 * Initialize MSI-X entries for Messaging Engine:
742 * this driver supports four RIO mailboxes (inbound and outbound)
743 * NOTE: Inbound message MBOX 0...4 use IB channels 4...7. Therefore
744 * offset +4 is added to IB MBOX number.
745 */
746 for (i = 0; i < RIO_MAX_MBOX; i++) {
747 entries[TSI721_VECT_IMB0_RCV + i].entry =
748 TSI721_MSIX_IMSG_DQ_RCV(i + 4);
749 entries[TSI721_VECT_IMB0_INT + i].entry =
750 TSI721_MSIX_IMSG_INT(i + 4);
751 entries[TSI721_VECT_OMB0_DONE + i].entry =
752 TSI721_MSIX_OMSG_DONE(i);
753 entries[TSI721_VECT_OMB0_INT + i].entry =
754 TSI721_MSIX_OMSG_INT(i);
755 }
756
757 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
758 /*
759 * Initialize MSI-X entries for Block DMA Engine:
760 * this driver supports XXX DMA channels
761 * (one is reserved for SRIO maintenance transactions)
762 */
763 for (i = 0; i < TSI721_DMA_CHNUM; i++) {
764 entries[TSI721_VECT_DMA0_DONE + i].entry =
765 TSI721_MSIX_DMACH_DONE(i);
766 entries[TSI721_VECT_DMA0_INT + i].entry =
767 TSI721_MSIX_DMACH_INT(i);
768 }
769 #endif /* CONFIG_RAPIDIO_DMA_ENGINE */
770
771 err = pci_enable_msix_exact(priv->pdev, entries, ARRAY_SIZE(entries));
772 if (err) {
773 dev_err(&priv->pdev->dev,
774 "Failed to enable MSI-X (err=%d)\n", err);
775 return err;
776 }
777
778 /*
779 * Copy MSI-X vector information into tsi721 private structure
780 */
781 priv->msix[TSI721_VECT_IDB].vector = entries[TSI721_VECT_IDB].vector;
782 snprintf(priv->msix[TSI721_VECT_IDB].irq_name, IRQ_DEVICE_NAME_MAX,
783 DRV_NAME "-idb@pci:%s", pci_name(priv->pdev));
784 priv->msix[TSI721_VECT_PWRX].vector = entries[TSI721_VECT_PWRX].vector;
785 snprintf(priv->msix[TSI721_VECT_PWRX].irq_name, IRQ_DEVICE_NAME_MAX,
786 DRV_NAME "-pwrx@pci:%s", pci_name(priv->pdev));
787
788 for (i = 0; i < RIO_MAX_MBOX; i++) {
789 priv->msix[TSI721_VECT_IMB0_RCV + i].vector =
790 entries[TSI721_VECT_IMB0_RCV + i].vector;
791 snprintf(priv->msix[TSI721_VECT_IMB0_RCV + i].irq_name,
792 IRQ_DEVICE_NAME_MAX, DRV_NAME "-imbr%d@pci:%s",
793 i, pci_name(priv->pdev));
794
795 priv->msix[TSI721_VECT_IMB0_INT + i].vector =
796 entries[TSI721_VECT_IMB0_INT + i].vector;
797 snprintf(priv->msix[TSI721_VECT_IMB0_INT + i].irq_name,
798 IRQ_DEVICE_NAME_MAX, DRV_NAME "-imbi%d@pci:%s",
799 i, pci_name(priv->pdev));
800
801 priv->msix[TSI721_VECT_OMB0_DONE + i].vector =
802 entries[TSI721_VECT_OMB0_DONE + i].vector;
803 snprintf(priv->msix[TSI721_VECT_OMB0_DONE + i].irq_name,
804 IRQ_DEVICE_NAME_MAX, DRV_NAME "-ombd%d@pci:%s",
805 i, pci_name(priv->pdev));
806
807 priv->msix[TSI721_VECT_OMB0_INT + i].vector =
808 entries[TSI721_VECT_OMB0_INT + i].vector;
809 snprintf(priv->msix[TSI721_VECT_OMB0_INT + i].irq_name,
810 IRQ_DEVICE_NAME_MAX, DRV_NAME "-ombi%d@pci:%s",
811 i, pci_name(priv->pdev));
812 }
813
814 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
815 for (i = 0; i < TSI721_DMA_CHNUM; i++) {
816 priv->msix[TSI721_VECT_DMA0_DONE + i].vector =
817 entries[TSI721_VECT_DMA0_DONE + i].vector;
818 snprintf(priv->msix[TSI721_VECT_DMA0_DONE + i].irq_name,
819 IRQ_DEVICE_NAME_MAX, DRV_NAME "-dmad%d@pci:%s",
820 i, pci_name(priv->pdev));
821
822 priv->msix[TSI721_VECT_DMA0_INT + i].vector =
823 entries[TSI721_VECT_DMA0_INT + i].vector;
824 snprintf(priv->msix[TSI721_VECT_DMA0_INT + i].irq_name,
825 IRQ_DEVICE_NAME_MAX, DRV_NAME "-dmai%d@pci:%s",
826 i, pci_name(priv->pdev));
827 }
828 #endif /* CONFIG_RAPIDIO_DMA_ENGINE */
829
830 return 0;
831 }
832 #endif /* CONFIG_PCI_MSI */
833
834 static int tsi721_request_irq(struct rio_mport *mport)
835 {
836 struct tsi721_device *priv = mport->priv;
837 int err;
838
839 #ifdef CONFIG_PCI_MSI
840 if (priv->flags & TSI721_USING_MSIX)
841 err = tsi721_request_msix(mport);
842 else
843 #endif
844 err = request_irq(priv->pdev->irq, tsi721_irqhandler,
845 (priv->flags & TSI721_USING_MSI) ? 0 : IRQF_SHARED,
846 DRV_NAME, (void *)mport);
847
848 if (err)
849 dev_err(&priv->pdev->dev,
850 "Unable to allocate interrupt, Error: %d\n", err);
851
852 return err;
853 }
854
855 /**
856 * tsi721_init_pc2sr_mapping - initializes outbound (PCIe->SRIO)
857 * translation regions.
858 * @priv: pointer to tsi721 private data
859 *
860 * Disables SREP translation regions.
861 */
862 static void tsi721_init_pc2sr_mapping(struct tsi721_device *priv)
863 {
864 int i;
865
866 /* Disable all PC2SR translation windows */
867 for (i = 0; i < TSI721_OBWIN_NUM; i++)
868 iowrite32(0, priv->regs + TSI721_OBWINLB(i));
869 }
870
871 /**
872 * tsi721_rio_map_inb_mem -- Mapping inbound memory region.
873 * @mport: RapidIO master port
874 * @lstart: Local memory space start address.
875 * @rstart: RapidIO space start address.
876 * @size: The mapping region size.
877 * @flags: Flags for mapping. 0 for using default flags.
878 *
879 * Return: 0 -- Success.
880 *
881 * This function will create the inbound mapping
882 * from rstart to lstart.
883 */
884 static int tsi721_rio_map_inb_mem(struct rio_mport *mport, dma_addr_t lstart,
885 u64 rstart, u32 size, u32 flags)
886 {
887 struct tsi721_device *priv = mport->priv;
888 int i, avail = -1;
889 u32 regval;
890 struct tsi721_ib_win *ib_win;
891 bool direct = (lstart == rstart);
892 u64 ibw_size;
893 dma_addr_t loc_start;
894 u64 ibw_start;
895 struct tsi721_ib_win_mapping *map = NULL;
896 int ret = -EBUSY;
897
898 if (direct) {
899 dev_dbg(&priv->pdev->dev,
900 "Direct (RIO_0x%llx -> PCIe_0x%pad), size=0x%x",
901 rstart, &lstart, size);
902
903 /* Calculate minimal acceptable window size and base address */
904
905 ibw_size = roundup_pow_of_two(size);
906 ibw_start = lstart & ~(ibw_size - 1);
907
908 while ((lstart + size) > (ibw_start + ibw_size)) {
909 ibw_size *= 2;
910 ibw_start = lstart & ~(ibw_size - 1);
911 if (ibw_size > 0x80000000) { /* Limit max size to 2GB */
912 return -EBUSY;
913 }
914 }
915
916 loc_start = ibw_start;
917
918 map = kzalloc(sizeof(struct tsi721_ib_win_mapping), GFP_ATOMIC);
919 if (map == NULL)
920 return -ENOMEM;
921
922 } else {
923 dev_dbg(&priv->pdev->dev,
924 "Translated (RIO_0x%llx -> PCIe_0x%pad), size=0x%x",
925 rstart, &lstart, size);
926
927 if (!is_power_of_2(size) || size < 0x1000 ||
928 ((u64)lstart & (size - 1)) || (rstart & (size - 1)))
929 return -EINVAL;
930 if (priv->ibwin_cnt == 0)
931 return -EBUSY;
932 ibw_start = rstart;
933 ibw_size = size;
934 loc_start = lstart;
935 }
936
937 /*
938 * Scan for overlapping with active regions and mark the first available
939 * IB window at the same time.
940 */
941 for (i = 0; i < TSI721_IBWIN_NUM; i++) {
942 ib_win = &priv->ib_win[i];
943
944 if (!ib_win->active) {
945 if (avail == -1) {
946 avail = i;
947 ret = 0;
948 }
949 } else if (ibw_start < (ib_win->rstart + ib_win->size) &&
950 (ibw_start + ibw_size) > ib_win->rstart) {
951 /* Return error if address translation involved */
952 if (direct && ib_win->xlat) {
953 ret = -EFAULT;
954 break;
955 }
956
957 /*
958 * Direct mappings usually are larger than originally
959 * requested fragments - check if this new request fits
960 * into it.
961 */
962 if (rstart >= ib_win->rstart &&
963 (rstart + size) <= (ib_win->rstart +
964 ib_win->size)) {
965 /* We are in - no further mapping required */
966 map->lstart = lstart;
967 list_add_tail(&map->node, &ib_win->mappings);
968 return 0;
969 }
970
971 ret = -EFAULT;
972 break;
973 }
974 }
975
976 if (ret)
977 goto out;
978 i = avail;
979
980 /* Sanity check: available IB window must be disabled at this point */
981 regval = ioread32(priv->regs + TSI721_IBWIN_LB(i));
982 if (WARN_ON(regval & TSI721_IBWIN_LB_WEN)) {
983 ret = -EIO;
984 goto out;
985 }
986
987 ib_win = &priv->ib_win[i];
988 ib_win->active = true;
989 ib_win->rstart = ibw_start;
990 ib_win->lstart = loc_start;
991 ib_win->size = ibw_size;
992 ib_win->xlat = (lstart != rstart);
993 INIT_LIST_HEAD(&ib_win->mappings);
994
995 /*
996 * When using direct IBW mapping and have larger than requested IBW size
997 * we can have multiple local memory blocks mapped through the same IBW
998 * To handle this situation we maintain list of "clients" for such IBWs.
999 */
1000 if (direct) {
1001 map->lstart = lstart;
1002 list_add_tail(&map->node, &ib_win->mappings);
1003 }
1004
1005 iowrite32(TSI721_IBWIN_SIZE(ibw_size) << 8,
1006 priv->regs + TSI721_IBWIN_SZ(i));
1007
1008 iowrite32(((u64)loc_start >> 32), priv->regs + TSI721_IBWIN_TUA(i));
1009 iowrite32(((u64)loc_start & TSI721_IBWIN_TLA_ADD),
1010 priv->regs + TSI721_IBWIN_TLA(i));
1011
1012 iowrite32(ibw_start >> 32, priv->regs + TSI721_IBWIN_UB(i));
1013 iowrite32((ibw_start & TSI721_IBWIN_LB_BA) | TSI721_IBWIN_LB_WEN,
1014 priv->regs + TSI721_IBWIN_LB(i));
1015
1016 priv->ibwin_cnt--;
1017
1018 dev_dbg(&priv->pdev->dev,
1019 "Configured IBWIN%d (RIO_0x%llx -> PCIe_0x%llx), size=0x%llx\n",
1020 i, ibw_start, (unsigned long long)loc_start, ibw_size);
1021
1022 return 0;
1023 out:
1024 kfree(map);
1025 return ret;
1026 }
1027
1028 /**
1029 * tsi721_rio_unmap_inb_mem -- Unmapping inbound memory region.
1030 * @mport: RapidIO master port
1031 * @lstart: Local memory space start address.
1032 */
1033 static void tsi721_rio_unmap_inb_mem(struct rio_mport *mport,
1034 dma_addr_t lstart)
1035 {
1036 struct tsi721_device *priv = mport->priv;
1037 struct tsi721_ib_win *ib_win;
1038 int i;
1039
1040 dev_dbg(&priv->pdev->dev,
1041 "Unmap IBW mapped to PCIe_0x%pad", &lstart);
1042
1043 /* Search for matching active inbound translation window */
1044 for (i = 0; i < TSI721_IBWIN_NUM; i++) {
1045 ib_win = &priv->ib_win[i];
1046
1047 /* Address translating IBWs must to be an exact march */
1048 if (!ib_win->active ||
1049 (ib_win->xlat && lstart != ib_win->lstart))
1050 continue;
1051
1052 if (lstart >= ib_win->lstart &&
1053 lstart < (ib_win->lstart + ib_win->size)) {
1054
1055 if (!ib_win->xlat) {
1056 struct tsi721_ib_win_mapping *map;
1057 int found = 0;
1058
1059 list_for_each_entry(map,
1060 &ib_win->mappings, node) {
1061 if (map->lstart == lstart) {
1062 list_del(&map->node);
1063 kfree(map);
1064 found = 1;
1065 break;
1066 }
1067 }
1068
1069 if (!found)
1070 continue;
1071
1072 if (!list_empty(&ib_win->mappings))
1073 break;
1074 }
1075
1076 dev_dbg(&priv->pdev->dev, "Disable IBWIN_%d", i);
1077 iowrite32(0, priv->regs + TSI721_IBWIN_LB(i));
1078 ib_win->active = false;
1079 priv->ibwin_cnt++;
1080 break;
1081 }
1082 }
1083
1084 if (i == TSI721_IBWIN_NUM)
1085 dev_dbg(&priv->pdev->dev,
1086 "IB window mapped to %pad not found", &lstart);
1087 }
1088
1089 /**
1090 * tsi721_init_sr2pc_mapping - initializes inbound (SRIO->PCIe)
1091 * translation regions.
1092 * @priv: pointer to tsi721 private data
1093 *
1094 * Disables inbound windows.
1095 */
1096 static void tsi721_init_sr2pc_mapping(struct tsi721_device *priv)
1097 {
1098 int i;
1099
1100 /* Disable all SR2PC inbound windows */
1101 for (i = 0; i < TSI721_IBWIN_NUM; i++)
1102 iowrite32(0, priv->regs + TSI721_IBWIN_LB(i));
1103 priv->ibwin_cnt = TSI721_IBWIN_NUM;
1104 }
1105
1106 /**
1107 * tsi721_port_write_init - Inbound port write interface init
1108 * @priv: pointer to tsi721 private data
1109 *
1110 * Initializes inbound port write handler.
1111 * Returns %0 on success or %-ENOMEM on failure.
1112 */
1113 static int tsi721_port_write_init(struct tsi721_device *priv)
1114 {
1115 priv->pw_discard_count = 0;
1116 INIT_WORK(&priv->pw_work, tsi721_pw_dpc);
1117 spin_lock_init(&priv->pw_fifo_lock);
1118 if (kfifo_alloc(&priv->pw_fifo,
1119 TSI721_RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) {
1120 dev_err(&priv->pdev->dev, "PW FIFO allocation failed\n");
1121 return -ENOMEM;
1122 }
1123
1124 /* Use reliable port-write capture mode */
1125 iowrite32(TSI721_RIO_PW_CTL_PWC_REL, priv->regs + TSI721_RIO_PW_CTL);
1126 return 0;
1127 }
1128
1129 static int tsi721_doorbell_init(struct tsi721_device *priv)
1130 {
1131 /* Outbound Doorbells do not require any setup.
1132 * Tsi721 uses dedicated PCI BAR1 to generate doorbells.
1133 * That BAR1 was mapped during the probe routine.
1134 */
1135
1136 /* Initialize Inbound Doorbell processing DPC and queue */
1137 priv->db_discard_count = 0;
1138 INIT_WORK(&priv->idb_work, tsi721_db_dpc);
1139
1140 /* Allocate buffer for inbound doorbells queue */
1141 priv->idb_base = dma_zalloc_coherent(&priv->pdev->dev,
1142 IDB_QSIZE * TSI721_IDB_ENTRY_SIZE,
1143 &priv->idb_dma, GFP_KERNEL);
1144 if (!priv->idb_base)
1145 return -ENOMEM;
1146
1147 dev_dbg(&priv->pdev->dev, "Allocated IDB buffer @ %p (phys = %llx)\n",
1148 priv->idb_base, (unsigned long long)priv->idb_dma);
1149
1150 iowrite32(TSI721_IDQ_SIZE_VAL(IDB_QSIZE),
1151 priv->regs + TSI721_IDQ_SIZE(IDB_QUEUE));
1152 iowrite32(((u64)priv->idb_dma >> 32),
1153 priv->regs + TSI721_IDQ_BASEU(IDB_QUEUE));
1154 iowrite32(((u64)priv->idb_dma & TSI721_IDQ_BASEL_ADDR),
1155 priv->regs + TSI721_IDQ_BASEL(IDB_QUEUE));
1156 /* Enable accepting all inbound doorbells */
1157 iowrite32(0, priv->regs + TSI721_IDQ_MASK(IDB_QUEUE));
1158
1159 iowrite32(TSI721_IDQ_INIT, priv->regs + TSI721_IDQ_CTL(IDB_QUEUE));
1160
1161 iowrite32(0, priv->regs + TSI721_IDQ_RP(IDB_QUEUE));
1162
1163 return 0;
1164 }
1165
1166 static void tsi721_doorbell_free(struct tsi721_device *priv)
1167 {
1168 if (priv->idb_base == NULL)
1169 return;
1170
1171 /* Free buffer allocated for inbound doorbell queue */
1172 dma_free_coherent(&priv->pdev->dev, IDB_QSIZE * TSI721_IDB_ENTRY_SIZE,
1173 priv->idb_base, priv->idb_dma);
1174 priv->idb_base = NULL;
1175 }
1176
1177 /**
1178 * tsi721_bdma_maint_init - Initialize maintenance request BDMA channel.
1179 * @priv: pointer to tsi721 private data
1180 *
1181 * Initialize BDMA channel allocated for RapidIO maintenance read/write
1182 * request generation
1183 * Returns %0 on success or %-ENOMEM on failure.
1184 */
1185 static int tsi721_bdma_maint_init(struct tsi721_device *priv)
1186 {
1187 struct tsi721_dma_desc *bd_ptr;
1188 u64 *sts_ptr;
1189 dma_addr_t bd_phys, sts_phys;
1190 int sts_size;
1191 int bd_num = 2;
1192 void __iomem *regs;
1193
1194 dev_dbg(&priv->pdev->dev,
1195 "Init Block DMA Engine for Maintenance requests, CH%d\n",
1196 TSI721_DMACH_MAINT);
1197
1198 /*
1199 * Initialize DMA channel for maintenance requests
1200 */
1201
1202 priv->mdma.ch_id = TSI721_DMACH_MAINT;
1203 regs = priv->regs + TSI721_DMAC_BASE(TSI721_DMACH_MAINT);
1204
1205 /* Allocate space for DMA descriptors */
1206 bd_ptr = dma_zalloc_coherent(&priv->pdev->dev,
1207 bd_num * sizeof(struct tsi721_dma_desc),
1208 &bd_phys, GFP_KERNEL);
1209 if (!bd_ptr)
1210 return -ENOMEM;
1211
1212 priv->mdma.bd_num = bd_num;
1213 priv->mdma.bd_phys = bd_phys;
1214 priv->mdma.bd_base = bd_ptr;
1215
1216 dev_dbg(&priv->pdev->dev, "DMA descriptors @ %p (phys = %llx)\n",
1217 bd_ptr, (unsigned long long)bd_phys);
1218
1219 /* Allocate space for descriptor status FIFO */
1220 sts_size = (bd_num >= TSI721_DMA_MINSTSSZ) ?
1221 bd_num : TSI721_DMA_MINSTSSZ;
1222 sts_size = roundup_pow_of_two(sts_size);
1223 sts_ptr = dma_zalloc_coherent(&priv->pdev->dev,
1224 sts_size * sizeof(struct tsi721_dma_sts),
1225 &sts_phys, GFP_KERNEL);
1226 if (!sts_ptr) {
1227 /* Free space allocated for DMA descriptors */
1228 dma_free_coherent(&priv->pdev->dev,
1229 bd_num * sizeof(struct tsi721_dma_desc),
1230 bd_ptr, bd_phys);
1231 priv->mdma.bd_base = NULL;
1232 return -ENOMEM;
1233 }
1234
1235 priv->mdma.sts_phys = sts_phys;
1236 priv->mdma.sts_base = sts_ptr;
1237 priv->mdma.sts_size = sts_size;
1238
1239 dev_dbg(&priv->pdev->dev,
1240 "desc status FIFO @ %p (phys = %llx) size=0x%x\n",
1241 sts_ptr, (unsigned long long)sts_phys, sts_size);
1242
1243 /* Initialize DMA descriptors ring */
1244 bd_ptr[bd_num - 1].type_id = cpu_to_le32(DTYPE3 << 29);
1245 bd_ptr[bd_num - 1].next_lo = cpu_to_le32((u64)bd_phys &
1246 TSI721_DMAC_DPTRL_MASK);
1247 bd_ptr[bd_num - 1].next_hi = cpu_to_le32((u64)bd_phys >> 32);
1248
1249 /* Setup DMA descriptor pointers */
1250 iowrite32(((u64)bd_phys >> 32), regs + TSI721_DMAC_DPTRH);
1251 iowrite32(((u64)bd_phys & TSI721_DMAC_DPTRL_MASK),
1252 regs + TSI721_DMAC_DPTRL);
1253
1254 /* Setup descriptor status FIFO */
1255 iowrite32(((u64)sts_phys >> 32), regs + TSI721_DMAC_DSBH);
1256 iowrite32(((u64)sts_phys & TSI721_DMAC_DSBL_MASK),
1257 regs + TSI721_DMAC_DSBL);
1258 iowrite32(TSI721_DMAC_DSSZ_SIZE(sts_size),
1259 regs + TSI721_DMAC_DSSZ);
1260
1261 /* Clear interrupt bits */
1262 iowrite32(TSI721_DMAC_INT_ALL, regs + TSI721_DMAC_INT);
1263
1264 ioread32(regs + TSI721_DMAC_INT);
1265
1266 /* Toggle DMA channel initialization */
1267 iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL);
1268 ioread32(regs + TSI721_DMAC_CTL);
1269 udelay(10);
1270
1271 return 0;
1272 }
1273
1274 static int tsi721_bdma_maint_free(struct tsi721_device *priv)
1275 {
1276 u32 ch_stat;
1277 struct tsi721_bdma_maint *mdma = &priv->mdma;
1278 void __iomem *regs = priv->regs + TSI721_DMAC_BASE(mdma->ch_id);
1279
1280 if (mdma->bd_base == NULL)
1281 return 0;
1282
1283 /* Check if DMA channel still running */
1284 ch_stat = ioread32(regs + TSI721_DMAC_STS);
1285 if (ch_stat & TSI721_DMAC_STS_RUN)
1286 return -EFAULT;
1287
1288 /* Put DMA channel into init state */
1289 iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL);
1290
1291 /* Free space allocated for DMA descriptors */
1292 dma_free_coherent(&priv->pdev->dev,
1293 mdma->bd_num * sizeof(struct tsi721_dma_desc),
1294 mdma->bd_base, mdma->bd_phys);
1295 mdma->bd_base = NULL;
1296
1297 /* Free space allocated for status FIFO */
1298 dma_free_coherent(&priv->pdev->dev,
1299 mdma->sts_size * sizeof(struct tsi721_dma_sts),
1300 mdma->sts_base, mdma->sts_phys);
1301 mdma->sts_base = NULL;
1302 return 0;
1303 }
1304
1305 /* Enable Inbound Messaging Interrupts */
1306 static void
1307 tsi721_imsg_interrupt_enable(struct tsi721_device *priv, int ch,
1308 u32 inte_mask)
1309 {
1310 u32 rval;
1311
1312 if (!inte_mask)
1313 return;
1314
1315 /* Clear pending Inbound Messaging interrupts */
1316 iowrite32(inte_mask, priv->regs + TSI721_IBDMAC_INT(ch));
1317
1318 /* Enable Inbound Messaging interrupts */
1319 rval = ioread32(priv->regs + TSI721_IBDMAC_INTE(ch));
1320 iowrite32(rval | inte_mask, priv->regs + TSI721_IBDMAC_INTE(ch));
1321
1322 if (priv->flags & TSI721_USING_MSIX)
1323 return; /* Finished if we are in MSI-X mode */
1324
1325 /*
1326 * For MSI and INTA interrupt signalling we need to enable next levels
1327 */
1328
1329 /* Enable Device Channel Interrupt */
1330 rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1331 iowrite32(rval | TSI721_INT_IMSG_CHAN(ch),
1332 priv->regs + TSI721_DEV_CHAN_INTE);
1333 }
1334
1335 /* Disable Inbound Messaging Interrupts */
1336 static void
1337 tsi721_imsg_interrupt_disable(struct tsi721_device *priv, int ch,
1338 u32 inte_mask)
1339 {
1340 u32 rval;
1341
1342 if (!inte_mask)
1343 return;
1344
1345 /* Clear pending Inbound Messaging interrupts */
1346 iowrite32(inte_mask, priv->regs + TSI721_IBDMAC_INT(ch));
1347
1348 /* Disable Inbound Messaging interrupts */
1349 rval = ioread32(priv->regs + TSI721_IBDMAC_INTE(ch));
1350 rval &= ~inte_mask;
1351 iowrite32(rval, priv->regs + TSI721_IBDMAC_INTE(ch));
1352
1353 if (priv->flags & TSI721_USING_MSIX)
1354 return; /* Finished if we are in MSI-X mode */
1355
1356 /*
1357 * For MSI and INTA interrupt signalling we need to disable next levels
1358 */
1359
1360 /* Disable Device Channel Interrupt */
1361 rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1362 rval &= ~TSI721_INT_IMSG_CHAN(ch);
1363 iowrite32(rval, priv->regs + TSI721_DEV_CHAN_INTE);
1364 }
1365
1366 /* Enable Outbound Messaging interrupts */
1367 static void
1368 tsi721_omsg_interrupt_enable(struct tsi721_device *priv, int ch,
1369 u32 inte_mask)
1370 {
1371 u32 rval;
1372
1373 if (!inte_mask)
1374 return;
1375
1376 /* Clear pending Outbound Messaging interrupts */
1377 iowrite32(inte_mask, priv->regs + TSI721_OBDMAC_INT(ch));
1378
1379 /* Enable Outbound Messaging channel interrupts */
1380 rval = ioread32(priv->regs + TSI721_OBDMAC_INTE(ch));
1381 iowrite32(rval | inte_mask, priv->regs + TSI721_OBDMAC_INTE(ch));
1382
1383 if (priv->flags & TSI721_USING_MSIX)
1384 return; /* Finished if we are in MSI-X mode */
1385
1386 /*
1387 * For MSI and INTA interrupt signalling we need to enable next levels
1388 */
1389
1390 /* Enable Device Channel Interrupt */
1391 rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1392 iowrite32(rval | TSI721_INT_OMSG_CHAN(ch),
1393 priv->regs + TSI721_DEV_CHAN_INTE);
1394 }
1395
1396 /* Disable Outbound Messaging interrupts */
1397 static void
1398 tsi721_omsg_interrupt_disable(struct tsi721_device *priv, int ch,
1399 u32 inte_mask)
1400 {
1401 u32 rval;
1402
1403 if (!inte_mask)
1404 return;
1405
1406 /* Clear pending Outbound Messaging interrupts */
1407 iowrite32(inte_mask, priv->regs + TSI721_OBDMAC_INT(ch));
1408
1409 /* Disable Outbound Messaging interrupts */
1410 rval = ioread32(priv->regs + TSI721_OBDMAC_INTE(ch));
1411 rval &= ~inte_mask;
1412 iowrite32(rval, priv->regs + TSI721_OBDMAC_INTE(ch));
1413
1414 if (priv->flags & TSI721_USING_MSIX)
1415 return; /* Finished if we are in MSI-X mode */
1416
1417 /*
1418 * For MSI and INTA interrupt signalling we need to disable next levels
1419 */
1420
1421 /* Disable Device Channel Interrupt */
1422 rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1423 rval &= ~TSI721_INT_OMSG_CHAN(ch);
1424 iowrite32(rval, priv->regs + TSI721_DEV_CHAN_INTE);
1425 }
1426
1427 /**
1428 * tsi721_add_outb_message - Add message to the Tsi721 outbound message queue
1429 * @mport: Master port with outbound message queue
1430 * @rdev: Target of outbound message
1431 * @mbox: Outbound mailbox
1432 * @buffer: Message to add to outbound queue
1433 * @len: Length of message
1434 */
1435 static int
1436 tsi721_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
1437 void *buffer, size_t len)
1438 {
1439 struct tsi721_device *priv = mport->priv;
1440 struct tsi721_omsg_desc *desc;
1441 u32 tx_slot;
1442
1443 if (!priv->omsg_init[mbox] ||
1444 len > TSI721_MSG_MAX_SIZE || len < 8)
1445 return -EINVAL;
1446
1447 tx_slot = priv->omsg_ring[mbox].tx_slot;
1448
1449 /* Copy copy message into transfer buffer */
1450 memcpy(priv->omsg_ring[mbox].omq_base[tx_slot], buffer, len);
1451
1452 if (len & 0x7)
1453 len += 8;
1454
1455 /* Build descriptor associated with buffer */
1456 desc = priv->omsg_ring[mbox].omd_base;
1457 desc[tx_slot].type_id = cpu_to_le32((DTYPE4 << 29) | rdev->destid);
1458 if (tx_slot % 4 == 0)
1459 desc[tx_slot].type_id |= cpu_to_le32(TSI721_OMD_IOF);
1460
1461 desc[tx_slot].msg_info =
1462 cpu_to_le32((mport->sys_size << 26) | (mbox << 22) |
1463 (0xe << 12) | (len & 0xff8));
1464 desc[tx_slot].bufptr_lo =
1465 cpu_to_le32((u64)priv->omsg_ring[mbox].omq_phys[tx_slot] &
1466 0xffffffff);
1467 desc[tx_slot].bufptr_hi =
1468 cpu_to_le32((u64)priv->omsg_ring[mbox].omq_phys[tx_slot] >> 32);
1469
1470 priv->omsg_ring[mbox].wr_count++;
1471
1472 /* Go to next descriptor */
1473 if (++priv->omsg_ring[mbox].tx_slot == priv->omsg_ring[mbox].size) {
1474 priv->omsg_ring[mbox].tx_slot = 0;
1475 /* Move through the ring link descriptor at the end */
1476 priv->omsg_ring[mbox].wr_count++;
1477 }
1478
1479 mb();
1480
1481 /* Set new write count value */
1482 iowrite32(priv->omsg_ring[mbox].wr_count,
1483 priv->regs + TSI721_OBDMAC_DWRCNT(mbox));
1484 ioread32(priv->regs + TSI721_OBDMAC_DWRCNT(mbox));
1485
1486 return 0;
1487 }
1488
1489 /**
1490 * tsi721_omsg_handler - Outbound Message Interrupt Handler
1491 * @priv: pointer to tsi721 private data
1492 * @ch: number of OB MSG channel to service
1493 *
1494 * Services channel interrupts from outbound messaging engine.
1495 */
1496 static void tsi721_omsg_handler(struct tsi721_device *priv, int ch)
1497 {
1498 u32 omsg_int;
1499
1500 spin_lock(&priv->omsg_ring[ch].lock);
1501
1502 omsg_int = ioread32(priv->regs + TSI721_OBDMAC_INT(ch));
1503
1504 if (omsg_int & TSI721_OBDMAC_INT_ST_FULL)
1505 dev_info(&priv->pdev->dev,
1506 "OB MBOX%d: Status FIFO is full\n", ch);
1507
1508 if (omsg_int & (TSI721_OBDMAC_INT_DONE | TSI721_OBDMAC_INT_IOF_DONE)) {
1509 u32 srd_ptr;
1510 u64 *sts_ptr, last_ptr = 0, prev_ptr = 0;
1511 int i, j;
1512 u32 tx_slot;
1513
1514 /*
1515 * Find last successfully processed descriptor
1516 */
1517
1518 /* Check and clear descriptor status FIFO entries */
1519 srd_ptr = priv->omsg_ring[ch].sts_rdptr;
1520 sts_ptr = priv->omsg_ring[ch].sts_base;
1521 j = srd_ptr * 8;
1522 while (sts_ptr[j]) {
1523 for (i = 0; i < 8 && sts_ptr[j]; i++, j++) {
1524 prev_ptr = last_ptr;
1525 last_ptr = le64_to_cpu(sts_ptr[j]);
1526 sts_ptr[j] = 0;
1527 }
1528
1529 ++srd_ptr;
1530 srd_ptr %= priv->omsg_ring[ch].sts_size;
1531 j = srd_ptr * 8;
1532 }
1533
1534 if (last_ptr == 0)
1535 goto no_sts_update;
1536
1537 priv->omsg_ring[ch].sts_rdptr = srd_ptr;
1538 iowrite32(srd_ptr, priv->regs + TSI721_OBDMAC_DSRP(ch));
1539
1540 if (!priv->mport->outb_msg[ch].mcback)
1541 goto no_sts_update;
1542
1543 /* Inform upper layer about transfer completion */
1544
1545 tx_slot = (last_ptr - (u64)priv->omsg_ring[ch].omd_phys)/
1546 sizeof(struct tsi721_omsg_desc);
1547
1548 /*
1549 * Check if this is a Link Descriptor (LD).
1550 * If yes, ignore LD and use descriptor processed
1551 * before LD.
1552 */
1553 if (tx_slot == priv->omsg_ring[ch].size) {
1554 if (prev_ptr)
1555 tx_slot = (prev_ptr -
1556 (u64)priv->omsg_ring[ch].omd_phys)/
1557 sizeof(struct tsi721_omsg_desc);
1558 else
1559 goto no_sts_update;
1560 }
1561
1562 /* Move slot index to the next message to be sent */
1563 ++tx_slot;
1564 if (tx_slot == priv->omsg_ring[ch].size)
1565 tx_slot = 0;
1566 BUG_ON(tx_slot >= priv->omsg_ring[ch].size);
1567 priv->mport->outb_msg[ch].mcback(priv->mport,
1568 priv->omsg_ring[ch].dev_id, ch,
1569 tx_slot);
1570 }
1571
1572 no_sts_update:
1573
1574 if (omsg_int & TSI721_OBDMAC_INT_ERROR) {
1575 /*
1576 * Outbound message operation aborted due to error,
1577 * reinitialize OB MSG channel
1578 */
1579
1580 dev_dbg(&priv->pdev->dev, "OB MSG ABORT ch_stat=%x\n",
1581 ioread32(priv->regs + TSI721_OBDMAC_STS(ch)));
1582
1583 iowrite32(TSI721_OBDMAC_INT_ERROR,
1584 priv->regs + TSI721_OBDMAC_INT(ch));
1585 iowrite32(TSI721_OBDMAC_CTL_INIT,
1586 priv->regs + TSI721_OBDMAC_CTL(ch));
1587 ioread32(priv->regs + TSI721_OBDMAC_CTL(ch));
1588
1589 /* Inform upper level to clear all pending tx slots */
1590 if (priv->mport->outb_msg[ch].mcback)
1591 priv->mport->outb_msg[ch].mcback(priv->mport,
1592 priv->omsg_ring[ch].dev_id, ch,
1593 priv->omsg_ring[ch].tx_slot);
1594 /* Synch tx_slot tracking */
1595 iowrite32(priv->omsg_ring[ch].tx_slot,
1596 priv->regs + TSI721_OBDMAC_DRDCNT(ch));
1597 ioread32(priv->regs + TSI721_OBDMAC_DRDCNT(ch));
1598 priv->omsg_ring[ch].wr_count = priv->omsg_ring[ch].tx_slot;
1599 priv->omsg_ring[ch].sts_rdptr = 0;
1600 }
1601
1602 /* Clear channel interrupts */
1603 iowrite32(omsg_int, priv->regs + TSI721_OBDMAC_INT(ch));
1604
1605 if (!(priv->flags & TSI721_USING_MSIX)) {
1606 u32 ch_inte;
1607
1608 /* Re-enable channel interrupts */
1609 ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1610 ch_inte |= TSI721_INT_OMSG_CHAN(ch);
1611 iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE);
1612 }
1613
1614 spin_unlock(&priv->omsg_ring[ch].lock);
1615 }
1616
1617 /**
1618 * tsi721_open_outb_mbox - Initialize Tsi721 outbound mailbox
1619 * @mport: Master port implementing Outbound Messaging Engine
1620 * @dev_id: Device specific pointer to pass on event
1621 * @mbox: Mailbox to open
1622 * @entries: Number of entries in the outbound mailbox ring
1623 */
1624 static int tsi721_open_outb_mbox(struct rio_mport *mport, void *dev_id,
1625 int mbox, int entries)
1626 {
1627 struct tsi721_device *priv = mport->priv;
1628 struct tsi721_omsg_desc *bd_ptr;
1629 int i, rc = 0;
1630
1631 if ((entries < TSI721_OMSGD_MIN_RING_SIZE) ||
1632 (entries > (TSI721_OMSGD_RING_SIZE)) ||
1633 (!is_power_of_2(entries)) || mbox >= RIO_MAX_MBOX) {
1634 rc = -EINVAL;
1635 goto out;
1636 }
1637
1638 priv->omsg_ring[mbox].dev_id = dev_id;
1639 priv->omsg_ring[mbox].size = entries;
1640 priv->omsg_ring[mbox].sts_rdptr = 0;
1641 spin_lock_init(&priv->omsg_ring[mbox].lock);
1642
1643 /* Outbound Msg Buffer allocation based on
1644 the number of maximum descriptor entries */
1645 for (i = 0; i < entries; i++) {
1646 priv->omsg_ring[mbox].omq_base[i] =
1647 dma_alloc_coherent(
1648 &priv->pdev->dev, TSI721_MSG_BUFFER_SIZE,
1649 &priv->omsg_ring[mbox].omq_phys[i],
1650 GFP_KERNEL);
1651 if (priv->omsg_ring[mbox].omq_base[i] == NULL) {
1652 dev_dbg(&priv->pdev->dev,
1653 "Unable to allocate OB MSG data buffer for"
1654 " MBOX%d\n", mbox);
1655 rc = -ENOMEM;
1656 goto out_buf;
1657 }
1658 }
1659
1660 /* Outbound message descriptor allocation */
1661 priv->omsg_ring[mbox].omd_base = dma_alloc_coherent(
1662 &priv->pdev->dev,
1663 (entries + 1) * sizeof(struct tsi721_omsg_desc),
1664 &priv->omsg_ring[mbox].omd_phys, GFP_KERNEL);
1665 if (priv->omsg_ring[mbox].omd_base == NULL) {
1666 dev_dbg(&priv->pdev->dev,
1667 "Unable to allocate OB MSG descriptor memory "
1668 "for MBOX%d\n", mbox);
1669 rc = -ENOMEM;
1670 goto out_buf;
1671 }
1672
1673 priv->omsg_ring[mbox].tx_slot = 0;
1674
1675 /* Outbound message descriptor status FIFO allocation */
1676 priv->omsg_ring[mbox].sts_size = roundup_pow_of_two(entries + 1);
1677 priv->omsg_ring[mbox].sts_base = dma_zalloc_coherent(&priv->pdev->dev,
1678 priv->omsg_ring[mbox].sts_size *
1679 sizeof(struct tsi721_dma_sts),
1680 &priv->omsg_ring[mbox].sts_phys, GFP_KERNEL);
1681 if (priv->omsg_ring[mbox].sts_base == NULL) {
1682 dev_dbg(&priv->pdev->dev,
1683 "Unable to allocate OB MSG descriptor status FIFO "
1684 "for MBOX%d\n", mbox);
1685 rc = -ENOMEM;
1686 goto out_desc;
1687 }
1688
1689 /*
1690 * Configure Outbound Messaging Engine
1691 */
1692
1693 /* Setup Outbound Message descriptor pointer */
1694 iowrite32(((u64)priv->omsg_ring[mbox].omd_phys >> 32),
1695 priv->regs + TSI721_OBDMAC_DPTRH(mbox));
1696 iowrite32(((u64)priv->omsg_ring[mbox].omd_phys &
1697 TSI721_OBDMAC_DPTRL_MASK),
1698 priv->regs + TSI721_OBDMAC_DPTRL(mbox));
1699
1700 /* Setup Outbound Message descriptor status FIFO */
1701 iowrite32(((u64)priv->omsg_ring[mbox].sts_phys >> 32),
1702 priv->regs + TSI721_OBDMAC_DSBH(mbox));
1703 iowrite32(((u64)priv->omsg_ring[mbox].sts_phys &
1704 TSI721_OBDMAC_DSBL_MASK),
1705 priv->regs + TSI721_OBDMAC_DSBL(mbox));
1706 iowrite32(TSI721_DMAC_DSSZ_SIZE(priv->omsg_ring[mbox].sts_size),
1707 priv->regs + (u32)TSI721_OBDMAC_DSSZ(mbox));
1708
1709 /* Enable interrupts */
1710
1711 #ifdef CONFIG_PCI_MSI
1712 if (priv->flags & TSI721_USING_MSIX) {
1713 /* Request interrupt service if we are in MSI-X mode */
1714 rc = request_irq(
1715 priv->msix[TSI721_VECT_OMB0_DONE + mbox].vector,
1716 tsi721_omsg_msix, 0,
1717 priv->msix[TSI721_VECT_OMB0_DONE + mbox].irq_name,
1718 (void *)mport);
1719
1720 if (rc) {
1721 dev_dbg(&priv->pdev->dev,
1722 "Unable to allocate MSI-X interrupt for "
1723 "OBOX%d-DONE\n", mbox);
1724 goto out_stat;
1725 }
1726
1727 rc = request_irq(priv->msix[TSI721_VECT_OMB0_INT + mbox].vector,
1728 tsi721_omsg_msix, 0,
1729 priv->msix[TSI721_VECT_OMB0_INT + mbox].irq_name,
1730 (void *)mport);
1731
1732 if (rc) {
1733 dev_dbg(&priv->pdev->dev,
1734 "Unable to allocate MSI-X interrupt for "
1735 "MBOX%d-INT\n", mbox);
1736 free_irq(
1737 priv->msix[TSI721_VECT_OMB0_DONE + mbox].vector,
1738 (void *)mport);
1739 goto out_stat;
1740 }
1741 }
1742 #endif /* CONFIG_PCI_MSI */
1743
1744 tsi721_omsg_interrupt_enable(priv, mbox, TSI721_OBDMAC_INT_ALL);
1745
1746 /* Initialize Outbound Message descriptors ring */
1747 bd_ptr = priv->omsg_ring[mbox].omd_base;
1748 bd_ptr[entries].type_id = cpu_to_le32(DTYPE5 << 29);
1749 bd_ptr[entries].msg_info = 0;
1750 bd_ptr[entries].next_lo =
1751 cpu_to_le32((u64)priv->omsg_ring[mbox].omd_phys &
1752 TSI721_OBDMAC_DPTRL_MASK);
1753 bd_ptr[entries].next_hi =
1754 cpu_to_le32((u64)priv->omsg_ring[mbox].omd_phys >> 32);
1755 priv->omsg_ring[mbox].wr_count = 0;
1756 mb();
1757
1758 /* Initialize Outbound Message engine */
1759 iowrite32(TSI721_OBDMAC_CTL_INIT, priv->regs + TSI721_OBDMAC_CTL(mbox));
1760 ioread32(priv->regs + TSI721_OBDMAC_DWRCNT(mbox));
1761 udelay(10);
1762
1763 priv->omsg_init[mbox] = 1;
1764
1765 return 0;
1766
1767 #ifdef CONFIG_PCI_MSI
1768 out_stat:
1769 dma_free_coherent(&priv->pdev->dev,
1770 priv->omsg_ring[mbox].sts_size * sizeof(struct tsi721_dma_sts),
1771 priv->omsg_ring[mbox].sts_base,
1772 priv->omsg_ring[mbox].sts_phys);
1773
1774 priv->omsg_ring[mbox].sts_base = NULL;
1775 #endif /* CONFIG_PCI_MSI */
1776
1777 out_desc:
1778 dma_free_coherent(&priv->pdev->dev,
1779 (entries + 1) * sizeof(struct tsi721_omsg_desc),
1780 priv->omsg_ring[mbox].omd_base,
1781 priv->omsg_ring[mbox].omd_phys);
1782
1783 priv->omsg_ring[mbox].omd_base = NULL;
1784
1785 out_buf:
1786 for (i = 0; i < priv->omsg_ring[mbox].size; i++) {
1787 if (priv->omsg_ring[mbox].omq_base[i]) {
1788 dma_free_coherent(&priv->pdev->dev,
1789 TSI721_MSG_BUFFER_SIZE,
1790 priv->omsg_ring[mbox].omq_base[i],
1791 priv->omsg_ring[mbox].omq_phys[i]);
1792
1793 priv->omsg_ring[mbox].omq_base[i] = NULL;
1794 }
1795 }
1796
1797 out:
1798 return rc;
1799 }
1800
1801 /**
1802 * tsi721_close_outb_mbox - Close Tsi721 outbound mailbox
1803 * @mport: Master port implementing the outbound message unit
1804 * @mbox: Mailbox to close
1805 */
1806 static void tsi721_close_outb_mbox(struct rio_mport *mport, int mbox)
1807 {
1808 struct tsi721_device *priv = mport->priv;
1809 u32 i;
1810
1811 if (!priv->omsg_init[mbox])
1812 return;
1813 priv->omsg_init[mbox] = 0;
1814
1815 /* Disable Interrupts */
1816
1817 tsi721_omsg_interrupt_disable(priv, mbox, TSI721_OBDMAC_INT_ALL);
1818
1819 #ifdef CONFIG_PCI_MSI
1820 if (priv->flags & TSI721_USING_MSIX) {
1821 free_irq(priv->msix[TSI721_VECT_OMB0_DONE + mbox].vector,
1822 (void *)mport);
1823 free_irq(priv->msix[TSI721_VECT_OMB0_INT + mbox].vector,
1824 (void *)mport);
1825 }
1826 #endif /* CONFIG_PCI_MSI */
1827
1828 /* Free OMSG Descriptor Status FIFO */
1829 dma_free_coherent(&priv->pdev->dev,
1830 priv->omsg_ring[mbox].sts_size * sizeof(struct tsi721_dma_sts),
1831 priv->omsg_ring[mbox].sts_base,
1832 priv->omsg_ring[mbox].sts_phys);
1833
1834 priv->omsg_ring[mbox].sts_base = NULL;
1835
1836 /* Free OMSG descriptors */
1837 dma_free_coherent(&priv->pdev->dev,
1838 (priv->omsg_ring[mbox].size + 1) *
1839 sizeof(struct tsi721_omsg_desc),
1840 priv->omsg_ring[mbox].omd_base,
1841 priv->omsg_ring[mbox].omd_phys);
1842
1843 priv->omsg_ring[mbox].omd_base = NULL;
1844
1845 /* Free message buffers */
1846 for (i = 0; i < priv->omsg_ring[mbox].size; i++) {
1847 if (priv->omsg_ring[mbox].omq_base[i]) {
1848 dma_free_coherent(&priv->pdev->dev,
1849 TSI721_MSG_BUFFER_SIZE,
1850 priv->omsg_ring[mbox].omq_base[i],
1851 priv->omsg_ring[mbox].omq_phys[i]);
1852
1853 priv->omsg_ring[mbox].omq_base[i] = NULL;
1854 }
1855 }
1856 }
1857
1858 /**
1859 * tsi721_imsg_handler - Inbound Message Interrupt Handler
1860 * @priv: pointer to tsi721 private data
1861 * @ch: inbound message channel number to service
1862 *
1863 * Services channel interrupts from inbound messaging engine.
1864 */
1865 static void tsi721_imsg_handler(struct tsi721_device *priv, int ch)
1866 {
1867 u32 mbox = ch - 4;
1868 u32 imsg_int;
1869
1870 spin_lock(&priv->imsg_ring[mbox].lock);
1871
1872 imsg_int = ioread32(priv->regs + TSI721_IBDMAC_INT(ch));
1873
1874 if (imsg_int & TSI721_IBDMAC_INT_SRTO)
1875 dev_info(&priv->pdev->dev, "IB MBOX%d SRIO timeout\n",
1876 mbox);
1877
1878 if (imsg_int & TSI721_IBDMAC_INT_PC_ERROR)
1879 dev_info(&priv->pdev->dev, "IB MBOX%d PCIe error\n",
1880 mbox);
1881
1882 if (imsg_int & TSI721_IBDMAC_INT_FQ_LOW)
1883 dev_info(&priv->pdev->dev,
1884 "IB MBOX%d IB free queue low\n", mbox);
1885
1886 /* Clear IB channel interrupts */
1887 iowrite32(imsg_int, priv->regs + TSI721_IBDMAC_INT(ch));
1888
1889 /* If an IB Msg is received notify the upper layer */
1890 if (imsg_int & TSI721_IBDMAC_INT_DQ_RCV &&
1891 priv->mport->inb_msg[mbox].mcback)
1892 priv->mport->inb_msg[mbox].mcback(priv->mport,
1893 priv->imsg_ring[mbox].dev_id, mbox, -1);
1894
1895 if (!(priv->flags & TSI721_USING_MSIX)) {
1896 u32 ch_inte;
1897
1898 /* Re-enable channel interrupts */
1899 ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1900 ch_inte |= TSI721_INT_IMSG_CHAN(ch);
1901 iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE);
1902 }
1903
1904 spin_unlock(&priv->imsg_ring[mbox].lock);
1905 }
1906
1907 /**
1908 * tsi721_open_inb_mbox - Initialize Tsi721 inbound mailbox
1909 * @mport: Master port implementing the Inbound Messaging Engine
1910 * @dev_id: Device specific pointer to pass on event
1911 * @mbox: Mailbox to open
1912 * @entries: Number of entries in the inbound mailbox ring
1913 */
1914 static int tsi721_open_inb_mbox(struct rio_mport *mport, void *dev_id,
1915 int mbox, int entries)
1916 {
1917 struct tsi721_device *priv = mport->priv;
1918 int ch = mbox + 4;
1919 int i;
1920 u64 *free_ptr;
1921 int rc = 0;
1922
1923 if ((entries < TSI721_IMSGD_MIN_RING_SIZE) ||
1924 (entries > TSI721_IMSGD_RING_SIZE) ||
1925 (!is_power_of_2(entries)) || mbox >= RIO_MAX_MBOX) {
1926 rc = -EINVAL;
1927 goto out;
1928 }
1929
1930 /* Initialize IB Messaging Ring */
1931 priv->imsg_ring[mbox].dev_id = dev_id;
1932 priv->imsg_ring[mbox].size = entries;
1933 priv->imsg_ring[mbox].rx_slot = 0;
1934 priv->imsg_ring[mbox].desc_rdptr = 0;
1935 priv->imsg_ring[mbox].fq_wrptr = 0;
1936 for (i = 0; i < priv->imsg_ring[mbox].size; i++)
1937 priv->imsg_ring[mbox].imq_base[i] = NULL;
1938 spin_lock_init(&priv->imsg_ring[mbox].lock);
1939
1940 /* Allocate buffers for incoming messages */
1941 priv->imsg_ring[mbox].buf_base =
1942 dma_alloc_coherent(&priv->pdev->dev,
1943 entries * TSI721_MSG_BUFFER_SIZE,
1944 &priv->imsg_ring[mbox].buf_phys,
1945 GFP_KERNEL);
1946
1947 if (priv->imsg_ring[mbox].buf_base == NULL) {
1948 dev_err(&priv->pdev->dev,
1949 "Failed to allocate buffers for IB MBOX%d\n", mbox);
1950 rc = -ENOMEM;
1951 goto out;
1952 }
1953
1954 /* Allocate memory for circular free list */
1955 priv->imsg_ring[mbox].imfq_base =
1956 dma_alloc_coherent(&priv->pdev->dev,
1957 entries * 8,
1958 &priv->imsg_ring[mbox].imfq_phys,
1959 GFP_KERNEL);
1960
1961 if (priv->imsg_ring[mbox].imfq_base == NULL) {
1962 dev_err(&priv->pdev->dev,
1963 "Failed to allocate free queue for IB MBOX%d\n", mbox);
1964 rc = -ENOMEM;
1965 goto out_buf;
1966 }
1967
1968 /* Allocate memory for Inbound message descriptors */
1969 priv->imsg_ring[mbox].imd_base =
1970 dma_alloc_coherent(&priv->pdev->dev,
1971 entries * sizeof(struct tsi721_imsg_desc),
1972 &priv->imsg_ring[mbox].imd_phys, GFP_KERNEL);
1973
1974 if (priv->imsg_ring[mbox].imd_base == NULL) {
1975 dev_err(&priv->pdev->dev,
1976 "Failed to allocate descriptor memory for IB MBOX%d\n",
1977 mbox);
1978 rc = -ENOMEM;
1979 goto out_dma;
1980 }
1981
1982 /* Fill free buffer pointer list */
1983 free_ptr = priv->imsg_ring[mbox].imfq_base;
1984 for (i = 0; i < entries; i++)
1985 free_ptr[i] = cpu_to_le64(
1986 (u64)(priv->imsg_ring[mbox].buf_phys) +
1987 i * 0x1000);
1988
1989 mb();
1990
1991 /*
1992 * For mapping of inbound SRIO Messages into appropriate queues we need
1993 * to set Inbound Device ID register in the messaging engine. We do it
1994 * once when first inbound mailbox is requested.
1995 */
1996 if (!(priv->flags & TSI721_IMSGID_SET)) {
1997 iowrite32((u32)priv->mport->host_deviceid,
1998 priv->regs + TSI721_IB_DEVID);
1999 priv->flags |= TSI721_IMSGID_SET;
2000 }
2001
2002 /*
2003 * Configure Inbound Messaging channel (ch = mbox + 4)
2004 */
2005
2006 /* Setup Inbound Message free queue */
2007 iowrite32(((u64)priv->imsg_ring[mbox].imfq_phys >> 32),
2008 priv->regs + TSI721_IBDMAC_FQBH(ch));
2009 iowrite32(((u64)priv->imsg_ring[mbox].imfq_phys &
2010 TSI721_IBDMAC_FQBL_MASK),
2011 priv->regs+TSI721_IBDMAC_FQBL(ch));
2012 iowrite32(TSI721_DMAC_DSSZ_SIZE(entries),
2013 priv->regs + TSI721_IBDMAC_FQSZ(ch));
2014
2015 /* Setup Inbound Message descriptor queue */
2016 iowrite32(((u64)priv->imsg_ring[mbox].imd_phys >> 32),
2017 priv->regs + TSI721_IBDMAC_DQBH(ch));
2018 iowrite32(((u32)priv->imsg_ring[mbox].imd_phys &
2019 (u32)TSI721_IBDMAC_DQBL_MASK),
2020 priv->regs+TSI721_IBDMAC_DQBL(ch));
2021 iowrite32(TSI721_DMAC_DSSZ_SIZE(entries),
2022 priv->regs + TSI721_IBDMAC_DQSZ(ch));
2023
2024 /* Enable interrupts */
2025
2026 #ifdef CONFIG_PCI_MSI
2027 if (priv->flags & TSI721_USING_MSIX) {
2028 /* Request interrupt service if we are in MSI-X mode */
2029 rc = request_irq(priv->msix[TSI721_VECT_IMB0_RCV + mbox].vector,
2030 tsi721_imsg_msix, 0,
2031 priv->msix[TSI721_VECT_IMB0_RCV + mbox].irq_name,
2032 (void *)mport);
2033
2034 if (rc) {
2035 dev_dbg(&priv->pdev->dev,
2036 "Unable to allocate MSI-X interrupt for "
2037 "IBOX%d-DONE\n", mbox);
2038 goto out_desc;
2039 }
2040
2041 rc = request_irq(priv->msix[TSI721_VECT_IMB0_INT + mbox].vector,
2042 tsi721_imsg_msix, 0,
2043 priv->msix[TSI721_VECT_IMB0_INT + mbox].irq_name,
2044 (void *)mport);
2045
2046 if (rc) {
2047 dev_dbg(&priv->pdev->dev,
2048 "Unable to allocate MSI-X interrupt for "
2049 "IBOX%d-INT\n", mbox);
2050 free_irq(
2051 priv->msix[TSI721_VECT_IMB0_RCV + mbox].vector,
2052 (void *)mport);
2053 goto out_desc;
2054 }
2055 }
2056 #endif /* CONFIG_PCI_MSI */
2057
2058 tsi721_imsg_interrupt_enable(priv, ch, TSI721_IBDMAC_INT_ALL);
2059
2060 /* Initialize Inbound Message Engine */
2061 iowrite32(TSI721_IBDMAC_CTL_INIT, priv->regs + TSI721_IBDMAC_CTL(ch));
2062 ioread32(priv->regs + TSI721_IBDMAC_CTL(ch));
2063 udelay(10);
2064 priv->imsg_ring[mbox].fq_wrptr = entries - 1;
2065 iowrite32(entries - 1, priv->regs + TSI721_IBDMAC_FQWP(ch));
2066
2067 priv->imsg_init[mbox] = 1;
2068 return 0;
2069
2070 #ifdef CONFIG_PCI_MSI
2071 out_desc:
2072 dma_free_coherent(&priv->pdev->dev,
2073 priv->imsg_ring[mbox].size * sizeof(struct tsi721_imsg_desc),
2074 priv->imsg_ring[mbox].imd_base,
2075 priv->imsg_ring[mbox].imd_phys);
2076
2077 priv->imsg_ring[mbox].imd_base = NULL;
2078 #endif /* CONFIG_PCI_MSI */
2079
2080 out_dma:
2081 dma_free_coherent(&priv->pdev->dev,
2082 priv->imsg_ring[mbox].size * 8,
2083 priv->imsg_ring[mbox].imfq_base,
2084 priv->imsg_ring[mbox].imfq_phys);
2085
2086 priv->imsg_ring[mbox].imfq_base = NULL;
2087
2088 out_buf:
2089 dma_free_coherent(&priv->pdev->dev,
2090 priv->imsg_ring[mbox].size * TSI721_MSG_BUFFER_SIZE,
2091 priv->imsg_ring[mbox].buf_base,
2092 priv->imsg_ring[mbox].buf_phys);
2093
2094 priv->imsg_ring[mbox].buf_base = NULL;
2095
2096 out:
2097 return rc;
2098 }
2099
2100 /**
2101 * tsi721_close_inb_mbox - Shut down Tsi721 inbound mailbox
2102 * @mport: Master port implementing the Inbound Messaging Engine
2103 * @mbox: Mailbox to close
2104 */
2105 static void tsi721_close_inb_mbox(struct rio_mport *mport, int mbox)
2106 {
2107 struct tsi721_device *priv = mport->priv;
2108 u32 rx_slot;
2109 int ch = mbox + 4;
2110
2111 if (!priv->imsg_init[mbox]) /* mbox isn't initialized yet */
2112 return;
2113 priv->imsg_init[mbox] = 0;
2114
2115 /* Disable Inbound Messaging Engine */
2116
2117 /* Disable Interrupts */
2118 tsi721_imsg_interrupt_disable(priv, ch, TSI721_OBDMAC_INT_MASK);
2119
2120 #ifdef CONFIG_PCI_MSI
2121 if (priv->flags & TSI721_USING_MSIX) {
2122 free_irq(priv->msix[TSI721_VECT_IMB0_RCV + mbox].vector,
2123 (void *)mport);
2124 free_irq(priv->msix[TSI721_VECT_IMB0_INT + mbox].vector,
2125 (void *)mport);
2126 }
2127 #endif /* CONFIG_PCI_MSI */
2128
2129 /* Clear Inbound Buffer Queue */
2130 for (rx_slot = 0; rx_slot < priv->imsg_ring[mbox].size; rx_slot++)
2131 priv->imsg_ring[mbox].imq_base[rx_slot] = NULL;
2132
2133 /* Free memory allocated for message buffers */
2134 dma_free_coherent(&priv->pdev->dev,
2135 priv->imsg_ring[mbox].size * TSI721_MSG_BUFFER_SIZE,
2136 priv->imsg_ring[mbox].buf_base,
2137 priv->imsg_ring[mbox].buf_phys);
2138
2139 priv->imsg_ring[mbox].buf_base = NULL;
2140
2141 /* Free memory allocated for free pointr list */
2142 dma_free_coherent(&priv->pdev->dev,
2143 priv->imsg_ring[mbox].size * 8,
2144 priv->imsg_ring[mbox].imfq_base,
2145 priv->imsg_ring[mbox].imfq_phys);
2146
2147 priv->imsg_ring[mbox].imfq_base = NULL;
2148
2149 /* Free memory allocated for RX descriptors */
2150 dma_free_coherent(&priv->pdev->dev,
2151 priv->imsg_ring[mbox].size * sizeof(struct tsi721_imsg_desc),
2152 priv->imsg_ring[mbox].imd_base,
2153 priv->imsg_ring[mbox].imd_phys);
2154
2155 priv->imsg_ring[mbox].imd_base = NULL;
2156 }
2157
2158 /**
2159 * tsi721_add_inb_buffer - Add buffer to the Tsi721 inbound message queue
2160 * @mport: Master port implementing the Inbound Messaging Engine
2161 * @mbox: Inbound mailbox number
2162 * @buf: Buffer to add to inbound queue
2163 */
2164 static int tsi721_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
2165 {
2166 struct tsi721_device *priv = mport->priv;
2167 u32 rx_slot;
2168 int rc = 0;
2169
2170 rx_slot = priv->imsg_ring[mbox].rx_slot;
2171 if (priv->imsg_ring[mbox].imq_base[rx_slot]) {
2172 dev_err(&priv->pdev->dev,
2173 "Error adding inbound buffer %d, buffer exists\n",
2174 rx_slot);
2175 rc = -EINVAL;
2176 goto out;
2177 }
2178
2179 priv->imsg_ring[mbox].imq_base[rx_slot] = buf;
2180
2181 if (++priv->imsg_ring[mbox].rx_slot == priv->imsg_ring[mbox].size)
2182 priv->imsg_ring[mbox].rx_slot = 0;
2183
2184 out:
2185 return rc;
2186 }
2187
2188 /**
2189 * tsi721_get_inb_message - Fetch inbound message from the Tsi721 MSG Queue
2190 * @mport: Master port implementing the Inbound Messaging Engine
2191 * @mbox: Inbound mailbox number
2192 *
2193 * Returns pointer to the message on success or NULL on failure.
2194 */
2195 static void *tsi721_get_inb_message(struct rio_mport *mport, int mbox)
2196 {
2197 struct tsi721_device *priv = mport->priv;
2198 struct tsi721_imsg_desc *desc;
2199 u32 rx_slot;
2200 void *rx_virt = NULL;
2201 u64 rx_phys;
2202 void *buf = NULL;
2203 u64 *free_ptr;
2204 int ch = mbox + 4;
2205 int msg_size;
2206
2207 if (!priv->imsg_init[mbox])
2208 return NULL;
2209
2210 desc = priv->imsg_ring[mbox].imd_base;
2211 desc += priv->imsg_ring[mbox].desc_rdptr;
2212
2213 if (!(le32_to_cpu(desc->msg_info) & TSI721_IMD_HO))
2214 goto out;
2215
2216 rx_slot = priv->imsg_ring[mbox].rx_slot;
2217 while (priv->imsg_ring[mbox].imq_base[rx_slot] == NULL) {
2218 if (++rx_slot == priv->imsg_ring[mbox].size)
2219 rx_slot = 0;
2220 }
2221
2222 rx_phys = ((u64)le32_to_cpu(desc->bufptr_hi) << 32) |
2223 le32_to_cpu(desc->bufptr_lo);
2224
2225 rx_virt = priv->imsg_ring[mbox].buf_base +
2226 (rx_phys - (u64)priv->imsg_ring[mbox].buf_phys);
2227
2228 buf = priv->imsg_ring[mbox].imq_base[rx_slot];
2229 msg_size = le32_to_cpu(desc->msg_info) & TSI721_IMD_BCOUNT;
2230 if (msg_size == 0)
2231 msg_size = RIO_MAX_MSG_SIZE;
2232
2233 memcpy(buf, rx_virt, msg_size);
2234 priv->imsg_ring[mbox].imq_base[rx_slot] = NULL;
2235
2236 desc->msg_info &= cpu_to_le32(~TSI721_IMD_HO);
2237 if (++priv->imsg_ring[mbox].desc_rdptr == priv->imsg_ring[mbox].size)
2238 priv->imsg_ring[mbox].desc_rdptr = 0;
2239
2240 iowrite32(priv->imsg_ring[mbox].desc_rdptr,
2241 priv->regs + TSI721_IBDMAC_DQRP(ch));
2242
2243 /* Return free buffer into the pointer list */
2244 free_ptr = priv->imsg_ring[mbox].imfq_base;
2245 free_ptr[priv->imsg_ring[mbox].fq_wrptr] = cpu_to_le64(rx_phys);
2246
2247 if (++priv->imsg_ring[mbox].fq_wrptr == priv->imsg_ring[mbox].size)
2248 priv->imsg_ring[mbox].fq_wrptr = 0;
2249
2250 iowrite32(priv->imsg_ring[mbox].fq_wrptr,
2251 priv->regs + TSI721_IBDMAC_FQWP(ch));
2252 out:
2253 return buf;
2254 }
2255
2256 /**
2257 * tsi721_messages_init - Initialization of Messaging Engine
2258 * @priv: pointer to tsi721 private data
2259 *
2260 * Configures Tsi721 messaging engine.
2261 */
2262 static int tsi721_messages_init(struct tsi721_device *priv)
2263 {
2264 int ch;
2265
2266 iowrite32(0, priv->regs + TSI721_SMSG_ECC_LOG);
2267 iowrite32(0, priv->regs + TSI721_RETRY_GEN_CNT);
2268 iowrite32(0, priv->regs + TSI721_RETRY_RX_CNT);
2269
2270 /* Set SRIO Message Request/Response Timeout */
2271 iowrite32(TSI721_RQRPTO_VAL, priv->regs + TSI721_RQRPTO);
2272
2273 /* Initialize Inbound Messaging Engine Registers */
2274 for (ch = 0; ch < TSI721_IMSG_CHNUM; ch++) {
2275 /* Clear interrupt bits */
2276 iowrite32(TSI721_IBDMAC_INT_MASK,
2277 priv->regs + TSI721_IBDMAC_INT(ch));
2278 /* Clear Status */
2279 iowrite32(0, priv->regs + TSI721_IBDMAC_STS(ch));
2280
2281 iowrite32(TSI721_SMSG_ECC_COR_LOG_MASK,
2282 priv->regs + TSI721_SMSG_ECC_COR_LOG(ch));
2283 iowrite32(TSI721_SMSG_ECC_NCOR_MASK,
2284 priv->regs + TSI721_SMSG_ECC_NCOR(ch));
2285 }
2286
2287 return 0;
2288 }
2289
2290 /**
2291 * tsi721_query_mport - Fetch inbound message from the Tsi721 MSG Queue
2292 * @mport: Master port implementing the Inbound Messaging Engine
2293 * @mbox: Inbound mailbox number
2294 *
2295 * Returns pointer to the message on success or NULL on failure.
2296 */
2297 static int tsi721_query_mport(struct rio_mport *mport,
2298 struct rio_mport_attr *attr)
2299 {
2300 struct tsi721_device *priv = mport->priv;
2301 u32 rval;
2302
2303 rval = ioread32(priv->regs + (0x100 + RIO_PORT_N_ERR_STS_CSR(0)));
2304 if (rval & RIO_PORT_N_ERR_STS_PORT_OK) {
2305 rval = ioread32(priv->regs + (0x100 + RIO_PORT_N_CTL2_CSR(0)));
2306 attr->link_speed = (rval & RIO_PORT_N_CTL2_SEL_BAUD) >> 28;
2307 rval = ioread32(priv->regs + (0x100 + RIO_PORT_N_CTL_CSR(0)));
2308 attr->link_width = (rval & RIO_PORT_N_CTL_IPW) >> 27;
2309 } else
2310 attr->link_speed = RIO_LINK_DOWN;
2311
2312 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
2313 attr->flags = RIO_MPORT_DMA | RIO_MPORT_DMA_SG;
2314 attr->dma_max_sge = 0;
2315 attr->dma_max_size = TSI721_BDMA_MAX_BCOUNT;
2316 attr->dma_align = 0;
2317 #else
2318 attr->flags = 0;
2319 #endif
2320 return 0;
2321 }
2322
2323 /**
2324 * tsi721_disable_ints - disables all device interrupts
2325 * @priv: pointer to tsi721 private data
2326 */
2327 static void tsi721_disable_ints(struct tsi721_device *priv)
2328 {
2329 int ch;
2330
2331 /* Disable all device level interrupts */
2332 iowrite32(0, priv->regs + TSI721_DEV_INTE);
2333
2334 /* Disable all Device Channel interrupts */
2335 iowrite32(0, priv->regs + TSI721_DEV_CHAN_INTE);
2336
2337 /* Disable all Inbound Msg Channel interrupts */
2338 for (ch = 0; ch < TSI721_IMSG_CHNUM; ch++)
2339 iowrite32(0, priv->regs + TSI721_IBDMAC_INTE(ch));
2340
2341 /* Disable all Outbound Msg Channel interrupts */
2342 for (ch = 0; ch < TSI721_OMSG_CHNUM; ch++)
2343 iowrite32(0, priv->regs + TSI721_OBDMAC_INTE(ch));
2344
2345 /* Disable all general messaging interrupts */
2346 iowrite32(0, priv->regs + TSI721_SMSG_INTE);
2347
2348 /* Disable all BDMA Channel interrupts */
2349 for (ch = 0; ch < TSI721_DMA_MAXCH; ch++)
2350 iowrite32(0,
2351 priv->regs + TSI721_DMAC_BASE(ch) + TSI721_DMAC_INTE);
2352
2353 /* Disable all general BDMA interrupts */
2354 iowrite32(0, priv->regs + TSI721_BDMA_INTE);
2355
2356 /* Disable all SRIO Channel interrupts */
2357 for (ch = 0; ch < TSI721_SRIO_MAXCH; ch++)
2358 iowrite32(0, priv->regs + TSI721_SR_CHINTE(ch));
2359
2360 /* Disable all general SR2PC interrupts */
2361 iowrite32(0, priv->regs + TSI721_SR2PC_GEN_INTE);
2362
2363 /* Disable all PC2SR interrupts */
2364 iowrite32(0, priv->regs + TSI721_PC2SR_INTE);
2365
2366 /* Disable all I2C interrupts */
2367 iowrite32(0, priv->regs + TSI721_I2C_INT_ENABLE);
2368
2369 /* Disable SRIO MAC interrupts */
2370 iowrite32(0, priv->regs + TSI721_RIO_EM_INT_ENABLE);
2371 iowrite32(0, priv->regs + TSI721_RIO_EM_DEV_INT_EN);
2372 }
2373
2374 /**
2375 * tsi721_setup_mport - Setup Tsi721 as RapidIO subsystem master port
2376 * @priv: pointer to tsi721 private data
2377 *
2378 * Configures Tsi721 as RapidIO master port.
2379 */
2380 static int tsi721_setup_mport(struct tsi721_device *priv)
2381 {
2382 struct pci_dev *pdev = priv->pdev;
2383 int err = 0;
2384 struct rio_ops *ops;
2385
2386 struct rio_mport *mport;
2387
2388 ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
2389 if (!ops) {
2390 dev_dbg(&pdev->dev, "Unable to allocate memory for rio_ops\n");
2391 return -ENOMEM;
2392 }
2393
2394 ops->lcread = tsi721_lcread;
2395 ops->lcwrite = tsi721_lcwrite;
2396 ops->cread = tsi721_cread_dma;
2397 ops->cwrite = tsi721_cwrite_dma;
2398 ops->dsend = tsi721_dsend;
2399 ops->open_inb_mbox = tsi721_open_inb_mbox;
2400 ops->close_inb_mbox = tsi721_close_inb_mbox;
2401 ops->open_outb_mbox = tsi721_open_outb_mbox;
2402 ops->close_outb_mbox = tsi721_close_outb_mbox;
2403 ops->add_outb_message = tsi721_add_outb_message;
2404 ops->add_inb_buffer = tsi721_add_inb_buffer;
2405 ops->get_inb_message = tsi721_get_inb_message;
2406 ops->map_inb = tsi721_rio_map_inb_mem;
2407 ops->unmap_inb = tsi721_rio_unmap_inb_mem;
2408 ops->query_mport = tsi721_query_mport;
2409
2410 mport = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
2411 if (!mport) {
2412 kfree(ops);
2413 dev_dbg(&pdev->dev, "Unable to allocate memory for mport\n");
2414 return -ENOMEM;
2415 }
2416
2417 mport->ops = ops;
2418 mport->index = 0;
2419 mport->sys_size = 0; /* small system */
2420 mport->phy_type = RIO_PHY_SERIAL;
2421 mport->priv = (void *)priv;
2422 mport->phys_efptr = 0x100;
2423 mport->dev.parent = &pdev->dev;
2424 priv->mport = mport;
2425
2426 INIT_LIST_HEAD(&mport->dbells);
2427
2428 rio_init_dbell_res(&mport->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
2429 rio_init_mbox_res(&mport->riores[RIO_INB_MBOX_RESOURCE], 0, 3);
2430 rio_init_mbox_res(&mport->riores[RIO_OUTB_MBOX_RESOURCE], 0, 3);
2431 snprintf(mport->name, RIO_MAX_MPORT_NAME, "%s(%s)",
2432 dev_driver_string(&pdev->dev), dev_name(&pdev->dev));
2433
2434 /* Hook up interrupt handler */
2435
2436 #ifdef CONFIG_PCI_MSI
2437 if (!tsi721_enable_msix(priv))
2438 priv->flags |= TSI721_USING_MSIX;
2439 else if (!pci_enable_msi(pdev))
2440 priv->flags |= TSI721_USING_MSI;
2441 else
2442 dev_info(&pdev->dev,
2443 "MSI/MSI-X is not available. Using legacy INTx.\n");
2444 #endif /* CONFIG_PCI_MSI */
2445
2446 err = tsi721_request_irq(mport);
2447
2448 if (!err) {
2449 tsi721_interrupts_init(priv);
2450 ops->pwenable = tsi721_pw_enable;
2451 } else {
2452 dev_err(&pdev->dev, "Unable to get assigned PCI IRQ "
2453 "vector %02X err=0x%x\n", pdev->irq, err);
2454 goto err_exit;
2455 }
2456
2457 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
2458 tsi721_register_dma(priv);
2459 #endif
2460 /* Enable SRIO link */
2461 iowrite32(ioread32(priv->regs + TSI721_DEVCTL) |
2462 TSI721_DEVCTL_SRBOOT_CMPL,
2463 priv->regs + TSI721_DEVCTL);
2464
2465 rio_register_mport(mport);
2466
2467 if (mport->host_deviceid >= 0)
2468 iowrite32(RIO_PORT_GEN_HOST | RIO_PORT_GEN_MASTER |
2469 RIO_PORT_GEN_DISCOVERED,
2470 priv->regs + (0x100 + RIO_PORT_GEN_CTL_CSR));
2471 else
2472 iowrite32(0, priv->regs + (0x100 + RIO_PORT_GEN_CTL_CSR));
2473
2474 return 0;
2475
2476 err_exit:
2477 kfree(mport);
2478 kfree(ops);
2479 return err;
2480 }
2481
2482 static int tsi721_probe(struct pci_dev *pdev,
2483 const struct pci_device_id *id)
2484 {
2485 struct tsi721_device *priv;
2486 int err;
2487
2488 priv = kzalloc(sizeof(struct tsi721_device), GFP_KERNEL);
2489 if (priv == NULL) {
2490 dev_err(&pdev->dev, "Failed to allocate memory for device\n");
2491 err = -ENOMEM;
2492 goto err_exit;
2493 }
2494
2495 err = pci_enable_device(pdev);
2496 if (err) {
2497 dev_err(&pdev->dev, "Failed to enable PCI device\n");
2498 goto err_clean;
2499 }
2500
2501 priv->pdev = pdev;
2502
2503 #ifdef DEBUG
2504 {
2505 int i;
2506 for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
2507 dev_dbg(&pdev->dev, "res[%d] @ 0x%llx (0x%lx, 0x%lx)\n",
2508 i, (unsigned long long)pci_resource_start(pdev, i),
2509 (unsigned long)pci_resource_len(pdev, i),
2510 pci_resource_flags(pdev, i));
2511 }
2512 }
2513 #endif
2514 /*
2515 * Verify BAR configuration
2516 */
2517
2518 /* BAR_0 (registers) must be 512KB+ in 32-bit address space */
2519 if (!(pci_resource_flags(pdev, BAR_0) & IORESOURCE_MEM) ||
2520 pci_resource_flags(pdev, BAR_0) & IORESOURCE_MEM_64 ||
2521 pci_resource_len(pdev, BAR_0) < TSI721_REG_SPACE_SIZE) {
2522 dev_err(&pdev->dev,
2523 "Missing or misconfigured CSR BAR0, aborting.\n");
2524 err = -ENODEV;
2525 goto err_disable_pdev;
2526 }
2527
2528 /* BAR_1 (outbound doorbells) must be 16MB+ in 32-bit address space */
2529 if (!(pci_resource_flags(pdev, BAR_1) & IORESOURCE_MEM) ||
2530 pci_resource_flags(pdev, BAR_1) & IORESOURCE_MEM_64 ||
2531 pci_resource_len(pdev, BAR_1) < TSI721_DB_WIN_SIZE) {
2532 dev_err(&pdev->dev,
2533 "Missing or misconfigured Doorbell BAR1, aborting.\n");
2534 err = -ENODEV;
2535 goto err_disable_pdev;
2536 }
2537
2538 /*
2539 * BAR_2 and BAR_4 (outbound translation) must be in 64-bit PCIe address
2540 * space.
2541 * NOTE: BAR_2 and BAR_4 are not used by this version of driver.
2542 * It may be a good idea to keep them disabled using HW configuration
2543 * to save PCI memory space.
2544 */
2545 if ((pci_resource_flags(pdev, BAR_2) & IORESOURCE_MEM) &&
2546 (pci_resource_flags(pdev, BAR_2) & IORESOURCE_MEM_64)) {
2547 dev_info(&pdev->dev, "Outbound BAR2 is not used but enabled.\n");
2548 }
2549
2550 if ((pci_resource_flags(pdev, BAR_4) & IORESOURCE_MEM) &&
2551 (pci_resource_flags(pdev, BAR_4) & IORESOURCE_MEM_64)) {
2552 dev_info(&pdev->dev, "Outbound BAR4 is not used but enabled.\n");
2553 }
2554
2555 err = pci_request_regions(pdev, DRV_NAME);
2556 if (err) {
2557 dev_err(&pdev->dev, "Cannot obtain PCI resources, "
2558 "aborting.\n");
2559 goto err_disable_pdev;
2560 }
2561
2562 pci_set_master(pdev);
2563
2564 priv->regs = pci_ioremap_bar(pdev, BAR_0);
2565 if (!priv->regs) {
2566 dev_err(&pdev->dev,
2567 "Unable to map device registers space, aborting\n");
2568 err = -ENOMEM;
2569 goto err_free_res;
2570 }
2571
2572 priv->odb_base = pci_ioremap_bar(pdev, BAR_1);
2573 if (!priv->odb_base) {
2574 dev_err(&pdev->dev,
2575 "Unable to map outbound doorbells space, aborting\n");
2576 err = -ENOMEM;
2577 goto err_unmap_bars;
2578 }
2579
2580 /* Configure DMA attributes. */
2581 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2582 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2583 if (err) {
2584 dev_info(&pdev->dev, "Unable to set DMA mask\n");
2585 goto err_unmap_bars;
2586 }
2587
2588 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2589 dev_info(&pdev->dev, "Unable to set consistent DMA mask\n");
2590 } else {
2591 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
2592 if (err)
2593 dev_info(&pdev->dev, "Unable to set consistent DMA mask\n");
2594 }
2595
2596 BUG_ON(!pci_is_pcie(pdev));
2597
2598 /* Clear "no snoop" and "relaxed ordering" bits. */
2599 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
2600 PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
2601
2602 /* Adjust PCIe completion timeout. */
2603 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL2, 0xf, 0x2);
2604
2605 /*
2606 * FIXUP: correct offsets of MSI-X tables in the MSI-X Capability Block
2607 */
2608 pci_write_config_dword(pdev, TSI721_PCIECFG_EPCTL, 0x01);
2609 pci_write_config_dword(pdev, TSI721_PCIECFG_MSIXTBL,
2610 TSI721_MSIXTBL_OFFSET);
2611 pci_write_config_dword(pdev, TSI721_PCIECFG_MSIXPBA,
2612 TSI721_MSIXPBA_OFFSET);
2613 pci_write_config_dword(pdev, TSI721_PCIECFG_EPCTL, 0);
2614 /* End of FIXUP */
2615
2616 tsi721_disable_ints(priv);
2617
2618 tsi721_init_pc2sr_mapping(priv);
2619 tsi721_init_sr2pc_mapping(priv);
2620
2621 if (tsi721_bdma_maint_init(priv)) {
2622 dev_err(&pdev->dev, "BDMA initialization failed, aborting\n");
2623 err = -ENOMEM;
2624 goto err_unmap_bars;
2625 }
2626
2627 err = tsi721_doorbell_init(priv);
2628 if (err)
2629 goto err_free_bdma;
2630
2631 tsi721_port_write_init(priv);
2632
2633 err = tsi721_messages_init(priv);
2634 if (err)
2635 goto err_free_consistent;
2636
2637 err = tsi721_setup_mport(priv);
2638 if (err)
2639 goto err_free_consistent;
2640
2641 return 0;
2642
2643 err_free_consistent:
2644 tsi721_doorbell_free(priv);
2645 err_free_bdma:
2646 tsi721_bdma_maint_free(priv);
2647 err_unmap_bars:
2648 if (priv->regs)
2649 iounmap(priv->regs);
2650 if (priv->odb_base)
2651 iounmap(priv->odb_base);
2652 err_free_res:
2653 pci_release_regions(pdev);
2654 pci_clear_master(pdev);
2655 err_disable_pdev:
2656 pci_disable_device(pdev);
2657 err_clean:
2658 kfree(priv);
2659 err_exit:
2660 return err;
2661 }
2662
2663 static const struct pci_device_id tsi721_pci_tbl[] = {
2664 { PCI_DEVICE(PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_TSI721) },
2665 { 0, } /* terminate list */
2666 };
2667
2668 MODULE_DEVICE_TABLE(pci, tsi721_pci_tbl);
2669
2670 static struct pci_driver tsi721_driver = {
2671 .name = "tsi721",
2672 .id_table = tsi721_pci_tbl,
2673 .probe = tsi721_probe,
2674 };
2675
2676 static int __init tsi721_init(void)
2677 {
2678 return pci_register_driver(&tsi721_driver);
2679 }
2680
2681 device_initcall(tsi721_init);
2682
2683 MODULE_DESCRIPTION("IDT Tsi721 PCIExpress-to-SRIO bridge driver");
2684 MODULE_AUTHOR("Integrated Device Technology, Inc.");
2685 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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