projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge remote-tracking branch 'tty/tty-next'
[deliverable/linux.git] / drivers / tty / serial / 8250 / 8250_dw.c
1 /*
2 * Synopsys DesignWare 8250 driver.
3 *
4 * Copyright 2011 Picochip, Jamie Iles.
5 * Copyright 2013 Intel Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
13 * LCR is written whilst busy. If it is, then a busy detect interrupt is
14 * raised, the LCR needs to be rewritten and the uart status register read.
15 */
16 #include <linux/device.h>
17 #include <linux/io.h>
18 #include <linux/module.h>
19 #include <linux/serial_8250.h>
20 #include <linux/serial_reg.h>
21 #include <linux/of.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_platform.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/acpi.h>
27 #include <linux/clk.h>
28 #include <linux/reset.h>
29 #include <linux/pm_runtime.h>
30
31 #include <asm/byteorder.h>
32
33 #include "8250.h"
34
35 /* Offsets for the DesignWare specific registers */
36 #define DW_UART_USR 0x1f /* UART Status Register */
37 #define DW_UART_CPR 0xf4 /* Component Parameter Register */
38 #define DW_UART_UCV 0xf8 /* UART Component Version */
39
40 /* Component Parameter Register bits */
41 #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0)
42 #define DW_UART_CPR_AFCE_MODE (1 << 4)
43 #define DW_UART_CPR_THRE_MODE (1 << 5)
44 #define DW_UART_CPR_SIR_MODE (1 << 6)
45 #define DW_UART_CPR_SIR_LP_MODE (1 << 7)
46 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
47 #define DW_UART_CPR_FIFO_ACCESS (1 << 9)
48 #define DW_UART_CPR_FIFO_STAT (1 << 10)
49 #define DW_UART_CPR_SHADOW (1 << 11)
50 #define DW_UART_CPR_ENCODED_PARMS (1 << 12)
51 #define DW_UART_CPR_DMA_EXTRA (1 << 13)
52 #define DW_UART_CPR_FIFO_MODE (0xff << 16)
53 /* Helper for fifo size calculation */
54 #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16)
55
56
57 struct dw8250_data {
58 u8 usr_reg;
59 int line;
60 int msr_mask_on;
61 int msr_mask_off;
62 struct clk *clk;
63 struct clk *pclk;
64 struct reset_control *rst;
65 struct uart_8250_dma dma;
66
67 unsigned int skip_autocfg:1;
68 unsigned int uart_16550_compatible:1;
69 };
70
71 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
72 {
73 struct dw8250_data *d = p->private_data;
74
75 /* Override any modem control signals if needed */
76 if (offset == UART_MSR) {
77 value |= d->msr_mask_on;
78 value &= ~d->msr_mask_off;
79 }
80
81 return value;
82 }
83
84 static void dw8250_force_idle(struct uart_port *p)
85 {
86 struct uart_8250_port *up = up_to_u8250p(p);
87
88 serial8250_clear_and_reinit_fifos(up);
89 (void)p->serial_in(p, UART_RX);
90 }
91
92 static void dw8250_check_lcr(struct uart_port *p, int value)
93 {
94 void __iomem *offset = p->membase + (UART_LCR << p->regshift);
95 int tries = 1000;
96
97 /* Make sure LCR write wasn't ignored */
98 while (tries--) {
99 unsigned int lcr = p->serial_in(p, UART_LCR);
100
101 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
102 return;
103
104 dw8250_force_idle(p);
105
106 #ifdef CONFIG_64BIT
107 if (p->type == PORT_OCTEON)
108 __raw_writeq(value & 0xff, offset);
109 else
110 #endif
111 if (p->iotype == UPIO_MEM32)
112 writel(value, offset);
113 else if (p->iotype == UPIO_MEM32BE)
114 iowrite32be(value, offset);
115 else
116 writeb(value, offset);
117 }
118 /*
119 * FIXME: this deadlocks if port->lock is already held
120 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
121 */
122 }
123
124 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
125 {
126 struct dw8250_data *d = p->private_data;
127
128 writeb(value, p->membase + (offset << p->regshift));
129
130 if (offset == UART_LCR && !d->uart_16550_compatible)
131 dw8250_check_lcr(p, value);
132 }
133
134 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
135 {
136 unsigned int value = readb(p->membase + (offset << p->regshift));
137
138 return dw8250_modify_msr(p, offset, value);
139 }
140
141 #ifdef CONFIG_64BIT
142 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
143 {
144 unsigned int value;
145
146 value = (u8)__raw_readq(p->membase + (offset << p->regshift));
147
148 return dw8250_modify_msr(p, offset, value);
149 }
150
151 static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
152 {
153 struct dw8250_data *d = p->private_data;
154
155 value &= 0xff;
156 __raw_writeq(value, p->membase + (offset << p->regshift));
157 /* Read back to ensure register write ordering. */
158 __raw_readq(p->membase + (UART_LCR << p->regshift));
159
160 if (offset == UART_LCR && !d->uart_16550_compatible)
161 dw8250_check_lcr(p, value);
162 }
163 #endif /* CONFIG_64BIT */
164
165 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
166 {
167 struct dw8250_data *d = p->private_data;
168
169 writel(value, p->membase + (offset << p->regshift));
170
171 if (offset == UART_LCR && !d->uart_16550_compatible)
172 dw8250_check_lcr(p, value);
173 }
174
175 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
176 {
177 unsigned int value = readl(p->membase + (offset << p->regshift));
178
179 return dw8250_modify_msr(p, offset, value);
180 }
181
182 static void dw8250_serial_out32be(struct uart_port *p, int offset, int value)
183 {
184 struct dw8250_data *d = p->private_data;
185
186 iowrite32be(value, p->membase + (offset << p->regshift));
187
188 if (offset == UART_LCR && !d->uart_16550_compatible)
189 dw8250_check_lcr(p, value);
190 }
191
192 static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset)
193 {
194 unsigned int value = ioread32be(p->membase + (offset << p->regshift));
195
196 return dw8250_modify_msr(p, offset, value);
197 }
198
199
200 static int dw8250_handle_irq(struct uart_port *p)
201 {
202 struct dw8250_data *d = p->private_data;
203 unsigned int iir = p->serial_in(p, UART_IIR);
204
205 if (serial8250_handle_irq(p, iir))
206 return 1;
207
208 if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
209 /* Clear the USR */
210 (void)p->serial_in(p, d->usr_reg);
211
212 return 1;
213 }
214
215 return 0;
216 }
217
218 static void
219 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
220 {
221 if (!state)
222 pm_runtime_get_sync(port->dev);
223
224 serial8250_do_pm(port, state, old);
225
226 if (state)
227 pm_runtime_put_sync_suspend(port->dev);
228 }
229
230 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
231 struct ktermios *old)
232 {
233 unsigned int baud = tty_termios_baud_rate(termios);
234 struct dw8250_data *d = p->private_data;
235 unsigned int rate;
236 int ret;
237
238 if (IS_ERR(d->clk) || !old)
239 goto out;
240
241 clk_disable_unprepare(d->clk);
242 rate = clk_round_rate(d->clk, baud * 16);
243 ret = clk_set_rate(d->clk, rate);
244 clk_prepare_enable(d->clk);
245
246 if (!ret)
247 p->uartclk = rate;
248
249 p->status &= ~UPSTAT_AUTOCTS;
250 if (termios->c_cflag & CRTSCTS)
251 p->status |= UPSTAT_AUTOCTS;
252
253 out:
254 serial8250_do_set_termios(p, termios, old);
255 }
256
257 /*
258 * dw8250_fallback_dma_filter will prevent the UART from getting just any free
259 * channel on platforms that have DMA engines, but don't have any channels
260 * assigned to the UART.
261 *
262 * REVISIT: This is a work around for limitation in the DMA Engine API. Once the
263 * core problem is fixed, this function is no longer needed.
264 */
265 static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param)
266 {
267 return false;
268 }
269
270 static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
271 {
272 return param == chan->device->dev->parent;
273 }
274
275 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
276 {
277 if (p->dev->of_node) {
278 struct device_node *np = p->dev->of_node;
279 int id;
280
281 /* get index of serial line, if found in DT aliases */
282 id = of_alias_get_id(np, "serial");
283 if (id >= 0)
284 p->line = id;
285 #ifdef CONFIG_64BIT
286 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
287 p->serial_in = dw8250_serial_inq;
288 p->serial_out = dw8250_serial_outq;
289 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
290 p->type = PORT_OCTEON;
291 data->usr_reg = 0x27;
292 data->skip_autocfg = true;
293 }
294 #endif
295 if (of_device_is_big_endian(p->dev->of_node)) {
296 p->iotype = UPIO_MEM32BE;
297 p->serial_in = dw8250_serial_in32be;
298 p->serial_out = dw8250_serial_out32be;
299 }
300 } else if (has_acpi_companion(p->dev)) {
301 const struct acpi_device_id *id;
302
303 id = acpi_match_device(p->dev->driver->acpi_match_table,
304 p->dev);
305 if (id && !strcmp(id->id, "APMC0D08")) {
306 p->iotype = UPIO_MEM32;
307 p->regshift = 2;
308 p->serial_in = dw8250_serial_in32;
309 data->uart_16550_compatible = true;
310 }
311 p->set_termios = dw8250_set_termios;
312 }
313
314 /* Platforms with iDMA */
315 if (platform_get_resource_byname(to_platform_device(p->dev),
316 IORESOURCE_MEM, "lpss_priv")) {
317 p->set_termios = dw8250_set_termios;
318 data->dma.rx_param = p->dev->parent;
319 data->dma.tx_param = p->dev->parent;
320 data->dma.fn = dw8250_idma_filter;
321 }
322 }
323
324 static void dw8250_setup_port(struct uart_port *p)
325 {
326 struct uart_8250_port *up = up_to_u8250p(p);
327 u32 reg;
328
329 /*
330 * If the Component Version Register returns zero, we know that
331 * ADDITIONAL_FEATURES are not enabled. No need to go any further.
332 */
333 if (p->iotype == UPIO_MEM32BE)
334 reg = ioread32be(p->membase + DW_UART_UCV);
335 else
336 reg = readl(p->membase + DW_UART_UCV);
337 if (!reg)
338 return;
339
340 dev_dbg(p->dev, "Designware UART version %c.%c%c\n",
341 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
342
343 if (p->iotype == UPIO_MEM32BE)
344 reg = ioread32be(p->membase + DW_UART_CPR);
345 else
346 reg = readl(p->membase + DW_UART_CPR);
347 if (!reg)
348 return;
349
350 /* Select the type based on fifo */
351 if (reg & DW_UART_CPR_FIFO_MODE) {
352 p->type = PORT_16550A;
353 p->flags |= UPF_FIXED_TYPE;
354 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
355 up->capabilities = UART_CAP_FIFO;
356 }
357
358 if (reg & DW_UART_CPR_AFCE_MODE)
359 up->capabilities |= UART_CAP_AFE;
360 }
361
362 static int dw8250_probe(struct platform_device *pdev)
363 {
364 struct uart_8250_port uart = {};
365 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
366 int irq = platform_get_irq(pdev, 0);
367 struct uart_port *p = &uart.port;
368 struct device *dev = &pdev->dev;
369 struct dw8250_data *data;
370 int err;
371 u32 val;
372
373 if (!regs) {
374 dev_err(dev, "no registers defined\n");
375 return -EINVAL;
376 }
377
378 if (irq < 0) {
379 if (irq != -EPROBE_DEFER)
380 dev_err(dev, "cannot get irq\n");
381 return irq;
382 }
383
384 spin_lock_init(&p->lock);
385 p->mapbase = regs->start;
386 p->irq = irq;
387 p->handle_irq = dw8250_handle_irq;
388 p->pm = dw8250_do_pm;
389 p->type = PORT_8250;
390 p->flags = UPF_SHARE_IRQ | UPF_FIXED_PORT;
391 p->dev = dev;
392 p->iotype = UPIO_MEM;
393 p->serial_in = dw8250_serial_in;
394 p->serial_out = dw8250_serial_out;
395
396 p->membase = devm_ioremap(dev, regs->start, resource_size(regs));
397 if (!p->membase)
398 return -ENOMEM;
399
400 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
401 if (!data)
402 return -ENOMEM;
403
404 data->dma.fn = dw8250_fallback_dma_filter;
405 data->usr_reg = DW_UART_USR;
406 p->private_data = data;
407
408 data->uart_16550_compatible = device_property_read_bool(dev,
409 "snps,uart-16550-compatible");
410
411 err = device_property_read_u32(dev, "reg-shift", &val);
412 if (!err)
413 p->regshift = val;
414
415 err = device_property_read_u32(dev, "reg-io-width", &val);
416 if (!err && val == 4) {
417 p->iotype = UPIO_MEM32;
418 p->serial_in = dw8250_serial_in32;
419 p->serial_out = dw8250_serial_out32;
420 }
421
422 if (device_property_read_bool(dev, "dcd-override")) {
423 /* Always report DCD as active */
424 data->msr_mask_on |= UART_MSR_DCD;
425 data->msr_mask_off |= UART_MSR_DDCD;
426 }
427
428 if (device_property_read_bool(dev, "dsr-override")) {
429 /* Always report DSR as active */
430 data->msr_mask_on |= UART_MSR_DSR;
431 data->msr_mask_off |= UART_MSR_DDSR;
432 }
433
434 if (device_property_read_bool(dev, "cts-override")) {
435 /* Always report CTS as active */
436 data->msr_mask_on |= UART_MSR_CTS;
437 data->msr_mask_off |= UART_MSR_DCTS;
438 }
439
440 if (device_property_read_bool(dev, "ri-override")) {
441 /* Always report Ring indicator as inactive */
442 data->msr_mask_off |= UART_MSR_RI;
443 data->msr_mask_off |= UART_MSR_TERI;
444 }
445
446 /* Always ask for fixed clock rate from a property. */
447 device_property_read_u32(dev, "clock-frequency", &p->uartclk);
448
449 /* If there is separate baudclk, get the rate from it. */
450 data->clk = devm_clk_get(dev, "baudclk");
451 if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER)
452 data->clk = devm_clk_get(dev, NULL);
453 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER)
454 return -EPROBE_DEFER;
455 if (!IS_ERR_OR_NULL(data->clk)) {
456 err = clk_prepare_enable(data->clk);
457 if (err)
458 dev_warn(dev, "could not enable optional baudclk: %d\n",
459 err);
460 else
461 p->uartclk = clk_get_rate(data->clk);
462 }
463
464 /* If no clock rate is defined, fail. */
465 if (!p->uartclk) {
466 dev_err(dev, "clock rate not defined\n");
467 return -EINVAL;
468 }
469
470 data->pclk = devm_clk_get(dev, "apb_pclk");
471 if (IS_ERR(data->pclk) && PTR_ERR(data->pclk) == -EPROBE_DEFER) {
472 err = -EPROBE_DEFER;
473 goto err_clk;
474 }
475 if (!IS_ERR(data->pclk)) {
476 err = clk_prepare_enable(data->pclk);
477 if (err) {
478 dev_err(dev, "could not enable apb_pclk\n");
479 goto err_clk;
480 }
481 }
482
483 data->rst = devm_reset_control_get_optional(dev, NULL);
484 if (IS_ERR(data->rst) && PTR_ERR(data->rst) == -EPROBE_DEFER) {
485 err = -EPROBE_DEFER;
486 goto err_pclk;
487 }
488 if (!IS_ERR(data->rst))
489 reset_control_deassert(data->rst);
490
491 dw8250_quirks(p, data);
492
493 /* If the Busy Functionality is not implemented, don't handle it */
494 if (data->uart_16550_compatible)
495 p->handle_irq = NULL;
496
497 if (!data->skip_autocfg)
498 dw8250_setup_port(p);
499
500 /* If we have a valid fifosize, try hooking up DMA */
501 if (p->fifosize) {
502 data->dma.rxconf.src_maxburst = p->fifosize / 4;
503 data->dma.txconf.dst_maxburst = p->fifosize / 4;
504 uart.dma = &data->dma;
505 }
506
507 data->line = serial8250_register_8250_port(&uart);
508 if (data->line < 0) {
509 err = data->line;
510 goto err_reset;
511 }
512
513 platform_set_drvdata(pdev, data);
514
515 pm_runtime_set_active(dev);
516 pm_runtime_enable(dev);
517
518 return 0;
519
520 err_reset:
521 if (!IS_ERR(data->rst))
522 reset_control_assert(data->rst);
523
524 err_pclk:
525 if (!IS_ERR(data->pclk))
526 clk_disable_unprepare(data->pclk);
527
528 err_clk:
529 if (!IS_ERR(data->clk))
530 clk_disable_unprepare(data->clk);
531
532 return err;
533 }
534
535 static int dw8250_remove(struct platform_device *pdev)
536 {
537 struct dw8250_data *data = platform_get_drvdata(pdev);
538
539 pm_runtime_get_sync(&pdev->dev);
540
541 serial8250_unregister_port(data->line);
542
543 if (!IS_ERR(data->rst))
544 reset_control_assert(data->rst);
545
546 if (!IS_ERR(data->pclk))
547 clk_disable_unprepare(data->pclk);
548
549 if (!IS_ERR(data->clk))
550 clk_disable_unprepare(data->clk);
551
552 pm_runtime_disable(&pdev->dev);
553 pm_runtime_put_noidle(&pdev->dev);
554
555 return 0;
556 }
557
558 #ifdef CONFIG_PM_SLEEP
559 static int dw8250_suspend(struct device *dev)
560 {
561 struct dw8250_data *data = dev_get_drvdata(dev);
562
563 serial8250_suspend_port(data->line);
564
565 return 0;
566 }
567
568 static int dw8250_resume(struct device *dev)
569 {
570 struct dw8250_data *data = dev_get_drvdata(dev);
571
572 serial8250_resume_port(data->line);
573
574 return 0;
575 }
576 #endif /* CONFIG_PM_SLEEP */
577
578 #ifdef CONFIG_PM
579 static int dw8250_runtime_suspend(struct device *dev)
580 {
581 struct dw8250_data *data = dev_get_drvdata(dev);
582
583 if (!IS_ERR(data->clk))
584 clk_disable_unprepare(data->clk);
585
586 if (!IS_ERR(data->pclk))
587 clk_disable_unprepare(data->pclk);
588
589 return 0;
590 }
591
592 static int dw8250_runtime_resume(struct device *dev)
593 {
594 struct dw8250_data *data = dev_get_drvdata(dev);
595
596 if (!IS_ERR(data->pclk))
597 clk_prepare_enable(data->pclk);
598
599 if (!IS_ERR(data->clk))
600 clk_prepare_enable(data->clk);
601
602 return 0;
603 }
604 #endif
605
606 static const struct dev_pm_ops dw8250_pm_ops = {
607 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
608 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
609 };
610
611 static const struct of_device_id dw8250_of_match[] = {
612 { .compatible = "snps,dw-apb-uart" },
613 { .compatible = "cavium,octeon-3860-uart" },
614 { /* Sentinel */ }
615 };
616 MODULE_DEVICE_TABLE(of, dw8250_of_match);
617
618 static const struct acpi_device_id dw8250_acpi_match[] = {
619 { "INT33C4", 0 },
620 { "INT33C5", 0 },
621 { "INT3434", 0 },
622 { "INT3435", 0 },
623 { "80860F0A", 0 },
624 { "8086228A", 0 },
625 { "APMC0D08", 0},
626 { "AMD0020", 0 },
627 { "AMDI0020", 0 },
628 { "HISI0031", 0 },
629 { },
630 };
631 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
632
633 static struct platform_driver dw8250_platform_driver = {
634 .driver = {
635 .name = "dw-apb-uart",
636 .pm = &dw8250_pm_ops,
637 .of_match_table = dw8250_of_match,
638 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
639 },
640 .probe = dw8250_probe,
641 .remove = dw8250_remove,
642 };
643
644 module_platform_driver(dw8250_platform_driver);
645
646 MODULE_AUTHOR("Jamie Iles");
647 MODULE_LICENSE("GPL");
648 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
649 MODULE_ALIAS("platform:dw-apb-uart");
Linux kernel - Deliverables
This page took 0.051694 seconds and 5 git commands to generate.