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Merge remote-tracking branch 'usb-gadget/next'
[deliverable/linux.git] / drivers / usb / dwc3 / core.c
1 /**
2 * core.c - DesignWare USB3 DRD Controller Core file
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include <linux/version.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/io.h>
32 #include <linux/list.h>
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/of.h>
36 #include <linux/acpi.h>
37 #include <linux/pinctrl/consumer.h>
38
39 #include <linux/usb/ch9.h>
40 #include <linux/usb/gadget.h>
41 #include <linux/usb/of.h>
42 #include <linux/usb/otg.h>
43
44 #include "core.h"
45 #include "gadget.h"
46 #include "io.h"
47
48 #include "debug.h"
49
50 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
51
52 /**
53 * dwc3_get_dr_mode - Validates and sets dr_mode
54 * @dwc: pointer to our context structure
55 */
56 static int dwc3_get_dr_mode(struct dwc3 *dwc)
57 {
58 enum usb_dr_mode mode;
59 struct device *dev = dwc->dev;
60 unsigned int hw_mode;
61
62 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
63 dwc->dr_mode = USB_DR_MODE_OTG;
64
65 mode = dwc->dr_mode;
66 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
67
68 switch (hw_mode) {
69 case DWC3_GHWPARAMS0_MODE_GADGET:
70 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
71 dev_err(dev,
72 "Controller does not support host mode.\n");
73 return -EINVAL;
74 }
75 mode = USB_DR_MODE_PERIPHERAL;
76 break;
77 case DWC3_GHWPARAMS0_MODE_HOST:
78 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
79 dev_err(dev,
80 "Controller does not support device mode.\n");
81 return -EINVAL;
82 }
83 mode = USB_DR_MODE_HOST;
84 break;
85 default:
86 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
87 mode = USB_DR_MODE_HOST;
88 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
89 mode = USB_DR_MODE_PERIPHERAL;
90 }
91
92 if (mode != dwc->dr_mode) {
93 dev_warn(dev,
94 "Configuration mismatch. dr_mode forced to %s\n",
95 mode == USB_DR_MODE_HOST ? "host" : "gadget");
96
97 dwc->dr_mode = mode;
98 }
99
100 return 0;
101 }
102
103 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
104 {
105 u32 reg;
106
107 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
108 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
109 reg |= DWC3_GCTL_PRTCAPDIR(mode);
110 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
111 }
112
113 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
114 {
115 struct dwc3 *dwc = dep->dwc;
116 u32 reg;
117
118 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
119 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
120 DWC3_GDBGFIFOSPACE_TYPE(type));
121
122 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
123
124 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
125 }
126
127 /**
128 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
129 * @dwc: pointer to our context structure
130 */
131 static int dwc3_core_soft_reset(struct dwc3 *dwc)
132 {
133 u32 reg;
134 int retries = 1000;
135 int ret;
136
137 usb_phy_init(dwc->usb2_phy);
138 usb_phy_init(dwc->usb3_phy);
139 ret = phy_init(dwc->usb2_generic_phy);
140 if (ret < 0)
141 return ret;
142
143 ret = phy_init(dwc->usb3_generic_phy);
144 if (ret < 0) {
145 phy_exit(dwc->usb2_generic_phy);
146 return ret;
147 }
148
149 /*
150 * We're resetting only the device side because, if we're in host mode,
151 * XHCI driver will reset the host block. If dwc3 was configured for
152 * host-only mode, then we can return early.
153 */
154 if (dwc->dr_mode == USB_DR_MODE_HOST)
155 return 0;
156
157 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
158 reg |= DWC3_DCTL_CSFTRST;
159 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
160
161 do {
162 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
163 if (!(reg & DWC3_DCTL_CSFTRST))
164 return 0;
165
166 udelay(1);
167 } while (--retries);
168
169 return -ETIMEDOUT;
170 }
171
172 /**
173 * dwc3_soft_reset - Issue soft reset
174 * @dwc: Pointer to our controller context structure
175 */
176 static int dwc3_soft_reset(struct dwc3 *dwc)
177 {
178 unsigned long timeout;
179 u32 reg;
180
181 timeout = jiffies + msecs_to_jiffies(500);
182 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
183 do {
184 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
185 if (!(reg & DWC3_DCTL_CSFTRST))
186 break;
187
188 if (time_after(jiffies, timeout)) {
189 dev_err(dwc->dev, "Reset Timed Out\n");
190 return -ETIMEDOUT;
191 }
192
193 cpu_relax();
194 } while (true);
195
196 return 0;
197 }
198
199 /*
200 * dwc3_frame_length_adjustment - Adjusts frame length if required
201 * @dwc3: Pointer to our controller context structure
202 */
203 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
204 {
205 u32 reg;
206 u32 dft;
207
208 if (dwc->revision < DWC3_REVISION_250A)
209 return;
210
211 if (dwc->fladj == 0)
212 return;
213
214 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
215 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
216 if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
217 "request value same as default, ignoring\n")) {
218 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
219 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
220 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
221 }
222 }
223
224 /**
225 * dwc3_free_one_event_buffer - Frees one event buffer
226 * @dwc: Pointer to our controller context structure
227 * @evt: Pointer to event buffer to be freed
228 */
229 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
230 struct dwc3_event_buffer *evt)
231 {
232 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
233 }
234
235 /**
236 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
237 * @dwc: Pointer to our controller context structure
238 * @length: size of the event buffer
239 *
240 * Returns a pointer to the allocated event buffer structure on success
241 * otherwise ERR_PTR(errno).
242 */
243 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
244 unsigned length)
245 {
246 struct dwc3_event_buffer *evt;
247
248 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
249 if (!evt)
250 return ERR_PTR(-ENOMEM);
251
252 evt->dwc = dwc;
253 evt->length = length;
254 evt->buf = dma_alloc_coherent(dwc->dev, length,
255 &evt->dma, GFP_KERNEL);
256 if (!evt->buf)
257 return ERR_PTR(-ENOMEM);
258
259 return evt;
260 }
261
262 /**
263 * dwc3_free_event_buffers - frees all allocated event buffers
264 * @dwc: Pointer to our controller context structure
265 */
266 static void dwc3_free_event_buffers(struct dwc3 *dwc)
267 {
268 struct dwc3_event_buffer *evt;
269
270 evt = dwc->ev_buf;
271 if (evt)
272 dwc3_free_one_event_buffer(dwc, evt);
273 }
274
275 /**
276 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
277 * @dwc: pointer to our controller context structure
278 * @length: size of event buffer
279 *
280 * Returns 0 on success otherwise negative errno. In the error case, dwc
281 * may contain some buffers allocated but not all which were requested.
282 */
283 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
284 {
285 struct dwc3_event_buffer *evt;
286
287 evt = dwc3_alloc_one_event_buffer(dwc, length);
288 if (IS_ERR(evt)) {
289 dev_err(dwc->dev, "can't allocate event buffer\n");
290 return PTR_ERR(evt);
291 }
292 dwc->ev_buf = evt;
293
294 return 0;
295 }
296
297 /**
298 * dwc3_event_buffers_setup - setup our allocated event buffers
299 * @dwc: pointer to our controller context structure
300 *
301 * Returns 0 on success otherwise negative errno.
302 */
303 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
304 {
305 struct dwc3_event_buffer *evt;
306
307 evt = dwc->ev_buf;
308 dwc3_trace(trace_dwc3_core,
309 "Event buf %p dma %08llx length %d\n",
310 evt->buf, (unsigned long long) evt->dma,
311 evt->length);
312
313 evt->lpos = 0;
314
315 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
316 lower_32_bits(evt->dma));
317 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
318 upper_32_bits(evt->dma));
319 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
320 DWC3_GEVNTSIZ_SIZE(evt->length));
321 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
322
323 return 0;
324 }
325
326 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
327 {
328 struct dwc3_event_buffer *evt;
329
330 evt = dwc->ev_buf;
331
332 evt->lpos = 0;
333
334 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
335 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
336 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
337 | DWC3_GEVNTSIZ_SIZE(0));
338 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
339 }
340
341 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
342 {
343 if (!dwc->has_hibernation)
344 return 0;
345
346 if (!dwc->nr_scratch)
347 return 0;
348
349 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
350 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
351 if (!dwc->scratchbuf)
352 return -ENOMEM;
353
354 return 0;
355 }
356
357 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
358 {
359 dma_addr_t scratch_addr;
360 u32 param;
361 int ret;
362
363 if (!dwc->has_hibernation)
364 return 0;
365
366 if (!dwc->nr_scratch)
367 return 0;
368
369 /* should never fall here */
370 if (!WARN_ON(dwc->scratchbuf))
371 return 0;
372
373 scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
374 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
375 DMA_BIDIRECTIONAL);
376 if (dma_mapping_error(dwc->dev, scratch_addr)) {
377 dev_err(dwc->dev, "failed to map scratch buffer\n");
378 ret = -EFAULT;
379 goto err0;
380 }
381
382 dwc->scratch_addr = scratch_addr;
383
384 param = lower_32_bits(scratch_addr);
385
386 ret = dwc3_send_gadget_generic_command(dwc,
387 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
388 if (ret < 0)
389 goto err1;
390
391 param = upper_32_bits(scratch_addr);
392
393 ret = dwc3_send_gadget_generic_command(dwc,
394 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
395 if (ret < 0)
396 goto err1;
397
398 return 0;
399
400 err1:
401 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
402 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
403
404 err0:
405 return ret;
406 }
407
408 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
409 {
410 if (!dwc->has_hibernation)
411 return;
412
413 if (!dwc->nr_scratch)
414 return;
415
416 /* should never fall here */
417 if (!WARN_ON(dwc->scratchbuf))
418 return;
419
420 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
421 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
422 kfree(dwc->scratchbuf);
423 }
424
425 static void dwc3_core_num_eps(struct dwc3 *dwc)
426 {
427 struct dwc3_hwparams *parms = &dwc->hwparams;
428
429 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
430 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
431
432 dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
433 dwc->num_in_eps, dwc->num_out_eps);
434 }
435
436 static void dwc3_cache_hwparams(struct dwc3 *dwc)
437 {
438 struct dwc3_hwparams *parms = &dwc->hwparams;
439
440 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
441 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
442 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
443 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
444 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
445 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
446 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
447 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
448 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
449 }
450
451 /**
452 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
453 * @dwc: Pointer to our controller context structure
454 *
455 * Returns 0 on success. The USB PHY interfaces are configured but not
456 * initialized. The PHY interfaces and the PHYs get initialized together with
457 * the core in dwc3_core_init.
458 */
459 static int dwc3_phy_setup(struct dwc3 *dwc)
460 {
461 u32 reg;
462 int ret;
463
464 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
465
466 /*
467 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
468 * to '0' during coreConsultant configuration. So default value
469 * will be '0' when the core is reset. Application needs to set it
470 * to '1' after the core initialization is completed.
471 */
472 if (dwc->revision > DWC3_REVISION_194A)
473 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
474
475 if (dwc->u2ss_inp3_quirk)
476 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
477
478 if (dwc->dis_rxdet_inp3_quirk)
479 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
480
481 if (dwc->req_p1p2p3_quirk)
482 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
483
484 if (dwc->del_p1p2p3_quirk)
485 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
486
487 if (dwc->del_phy_power_chg_quirk)
488 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
489
490 if (dwc->lfps_filter_quirk)
491 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
492
493 if (dwc->rx_detect_poll_quirk)
494 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
495
496 if (dwc->tx_de_emphasis_quirk)
497 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
498
499 if (dwc->dis_u3_susphy_quirk)
500 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
501
502 if (dwc->dis_del_phy_power_chg_quirk)
503 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
504
505 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
506
507 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
508
509 /* Select the HS PHY interface */
510 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
511 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
512 if (dwc->hsphy_interface &&
513 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
514 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
515 break;
516 } else if (dwc->hsphy_interface &&
517 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
518 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
519 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
520 } else {
521 /* Relying on default value. */
522 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
523 break;
524 }
525 /* FALLTHROUGH */
526 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
527 /* Making sure the interface and PHY are operational */
528 ret = dwc3_soft_reset(dwc);
529 if (ret)
530 return ret;
531
532 udelay(1);
533
534 ret = dwc3_ulpi_init(dwc);
535 if (ret)
536 return ret;
537 /* FALLTHROUGH */
538 default:
539 break;
540 }
541
542 switch (dwc->hsphy_mode) {
543 case USBPHY_INTERFACE_MODE_UTMI:
544 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
545 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
546 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
547 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
548 break;
549 case USBPHY_INTERFACE_MODE_UTMIW:
550 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
551 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
552 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
553 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
554 break;
555 default:
556 break;
557 }
558
559 /*
560 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
561 * '0' during coreConsultant configuration. So default value will
562 * be '0' when the core is reset. Application needs to set it to
563 * '1' after the core initialization is completed.
564 */
565 if (dwc->revision > DWC3_REVISION_194A)
566 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
567
568 if (dwc->dis_u2_susphy_quirk)
569 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
570
571 if (dwc->dis_enblslpm_quirk)
572 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
573
574 if (dwc->dis_u2_freeclk_exists_quirk)
575 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
576
577 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
578
579 return 0;
580 }
581
582 static void dwc3_core_exit(struct dwc3 *dwc)
583 {
584 dwc3_event_buffers_cleanup(dwc);
585
586 usb_phy_shutdown(dwc->usb2_phy);
587 usb_phy_shutdown(dwc->usb3_phy);
588 phy_exit(dwc->usb2_generic_phy);
589 phy_exit(dwc->usb3_generic_phy);
590
591 usb_phy_set_suspend(dwc->usb2_phy, 1);
592 usb_phy_set_suspend(dwc->usb3_phy, 1);
593 phy_power_off(dwc->usb2_generic_phy);
594 phy_power_off(dwc->usb3_generic_phy);
595 }
596
597 /**
598 * dwc3_core_init - Low-level initialization of DWC3 Core
599 * @dwc: Pointer to our controller context structure
600 *
601 * Returns 0 on success otherwise negative errno.
602 */
603 static int dwc3_core_init(struct dwc3 *dwc)
604 {
605 u32 hwparams4 = dwc->hwparams.hwparams4;
606 u32 reg;
607 int ret;
608
609 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
610 /* This should read as U3 followed by revision number */
611 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
612 /* Detected DWC_usb3 IP */
613 dwc->revision = reg;
614 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
615 /* Detected DWC_usb31 IP */
616 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
617 dwc->revision |= DWC3_REVISION_IS_DWC31;
618 } else {
619 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
620 ret = -ENODEV;
621 goto err0;
622 }
623
624 /*
625 * Write Linux Version Code to our GUID register so it's easy to figure
626 * out which kernel version a bug was found.
627 */
628 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
629
630 /* Handle USB2.0-only core configuration */
631 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
632 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
633 if (dwc->maximum_speed == USB_SPEED_SUPER)
634 dwc->maximum_speed = USB_SPEED_HIGH;
635 }
636
637 /* issue device SoftReset too */
638 ret = dwc3_soft_reset(dwc);
639 if (ret)
640 goto err0;
641
642 ret = dwc3_core_soft_reset(dwc);
643 if (ret)
644 goto err0;
645
646 ret = dwc3_phy_setup(dwc);
647 if (ret)
648 goto err0;
649
650 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
651 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
652
653 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
654 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
655 /**
656 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
657 * issue which would cause xHCI compliance tests to fail.
658 *
659 * Because of that we cannot enable clock gating on such
660 * configurations.
661 *
662 * Refers to:
663 *
664 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
665 * SOF/ITP Mode Used
666 */
667 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
668 dwc->dr_mode == USB_DR_MODE_OTG) &&
669 (dwc->revision >= DWC3_REVISION_210A &&
670 dwc->revision <= DWC3_REVISION_250A))
671 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
672 else
673 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
674 break;
675 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
676 /* enable hibernation here */
677 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
678
679 /*
680 * REVISIT Enabling this bit so that host-mode hibernation
681 * will work. Device-mode hibernation is not yet implemented.
682 */
683 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
684 break;
685 default:
686 dwc3_trace(trace_dwc3_core, "No power optimization available\n");
687 }
688
689 /* check if current dwc3 is on simulation board */
690 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
691 dwc3_trace(trace_dwc3_core,
692 "running on FPGA platform\n");
693 dwc->is_fpga = true;
694 }
695
696 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
697 "disable_scramble cannot be used on non-FPGA builds\n");
698
699 if (dwc->disable_scramble_quirk && dwc->is_fpga)
700 reg |= DWC3_GCTL_DISSCRAMBLE;
701 else
702 reg &= ~DWC3_GCTL_DISSCRAMBLE;
703
704 if (dwc->u2exit_lfps_quirk)
705 reg |= DWC3_GCTL_U2EXIT_LFPS;
706
707 /*
708 * WORKAROUND: DWC3 revisions <1.90a have a bug
709 * where the device can fail to connect at SuperSpeed
710 * and falls back to high-speed mode which causes
711 * the device to enter a Connect/Disconnect loop
712 */
713 if (dwc->revision < DWC3_REVISION_190A)
714 reg |= DWC3_GCTL_U2RSTECN;
715
716 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
717
718 dwc3_core_num_eps(dwc);
719
720 ret = dwc3_setup_scratch_buffers(dwc);
721 if (ret)
722 goto err1;
723
724 /* Adjust Frame Length */
725 dwc3_frame_length_adjustment(dwc);
726
727 usb_phy_set_suspend(dwc->usb2_phy, 0);
728 usb_phy_set_suspend(dwc->usb3_phy, 0);
729 ret = phy_power_on(dwc->usb2_generic_phy);
730 if (ret < 0)
731 goto err2;
732
733 ret = phy_power_on(dwc->usb3_generic_phy);
734 if (ret < 0)
735 goto err3;
736
737 ret = dwc3_event_buffers_setup(dwc);
738 if (ret) {
739 dev_err(dwc->dev, "failed to setup event buffers\n");
740 goto err4;
741 }
742
743 switch (dwc->dr_mode) {
744 case USB_DR_MODE_PERIPHERAL:
745 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
746 break;
747 case USB_DR_MODE_HOST:
748 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
749 break;
750 case USB_DR_MODE_OTG:
751 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
752 break;
753 default:
754 dev_warn(dwc->dev, "Unsupported mode %d\n", dwc->dr_mode);
755 break;
756 }
757
758 /*
759 * ENDXFER polling is available on version 3.10a and later of
760 * the DWC_usb3 controller. It is NOT available in the
761 * DWC_usb31 controller.
762 */
763 if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
764 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
765 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
766 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
767 }
768
769 return 0;
770
771 err4:
772 phy_power_off(dwc->usb2_generic_phy);
773
774 err3:
775 phy_power_off(dwc->usb3_generic_phy);
776
777 err2:
778 usb_phy_set_suspend(dwc->usb2_phy, 1);
779 usb_phy_set_suspend(dwc->usb3_phy, 1);
780 dwc3_core_exit(dwc);
781
782 err1:
783 usb_phy_shutdown(dwc->usb2_phy);
784 usb_phy_shutdown(dwc->usb3_phy);
785 phy_exit(dwc->usb2_generic_phy);
786 phy_exit(dwc->usb3_generic_phy);
787
788 err0:
789 return ret;
790 }
791
792 static int dwc3_core_get_phy(struct dwc3 *dwc)
793 {
794 struct device *dev = dwc->dev;
795 struct device_node *node = dev->of_node;
796 int ret;
797
798 if (node) {
799 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
800 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
801 } else {
802 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
803 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
804 }
805
806 if (IS_ERR(dwc->usb2_phy)) {
807 ret = PTR_ERR(dwc->usb2_phy);
808 if (ret == -ENXIO || ret == -ENODEV) {
809 dwc->usb2_phy = NULL;
810 } else if (ret == -EPROBE_DEFER) {
811 return ret;
812 } else {
813 dev_err(dev, "no usb2 phy configured\n");
814 return ret;
815 }
816 }
817
818 if (IS_ERR(dwc->usb3_phy)) {
819 ret = PTR_ERR(dwc->usb3_phy);
820 if (ret == -ENXIO || ret == -ENODEV) {
821 dwc->usb3_phy = NULL;
822 } else if (ret == -EPROBE_DEFER) {
823 return ret;
824 } else {
825 dev_err(dev, "no usb3 phy configured\n");
826 return ret;
827 }
828 }
829
830 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
831 if (IS_ERR(dwc->usb2_generic_phy)) {
832 ret = PTR_ERR(dwc->usb2_generic_phy);
833 if (ret == -ENOSYS || ret == -ENODEV) {
834 dwc->usb2_generic_phy = NULL;
835 } else if (ret == -EPROBE_DEFER) {
836 return ret;
837 } else {
838 dev_err(dev, "no usb2 phy configured\n");
839 return ret;
840 }
841 }
842
843 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
844 if (IS_ERR(dwc->usb3_generic_phy)) {
845 ret = PTR_ERR(dwc->usb3_generic_phy);
846 if (ret == -ENOSYS || ret == -ENODEV) {
847 dwc->usb3_generic_phy = NULL;
848 } else if (ret == -EPROBE_DEFER) {
849 return ret;
850 } else {
851 dev_err(dev, "no usb3 phy configured\n");
852 return ret;
853 }
854 }
855
856 return 0;
857 }
858
859 static int dwc3_core_init_mode(struct dwc3 *dwc)
860 {
861 struct device *dev = dwc->dev;
862 int ret;
863
864 switch (dwc->dr_mode) {
865 case USB_DR_MODE_PERIPHERAL:
866 ret = dwc3_gadget_init(dwc);
867 if (ret) {
868 if (ret != -EPROBE_DEFER)
869 dev_err(dev, "failed to initialize gadget\n");
870 return ret;
871 }
872 break;
873 case USB_DR_MODE_HOST:
874 ret = dwc3_host_init(dwc);
875 if (ret) {
876 if (ret != -EPROBE_DEFER)
877 dev_err(dev, "failed to initialize host\n");
878 return ret;
879 }
880 break;
881 case USB_DR_MODE_OTG:
882 ret = dwc3_host_init(dwc);
883 if (ret) {
884 if (ret != -EPROBE_DEFER)
885 dev_err(dev, "failed to initialize host\n");
886 return ret;
887 }
888
889 ret = dwc3_gadget_init(dwc);
890 if (ret) {
891 if (ret != -EPROBE_DEFER)
892 dev_err(dev, "failed to initialize gadget\n");
893 return ret;
894 }
895 break;
896 default:
897 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
898 return -EINVAL;
899 }
900
901 return 0;
902 }
903
904 static void dwc3_core_exit_mode(struct dwc3 *dwc)
905 {
906 switch (dwc->dr_mode) {
907 case USB_DR_MODE_PERIPHERAL:
908 dwc3_gadget_exit(dwc);
909 break;
910 case USB_DR_MODE_HOST:
911 dwc3_host_exit(dwc);
912 break;
913 case USB_DR_MODE_OTG:
914 dwc3_host_exit(dwc);
915 dwc3_gadget_exit(dwc);
916 break;
917 default:
918 /* do nothing */
919 break;
920 }
921 }
922
923 #define DWC3_ALIGN_MASK (16 - 1)
924
925 static int dwc3_probe(struct platform_device *pdev)
926 {
927 struct device *dev = &pdev->dev;
928 struct resource *res;
929 struct dwc3 *dwc;
930 u8 lpm_nyet_threshold;
931 u8 tx_de_emphasis;
932 u8 hird_threshold;
933
934 int ret;
935
936 void __iomem *regs;
937 void *mem;
938
939 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
940 if (!mem)
941 return -ENOMEM;
942
943 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
944 dwc->mem = mem;
945 dwc->dev = dev;
946
947 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
948 if (!res) {
949 dev_err(dev, "missing memory resource\n");
950 return -ENODEV;
951 }
952
953 dwc->xhci_resources[0].start = res->start;
954 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
955 DWC3_XHCI_REGS_END;
956 dwc->xhci_resources[0].flags = res->flags;
957 dwc->xhci_resources[0].name = res->name;
958
959 res->start += DWC3_GLOBALS_REGS_START;
960
961 /*
962 * Request memory region but exclude xHCI regs,
963 * since it will be requested by the xhci-plat driver.
964 */
965 regs = devm_ioremap_resource(dev, res);
966 if (IS_ERR(regs)) {
967 ret = PTR_ERR(regs);
968 goto err0;
969 }
970
971 dwc->regs = regs;
972 dwc->regs_size = resource_size(res);
973
974 /* default to highest possible threshold */
975 lpm_nyet_threshold = 0xff;
976
977 /* default to -3.5dB de-emphasis */
978 tx_de_emphasis = 1;
979
980 /*
981 * default to assert utmi_sleep_n and use maximum allowed HIRD
982 * threshold value of 0b1100
983 */
984 hird_threshold = 12;
985
986 dwc->maximum_speed = usb_get_maximum_speed(dev);
987 dwc->dr_mode = usb_get_dr_mode(dev);
988 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
989
990 dwc->has_lpm_erratum = device_property_read_bool(dev,
991 "snps,has-lpm-erratum");
992 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
993 &lpm_nyet_threshold);
994 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
995 "snps,is-utmi-l1-suspend");
996 device_property_read_u8(dev, "snps,hird-threshold",
997 &hird_threshold);
998 dwc->usb3_lpm_capable = device_property_read_bool(dev,
999 "snps,usb3_lpm_capable");
1000
1001 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1002 "snps,disable_scramble_quirk");
1003 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1004 "snps,u2exit_lfps_quirk");
1005 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1006 "snps,u2ss_inp3_quirk");
1007 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1008 "snps,req_p1p2p3_quirk");
1009 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1010 "snps,del_p1p2p3_quirk");
1011 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1012 "snps,del_phy_power_chg_quirk");
1013 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1014 "snps,lfps_filter_quirk");
1015 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1016 "snps,rx_detect_poll_quirk");
1017 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1018 "snps,dis_u3_susphy_quirk");
1019 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1020 "snps,dis_u2_susphy_quirk");
1021 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1022 "snps,dis_enblslpm_quirk");
1023 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1024 "snps,dis_rxdet_inp3_quirk");
1025 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1026 "snps,dis-u2-freeclk-exists-quirk");
1027 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1028 "snps,dis-del-phy-power-chg-quirk");
1029
1030 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1031 "snps,tx_de_emphasis_quirk");
1032 device_property_read_u8(dev, "snps,tx_de_emphasis",
1033 &tx_de_emphasis);
1034 device_property_read_string(dev, "snps,hsphy_interface",
1035 &dwc->hsphy_interface);
1036 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1037 &dwc->fladj);
1038
1039 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1040 dwc->tx_de_emphasis = tx_de_emphasis;
1041
1042 dwc->hird_threshold = hird_threshold
1043 | (dwc->is_utmi_l1_suspend << 4);
1044
1045 platform_set_drvdata(pdev, dwc);
1046 dwc3_cache_hwparams(dwc);
1047
1048 ret = dwc3_core_get_phy(dwc);
1049 if (ret)
1050 goto err0;
1051
1052 spin_lock_init(&dwc->lock);
1053
1054 if (!dev->dma_mask) {
1055 dev->dma_mask = dev->parent->dma_mask;
1056 dev->dma_parms = dev->parent->dma_parms;
1057 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
1058 }
1059
1060 pm_runtime_set_active(dev);
1061 pm_runtime_use_autosuspend(dev);
1062 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1063 pm_runtime_enable(dev);
1064 ret = pm_runtime_get_sync(dev);
1065 if (ret < 0)
1066 goto err1;
1067
1068 pm_runtime_forbid(dev);
1069
1070 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1071 if (ret) {
1072 dev_err(dwc->dev, "failed to allocate event buffers\n");
1073 ret = -ENOMEM;
1074 goto err2;
1075 }
1076
1077 ret = dwc3_get_dr_mode(dwc);
1078 if (ret)
1079 goto err3;
1080
1081 ret = dwc3_alloc_scratch_buffers(dwc);
1082 if (ret)
1083 goto err3;
1084
1085 ret = dwc3_core_init(dwc);
1086 if (ret) {
1087 dev_err(dev, "failed to initialize core\n");
1088 goto err4;
1089 }
1090
1091 /* Check the maximum_speed parameter */
1092 switch (dwc->maximum_speed) {
1093 case USB_SPEED_LOW:
1094 case USB_SPEED_FULL:
1095 case USB_SPEED_HIGH:
1096 case USB_SPEED_SUPER:
1097 case USB_SPEED_SUPER_PLUS:
1098 break;
1099 default:
1100 dev_err(dev, "invalid maximum_speed parameter %d\n",
1101 dwc->maximum_speed);
1102 /* fall through */
1103 case USB_SPEED_UNKNOWN:
1104 /* default to superspeed */
1105 dwc->maximum_speed = USB_SPEED_SUPER;
1106
1107 /*
1108 * default to superspeed plus if we are capable.
1109 */
1110 if (dwc3_is_usb31(dwc) &&
1111 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1112 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1113 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1114
1115 break;
1116 }
1117
1118 ret = dwc3_core_init_mode(dwc);
1119 if (ret)
1120 goto err5;
1121
1122 dwc3_debugfs_init(dwc);
1123 pm_runtime_put(dev);
1124
1125 return 0;
1126
1127 err5:
1128 dwc3_event_buffers_cleanup(dwc);
1129
1130 err4:
1131 dwc3_free_scratch_buffers(dwc);
1132
1133 err3:
1134 dwc3_free_event_buffers(dwc);
1135 dwc3_ulpi_exit(dwc);
1136
1137 err2:
1138 pm_runtime_allow(&pdev->dev);
1139
1140 err1:
1141 pm_runtime_put_sync(&pdev->dev);
1142 pm_runtime_disable(&pdev->dev);
1143
1144 err0:
1145 /*
1146 * restore res->start back to its original value so that, in case the
1147 * probe is deferred, we don't end up getting error in request the
1148 * memory region the next time probe is called.
1149 */
1150 res->start -= DWC3_GLOBALS_REGS_START;
1151
1152 return ret;
1153 }
1154
1155 static int dwc3_remove(struct platform_device *pdev)
1156 {
1157 struct dwc3 *dwc = platform_get_drvdata(pdev);
1158 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1159
1160 pm_runtime_get_sync(&pdev->dev);
1161 /*
1162 * restore res->start back to its original value so that, in case the
1163 * probe is deferred, we don't end up getting error in request the
1164 * memory region the next time probe is called.
1165 */
1166 res->start -= DWC3_GLOBALS_REGS_START;
1167
1168 dwc3_debugfs_exit(dwc);
1169 dwc3_core_exit_mode(dwc);
1170
1171 dwc3_core_exit(dwc);
1172 dwc3_ulpi_exit(dwc);
1173
1174 pm_runtime_put_sync(&pdev->dev);
1175 pm_runtime_allow(&pdev->dev);
1176 pm_runtime_disable(&pdev->dev);
1177
1178 dwc3_free_event_buffers(dwc);
1179 dwc3_free_scratch_buffers(dwc);
1180
1181 return 0;
1182 }
1183
1184 #ifdef CONFIG_PM
1185 static int dwc3_suspend_common(struct dwc3 *dwc)
1186 {
1187 unsigned long flags;
1188
1189 switch (dwc->dr_mode) {
1190 case USB_DR_MODE_PERIPHERAL:
1191 case USB_DR_MODE_OTG:
1192 spin_lock_irqsave(&dwc->lock, flags);
1193 dwc3_gadget_suspend(dwc);
1194 spin_unlock_irqrestore(&dwc->lock, flags);
1195 break;
1196 case USB_DR_MODE_HOST:
1197 default:
1198 /* do nothing */
1199 break;
1200 }
1201
1202 dwc3_core_exit(dwc);
1203
1204 return 0;
1205 }
1206
1207 static int dwc3_resume_common(struct dwc3 *dwc)
1208 {
1209 unsigned long flags;
1210 int ret;
1211
1212 ret = dwc3_core_init(dwc);
1213 if (ret)
1214 return ret;
1215
1216 switch (dwc->dr_mode) {
1217 case USB_DR_MODE_PERIPHERAL:
1218 case USB_DR_MODE_OTG:
1219 spin_lock_irqsave(&dwc->lock, flags);
1220 dwc3_gadget_resume(dwc);
1221 spin_unlock_irqrestore(&dwc->lock, flags);
1222 /* FALLTHROUGH */
1223 case USB_DR_MODE_HOST:
1224 default:
1225 /* do nothing */
1226 break;
1227 }
1228
1229 return 0;
1230 }
1231
1232 static int dwc3_runtime_checks(struct dwc3 *dwc)
1233 {
1234 switch (dwc->dr_mode) {
1235 case USB_DR_MODE_PERIPHERAL:
1236 case USB_DR_MODE_OTG:
1237 if (dwc->connected)
1238 return -EBUSY;
1239 break;
1240 case USB_DR_MODE_HOST:
1241 default:
1242 /* do nothing */
1243 break;
1244 }
1245
1246 return 0;
1247 }
1248
1249 static int dwc3_runtime_suspend(struct device *dev)
1250 {
1251 struct dwc3 *dwc = dev_get_drvdata(dev);
1252 int ret;
1253
1254 if (dwc3_runtime_checks(dwc))
1255 return -EBUSY;
1256
1257 ret = dwc3_suspend_common(dwc);
1258 if (ret)
1259 return ret;
1260
1261 device_init_wakeup(dev, true);
1262
1263 return 0;
1264 }
1265
1266 static int dwc3_runtime_resume(struct device *dev)
1267 {
1268 struct dwc3 *dwc = dev_get_drvdata(dev);
1269 int ret;
1270
1271 device_init_wakeup(dev, false);
1272
1273 ret = dwc3_resume_common(dwc);
1274 if (ret)
1275 return ret;
1276
1277 switch (dwc->dr_mode) {
1278 case USB_DR_MODE_PERIPHERAL:
1279 case USB_DR_MODE_OTG:
1280 dwc3_gadget_process_pending_events(dwc);
1281 break;
1282 case USB_DR_MODE_HOST:
1283 default:
1284 /* do nothing */
1285 break;
1286 }
1287
1288 pm_runtime_mark_last_busy(dev);
1289 pm_runtime_put(dev);
1290
1291 return 0;
1292 }
1293
1294 static int dwc3_runtime_idle(struct device *dev)
1295 {
1296 struct dwc3 *dwc = dev_get_drvdata(dev);
1297
1298 switch (dwc->dr_mode) {
1299 case USB_DR_MODE_PERIPHERAL:
1300 case USB_DR_MODE_OTG:
1301 if (dwc3_runtime_checks(dwc))
1302 return -EBUSY;
1303 break;
1304 case USB_DR_MODE_HOST:
1305 default:
1306 /* do nothing */
1307 break;
1308 }
1309
1310 pm_runtime_mark_last_busy(dev);
1311 pm_runtime_autosuspend(dev);
1312
1313 return 0;
1314 }
1315 #endif /* CONFIG_PM */
1316
1317 #ifdef CONFIG_PM_SLEEP
1318 static int dwc3_suspend(struct device *dev)
1319 {
1320 struct dwc3 *dwc = dev_get_drvdata(dev);
1321 int ret;
1322
1323 ret = dwc3_suspend_common(dwc);
1324 if (ret)
1325 return ret;
1326
1327 pinctrl_pm_select_sleep_state(dev);
1328
1329 return 0;
1330 }
1331
1332 static int dwc3_resume(struct device *dev)
1333 {
1334 struct dwc3 *dwc = dev_get_drvdata(dev);
1335 int ret;
1336
1337 pinctrl_pm_select_default_state(dev);
1338
1339 ret = dwc3_resume_common(dwc);
1340 if (ret)
1341 return ret;
1342
1343 pm_runtime_disable(dev);
1344 pm_runtime_set_active(dev);
1345 pm_runtime_enable(dev);
1346
1347 return 0;
1348 }
1349 #endif /* CONFIG_PM_SLEEP */
1350
1351 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1352 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1353 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1354 dwc3_runtime_idle)
1355 };
1356
1357 #ifdef CONFIG_OF
1358 static const struct of_device_id of_dwc3_match[] = {
1359 {
1360 .compatible = "snps,dwc3"
1361 },
1362 {
1363 .compatible = "synopsys,dwc3"
1364 },
1365 { },
1366 };
1367 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1368 #endif
1369
1370 #ifdef CONFIG_ACPI
1371
1372 #define ACPI_ID_INTEL_BSW "808622B7"
1373
1374 static const struct acpi_device_id dwc3_acpi_match[] = {
1375 { ACPI_ID_INTEL_BSW, 0 },
1376 { },
1377 };
1378 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1379 #endif
1380
1381 static struct platform_driver dwc3_driver = {
1382 .probe = dwc3_probe,
1383 .remove = dwc3_remove,
1384 .driver = {
1385 .name = "dwc3",
1386 .of_match_table = of_match_ptr(of_dwc3_match),
1387 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1388 .pm = &dwc3_dev_pm_ops,
1389 },
1390 };
1391
1392 module_platform_driver(dwc3_driver);
1393
1394 MODULE_ALIAS("platform:dwc3");
1395 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1396 MODULE_LICENSE("GPL v2");
1397 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
Linux kernel - Deliverables
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