projects / deliverable / linux.git / blob
? search:


77c141797152ef80af0a9e2d0070bfc56e796f27
[deliverable/linux.git] / include / linux / mlx5 / device.h
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX5_DEVICE_H
34 #define MLX5_DEVICE_H
35
36 #include <linux/types.h>
37 #include <rdma/ib_verbs.h>
38 #include <linux/mlx5/mlx5_ifc.h>
39
40 #if defined(__LITTLE_ENDIAN)
41 #define MLX5_SET_HOST_ENDIANNESS 0
42 #elif defined(__BIG_ENDIAN)
43 #define MLX5_SET_HOST_ENDIANNESS 0x80
44 #else
45 #error Host endianness not defined
46 #endif
47
48 /* helper macros */
49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51 #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
52 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
53 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
56 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
57 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
58
59 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
60 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
61 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
62 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
63 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
64 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
65 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
66 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
67
68 /* insert a value to a struct */
69 #define MLX5_SET(typ, p, fld, v) do { \
70 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
71 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
72 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
73 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
74 << __mlx5_dw_bit_off(typ, fld))); \
75 } while (0)
76
77 #define MLX5_SET_TO_ONES(typ, p, fld) do { \
78 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
79 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
80 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
81 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
82 << __mlx5_dw_bit_off(typ, fld))); \
83 } while (0)
84
85 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
86 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
87 __mlx5_mask(typ, fld))
88
89 #define MLX5_GET_PR(typ, p, fld) ({ \
90 u32 ___t = MLX5_GET(typ, p, fld); \
91 pr_debug(#fld " = 0x%x\n", ___t); \
92 ___t; \
93 })
94
95 #define MLX5_SET64(typ, p, fld, v) do { \
96 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
97 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
98 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
99 } while (0)
100
101 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
102
103 #define MLX5_GET64_PR(typ, p, fld) ({ \
104 u64 ___t = MLX5_GET64(typ, p, fld); \
105 pr_debug(#fld " = 0x%llx\n", ___t); \
106 ___t; \
107 })
108
109 /* Big endian getters */
110 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
111 __mlx5_64_off(typ, fld)))
112
113 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \
114 type_t tmp; \
115 switch (sizeof(tmp)) { \
116 case sizeof(u8): \
117 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
118 break; \
119 case sizeof(u16): \
120 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
121 break; \
122 case sizeof(u32): \
123 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
124 break; \
125 case sizeof(u64): \
126 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
127 break; \
128 } \
129 tmp; \
130 })
131
132 enum mlx5_inline_modes {
133 MLX5_INLINE_MODE_NONE,
134 MLX5_INLINE_MODE_L2,
135 MLX5_INLINE_MODE_IP,
136 MLX5_INLINE_MODE_TCP_UDP,
137 };
138
139 enum {
140 MLX5_MAX_COMMANDS = 32,
141 MLX5_CMD_DATA_BLOCK_SIZE = 512,
142 MLX5_PCI_CMD_XPORT = 7,
143 MLX5_MKEY_BSF_OCTO_SIZE = 4,
144 MLX5_MAX_PSVS = 4,
145 };
146
147 enum {
148 MLX5_EXTENDED_UD_AV = 0x80000000,
149 };
150
151 enum {
152 MLX5_CQ_STATE_ARMED = 9,
153 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
154 MLX5_CQ_STATE_FIRED = 0xa,
155 };
156
157 enum {
158 MLX5_STAT_RATE_OFFSET = 5,
159 };
160
161 enum {
162 MLX5_INLINE_SEG = 0x80000000,
163 };
164
165 enum {
166 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
167 };
168
169 enum {
170 MLX5_MIN_PKEY_TABLE_SIZE = 128,
171 MLX5_MAX_LOG_PKEY_TABLE = 5,
172 };
173
174 enum {
175 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
176 };
177
178 enum {
179 MLX5_PFAULT_SUBTYPE_WQE = 0,
180 MLX5_PFAULT_SUBTYPE_RDMA = 1,
181 };
182
183 enum {
184 MLX5_PERM_LOCAL_READ = 1 << 2,
185 MLX5_PERM_LOCAL_WRITE = 1 << 3,
186 MLX5_PERM_REMOTE_READ = 1 << 4,
187 MLX5_PERM_REMOTE_WRITE = 1 << 5,
188 MLX5_PERM_ATOMIC = 1 << 6,
189 MLX5_PERM_UMR_EN = 1 << 7,
190 };
191
192 enum {
193 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
194 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
195 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
196 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
197 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
198 };
199
200 enum {
201 MLX5_EN_RD = (u64)1,
202 MLX5_EN_WR = (u64)2
203 };
204
205 enum {
206 MLX5_BF_REGS_PER_PAGE = 4,
207 MLX5_MAX_UAR_PAGES = 1 << 8,
208 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
209 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
210 };
211
212 enum {
213 MLX5_MKEY_MASK_LEN = 1ull << 0,
214 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
215 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
216 MLX5_MKEY_MASK_PD = 1ull << 7,
217 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
218 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
219 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
220 MLX5_MKEY_MASK_KEY = 1ull << 13,
221 MLX5_MKEY_MASK_QPN = 1ull << 14,
222 MLX5_MKEY_MASK_LR = 1ull << 17,
223 MLX5_MKEY_MASK_LW = 1ull << 18,
224 MLX5_MKEY_MASK_RR = 1ull << 19,
225 MLX5_MKEY_MASK_RW = 1ull << 20,
226 MLX5_MKEY_MASK_A = 1ull << 21,
227 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
228 MLX5_MKEY_MASK_FREE = 1ull << 29,
229 };
230
231 enum {
232 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
233
234 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
235 MLX5_UMR_CHECK_FREE = (2 << 5),
236
237 MLX5_UMR_INLINE = (1 << 7),
238 };
239
240 #define MLX5_UMR_MTT_ALIGNMENT 0x40
241 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
242 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
243
244 #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
245
246 enum {
247 MLX5_EVENT_QUEUE_TYPE_QP = 0,
248 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
249 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
250 };
251
252 enum mlx5_event {
253 MLX5_EVENT_TYPE_COMP = 0x0,
254
255 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
256 MLX5_EVENT_TYPE_COMM_EST = 0x02,
257 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
258 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
259 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
260
261 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
262 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
263 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
264 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
265 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
266 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
267
268 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
269 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
270 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
271 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
272
273 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
274 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
275
276 MLX5_EVENT_TYPE_CMD = 0x0a,
277 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
278
279 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
280 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
281 };
282
283 enum {
284 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
285 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
286 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
287 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
288 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
289 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
290 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
291 };
292
293 enum {
294 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
295 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
296 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
297 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
298 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
299 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
300 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
301 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
302 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
303 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
304 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
305 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
306 };
307
308 enum {
309 MLX5_ROCE_VERSION_1 = 0,
310 MLX5_ROCE_VERSION_2 = 2,
311 };
312
313 enum {
314 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
315 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
316 };
317
318 enum {
319 MLX5_ROCE_L3_TYPE_IPV4 = 0,
320 MLX5_ROCE_L3_TYPE_IPV6 = 1,
321 };
322
323 enum {
324 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
325 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
326 };
327
328 enum {
329 MLX5_OPCODE_NOP = 0x00,
330 MLX5_OPCODE_SEND_INVAL = 0x01,
331 MLX5_OPCODE_RDMA_WRITE = 0x08,
332 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
333 MLX5_OPCODE_SEND = 0x0a,
334 MLX5_OPCODE_SEND_IMM = 0x0b,
335 MLX5_OPCODE_LSO = 0x0e,
336 MLX5_OPCODE_RDMA_READ = 0x10,
337 MLX5_OPCODE_ATOMIC_CS = 0x11,
338 MLX5_OPCODE_ATOMIC_FA = 0x12,
339 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
340 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
341 MLX5_OPCODE_BIND_MW = 0x18,
342 MLX5_OPCODE_CONFIG_CMD = 0x1f,
343
344 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
345 MLX5_RECV_OPCODE_SEND = 0x01,
346 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
347 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
348
349 MLX5_CQE_OPCODE_ERROR = 0x1e,
350 MLX5_CQE_OPCODE_RESIZE = 0x16,
351
352 MLX5_OPCODE_SET_PSV = 0x20,
353 MLX5_OPCODE_GET_PSV = 0x21,
354 MLX5_OPCODE_CHECK_PSV = 0x22,
355 MLX5_OPCODE_RGET_PSV = 0x26,
356 MLX5_OPCODE_RCHECK_PSV = 0x27,
357
358 MLX5_OPCODE_UMR = 0x25,
359
360 };
361
362 enum {
363 MLX5_SET_PORT_RESET_QKEY = 0,
364 MLX5_SET_PORT_GUID0 = 16,
365 MLX5_SET_PORT_NODE_GUID = 17,
366 MLX5_SET_PORT_SYS_GUID = 18,
367 MLX5_SET_PORT_GID_TABLE = 19,
368 MLX5_SET_PORT_PKEY_TABLE = 20,
369 };
370
371 enum {
372 MLX5_BW_NO_LIMIT = 0,
373 MLX5_100_MBPS_UNIT = 3,
374 MLX5_GBPS_UNIT = 4,
375 };
376
377 enum {
378 MLX5_MAX_PAGE_SHIFT = 31
379 };
380
381 enum {
382 MLX5_ADAPTER_PAGE_SHIFT = 12,
383 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
384 };
385
386 enum {
387 MLX5_CAP_OFF_CMDIF_CSUM = 46,
388 };
389
390 enum {
391 /*
392 * Max wqe size for rdma read is 512 bytes, so this
393 * limits our max_sge_rd as the wqe needs to fit:
394 * - ctrl segment (16 bytes)
395 * - rdma segment (16 bytes)
396 * - scatter elements (16 bytes each)
397 */
398 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
399 };
400
401 enum mlx5_odp_transport_cap_bits {
402 MLX5_ODP_SUPPORT_SEND = 1 << 31,
403 MLX5_ODP_SUPPORT_RECV = 1 << 30,
404 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
405 MLX5_ODP_SUPPORT_READ = 1 << 28,
406 };
407
408 struct mlx5_odp_caps {
409 char reserved[0x10];
410 struct {
411 __be32 rc_odp_caps;
412 __be32 uc_odp_caps;
413 __be32 ud_odp_caps;
414 } per_transport_caps;
415 char reserved2[0xe4];
416 };
417
418 struct mlx5_cmd_layout {
419 u8 type;
420 u8 rsvd0[3];
421 __be32 inlen;
422 __be64 in_ptr;
423 __be32 in[4];
424 __be32 out[4];
425 __be64 out_ptr;
426 __be32 outlen;
427 u8 token;
428 u8 sig;
429 u8 rsvd1;
430 u8 status_own;
431 };
432
433 struct health_buffer {
434 __be32 assert_var[5];
435 __be32 rsvd0[3];
436 __be32 assert_exit_ptr;
437 __be32 assert_callra;
438 __be32 rsvd1[2];
439 __be32 fw_ver;
440 __be32 hw_id;
441 __be32 rsvd2;
442 u8 irisc_index;
443 u8 synd;
444 __be16 ext_synd;
445 };
446
447 struct mlx5_init_seg {
448 __be32 fw_rev;
449 __be32 cmdif_rev_fw_sub;
450 __be32 rsvd0[2];
451 __be32 cmdq_addr_h;
452 __be32 cmdq_addr_l_sz;
453 __be32 cmd_dbell;
454 __be32 rsvd1[120];
455 __be32 initializing;
456 struct health_buffer health;
457 __be32 rsvd2[880];
458 __be32 internal_timer_h;
459 __be32 internal_timer_l;
460 __be32 rsvd3[2];
461 __be32 health_counter;
462 __be32 rsvd4[1019];
463 __be64 ieee1588_clk;
464 __be32 ieee1588_clk_type;
465 __be32 clr_intx;
466 };
467
468 struct mlx5_eqe_comp {
469 __be32 reserved[6];
470 __be32 cqn;
471 };
472
473 struct mlx5_eqe_qp_srq {
474 __be32 reserved1[5];
475 u8 type;
476 u8 reserved2[3];
477 __be32 qp_srq_n;
478 };
479
480 struct mlx5_eqe_cq_err {
481 __be32 cqn;
482 u8 reserved1[7];
483 u8 syndrome;
484 };
485
486 struct mlx5_eqe_port_state {
487 u8 reserved0[8];
488 u8 port;
489 };
490
491 struct mlx5_eqe_gpio {
492 __be32 reserved0[2];
493 __be64 gpio_event;
494 };
495
496 struct mlx5_eqe_congestion {
497 u8 type;
498 u8 rsvd0;
499 u8 congestion_level;
500 };
501
502 struct mlx5_eqe_stall_vl {
503 u8 rsvd0[3];
504 u8 port_vl;
505 };
506
507 struct mlx5_eqe_cmd {
508 __be32 vector;
509 __be32 rsvd[6];
510 };
511
512 struct mlx5_eqe_page_req {
513 u8 rsvd0[2];
514 __be16 func_id;
515 __be32 num_pages;
516 __be32 rsvd1[5];
517 };
518
519 struct mlx5_eqe_page_fault {
520 __be32 bytes_committed;
521 union {
522 struct {
523 u16 reserved1;
524 __be16 wqe_index;
525 u16 reserved2;
526 __be16 packet_length;
527 u8 reserved3[12];
528 } __packed wqe;
529 struct {
530 __be32 r_key;
531 u16 reserved1;
532 __be16 packet_length;
533 __be32 rdma_op_len;
534 __be64 rdma_va;
535 } __packed rdma;
536 } __packed;
537 __be32 flags_qpn;
538 } __packed;
539
540 struct mlx5_eqe_vport_change {
541 u8 rsvd0[2];
542 __be16 vport_num;
543 __be32 rsvd1[6];
544 } __packed;
545
546 union ev_data {
547 __be32 raw[7];
548 struct mlx5_eqe_cmd cmd;
549 struct mlx5_eqe_comp comp;
550 struct mlx5_eqe_qp_srq qp_srq;
551 struct mlx5_eqe_cq_err cq_err;
552 struct mlx5_eqe_port_state port;
553 struct mlx5_eqe_gpio gpio;
554 struct mlx5_eqe_congestion cong;
555 struct mlx5_eqe_stall_vl stall_vl;
556 struct mlx5_eqe_page_req req_pages;
557 struct mlx5_eqe_page_fault page_fault;
558 struct mlx5_eqe_vport_change vport_change;
559 } __packed;
560
561 struct mlx5_eqe {
562 u8 rsvd0;
563 u8 type;
564 u8 rsvd1;
565 u8 sub_type;
566 __be32 rsvd2[7];
567 union ev_data data;
568 __be16 rsvd3;
569 u8 signature;
570 u8 owner;
571 } __packed;
572
573 struct mlx5_cmd_prot_block {
574 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
575 u8 rsvd0[48];
576 __be64 next;
577 __be32 block_num;
578 u8 rsvd1;
579 u8 token;
580 u8 ctrl_sig;
581 u8 sig;
582 };
583
584 enum {
585 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
586 };
587
588 struct mlx5_err_cqe {
589 u8 rsvd0[32];
590 __be32 srqn;
591 u8 rsvd1[18];
592 u8 vendor_err_synd;
593 u8 syndrome;
594 __be32 s_wqe_opcode_qpn;
595 __be16 wqe_counter;
596 u8 signature;
597 u8 op_own;
598 };
599
600 struct mlx5_cqe64 {
601 u8 outer_l3_tunneled;
602 u8 rsvd0;
603 __be16 wqe_id;
604 u8 lro_tcppsh_abort_dupack;
605 u8 lro_min_ttl;
606 __be16 lro_tcp_win;
607 __be32 lro_ack_seq_num;
608 __be32 rss_hash_result;
609 u8 rss_hash_type;
610 u8 ml_path;
611 u8 rsvd20[2];
612 __be16 check_sum;
613 __be16 slid;
614 __be32 flags_rqpn;
615 u8 hds_ip_ext;
616 u8 l4_l3_hdr_type;
617 __be16 vlan_info;
618 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
619 __be32 imm_inval_pkey;
620 u8 rsvd40[4];
621 __be32 byte_cnt;
622 __be32 timestamp_h;
623 __be32 timestamp_l;
624 __be32 sop_drop_qpn;
625 __be16 wqe_counter;
626 u8 signature;
627 u8 op_own;
628 };
629
630 struct mlx5_mini_cqe8 {
631 union {
632 __be32 rx_hash_result;
633 struct {
634 __be16 checksum;
635 __be16 rsvd;
636 };
637 struct {
638 __be16 wqe_counter;
639 u8 s_wqe_opcode;
640 u8 reserved;
641 } s_wqe_info;
642 };
643 __be32 byte_cnt;
644 };
645
646 enum {
647 MLX5_NO_INLINE_DATA,
648 MLX5_INLINE_DATA32_SEG,
649 MLX5_INLINE_DATA64_SEG,
650 MLX5_COMPRESSED,
651 };
652
653 enum {
654 MLX5_CQE_FORMAT_CSUM = 0x1,
655 };
656
657 #define MLX5_MINI_CQE_ARRAY_SIZE 8
658
659 static inline int mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
660 {
661 return (cqe->op_own >> 2) & 0x3;
662 }
663
664 static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
665 {
666 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
667 }
668
669 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
670 {
671 return (cqe->l4_l3_hdr_type >> 4) & 0x7;
672 }
673
674 static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe)
675 {
676 return (cqe->l4_l3_hdr_type >> 2) & 0x3;
677 }
678
679 static inline u8 cqe_is_tunneled(struct mlx5_cqe64 *cqe)
680 {
681 return cqe->outer_l3_tunneled & 0x1;
682 }
683
684 static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
685 {
686 return !!(cqe->l4_l3_hdr_type & 0x1);
687 }
688
689 static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
690 {
691 u32 hi, lo;
692
693 hi = be32_to_cpu(cqe->timestamp_h);
694 lo = be32_to_cpu(cqe->timestamp_l);
695
696 return (u64)lo | ((u64)hi << 32);
697 }
698
699 struct mpwrq_cqe_bc {
700 __be16 filler_consumed_strides;
701 __be16 byte_cnt;
702 };
703
704 static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
705 {
706 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
707
708 return be16_to_cpu(bc->byte_cnt);
709 }
710
711 static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
712 {
713 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
714 }
715
716 static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
717 {
718 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
719
720 return mpwrq_get_cqe_bc_consumed_strides(bc);
721 }
722
723 static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
724 {
725 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
726
727 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
728 }
729
730 static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
731 {
732 return be16_to_cpu(cqe->wqe_counter);
733 }
734
735 enum {
736 CQE_L4_HDR_TYPE_NONE = 0x0,
737 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
738 CQE_L4_HDR_TYPE_UDP = 0x2,
739 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
740 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
741 };
742
743 enum {
744 CQE_RSS_HTYPE_IP = 0x3 << 6,
745 CQE_RSS_HTYPE_L4 = 0x3 << 2,
746 };
747
748 enum {
749 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
750 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
751 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
752 };
753
754 enum {
755 CQE_L2_OK = 1 << 0,
756 CQE_L3_OK = 1 << 1,
757 CQE_L4_OK = 1 << 2,
758 };
759
760 struct mlx5_sig_err_cqe {
761 u8 rsvd0[16];
762 __be32 expected_trans_sig;
763 __be32 actual_trans_sig;
764 __be32 expected_reftag;
765 __be32 actual_reftag;
766 __be16 syndrome;
767 u8 rsvd22[2];
768 __be32 mkey;
769 __be64 err_offset;
770 u8 rsvd30[8];
771 __be32 qpn;
772 u8 rsvd38[2];
773 u8 signature;
774 u8 op_own;
775 };
776
777 struct mlx5_wqe_srq_next_seg {
778 u8 rsvd0[2];
779 __be16 next_wqe_index;
780 u8 signature;
781 u8 rsvd1[11];
782 };
783
784 union mlx5_ext_cqe {
785 struct ib_grh grh;
786 u8 inl[64];
787 };
788
789 struct mlx5_cqe128 {
790 union mlx5_ext_cqe inl_grh;
791 struct mlx5_cqe64 cqe64;
792 };
793
794 enum {
795 MLX5_MKEY_STATUS_FREE = 1 << 6,
796 };
797
798 enum {
799 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
800 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
801 MLX5_MKEY_BSF_EN = 1 << 30,
802 MLX5_MKEY_LEN64 = 1 << 31,
803 };
804
805 struct mlx5_mkey_seg {
806 /* This is a two bit field occupying bits 31-30.
807 * bit 31 is always 0,
808 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
809 */
810 u8 status;
811 u8 pcie_control;
812 u8 flags;
813 u8 version;
814 __be32 qpn_mkey7_0;
815 u8 rsvd1[4];
816 __be32 flags_pd;
817 __be64 start_addr;
818 __be64 len;
819 __be32 bsfs_octo_size;
820 u8 rsvd2[16];
821 __be32 xlt_oct_size;
822 u8 rsvd3[3];
823 u8 log2_page_size;
824 u8 rsvd4[4];
825 };
826
827 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
828
829 enum {
830 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
831 };
832
833 enum {
834 VPORT_STATE_DOWN = 0x0,
835 VPORT_STATE_UP = 0x1,
836 };
837
838 enum {
839 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0,
840 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1,
841 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2,
842 };
843
844 enum {
845 MLX5_L3_PROT_TYPE_IPV4 = 0,
846 MLX5_L3_PROT_TYPE_IPV6 = 1,
847 };
848
849 enum {
850 MLX5_L4_PROT_TYPE_TCP = 0,
851 MLX5_L4_PROT_TYPE_UDP = 1,
852 };
853
854 enum {
855 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
856 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
857 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
858 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
859 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
860 };
861
862 enum {
863 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
864 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
865 MLX5_MATCH_INNER_HEADERS = 1 << 2,
866
867 };
868
869 enum {
870 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
871 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
872 };
873
874 enum {
875 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
876 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
877 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
878 };
879
880 enum mlx5_list_type {
881 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
882 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
883 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
884 };
885
886 enum {
887 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
888 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
889 };
890
891 enum mlx5_wol_mode {
892 MLX5_WOL_DISABLE = 0,
893 MLX5_WOL_SECURED_MAGIC = 1 << 1,
894 MLX5_WOL_MAGIC = 1 << 2,
895 MLX5_WOL_ARP = 1 << 3,
896 MLX5_WOL_BROADCAST = 1 << 4,
897 MLX5_WOL_MULTICAST = 1 << 5,
898 MLX5_WOL_UNICAST = 1 << 6,
899 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
900 };
901
902 /* MLX5 DEV CAPs */
903
904 /* TODO: EAT.ME */
905 enum mlx5_cap_mode {
906 HCA_CAP_OPMOD_GET_MAX = 0,
907 HCA_CAP_OPMOD_GET_CUR = 1,
908 };
909
910 enum mlx5_cap_type {
911 MLX5_CAP_GENERAL = 0,
912 MLX5_CAP_ETHERNET_OFFLOADS,
913 MLX5_CAP_ODP,
914 MLX5_CAP_ATOMIC,
915 MLX5_CAP_ROCE,
916 MLX5_CAP_IPOIB_OFFLOADS,
917 MLX5_CAP_EOIB_OFFLOADS,
918 MLX5_CAP_FLOW_TABLE,
919 MLX5_CAP_ESWITCH_FLOW_TABLE,
920 MLX5_CAP_ESWITCH,
921 MLX5_CAP_RESERVED,
922 MLX5_CAP_VECTOR_CALC,
923 MLX5_CAP_QOS,
924 /* NUM OF CAP Types */
925 MLX5_CAP_NUM
926 };
927
928 /* GET Dev Caps macros */
929 #define MLX5_CAP_GEN(mdev, cap) \
930 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
931
932 #define MLX5_CAP_GEN_MAX(mdev, cap) \
933 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
934
935 #define MLX5_CAP_ETH(mdev, cap) \
936 MLX5_GET(per_protocol_networking_offload_caps,\
937 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
938
939 #define MLX5_CAP_ETH_MAX(mdev, cap) \
940 MLX5_GET(per_protocol_networking_offload_caps,\
941 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
942
943 #define MLX5_CAP_ROCE(mdev, cap) \
944 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
945
946 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
947 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
948
949 #define MLX5_CAP_ATOMIC(mdev, cap) \
950 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
951
952 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
953 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
954
955 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
956 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
957
958 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
959 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
960
961 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
962 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
963
964 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
965 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
966
967 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
968 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
969
970 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \
971 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
972
973 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
974 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
975
976 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \
977 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
978
979 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
980 MLX5_GET(flow_table_eswitch_cap, \
981 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
982
983 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
984 MLX5_GET(flow_table_eswitch_cap, \
985 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
986
987 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
988 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
989
990 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
991 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
992
993 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
994 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
995
996 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
997 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
998
999 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1000 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1001
1002 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1003 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1004
1005 #define MLX5_CAP_ESW(mdev, cap) \
1006 MLX5_GET(e_switch_cap, \
1007 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1008
1009 #define MLX5_CAP_ESW_MAX(mdev, cap) \
1010 MLX5_GET(e_switch_cap, \
1011 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1012
1013 #define MLX5_CAP_ODP(mdev, cap)\
1014 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1015
1016 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1017 MLX5_GET(vector_calc_cap, \
1018 mdev->hca_caps_cur[MLX5_CAP_VECTOR_CALC], cap)
1019
1020 #define MLX5_CAP_QOS(mdev, cap)\
1021 MLX5_GET(qos_cap, mdev->hca_caps_cur[MLX5_CAP_QOS], cap)
1022
1023 enum {
1024 MLX5_CMD_STAT_OK = 0x0,
1025 MLX5_CMD_STAT_INT_ERR = 0x1,
1026 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1027 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1028 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1029 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1030 MLX5_CMD_STAT_RES_BUSY = 0x6,
1031 MLX5_CMD_STAT_LIM_ERR = 0x8,
1032 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1033 MLX5_CMD_STAT_IX_ERR = 0xa,
1034 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1035 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1036 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1037 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1038 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1039 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1040 };
1041
1042 enum {
1043 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1044 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1045 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1046 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1047 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1048 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1049 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1050 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1051 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1052 };
1053
1054 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1055 {
1056 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1057 return 0;
1058 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1059 }
1060
1061 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
1062 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
1063 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1064 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1065 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1066 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
1067
1068 #endif /* MLX5_DEVICE_H */
Linux kernel - Deliverables
This page took 0.061628 seconds and 4 git commands to generate.