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Merge branch 'for-linus' of git://git.kernel.dk/linux-block
[deliverable/linux.git] / sound / soc / codecs / nau8825.c
1 /*
2 * Nuvoton NAU8825 audio codec driver
3 *
4 * Copyright 2015 Google Chromium project.
5 * Author: Anatol Pomozov <anatol@chromium.org>
6 * Copyright 2015 Nuvoton Technology Corp.
7 * Co-author: Meng-Huang Kuo <mhkuo@nuvoton.com>
8 *
9 * Licensed under the GPL-2.
10 */
11
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/i2c.h>
16 #include <linux/regmap.h>
17 #include <linux/slab.h>
18 #include <linux/clk.h>
19 #include <linux/acpi.h>
20 #include <linux/math64.h>
21
22 #include <sound/initval.h>
23 #include <sound/tlv.h>
24 #include <sound/core.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/soc.h>
28 #include <sound/jack.h>
29
30
31 #include "nau8825.h"
32
33 #define NAU_FREF_MAX 13500000
34 #define NAU_FVCO_MAX 100000000
35 #define NAU_FVCO_MIN 90000000
36
37 struct nau8825_fll {
38 int mclk_src;
39 int ratio;
40 int fll_frac;
41 int fll_int;
42 int clk_ref_div;
43 };
44
45 struct nau8825_fll_attr {
46 unsigned int param;
47 unsigned int val;
48 };
49
50 /* scaling for mclk from sysclk_src output */
51 static const struct nau8825_fll_attr mclk_src_scaling[] = {
52 { 1, 0x0 },
53 { 2, 0x2 },
54 { 4, 0x3 },
55 { 8, 0x4 },
56 { 16, 0x5 },
57 { 32, 0x6 },
58 { 3, 0x7 },
59 { 6, 0xa },
60 { 12, 0xb },
61 { 24, 0xc },
62 { 48, 0xd },
63 { 96, 0xe },
64 { 5, 0xf },
65 };
66
67 /* ratio for input clk freq */
68 static const struct nau8825_fll_attr fll_ratio[] = {
69 { 512000, 0x01 },
70 { 256000, 0x02 },
71 { 128000, 0x04 },
72 { 64000, 0x08 },
73 { 32000, 0x10 },
74 { 8000, 0x20 },
75 { 4000, 0x40 },
76 };
77
78 static const struct nau8825_fll_attr fll_pre_scalar[] = {
79 { 1, 0x0 },
80 { 2, 0x1 },
81 { 4, 0x2 },
82 { 8, 0x3 },
83 };
84
85 static const struct reg_default nau8825_reg_defaults[] = {
86 { NAU8825_REG_ENA_CTRL, 0x00ff },
87 { NAU8825_REG_IIC_ADDR_SET, 0x0 },
88 { NAU8825_REG_CLK_DIVIDER, 0x0050 },
89 { NAU8825_REG_FLL1, 0x0 },
90 { NAU8825_REG_FLL2, 0x3126 },
91 { NAU8825_REG_FLL3, 0x0008 },
92 { NAU8825_REG_FLL4, 0x0010 },
93 { NAU8825_REG_FLL5, 0x0 },
94 { NAU8825_REG_FLL6, 0x6000 },
95 { NAU8825_REG_FLL_VCO_RSV, 0xf13c },
96 { NAU8825_REG_HSD_CTRL, 0x000c },
97 { NAU8825_REG_JACK_DET_CTRL, 0x0 },
98 { NAU8825_REG_INTERRUPT_MASK, 0x0 },
99 { NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff },
100 { NAU8825_REG_SAR_CTRL, 0x0015 },
101 { NAU8825_REG_KEYDET_CTRL, 0x0110 },
102 { NAU8825_REG_VDET_THRESHOLD_1, 0x0 },
103 { NAU8825_REG_VDET_THRESHOLD_2, 0x0 },
104 { NAU8825_REG_VDET_THRESHOLD_3, 0x0 },
105 { NAU8825_REG_VDET_THRESHOLD_4, 0x0 },
106 { NAU8825_REG_GPIO34_CTRL, 0x0 },
107 { NAU8825_REG_GPIO12_CTRL, 0x0 },
108 { NAU8825_REG_TDM_CTRL, 0x0 },
109 { NAU8825_REG_I2S_PCM_CTRL1, 0x000b },
110 { NAU8825_REG_I2S_PCM_CTRL2, 0x8010 },
111 { NAU8825_REG_LEFT_TIME_SLOT, 0x0 },
112 { NAU8825_REG_RIGHT_TIME_SLOT, 0x0 },
113 { NAU8825_REG_BIQ_CTRL, 0x0 },
114 { NAU8825_REG_BIQ_COF1, 0x0 },
115 { NAU8825_REG_BIQ_COF2, 0x0 },
116 { NAU8825_REG_BIQ_COF3, 0x0 },
117 { NAU8825_REG_BIQ_COF4, 0x0 },
118 { NAU8825_REG_BIQ_COF5, 0x0 },
119 { NAU8825_REG_BIQ_COF6, 0x0 },
120 { NAU8825_REG_BIQ_COF7, 0x0 },
121 { NAU8825_REG_BIQ_COF8, 0x0 },
122 { NAU8825_REG_BIQ_COF9, 0x0 },
123 { NAU8825_REG_BIQ_COF10, 0x0 },
124 { NAU8825_REG_ADC_RATE, 0x0010 },
125 { NAU8825_REG_DAC_CTRL1, 0x0001 },
126 { NAU8825_REG_DAC_CTRL2, 0x0 },
127 { NAU8825_REG_DAC_DGAIN_CTRL, 0x0 },
128 { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf },
129 { NAU8825_REG_MUTE_CTRL, 0x0 },
130 { NAU8825_REG_HSVOL_CTRL, 0x0 },
131 { NAU8825_REG_DACL_CTRL, 0x02cf },
132 { NAU8825_REG_DACR_CTRL, 0x00cf },
133 { NAU8825_REG_ADC_DRC_KNEE_IP12, 0x1486 },
134 { NAU8825_REG_ADC_DRC_KNEE_IP34, 0x0f12 },
135 { NAU8825_REG_ADC_DRC_SLOPES, 0x25ff },
136 { NAU8825_REG_ADC_DRC_ATKDCY, 0x3457 },
137 { NAU8825_REG_DAC_DRC_KNEE_IP12, 0x1486 },
138 { NAU8825_REG_DAC_DRC_KNEE_IP34, 0x0f12 },
139 { NAU8825_REG_DAC_DRC_SLOPES, 0x25f9 },
140 { NAU8825_REG_DAC_DRC_ATKDCY, 0x3457 },
141 { NAU8825_REG_IMM_MODE_CTRL, 0x0 },
142 { NAU8825_REG_CLASSG_CTRL, 0x0 },
143 { NAU8825_REG_OPT_EFUSE_CTRL, 0x0 },
144 { NAU8825_REG_MISC_CTRL, 0x0 },
145 { NAU8825_REG_BIAS_ADJ, 0x0 },
146 { NAU8825_REG_TRIM_SETTINGS, 0x0 },
147 { NAU8825_REG_ANALOG_CONTROL_1, 0x0 },
148 { NAU8825_REG_ANALOG_CONTROL_2, 0x0 },
149 { NAU8825_REG_ANALOG_ADC_1, 0x0011 },
150 { NAU8825_REG_ANALOG_ADC_2, 0x0020 },
151 { NAU8825_REG_RDAC, 0x0008 },
152 { NAU8825_REG_MIC_BIAS, 0x0006 },
153 { NAU8825_REG_BOOST, 0x0 },
154 { NAU8825_REG_FEPGA, 0x0 },
155 { NAU8825_REG_POWER_UP_CONTROL, 0x0 },
156 { NAU8825_REG_CHARGE_PUMP, 0x0 },
157 };
158
159 static bool nau8825_readable_reg(struct device *dev, unsigned int reg)
160 {
161 switch (reg) {
162 case NAU8825_REG_ENA_CTRL ... NAU8825_REG_FLL_VCO_RSV:
163 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
164 case NAU8825_REG_INTERRUPT_MASK ... NAU8825_REG_KEYDET_CTRL:
165 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
166 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
167 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
168 case NAU8825_REG_IMM_MODE_CTRL ... NAU8825_REG_IMM_RMS_R:
169 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
170 case NAU8825_REG_MISC_CTRL:
171 case NAU8825_REG_I2C_DEVICE_ID ... NAU8825_REG_SARDOUT_RAM_STATUS:
172 case NAU8825_REG_BIAS_ADJ:
173 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
174 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
175 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
176 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_GENERAL_STATUS:
177 return true;
178 default:
179 return false;
180 }
181
182 }
183
184 static bool nau8825_writeable_reg(struct device *dev, unsigned int reg)
185 {
186 switch (reg) {
187 case NAU8825_REG_RESET ... NAU8825_REG_FLL_VCO_RSV:
188 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
189 case NAU8825_REG_INTERRUPT_MASK:
190 case NAU8825_REG_INT_CLR_KEY_STATUS ... NAU8825_REG_KEYDET_CTRL:
191 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
192 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
193 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
194 case NAU8825_REG_IMM_MODE_CTRL:
195 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
196 case NAU8825_REG_MISC_CTRL:
197 case NAU8825_REG_BIAS_ADJ:
198 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
199 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
200 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
201 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_CHARGE_PUMP:
202 return true;
203 default:
204 return false;
205 }
206 }
207
208 static bool nau8825_volatile_reg(struct device *dev, unsigned int reg)
209 {
210 switch (reg) {
211 case NAU8825_REG_RESET:
212 case NAU8825_REG_IRQ_STATUS:
213 case NAU8825_REG_INT_CLR_KEY_STATUS:
214 case NAU8825_REG_IMM_RMS_L:
215 case NAU8825_REG_IMM_RMS_R:
216 case NAU8825_REG_I2C_DEVICE_ID:
217 case NAU8825_REG_SARDOUT_RAM_STATUS:
218 case NAU8825_REG_CHARGE_PUMP_INPUT_READ:
219 case NAU8825_REG_GENERAL_STATUS:
220 return true;
221 default:
222 return false;
223 }
224 }
225
226 static int nau8825_pump_event(struct snd_soc_dapm_widget *w,
227 struct snd_kcontrol *kcontrol, int event)
228 {
229 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
230 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
231
232 switch (event) {
233 case SND_SOC_DAPM_POST_PMU:
234 /* Prevent startup click by letting charge pump to ramp up */
235 msleep(10);
236 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
237 NAU8825_JAMNODCLOW, NAU8825_JAMNODCLOW);
238 break;
239 case SND_SOC_DAPM_PRE_PMD:
240 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
241 NAU8825_JAMNODCLOW, 0);
242 break;
243 default:
244 return -EINVAL;
245 }
246
247 return 0;
248 }
249
250 static int nau8825_output_dac_event(struct snd_soc_dapm_widget *w,
251 struct snd_kcontrol *kcontrol, int event)
252 {
253 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
254 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
255
256 switch (event) {
257 case SND_SOC_DAPM_PRE_PMU:
258 /* Disables the TESTDAC to let DAC signal pass through. */
259 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
260 NAU8825_BIAS_TESTDAC_EN, 0);
261 break;
262 case SND_SOC_DAPM_POST_PMD:
263 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
264 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
265 break;
266 default:
267 return -EINVAL;
268 }
269
270 return 0;
271 }
272
273 static const char * const nau8825_adc_decimation[] = {
274 "32", "64", "128", "256"
275 };
276
277 static const struct soc_enum nau8825_adc_decimation_enum =
278 SOC_ENUM_SINGLE(NAU8825_REG_ADC_RATE, NAU8825_ADC_SYNC_DOWN_SFT,
279 ARRAY_SIZE(nau8825_adc_decimation), nau8825_adc_decimation);
280
281 static const char * const nau8825_dac_oversampl[] = {
282 "64", "256", "128", "", "32"
283 };
284
285 static const struct soc_enum nau8825_dac_oversampl_enum =
286 SOC_ENUM_SINGLE(NAU8825_REG_DAC_CTRL1, NAU8825_DAC_OVERSAMPLE_SFT,
287 ARRAY_SIZE(nau8825_dac_oversampl), nau8825_dac_oversampl);
288
289 static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -10300, 2400);
290 static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0);
291 static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -5400, 0);
292 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
293 static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -9600, 2400);
294
295 static const struct snd_kcontrol_new nau8825_controls[] = {
296 SOC_SINGLE_TLV("Mic Volume", NAU8825_REG_ADC_DGAIN_CTRL,
297 0, 0xff, 0, adc_vol_tlv),
298 SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8825_REG_ADC_DGAIN_CTRL,
299 12, 8, 0x0f, 0, sidetone_vol_tlv),
300 SOC_DOUBLE_TLV("Headphone Volume", NAU8825_REG_HSVOL_CTRL,
301 6, 0, 0x3f, 1, dac_vol_tlv),
302 SOC_SINGLE_TLV("Frontend PGA Volume", NAU8825_REG_POWER_UP_CONTROL,
303 8, 37, 0, fepga_gain_tlv),
304 SOC_DOUBLE_TLV("Headphone Crosstalk Volume", NAU8825_REG_DAC_DGAIN_CTRL,
305 0, 8, 0xff, 0, crosstalk_vol_tlv),
306
307 SOC_ENUM("ADC Decimation Rate", nau8825_adc_decimation_enum),
308 SOC_ENUM("DAC Oversampling Rate", nau8825_dac_oversampl_enum),
309 };
310
311 /* DAC Mux 0x33[9] and 0x34[9] */
312 static const char * const nau8825_dac_src[] = {
313 "DACL", "DACR",
314 };
315
316 static SOC_ENUM_SINGLE_DECL(
317 nau8825_dacl_enum, NAU8825_REG_DACL_CTRL,
318 NAU8825_DACL_CH_SEL_SFT, nau8825_dac_src);
319
320 static SOC_ENUM_SINGLE_DECL(
321 nau8825_dacr_enum, NAU8825_REG_DACR_CTRL,
322 NAU8825_DACR_CH_SEL_SFT, nau8825_dac_src);
323
324 static const struct snd_kcontrol_new nau8825_dacl_mux =
325 SOC_DAPM_ENUM("DACL Source", nau8825_dacl_enum);
326
327 static const struct snd_kcontrol_new nau8825_dacr_mux =
328 SOC_DAPM_ENUM("DACR Source", nau8825_dacr_enum);
329
330
331 static const struct snd_soc_dapm_widget nau8825_dapm_widgets[] = {
332 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8825_REG_I2S_PCM_CTRL2,
333 15, 1),
334
335 SND_SOC_DAPM_INPUT("MIC"),
336 SND_SOC_DAPM_MICBIAS("MICBIAS", NAU8825_REG_MIC_BIAS, 8, 0),
337
338 SND_SOC_DAPM_PGA("Frontend PGA", NAU8825_REG_POWER_UP_CONTROL, 14, 0,
339 NULL, 0),
340
341 SND_SOC_DAPM_ADC("ADC", NULL, NAU8825_REG_ENA_CTRL, 8, 0),
342 SND_SOC_DAPM_SUPPLY("ADC Clock", NAU8825_REG_ENA_CTRL, 7, 0, NULL, 0),
343 SND_SOC_DAPM_SUPPLY("ADC Power", NAU8825_REG_ANALOG_ADC_2, 6, 0, NULL,
344 0),
345
346 /* ADC for button press detection. A dapm supply widget is used to
347 * prevent dapm_power_widgets keeping the codec at SND_SOC_BIAS_ON
348 * during suspend.
349 */
350 SND_SOC_DAPM_SUPPLY("SAR", NAU8825_REG_SAR_CTRL,
351 NAU8825_SAR_ADC_EN_SFT, 0, NULL, 0),
352
353 SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8825_REG_RDAC, 12, 0, NULL, 0),
354 SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8825_REG_RDAC, 13, 0, NULL, 0),
355 SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8825_REG_RDAC, 8, 0, NULL, 0),
356 SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8825_REG_RDAC, 9, 0, NULL, 0),
357
358 SND_SOC_DAPM_DAC("DDACR", NULL, NAU8825_REG_ENA_CTRL,
359 NAU8825_ENABLE_DACR_SFT, 0),
360 SND_SOC_DAPM_DAC("DDACL", NULL, NAU8825_REG_ENA_CTRL,
361 NAU8825_ENABLE_DACL_SFT, 0),
362 SND_SOC_DAPM_SUPPLY("DDAC Clock", NAU8825_REG_ENA_CTRL, 6, 0, NULL, 0),
363
364 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacl_mux),
365 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacr_mux),
366
367 SND_SOC_DAPM_PGA_S("HP amp L", 0,
368 NAU8825_REG_CLASSG_CTRL, 1, 0, NULL, 0),
369 SND_SOC_DAPM_PGA_S("HP amp R", 0,
370 NAU8825_REG_CLASSG_CTRL, 2, 0, NULL, 0),
371
372 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8825_REG_CHARGE_PUMP, 5, 0,
373 nau8825_pump_event, SND_SOC_DAPM_POST_PMU |
374 SND_SOC_DAPM_PRE_PMD),
375
376 SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4,
377 NAU8825_REG_POWER_UP_CONTROL, 5, 0, NULL, 0),
378 SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4,
379 NAU8825_REG_POWER_UP_CONTROL, 4, 0, NULL, 0),
380 SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5,
381 NAU8825_REG_POWER_UP_CONTROL, 3, 0, NULL, 0),
382 SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5,
383 NAU8825_REG_POWER_UP_CONTROL, 2, 0, NULL, 0),
384 SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6,
385 NAU8825_REG_POWER_UP_CONTROL, 1, 0, NULL, 0),
386 SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6,
387 NAU8825_REG_POWER_UP_CONTROL, 0, 0, NULL, 0),
388
389 SND_SOC_DAPM_PGA_S("Output DACL", 7,
390 NAU8825_REG_CHARGE_PUMP, 8, 1, nau8825_output_dac_event,
391 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
392 SND_SOC_DAPM_PGA_S("Output DACR", 7,
393 NAU8825_REG_CHARGE_PUMP, 9, 1, nau8825_output_dac_event,
394 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
395
396 /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */
397 SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8,
398 NAU8825_REG_HSD_CTRL, 0, 1, NULL, 0),
399 SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8,
400 NAU8825_REG_HSD_CTRL, 1, 1, NULL, 0),
401
402 /* High current HPOL/R boost driver */
403 SND_SOC_DAPM_PGA_S("HP Boost Driver", 9,
404 NAU8825_REG_BOOST, 9, 1, NULL, 0),
405
406 /* Class G operation control*/
407 SND_SOC_DAPM_PGA_S("Class G", 10,
408 NAU8825_REG_CLASSG_CTRL, 0, 0, NULL, 0),
409
410 SND_SOC_DAPM_OUTPUT("HPOL"),
411 SND_SOC_DAPM_OUTPUT("HPOR"),
412 };
413
414 static const struct snd_soc_dapm_route nau8825_dapm_routes[] = {
415 {"Frontend PGA", NULL, "MIC"},
416 {"ADC", NULL, "Frontend PGA"},
417 {"ADC", NULL, "ADC Clock"},
418 {"ADC", NULL, "ADC Power"},
419 {"AIFTX", NULL, "ADC"},
420
421 {"DDACL", NULL, "Playback"},
422 {"DDACR", NULL, "Playback"},
423 {"DDACL", NULL, "DDAC Clock"},
424 {"DDACR", NULL, "DDAC Clock"},
425 {"DACL Mux", "DACL", "DDACL"},
426 {"DACL Mux", "DACR", "DDACR"},
427 {"DACR Mux", "DACL", "DDACL"},
428 {"DACR Mux", "DACR", "DDACR"},
429 {"HP amp L", NULL, "DACL Mux"},
430 {"HP amp R", NULL, "DACR Mux"},
431 {"Charge Pump", NULL, "HP amp L"},
432 {"Charge Pump", NULL, "HP amp R"},
433 {"ADACL", NULL, "Charge Pump"},
434 {"ADACR", NULL, "Charge Pump"},
435 {"ADACL Clock", NULL, "ADACL"},
436 {"ADACR Clock", NULL, "ADACR"},
437 {"Output Driver L Stage 1", NULL, "ADACL Clock"},
438 {"Output Driver R Stage 1", NULL, "ADACR Clock"},
439 {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"},
440 {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"},
441 {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"},
442 {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"},
443 {"Output DACL", NULL, "Output Driver L Stage 3"},
444 {"Output DACR", NULL, "Output Driver R Stage 3"},
445 {"HPOL Pulldown", NULL, "Output DACL"},
446 {"HPOR Pulldown", NULL, "Output DACR"},
447 {"HP Boost Driver", NULL, "HPOL Pulldown"},
448 {"HP Boost Driver", NULL, "HPOR Pulldown"},
449 {"Class G", NULL, "HP Boost Driver"},
450 {"HPOL", NULL, "Class G"},
451 {"HPOR", NULL, "Class G"},
452 };
453
454 static int nau8825_hw_params(struct snd_pcm_substream *substream,
455 struct snd_pcm_hw_params *params,
456 struct snd_soc_dai *dai)
457 {
458 struct snd_soc_codec *codec = dai->codec;
459 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
460 unsigned int val_len = 0;
461
462 switch (params_width(params)) {
463 case 16:
464 val_len |= NAU8825_I2S_DL_16;
465 break;
466 case 20:
467 val_len |= NAU8825_I2S_DL_20;
468 break;
469 case 24:
470 val_len |= NAU8825_I2S_DL_24;
471 break;
472 case 32:
473 val_len |= NAU8825_I2S_DL_32;
474 break;
475 default:
476 return -EINVAL;
477 }
478
479 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
480 NAU8825_I2S_DL_MASK, val_len);
481
482 return 0;
483 }
484
485 static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
486 {
487 struct snd_soc_codec *codec = codec_dai->codec;
488 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
489 unsigned int ctrl1_val = 0, ctrl2_val = 0;
490
491 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
492 case SND_SOC_DAIFMT_CBM_CFM:
493 ctrl2_val |= NAU8825_I2S_MS_MASTER;
494 break;
495 case SND_SOC_DAIFMT_CBS_CFS:
496 break;
497 default:
498 return -EINVAL;
499 }
500
501 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
502 case SND_SOC_DAIFMT_NB_NF:
503 break;
504 case SND_SOC_DAIFMT_IB_NF:
505 ctrl1_val |= NAU8825_I2S_BP_INV;
506 break;
507 default:
508 return -EINVAL;
509 }
510
511 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
512 case SND_SOC_DAIFMT_I2S:
513 ctrl1_val |= NAU8825_I2S_DF_I2S;
514 break;
515 case SND_SOC_DAIFMT_LEFT_J:
516 ctrl1_val |= NAU8825_I2S_DF_LEFT;
517 break;
518 case SND_SOC_DAIFMT_RIGHT_J:
519 ctrl1_val |= NAU8825_I2S_DF_RIGTH;
520 break;
521 case SND_SOC_DAIFMT_DSP_A:
522 ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
523 break;
524 case SND_SOC_DAIFMT_DSP_B:
525 ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
526 ctrl1_val |= NAU8825_I2S_PCMB_EN;
527 break;
528 default:
529 return -EINVAL;
530 }
531
532 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
533 NAU8825_I2S_DL_MASK | NAU8825_I2S_DF_MASK |
534 NAU8825_I2S_BP_MASK | NAU8825_I2S_PCMB_MASK,
535 ctrl1_val);
536 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
537 NAU8825_I2S_MS_MASK, ctrl2_val);
538
539 return 0;
540 }
541
542 static const struct snd_soc_dai_ops nau8825_dai_ops = {
543 .hw_params = nau8825_hw_params,
544 .set_fmt = nau8825_set_dai_fmt,
545 };
546
547 #define NAU8825_RATES SNDRV_PCM_RATE_8000_192000
548 #define NAU8825_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
549 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
550
551 static struct snd_soc_dai_driver nau8825_dai = {
552 .name = "nau8825-hifi",
553 .playback = {
554 .stream_name = "Playback",
555 .channels_min = 1,
556 .channels_max = 2,
557 .rates = NAU8825_RATES,
558 .formats = NAU8825_FORMATS,
559 },
560 .capture = {
561 .stream_name = "Capture",
562 .channels_min = 1,
563 .channels_max = 1,
564 .rates = NAU8825_RATES,
565 .formats = NAU8825_FORMATS,
566 },
567 .ops = &nau8825_dai_ops,
568 };
569
570 /**
571 * nau8825_enable_jack_detect - Specify a jack for event reporting
572 *
573 * @component: component to register the jack with
574 * @jack: jack to use to report headset and button events on
575 *
576 * After this function has been called the headset insert/remove and button
577 * events will be routed to the given jack. Jack can be null to stop
578 * reporting.
579 */
580 int nau8825_enable_jack_detect(struct snd_soc_codec *codec,
581 struct snd_soc_jack *jack)
582 {
583 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
584 struct regmap *regmap = nau8825->regmap;
585
586 nau8825->jack = jack;
587
588 /* Ground HP Outputs[1:0], needed for headset auto detection
589 * Enable Automatic Mic/Gnd switching reading on insert interrupt[6]
590 */
591 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
592 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
593 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
594
595 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
596 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_EJECT_EN, 0);
597
598 return 0;
599 }
600 EXPORT_SYMBOL_GPL(nau8825_enable_jack_detect);
601
602
603 static bool nau8825_is_jack_inserted(struct regmap *regmap)
604 {
605 int status;
606
607 regmap_read(regmap, NAU8825_REG_I2C_DEVICE_ID, &status);
608 return !(status & NAU8825_GPIO2JD1);
609 }
610
611 static void nau8825_restart_jack_detection(struct regmap *regmap)
612 {
613 /* Chip needs one FSCLK cycle in order to generate interrupts,
614 * as we cannot guarantee one will be provided by the system. Turning
615 * master mode on then off enables us to generate that FSCLK cycle
616 * with a minimum of contention on the clock bus.
617 */
618 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
619 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_MASTER);
620 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
621 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_SLAVE);
622
623 /* this will restart the entire jack detection process including MIC/GND
624 * switching and create interrupts. We have to go from 0 to 1 and back
625 * to 0 to restart.
626 */
627 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
628 NAU8825_JACK_DET_RESTART, NAU8825_JACK_DET_RESTART);
629 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
630 NAU8825_JACK_DET_RESTART, 0);
631 }
632
633 static void nau8825_eject_jack(struct nau8825 *nau8825)
634 {
635 struct snd_soc_dapm_context *dapm = nau8825->dapm;
636 struct regmap *regmap = nau8825->regmap;
637
638 snd_soc_dapm_disable_pin(dapm, "SAR");
639 snd_soc_dapm_disable_pin(dapm, "MICBIAS");
640 /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */
641 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
642 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0);
643 /* ground HPL/HPR, MICGRND1/2 */
644 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 0xf, 0xf);
645
646 snd_soc_dapm_sync(dapm);
647 }
648
649 static int nau8825_button_decode(int value)
650 {
651 int buttons = 0;
652
653 /* The chip supports up to 8 buttons, but ALSA defines only 6 buttons */
654 if (value & BIT(0))
655 buttons |= SND_JACK_BTN_0;
656 if (value & BIT(1))
657 buttons |= SND_JACK_BTN_1;
658 if (value & BIT(2))
659 buttons |= SND_JACK_BTN_2;
660 if (value & BIT(3))
661 buttons |= SND_JACK_BTN_3;
662 if (value & BIT(4))
663 buttons |= SND_JACK_BTN_4;
664 if (value & BIT(5))
665 buttons |= SND_JACK_BTN_5;
666
667 return buttons;
668 }
669
670 static int nau8825_jack_insert(struct nau8825 *nau8825)
671 {
672 struct regmap *regmap = nau8825->regmap;
673 struct snd_soc_dapm_context *dapm = nau8825->dapm;
674 int jack_status_reg, mic_detected;
675 int type = 0;
676
677 regmap_read(regmap, NAU8825_REG_GENERAL_STATUS, &jack_status_reg);
678 mic_detected = (jack_status_reg >> 10) & 3;
679
680 switch (mic_detected) {
681 case 0:
682 /* no mic */
683 type = SND_JACK_HEADPHONE;
684 break;
685 case 1:
686 dev_dbg(nau8825->dev, "OMTP (micgnd1) mic connected\n");
687 type = SND_JACK_HEADSET;
688
689 /* Unground MICGND1 */
690 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
691 1 << 2);
692 /* Attach 2kOhm Resistor from MICBIAS to MICGND1 */
693 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
694 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
695 NAU8825_MICBIAS_JKR2);
696 /* Attach SARADC to MICGND1 */
697 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
698 NAU8825_SAR_INPUT_MASK,
699 NAU8825_SAR_INPUT_JKR2);
700
701 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
702 snd_soc_dapm_force_enable_pin(dapm, "SAR");
703 snd_soc_dapm_sync(dapm);
704 break;
705 case 2:
706 case 3:
707 dev_dbg(nau8825->dev, "CTIA (micgnd2) mic connected\n");
708 type = SND_JACK_HEADSET;
709
710 /* Unground MICGND2 */
711 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
712 2 << 2);
713 /* Attach 2kOhm Resistor from MICBIAS to MICGND2 */
714 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
715 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
716 NAU8825_MICBIAS_JKSLV);
717 /* Attach SARADC to MICGND2 */
718 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
719 NAU8825_SAR_INPUT_MASK,
720 NAU8825_SAR_INPUT_JKSLV);
721
722 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
723 snd_soc_dapm_force_enable_pin(dapm, "SAR");
724 snd_soc_dapm_sync(dapm);
725 break;
726 }
727
728 /* Leaving HPOL/R grounded after jack insert by default. They will be
729 * ungrounded as part of the widget power up sequence at the beginning
730 * of playback to reduce pop.
731 */
732 return type;
733 }
734
735 #define NAU8825_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \
736 SND_JACK_BTN_2 | SND_JACK_BTN_3)
737
738 static irqreturn_t nau8825_interrupt(int irq, void *data)
739 {
740 struct nau8825 *nau8825 = (struct nau8825 *)data;
741 struct regmap *regmap = nau8825->regmap;
742 int active_irq, clear_irq = 0, event = 0, event_mask = 0;
743
744 if (regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq)) {
745 dev_err(nau8825->dev, "failed to read irq status\n");
746 return IRQ_NONE;
747 }
748
749 if ((active_irq & NAU8825_JACK_EJECTION_IRQ_MASK) ==
750 NAU8825_JACK_EJECTION_DETECTED) {
751
752 nau8825_eject_jack(nau8825);
753 event_mask |= SND_JACK_HEADSET;
754 clear_irq = NAU8825_JACK_EJECTION_IRQ_MASK;
755 } else if (active_irq & NAU8825_KEY_SHORT_PRESS_IRQ) {
756 int key_status;
757
758 regmap_read(regmap, NAU8825_REG_INT_CLR_KEY_STATUS,
759 &key_status);
760
761 /* upper 8 bits of the register are for short pressed keys,
762 * lower 8 bits - for long pressed buttons
763 */
764 nau8825->button_pressed = nau8825_button_decode(
765 key_status >> 8);
766
767 event |= nau8825->button_pressed;
768 event_mask |= NAU8825_BUTTONS;
769 clear_irq = NAU8825_KEY_SHORT_PRESS_IRQ;
770 } else if (active_irq & NAU8825_KEY_RELEASE_IRQ) {
771 event_mask = NAU8825_BUTTONS;
772 clear_irq = NAU8825_KEY_RELEASE_IRQ;
773 } else if (active_irq & NAU8825_HEADSET_COMPLETION_IRQ) {
774 if (nau8825_is_jack_inserted(regmap)) {
775 event |= nau8825_jack_insert(nau8825);
776 } else {
777 dev_warn(nau8825->dev, "Headset completion IRQ fired but no headset connected\n");
778 nau8825_eject_jack(nau8825);
779 }
780
781 event_mask |= SND_JACK_HEADSET;
782 clear_irq = NAU8825_HEADSET_COMPLETION_IRQ;
783 }
784
785 if (!clear_irq)
786 clear_irq = active_irq;
787 /* clears the rightmost interruption */
788 regmap_write(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
789
790 if (event_mask)
791 snd_soc_jack_report(nau8825->jack, event, event_mask);
792
793 return IRQ_HANDLED;
794 }
795
796 static void nau8825_setup_buttons(struct nau8825 *nau8825)
797 {
798 struct regmap *regmap = nau8825->regmap;
799
800 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
801 NAU8825_SAR_TRACKING_GAIN_MASK,
802 nau8825->sar_voltage << NAU8825_SAR_TRACKING_GAIN_SFT);
803 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
804 NAU8825_SAR_COMPARE_TIME_MASK,
805 nau8825->sar_compare_time << NAU8825_SAR_COMPARE_TIME_SFT);
806 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
807 NAU8825_SAR_SAMPLING_TIME_MASK,
808 nau8825->sar_sampling_time << NAU8825_SAR_SAMPLING_TIME_SFT);
809
810 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
811 NAU8825_KEYDET_LEVELS_NR_MASK,
812 (nau8825->sar_threshold_num - 1) << NAU8825_KEYDET_LEVELS_NR_SFT);
813 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
814 NAU8825_KEYDET_HYSTERESIS_MASK,
815 nau8825->sar_hysteresis << NAU8825_KEYDET_HYSTERESIS_SFT);
816 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
817 NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK,
818 nau8825->key_debounce << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT);
819
820 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_1,
821 (nau8825->sar_threshold[0] << 8) | nau8825->sar_threshold[1]);
822 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_2,
823 (nau8825->sar_threshold[2] << 8) | nau8825->sar_threshold[3]);
824 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_3,
825 (nau8825->sar_threshold[4] << 8) | nau8825->sar_threshold[5]);
826 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_4,
827 (nau8825->sar_threshold[6] << 8) | nau8825->sar_threshold[7]);
828
829 /* Enable short press and release interruptions */
830 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
831 NAU8825_IRQ_KEY_SHORT_PRESS_EN | NAU8825_IRQ_KEY_RELEASE_EN,
832 0);
833 }
834
835 static void nau8825_init_regs(struct nau8825 *nau8825)
836 {
837 struct regmap *regmap = nau8825->regmap;
838
839 /* Latch IIC LSB value */
840 regmap_write(regmap, NAU8825_REG_IIC_ADDR_SET, 0x0001);
841 /* Enable Bias/Vmid */
842 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
843 NAU8825_BIAS_VMID, NAU8825_BIAS_VMID);
844 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
845 NAU8825_GLOBAL_BIAS_EN, NAU8825_GLOBAL_BIAS_EN);
846
847 /* VMID Tieoff */
848 regmap_update_bits(regmap, NAU8825_REG_BIAS_ADJ,
849 NAU8825_BIAS_VMID_SEL_MASK,
850 nau8825->vref_impedance << NAU8825_BIAS_VMID_SEL_SFT);
851 /* Disable Boost Driver, Automatic Short circuit protection enable */
852 regmap_update_bits(regmap, NAU8825_REG_BOOST,
853 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
854 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN,
855 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
856 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN);
857
858 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
859 NAU8825_JKDET_OUTPUT_EN,
860 nau8825->jkdet_enable ? 0 : NAU8825_JKDET_OUTPUT_EN);
861 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
862 NAU8825_JKDET_PULL_EN,
863 nau8825->jkdet_pull_enable ? 0 : NAU8825_JKDET_PULL_EN);
864 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
865 NAU8825_JKDET_PULL_UP,
866 nau8825->jkdet_pull_up ? NAU8825_JKDET_PULL_UP : 0);
867 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
868 NAU8825_JACK_POLARITY,
869 /* jkdet_polarity - 1 is for active-low */
870 nau8825->jkdet_polarity ? 0 : NAU8825_JACK_POLARITY);
871
872 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
873 NAU8825_JACK_INSERT_DEBOUNCE_MASK,
874 nau8825->jack_insert_debounce << NAU8825_JACK_INSERT_DEBOUNCE_SFT);
875 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
876 NAU8825_JACK_EJECT_DEBOUNCE_MASK,
877 nau8825->jack_eject_debounce << NAU8825_JACK_EJECT_DEBOUNCE_SFT);
878
879 /* Mask unneeded IRQs: 1 - disable, 0 - enable */
880 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 0x7ff, 0x7ff);
881
882 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
883 NAU8825_MICBIAS_VOLTAGE_MASK, nau8825->micbias_voltage);
884
885 if (nau8825->sar_threshold_num)
886 nau8825_setup_buttons(nau8825);
887
888 /* Default oversampling/decimations settings are unusable
889 * (audible hiss). Set it to something better.
890 */
891 regmap_update_bits(regmap, NAU8825_REG_ADC_RATE,
892 NAU8825_ADC_SYNC_DOWN_MASK, NAU8825_ADC_SYNC_DOWN_128);
893 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
894 NAU8825_DAC_OVERSAMPLE_MASK, NAU8825_DAC_OVERSAMPLE_128);
895 /* Disable DACR/L power */
896 regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP,
897 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
898 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
899 /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input
900 * signal to avoid any glitches due to power up transients in both
901 * the analog and digital DAC circuit.
902 */
903 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
904 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
905 /* CICCLP off */
906 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
907 NAU8825_DAC_CLIP_OFF, NAU8825_DAC_CLIP_OFF);
908
909 /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */
910 regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_2,
911 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
912 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB,
913 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
914 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB);
915 /* Class G timer 64ms */
916 regmap_update_bits(regmap, NAU8825_REG_CLASSG_CTRL,
917 NAU8825_CLASSG_TIMER_MASK,
918 0x20 << NAU8825_CLASSG_TIMER_SFT);
919 /* DAC clock delay 2ns, VREF */
920 regmap_update_bits(regmap, NAU8825_REG_RDAC,
921 NAU8825_RDAC_CLK_DELAY_MASK | NAU8825_RDAC_VREF_MASK,
922 (0x2 << NAU8825_RDAC_CLK_DELAY_SFT) |
923 (0x3 << NAU8825_RDAC_VREF_SFT));
924 }
925
926 static const struct regmap_config nau8825_regmap_config = {
927 .val_bits = 16,
928 .reg_bits = 16,
929
930 .max_register = NAU8825_REG_MAX,
931 .readable_reg = nau8825_readable_reg,
932 .writeable_reg = nau8825_writeable_reg,
933 .volatile_reg = nau8825_volatile_reg,
934
935 .cache_type = REGCACHE_RBTREE,
936 .reg_defaults = nau8825_reg_defaults,
937 .num_reg_defaults = ARRAY_SIZE(nau8825_reg_defaults),
938 };
939
940 static int nau8825_codec_probe(struct snd_soc_codec *codec)
941 {
942 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
943 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
944
945 nau8825->dapm = dapm;
946
947 /* The interrupt clock is gated by x1[10:8],
948 * one of them needs to be enabled all the time for
949 * interrupts to happen.
950 */
951 snd_soc_dapm_force_enable_pin(dapm, "DDACR");
952 snd_soc_dapm_sync(dapm);
953
954 /* Unmask interruptions. Handler uses dapm object so we can enable
955 * interruptions only after dapm is fully initialized.
956 */
957 regmap_write(nau8825->regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 0);
958 nau8825_restart_jack_detection(nau8825->regmap);
959
960 return 0;
961 }
962
963 /**
964 * nau8825_calc_fll_param - Calculate FLL parameters.
965 * @fll_in: external clock provided to codec.
966 * @fs: sampling rate.
967 * @fll_param: Pointer to structure of FLL parameters.
968 *
969 * Calculate FLL parameters to configure codec.
970 *
971 * Returns 0 for success or negative error code.
972 */
973 static int nau8825_calc_fll_param(unsigned int fll_in, unsigned int fs,
974 struct nau8825_fll *fll_param)
975 {
976 u64 fvco;
977 unsigned int fref, i;
978
979 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
980 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
981 * FREF = freq_in / NAU8825_FLL_REF_DIV_MASK
982 */
983 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
984 fref = fll_in / fll_pre_scalar[i].param;
985 if (fref <= NAU_FREF_MAX)
986 break;
987 }
988 if (i == ARRAY_SIZE(fll_pre_scalar))
989 return -EINVAL;
990 fll_param->clk_ref_div = fll_pre_scalar[i].val;
991
992 /* Choose the FLL ratio based on FREF */
993 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
994 if (fref >= fll_ratio[i].param)
995 break;
996 }
997 if (i == ARRAY_SIZE(fll_ratio))
998 return -EINVAL;
999 fll_param->ratio = fll_ratio[i].val;
1000
1001 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
1002 * FDCO must be within the 90MHz - 100MHz or the FFL cannot be
1003 * guaranteed across the full range of operation.
1004 * FDCO = freq_out * 2 * mclk_src_scaling
1005 */
1006 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
1007 fvco = 256 * fs * 2 * mclk_src_scaling[i].param;
1008 if (NAU_FVCO_MIN < fvco && fvco < NAU_FVCO_MAX)
1009 break;
1010 }
1011 if (i == ARRAY_SIZE(mclk_src_scaling))
1012 return -EINVAL;
1013 fll_param->mclk_src = mclk_src_scaling[i].val;
1014
1015 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
1016 * input based on FDCO, FREF and FLL ratio.
1017 */
1018 fvco = div_u64(fvco << 16, fref * fll_param->ratio);
1019 fll_param->fll_int = (fvco >> 16) & 0x3FF;
1020 fll_param->fll_frac = fvco & 0xFFFF;
1021 return 0;
1022 }
1023
1024 static void nau8825_fll_apply(struct nau8825 *nau8825,
1025 struct nau8825_fll *fll_param)
1026 {
1027 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
1028 NAU8825_CLK_MCLK_SRC_MASK, fll_param->mclk_src);
1029 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
1030 NAU8825_FLL_RATIO_MASK, fll_param->ratio);
1031 /* FLL 16-bit fractional input */
1032 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, fll_param->fll_frac);
1033 /* FLL 10-bit integer input */
1034 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL3,
1035 NAU8825_FLL_INTEGER_MASK, fll_param->fll_int);
1036 /* FLL pre-scaler */
1037 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL4,
1038 NAU8825_FLL_REF_DIV_MASK, fll_param->clk_ref_div);
1039 /* select divided VCO input */
1040 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
1041 NAU8825_FLL_FILTER_SW_MASK, 0x0000);
1042 /* FLL sigma delta modulator enable */
1043 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
1044 NAU8825_SDM_EN_MASK, NAU8825_SDM_EN);
1045 }
1046
1047 /* freq_out must be 256*Fs in order to achieve the best performance */
1048 static int nau8825_set_pll(struct snd_soc_codec *codec, int pll_id, int source,
1049 unsigned int freq_in, unsigned int freq_out)
1050 {
1051 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1052 struct nau8825_fll fll_param;
1053 int ret, fs;
1054
1055 fs = freq_out / 256;
1056 ret = nau8825_calc_fll_param(freq_in, fs, &fll_param);
1057 if (ret < 0) {
1058 dev_err(codec->dev, "Unsupported input clock %d\n", freq_in);
1059 return ret;
1060 }
1061 dev_dbg(codec->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
1062 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
1063 fll_param.fll_int, fll_param.clk_ref_div);
1064
1065 nau8825_fll_apply(nau8825, &fll_param);
1066 mdelay(2);
1067 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
1068 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
1069 return 0;
1070 }
1071
1072 static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
1073 unsigned int freq)
1074 {
1075 struct regmap *regmap = nau8825->regmap;
1076 int ret;
1077
1078 switch (clk_id) {
1079 case NAU8825_CLK_MCLK:
1080 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
1081 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK);
1082 regmap_update_bits(regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN, 0);
1083
1084 /* We selected MCLK source but the clock itself managed externally */
1085 if (!nau8825->mclk)
1086 break;
1087
1088 if (!nau8825->mclk_freq) {
1089 ret = clk_prepare_enable(nau8825->mclk);
1090 if (ret) {
1091 dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
1092 return ret;
1093 }
1094 }
1095
1096 if (nau8825->mclk_freq != freq) {
1097 nau8825->mclk_freq = freq;
1098
1099 freq = clk_round_rate(nau8825->mclk, freq);
1100 ret = clk_set_rate(nau8825->mclk, freq);
1101 if (ret) {
1102 dev_err(nau8825->dev, "Unable to set mclk rate\n");
1103 return ret;
1104 }
1105 }
1106
1107 break;
1108 case NAU8825_CLK_INTERNAL:
1109 regmap_update_bits(regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN,
1110 NAU8825_DCO_EN);
1111 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
1112 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
1113
1114 if (nau8825->mclk_freq) {
1115 clk_disable_unprepare(nau8825->mclk);
1116 nau8825->mclk_freq = 0;
1117 }
1118
1119 break;
1120 default:
1121 dev_err(nau8825->dev, "Invalid clock id (%d)\n", clk_id);
1122 return -EINVAL;
1123 }
1124
1125 dev_dbg(nau8825->dev, "Sysclk is %dHz and clock id is %d\n", freq,
1126 clk_id);
1127 return 0;
1128 }
1129
1130 static int nau8825_set_sysclk(struct snd_soc_codec *codec, int clk_id,
1131 int source, unsigned int freq, int dir)
1132 {
1133 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1134
1135 return nau8825_configure_sysclk(nau8825, clk_id, freq);
1136 }
1137
1138 static int nau8825_set_bias_level(struct snd_soc_codec *codec,
1139 enum snd_soc_bias_level level)
1140 {
1141 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1142 int ret;
1143
1144 switch (level) {
1145 case SND_SOC_BIAS_ON:
1146 break;
1147
1148 case SND_SOC_BIAS_PREPARE:
1149 break;
1150
1151 case SND_SOC_BIAS_STANDBY:
1152 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
1153 if (nau8825->mclk_freq) {
1154 ret = clk_prepare_enable(nau8825->mclk);
1155 if (ret) {
1156 dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
1157 return ret;
1158 }
1159 }
1160 }
1161 break;
1162
1163 case SND_SOC_BIAS_OFF:
1164 if (nau8825->mclk_freq)
1165 clk_disable_unprepare(nau8825->mclk);
1166 break;
1167 }
1168 return 0;
1169 }
1170
1171 #ifdef CONFIG_PM
1172 static int nau8825_suspend(struct snd_soc_codec *codec)
1173 {
1174 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1175
1176 disable_irq(nau8825->irq);
1177 regcache_cache_only(nau8825->regmap, true);
1178 regcache_mark_dirty(nau8825->regmap);
1179
1180 return 0;
1181 }
1182
1183 static int nau8825_resume(struct snd_soc_codec *codec)
1184 {
1185 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1186
1187 /* The chip may lose power and reset in S3. regcache_sync restores
1188 * register values including configurations for sysclk, irq, and
1189 * jack/button detection.
1190 */
1191 regcache_cache_only(nau8825->regmap, false);
1192 regcache_sync(nau8825->regmap);
1193
1194 /* Check the jack plug status directly. If the headset is unplugged
1195 * during S3 when the chip has no power, there will be no jack
1196 * detection irq even after the nau8825_restart_jack_detection below,
1197 * because the chip just thinks no headset has ever been plugged in.
1198 */
1199 if (!nau8825_is_jack_inserted(nau8825->regmap)) {
1200 nau8825_eject_jack(nau8825);
1201 snd_soc_jack_report(nau8825->jack, 0, SND_JACK_HEADSET);
1202 }
1203
1204 enable_irq(nau8825->irq);
1205
1206 /* Run jack detection to check the type (OMTP or CTIA) of the headset
1207 * if there is one. This handles the case where a different type of
1208 * headset is plugged in during S3. This triggers an IRQ iff a headset
1209 * is already plugged in.
1210 */
1211 nau8825_restart_jack_detection(nau8825->regmap);
1212
1213 return 0;
1214 }
1215 #else
1216 #define nau8825_suspend NULL
1217 #define nau8825_resume NULL
1218 #endif
1219
1220 static struct snd_soc_codec_driver nau8825_codec_driver = {
1221 .probe = nau8825_codec_probe,
1222 .set_sysclk = nau8825_set_sysclk,
1223 .set_pll = nau8825_set_pll,
1224 .set_bias_level = nau8825_set_bias_level,
1225 .suspend_bias_off = true,
1226 .suspend = nau8825_suspend,
1227 .resume = nau8825_resume,
1228
1229 .controls = nau8825_controls,
1230 .num_controls = ARRAY_SIZE(nau8825_controls),
1231 .dapm_widgets = nau8825_dapm_widgets,
1232 .num_dapm_widgets = ARRAY_SIZE(nau8825_dapm_widgets),
1233 .dapm_routes = nau8825_dapm_routes,
1234 .num_dapm_routes = ARRAY_SIZE(nau8825_dapm_routes),
1235 };
1236
1237 static void nau8825_reset_chip(struct regmap *regmap)
1238 {
1239 regmap_write(regmap, NAU8825_REG_RESET, 0x00);
1240 regmap_write(regmap, NAU8825_REG_RESET, 0x00);
1241 }
1242
1243 static void nau8825_print_device_properties(struct nau8825 *nau8825)
1244 {
1245 int i;
1246 struct device *dev = nau8825->dev;
1247
1248 dev_dbg(dev, "jkdet-enable: %d\n", nau8825->jkdet_enable);
1249 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8825->jkdet_pull_enable);
1250 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8825->jkdet_pull_up);
1251 dev_dbg(dev, "jkdet-polarity: %d\n", nau8825->jkdet_polarity);
1252 dev_dbg(dev, "micbias-voltage: %d\n", nau8825->micbias_voltage);
1253 dev_dbg(dev, "vref-impedance: %d\n", nau8825->vref_impedance);
1254
1255 dev_dbg(dev, "sar-threshold-num: %d\n", nau8825->sar_threshold_num);
1256 for (i = 0; i < nau8825->sar_threshold_num; i++)
1257 dev_dbg(dev, "sar-threshold[%d]=%d\n", i,
1258 nau8825->sar_threshold[i]);
1259
1260 dev_dbg(dev, "sar-hysteresis: %d\n", nau8825->sar_hysteresis);
1261 dev_dbg(dev, "sar-voltage: %d\n", nau8825->sar_voltage);
1262 dev_dbg(dev, "sar-compare-time: %d\n", nau8825->sar_compare_time);
1263 dev_dbg(dev, "sar-sampling-time: %d\n", nau8825->sar_sampling_time);
1264 dev_dbg(dev, "short-key-debounce: %d\n", nau8825->key_debounce);
1265 dev_dbg(dev, "jack-insert-debounce: %d\n",
1266 nau8825->jack_insert_debounce);
1267 dev_dbg(dev, "jack-eject-debounce: %d\n",
1268 nau8825->jack_eject_debounce);
1269 }
1270
1271 static int nau8825_read_device_properties(struct device *dev,
1272 struct nau8825 *nau8825) {
1273
1274 nau8825->jkdet_enable = device_property_read_bool(dev,
1275 "nuvoton,jkdet-enable");
1276 nau8825->jkdet_pull_enable = device_property_read_bool(dev,
1277 "nuvoton,jkdet-pull-enable");
1278 nau8825->jkdet_pull_up = device_property_read_bool(dev,
1279 "nuvoton,jkdet-pull-up");
1280 device_property_read_u32(dev, "nuvoton,jkdet-polarity",
1281 &nau8825->jkdet_polarity);
1282 device_property_read_u32(dev, "nuvoton,micbias-voltage",
1283 &nau8825->micbias_voltage);
1284 device_property_read_u32(dev, "nuvoton,vref-impedance",
1285 &nau8825->vref_impedance);
1286 device_property_read_u32(dev, "nuvoton,sar-threshold-num",
1287 &nau8825->sar_threshold_num);
1288 device_property_read_u32_array(dev, "nuvoton,sar-threshold",
1289 nau8825->sar_threshold, nau8825->sar_threshold_num);
1290 device_property_read_u32(dev, "nuvoton,sar-hysteresis",
1291 &nau8825->sar_hysteresis);
1292 device_property_read_u32(dev, "nuvoton,sar-voltage",
1293 &nau8825->sar_voltage);
1294 device_property_read_u32(dev, "nuvoton,sar-compare-time",
1295 &nau8825->sar_compare_time);
1296 device_property_read_u32(dev, "nuvoton,sar-sampling-time",
1297 &nau8825->sar_sampling_time);
1298 device_property_read_u32(dev, "nuvoton,short-key-debounce",
1299 &nau8825->key_debounce);
1300 device_property_read_u32(dev, "nuvoton,jack-insert-debounce",
1301 &nau8825->jack_insert_debounce);
1302 device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
1303 &nau8825->jack_eject_debounce);
1304
1305 nau8825->mclk = devm_clk_get(dev, "mclk");
1306 if (PTR_ERR(nau8825->mclk) == -EPROBE_DEFER) {
1307 return -EPROBE_DEFER;
1308 } else if (PTR_ERR(nau8825->mclk) == -ENOENT) {
1309 /* The MCLK is managed externally or not used at all */
1310 nau8825->mclk = NULL;
1311 dev_info(dev, "No 'mclk' clock found, assume MCLK is managed externally");
1312 } else if (IS_ERR(nau8825->mclk)) {
1313 return -EINVAL;
1314 }
1315
1316 return 0;
1317 }
1318
1319 static int nau8825_setup_irq(struct nau8825 *nau8825)
1320 {
1321 struct regmap *regmap = nau8825->regmap;
1322 int ret;
1323
1324 /* IRQ Output Enable */
1325 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1326 NAU8825_IRQ_OUTPUT_EN, NAU8825_IRQ_OUTPUT_EN);
1327
1328 /* Enable internal VCO needed for interruptions */
1329 nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
1330
1331 /* Enable DDACR needed for interrupts
1332 * It is the same as force_enable_pin("DDACR") we do later
1333 */
1334 regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
1335 NAU8825_ENABLE_DACR, NAU8825_ENABLE_DACR);
1336
1337 ret = devm_request_threaded_irq(nau8825->dev, nau8825->irq, NULL,
1338 nau8825_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1339 "nau8825", nau8825);
1340
1341 if (ret) {
1342 dev_err(nau8825->dev, "Cannot request irq %d (%d)\n",
1343 nau8825->irq, ret);
1344 return ret;
1345 }
1346
1347 return 0;
1348 }
1349
1350 static int nau8825_i2c_probe(struct i2c_client *i2c,
1351 const struct i2c_device_id *id)
1352 {
1353 struct device *dev = &i2c->dev;
1354 struct nau8825 *nau8825 = dev_get_platdata(&i2c->dev);
1355 int ret, value;
1356
1357 if (!nau8825) {
1358 nau8825 = devm_kzalloc(dev, sizeof(*nau8825), GFP_KERNEL);
1359 if (!nau8825)
1360 return -ENOMEM;
1361 ret = nau8825_read_device_properties(dev, nau8825);
1362 if (ret)
1363 return ret;
1364 }
1365
1366 i2c_set_clientdata(i2c, nau8825);
1367
1368 nau8825->regmap = devm_regmap_init_i2c(i2c, &nau8825_regmap_config);
1369 if (IS_ERR(nau8825->regmap))
1370 return PTR_ERR(nau8825->regmap);
1371 nau8825->dev = dev;
1372 nau8825->irq = i2c->irq;
1373
1374 nau8825_print_device_properties(nau8825);
1375
1376 nau8825_reset_chip(nau8825->regmap);
1377 ret = regmap_read(nau8825->regmap, NAU8825_REG_I2C_DEVICE_ID, &value);
1378 if (ret < 0) {
1379 dev_err(dev, "Failed to read device id from the NAU8825: %d\n",
1380 ret);
1381 return ret;
1382 }
1383 if ((value & NAU8825_SOFTWARE_ID_MASK) !=
1384 NAU8825_SOFTWARE_ID_NAU8825) {
1385 dev_err(dev, "Not a NAU8825 chip\n");
1386 return -ENODEV;
1387 }
1388
1389 nau8825_init_regs(nau8825);
1390
1391 if (i2c->irq)
1392 nau8825_setup_irq(nau8825);
1393
1394 return snd_soc_register_codec(&i2c->dev, &nau8825_codec_driver,
1395 &nau8825_dai, 1);
1396 }
1397
1398 static int nau8825_i2c_remove(struct i2c_client *client)
1399 {
1400 snd_soc_unregister_codec(&client->dev);
1401 return 0;
1402 }
1403
1404 static const struct i2c_device_id nau8825_i2c_ids[] = {
1405 { "nau8825", 0 },
1406 { }
1407 };
1408
1409 #ifdef CONFIG_OF
1410 static const struct of_device_id nau8825_of_ids[] = {
1411 { .compatible = "nuvoton,nau8825", },
1412 {}
1413 };
1414 MODULE_DEVICE_TABLE(of, nau8825_of_ids);
1415 #endif
1416
1417 #ifdef CONFIG_ACPI
1418 static const struct acpi_device_id nau8825_acpi_match[] = {
1419 { "10508825", 0 },
1420 {},
1421 };
1422 MODULE_DEVICE_TABLE(acpi, nau8825_acpi_match);
1423 #endif
1424
1425 static struct i2c_driver nau8825_driver = {
1426 .driver = {
1427 .name = "nau8825",
1428 .of_match_table = of_match_ptr(nau8825_of_ids),
1429 .acpi_match_table = ACPI_PTR(nau8825_acpi_match),
1430 },
1431 .probe = nau8825_i2c_probe,
1432 .remove = nau8825_i2c_remove,
1433 .id_table = nau8825_i2c_ids,
1434 };
1435 module_i2c_driver(nau8825_driver);
1436
1437 MODULE_DESCRIPTION("ASoC nau8825 driver");
1438 MODULE_AUTHOR("Anatol Pomozov <anatol@chromium.org>");
1439 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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