drm/amdgpu/cik: move sdma tiling config setup into sdma code

Split sdma and gfx programming.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 7ba34522c833ac4ab2c16747ab55b1d707b69285..675f34916aabf13f150a56a62519e34a81d73336 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -393,6 +393,9 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
                cik_srbm_select(adev, 0, 0, 0, 0);
                mutex_unlock(&adev->srbm_mutex);
 
+               WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
+                      adev->gfx.config.gb_addr_config & 0x70);
+
                WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
                WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 
@@ -1065,6 +1068,8 @@ static void cik_sdma_print_status(void *handle)
                         i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
                dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
                         i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
+               dev_info(adev->dev, "  SDMA%d_TILING_CONFIG=0x%08X\n",
+                        i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i]));
                mutex_lock(&adev->srbm_mutex);
                for (j = 0; j < 16; j++) {
                        cik_srbm_select(adev, 0, 0, 0, j);

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 6ae7b9d3c748c05a65257d677feb8c4e80914b32..08c276c2080d951744e4c7949810e17b7f5ba84e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -1721,8 +1721,6 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
        WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
        WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
        WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
-       WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, adev->gfx.config.gb_addr_config & 0x70);
-       WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, adev->gfx.config.gb_addr_config & 0x70);
        WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
        WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
        WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
@@ -4602,10 +4600,6 @@ static void gfx_v7_0_print_status(void *handle)
                 RREG32(mmHDP_ADDR_CONFIG));
        dev_info(adev->dev, "  DMIF_ADDR_CALC=0x%08X\n",
                 RREG32(mmDMIF_ADDR_CALC));
-       dev_info(adev->dev, "  SDMA0_TILING_CONFIG=0x%08X\n",
-                RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET));
-       dev_info(adev->dev, "  SDMA1_TILING_CONFIG=0x%08X\n",
-                RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET));
        dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
                 RREG32(mmUVD_UDEC_ADDR_CONFIG));
        dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",