Merge branches 'misc' and 'misc-rc6' into for-linus

diff --cc Documentation/devicetree/bindings/arm/l2c2x0.txt
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- - arm,shared-override : The default behavior of the pl310 cache controller with
-   respect to the shareable attribute is to transform "normal memory
-   non-cacheable transactions" into "cacheable no allocate" (for reads) or
-   "write through no write allocate" (for writes).
 +* ARM L2 Cache Controller
 +
 +ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/PL220/
 +PL310 and variants) based level 2 cache controller. All these various implementations
 +of the L2 cache controller have compatible programming models (Note 1).
 +Some of the properties that are just prefixed "cache-*" are taken from section
 +3.7.3 of the ePAPR v1.1 specification which can be found at:
 +https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf
 +
 +The ARM L2 cache representation in the device tree should be done as follows:
 +
 +Required properties:
 +
 +- compatible : should be one of:
 +  "arm,pl310-cache"
 +  "arm,l220-cache"
 +  "arm,l210-cache"
 +  "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
 +  "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
 +     offset needs to be added to the address before passing down to the L2
 +     cache controller
 +  "marvell,aurora-system-cache": Marvell Controller designed to be
 +     compatible with the ARM one, with system cache mode (meaning
 +     maintenance operations on L1 are broadcasted to the L2 and L2
 +     performs the same operation).
 +  "marvell,aurora-outer-cache": Marvell Controller designed to be
 +     compatible with the ARM one with outer cache mode.
 +  "marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible
 +     with arm,pl310-cache controller.
 +- cache-unified : Specifies the cache is a unified cache.
 +- cache-level : Should be set to 2 for a level 2 cache.
 +- reg : Physical base address and size of cache controller's memory mapped
 +  registers.
 +
 +Optional properties:
 +
 +- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of
 +  read, write and setup latencies. Minimum valid values are 1. Controllers
 +  without setup latency control should use a value of 0.
 +- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of
 +  read, write and setup latencies. Controllers without setup latency control
 +  should use 0. Controllers without separate read and write Tag RAM latency
 +  values should only use the first cell.
 +- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
 +- arm,filter-ranges : <start length> Starting address and length of window to
 +  filter. Addresses in the filter window are directed to the M1 port. Other
 +  addresses will go to the M0 port.
 +- arm,io-coherent : indicates that the system is operating in an hardware
 +  I/O coherent mode. Valid only when the arm,pl310-cache compatible
 +  string is used.
 +- interrupts : 1 combined interrupt.
 +- cache-size : specifies the size in bytes of the cache
 +- cache-sets : specifies the number of associativity sets of the cache
 +- cache-block-size : specifies the size in bytes of a cache block
 +- cache-line-size : specifies the size in bytes of a line in the cache,
 +  if this is not specified, the line size is assumed to be equal to the
 +  cache block size
 +- cache-id-part: cache id part number to be used if it is not present
 +  on hardware
 +- wt-override: If present then L2 is forced to Write through mode
 +- arm,double-linefill : Override double linefill enable setting. Enable if
 +  non-zero, disable if zero.
 +- arm,double-linefill-incr : Override double linefill on INCR read. Enable
 +  if non-zero, disable if zero.
 +- arm,double-linefill-wrap : Override double linefill on WRAP read. Enable
 +  if non-zero, disable if zero.
 +- arm,prefetch-drop : Override prefetch drop enable setting. Enable if non-zero,
 +  disable if zero.
 +- arm,prefetch-offset : Override prefetch offset value. Valid values are
 +  0-7, 15, 23, and 31.
++- arm,shared-override : The default behavior of the L220 or PL310 cache
++  controllers with respect to the shareable attribute is to transform "normal
++  memory non-cacheable transactions" into "cacheable no allocate" (for reads)
++  or "write through no write allocate" (for writes).
 +  On systems where this may cause DMA buffer corruption, this property must be
 +  specified to indicate that such transforms are precluded.
++- arm,parity-enable : enable parity checking on the L2 cache (L220 or PL310).
++- arm,parity-disable : disable parity checking on the L2 cache (L220 or PL310).
++- arm,outer-sync-disable : disable the outer sync operation on the L2 cache.
++  Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
++  will randomly hang unless outer sync operations are disabled.
 +- prefetch-data : Data prefetch. Value: <0> (forcibly disable), <1>
 +  (forcibly enable), property absent (retain settings set by firmware)
 +- prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable),
 +  <1> (forcibly enable), property absent (retain settings set by
 +  firmware)
 +
 +Example:
 +
 +L2: cache-controller {
 +        compatible = "arm,pl310-cache";
 +        reg = <0xfff12000 0x1000>;
 +        arm,data-latency = <1 1 1>;
 +        arm,tag-latency = <2 2 2>;
 +        arm,filter-ranges = <0x80000000 0x8000000>;
 +        cache-unified;
 +        cache-level = <2>;
 +      interrupts = <45>;
 +};
 +
 +Note 1: The description in this document doesn't apply to integrated L2
 +      cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
 +      integrated L2 controllers are assumed to be all preconfigured by
 +      early secure boot code. Thus no need to deal with their configuration
 +      in the kernel at all.

diff --cc arch/arm/Kconfig
Simple merge

diff --cc arch/arm/mm/proc-v7.S
Simple merge

diff --cc arch/arm64/Kconfig
Simple merge