Merge remote-tracking branch 'irqchip/irqchip/for-next'

diff --combined arch/arm64/Kconfig.platforms
index 567498e969ff0d3ef7ae00949793c3d3c86cb164,0b988f315c40d41e6bc48d51a861a8ce6c8b2b61..4e0e1071f2e8cd9190d009f6345df616208f1621
--- 1/arch/arm64/Kconfig.platforms
--- 2/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@@ -3,14 -3,12 +3,14 @@@ menu "Platform selection
  config ARCH_SUNXI
        bool "Allwinner sunxi 64-bit SoC Family"
        select GENERIC_IRQ_CHIP
 +      select PINCTRL
 +      select PINCTRL_SUN50I_A64
        help
          This enables support for Allwinner sunxi based SoCs like the A64.
  
  config ARCH_ALPINE
        bool "Annapurna Labs Alpine platform"
 -      select ALPINE_MSI
 +      select ALPINE_MSI if PCI
        help
          This enables support for the Annapurna Labs Alpine
          Soc family.
@@@ -57,7 -55,6 +57,7 @@@ config ARCH_EXYNO
  
  config ARCH_LAYERSCAPE
        bool "ARMv8 based Freescale Layerscape SoC family"
 +      select EDAC_SUPPORT
        help
          This enables support for the Freescale Layerscape SoC family.
  
@@@ -69,7 -66,7 +69,7 @@@ config ARCH_LG1
  config ARCH_HISI
        bool "Hisilicon SoC Family"
        select ARM_TIMER_SP804
 -      select HISILICON_IRQ_MBIGEN
 +      select HISILICON_IRQ_MBIGEN if PCI
        help
          This enables support for Hisilicon ARMv8 SoC family
  
@@@ -96,6 -93,7 +96,7 @@@ config ARCH_MVEB
        select ARMADA_CP110_SYSCON
        select ARMADA_37XX_CLK
        select MVEBU_ODMI
+       select MVEBU_PIC
        help
          This enables support for Marvell EBU familly, including:
           - Armada 3700 SoC Family
@@@ -162,9 -160,8 +163,9 @@@ config ARCH_TEGR
        select CLKSRC_MMIO
        select CLKSRC_OF
        select GENERIC_CLOCKEVENTS
 -      select HAVE_CLK
        select PINCTRL
 +      select PM
 +      select PM_GENERIC_DOMAINS
        select RESET_CONTROLLER
        help
          This enables support for the NVIDIA Tegra SoC family.

diff --combined drivers/irqchip/Makefile
index 92fa06e16a17ffe53eb35bb480055b3596821ffe,cecc4ca7181b67307c257a60f72f63a60ae9f0c6..83cec518cdf27dba0b5b78577204f196a8af57cc
--- 1/drivers/irqchip/Makefile
--- 2/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@@ -25,7 -25,7 +25,7 @@@ obj-$(CONFIG_ARCH_SUNXI)              += irq-sunxi-
  obj-$(CONFIG_ARCH_SPEAR3XX)           += spear-shirq.o
  obj-$(CONFIG_ARM_GIC)                 += irq-gic.o irq-gic-common.o
  obj-$(CONFIG_ARM_GIC_PM)              += irq-gic-pm.o
 -obj-$(CONFIG_REALVIEW_DT)             += irq-gic-realview.o
 +obj-$(CONFIG_ARCH_REALVIEW)           += irq-gic-realview.o
  obj-$(CONFIG_ARM_GIC_V2M)             += irq-gic-v2m.o
  obj-$(CONFIG_ARM_GIC_V3)              += irq-gic-v3.o irq-gic-common.o
  obj-$(CONFIG_ARM_GIC_V3_ITS)          += irq-gic-v3-its.o irq-gic-v3-its-pci-msi.o irq-gic-v3-its-platform-msi.o
@@@ -40,6 -40,7 +40,7 @@@ obj-$(CONFIG_I8259)                   += irq-i8259.
  obj-$(CONFIG_IMGPDC_IRQ)              += irq-imgpdc.o
  obj-$(CONFIG_IRQ_MIPS_CPU)            += irq-mips-cpu.o
  obj-$(CONFIG_SIRF_IRQ)                        += irq-sirfsoc.o
+ obj-$(CONFIG_JCORE_AIC)                       += irq-jcore-aic.o
  obj-$(CONFIG_RENESAS_INTC_IRQPIN)     += irq-renesas-intc-irqpin.o
  obj-$(CONFIG_RENESAS_IRQC)            += irq-renesas-irqc.o
  obj-$(CONFIG_VERSATILE_FPGA_IRQ)      += irq-versatile-fpga.o
@@@ -68,6 -69,7 +69,7 @@@ obj-$(CONFIG_INGENIC_IRQ)             += irq-ingen
  obj-$(CONFIG_IMX_GPCV2)                       += irq-imx-gpcv2.o
  obj-$(CONFIG_PIC32_EVIC)              += irq-pic32-evic.o
  obj-$(CONFIG_MVEBU_ODMI)              += irq-mvebu-odmi.o
+ obj-$(CONFIG_MVEBU_PIC)                       += irq-mvebu-pic.o
  obj-$(CONFIG_LS_SCFG_MSI)             += irq-ls-scfg-msi.o
  obj-$(CONFIG_EZNPS_GIC)                       += irq-eznps.o
  obj-$(CONFIG_ARCH_ASPEED)             += irq-aspeed-vic.o

diff --combined drivers/irqchip/irq-mips-gic.c
index 83f498393a7f0b5d82264cfd3cd340f0cf6c3c1f,a376fc6322637381dd37a07879ff61492e2a950e..a2c22a12d343f97417cc4d368913d21d992e5a99
--- 1/drivers/irqchip/irq-mips-gic.c
--- 2/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@@ -371,18 -371,13 +371,13 @@@ static void gic_handle_shared_int(bool 
        bitmap_and(pending, pending, intrmask, gic_shared_intrs);
        bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs);
  
-       intr = find_first_bit(pending, gic_shared_intrs);
-       while (intr != gic_shared_intrs) {
+       for_each_set_bit(intr, pending, gic_shared_intrs) {
                virq = irq_linear_revmap(gic_irq_domain,
                                         GIC_SHARED_TO_HWIRQ(intr));
                if (chained)
                        generic_handle_irq(virq);
                else
                        do_IRQ(virq);
- 
-               /* go to next pending bit */
-               bitmap_clear(pending, intr, 1);
-               intr = find_first_bit(pending, gic_shared_intrs);
        }
  }
  
@@@ -713,6 -708,9 +708,6 @@@ static int gic_shared_irq_domain_map(st
        unsigned long flags;
        int i;
  
 -      irq_set_chip_and_handler(virq, &gic_level_irq_controller,
 -                               handle_level_irq);
 -
        spin_lock_irqsave(&gic_lock, flags);
        gic_map_to_pin(intr, gic_cpu_pin);
        gic_map_to_vpe(intr, mips_cm_vp_id(vpe));
@@@ -729,10 -727,6 +724,10 @@@ static int gic_irq_domain_map(struct ir
  {
        if (GIC_HWIRQ_TO_LOCAL(hw) < GIC_NUM_LOCAL_INTRS)
                return gic_local_irq_domain_map(d, virq, hw);
 +
 +      irq_set_chip_and_handler(virq, &gic_level_irq_controller,
 +                               handle_level_irq);
 +
        return gic_shared_irq_domain_map(d, virq, hw, 0);
  }
  
@@@ -772,13 -766,11 +767,13 @@@ static int gic_irq_domain_alloc(struct 
                        hwirq = GIC_SHARED_TO_HWIRQ(base_hwirq + i);
  
                        ret = irq_domain_set_hwirq_and_chip(d, virq + i, hwirq,
 -                                                          &gic_edge_irq_controller,
 +                                                          &gic_level_irq_controller,
                                                            NULL);
                        if (ret)
                                goto error;
  
 +                      irq_set_handler(virq + i, handle_level_irq);
 +
                        ret = gic_shared_irq_domain_map(d, virq + i, hwirq, cpu);
                        if (ret)
                                goto error;
@@@ -893,17 -885,10 +888,17 @@@ void gic_dev_domain_free(struct irq_dom
        return;
  }
  
 +static void gic_dev_domain_activate(struct irq_domain *domain,
 +                                  struct irq_data *d)
 +{
 +      gic_shared_irq_domain_map(domain, d->irq, d->hwirq, 0);
 +}
 +
  static struct irq_domain_ops gic_dev_domain_ops = {
        .xlate = gic_dev_domain_xlate,
        .alloc = gic_dev_domain_alloc,
        .free = gic_dev_domain_free,
 +      .activate = gic_dev_domain_activate,
  };
  
  static int gic_ipi_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,