clk: h8300: Migrate to clk_hw based registration APIs
authorStephen Boyd <stephen.boyd@linaro.org>
Tue, 16 Aug 2016 22:37:57 +0000 (15:37 -0700)
committerStephen Boyd <sboyd@codeaurora.org>
Thu, 25 Aug 2016 00:37:10 +0000 (17:37 -0700)
Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers while registering clks in
these drivers, allowing us to move closer to a clear split of
consumer and provider clk APIs.

Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: <uclinux-h8-devel@lists.sourceforge.jp>
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/h8300/clk-div.c
drivers/clk/h8300/clk-h8s2678.c

index 4bf44a25d950daea6c0b526b90b890e5c361cda3..715b882205a8587a001a80017500b44f10a8f4df 100644 (file)
@@ -14,7 +14,7 @@ static DEFINE_SPINLOCK(clklock);
 static void __init h8300_div_clk_setup(struct device_node *node)
 {
        unsigned int num_parents;
-       struct clk *clk;
+       struct clk_hw *hw;
        const char *clk_name = node->name;
        const char *parent_name;
        void __iomem *divcr = NULL;
@@ -38,15 +38,15 @@ static void __init h8300_div_clk_setup(struct device_node *node)
 
        parent_name = of_clk_get_parent_name(node, 0);
        of_property_read_u32(node, "renesas,width", &width);
-       clk = clk_register_divider(NULL, clk_name, parent_name,
+       hw = clk_hw_register_divider(NULL, clk_name, parent_name,
                                   CLK_SET_RATE_GATE, divcr, offset, width,
                                   CLK_DIVIDER_POWER_OF_TWO, &clklock);
-       if (!IS_ERR(clk)) {
-               of_clk_add_provider(node, of_clk_src_simple_get, clk);
+       if (!IS_ERR(hw)) {
+               of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
                return;
        }
        pr_err("%s: failed to register %s div clock (%ld)\n",
-              __func__, clk_name, PTR_ERR(clk));
+              __func__, clk_name, PTR_ERR(hw));
 error:
        if (divcr)
                iounmap(divcr);
index c9c2fd575ef7d0e8aa660c61c8ec5470f09cf1c8..a263124606211bf3514eaf24b77ae66fbb36922c 100644 (file)
@@ -84,11 +84,11 @@ static const struct clk_ops pll_ops = {
 static void __init h8s2678_pll_clk_setup(struct device_node *node)
 {
        unsigned int num_parents;
-       struct clk *clk;
        const char *clk_name = node->name;
        const char *parent_name;
        struct pll_clock *pll_clock;
        struct clk_init_data init;
+       int ret;
 
        num_parents = of_clk_get_parent_count(node);
        if (!num_parents) {
@@ -121,14 +121,14 @@ static void __init h8s2678_pll_clk_setup(struct device_node *node)
        init.num_parents = 1;
        pll_clock->hw.init = &init;
 
-       clk = clk_register(NULL, &pll_clock->hw);
-       if (IS_ERR(clk)) {
-               pr_err("%s: failed to register %s div clock (%ld)\n",
-                      __func__, clk_name, PTR_ERR(clk));
+       ret = clk_hw_register(NULL, &pll_clock->hw);
+       if (ret) {
+               pr_err("%s: failed to register %s div clock (%d)\n",
+                      __func__, clk_name, ret);
                goto unmap_pllcr;
        }
 
-       of_clk_add_provider(node, of_clk_src_simple_get, clk);
+       of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clock->hw);
        return;
 
 unmap_pllcr:
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