rseq: do not set back rseq_cs to 0
[lttng-ust.git] / libringbuffer / rseq-ppc.h
1 /*
2 * rseq-ppc.h
3 *
4 * (C) Copyright 2016 - Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
5 * (C) Copyright 2016 - Boqun Feng <boqun.feng@gmail.com>
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
20 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 */
25
26 #define has_fast_acquire_release() 0
27
28 #ifdef __PPC64__
29 #define has_single_copy_load_64() 1
30 #else
31 #define has_single_copy_load_64() 0
32 #endif
33
34 /*
35 * The __rseq_table section can be used by debuggers to better handle
36 * single-stepping through the restartable critical sections.
37 */
38
39 #ifdef __PPC64__
40
41 #define RSEQ_FINISH_ASM(_target_final, _to_write_final, _start_value, \
42 _failure, _spec_store, _spec_input, \
43 _final_store, _final_input, _extra_clobber, \
44 _setup, _teardown, _scratch) \
45 __asm__ __volatile__ goto ( \
46 ".pushsection __rseq_table, \"aw\"\n\t" \
47 ".balign 32\n\t" \
48 "3:\n\t" \
49 ".quad 1f, 2f, 4f, 0x0\n\t" \
50 ".popsection\n\t" \
51 "1:\n\t" \
52 _setup \
53 RSEQ_INJECT_ASM(1) \
54 "lis %%r17, (3b)@highest\n\t" \
55 "ori %%r17, %%r17, (3b)@higher\n\t" \
56 "rldicr %%r17, %%r17, 32, 31\n\t" \
57 "oris %%r17, %%r17, (3b)@h\n\t" \
58 "ori %%r17, %%r17, (3b)@l\n\t" \
59 "std %%r17, 0(%[rseq_cs])\n\t" \
60 RSEQ_INJECT_ASM(2) \
61 "lwz %%r17, %[current_event_counter]\n\t" \
62 "cmpw cr7, %[start_event_counter], %%r17\n\t" \
63 "bne- cr7, 4f\n\t" \
64 RSEQ_INJECT_ASM(3) \
65 _spec_store \
66 _final_store \
67 "2:\n\t" \
68 RSEQ_INJECT_ASM(5) \
69 _teardown \
70 "b 5f\n\t" \
71 "4:\n\t" \
72 _teardown \
73 "b %l[failure]\n\t" \
74 "5:\n\t" \
75 : /* gcc asm goto does not allow outputs */ \
76 : [start_event_counter]"r"((_start_value).event_counter), \
77 [current_event_counter]"m"((_start_value).rseqp->u.e.event_counter), \
78 [rseq_cs]"b"(&(_start_value).rseqp->rseq_cs) \
79 _spec_input \
80 _final_input \
81 RSEQ_INJECT_INPUT \
82 : "r17", "memory", "cc" \
83 _extra_clobber \
84 RSEQ_INJECT_CLOBBER \
85 : _failure \
86 )
87
88 #define RSEQ_FINISH_FINAL_STORE_ASM() \
89 "std %[to_write_final], 0(%[target_final])\n\t"
90
91 #define RSEQ_FINISH_FINAL_STORE_RELEASE_ASM() \
92 "lwsync\n\t" \
93 RSEQ_FINISH_FINAL_STORE_ASM()
94
95 #define RSEQ_FINISH_FINAL_STORE_INPUT(_target_final, _to_write_final) \
96 , [to_write_final]"r"(_to_write_final), \
97 [target_final]"b"(_target_final)
98
99 #define RSEQ_FINISH_SPECULATIVE_STORE_ASM() \
100 "std %[to_write_spec], 0(%[target_spec])\n\t" \
101 RSEQ_INJECT_ASM(4)
102
103 #define RSEQ_FINISH_SPECULATIVE_STORE_INPUT(_target_spec, _to_write_spec) \
104 , [to_write_spec]"r"(_to_write_spec), \
105 [target_spec]"b"(_target_spec)
106
107 /* TODO: implement a faster memcpy. */
108 #define RSEQ_FINISH_MEMCPY_STORE_ASM() \
109 "cmpdi %%r19, 0\n\t" \
110 "beq 333f\n\t" \
111 "addi %%r20, %%r20, -1\n\t" \
112 "addi %%r21, %%r21, -1\n\t" \
113 "222:\n\t" \
114 "lbzu %%r18, 1(%%r20)\n\t" \
115 "stbu %%r18, 1(%%r21)\n\t" \
116 "addi %%r19, %%r19, -1\n\t" \
117 "cmpdi %%r19, 0\n\t" \
118 "bne 222b\n\t" \
119 "333:\n\t" \
120 RSEQ_INJECT_ASM(4)
121
122 #define RSEQ_FINISH_MEMCPY_STORE_INPUT(_target_memcpy, _to_write_memcpy, _len_memcpy) \
123 , [to_write_memcpy]"r"(_to_write_memcpy), \
124 [target_memcpy]"r"(_target_memcpy), \
125 [len_memcpy]"r"(_len_memcpy)
126
127 #define RSEQ_FINISH_MEMCPY_CLOBBER() \
128 , "r18", "r19", "r20", "r21"
129
130 #define RSEQ_FINISH_MEMCPY_SCRATCH()
131
132 /*
133 * We use extra registers to hold the input registers, and we don't need to
134 * save and restore the input registers.
135 */
136 #define RSEQ_FINISH_MEMCPY_SETUP() \
137 "mr %%r19, %[len_memcpy]\n\t" \
138 "mr %%r20, %[to_write_memcpy]\n\t" \
139 "mr %%r21, %[target_memcpy]\n\t" \
140
141 #define RSEQ_FINISH_MEMCPY_TEARDOWN()
142
143 #else /* #ifdef __PPC64__ */
144
145 #define RSEQ_FINISH_ASM(_target_final, _to_write_final, _start_value, \
146 _failure, _spec_store, _spec_input, \
147 _final_store, _final_input, _extra_clobber, \
148 _setup, _teardown, _scratch) \
149 __asm__ __volatile__ goto ( \
150 ".pushsection __rseq_table, \"aw\"\n\t" \
151 ".balign 32\n\t" \
152 "3:\n\t" \
153 /* 32-bit only supported on BE */ \
154 ".long 0x0, 1f, 0x0, 2f, 0x0, 4f, 0x0, 0x0\n\t" \
155 ".popsection\n\t" \
156 "1:\n\t" \
157 _setup \
158 RSEQ_INJECT_ASM(1) \
159 "lis %%r17, (3b)@ha\n\t" \
160 "addi %%r17, %%r17, (3b)@l\n\t" \
161 "stw %%r17, 0(%[rseq_cs])\n\t" \
162 RSEQ_INJECT_ASM(2) \
163 "lwz %%r17, %[current_event_counter]\n\t" \
164 "cmpw cr7, %[start_event_counter], %%r17\n\t" \
165 "bne- cr7, 4f\n\t" \
166 RSEQ_INJECT_ASM(3) \
167 _spec_store \
168 _final_store \
169 "2:\n\t" \
170 RSEQ_INJECT_ASM(5) \
171 _teardown \
172 "b 5f\n\t" \
173 "4:\n\t" \
174 _teardown \
175 "b %l[failure]\n\t" \
176 "5:\n\t" \
177 : /* gcc asm goto does not allow outputs */ \
178 : [start_event_counter]"r"((_start_value).event_counter), \
179 [current_event_counter]"m"((_start_value).rseqp->u.e.event_counter), \
180 [rseq_cs]"b"(&(_start_value).rseqp->rseq_cs) \
181 _spec_input \
182 _final_input \
183 RSEQ_INJECT_INPUT \
184 : "r17", "memory", "cc" \
185 _extra_clobber \
186 RSEQ_INJECT_CLOBBER \
187 : _failure \
188 )
189
190 #define RSEQ_FINISH_FINAL_STORE_ASM() \
191 "stw %[to_write_final], 0(%[target_final])\n\t"
192
193 #define RSEQ_FINISH_FINAL_STORE_RELEASE_ASM() \
194 "lwsync\n\t" \
195 RSEQ_FINISH_FINAL_STORE_ASM()
196
197 #define RSEQ_FINISH_FINAL_STORE_INPUT(_target_final, _to_write_final) \
198 , [to_write_final]"r"(_to_write_final), \
199 [target_final]"b"(_target_final)
200
201 #define RSEQ_FINISH_SPECULATIVE_STORE_ASM() \
202 "stw %[to_write_spec], 0(%[target_spec])\n\t" \
203 RSEQ_INJECT_ASM(4)
204
205 #define RSEQ_FINISH_SPECULATIVE_STORE_INPUT(_target_spec, _to_write_spec) \
206 , [to_write_spec]"r"(_to_write_spec), \
207 [target_spec]"b"(_target_spec)
208
209 /* TODO: implement a faster memcpy. */
210 #define RSEQ_FINISH_MEMCPY_STORE_ASM() \
211 "cmpwi %%r19, 0\n\t" \
212 "beq 333f\n\t" \
213 "addi %%r20, %%r20, -1\n\t" \
214 "addi %%r21, %%r21, -1\n\t" \
215 "222:\n\t" \
216 "lbzu %%r18, 1(%%r20)\n\t" \
217 "stbu %%r18, 1(%%r21)\n\t" \
218 "addi %%r19, %%r19, -1\n\t" \
219 "cmpwi %%r19, 0\n\t" \
220 "bne 222b\n\t" \
221 "333:\n\t" \
222 RSEQ_INJECT_ASM(4)
223
224 #define RSEQ_FINISH_MEMCPY_STORE_INPUT(_target_memcpy, _to_write_memcpy, _len_memcpy) \
225 , [to_write_memcpy]"r"(_to_write_memcpy), \
226 [target_memcpy]"r"(_target_memcpy), \
227 [len_memcpy]"r"(_len_memcpy)
228
229 #define RSEQ_FINISH_MEMCPY_CLOBBER() \
230 , "r18", "r19", "r20", "r21"
231
232 #define RSEQ_FINISH_MEMCPY_SCRATCH()
233
234 /*
235 * We use extra registers to hold the input registers, and we don't need to
236 * save and restore the input registers.
237 */
238 #define RSEQ_FINISH_MEMCPY_SETUP() \
239 "mr %%r19, %[len_memcpy]\n\t" \
240 "mr %%r20, %[to_write_memcpy]\n\t" \
241 "mr %%r21, %[target_memcpy]\n\t" \
242
243 #define RSEQ_FINISH_MEMCPY_TEARDOWN()
244
245 #endif /* #else #ifdef __PPC64__ */
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