Commit | Line | Data |
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ac23d4ee JS |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * SGI UV APIC functions (note: not an Intel compatible APIC) | |
7 | * | |
b15cc4a1 | 8 | * Copyright (C) 2007-2013 Silicon Graphics, Inc. All rights reserved. |
ac23d4ee | 9 | */ |
ac23d4ee | 10 | #include <linux/cpumask.h> |
0b1da1c8 IM |
11 | #include <linux/hardirq.h> |
12 | #include <linux/proc_fs.h> | |
13 | #include <linux/threads.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
ac23d4ee | 16 | #include <linux/string.h> |
ac23d4ee | 17 | #include <linux/ctype.h> |
ac23d4ee | 18 | #include <linux/sched.h> |
7f1baa06 | 19 | #include <linux/timer.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
0b1da1c8 IM |
21 | #include <linux/cpu.h> |
22 | #include <linux/init.h> | |
27229ca6 | 23 | #include <linux/io.h> |
841582ea | 24 | #include <linux/pci.h> |
78c06176 | 25 | #include <linux/kdebug.h> |
ca444564 | 26 | #include <linux/delay.h> |
818987e9 | 27 | #include <linux/crash_dump.h> |
0b1da1c8 | 28 | |
ac23d4ee JS |
29 | #include <asm/uv/uv_mmrs.h> |
30 | #include <asm/uv/uv_hub.h> | |
0b1da1c8 IM |
31 | #include <asm/current.h> |
32 | #include <asm/pgtable.h> | |
7019cc2d | 33 | #include <asm/uv/bios.h> |
0b1da1c8 IM |
34 | #include <asm/uv/uv.h> |
35 | #include <asm/apic.h> | |
36 | #include <asm/ipi.h> | |
37 | #include <asm/smp.h> | |
fd12a0d6 | 38 | #include <asm/x86_init.h> |
818987e9 | 39 | #include <asm/emergency-restart.h> |
1d44e828 JS |
40 | #include <asm/nmi.h> |
41 | ||
42 | /* BMC sets a bit this MMR non-zero before sending an NMI */ | |
43 | #define UVH_NMI_MMR UVH_SCRATCH5 | |
44 | #define UVH_NMI_MMR_CLEAR (UVH_NMI_MMR + 8) | |
45 | #define UV_NMI_PENDING_MASK (1UL << 63) | |
46 | DEFINE_PER_CPU(unsigned long, cpu_last_nmi_count); | |
ac23d4ee | 47 | |
510b3725 YL |
48 | DEFINE_PER_CPU(int, x2apic_extra_bits); |
49 | ||
841582ea MT |
50 | #define PR_DEVEL(fmt, args...) pr_devel("%s: " fmt, __func__, args) |
51 | ||
1b9b89e7 | 52 | static enum uv_system_type uv_system_type; |
fd12a0d6 | 53 | static u64 gru_start_paddr, gru_end_paddr; |
c8f730b1 | 54 | static union uvh_apicid uvh_apicid; |
7a1110e8 JS |
55 | int uv_min_hub_revision_id; |
56 | EXPORT_SYMBOL_GPL(uv_min_hub_revision_id); | |
8191c9f6 DS |
57 | unsigned int uv_apicid_hibits; |
58 | EXPORT_SYMBOL_GPL(uv_apicid_hibits); | |
78c06176 | 59 | static DEFINE_SPINLOCK(uv_nmi_lock); |
fd12a0d6 | 60 | |
1a8880a1 SS |
61 | static struct apic apic_x2apic_uv_x; |
62 | ||
e6810413 JS |
63 | static unsigned long __init uv_early_read_mmr(unsigned long addr) |
64 | { | |
65 | unsigned long val, *mmr; | |
66 | ||
67 | mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr)); | |
68 | val = *mmr; | |
69 | early_iounmap(mmr, sizeof(*mmr)); | |
70 | return val; | |
71 | } | |
72 | ||
eb41c8be | 73 | static inline bool is_GRU_range(u64 start, u64 end) |
fd12a0d6 | 74 | { |
ccef0864 | 75 | return start >= gru_start_paddr && end <= gru_end_paddr; |
fd12a0d6 JS |
76 | } |
77 | ||
eb41c8be | 78 | static bool uv_is_untracked_pat_range(u64 start, u64 end) |
fd12a0d6 JS |
79 | { |
80 | return is_ISA_range(start, end) || is_GRU_range(start, end); | |
81 | } | |
1b9b89e7 | 82 | |
d8850ba4 | 83 | static int __init early_get_pnodeid(void) |
27229ca6 JS |
84 | { |
85 | union uvh_node_id_u node_id; | |
d8850ba4 JS |
86 | union uvh_rh_gam_config_mmr_u m_n_config; |
87 | int pnode; | |
7a1110e8 JS |
88 | |
89 | /* Currently, all blades have same revision number */ | |
e6810413 | 90 | node_id.v = uv_early_read_mmr(UVH_NODE_ID); |
d8850ba4 | 91 | m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR); |
7a1110e8 JS |
92 | uv_min_hub_revision_id = node_id.s.revision; |
93 | ||
b15cc4a1 MT |
94 | switch (node_id.s.part_number) { |
95 | case UV2_HUB_PART_NUMBER: | |
96 | case UV2_HUB_PART_NUMBER_X: | |
b495e039 | 97 | uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1; |
b15cc4a1 MT |
98 | break; |
99 | case UV3_HUB_PART_NUMBER: | |
100 | case UV3_HUB_PART_NUMBER_X: | |
101 | uv_min_hub_revision_id += UV3_HUB_REVISION_BASE - 1; | |
102 | break; | |
103 | } | |
2a919596 JS |
104 | |
105 | uv_hub_info->hub_revision = uv_min_hub_revision_id; | |
d8850ba4 JS |
106 | pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1); |
107 | return pnode; | |
27229ca6 JS |
108 | } |
109 | ||
0520bd84 | 110 | static void __init early_get_apic_pnode_shift(void) |
c8f730b1 | 111 | { |
e6810413 | 112 | uvh_apicid.v = uv_early_read_mmr(UVH_APICID); |
c8f730b1 RA |
113 | if (!uvh_apicid.v) |
114 | /* | |
115 | * Old bios, use default value | |
116 | */ | |
117 | uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT; | |
c8f730b1 RA |
118 | } |
119 | ||
8191c9f6 DS |
120 | /* |
121 | * Add an extra bit as dictated by bios to the destination apicid of | |
122 | * interrupts potentially passing through the UV HUB. This prevents | |
123 | * a deadlock between interrupts and IO port operations. | |
124 | */ | |
125 | static void __init uv_set_apicid_hibit(void) | |
126 | { | |
2a919596 | 127 | union uv1h_lb_target_physical_apic_id_mask_u apicid_mask; |
8191c9f6 | 128 | |
2a919596 JS |
129 | if (is_uv1_hub()) { |
130 | apicid_mask.v = | |
131 | uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK); | |
132 | uv_apicid_hibits = | |
133 | apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK; | |
134 | } | |
8191c9f6 DS |
135 | } |
136 | ||
52459ab9 | 137 | static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) |
1b9b89e7 | 138 | { |
b15cc4a1 | 139 | int pnodeid, is_uv1, is_uv2, is_uv3; |
1d2c867c | 140 | |
2a919596 JS |
141 | is_uv1 = !strcmp(oem_id, "SGI"); |
142 | is_uv2 = !strcmp(oem_id, "SGI2"); | |
b15cc4a1 MT |
143 | is_uv3 = !strncmp(oem_id, "SGI3", 4); /* there are varieties of UV3 */ |
144 | if (is_uv1 || is_uv2 || is_uv3) { | |
2a919596 | 145 | uv_hub_info->hub_revision = |
b15cc4a1 MT |
146 | (is_uv1 ? UV1_HUB_REVISION_BASE : |
147 | (is_uv2 ? UV2_HUB_REVISION_BASE : | |
148 | UV3_HUB_REVISION_BASE)); | |
d8850ba4 | 149 | pnodeid = early_get_pnodeid(); |
0520bd84 | 150 | early_get_apic_pnode_shift(); |
fd12a0d6 | 151 | x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range; |
78c06176 | 152 | x86_platform.nmi_init = uv_nmi_init; |
1b9b89e7 YL |
153 | if (!strcmp(oem_table_id, "UVL")) |
154 | uv_system_type = UV_LEGACY_APIC; | |
155 | else if (!strcmp(oem_table_id, "UVX")) | |
156 | uv_system_type = UV_X2APIC; | |
157 | else if (!strcmp(oem_table_id, "UVH")) { | |
0a3aee0d | 158 | __this_cpu_write(x2apic_extra_bits, |
72eb6a79 | 159 | pnodeid << uvh_apicid.s.pnode_shift); |
1b9b89e7 | 160 | uv_system_type = UV_NON_UNIQUE_APIC; |
8191c9f6 | 161 | uv_set_apicid_hibit(); |
1b9b89e7 YL |
162 | return 1; |
163 | } | |
164 | } | |
165 | return 0; | |
166 | } | |
167 | ||
168 | enum uv_system_type get_uv_system_type(void) | |
169 | { | |
170 | return uv_system_type; | |
171 | } | |
172 | ||
173 | int is_uv_system(void) | |
174 | { | |
175 | return uv_system_type != UV_NONE; | |
176 | } | |
8067794b | 177 | EXPORT_SYMBOL_GPL(is_uv_system); |
1b9b89e7 | 178 | |
ac23d4ee JS |
179 | DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); |
180 | EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info); | |
181 | ||
182 | struct uv_blade_info *uv_blade_info; | |
183 | EXPORT_SYMBOL_GPL(uv_blade_info); | |
184 | ||
185 | short *uv_node_to_blade; | |
186 | EXPORT_SYMBOL_GPL(uv_node_to_blade); | |
187 | ||
188 | short *uv_cpu_to_blade; | |
189 | EXPORT_SYMBOL_GPL(uv_cpu_to_blade); | |
190 | ||
191 | short uv_possible_blades; | |
192 | EXPORT_SYMBOL_GPL(uv_possible_blades); | |
193 | ||
7019cc2d RA |
194 | unsigned long sn_rtc_cycles_per_second; |
195 | EXPORT_SYMBOL(sn_rtc_cycles_per_second); | |
196 | ||
667c5296 | 197 | static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip) |
ac23d4ee | 198 | { |
0b1da1c8 | 199 | #ifdef CONFIG_SMP |
ac23d4ee | 200 | unsigned long val; |
9f5314fb | 201 | int pnode; |
ac23d4ee | 202 | |
9f5314fb | 203 | pnode = uv_apicid_to_pnode(phys_apicid); |
8191c9f6 | 204 | phys_apicid |= uv_apicid_hibits; |
ac23d4ee JS |
205 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | |
206 | (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | | |
2b6163bf | 207 | ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | |
34d05591 | 208 | APIC_DM_INIT; |
9f5314fb | 209 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
34d05591 JS |
210 | |
211 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | | |
212 | (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | | |
2b6163bf | 213 | ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | |
34d05591 | 214 | APIC_DM_STARTUP; |
9f5314fb | 215 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
2b6163bf YL |
216 | |
217 | atomic_set(&init_deasserted, 1); | |
0b1da1c8 | 218 | #endif |
ac23d4ee JS |
219 | return 0; |
220 | } | |
221 | ||
222 | static void uv_send_IPI_one(int cpu, int vector) | |
223 | { | |
66666e50 | 224 | unsigned long apicid; |
9f5314fb | 225 | int pnode; |
ac23d4ee | 226 | |
1e0b5d00 | 227 | apicid = per_cpu(x86_cpu_to_apicid, cpu); |
9f5314fb | 228 | pnode = uv_apicid_to_pnode(apicid); |
66666e50 | 229 | uv_hub_send_ipi(pnode, apicid, vector); |
ac23d4ee JS |
230 | } |
231 | ||
bcda016e | 232 | static void uv_send_IPI_mask(const struct cpumask *mask, int vector) |
ac23d4ee JS |
233 | { |
234 | unsigned int cpu; | |
235 | ||
bcda016e | 236 | for_each_cpu(cpu, mask) |
e7986739 MT |
237 | uv_send_IPI_one(cpu, vector); |
238 | } | |
239 | ||
bcda016e | 240 | static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) |
e7986739 | 241 | { |
e7986739 | 242 | unsigned int this_cpu = smp_processor_id(); |
dac5f412 | 243 | unsigned int cpu; |
e7986739 | 244 | |
dac5f412 | 245 | for_each_cpu(cpu, mask) { |
e7986739 | 246 | if (cpu != this_cpu) |
ac23d4ee | 247 | uv_send_IPI_one(cpu, vector); |
dac5f412 | 248 | } |
ac23d4ee JS |
249 | } |
250 | ||
251 | static void uv_send_IPI_allbutself(int vector) | |
252 | { | |
e7986739 | 253 | unsigned int this_cpu = smp_processor_id(); |
dac5f412 | 254 | unsigned int cpu; |
ac23d4ee | 255 | |
dac5f412 | 256 | for_each_online_cpu(cpu) { |
e7986739 MT |
257 | if (cpu != this_cpu) |
258 | uv_send_IPI_one(cpu, vector); | |
dac5f412 | 259 | } |
ac23d4ee JS |
260 | } |
261 | ||
262 | static void uv_send_IPI_all(int vector) | |
263 | { | |
bcda016e | 264 | uv_send_IPI_mask(cpu_online_mask, vector); |
ac23d4ee JS |
265 | } |
266 | ||
b7157acf SP |
267 | static int uv_apic_id_valid(int apicid) |
268 | { | |
269 | return 1; | |
270 | } | |
271 | ||
ac23d4ee JS |
272 | static int uv_apic_id_registered(void) |
273 | { | |
274 | return 1; | |
275 | } | |
276 | ||
277d1f58 | 277 | static void uv_init_apic_ldr(void) |
5c520a67 SS |
278 | { |
279 | } | |
280 | ||
ff164324 | 281 | static int |
debccb3e | 282 | uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
ff164324 AG |
283 | const struct cpumask *andmask, |
284 | unsigned int *apicid) | |
95d313cf | 285 | { |
ea3807ea | 286 | int unsigned cpu; |
95d313cf MT |
287 | |
288 | /* | |
289 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | |
290 | * May as well be the first. | |
291 | */ | |
debccb3e | 292 | for_each_cpu_and(cpu, cpumask, andmask) { |
a775a38b MT |
293 | if (cpumask_test_cpu(cpu, cpu_online_mask)) |
294 | break; | |
debccb3e | 295 | } |
ff164324 | 296 | |
ea3807ea | 297 | if (likely(cpu < nr_cpu_ids)) { |
a5a39156 AG |
298 | *apicid = per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits; |
299 | return 0; | |
a5a39156 | 300 | } |
ea3807ea AG |
301 | |
302 | return -EINVAL; | |
95d313cf MT |
303 | } |
304 | ||
ca6c8ed4 | 305 | static unsigned int x2apic_get_apic_id(unsigned long x) |
0c81c746 SS |
306 | { |
307 | unsigned int id; | |
308 | ||
309 | WARN_ON(preemptible() && num_online_cpus() > 1); | |
0a3aee0d | 310 | id = x | __this_cpu_read(x2apic_extra_bits); |
0c81c746 SS |
311 | |
312 | return id; | |
313 | } | |
314 | ||
1b9b89e7 | 315 | static unsigned long set_apic_id(unsigned int id) |
f910a9dc YL |
316 | { |
317 | unsigned long x; | |
318 | ||
319 | /* maskout x2apic_extra_bits ? */ | |
320 | x = id; | |
321 | return x; | |
322 | } | |
323 | ||
324 | static unsigned int uv_read_apic_id(void) | |
325 | { | |
326 | ||
ca6c8ed4 | 327 | return x2apic_get_apic_id(apic_read(APIC_ID)); |
f910a9dc YL |
328 | } |
329 | ||
d4c9a9f3 | 330 | static int uv_phys_pkg_id(int initial_apicid, int index_msb) |
ac23d4ee | 331 | { |
0c81c746 | 332 | return uv_read_apic_id() >> index_msb; |
ac23d4ee JS |
333 | } |
334 | ||
ac23d4ee JS |
335 | static void uv_send_IPI_self(int vector) |
336 | { | |
337 | apic_write(APIC_SELF_IPI, vector); | |
338 | } | |
ac23d4ee | 339 | |
9ebd680b SS |
340 | static int uv_probe(void) |
341 | { | |
342 | return apic == &apic_x2apic_uv_x; | |
343 | } | |
344 | ||
1a8880a1 | 345 | static struct apic __refdata apic_x2apic_uv_x = { |
c7967329 IM |
346 | |
347 | .name = "UV large system", | |
9ebd680b | 348 | .probe = uv_probe, |
c7967329 | 349 | .acpi_madt_oem_check = uv_acpi_madt_oem_check, |
b7157acf | 350 | .apic_id_valid = uv_apic_id_valid, |
c7967329 IM |
351 | .apic_id_registered = uv_apic_id_registered, |
352 | ||
f8987a10 | 353 | .irq_delivery_mode = dest_Fixed, |
c5997fa8 | 354 | .irq_dest_mode = 0, /* physical */ |
c7967329 | 355 | |
bf721d3a | 356 | .target_cpus = online_target_cpus, |
08125d3e | 357 | .disable_esr = 0, |
bdb1a9b6 | 358 | .dest_logical = APIC_DEST_LOGICAL, |
c7967329 IM |
359 | .check_apicid_used = NULL, |
360 | .check_apicid_present = NULL, | |
361 | ||
9d8e1066 | 362 | .vector_allocation_domain = default_vector_allocation_domain, |
c7967329 IM |
363 | .init_apic_ldr = uv_init_apic_ldr, |
364 | ||
365 | .ioapic_phys_id_map = NULL, | |
366 | .setup_apic_routing = NULL, | |
367 | .multi_timer_check = NULL, | |
a21769a4 | 368 | .cpu_present_to_apicid = default_cpu_present_to_apicid, |
c7967329 IM |
369 | .apicid_to_cpu_present = NULL, |
370 | .setup_portio_remap = NULL, | |
a27a6210 | 371 | .check_phys_apicid_present = default_check_phys_apicid_present, |
c7967329 | 372 | .enable_apic_mode = NULL, |
d4c9a9f3 | 373 | .phys_pkg_id = uv_phys_pkg_id, |
c7967329 IM |
374 | .mps_oem_check = NULL, |
375 | ||
ca6c8ed4 | 376 | .get_apic_id = x2apic_get_apic_id, |
c7967329 IM |
377 | .set_apic_id = set_apic_id, |
378 | .apic_id_mask = 0xFFFFFFFFu, | |
379 | ||
c7967329 IM |
380 | .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and, |
381 | ||
382 | .send_IPI_mask = uv_send_IPI_mask, | |
383 | .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself, | |
384 | .send_IPI_allbutself = uv_send_IPI_allbutself, | |
385 | .send_IPI_all = uv_send_IPI_all, | |
386 | .send_IPI_self = uv_send_IPI_self, | |
387 | ||
1f5bcabf | 388 | .wakeup_secondary_cpu = uv_wakeup_secondary, |
abfa584c IM |
389 | .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW, |
390 | .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH, | |
c7967329 IM |
391 | .wait_for_init_deassert = NULL, |
392 | .smp_callin_clear_local_apic = NULL, | |
c7967329 | 393 | .inquire_remote_apic = NULL, |
c1eeb2de YL |
394 | |
395 | .read = native_apic_msr_read, | |
396 | .write = native_apic_msr_write, | |
0ab711ae | 397 | .eoi_write = native_apic_msr_eoi_write, |
c1eeb2de YL |
398 | .icr_read = native_x2apic_icr_read, |
399 | .icr_write = native_x2apic_icr_write, | |
400 | .wait_icr_idle = native_x2apic_wait_icr_idle, | |
401 | .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, | |
ac23d4ee JS |
402 | }; |
403 | ||
9f5314fb | 404 | static __cpuinit void set_x2apic_extra_bits(int pnode) |
ac23d4ee | 405 | { |
16ee8db6 | 406 | __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift); |
ac23d4ee JS |
407 | } |
408 | ||
409 | /* | |
410 | * Called on boot cpu. | |
411 | */ | |
9f5314fb JS |
412 | static __init int boot_pnode_to_blade(int pnode) |
413 | { | |
414 | int blade; | |
415 | ||
416 | for (blade = 0; blade < uv_num_possible_blades(); blade++) | |
417 | if (pnode == uv_blade_info[blade].pnode) | |
418 | return blade; | |
419 | BUG(); | |
420 | } | |
421 | ||
422 | struct redir_addr { | |
423 | unsigned long redirect; | |
424 | unsigned long alias; | |
425 | }; | |
426 | ||
427 | #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT | |
428 | ||
429 | static __initdata struct redir_addr redir_addrs[] = { | |
62b0cfc2 JS |
430 | {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR}, |
431 | {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR}, | |
432 | {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR}, | |
9f5314fb JS |
433 | }; |
434 | ||
435 | static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) | |
436 | { | |
62b0cfc2 | 437 | union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias; |
9f5314fb JS |
438 | union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect; |
439 | int i; | |
440 | ||
441 | for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) { | |
442 | alias.v = uv_read_local_mmr(redir_addrs[i].alias); | |
036ed8ba | 443 | if (alias.s.enable && alias.s.base == 0) { |
9f5314fb JS |
444 | *size = (1UL << alias.s.m_alias); |
445 | redirect.v = uv_read_local_mmr(redir_addrs[i].redirect); | |
446 | *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT; | |
447 | return; | |
448 | } | |
449 | } | |
036ed8ba | 450 | *base = *size = 0; |
9f5314fb JS |
451 | } |
452 | ||
83f5d894 JS |
453 | enum map_type {map_wb, map_uc}; |
454 | ||
fcfbb2b5 MT |
455 | static __init void map_high(char *id, unsigned long base, int pshift, |
456 | int bshift, int max_pnode, enum map_type map_type) | |
83f5d894 JS |
457 | { |
458 | unsigned long bytes, paddr; | |
459 | ||
fcfbb2b5 MT |
460 | paddr = base << pshift; |
461 | bytes = (1UL << bshift) * (max_pnode + 1); | |
b15cc4a1 MT |
462 | if (!paddr) { |
463 | pr_info("UV: Map %s_HI base address NULL\n", id); | |
464 | return; | |
465 | } | |
466 | pr_info("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes); | |
83f5d894 JS |
467 | if (map_type == map_uc) |
468 | init_extra_mapping_uc(paddr, bytes); | |
469 | else | |
470 | init_extra_mapping_wb(paddr, bytes); | |
83f5d894 | 471 | } |
b15cc4a1 | 472 | |
83f5d894 JS |
473 | static __init void map_gru_high(int max_pnode) |
474 | { | |
475 | union uvh_rh_gam_gru_overlay_config_mmr_u gru; | |
476 | int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
477 | ||
478 | gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR); | |
fd12a0d6 | 479 | if (gru.s.enable) { |
fcfbb2b5 | 480 | map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb); |
fd12a0d6 JS |
481 | gru_start_paddr = ((u64)gru.s.base << shift); |
482 | gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1); | |
b15cc4a1 MT |
483 | } else { |
484 | pr_info("UV: GRU disabled\n"); | |
fd12a0d6 | 485 | } |
83f5d894 JS |
486 | } |
487 | ||
daf7b9c9 JS |
488 | static __init void map_mmr_high(int max_pnode) |
489 | { | |
490 | union uvh_rh_gam_mmr_overlay_config_mmr_u mmr; | |
491 | int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
492 | ||
493 | mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR); | |
494 | if (mmr.s.enable) | |
fcfbb2b5 | 495 | map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc); |
b15cc4a1 MT |
496 | else |
497 | pr_info("UV: MMR disabled\n"); | |
498 | } | |
499 | ||
500 | /* | |
501 | * This commonality works because both 0 & 1 versions of the MMIOH OVERLAY | |
502 | * and REDIRECT MMR regs are exactly the same on UV3. | |
503 | */ | |
504 | struct mmioh_config { | |
505 | unsigned long overlay; | |
506 | unsigned long redirect; | |
507 | char *id; | |
508 | }; | |
509 | ||
510 | static __initdata struct mmioh_config mmiohs[] = { | |
511 | { | |
512 | UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR, | |
513 | UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR, | |
514 | "MMIOH0" | |
515 | }, | |
516 | { | |
517 | UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR, | |
518 | UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR, | |
519 | "MMIOH1" | |
520 | }, | |
521 | }; | |
522 | ||
523 | static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode) | |
524 | { | |
525 | union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay; | |
526 | unsigned long mmr; | |
527 | unsigned long base; | |
528 | int i, n, shift, m_io, max_io; | |
529 | int nasid, lnasid, fi, li; | |
530 | char *id; | |
531 | ||
532 | id = mmiohs[index].id; | |
533 | overlay.v = uv_read_local_mmr(mmiohs[index].overlay); | |
534 | pr_info("UV: %s overlay 0x%lx base:0x%x m_io:%d\n", | |
535 | id, overlay.v, overlay.s3.base, overlay.s3.m_io); | |
536 | if (!overlay.s3.enable) { | |
537 | pr_info("UV: %s disabled\n", id); | |
538 | return; | |
539 | } | |
540 | ||
541 | shift = UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT; | |
542 | base = (unsigned long)overlay.s3.base; | |
543 | m_io = overlay.s3.m_io; | |
544 | mmr = mmiohs[index].redirect; | |
545 | n = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH; | |
546 | min_pnode *= 2; /* convert to NASID */ | |
547 | max_pnode *= 2; | |
548 | max_io = lnasid = fi = li = -1; | |
549 | ||
550 | for (i = 0; i < n; i++) { | |
551 | union uv3h_rh_gam_mmioh_redirect_config0_mmr_u redirect; | |
552 | ||
553 | redirect.v = uv_read_local_mmr(mmr + i * 8); | |
554 | nasid = redirect.s3.nasid; | |
555 | if (nasid < min_pnode || max_pnode < nasid) | |
556 | nasid = -1; /* invalid NASID */ | |
557 | ||
558 | if (nasid == lnasid) { | |
559 | li = i; | |
560 | if (i != n-1) /* last entry check */ | |
561 | continue; | |
562 | } | |
563 | ||
564 | /* check if we have a cached (or last) redirect to print */ | |
565 | if (lnasid != -1 || (i == n-1 && nasid != -1)) { | |
566 | unsigned long addr1, addr2; | |
567 | int f, l; | |
568 | ||
569 | if (lnasid == -1) { | |
570 | f = l = i; | |
571 | lnasid = nasid; | |
572 | } else { | |
573 | f = fi; | |
574 | l = li; | |
575 | } | |
576 | addr1 = (base << shift) + | |
577 | f * (unsigned long)(1 << m_io); | |
578 | addr2 = (base << shift) + | |
579 | (l + 1) * (unsigned long)(1 << m_io); | |
580 | pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n", | |
581 | id, fi, li, lnasid, addr1, addr2); | |
582 | if (max_io < l) | |
583 | max_io = l; | |
584 | } | |
585 | fi = li = i; | |
586 | lnasid = nasid; | |
587 | } | |
588 | ||
589 | pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n", | |
590 | id, base, shift, m_io, max_io); | |
591 | ||
592 | if (max_io >= 0) | |
593 | map_high(id, base, shift, m_io, max_io, map_uc); | |
daf7b9c9 JS |
594 | } |
595 | ||
b15cc4a1 | 596 | static __init void map_mmioh_high(int min_pnode, int max_pnode) |
83f5d894 JS |
597 | { |
598 | union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh; | |
b15cc4a1 MT |
599 | unsigned long mmr, base; |
600 | int shift, enable, m_io, n_io; | |
83f5d894 | 601 | |
b15cc4a1 MT |
602 | if (is_uv3_hub()) { |
603 | /* Map both MMIOH Regions */ | |
604 | map_mmioh_high_uv3(0, min_pnode, max_pnode); | |
605 | map_mmioh_high_uv3(1, min_pnode, max_pnode); | |
606 | return; | |
2a919596 | 607 | } |
b15cc4a1 MT |
608 | |
609 | if (is_uv1_hub()) { | |
610 | mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR; | |
611 | shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
612 | mmioh.v = uv_read_local_mmr(mmr); | |
613 | enable = !!mmioh.s1.enable; | |
614 | base = mmioh.s1.base; | |
615 | m_io = mmioh.s1.m_io; | |
616 | n_io = mmioh.s1.n_io; | |
617 | } else if (is_uv2_hub()) { | |
618 | mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR; | |
2a919596 | 619 | shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; |
b15cc4a1 MT |
620 | mmioh.v = uv_read_local_mmr(mmr); |
621 | enable = !!mmioh.s2.enable; | |
622 | base = mmioh.s2.base; | |
623 | m_io = mmioh.s2.m_io; | |
624 | n_io = mmioh.s2.n_io; | |
625 | } else | |
626 | return; | |
627 | ||
628 | if (enable) { | |
629 | max_pnode &= (1 << n_io) - 1; | |
630 | pr_info( | |
631 | "UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n", | |
632 | base, shift, m_io, n_io, max_pnode); | |
633 | map_high("MMIOH", base, shift, m_io, max_pnode, map_uc); | |
634 | } else { | |
635 | pr_info("UV: MMIOH disabled\n"); | |
2a919596 | 636 | } |
83f5d894 JS |
637 | } |
638 | ||
918bc960 JS |
639 | static __init void map_low_mmrs(void) |
640 | { | |
641 | init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE); | |
642 | init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE); | |
643 | } | |
644 | ||
7019cc2d RA |
645 | static __init void uv_rtc_init(void) |
646 | { | |
922402f1 RA |
647 | long status; |
648 | u64 ticks_per_sec; | |
7019cc2d | 649 | |
922402f1 RA |
650 | status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, |
651 | &ticks_per_sec); | |
652 | if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) { | |
7019cc2d RA |
653 | printk(KERN_WARNING |
654 | "unable to determine platform RTC clock frequency, " | |
655 | "guessing.\n"); | |
656 | /* BIOS gives wrong value for clock freq. so guess */ | |
657 | sn_rtc_cycles_per_second = 1000000000000UL / 30000UL; | |
658 | } else | |
659 | sn_rtc_cycles_per_second = ticks_per_sec; | |
660 | } | |
661 | ||
7f1baa06 MT |
662 | /* |
663 | * percpu heartbeat timer | |
664 | */ | |
665 | static void uv_heartbeat(unsigned long ignored) | |
666 | { | |
667 | struct timer_list *timer = &uv_hub_info->scir.timer; | |
668 | unsigned char bits = uv_hub_info->scir.state; | |
669 | ||
670 | /* flip heartbeat bit */ | |
671 | bits ^= SCIR_CPU_HEARTBEAT; | |
672 | ||
69a72a0e MT |
673 | /* is this cpu idle? */ |
674 | if (idle_cpu(raw_smp_processor_id())) | |
7f1baa06 MT |
675 | bits &= ~SCIR_CPU_ACTIVITY; |
676 | else | |
677 | bits |= SCIR_CPU_ACTIVITY; | |
678 | ||
679 | /* update system controller interface reg */ | |
680 | uv_set_scir_bits(bits); | |
681 | ||
682 | /* enable next timer period */ | |
5c333864 | 683 | mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL); |
7f1baa06 MT |
684 | } |
685 | ||
686 | static void __cpuinit uv_heartbeat_enable(int cpu) | |
687 | { | |
99659a92 | 688 | while (!uv_cpu_hub_info(cpu)->scir.enabled) { |
7f1baa06 MT |
689 | struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer; |
690 | ||
691 | uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY); | |
692 | setup_timer(timer, uv_heartbeat, cpu); | |
693 | timer->expires = jiffies + SCIR_CPU_HB_INTERVAL; | |
694 | add_timer_on(timer, cpu); | |
695 | uv_cpu_hub_info(cpu)->scir.enabled = 1; | |
7f1baa06 | 696 | |
99659a92 RK |
697 | /* also ensure that boot cpu is enabled */ |
698 | cpu = 0; | |
699 | } | |
7f1baa06 MT |
700 | } |
701 | ||
77be80e4 | 702 | #ifdef CONFIG_HOTPLUG_CPU |
7f1baa06 MT |
703 | static void __cpuinit uv_heartbeat_disable(int cpu) |
704 | { | |
705 | if (uv_cpu_hub_info(cpu)->scir.enabled) { | |
706 | uv_cpu_hub_info(cpu)->scir.enabled = 0; | |
707 | del_timer(&uv_cpu_hub_info(cpu)->scir.timer); | |
708 | } | |
709 | uv_set_cpu_scir_bits(cpu, 0xff); | |
710 | } | |
711 | ||
7f1baa06 MT |
712 | /* |
713 | * cpu hotplug notifier | |
714 | */ | |
715 | static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self, | |
716 | unsigned long action, void *hcpu) | |
717 | { | |
718 | long cpu = (long)hcpu; | |
719 | ||
720 | switch (action) { | |
721 | case CPU_ONLINE: | |
722 | uv_heartbeat_enable(cpu); | |
723 | break; | |
724 | case CPU_DOWN_PREPARE: | |
725 | uv_heartbeat_disable(cpu); | |
726 | break; | |
727 | default: | |
728 | break; | |
729 | } | |
730 | return NOTIFY_OK; | |
731 | } | |
732 | ||
733 | static __init void uv_scir_register_cpu_notifier(void) | |
734 | { | |
735 | hotcpu_notifier(uv_scir_cpu_notify, 0); | |
736 | } | |
737 | ||
738 | #else /* !CONFIG_HOTPLUG_CPU */ | |
739 | ||
740 | static __init void uv_scir_register_cpu_notifier(void) | |
741 | { | |
742 | } | |
743 | ||
744 | static __init int uv_init_heartbeat(void) | |
745 | { | |
746 | int cpu; | |
747 | ||
748 | if (is_uv_system()) | |
749 | for_each_online_cpu(cpu) | |
750 | uv_heartbeat_enable(cpu); | |
751 | return 0; | |
752 | } | |
753 | ||
754 | late_initcall(uv_init_heartbeat); | |
755 | ||
756 | #endif /* !CONFIG_HOTPLUG_CPU */ | |
757 | ||
841582ea MT |
758 | /* Direct Legacy VGA I/O traffic to designated IOH */ |
759 | int uv_set_vga_state(struct pci_dev *pdev, bool decode, | |
7ad35cf2 | 760 | unsigned int command_bits, u32 flags) |
841582ea MT |
761 | { |
762 | int domain, bus, rc; | |
763 | ||
7ad35cf2 DA |
764 | PR_DEVEL("devfn %x decode %d cmd %x flags %d\n", |
765 | pdev->devfn, decode, command_bits, flags); | |
841582ea | 766 | |
7ad35cf2 | 767 | if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) |
841582ea MT |
768 | return 0; |
769 | ||
770 | if ((command_bits & PCI_COMMAND_IO) == 0) | |
771 | return 0; | |
772 | ||
773 | domain = pci_domain_nr(pdev->bus); | |
774 | bus = pdev->bus->number; | |
775 | ||
776 | rc = uv_bios_set_legacy_vga_target(decode, domain, bus); | |
777 | PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc); | |
778 | ||
779 | return rc; | |
780 | } | |
781 | ||
8da077d6 JS |
782 | /* |
783 | * Called on each cpu to initialize the per_cpu UV data area. | |
0b1da1c8 | 784 | * FIXME: hotplug not supported yet |
8da077d6 JS |
785 | */ |
786 | void __cpuinit uv_cpu_init(void) | |
787 | { | |
788 | /* CPU 0 initilization will be done via uv_system_init. */ | |
789 | if (!uv_blade_info) | |
790 | return; | |
791 | ||
792 | uv_blade_info[uv_numa_blade_id()].nr_online_cpus++; | |
793 | ||
794 | if (get_uv_system_type() == UV_NON_UNIQUE_APIC) | |
795 | set_x2apic_extra_bits(uv_hub_info->pnode); | |
796 | } | |
797 | ||
78c06176 RA |
798 | /* |
799 | * When NMI is received, print a stack trace. | |
800 | */ | |
9c48f1c6 | 801 | int uv_handle_nmi(unsigned int reason, struct pt_regs *regs) |
78c06176 | 802 | { |
1d44e828 JS |
803 | unsigned long real_uv_nmi; |
804 | int bid; | |
805 | ||
78c06176 | 806 | /* |
1d44e828 JS |
807 | * Each blade has an MMR that indicates when an NMI has been sent |
808 | * to cpus on the blade. If an NMI is detected, atomically | |
809 | * clear the MMR and update a per-blade NMI count used to | |
810 | * cause each cpu on the blade to notice a new NMI. | |
811 | */ | |
812 | bid = uv_numa_blade_id(); | |
813 | real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK); | |
814 | ||
815 | if (unlikely(real_uv_nmi)) { | |
816 | spin_lock(&uv_blade_info[bid].nmi_lock); | |
817 | real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK); | |
818 | if (real_uv_nmi) { | |
819 | uv_blade_info[bid].nmi_count++; | |
820 | uv_write_local_mmr(UVH_NMI_MMR_CLEAR, UV_NMI_PENDING_MASK); | |
821 | } | |
822 | spin_unlock(&uv_blade_info[bid].nmi_lock); | |
823 | } | |
824 | ||
825 | if (likely(__get_cpu_var(cpu_last_nmi_count) == uv_blade_info[bid].nmi_count)) | |
9c48f1c6 | 826 | return NMI_DONE; |
1d44e828 JS |
827 | |
828 | __get_cpu_var(cpu_last_nmi_count) = uv_blade_info[bid].nmi_count; | |
829 | ||
830 | /* | |
831 | * Use a lock so only one cpu prints at a time. | |
832 | * This prevents intermixed output. | |
78c06176 RA |
833 | */ |
834 | spin_lock(&uv_nmi_lock); | |
1d44e828 | 835 | pr_info("UV NMI stack dump cpu %u:\n", smp_processor_id()); |
78c06176 RA |
836 | dump_stack(); |
837 | spin_unlock(&uv_nmi_lock); | |
838 | ||
9c48f1c6 | 839 | return NMI_HANDLED; |
78c06176 RA |
840 | } |
841 | ||
78c06176 RA |
842 | void uv_register_nmi_notifier(void) |
843 | { | |
9c48f1c6 | 844 | if (register_nmi_handler(NMI_UNKNOWN, uv_handle_nmi, 0, "uv")) |
78c06176 RA |
845 | printk(KERN_WARNING "UV NMI handler failed to register\n"); |
846 | } | |
847 | ||
848 | void uv_nmi_init(void) | |
849 | { | |
850 | unsigned int value; | |
851 | ||
852 | /* | |
853 | * Unmask NMI on all cpus | |
854 | */ | |
855 | value = apic_read(APIC_LVT1) | APIC_DM_NMI; | |
856 | value &= ~APIC_LVT_MASKED; | |
857 | apic_write(APIC_LVT1, value); | |
858 | } | |
c4bd1fda MS |
859 | |
860 | void __init uv_system_init(void) | |
ac23d4ee | 861 | { |
62b0cfc2 | 862 | union uvh_rh_gam_config_mmr_u m_n_config; |
9f5314fb JS |
863 | union uvh_node_id_u node_id; |
864 | unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size; | |
b15cc4a1 MT |
865 | int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val; |
866 | int gnode_extra, min_pnode = 999999, max_pnode = -1; | |
6a891a24 | 867 | unsigned long mmr_base, present, paddr; |
b15cc4a1 MT |
868 | unsigned short pnode_mask; |
869 | char *hub = (is_uv1_hub() ? "UV1" : | |
870 | (is_uv2_hub() ? "UV2" : | |
871 | "UV3")); | |
ac23d4ee | 872 | |
b15cc4a1 | 873 | pr_info("UV: Found %s hub\n", hub); |
918bc960 JS |
874 | map_low_mmrs(); |
875 | ||
62b0cfc2 | 876 | m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR ); |
9f5314fb JS |
877 | m_val = m_n_config.s.m_skt; |
878 | n_val = m_n_config.s.n_skt; | |
b15cc4a1 | 879 | pnode_mask = (1 << n_val) - 1; |
ac23d4ee JS |
880 | mmr_base = |
881 | uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & | |
882 | ~UV_MMR_ENABLE; | |
d8850ba4 | 883 | |
c4ed3f04 JS |
884 | node_id.v = uv_read_local_mmr(UVH_NODE_ID); |
885 | gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1; | |
886 | gnode_upper = ((unsigned long)gnode_extra << m_val); | |
b15cc4a1 MT |
887 | pr_info("UV: N:%d M:%d pnode_mask:0x%x gnode_upper/extra:0x%lx/0x%x\n", |
888 | n_val, m_val, pnode_mask, gnode_upper, gnode_extra); | |
c4ed3f04 | 889 | |
b15cc4a1 | 890 | pr_info("UV: global MMR base 0x%lx\n", mmr_base); |
ac23d4ee | 891 | |
9f5314fb JS |
892 | for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) |
893 | uv_possible_blades += | |
894 | hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8)); | |
da517a08 JS |
895 | |
896 | /* uv_num_possible_blades() is really the hub count */ | |
b15cc4a1 | 897 | pr_info("UV: Found %d blades, %d hubs\n", |
da517a08 JS |
898 | is_uv1_hub() ? uv_num_possible_blades() : |
899 | (uv_num_possible_blades() + 1) / 2, | |
900 | uv_num_possible_blades()); | |
ac23d4ee JS |
901 | |
902 | bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades(); | |
1d44e828 | 903 | uv_blade_info = kzalloc(bytes, GFP_KERNEL); |
9a8709d4 | 904 | BUG_ON(!uv_blade_info); |
1d44e828 | 905 | |
6c7184b7 JS |
906 | for (blade = 0; blade < uv_num_possible_blades(); blade++) |
907 | uv_blade_info[blade].memory_nid = -1; | |
ac23d4ee | 908 | |
9f5314fb JS |
909 | get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size); |
910 | ||
ac23d4ee | 911 | bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes(); |
ef020ab0 | 912 | uv_node_to_blade = kmalloc(bytes, GFP_KERNEL); |
9a8709d4 | 913 | BUG_ON(!uv_node_to_blade); |
ac23d4ee JS |
914 | memset(uv_node_to_blade, 255, bytes); |
915 | ||
916 | bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus(); | |
ef020ab0 | 917 | uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL); |
9a8709d4 | 918 | BUG_ON(!uv_cpu_to_blade); |
ac23d4ee JS |
919 | memset(uv_cpu_to_blade, 255, bytes); |
920 | ||
9f5314fb JS |
921 | blade = 0; |
922 | for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) { | |
923 | present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8); | |
924 | for (j = 0; j < 64; j++) { | |
925 | if (!test_bit(j, &present)) | |
926 | continue; | |
d8850ba4 | 927 | pnode = (i * 64 + j) & pnode_mask; |
36ac4b98 | 928 | uv_blade_info[blade].pnode = pnode; |
9f5314fb | 929 | uv_blade_info[blade].nr_possible_cpus = 0; |
ac23d4ee | 930 | uv_blade_info[blade].nr_online_cpus = 0; |
1d44e828 | 931 | spin_lock_init(&uv_blade_info[blade].nmi_lock); |
b15cc4a1 | 932 | min_pnode = min(pnode, min_pnode); |
36ac4b98 | 933 | max_pnode = max(pnode, max_pnode); |
9f5314fb | 934 | blade++; |
ac23d4ee | 935 | } |
9f5314fb | 936 | } |
ac23d4ee | 937 | |
7f594232 | 938 | uv_bios_init(); |
b76365a1 RA |
939 | uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, |
940 | &sn_region_size, &system_serial_number); | |
7019cc2d RA |
941 | uv_rtc_init(); |
942 | ||
9f5314fb | 943 | for_each_present_cpu(cpu) { |
39d30770 MT |
944 | int apicid = per_cpu(x86_cpu_to_apicid, cpu); |
945 | ||
9f5314fb | 946 | nid = cpu_to_node(cpu); |
c8f730b1 RA |
947 | /* |
948 | * apic_pnode_shift must be set before calling uv_apicid_to_pnode(); | |
949 | */ | |
d8850ba4 | 950 | uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask; |
c8f730b1 | 951 | uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift; |
2a919596 JS |
952 | uv_cpu_hub_info(cpu)->hub_revision = uv_hub_info->hub_revision; |
953 | ||
6a469e46 JS |
954 | uv_cpu_hub_info(cpu)->m_shift = 64 - m_val; |
955 | uv_cpu_hub_info(cpu)->n_lshift = is_uv2_1_hub() ? | |
956 | (m_val == 40 ? 40 : 39) : m_val; | |
957 | ||
39d30770 | 958 | pnode = uv_apicid_to_pnode(apicid); |
9f5314fb JS |
959 | blade = boot_pnode_to_blade(pnode); |
960 | lcpu = uv_blade_info[blade].nr_possible_cpus; | |
961 | uv_blade_info[blade].nr_possible_cpus++; | |
962 | ||
6c7184b7 JS |
963 | /* Any node on the blade, else will contain -1. */ |
964 | uv_blade_info[blade].memory_nid = nid; | |
965 | ||
9f5314fb | 966 | uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base; |
189f67c4 | 967 | uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size; |
9f5314fb | 968 | uv_cpu_hub_info(cpu)->m_val = m_val; |
036ed8ba | 969 | uv_cpu_hub_info(cpu)->n_val = n_val; |
ac23d4ee JS |
970 | uv_cpu_hub_info(cpu)->numa_blade_id = blade; |
971 | uv_cpu_hub_info(cpu)->blade_processor_id = lcpu; | |
9f5314fb | 972 | uv_cpu_hub_info(cpu)->pnode = pnode; |
036ed8ba | 973 | uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1; |
9f5314fb | 974 | uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper; |
c4ed3f04 | 975 | uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra; |
ac23d4ee | 976 | uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base; |
b0f20989 | 977 | uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id; |
39d30770 | 978 | uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid); |
ac23d4ee JS |
979 | uv_node_to_blade[nid] = blade; |
980 | uv_cpu_to_blade[cpu] = blade; | |
ac23d4ee | 981 | } |
83f5d894 | 982 | |
6a891a24 JS |
983 | /* Add blade/pnode info for nodes without cpus */ |
984 | for_each_online_node(nid) { | |
985 | if (uv_node_to_blade[nid] >= 0) | |
986 | continue; | |
987 | paddr = node_start_pfn(nid) << PAGE_SHIFT; | |
6a469e46 | 988 | pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr)); |
6a891a24 JS |
989 | blade = boot_pnode_to_blade(pnode); |
990 | uv_node_to_blade[nid] = blade; | |
991 | } | |
992 | ||
83f5d894 | 993 | map_gru_high(max_pnode); |
daf7b9c9 | 994 | map_mmr_high(max_pnode); |
b15cc4a1 | 995 | map_mmioh_high(min_pnode, max_pnode); |
ac23d4ee | 996 | |
8da077d6 | 997 | uv_cpu_init(); |
7f1baa06 | 998 | uv_scir_register_cpu_notifier(); |
78c06176 | 999 | uv_register_nmi_notifier(); |
a3d732f9 | 1000 | proc_mkdir("sgi_uv", NULL); |
841582ea MT |
1001 | |
1002 | /* register Legacy VGA I/O redirection handler */ | |
1003 | pci_register_set_vga_state(uv_set_vga_state); | |
818987e9 CW |
1004 | |
1005 | /* | |
1006 | * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as | |
1007 | * EFI is not enabled in the kdump kernel. | |
1008 | */ | |
1009 | if (is_kdump_kernel()) | |
1010 | reboot_type = BOOT_ACPI; | |
ac23d4ee | 1011 | } |
107e0e0c SS |
1012 | |
1013 | apic_driver(apic_x2apic_uv_x); |