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KVM: use proper hrtimer function to retrieve expiration time
[deliverable/linux.git] / arch / x86 / kvm / mmu.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 *
11 * Authors:
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
14 *
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
17 *
18 */
e495606d 19
1d737c8a 20#include "mmu.h"
6de4f3ad 21#include "kvm_cache_regs.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732
AK		 24#include <linux/types.h>
25#include <linux/string.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
28#include <linux/module.h>
448353ca 29#include <linux/swap.h>
05da4558 30#include <linux/hugetlb.h>
2f333bcb 31#include <linux/compiler.h>
6aa8b732 32
e495606d
AK		 33#include <asm/page.h>
34#include <asm/cmpxchg.h>
4e542370 35#include <asm/io.h>
13673a90 36#include <asm/vmx.h>
6aa8b732 37
18552672
JR		 38/*
39 * When setting this variable to true it enables Two-Dimensional-Paging
40 * where the hardware walks 2 page tables:
41 * 1. the guest-virtual to guest-physical
42 * 2. while doing 1. it walks guest-physical to host-physical
43 * If the hardware supports that we don't need to do shadow paging.
44 */
2f333bcb 45bool tdp_enabled = false;
18552672 46
37a7d8b0
AK		 47#undef MMU_DEBUG
48
49#undef AUDIT
50
51#ifdef AUDIT
52static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg);
53#else
54static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {}
55#endif
56
57#ifdef MMU_DEBUG
58
59#define pgprintk(x...) do { if (dbg) printk(x); } while (0)
60#define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
61
62#else
63
64#define pgprintk(x...) do { } while (0)
65#define rmap_printk(x...) do { } while (0)
66
67#endif
68
69#if defined(MMU_DEBUG) || defined(AUDIT)
6ada8cca
AK		 70static int dbg = 0;
71module_param(dbg, bool, 0644);
37a7d8b0 72#endif
6aa8b732 73
582801a9
MT		 74static int oos_shadow = 1;
75module_param(oos_shadow, bool, 0644);
76
d6c69ee9
YD		 77#ifndef MMU_DEBUG
78#define ASSERT(x) do { } while (0)
79#else
6aa8b732
AK		 80#define ASSERT(x) \
81 if (!(x)) { \
82 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
83 __FILE__, __LINE__, #x); \
84 }
d6c69ee9 85#endif
6aa8b732 86
6aa8b732
AK		 87#define PT_FIRST_AVAIL_BITS_SHIFT 9
88#define PT64_SECOND_AVAIL_BITS_SHIFT 52
89
6aa8b732
AK		 90#define VALID_PAGE(x) ((x) != INVALID_PAGE)
91
92#define PT64_LEVEL_BITS 9
93
94#define PT64_LEVEL_SHIFT(level) \
d77c26fc 95 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
6aa8b732
AK		 96
97#define PT64_LEVEL_MASK(level) \
98 (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
99
100#define PT64_INDEX(address, level)\
101 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
102
103
104#define PT32_LEVEL_BITS 10
105
106#define PT32_LEVEL_SHIFT(level) \
d77c26fc 107 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
6aa8b732
AK		 108
109#define PT32_LEVEL_MASK(level) \
110 (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
e04da980
JR		 111#define PT32_LVL_OFFSET_MASK(level) \
112 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
113 * PT32_LEVEL_BITS))) - 1))
6aa8b732
AK		 114
115#define PT32_INDEX(address, level)\
116 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
117
118
27aba766 119#define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
6aa8b732
AK		 120#define PT64_DIR_BASE_ADDR_MASK \
121 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
e04da980
JR		 122#define PT64_LVL_ADDR_MASK(level) \
123 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
124 * PT64_LEVEL_BITS))) - 1))
125#define PT64_LVL_OFFSET_MASK(level) \
126 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
127 * PT64_LEVEL_BITS))) - 1))
6aa8b732
AK		 128
129#define PT32_BASE_ADDR_MASK PAGE_MASK
130#define PT32_DIR_BASE_ADDR_MASK \
131 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
e04da980
JR		 132#define PT32_LVL_ADDR_MASK(level) \
133 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
134 * PT32_LEVEL_BITS))) - 1))
6aa8b732 135
79539cec
AK		 136#define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
137 | PT64_NX_MASK)
6aa8b732
AK		 138
139#define PFERR_PRESENT_MASK (1U << 0)
140#define PFERR_WRITE_MASK (1U << 1)
141#define PFERR_USER_MASK (1U << 2)
82725b20 142#define PFERR_RSVD_MASK (1U << 3)
73b1087e 143#define PFERR_FETCH_MASK (1U << 4)
6aa8b732 144
e04da980 145#define PT_PDPE_LEVEL 3
6aa8b732
AK		 146#define PT_DIRECTORY_LEVEL 2
147#define PT_PAGE_TABLE_LEVEL 1
148
cd4a4e53
AK		 149#define RMAP_EXT 4
150
fe135d2c
AK		 151#define ACC_EXEC_MASK 1
152#define ACC_WRITE_MASK PT_WRITABLE_MASK
153#define ACC_USER_MASK PT_USER_MASK
154#define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
155
07420171
AK		 156#define CREATE_TRACE_POINTS
157#include "mmutrace.h"
158
1403283a
IE		 159#define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
160
135f8c2b
AK		 161#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
162
cd4a4e53 163struct kvm_rmap_desc {
d555c333 164 u64 *sptes[RMAP_EXT];
cd4a4e53
AK		 165 struct kvm_rmap_desc *more;
166};
167
2d11123a
AK		 168struct kvm_shadow_walk_iterator {
169 u64 addr;
170 hpa_t shadow_addr;
171 int level;
172 u64 *sptep;
173 unsigned index;
174};
175
176#define for_each_shadow_entry(_vcpu, _addr, _walker) \
177 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
178 shadow_walk_okay(&(_walker)); \
179 shadow_walk_next(&(_walker)))
180
181
4731d4c7
MT		 182struct kvm_unsync_walk {
183 int (*entry) (struct kvm_mmu_page *sp, struct kvm_unsync_walk *walk);
184};
185
ad8cfbe3
MT		 186typedef int (*mmu_parent_walk_fn) (struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp);
187
b5a33a75
AK		 188static struct kmem_cache *pte_chain_cache;
189static struct kmem_cache *rmap_desc_cache;
d3d25b04 190static struct kmem_cache *mmu_page_header_cache;
b5a33a75 191
c7addb90
AK		 192static u64 __read_mostly shadow_trap_nonpresent_pte;
193static u64 __read_mostly shadow_notrap_nonpresent_pte;
7b52345e
SY		 194static u64 __read_mostly shadow_base_present_pte;
195static u64 __read_mostly shadow_nx_mask;
196static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
197static u64 __read_mostly shadow_user_mask;
198static u64 __read_mostly shadow_accessed_mask;
199static u64 __read_mostly shadow_dirty_mask;
c7addb90 200
82725b20
DE		 201static inline u64 rsvd_bits(int s, int e)
202{
203 return ((1ULL << (e - s + 1)) - 1) << s;
204}
205
c7addb90
AK		 206void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
207{
208 shadow_trap_nonpresent_pte = trap_pte;
209 shadow_notrap_nonpresent_pte = notrap_pte;
210}
211EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
212
7b52345e
SY		 213void kvm_mmu_set_base_ptes(u64 base_pte)
214{
215 shadow_base_present_pte = base_pte;
216}
217EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes);
218
219void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
4b12f0de 220 u64 dirty_mask, u64 nx_mask, u64 x_mask)
7b52345e
SY		 221{
222 shadow_user_mask = user_mask;
223 shadow_accessed_mask = accessed_mask;
224 shadow_dirty_mask = dirty_mask;
225 shadow_nx_mask = nx_mask;
226 shadow_x_mask = x_mask;
227}
228EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
229
6aa8b732
AK		 230static int is_write_protection(struct kvm_vcpu *vcpu)
231{
ad312c7c 232 return vcpu->arch.cr0 & X86_CR0_WP;
6aa8b732
AK		 233}
234
235static int is_cpuid_PSE36(void)
236{
237 return 1;
238}
239
73b1087e
AK		 240static int is_nx(struct kvm_vcpu *vcpu)
241{
ad312c7c 242 return vcpu->arch.shadow_efer & EFER_NX;
73b1087e
AK		 243}
244
c7addb90
AK		 245static int is_shadow_present_pte(u64 pte)
246{
c7addb90
AK		 247 return pte != shadow_trap_nonpresent_pte
248 && pte != shadow_notrap_nonpresent_pte;
249}
250
05da4558
MT		 251static int is_large_pte(u64 pte)
252{
253 return pte & PT_PAGE_SIZE_MASK;
254}
255
6aa8b732
AK		 256static int is_writeble_pte(unsigned long pte)
257{
258 return pte & PT_WRITABLE_MASK;
259}
260
43a3795a 261static int is_dirty_gpte(unsigned long pte)
e3c5e7ec 262{
439e218a 263 return pte & PT_DIRTY_MASK;
e3c5e7ec
AK		 264}
265
43a3795a 266static int is_rmap_spte(u64 pte)
cd4a4e53 267{
4b1a80fa 268 return is_shadow_present_pte(pte);
cd4a4e53
AK		 269}
270
776e6633
MT		 271static int is_last_spte(u64 pte, int level)
272{
273 if (level == PT_PAGE_TABLE_LEVEL)
274 return 1;
852e3c19 275 if (is_large_pte(pte))
776e6633
MT		 276 return 1;
277 return 0;
278}
279
35149e21 280static pfn_t spte_to_pfn(u64 pte)
0b49ea86 281{
35149e21 282 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
0b49ea86
AK		 283}
284
da928521
AK		 285static gfn_t pse36_gfn_delta(u32 gpte)
286{
287 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
288
289 return (gpte & PT32_DIR_PSE36_MASK) << shift;
290}
291
d555c333 292static void __set_spte(u64 *sptep, u64 spte)
e663ee64
AK		 293{
294#ifdef CONFIG_X86_64
295 set_64bit((unsigned long *)sptep, spte);
296#else
297 set_64bit((unsigned long long *)sptep, spte);
298#endif
299}
300
e2dec939 301static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
2e3e5882 302 struct kmem_cache *base_cache, int min)
714b93da
AK		 303{
304 void *obj;
305
306 if (cache->nobjs >= min)
e2dec939 307 return 0;
714b93da 308 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 309 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
714b93da 310 if (!obj)
e2dec939 311 return -ENOMEM;
714b93da
AK		 312 cache->objects[cache->nobjs++] = obj;
313 }
e2dec939 314 return 0;
714b93da
AK		 315}
316
317static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc)
318{
319 while (mc->nobjs)
320 kfree(mc->objects[--mc->nobjs]);
321}
322
c1158e63 323static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
2e3e5882 324 int min)
c1158e63
AK		 325{
326 struct page *page;
327
328 if (cache->nobjs >= min)
329 return 0;
330 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 331 page = alloc_page(GFP_KERNEL);
c1158e63
AK		 332 if (!page)
333 return -ENOMEM;
334 set_page_private(page, 0);
335 cache->objects[cache->nobjs++] = page_address(page);
336 }
337 return 0;
338}
339
340static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
341{
342 while (mc->nobjs)
c4d198d5 343 free_page((unsigned long)mc->objects[--mc->nobjs]);
c1158e63
AK		 344}
345
2e3e5882 346static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
714b93da 347{
e2dec939
AK		 348 int r;
349
ad312c7c 350 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache,
2e3e5882 351 pte_chain_cache, 4);
e2dec939
AK		 352 if (r)
353 goto out;
ad312c7c 354 r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache,
c41ef344 355 rmap_desc_cache, 4);
d3d25b04
AK		 356 if (r)
357 goto out;
ad312c7c 358 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
d3d25b04
AK		 359 if (r)
360 goto out;
ad312c7c 361 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
2e3e5882 362 mmu_page_header_cache, 4);
e2dec939
AK		 363out:
364 return r;
714b93da
AK		 365}
366
367static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
368{
ad312c7c
ZX		 369 mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache);
370 mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache);
371 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
372 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
714b93da
AK		 373}
374
375static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
376 size_t size)
377{
378 void *p;
379
380 BUG_ON(!mc->nobjs);
381 p = mc->objects[--mc->nobjs];
714b93da
AK		 382 return p;
383}
384
714b93da
AK		 385static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu)
386{
ad312c7c 387 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache,
714b93da
AK		 388 sizeof(struct kvm_pte_chain));
389}
390
90cb0529 391static void mmu_free_pte_chain(struct kvm_pte_chain *pc)
714b93da 392{
90cb0529 393 kfree(pc);
714b93da
AK		 394}
395
396static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu)
397{
ad312c7c 398 return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache,
714b93da
AK		 399 sizeof(struct kvm_rmap_desc));
400}
401
90cb0529 402static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd)
714b93da 403{
90cb0529 404 kfree(rd);
714b93da
AK		 405}
406
05da4558
MT		 407/*
408 * Return the pointer to the largepage write count for a given
409 * gfn, handling slots that are not large page aligned.
410 */
d25797b2
JR		 411static int *slot_largepage_idx(gfn_t gfn,
412 struct kvm_memory_slot *slot,
413 int level)
05da4558
MT		 414{
415 unsigned long idx;
416
d25797b2
JR		 417 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
418 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
419 return &slot->lpage_info[level - 2][idx].write_count;
05da4558
MT		 420}
421
422static void account_shadowed(struct kvm *kvm, gfn_t gfn)
423{
d25797b2 424 struct kvm_memory_slot *slot;
05da4558 425 int *write_count;
d25797b2 426 int i;
05da4558 427
2843099f 428 gfn = unalias_gfn(kvm, gfn);
d25797b2
JR		 429
430 slot = gfn_to_memslot_unaliased(kvm, gfn);
431 for (i = PT_DIRECTORY_LEVEL;
432 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
433 write_count = slot_largepage_idx(gfn, slot, i);
434 *write_count += 1;
435 }
05da4558
MT		 436}
437
438static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
439{
d25797b2 440 struct kvm_memory_slot *slot;
05da4558 441 int *write_count;
d25797b2 442 int i;
05da4558 443
2843099f 444 gfn = unalias_gfn(kvm, gfn);
d25797b2
JR		 445 for (i = PT_DIRECTORY_LEVEL;
446 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
447 slot = gfn_to_memslot_unaliased(kvm, gfn);
448 write_count = slot_largepage_idx(gfn, slot, i);
449 *write_count -= 1;
450 WARN_ON(*write_count < 0);
451 }
05da4558
MT		 452}
453
d25797b2
JR		 454static int has_wrprotected_page(struct kvm *kvm,
455 gfn_t gfn,
456 int level)
05da4558 457{
2843099f 458 struct kvm_memory_slot *slot;
05da4558
MT		 459 int *largepage_idx;
460
2843099f
IE		 461 gfn = unalias_gfn(kvm, gfn);
462 slot = gfn_to_memslot_unaliased(kvm, gfn);
05da4558 463 if (slot) {
d25797b2 464 largepage_idx = slot_largepage_idx(gfn, slot, level);
05da4558
MT		 465 return *largepage_idx;
466 }
467
468 return 1;
469}
470
d25797b2 471static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
05da4558 472{
d25797b2 473 unsigned long page_size = PAGE_SIZE;
05da4558
MT		 474 struct vm_area_struct *vma;
475 unsigned long addr;
d25797b2 476 int i, ret = 0;
05da4558
MT		 477
478 addr = gfn_to_hva(kvm, gfn);
479 if (kvm_is_error_hva(addr))
d25797b2 480 return page_size;
05da4558 481
4c2155ce 482 down_read(&current->mm->mmap_sem);
05da4558 483 vma = find_vma(current->mm, addr);
d25797b2
JR		 484 if (!vma)
485 goto out;
486
487 page_size = vma_kernel_pagesize(vma);
488
489out:
4c2155ce 490 up_read(&current->mm->mmap_sem);
05da4558 491
d25797b2
JR		 492 for (i = PT_PAGE_TABLE_LEVEL;
493 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
494 if (page_size >= KVM_HPAGE_SIZE(i))
495 ret = i;
496 else
497 break;
498 }
499
4c2155ce 500 return ret;
05da4558
MT		 501}
502
d25797b2 503static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
05da4558
MT		 504{
505 struct kvm_memory_slot *slot;
d25797b2
JR		 506 int host_level;
507 int level = PT_PAGE_TABLE_LEVEL;
05da4558
MT		 508
509 slot = gfn_to_memslot(vcpu->kvm, large_gfn);
510 if (slot && slot->dirty_bitmap)
d25797b2 511 return PT_PAGE_TABLE_LEVEL;
05da4558 512
d25797b2
JR		 513 host_level = host_mapping_level(vcpu->kvm, large_gfn);
514
515 if (host_level == PT_PAGE_TABLE_LEVEL)
516 return host_level;
517
518 for (level = PT_DIRECTORY_LEVEL; level <= host_level; ++level) {
519
520 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
521 break;
522 }
523
524 return level - 1;
05da4558
MT		 525}
526
290fc38d
IE		 527/*
528 * Take gfn and return the reverse mapping to it.
529 * Note: gfn must be unaliased before this function get called
530 */
531
44ad9944 532static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
290fc38d
IE		 533{
534 struct kvm_memory_slot *slot;
05da4558 535 unsigned long idx;
290fc38d
IE		 536
537 slot = gfn_to_memslot(kvm, gfn);
44ad9944 538 if (likely(level == PT_PAGE_TABLE_LEVEL))
05da4558
MT		 539 return &slot->rmap[gfn - slot->base_gfn];
540
44ad9944
JR		 541 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
542 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
05da4558 543
44ad9944 544 return &slot->lpage_info[level - 2][idx].rmap_pde;
290fc38d
IE		 545}
546
cd4a4e53
AK		 547/*
548 * Reverse mapping data structures:
549 *
290fc38d
IE		 550 * If rmapp bit zero is zero, then rmapp point to the shadw page table entry
551 * that points to page_address(page).
cd4a4e53 552 *
290fc38d
IE		 553 * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc
554 * containing more mappings.
53a27b39
MT		 555 *
556 * Returns the number of rmap entries before the spte was added or zero if
557 * the spte was not added.
558 *
cd4a4e53 559 */
44ad9944 560static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
cd4a4e53 561{
4db35314 562 struct kvm_mmu_page *sp;
cd4a4e53 563 struct kvm_rmap_desc *desc;
290fc38d 564 unsigned long *rmapp;
53a27b39 565 int i, count = 0;
cd4a4e53 566
43a3795a 567 if (!is_rmap_spte(*spte))
53a27b39 568 return count;
290fc38d 569 gfn = unalias_gfn(vcpu->kvm, gfn);
4db35314
AK		 570 sp = page_header(__pa(spte));
571 sp->gfns[spte - sp->spt] = gfn;
44ad9944 572 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
290fc38d 573 if (!*rmapp) {
cd4a4e53 574 rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte);
290fc38d
IE		 575 *rmapp = (unsigned long)spte;
576 } else if (!(*rmapp & 1)) {
cd4a4e53 577 rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte);
714b93da 578 desc = mmu_alloc_rmap_desc(vcpu);
d555c333
AK		 579 desc->sptes[0] = (u64 *)*rmapp;
580 desc->sptes[1] = spte;
290fc38d 581 *rmapp = (unsigned long)desc | 1;
cd4a4e53
AK		 582 } else {
583 rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte);
290fc38d 584 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
d555c333 585 while (desc->sptes[RMAP_EXT-1] && desc->more) {
cd4a4e53 586 desc = desc->more;
53a27b39
MT		 587 count += RMAP_EXT;
588 }
d555c333 589 if (desc->sptes[RMAP_EXT-1]) {
714b93da 590 desc->more = mmu_alloc_rmap_desc(vcpu);
cd4a4e53
AK		 591 desc = desc->more;
592 }
d555c333 593 for (i = 0; desc->sptes[i]; ++i)
cd4a4e53 594 ;
d555c333 595 desc->sptes[i] = spte;
cd4a4e53 596 }
53a27b39 597 return count;
cd4a4e53
AK		 598}
599
290fc38d 600static void rmap_desc_remove_entry(unsigned long *rmapp,
cd4a4e53
AK		 601 struct kvm_rmap_desc *desc,
602 int i,
603 struct kvm_rmap_desc *prev_desc)
604{
605 int j;
606
d555c333 607 for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j)
cd4a4e53 608 ;
d555c333
AK		 609 desc->sptes[i] = desc->sptes[j];
610 desc->sptes[j] = NULL;
cd4a4e53
AK		 611 if (j != 0)
612 return;
613 if (!prev_desc && !desc->more)
d555c333 614 *rmapp = (unsigned long)desc->sptes[0];
cd4a4e53
AK		 615 else
616 if (prev_desc)
617 prev_desc->more = desc->more;
618 else
290fc38d 619 *rmapp = (unsigned long)desc->more | 1;
90cb0529 620 mmu_free_rmap_desc(desc);
cd4a4e53
AK		 621}
622
290fc38d 623static void rmap_remove(struct kvm *kvm, u64 *spte)
cd4a4e53 624{
cd4a4e53
AK		 625 struct kvm_rmap_desc *desc;
626 struct kvm_rmap_desc *prev_desc;
4db35314 627 struct kvm_mmu_page *sp;
35149e21 628 pfn_t pfn;
290fc38d 629 unsigned long *rmapp;
cd4a4e53
AK		 630 int i;
631
43a3795a 632 if (!is_rmap_spte(*spte))
cd4a4e53 633 return;
4db35314 634 sp = page_header(__pa(spte));
35149e21 635 pfn = spte_to_pfn(*spte);
7b52345e 636 if (*spte & shadow_accessed_mask)
35149e21 637 kvm_set_pfn_accessed(pfn);
b4231d61 638 if (is_writeble_pte(*spte))
acb66dd0 639 kvm_set_pfn_dirty(pfn);
44ad9944 640 rmapp = gfn_to_rmap(kvm, sp->gfns[spte - sp->spt], sp->role.level);
290fc38d 641 if (!*rmapp) {
cd4a4e53
AK		 642 printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte);
643 BUG();
290fc38d 644 } else if (!(*rmapp & 1)) {
cd4a4e53 645 rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte);
290fc38d 646 if ((u64 *)*rmapp != spte) {
cd4a4e53
AK		 647 printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n",
648 spte, *spte);
649 BUG();
650 }
290fc38d 651 *rmapp = 0;
cd4a4e53
AK		 652 } else {
653 rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte);
290fc38d 654 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
cd4a4e53
AK		 655 prev_desc = NULL;
656 while (desc) {
d555c333
AK		 657 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i)
658 if (desc->sptes[i] == spte) {
290fc38d 659 rmap_desc_remove_entry(rmapp,
714b93da 660 desc, i,
cd4a4e53
AK		 661 prev_desc);
662 return;
663 }
664 prev_desc = desc;
665 desc = desc->more;
666 }
667 BUG();
668 }
669}
670
98348e95 671static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
374cbac0 672{
374cbac0 673 struct kvm_rmap_desc *desc;
98348e95
IE		 674 struct kvm_rmap_desc *prev_desc;
675 u64 *prev_spte;
676 int i;
677
678 if (!*rmapp)
679 return NULL;
680 else if (!(*rmapp & 1)) {
681 if (!spte)
682 return (u64 *)*rmapp;
683 return NULL;
684 }
685 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
686 prev_desc = NULL;
687 prev_spte = NULL;
688 while (desc) {
d555c333 689 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) {
98348e95 690 if (prev_spte == spte)
d555c333
AK		 691 return desc->sptes[i];
692 prev_spte = desc->sptes[i];
98348e95
IE		 693 }
694 desc = desc->more;
695 }
696 return NULL;
697}
698
b1a36821 699static int rmap_write_protect(struct kvm *kvm, u64 gfn)
98348e95 700{
290fc38d 701 unsigned long *rmapp;
374cbac0 702 u64 *spte;
44ad9944 703 int i, write_protected = 0;
374cbac0 704
4a4c9924 705 gfn = unalias_gfn(kvm, gfn);
44ad9944 706 rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
374cbac0 707
98348e95
IE		 708 spte = rmap_next(kvm, rmapp, NULL);
709 while (spte) {
374cbac0 710 BUG_ON(!spte);
374cbac0 711 BUG_ON(!(*spte & PT_PRESENT_MASK));
374cbac0 712 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
caa5b8a5 713 if (is_writeble_pte(*spte)) {
d555c333 714 __set_spte(spte, *spte & ~PT_WRITABLE_MASK);
caa5b8a5
ED		 715 write_protected = 1;
716 }
9647c14c 717 spte = rmap_next(kvm, rmapp, spte);
374cbac0 718 }
855149aa 719 if (write_protected) {
35149e21 720 pfn_t pfn;
855149aa
IE		 721
722 spte = rmap_next(kvm, rmapp, NULL);
35149e21
AL		 723 pfn = spte_to_pfn(*spte);
724 kvm_set_pfn_dirty(pfn);
855149aa
IE		 725 }
726
05da4558 727 /* check for huge page mappings */
44ad9944
JR		 728 for (i = PT_DIRECTORY_LEVEL;
729 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
730 rmapp = gfn_to_rmap(kvm, gfn, i);
731 spte = rmap_next(kvm, rmapp, NULL);
732 while (spte) {
733 BUG_ON(!spte);
734 BUG_ON(!(*spte & PT_PRESENT_MASK));
735 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
736 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
737 if (is_writeble_pte(*spte)) {
738 rmap_remove(kvm, spte);
739 --kvm->stat.lpages;
740 __set_spte(spte, shadow_trap_nonpresent_pte);
741 spte = NULL;
742 write_protected = 1;
743 }
744 spte = rmap_next(kvm, rmapp, spte);
05da4558 745 }
05da4558
MT		 746 }
747
b1a36821 748 return write_protected;
374cbac0
AK		 749}
750
3da0dd43 751static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp, u64 data)
e930bffe
AA		 752{
753 u64 *spte;
754 int need_tlb_flush = 0;
755
756 while ((spte = rmap_next(kvm, rmapp, NULL))) {
757 BUG_ON(!(*spte & PT_PRESENT_MASK));
758 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
759 rmap_remove(kvm, spte);
d555c333 760 __set_spte(spte, shadow_trap_nonpresent_pte);
e930bffe
AA		 761 need_tlb_flush = 1;
762 }
763 return need_tlb_flush;
764}
765
3da0dd43
IE		 766static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp, u64 data)
767{
768 int need_flush = 0;
769 u64 *spte, new_spte;
770 pte_t *ptep = (pte_t *)data;
771 pfn_t new_pfn;
772
773 WARN_ON(pte_huge(*ptep));
774 new_pfn = pte_pfn(*ptep);
775 spte = rmap_next(kvm, rmapp, NULL);
776 while (spte) {
777 BUG_ON(!is_shadow_present_pte(*spte));
778 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
779 need_flush = 1;
780 if (pte_write(*ptep)) {
781 rmap_remove(kvm, spte);
782 __set_spte(spte, shadow_trap_nonpresent_pte);
783 spte = rmap_next(kvm, rmapp, NULL);
784 } else {
785 new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
786 new_spte |= (u64)new_pfn << PAGE_SHIFT;
787
788 new_spte &= ~PT_WRITABLE_MASK;
789 new_spte &= ~SPTE_HOST_WRITEABLE;
790 if (is_writeble_pte(*spte))
791 kvm_set_pfn_dirty(spte_to_pfn(*spte));
792 __set_spte(spte, new_spte);
793 spte = rmap_next(kvm, rmapp, spte);
794 }
795 }
796 if (need_flush)
797 kvm_flush_remote_tlbs(kvm);
798
799 return 0;
800}
801
802static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, u64 data,
803 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
804 u64 data))
e930bffe 805{
852e3c19 806 int i, j;
e930bffe
AA		 807 int retval = 0;
808
809 /*
810 * If mmap_sem isn't taken, we can look the memslots with only
811 * the mmu_lock by skipping over the slots with userspace_addr == 0.
812 */
813 for (i = 0; i < kvm->nmemslots; i++) {
814 struct kvm_memory_slot *memslot = &kvm->memslots[i];
815 unsigned long start = memslot->userspace_addr;
816 unsigned long end;
817
818 /* mmu_lock protects userspace_addr */
819 if (!start)
820 continue;
821
822 end = start + (memslot->npages << PAGE_SHIFT);
823 if (hva >= start && hva < end) {
824 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
852e3c19 825
3da0dd43
IE		 826 retval |= handler(kvm, &memslot->rmap[gfn_offset],
827 data);
852e3c19
JR		 828
829 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
830 int idx = gfn_offset;
831 idx /= KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL + j);
832 retval |= handler(kvm,
3da0dd43
IE		 833 &memslot->lpage_info[j][idx].rmap_pde,
834 data);
852e3c19 835 }
e930bffe
AA		 836 }
837 }
838
839 return retval;
840}
841
842int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
843{
3da0dd43
IE		 844 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
845}
846
847void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
848{
849 kvm_handle_hva(kvm, hva, (u64)&pte, kvm_set_pte_rmapp);
e930bffe
AA		 850}
851
3da0dd43 852static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp, u64 data)
e930bffe
AA		 853{
854 u64 *spte;
855 int young = 0;
856
534e38b4
SY		 857 /* always return old for EPT */
858 if (!shadow_accessed_mask)
859 return 0;
860
e930bffe
AA		 861 spte = rmap_next(kvm, rmapp, NULL);
862 while (spte) {
863 int _young;
864 u64 _spte = *spte;
865 BUG_ON(!(_spte & PT_PRESENT_MASK));
866 _young = _spte & PT_ACCESSED_MASK;
867 if (_young) {
868 young = 1;
869 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
870 }
871 spte = rmap_next(kvm, rmapp, spte);
872 }
873 return young;
874}
875
53a27b39
MT		 876#define RMAP_RECYCLE_THRESHOLD 1000
877
852e3c19 878static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
53a27b39
MT		 879{
880 unsigned long *rmapp;
852e3c19
JR		 881 struct kvm_mmu_page *sp;
882
883 sp = page_header(__pa(spte));
53a27b39
MT		 884
885 gfn = unalias_gfn(vcpu->kvm, gfn);
852e3c19 886 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
53a27b39 887
3da0dd43 888 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
53a27b39
MT		 889 kvm_flush_remote_tlbs(vcpu->kvm);
890}
891
e930bffe
AA		 892int kvm_age_hva(struct kvm *kvm, unsigned long hva)
893{
3da0dd43 894 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
e930bffe
AA		 895}
896
d6c69ee9 897#ifdef MMU_DEBUG
47ad8e68 898static int is_empty_shadow_page(u64 *spt)
6aa8b732 899{
139bdb2d
AK		 900 u64 *pos;
901 u64 *end;
902
47ad8e68 903 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
3c915510 904 if (is_shadow_present_pte(*pos)) {
b8688d51 905 printk(KERN_ERR "%s: %p %llx\n", __func__,
139bdb2d 906 pos, *pos);
6aa8b732 907 return 0;
139bdb2d 908 }
6aa8b732
AK		 909 return 1;
910}
d6c69ee9 911#endif
6aa8b732 912
4db35314 913static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
260746c0 914{
4db35314
AK		 915 ASSERT(is_empty_shadow_page(sp->spt));
916 list_del(&sp->link);
917 __free_page(virt_to_page(sp->spt));
918 __free_page(virt_to_page(sp->gfns));
919 kfree(sp);
f05e70ac 920 ++kvm->arch.n_free_mmu_pages;
260746c0
AK		 921}
922
cea0f0e7
AK		 923static unsigned kvm_page_table_hashfn(gfn_t gfn)
924{
1ae0a13d 925 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
cea0f0e7
AK		 926}
927
25c0de2c
AK		 928static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
929 u64 *parent_pte)
6aa8b732 930{
4db35314 931 struct kvm_mmu_page *sp;
6aa8b732 932
ad312c7c
ZX		 933 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp);
934 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
935 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
4db35314 936 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
f05e70ac 937 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
6cffe8ca 938 INIT_LIST_HEAD(&sp->oos_link);
291f26bc 939 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
4db35314
AK		 940 sp->multimapped = 0;
941 sp->parent_pte = parent_pte;
f05e70ac 942 --vcpu->kvm->arch.n_free_mmu_pages;
4db35314 943 return sp;
6aa8b732
AK		 944}
945
714b93da 946static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
4db35314 947 struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7
AK		 948{
949 struct kvm_pte_chain *pte_chain;
950 struct hlist_node *node;
951 int i;
952
953 if (!parent_pte)
954 return;
4db35314
AK		 955 if (!sp->multimapped) {
956 u64 *old = sp->parent_pte;
cea0f0e7
AK		 957
958 if (!old) {
4db35314 959 sp->parent_pte = parent_pte;
cea0f0e7
AK		 960 return;
961 }
4db35314 962 sp->multimapped = 1;
714b93da 963 pte_chain = mmu_alloc_pte_chain(vcpu);
4db35314
AK		 964 INIT_HLIST_HEAD(&sp->parent_ptes);
965 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 966 pte_chain->parent_ptes[0] = old;
967 }
4db35314 968 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) {
cea0f0e7
AK		 969 if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1])
970 continue;
971 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i)
972 if (!pte_chain->parent_ptes[i]) {
973 pte_chain->parent_ptes[i] = parent_pte;
974 return;
975 }
976 }
714b93da 977 pte_chain = mmu_alloc_pte_chain(vcpu);
cea0f0e7 978 BUG_ON(!pte_chain);
4db35314 979 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
cea0f0e7
AK		 980 pte_chain->parent_ptes[0] = parent_pte;
981}
982
4db35314 983static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
cea0f0e7
AK		 984 u64 *parent_pte)
985{
986 struct kvm_pte_chain *pte_chain;
987 struct hlist_node *node;
988 int i;
989
4db35314
AK		 990 if (!sp->multimapped) {
991 BUG_ON(sp->parent_pte != parent_pte);
992 sp->parent_pte = NULL;
cea0f0e7
AK		 993 return;
994 }
4db35314 995 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
cea0f0e7
AK		 996 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
997 if (!pte_chain->parent_ptes[i])
998 break;
999 if (pte_chain->parent_ptes[i] != parent_pte)
1000 continue;
697fe2e2
AK		 1001 while (i + 1 < NR_PTE_CHAIN_ENTRIES
1002 && pte_chain->parent_ptes[i + 1]) {
cea0f0e7
AK		 1003 pte_chain->parent_ptes[i]
1004 = pte_chain->parent_ptes[i + 1];
1005 ++i;
1006 }
1007 pte_chain->parent_ptes[i] = NULL;
697fe2e2
AK		 1008 if (i == 0) {
1009 hlist_del(&pte_chain->link);
90cb0529 1010 mmu_free_pte_chain(pte_chain);
4db35314
AK		 1011 if (hlist_empty(&sp->parent_ptes)) {
1012 sp->multimapped = 0;
1013 sp->parent_pte = NULL;
697fe2e2
AK		 1014 }
1015 }
cea0f0e7
AK		 1016 return;
1017 }
1018 BUG();
1019}
1020
ad8cfbe3
MT		 1021
1022static void mmu_parent_walk(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1023 mmu_parent_walk_fn fn)
1024{
1025 struct kvm_pte_chain *pte_chain;
1026 struct hlist_node *node;
1027 struct kvm_mmu_page *parent_sp;
1028 int i;
1029
1030 if (!sp->multimapped && sp->parent_pte) {
1031 parent_sp = page_header(__pa(sp->parent_pte));
1032 fn(vcpu, parent_sp);
1033 mmu_parent_walk(vcpu, parent_sp, fn);
1034 return;
1035 }
1036 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1037 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1038 if (!pte_chain->parent_ptes[i])
1039 break;
1040 parent_sp = page_header(__pa(pte_chain->parent_ptes[i]));
1041 fn(vcpu, parent_sp);
1042 mmu_parent_walk(vcpu, parent_sp, fn);
1043 }
1044}
1045
0074ff63
MT		 1046static void kvm_mmu_update_unsync_bitmap(u64 *spte)
1047{
1048 unsigned int index;
1049 struct kvm_mmu_page *sp = page_header(__pa(spte));
1050
1051 index = spte - sp->spt;
60c8aec6
MT		 1052 if (!__test_and_set_bit(index, sp->unsync_child_bitmap))
1053 sp->unsync_children++;
1054 WARN_ON(!sp->unsync_children);
0074ff63
MT		 1055}
1056
1057static void kvm_mmu_update_parents_unsync(struct kvm_mmu_page *sp)
1058{
1059 struct kvm_pte_chain *pte_chain;
1060 struct hlist_node *node;
1061 int i;
1062
1063 if (!sp->parent_pte)
1064 return;
1065
1066 if (!sp->multimapped) {
1067 kvm_mmu_update_unsync_bitmap(sp->parent_pte);
1068 return;
1069 }
1070
1071 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1072 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1073 if (!pte_chain->parent_ptes[i])
1074 break;
1075 kvm_mmu_update_unsync_bitmap(pte_chain->parent_ptes[i]);
1076 }
1077}
1078
1079static int unsync_walk_fn(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1080{
0074ff63
MT		 1081 kvm_mmu_update_parents_unsync(sp);
1082 return 1;
1083}
1084
1085static void kvm_mmu_mark_parents_unsync(struct kvm_vcpu *vcpu,
1086 struct kvm_mmu_page *sp)
1087{
1088 mmu_parent_walk(vcpu, sp, unsync_walk_fn);
1089 kvm_mmu_update_parents_unsync(sp);
1090}
1091
d761a501
AK		 1092static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
1093 struct kvm_mmu_page *sp)
1094{
1095 int i;
1096
1097 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1098 sp->spt[i] = shadow_trap_nonpresent_pte;
1099}
1100
e8bc217a
MT		 1101static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1102 struct kvm_mmu_page *sp)
1103{
1104 return 1;
1105}
1106
a7052897
MT		 1107static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1108{
1109}
1110
60c8aec6
MT		 1111#define KVM_PAGE_ARRAY_NR 16
1112
1113struct kvm_mmu_pages {
1114 struct mmu_page_and_offset {
1115 struct kvm_mmu_page *sp;
1116 unsigned int idx;
1117 } page[KVM_PAGE_ARRAY_NR];
1118 unsigned int nr;
1119};
1120
0074ff63
MT		 1121#define for_each_unsync_children(bitmap, idx) \
1122 for (idx = find_first_bit(bitmap, 512); \
1123 idx < 512; \
1124 idx = find_next_bit(bitmap, 512, idx+1))
1125
cded19f3
HE		 1126static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1127 int idx)
4731d4c7 1128{
60c8aec6 1129 int i;
4731d4c7 1130
60c8aec6
MT		 1131 if (sp->unsync)
1132 for (i=0; i < pvec->nr; i++)
1133 if (pvec->page[i].sp == sp)
1134 return 0;
1135
1136 pvec->page[pvec->nr].sp = sp;
1137 pvec->page[pvec->nr].idx = idx;
1138 pvec->nr++;
1139 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1140}
1141
1142static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1143 struct kvm_mmu_pages *pvec)
1144{
1145 int i, ret, nr_unsync_leaf = 0;
4731d4c7 1146
0074ff63 1147 for_each_unsync_children(sp->unsync_child_bitmap, i) {
4731d4c7
MT		 1148 u64 ent = sp->spt[i];
1149
87917239 1150 if (is_shadow_present_pte(ent) && !is_large_pte(ent)) {
4731d4c7
MT		 1151 struct kvm_mmu_page *child;
1152 child = page_header(ent & PT64_BASE_ADDR_MASK);
1153
1154 if (child->unsync_children) {
60c8aec6
MT		 1155 if (mmu_pages_add(pvec, child, i))
1156 return -ENOSPC;
1157
1158 ret = __mmu_unsync_walk(child, pvec);
1159 if (!ret)
1160 __clear_bit(i, sp->unsync_child_bitmap);
1161 else if (ret > 0)
1162 nr_unsync_leaf += ret;
1163 else
4731d4c7
MT		 1164 return ret;
1165 }
1166
1167 if (child->unsync) {
60c8aec6
MT		 1168 nr_unsync_leaf++;
1169 if (mmu_pages_add(pvec, child, i))
1170 return -ENOSPC;
4731d4c7
MT		 1171 }
1172 }
1173 }
1174
0074ff63 1175 if (find_first_bit(sp->unsync_child_bitmap, 512) == 512)
4731d4c7
MT		 1176 sp->unsync_children = 0;
1177
60c8aec6
MT		 1178 return nr_unsync_leaf;
1179}
1180
1181static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1182 struct kvm_mmu_pages *pvec)
1183{
1184 if (!sp->unsync_children)
1185 return 0;
1186
1187 mmu_pages_add(pvec, sp, 0);
1188 return __mmu_unsync_walk(sp, pvec);
4731d4c7
MT		 1189}
1190
4db35314 1191static struct kvm_mmu_page *kvm_mmu_lookup_page(struct kvm *kvm, gfn_t gfn)
cea0f0e7
AK		 1192{
1193 unsigned index;
1194 struct hlist_head *bucket;
4db35314 1195 struct kvm_mmu_page *sp;
cea0f0e7
AK		 1196 struct hlist_node *node;
1197
b8688d51 1198 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
1ae0a13d 1199 index = kvm_page_table_hashfn(gfn);
f05e70ac 1200 bucket = &kvm->arch.mmu_page_hash[index];
4db35314 1201 hlist_for_each_entry(sp, node, bucket, hash_link)
f6e2c02b 1202 if (sp->gfn == gfn && !sp->role.direct
2e53d63a 1203 && !sp->role.invalid) {
cea0f0e7 1204 pgprintk("%s: found role %x\n",
b8688d51 1205 __func__, sp->role.word);
4db35314 1206 return sp;
cea0f0e7
AK		 1207 }
1208 return NULL;
1209}
1210
4731d4c7
MT		 1211static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1212{
1213 WARN_ON(!sp->unsync);
1214 sp->unsync = 0;
1215 --kvm->stat.mmu_unsync;
1216}
1217
1218static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp);
1219
1220static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1221{
1222 if (sp->role.glevels != vcpu->arch.mmu.root_level) {
1223 kvm_mmu_zap_page(vcpu->kvm, sp);
1224 return 1;
1225 }
1226
f691fe1d 1227 trace_kvm_mmu_sync_page(sp);
b1a36821
MT		 1228 if (rmap_write_protect(vcpu->kvm, sp->gfn))
1229 kvm_flush_remote_tlbs(vcpu->kvm);
0c0f40bd 1230 kvm_unlink_unsync_page(vcpu->kvm, sp);
4731d4c7
MT		 1231 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1232 kvm_mmu_zap_page(vcpu->kvm, sp);
1233 return 1;
1234 }
1235
1236 kvm_mmu_flush_tlb(vcpu);
4731d4c7
MT		 1237 return 0;
1238}
1239
60c8aec6
MT		 1240struct mmu_page_path {
1241 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1242 unsigned int idx[PT64_ROOT_LEVEL-1];
4731d4c7
MT		 1243};
1244
60c8aec6
MT		 1245#define for_each_sp(pvec, sp, parents, i) \
1246 for (i = mmu_pages_next(&pvec, &parents, -1), \
1247 sp = pvec.page[i].sp; \
1248 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1249 i = mmu_pages_next(&pvec, &parents, i))
1250
cded19f3
HE		 1251static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1252 struct mmu_page_path *parents,
1253 int i)
60c8aec6
MT		 1254{
1255 int n;
1256
1257 for (n = i+1; n < pvec->nr; n++) {
1258 struct kvm_mmu_page *sp = pvec->page[n].sp;
1259
1260 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1261 parents->idx[0] = pvec->page[n].idx;
1262 return n;
1263 }
1264
1265 parents->parent[sp->role.level-2] = sp;
1266 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1267 }
1268
1269 return n;
1270}
1271
cded19f3 1272static void mmu_pages_clear_parents(struct mmu_page_path *parents)
4731d4c7 1273{
60c8aec6
MT		 1274 struct kvm_mmu_page *sp;
1275 unsigned int level = 0;
1276
1277 do {
1278 unsigned int idx = parents->idx[level];
4731d4c7 1279
60c8aec6
MT		 1280 sp = parents->parent[level];
1281 if (!sp)
1282 return;
1283
1284 --sp->unsync_children;
1285 WARN_ON((int)sp->unsync_children < 0);
1286 __clear_bit(idx, sp->unsync_child_bitmap);
1287 level++;
1288 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
4731d4c7
MT		 1289}
1290
60c8aec6
MT		 1291static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1292 struct mmu_page_path *parents,
1293 struct kvm_mmu_pages *pvec)
4731d4c7 1294{
60c8aec6
MT		 1295 parents->parent[parent->role.level-1] = NULL;
1296 pvec->nr = 0;
1297}
4731d4c7 1298
60c8aec6
MT		 1299static void mmu_sync_children(struct kvm_vcpu *vcpu,
1300 struct kvm_mmu_page *parent)
1301{
1302 int i;
1303 struct kvm_mmu_page *sp;
1304 struct mmu_page_path parents;
1305 struct kvm_mmu_pages pages;
1306
1307 kvm_mmu_pages_init(parent, &parents, &pages);
1308 while (mmu_unsync_walk(parent, &pages)) {
b1a36821
MT		 1309 int protected = 0;
1310
1311 for_each_sp(pages, sp, parents, i)
1312 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1313
1314 if (protected)
1315 kvm_flush_remote_tlbs(vcpu->kvm);
1316
60c8aec6
MT		 1317 for_each_sp(pages, sp, parents, i) {
1318 kvm_sync_page(vcpu, sp);
1319 mmu_pages_clear_parents(&parents);
1320 }
4731d4c7 1321 cond_resched_lock(&vcpu->kvm->mmu_lock);
60c8aec6
MT		 1322 kvm_mmu_pages_init(parent, &parents, &pages);
1323 }
4731d4c7
MT		 1324}
1325
cea0f0e7
AK		 1326static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1327 gfn_t gfn,
1328 gva_t gaddr,
1329 unsigned level,
f6e2c02b 1330 int direct,
41074d07 1331 unsigned access,
f7d9c7b7 1332 u64 *parent_pte)
cea0f0e7
AK		 1333{
1334 union kvm_mmu_page_role role;
1335 unsigned index;
1336 unsigned quadrant;
1337 struct hlist_head *bucket;
4db35314 1338 struct kvm_mmu_page *sp;
4731d4c7 1339 struct hlist_node *node, *tmp;
cea0f0e7 1340
a770f6f2 1341 role = vcpu->arch.mmu.base_role;
cea0f0e7 1342 role.level = level;
f6e2c02b 1343 role.direct = direct;
41074d07 1344 role.access = access;
ad312c7c 1345 if (vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
cea0f0e7
AK		 1346 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1347 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1348 role.quadrant = quadrant;
1349 }
1ae0a13d 1350 index = kvm_page_table_hashfn(gfn);
f05e70ac 1351 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
4731d4c7
MT		 1352 hlist_for_each_entry_safe(sp, node, tmp, bucket, hash_link)
1353 if (sp->gfn == gfn) {
1354 if (sp->unsync)
1355 if (kvm_sync_page(vcpu, sp))
1356 continue;
1357
1358 if (sp->role.word != role.word)
1359 continue;
1360
4db35314 1361 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
0074ff63
MT		 1362 if (sp->unsync_children) {
1363 set_bit(KVM_REQ_MMU_SYNC, &vcpu->requests);
1364 kvm_mmu_mark_parents_unsync(vcpu, sp);
1365 }
f691fe1d 1366 trace_kvm_mmu_get_page(sp, false);
4db35314 1367 return sp;
cea0f0e7 1368 }
dfc5aa00 1369 ++vcpu->kvm->stat.mmu_cache_miss;
4db35314
AK		 1370 sp = kvm_mmu_alloc_page(vcpu, parent_pte);
1371 if (!sp)
1372 return sp;
4db35314
AK		 1373 sp->gfn = gfn;
1374 sp->role = role;
1375 hlist_add_head(&sp->hash_link, bucket);
f6e2c02b 1376 if (!direct) {
b1a36821
MT		 1377 if (rmap_write_protect(vcpu->kvm, gfn))
1378 kvm_flush_remote_tlbs(vcpu->kvm);
4731d4c7
MT		 1379 account_shadowed(vcpu->kvm, gfn);
1380 }
131d8279
AK		 1381 if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte)
1382 vcpu->arch.mmu.prefetch_page(vcpu, sp);
1383 else
1384 nonpaging_prefetch_page(vcpu, sp);
f691fe1d 1385 trace_kvm_mmu_get_page(sp, true);
4db35314 1386 return sp;
cea0f0e7
AK		 1387}
1388
2d11123a
AK		 1389static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1390 struct kvm_vcpu *vcpu, u64 addr)
1391{
1392 iterator->addr = addr;
1393 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1394 iterator->level = vcpu->arch.mmu.shadow_root_level;
1395 if (iterator->level == PT32E_ROOT_LEVEL) {
1396 iterator->shadow_addr
1397 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1398 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1399 --iterator->level;
1400 if (!iterator->shadow_addr)
1401 iterator->level = 0;
1402 }
1403}
1404
1405static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1406{
1407 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1408 return false;
4d88954d
MT		 1409
1410 if (iterator->level == PT_PAGE_TABLE_LEVEL)
1411 if (is_large_pte(*iterator->sptep))
1412 return false;
1413
2d11123a
AK		 1414 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1415 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1416 return true;
1417}
1418
1419static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1420{
1421 iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK;
1422 --iterator->level;
1423}
1424
90cb0529 1425static void kvm_mmu_page_unlink_children(struct kvm *kvm,
4db35314 1426 struct kvm_mmu_page *sp)
a436036b 1427{
697fe2e2
AK		 1428 unsigned i;
1429 u64 *pt;
1430 u64 ent;
1431
4db35314 1432 pt = sp->spt;
697fe2e2 1433
697fe2e2
AK		 1434 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1435 ent = pt[i];
1436
05da4558 1437 if (is_shadow_present_pte(ent)) {
776e6633 1438 if (!is_last_spte(ent, sp->role.level)) {
05da4558
MT		 1439 ent &= PT64_BASE_ADDR_MASK;
1440 mmu_page_remove_parent_pte(page_header(ent),
1441 &pt[i]);
1442 } else {
776e6633
MT		 1443 if (is_large_pte(ent))
1444 --kvm->stat.lpages;
05da4558
MT		 1445 rmap_remove(kvm, &pt[i]);
1446 }
1447 }
c7addb90 1448 pt[i] = shadow_trap_nonpresent_pte;
697fe2e2 1449 }
a436036b
AK		 1450}
1451
4db35314 1452static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7 1453{
4db35314 1454 mmu_page_remove_parent_pte(sp, parent_pte);
a436036b
AK		 1455}
1456
12b7d28f
AK		 1457static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1458{
1459 int i;
988a2cae 1460 struct kvm_vcpu *vcpu;
12b7d28f 1461
988a2cae
GN		 1462 kvm_for_each_vcpu(i, vcpu, kvm)
1463 vcpu->arch.last_pte_updated = NULL;
12b7d28f
AK		 1464}
1465
31aa2b44 1466static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
a436036b
AK		 1467{
1468 u64 *parent_pte;
1469
4db35314
AK		 1470 while (sp->multimapped || sp->parent_pte) {
1471 if (!sp->multimapped)
1472 parent_pte = sp->parent_pte;
a436036b
AK		 1473 else {
1474 struct kvm_pte_chain *chain;
1475
4db35314 1476 chain = container_of(sp->parent_ptes.first,
a436036b
AK		 1477 struct kvm_pte_chain, link);
1478 parent_pte = chain->parent_ptes[0];
1479 }
697fe2e2 1480 BUG_ON(!parent_pte);
4db35314 1481 kvm_mmu_put_page(sp, parent_pte);
d555c333 1482 __set_spte(parent_pte, shadow_trap_nonpresent_pte);
a436036b 1483 }
31aa2b44
AK		 1484}
1485
60c8aec6
MT		 1486static int mmu_zap_unsync_children(struct kvm *kvm,
1487 struct kvm_mmu_page *parent)
4731d4c7 1488{
60c8aec6
MT		 1489 int i, zapped = 0;
1490 struct mmu_page_path parents;
1491 struct kvm_mmu_pages pages;
4731d4c7 1492
60c8aec6 1493 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
4731d4c7 1494 return 0;
60c8aec6
MT		 1495
1496 kvm_mmu_pages_init(parent, &parents, &pages);
1497 while (mmu_unsync_walk(parent, &pages)) {
1498 struct kvm_mmu_page *sp;
1499
1500 for_each_sp(pages, sp, parents, i) {
1501 kvm_mmu_zap_page(kvm, sp);
1502 mmu_pages_clear_parents(&parents);
1503 }
1504 zapped += pages.nr;
1505 kvm_mmu_pages_init(parent, &parents, &pages);
1506 }
1507
1508 return zapped;
4731d4c7
MT		 1509}
1510
07385413 1511static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp)
31aa2b44 1512{
4731d4c7 1513 int ret;
f691fe1d
AK		 1514
1515 trace_kvm_mmu_zap_page(sp);
31aa2b44 1516 ++kvm->stat.mmu_shadow_zapped;
4731d4c7 1517 ret = mmu_zap_unsync_children(kvm, sp);
4db35314 1518 kvm_mmu_page_unlink_children(kvm, sp);
31aa2b44 1519 kvm_mmu_unlink_parents(kvm, sp);
5b5c6a5a 1520 kvm_flush_remote_tlbs(kvm);
f6e2c02b 1521 if (!sp->role.invalid && !sp->role.direct)
5b5c6a5a 1522 unaccount_shadowed(kvm, sp->gfn);
4731d4c7
MT		 1523 if (sp->unsync)
1524 kvm_unlink_unsync_page(kvm, sp);
4db35314
AK		 1525 if (!sp->root_count) {
1526 hlist_del(&sp->hash_link);
1527 kvm_mmu_free_page(kvm, sp);
2e53d63a 1528 } else {
2e53d63a 1529 sp->role.invalid = 1;
5b5c6a5a 1530 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2e53d63a
MT		 1531 kvm_reload_remote_mmus(kvm);
1532 }
12b7d28f 1533 kvm_mmu_reset_last_pte_updated(kvm);
4731d4c7 1534 return ret;
a436036b
AK		 1535}
1536
82ce2c96
IE		 1537/*
1538 * Changing the number of mmu pages allocated to the vm
1539 * Note: if kvm_nr_mmu_pages is too small, you will get dead lock
1540 */
1541void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages)
1542{
025dbbf3
MT		 1543 int used_pages;
1544
1545 used_pages = kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages;
1546 used_pages = max(0, used_pages);
1547
82ce2c96
IE		 1548 /*
1549 * If we set the number of mmu pages to be smaller be than the
1550 * number of actived pages , we must to free some mmu pages before we
1551 * change the value
1552 */
1553
025dbbf3
MT		 1554 if (used_pages > kvm_nr_mmu_pages) {
1555 while (used_pages > kvm_nr_mmu_pages) {
82ce2c96
IE		 1556 struct kvm_mmu_page *page;
1557
f05e70ac 1558 page = container_of(kvm->arch.active_mmu_pages.prev,
82ce2c96
IE		 1559 struct kvm_mmu_page, link);
1560 kvm_mmu_zap_page(kvm, page);
025dbbf3 1561 used_pages--;
82ce2c96 1562 }
f05e70ac 1563 kvm->arch.n_free_mmu_pages = 0;
82ce2c96
IE		 1564 }
1565 else
f05e70ac
ZX		 1566 kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages
1567 - kvm->arch.n_alloc_mmu_pages;
82ce2c96 1568
f05e70ac 1569 kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages;
82ce2c96
IE		 1570}
1571
f67a46f4 1572static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
a436036b
AK		 1573{
1574 unsigned index;
1575 struct hlist_head *bucket;
4db35314 1576 struct kvm_mmu_page *sp;
a436036b
AK		 1577 struct hlist_node *node, *n;
1578 int r;
1579
b8688d51 1580 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
a436036b 1581 r = 0;
1ae0a13d 1582 index = kvm_page_table_hashfn(gfn);
f05e70ac 1583 bucket = &kvm->arch.mmu_page_hash[index];
4db35314 1584 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link)
f6e2c02b 1585 if (sp->gfn == gfn && !sp->role.direct) {
b8688d51 1586 pgprintk("%s: gfn %lx role %x\n", __func__, gfn,
4db35314 1587 sp->role.word);
a436036b 1588 r = 1;
07385413
MT		 1589 if (kvm_mmu_zap_page(kvm, sp))
1590 n = bucket->first;
a436036b
AK		 1591 }
1592 return r;
cea0f0e7
AK		 1593}
1594
f67a46f4 1595static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
97a0a01e 1596{
4677a3b6
AK		 1597 unsigned index;
1598 struct hlist_head *bucket;
4db35314 1599 struct kvm_mmu_page *sp;
4677a3b6 1600 struct hlist_node *node, *nn;
97a0a01e 1601
4677a3b6
AK		 1602 index = kvm_page_table_hashfn(gfn);
1603 bucket = &kvm->arch.mmu_page_hash[index];
1604 hlist_for_each_entry_safe(sp, node, nn, bucket, hash_link) {
f6e2c02b 1605 if (sp->gfn == gfn && !sp->role.direct
4677a3b6
AK		 1606 && !sp->role.invalid) {
1607 pgprintk("%s: zap %lx %x\n",
1608 __func__, gfn, sp->role.word);
1609 kvm_mmu_zap_page(kvm, sp);
1610 }
97a0a01e
AK		 1611 }
1612}
1613
38c335f1 1614static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
6aa8b732 1615{
38c335f1 1616 int slot = memslot_id(kvm, gfn_to_memslot(kvm, gfn));
4db35314 1617 struct kvm_mmu_page *sp = page_header(__pa(pte));
6aa8b732 1618
291f26bc 1619 __set_bit(slot, sp->slot_bitmap);
6aa8b732
AK		 1620}
1621
6844dec6
MT		 1622static void mmu_convert_notrap(struct kvm_mmu_page *sp)
1623{
1624 int i;
1625 u64 *pt = sp->spt;
1626
1627 if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte)
1628 return;
1629
1630 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1631 if (pt[i] == shadow_notrap_nonpresent_pte)
d555c333 1632 __set_spte(&pt[i], shadow_trap_nonpresent_pte);
6844dec6
MT		 1633 }
1634}
1635
039576c0
AK		 1636struct page *gva_to_page(struct kvm_vcpu *vcpu, gva_t gva)
1637{
72dc67a6
IE		 1638 struct page *page;
1639
ad312c7c 1640 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva);
039576c0
AK		 1641
1642 if (gpa == UNMAPPED_GVA)
1643 return NULL;
72dc67a6 1644
72dc67a6 1645 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6
IE		 1646
1647 return page;
039576c0
AK		 1648}
1649
74be52e3
SY		 1650/*
1651 * The function is based on mtrr_type_lookup() in
1652 * arch/x86/kernel/cpu/mtrr/generic.c
1653 */
1654static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
1655 u64 start, u64 end)
1656{
1657 int i;
1658 u64 base, mask;
1659 u8 prev_match, curr_match;
1660 int num_var_ranges = KVM_NR_VAR_MTRR;
1661
1662 if (!mtrr_state->enabled)
1663 return 0xFF;
1664
1665 /* Make end inclusive end, instead of exclusive */
1666 end--;
1667
1668 /* Look in fixed ranges. Just return the type as per start */
1669 if (mtrr_state->have_fixed && (start < 0x100000)) {
1670 int idx;
1671
1672 if (start < 0x80000) {
1673 idx = 0;
1674 idx += (start >> 16);
1675 return mtrr_state->fixed_ranges[idx];
1676 } else if (start < 0xC0000) {
1677 idx = 1 * 8;
1678 idx += ((start - 0x80000) >> 14);
1679 return mtrr_state->fixed_ranges[idx];
1680 } else if (start < 0x1000000) {
1681 idx = 3 * 8;
1682 idx += ((start - 0xC0000) >> 12);
1683 return mtrr_state->fixed_ranges[idx];
1684 }
1685 }
1686
1687 /*
1688 * Look in variable ranges
1689 * Look of multiple ranges matching this address and pick type
1690 * as per MTRR precedence
1691 */
1692 if (!(mtrr_state->enabled & 2))
1693 return mtrr_state->def_type;
1694
1695 prev_match = 0xFF;
1696 for (i = 0; i < num_var_ranges; ++i) {
1697 unsigned short start_state, end_state;
1698
1699 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
1700 continue;
1701
1702 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
1703 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
1704 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
1705 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
1706
1707 start_state = ((start & mask) == (base & mask));
1708 end_state = ((end & mask) == (base & mask));
1709 if (start_state != end_state)
1710 return 0xFE;
1711
1712 if ((start & mask) != (base & mask))
1713 continue;
1714
1715 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
1716 if (prev_match == 0xFF) {
1717 prev_match = curr_match;
1718 continue;
1719 }
1720
1721 if (prev_match == MTRR_TYPE_UNCACHABLE ||
1722 curr_match == MTRR_TYPE_UNCACHABLE)
1723 return MTRR_TYPE_UNCACHABLE;
1724
1725 if ((prev_match == MTRR_TYPE_WRBACK &&
1726 curr_match == MTRR_TYPE_WRTHROUGH) ||
1727 (prev_match == MTRR_TYPE_WRTHROUGH &&
1728 curr_match == MTRR_TYPE_WRBACK)) {
1729 prev_match = MTRR_TYPE_WRTHROUGH;
1730 curr_match = MTRR_TYPE_WRTHROUGH;
1731 }
1732
1733 if (prev_match != curr_match)
1734 return MTRR_TYPE_UNCACHABLE;
1735 }
1736
1737 if (prev_match != 0xFF)
1738 return prev_match;
1739
1740 return mtrr_state->def_type;
1741}
1742
4b12f0de 1743u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
74be52e3
SY		 1744{
1745 u8 mtrr;
1746
1747 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
1748 (gfn << PAGE_SHIFT) + PAGE_SIZE);
1749 if (mtrr == 0xfe || mtrr == 0xff)
1750 mtrr = MTRR_TYPE_WRBACK;
1751 return mtrr;
1752}
4b12f0de 1753EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
74be52e3 1754
4731d4c7
MT		 1755static int kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1756{
1757 unsigned index;
1758 struct hlist_head *bucket;
1759 struct kvm_mmu_page *s;
1760 struct hlist_node *node, *n;
1761
f691fe1d 1762 trace_kvm_mmu_unsync_page(sp);
4731d4c7
MT		 1763 index = kvm_page_table_hashfn(sp->gfn);
1764 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
1765 /* don't unsync if pagetable is shadowed with multiple roles */
1766 hlist_for_each_entry_safe(s, node, n, bucket, hash_link) {
f6e2c02b 1767 if (s->gfn != sp->gfn || s->role.direct)
4731d4c7
MT		 1768 continue;
1769 if (s->role.word != sp->role.word)
1770 return 1;
1771 }
4731d4c7
MT		 1772 ++vcpu->kvm->stat.mmu_unsync;
1773 sp->unsync = 1;
6cffe8ca 1774
c2d0ee46 1775 kvm_mmu_mark_parents_unsync(vcpu, sp);
6cffe8ca 1776
4731d4c7
MT		 1777 mmu_convert_notrap(sp);
1778 return 0;
1779}
1780
1781static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
1782 bool can_unsync)
1783{
1784 struct kvm_mmu_page *shadow;
1785
1786 shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
1787 if (shadow) {
1788 if (shadow->role.level != PT_PAGE_TABLE_LEVEL)
1789 return 1;
1790 if (shadow->unsync)
1791 return 0;
582801a9 1792 if (can_unsync && oos_shadow)
4731d4c7
MT		 1793 return kvm_unsync_page(vcpu, shadow);
1794 return 1;
1795 }
1796 return 0;
1797}
1798
d555c333 1799static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd 1800 unsigned pte_access, int user_fault,
852e3c19 1801 int write_fault, int dirty, int level,
c2d0ee46 1802 gfn_t gfn, pfn_t pfn, bool speculative,
1403283a 1803 bool can_unsync, bool reset_host_protection)
1c4f1fd6
AK		 1804{
1805 u64 spte;
1e73f9dd 1806 int ret = 0;
64d4d521 1807
1c4f1fd6
AK		 1808 /*
1809 * We don't set the accessed bit, since we sometimes want to see
1810 * whether the guest actually used the pte (in order to detect
1811 * demand paging).
1812 */
7b52345e 1813 spte = shadow_base_present_pte | shadow_dirty_mask;
947da538 1814 if (!speculative)
3201b5d9 1815 spte |= shadow_accessed_mask;
1c4f1fd6
AK		 1816 if (!dirty)
1817 pte_access &= ~ACC_WRITE_MASK;
7b52345e
SY		 1818 if (pte_access & ACC_EXEC_MASK)
1819 spte |= shadow_x_mask;
1820 else
1821 spte |= shadow_nx_mask;
1c4f1fd6 1822 if (pte_access & ACC_USER_MASK)
7b52345e 1823 spte |= shadow_user_mask;
852e3c19 1824 if (level > PT_PAGE_TABLE_LEVEL)
05da4558 1825 spte |= PT_PAGE_SIZE_MASK;
4b12f0de
SY		 1826 if (tdp_enabled)
1827 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
1828 kvm_is_mmio_pfn(pfn));
1c4f1fd6 1829
1403283a
IE		 1830 if (reset_host_protection)
1831 spte |= SPTE_HOST_WRITEABLE;
1832
35149e21 1833 spte |= (u64)pfn << PAGE_SHIFT;
1c4f1fd6
AK		 1834
1835 if ((pte_access & ACC_WRITE_MASK)
1836 || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
1c4f1fd6 1837
852e3c19
JR		 1838 if (level > PT_PAGE_TABLE_LEVEL &&
1839 has_wrprotected_page(vcpu->kvm, gfn, level)) {
38187c83
MT		 1840 ret = 1;
1841 spte = shadow_trap_nonpresent_pte;
1842 goto set_pte;
1843 }
1844
1c4f1fd6 1845 spte |= PT_WRITABLE_MASK;
1c4f1fd6 1846
ecc5589f
MT		 1847 /*
1848 * Optimization: for pte sync, if spte was writable the hash
1849 * lookup is unnecessary (and expensive). Write protection
1850 * is responsibility of mmu_get_page / kvm_sync_page.
1851 * Same reasoning can be applied to dirty page accounting.
1852 */
d555c333 1853 if (!can_unsync && is_writeble_pte(*sptep))
ecc5589f
MT		 1854 goto set_pte;
1855
4731d4c7 1856 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
1c4f1fd6 1857 pgprintk("%s: found shadow page for %lx, marking ro\n",
b8688d51 1858 __func__, gfn);
1e73f9dd 1859 ret = 1;
1c4f1fd6 1860 pte_access &= ~ACC_WRITE_MASK;
a378b4e6 1861 if (is_writeble_pte(spte))
1c4f1fd6 1862 spte &= ~PT_WRITABLE_MASK;
1c4f1fd6
AK		 1863 }
1864 }
1865
1c4f1fd6
AK		 1866 if (pte_access & ACC_WRITE_MASK)
1867 mark_page_dirty(vcpu->kvm, gfn);
1868
38187c83 1869set_pte:
d555c333 1870 __set_spte(sptep, spte);
1e73f9dd
MT		 1871 return ret;
1872}
1873
d555c333 1874static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd
MT		 1875 unsigned pt_access, unsigned pte_access,
1876 int user_fault, int write_fault, int dirty,
852e3c19 1877 int *ptwrite, int level, gfn_t gfn,
1403283a
IE		 1878 pfn_t pfn, bool speculative,
1879 bool reset_host_protection)
1e73f9dd
MT		 1880{
1881 int was_rmapped = 0;
d555c333 1882 int was_writeble = is_writeble_pte(*sptep);
53a27b39 1883 int rmap_count;
1e73f9dd
MT		 1884
1885 pgprintk("%s: spte %llx access %x write_fault %d"
1886 " user_fault %d gfn %lx\n",
d555c333 1887 __func__, *sptep, pt_access,
1e73f9dd
MT		 1888 write_fault, user_fault, gfn);
1889
d555c333 1890 if (is_rmap_spte(*sptep)) {
1e73f9dd
MT		 1891 /*
1892 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
1893 * the parent of the now unreachable PTE.
1894 */
852e3c19
JR		 1895 if (level > PT_PAGE_TABLE_LEVEL &&
1896 !is_large_pte(*sptep)) {
1e73f9dd 1897 struct kvm_mmu_page *child;
d555c333 1898 u64 pte = *sptep;
1e73f9dd
MT		 1899
1900 child = page_header(pte & PT64_BASE_ADDR_MASK);
d555c333
AK		 1901 mmu_page_remove_parent_pte(child, sptep);
1902 } else if (pfn != spte_to_pfn(*sptep)) {
1e73f9dd 1903 pgprintk("hfn old %lx new %lx\n",
d555c333
AK		 1904 spte_to_pfn(*sptep), pfn);
1905 rmap_remove(vcpu->kvm, sptep);
6bed6b9e
JR		 1906 } else
1907 was_rmapped = 1;
1e73f9dd 1908 }
852e3c19 1909
d555c333 1910 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
1403283a
IE		 1911 dirty, level, gfn, pfn, speculative, true,
1912 reset_host_protection)) {
1e73f9dd
MT		 1913 if (write_fault)
1914 *ptwrite = 1;
a378b4e6
MT		 1915 kvm_x86_ops->tlb_flush(vcpu);
1916 }
1e73f9dd 1917
d555c333 1918 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
1e73f9dd 1919 pgprintk("instantiating %s PTE (%s) at %ld (%llx) addr %p\n",
d555c333 1920 is_large_pte(*sptep)? "2MB" : "4kB",
a205bc19
JR		 1921 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
1922 *sptep, sptep);
d555c333 1923 if (!was_rmapped && is_large_pte(*sptep))
05da4558
MT		 1924 ++vcpu->kvm->stat.lpages;
1925
d555c333 1926 page_header_update_slot(vcpu->kvm, sptep, gfn);
1c4f1fd6 1927 if (!was_rmapped) {
44ad9944 1928 rmap_count = rmap_add(vcpu, sptep, gfn);
acb66dd0 1929 kvm_release_pfn_clean(pfn);
53a27b39 1930 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
852e3c19 1931 rmap_recycle(vcpu, sptep, gfn);
75e68e60
IE		 1932 } else {
1933 if (was_writeble)
35149e21 1934 kvm_release_pfn_dirty(pfn);
75e68e60 1935 else
35149e21 1936 kvm_release_pfn_clean(pfn);
1c4f1fd6 1937 }
1b7fcd32 1938 if (speculative) {
d555c333 1939 vcpu->arch.last_pte_updated = sptep;
1b7fcd32
AK		 1940 vcpu->arch.last_pte_gfn = gfn;
1941 }
1c4f1fd6
AK		 1942}
1943
6aa8b732
AK		 1944static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
1945{
1946}
1947
9f652d21 1948static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
852e3c19 1949 int level, gfn_t gfn, pfn_t pfn)
140754bc 1950{
9f652d21 1951 struct kvm_shadow_walk_iterator iterator;
140754bc 1952 struct kvm_mmu_page *sp;
9f652d21 1953 int pt_write = 0;
140754bc 1954 gfn_t pseudo_gfn;
6aa8b732 1955
9f652d21 1956 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
852e3c19 1957 if (iterator.level == level) {
9f652d21
AK		 1958 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL,
1959 0, write, 1, &pt_write,
1403283a 1960 level, gfn, pfn, false, true);
9f652d21
AK		 1961 ++vcpu->stat.pf_fixed;
1962 break;
6aa8b732
AK		 1963 }
1964
9f652d21
AK		 1965 if (*iterator.sptep == shadow_trap_nonpresent_pte) {
1966 pseudo_gfn = (iterator.addr & PT64_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
1967 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
1968 iterator.level - 1,
1969 1, ACC_ALL, iterator.sptep);
1970 if (!sp) {
1971 pgprintk("nonpaging_map: ENOMEM\n");
1972 kvm_release_pfn_clean(pfn);
1973 return -ENOMEM;
1974 }
140754bc 1975
d555c333
AK		 1976 __set_spte(iterator.sptep,
1977 __pa(sp->spt)
1978 | PT_PRESENT_MASK | PT_WRITABLE_MASK
1979 | shadow_user_mask | shadow_x_mask);
9f652d21
AK		 1980 }
1981 }
1982 return pt_write;
6aa8b732
AK		 1983}
1984
10589a46
MT		 1985static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
1986{
1987 int r;
852e3c19 1988 int level;
35149e21 1989 pfn_t pfn;
e930bffe 1990 unsigned long mmu_seq;
aaee2c94 1991
852e3c19
JR		 1992 level = mapping_level(vcpu, gfn);
1993
1994 /*
1995 * This path builds a PAE pagetable - so we can map 2mb pages at
1996 * maximum. Therefore check if the level is larger than that.
1997 */
1998 if (level > PT_DIRECTORY_LEVEL)
1999 level = PT_DIRECTORY_LEVEL;
2000
2001 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
05da4558 2002
e930bffe 2003 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2004 smp_rmb();
35149e21 2005 pfn = gfn_to_pfn(vcpu->kvm, gfn);
aaee2c94 2006
d196e343 2007 /* mmio */
35149e21
AL		 2008 if (is_error_pfn(pfn)) {
2009 kvm_release_pfn_clean(pfn);
d196e343
AK		 2010 return 1;
2011 }
2012
aaee2c94 2013 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2014 if (mmu_notifier_retry(vcpu, mmu_seq))
2015 goto out_unlock;
eb787d10 2016 kvm_mmu_free_some_pages(vcpu);
852e3c19 2017 r = __direct_map(vcpu, v, write, level, gfn, pfn);
aaee2c94
MT		 2018 spin_unlock(&vcpu->kvm->mmu_lock);
2019
aaee2c94 2020
10589a46 2021 return r;
e930bffe
AA		 2022
2023out_unlock:
2024 spin_unlock(&vcpu->kvm->mmu_lock);
2025 kvm_release_pfn_clean(pfn);
2026 return 0;
10589a46
MT		 2027}
2028
2029
17ac10ad
AK		 2030static void mmu_free_roots(struct kvm_vcpu *vcpu)
2031{
2032 int i;
4db35314 2033 struct kvm_mmu_page *sp;
17ac10ad 2034
ad312c7c 2035 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
7b53aa56 2036 return;
aaee2c94 2037 spin_lock(&vcpu->kvm->mmu_lock);
ad312c7c
ZX		 2038 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2039 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad 2040
4db35314
AK		 2041 sp = page_header(root);
2042 --sp->root_count;
2e53d63a
MT		 2043 if (!sp->root_count && sp->role.invalid)
2044 kvm_mmu_zap_page(vcpu->kvm, sp);
ad312c7c 2045 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
aaee2c94 2046 spin_unlock(&vcpu->kvm->mmu_lock);
17ac10ad
AK		 2047 return;
2048 }
17ac10ad 2049 for (i = 0; i < 4; ++i) {
ad312c7c 2050 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad 2051
417726a3 2052 if (root) {
417726a3 2053 root &= PT64_BASE_ADDR_MASK;
4db35314
AK		 2054 sp = page_header(root);
2055 --sp->root_count;
2e53d63a
MT		 2056 if (!sp->root_count && sp->role.invalid)
2057 kvm_mmu_zap_page(vcpu->kvm, sp);
417726a3 2058 }
ad312c7c 2059 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2060 }
aaee2c94 2061 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 2062 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
17ac10ad
AK		 2063}
2064
8986ecc0
MT		 2065static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2066{
2067 int ret = 0;
2068
2069 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2070 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2071 ret = 1;
2072 }
2073
2074 return ret;
2075}
2076
2077static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
17ac10ad
AK		 2078{
2079 int i;
cea0f0e7 2080 gfn_t root_gfn;
4db35314 2081 struct kvm_mmu_page *sp;
f6e2c02b 2082 int direct = 0;
6de4f3ad 2083 u64 pdptr;
3bb65a22 2084
ad312c7c 2085 root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT;
17ac10ad 2086
ad312c7c
ZX		 2087 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2088 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad
AK		 2089
2090 ASSERT(!VALID_PAGE(root));
fb72d167 2091 if (tdp_enabled)
f6e2c02b 2092 direct = 1;
8986ecc0
MT		 2093 if (mmu_check_root(vcpu, root_gfn))
2094 return 1;
4db35314 2095 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
f6e2c02b 2096 PT64_ROOT_LEVEL, direct,
fb72d167 2097 ACC_ALL, NULL);
4db35314
AK		 2098 root = __pa(sp->spt);
2099 ++sp->root_count;
ad312c7c 2100 vcpu->arch.mmu.root_hpa = root;
8986ecc0 2101 return 0;
17ac10ad 2102 }
f6e2c02b 2103 direct = !is_paging(vcpu);
fb72d167 2104 if (tdp_enabled)
f6e2c02b 2105 direct = 1;
17ac10ad 2106 for (i = 0; i < 4; ++i) {
ad312c7c 2107 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad
AK		 2108
2109 ASSERT(!VALID_PAGE(root));
ad312c7c 2110 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
6de4f3ad 2111 pdptr = kvm_pdptr_read(vcpu, i);
43a3795a 2112 if (!is_present_gpte(pdptr)) {
ad312c7c 2113 vcpu->arch.mmu.pae_root[i] = 0;
417726a3
AK		 2114 continue;
2115 }
6de4f3ad 2116 root_gfn = pdptr >> PAGE_SHIFT;
ad312c7c 2117 } else if (vcpu->arch.mmu.root_level == 0)
cea0f0e7 2118 root_gfn = 0;
8986ecc0
MT		 2119 if (mmu_check_root(vcpu, root_gfn))
2120 return 1;
4db35314 2121 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
f6e2c02b 2122 PT32_ROOT_LEVEL, direct,
f7d9c7b7 2123 ACC_ALL, NULL);
4db35314
AK		 2124 root = __pa(sp->spt);
2125 ++sp->root_count;
ad312c7c 2126 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
17ac10ad 2127 }
ad312c7c 2128 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
8986ecc0 2129 return 0;
17ac10ad
AK		 2130}
2131
0ba73cda
MT		 2132static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2133{
2134 int i;
2135 struct kvm_mmu_page *sp;
2136
2137 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2138 return;
2139 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2140 hpa_t root = vcpu->arch.mmu.root_hpa;
2141 sp = page_header(root);
2142 mmu_sync_children(vcpu, sp);
2143 return;
2144 }
2145 for (i = 0; i < 4; ++i) {
2146 hpa_t root = vcpu->arch.mmu.pae_root[i];
2147
8986ecc0 2148 if (root && VALID_PAGE(root)) {
0ba73cda
MT		 2149 root &= PT64_BASE_ADDR_MASK;
2150 sp = page_header(root);
2151 mmu_sync_children(vcpu, sp);
2152 }
2153 }
2154}
2155
2156void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2157{
2158 spin_lock(&vcpu->kvm->mmu_lock);
2159 mmu_sync_roots(vcpu);
6cffe8ca 2160 spin_unlock(&vcpu->kvm->mmu_lock);
0ba73cda
MT		 2161}
2162
6aa8b732
AK		 2163static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr)
2164{
2165 return vaddr;
2166}
2167
2168static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3f3e7124 2169 u32 error_code)
6aa8b732 2170{
e833240f 2171 gfn_t gfn;
e2dec939 2172 int r;
6aa8b732 2173
b8688d51 2174 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
e2dec939
AK		 2175 r = mmu_topup_memory_caches(vcpu);
2176 if (r)
2177 return r;
714b93da 2178
6aa8b732 2179 ASSERT(vcpu);
ad312c7c 2180 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2181
e833240f 2182 gfn = gva >> PAGE_SHIFT;
6aa8b732 2183
e833240f
AK		 2184 return nonpaging_map(vcpu, gva & PAGE_MASK,
2185 error_code & PFERR_WRITE_MASK, gfn);
6aa8b732
AK		 2186}
2187
fb72d167
JR		 2188static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
2189 u32 error_code)
2190{
35149e21 2191 pfn_t pfn;
fb72d167 2192 int r;
852e3c19 2193 int level;
05da4558 2194 gfn_t gfn = gpa >> PAGE_SHIFT;
e930bffe 2195 unsigned long mmu_seq;
fb72d167
JR		 2196
2197 ASSERT(vcpu);
2198 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2199
2200 r = mmu_topup_memory_caches(vcpu);
2201 if (r)
2202 return r;
2203
852e3c19
JR		 2204 level = mapping_level(vcpu, gfn);
2205
2206 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2207
e930bffe 2208 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2209 smp_rmb();
35149e21 2210 pfn = gfn_to_pfn(vcpu->kvm, gfn);
35149e21
AL		 2211 if (is_error_pfn(pfn)) {
2212 kvm_release_pfn_clean(pfn);
fb72d167
JR		 2213 return 1;
2214 }
2215 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2216 if (mmu_notifier_retry(vcpu, mmu_seq))
2217 goto out_unlock;
fb72d167
JR		 2218 kvm_mmu_free_some_pages(vcpu);
2219 r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK,
852e3c19 2220 level, gfn, pfn);
fb72d167 2221 spin_unlock(&vcpu->kvm->mmu_lock);
fb72d167
JR		 2222
2223 return r;
e930bffe
AA		 2224
2225out_unlock:
2226 spin_unlock(&vcpu->kvm->mmu_lock);
2227 kvm_release_pfn_clean(pfn);
2228 return 0;
fb72d167
JR		 2229}
2230
6aa8b732
AK		 2231static void nonpaging_free(struct kvm_vcpu *vcpu)
2232{
17ac10ad 2233 mmu_free_roots(vcpu);
6aa8b732
AK		 2234}
2235
2236static int nonpaging_init_context(struct kvm_vcpu *vcpu)
2237{
ad312c7c 2238 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2239
2240 context->new_cr3 = nonpaging_new_cr3;
2241 context->page_fault = nonpaging_page_fault;
6aa8b732
AK		 2242 context->gva_to_gpa = nonpaging_gva_to_gpa;
2243 context->free = nonpaging_free;
c7addb90 2244 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2245 context->sync_page = nonpaging_sync_page;
a7052897 2246 context->invlpg = nonpaging_invlpg;
cea0f0e7 2247 context->root_level = 0;
6aa8b732 2248 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2249 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2250 return 0;
2251}
2252
d835dfec 2253void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
6aa8b732 2254{
1165f5fe 2255 ++vcpu->stat.tlb_flush;
cbdd1bea 2256 kvm_x86_ops->tlb_flush(vcpu);
6aa8b732
AK		 2257}
2258
2259static void paging_new_cr3(struct kvm_vcpu *vcpu)
2260{
b8688d51 2261 pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3);
cea0f0e7 2262 mmu_free_roots(vcpu);
6aa8b732
AK		 2263}
2264
6aa8b732
AK		 2265static void inject_page_fault(struct kvm_vcpu *vcpu,
2266 u64 addr,
2267 u32 err_code)
2268{
c3c91fee 2269 kvm_inject_page_fault(vcpu, addr, err_code);
6aa8b732
AK		 2270}
2271
6aa8b732
AK		 2272static void paging_free(struct kvm_vcpu *vcpu)
2273{
2274 nonpaging_free(vcpu);
2275}
2276
82725b20
DE		 2277static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level)
2278{
2279 int bit7;
2280
2281 bit7 = (gpte >> 7) & 1;
2282 return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0;
2283}
2284
6aa8b732
AK		 2285#define PTTYPE 64
2286#include "paging_tmpl.h"
2287#undef PTTYPE
2288
2289#define PTTYPE 32
2290#include "paging_tmpl.h"
2291#undef PTTYPE
2292
82725b20
DE		 2293static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level)
2294{
2295 struct kvm_mmu *context = &vcpu->arch.mmu;
2296 int maxphyaddr = cpuid_maxphyaddr(vcpu);
2297 u64 exb_bit_rsvd = 0;
2298
2299 if (!is_nx(vcpu))
2300 exb_bit_rsvd = rsvd_bits(63, 63);
2301 switch (level) {
2302 case PT32_ROOT_LEVEL:
2303 /* no rsvd bits for 2 level 4K page table entries */
2304 context->rsvd_bits_mask[0][1] = 0;
2305 context->rsvd_bits_mask[0][0] = 0;
2306 if (is_cpuid_PSE36())
2307 /* 36bits PSE 4MB page */
2308 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
2309 else
2310 /* 32 bits PSE 4MB page */
2311 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
29a4b933 2312 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE		 2313 break;
2314 case PT32E_ROOT_LEVEL:
20c466b5
DE		 2315 context->rsvd_bits_mask[0][2] =
2316 rsvd_bits(maxphyaddr, 63) |
2317 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
82725b20 2318 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2319 rsvd_bits(maxphyaddr, 62); /* PDE */
82725b20
DE		 2320 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2321 rsvd_bits(maxphyaddr, 62); /* PTE */
2322 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2323 rsvd_bits(maxphyaddr, 62) |
2324 rsvd_bits(13, 20); /* large page */
29a4b933 2325 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE		 2326 break;
2327 case PT64_ROOT_LEVEL:
2328 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
2329 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2330 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
2331 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2332 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2333 rsvd_bits(maxphyaddr, 51);
82725b20
DE		 2334 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2335 rsvd_bits(maxphyaddr, 51);
2336 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
e04da980
JR		 2337 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
2338 rsvd_bits(maxphyaddr, 51) |
2339 rsvd_bits(13, 29);
82725b20 2340 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4c26b4cd
SY		 2341 rsvd_bits(maxphyaddr, 51) |
2342 rsvd_bits(13, 20); /* large page */
29a4b933 2343 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
82725b20
DE		 2344 break;
2345 }
2346}
2347
17ac10ad 2348static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level)
6aa8b732 2349{
ad312c7c 2350 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK		 2351
2352 ASSERT(is_pae(vcpu));
2353 context->new_cr3 = paging_new_cr3;
2354 context->page_fault = paging64_page_fault;
6aa8b732 2355 context->gva_to_gpa = paging64_gva_to_gpa;
c7addb90 2356 context->prefetch_page = paging64_prefetch_page;
e8bc217a 2357 context->sync_page = paging64_sync_page;
a7052897 2358 context->invlpg = paging64_invlpg;
6aa8b732 2359 context->free = paging_free;
17ac10ad
AK		 2360 context->root_level = level;
2361 context->shadow_root_level = level;
17c3ba9d 2362 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2363 return 0;
2364}
2365
17ac10ad
AK		 2366static int paging64_init_context(struct kvm_vcpu *vcpu)
2367{
82725b20 2368 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
17ac10ad
AK		 2369 return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL);
2370}
2371
6aa8b732
AK		 2372static int paging32_init_context(struct kvm_vcpu *vcpu)
2373{
ad312c7c 2374 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732 2375
82725b20 2376 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
6aa8b732
AK		 2377 context->new_cr3 = paging_new_cr3;
2378 context->page_fault = paging32_page_fault;
6aa8b732
AK		 2379 context->gva_to_gpa = paging32_gva_to_gpa;
2380 context->free = paging_free;
c7addb90 2381 context->prefetch_page = paging32_prefetch_page;
e8bc217a 2382 context->sync_page = paging32_sync_page;
a7052897 2383 context->invlpg = paging32_invlpg;
6aa8b732
AK		 2384 context->root_level = PT32_ROOT_LEVEL;
2385 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2386 context->root_hpa = INVALID_PAGE;
6aa8b732
AK		 2387 return 0;
2388}
2389
2390static int paging32E_init_context(struct kvm_vcpu *vcpu)
2391{
82725b20 2392 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
17ac10ad 2393 return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL);
6aa8b732
AK		 2394}
2395
fb72d167
JR		 2396static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
2397{
2398 struct kvm_mmu *context = &vcpu->arch.mmu;
2399
2400 context->new_cr3 = nonpaging_new_cr3;
2401 context->page_fault = tdp_page_fault;
2402 context->free = nonpaging_free;
2403 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2404 context->sync_page = nonpaging_sync_page;
a7052897 2405 context->invlpg = nonpaging_invlpg;
67253af5 2406 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
fb72d167
JR		 2407 context->root_hpa = INVALID_PAGE;
2408
2409 if (!is_paging(vcpu)) {
2410 context->gva_to_gpa = nonpaging_gva_to_gpa;
2411 context->root_level = 0;
2412 } else if (is_long_mode(vcpu)) {
82725b20 2413 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
fb72d167
JR		 2414 context->gva_to_gpa = paging64_gva_to_gpa;
2415 context->root_level = PT64_ROOT_LEVEL;
2416 } else if (is_pae(vcpu)) {
82725b20 2417 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
fb72d167
JR		 2418 context->gva_to_gpa = paging64_gva_to_gpa;
2419 context->root_level = PT32E_ROOT_LEVEL;
2420 } else {
82725b20 2421 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
fb72d167
JR		 2422 context->gva_to_gpa = paging32_gva_to_gpa;
2423 context->root_level = PT32_ROOT_LEVEL;
2424 }
2425
2426 return 0;
2427}
2428
2429static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
6aa8b732 2430{
a770f6f2
AK		 2431 int r;
2432
6aa8b732 2433 ASSERT(vcpu);
ad312c7c 2434 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732
AK		 2435
2436 if (!is_paging(vcpu))
a770f6f2 2437 r = nonpaging_init_context(vcpu);
a9058ecd 2438 else if (is_long_mode(vcpu))
a770f6f2 2439 r = paging64_init_context(vcpu);
6aa8b732 2440 else if (is_pae(vcpu))
a770f6f2 2441 r = paging32E_init_context(vcpu);
6aa8b732 2442 else
a770f6f2
AK		 2443 r = paging32_init_context(vcpu);
2444
2445 vcpu->arch.mmu.base_role.glevels = vcpu->arch.mmu.root_level;
2446
2447 return r;
6aa8b732
AK		 2448}
2449
fb72d167
JR		 2450static int init_kvm_mmu(struct kvm_vcpu *vcpu)
2451{
35149e21
AL		 2452 vcpu->arch.update_pte.pfn = bad_pfn;
2453
fb72d167
JR		 2454 if (tdp_enabled)
2455 return init_kvm_tdp_mmu(vcpu);
2456 else
2457 return init_kvm_softmmu(vcpu);
2458}
2459
6aa8b732
AK		 2460static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
2461{
2462 ASSERT(vcpu);
ad312c7c
ZX		 2463 if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
2464 vcpu->arch.mmu.free(vcpu);
2465 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
6aa8b732
AK		 2466 }
2467}
2468
2469int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
17c3ba9d
AK		 2470{
2471 destroy_kvm_mmu(vcpu);
2472 return init_kvm_mmu(vcpu);
2473}
8668a3c4 2474EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
17c3ba9d
AK		 2475
2476int kvm_mmu_load(struct kvm_vcpu *vcpu)
6aa8b732 2477{
714b93da
AK		 2478 int r;
2479
e2dec939 2480 r = mmu_topup_memory_caches(vcpu);
17c3ba9d
AK		 2481 if (r)
2482 goto out;
aaee2c94 2483 spin_lock(&vcpu->kvm->mmu_lock);
eb787d10 2484 kvm_mmu_free_some_pages(vcpu);
8986ecc0 2485 r = mmu_alloc_roots(vcpu);
0ba73cda 2486 mmu_sync_roots(vcpu);
aaee2c94 2487 spin_unlock(&vcpu->kvm->mmu_lock);
8986ecc0
MT		 2488 if (r)
2489 goto out;
3662cb1c 2490 /* set_cr3() should ensure TLB has been flushed */
ad312c7c 2491 kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
714b93da
AK		 2492out:
2493 return r;
6aa8b732 2494}
17c3ba9d
AK		 2495EXPORT_SYMBOL_GPL(kvm_mmu_load);
2496
2497void kvm_mmu_unload(struct kvm_vcpu *vcpu)
2498{
2499 mmu_free_roots(vcpu);
2500}
6aa8b732 2501
09072daf 2502static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
4db35314 2503 struct kvm_mmu_page *sp,
ac1b714e
AK		 2504 u64 *spte)
2505{
2506 u64 pte;
2507 struct kvm_mmu_page *child;
2508
2509 pte = *spte;
c7addb90 2510 if (is_shadow_present_pte(pte)) {
776e6633 2511 if (is_last_spte(pte, sp->role.level))
290fc38d 2512 rmap_remove(vcpu->kvm, spte);
ac1b714e
AK		 2513 else {
2514 child = page_header(pte & PT64_BASE_ADDR_MASK);
90cb0529 2515 mmu_page_remove_parent_pte(child, spte);
ac1b714e
AK		 2516 }
2517 }
d555c333 2518 __set_spte(spte, shadow_trap_nonpresent_pte);
05da4558
MT		 2519 if (is_large_pte(pte))
2520 --vcpu->kvm->stat.lpages;
ac1b714e
AK		 2521}
2522
0028425f 2523static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4db35314 2524 struct kvm_mmu_page *sp,
0028425f 2525 u64 *spte,
489f1d65 2526 const void *new)
0028425f 2527{
30945387 2528 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
7e4e4056
JR		 2529 ++vcpu->kvm->stat.mmu_pde_zapped;
2530 return;
30945387 2531 }
0028425f 2532
4cee5764 2533 ++vcpu->kvm->stat.mmu_pte_updated;
4db35314 2534 if (sp->role.glevels == PT32_ROOT_LEVEL)
489f1d65 2535 paging32_update_pte(vcpu, sp, spte, new);
0028425f 2536 else
489f1d65 2537 paging64_update_pte(vcpu, sp, spte, new);
0028425f
AK		 2538}
2539
79539cec
AK		 2540static bool need_remote_flush(u64 old, u64 new)
2541{
2542 if (!is_shadow_present_pte(old))
2543 return false;
2544 if (!is_shadow_present_pte(new))
2545 return true;
2546 if ((old ^ new) & PT64_BASE_ADDR_MASK)
2547 return true;
2548 old ^= PT64_NX_MASK;
2549 new ^= PT64_NX_MASK;
2550 return (old & ~new & PT64_PERM_MASK) != 0;
2551}
2552
2553static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, u64 old, u64 new)
2554{
2555 if (need_remote_flush(old, new))
2556 kvm_flush_remote_tlbs(vcpu->kvm);
2557 else
2558 kvm_mmu_flush_tlb(vcpu);
2559}
2560
12b7d28f
AK		 2561static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
2562{
ad312c7c 2563 u64 *spte = vcpu->arch.last_pte_updated;
12b7d28f 2564
7b52345e 2565 return !!(spte && (*spte & shadow_accessed_mask));
12b7d28f
AK		 2566}
2567
d7824fff
AK		 2568static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
2569 const u8 *new, int bytes)
2570{
2571 gfn_t gfn;
2572 int r;
2573 u64 gpte = 0;
35149e21 2574 pfn_t pfn;
d7824fff
AK		 2575
2576 if (bytes != 4 && bytes != 8)
2577 return;
2578
2579 /*
2580 * Assume that the pte write on a page table of the same type
2581 * as the current vcpu paging mode. This is nearly always true
2582 * (might be false while changing modes). Note it is verified later
2583 * by update_pte().
2584 */
2585 if (is_pae(vcpu)) {
2586 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
2587 if ((bytes == 4) && (gpa % 4 == 0)) {
2588 r = kvm_read_guest(vcpu->kvm, gpa & ~(u64)7, &gpte, 8);
2589 if (r)
2590 return;
2591 memcpy((void *)&gpte + (gpa % 8), new, 4);
2592 } else if ((bytes == 8) && (gpa % 8 == 0)) {
2593 memcpy((void *)&gpte, new, 8);
2594 }
2595 } else {
2596 if ((bytes == 4) && (gpa % 4 == 0))
2597 memcpy((void *)&gpte, new, 4);
2598 }
43a3795a 2599 if (!is_present_gpte(gpte))
d7824fff
AK		 2600 return;
2601 gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
72dc67a6 2602
e930bffe 2603 vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2604 smp_rmb();
35149e21 2605 pfn = gfn_to_pfn(vcpu->kvm, gfn);
72dc67a6 2606
35149e21
AL		 2607 if (is_error_pfn(pfn)) {
2608 kvm_release_pfn_clean(pfn);
d196e343
AK		 2609 return;
2610 }
d7824fff 2611 vcpu->arch.update_pte.gfn = gfn;
35149e21 2612 vcpu->arch.update_pte.pfn = pfn;
d7824fff
AK		 2613}
2614
1b7fcd32
AK		 2615static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
2616{
2617 u64 *spte = vcpu->arch.last_pte_updated;
2618
2619 if (spte
2620 && vcpu->arch.last_pte_gfn == gfn
2621 && shadow_accessed_mask
2622 && !(*spte & shadow_accessed_mask)
2623 && is_shadow_present_pte(*spte))
2624 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
2625}
2626
09072daf 2627void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
ad218f85
MT		 2628 const u8 *new, int bytes,
2629 bool guest_initiated)
da4a00f0 2630{
9b7a0325 2631 gfn_t gfn = gpa >> PAGE_SHIFT;
4db35314 2632 struct kvm_mmu_page *sp;
0e7bc4b9 2633 struct hlist_node *node, *n;
9b7a0325
AK		 2634 struct hlist_head *bucket;
2635 unsigned index;
489f1d65 2636 u64 entry, gentry;
9b7a0325 2637 u64 *spte;
9b7a0325 2638 unsigned offset = offset_in_page(gpa);
0e7bc4b9 2639 unsigned pte_size;
9b7a0325 2640 unsigned page_offset;
0e7bc4b9 2641 unsigned misaligned;
fce0657f 2642 unsigned quadrant;
9b7a0325 2643 int level;
86a5ba02 2644 int flooded = 0;
ac1b714e 2645 int npte;
489f1d65 2646 int r;
9b7a0325 2647
b8688d51 2648 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
d7824fff 2649 mmu_guess_page_from_pte_write(vcpu, gpa, new, bytes);
aaee2c94 2650 spin_lock(&vcpu->kvm->mmu_lock);
1b7fcd32 2651 kvm_mmu_access_page(vcpu, gfn);
eb787d10 2652 kvm_mmu_free_some_pages(vcpu);
4cee5764 2653 ++vcpu->kvm->stat.mmu_pte_write;
c7addb90 2654 kvm_mmu_audit(vcpu, "pre pte write");
ad218f85
MT		 2655 if (guest_initiated) {
2656 if (gfn == vcpu->arch.last_pt_write_gfn
2657 && !last_updated_pte_accessed(vcpu)) {
2658 ++vcpu->arch.last_pt_write_count;
2659 if (vcpu->arch.last_pt_write_count >= 3)
2660 flooded = 1;
2661 } else {
2662 vcpu->arch.last_pt_write_gfn = gfn;
2663 vcpu->arch.last_pt_write_count = 1;
2664 vcpu->arch.last_pte_updated = NULL;
2665 }
86a5ba02 2666 }
1ae0a13d 2667 index = kvm_page_table_hashfn(gfn);
f05e70ac 2668 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
4db35314 2669 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) {
f6e2c02b 2670 if (sp->gfn != gfn || sp->role.direct || sp->role.invalid)
9b7a0325 2671 continue;
4db35314 2672 pte_size = sp->role.glevels == PT32_ROOT_LEVEL ? 4 : 8;
0e7bc4b9 2673 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
e925c5ba 2674 misaligned |= bytes < 4;
86a5ba02 2675 if (misaligned || flooded) {
0e7bc4b9
AK		 2676 /*
2677 * Misaligned accesses are too much trouble to fix
2678 * up; also, they usually indicate a page is not used
2679 * as a page table.
86a5ba02
AK		 2680 *
2681 * If we're seeing too many writes to a page,
2682 * it may no longer be a page table, or we may be
2683 * forking, in which case it is better to unmap the
2684 * page.
0e7bc4b9
AK		 2685 */
2686 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4db35314 2687 gpa, bytes, sp->role.word);
07385413
MT		 2688 if (kvm_mmu_zap_page(vcpu->kvm, sp))
2689 n = bucket->first;
4cee5764 2690 ++vcpu->kvm->stat.mmu_flooded;
0e7bc4b9
AK		 2691 continue;
2692 }
9b7a0325 2693 page_offset = offset;
4db35314 2694 level = sp->role.level;
ac1b714e 2695 npte = 1;
4db35314 2696 if (sp->role.glevels == PT32_ROOT_LEVEL) {
ac1b714e
AK		 2697 page_offset <<= 1; /* 32->64 */
2698 /*
2699 * A 32-bit pde maps 4MB while the shadow pdes map
2700 * only 2MB. So we need to double the offset again
2701 * and zap two pdes instead of one.
2702 */
2703 if (level == PT32_ROOT_LEVEL) {
6b8d0f9b 2704 page_offset &= ~7; /* kill rounding error */
ac1b714e
AK		 2705 page_offset <<= 1;
2706 npte = 2;
2707 }
fce0657f 2708 quadrant = page_offset >> PAGE_SHIFT;
9b7a0325 2709 page_offset &= ~PAGE_MASK;
4db35314 2710 if (quadrant != sp->role.quadrant)
fce0657f 2711 continue;
9b7a0325 2712 }
4db35314 2713 spte = &sp->spt[page_offset / sizeof(*spte)];
489f1d65
DE		 2714 if ((gpa & (pte_size - 1)) || (bytes < pte_size)) {
2715 gentry = 0;
2716 r = kvm_read_guest_atomic(vcpu->kvm,
2717 gpa & ~(u64)(pte_size - 1),
2718 &gentry, pte_size);
2719 new = (const void *)&gentry;
2720 if (r < 0)
2721 new = NULL;
2722 }
ac1b714e 2723 while (npte--) {
79539cec 2724 entry = *spte;
4db35314 2725 mmu_pte_write_zap_pte(vcpu, sp, spte);
489f1d65
DE		 2726 if (new)
2727 mmu_pte_write_new_pte(vcpu, sp, spte, new);
79539cec 2728 mmu_pte_write_flush_tlb(vcpu, entry, *spte);
ac1b714e 2729 ++spte;
9b7a0325 2730 }
9b7a0325 2731 }
c7addb90 2732 kvm_mmu_audit(vcpu, "post pte write");
aaee2c94 2733 spin_unlock(&vcpu->kvm->mmu_lock);
35149e21
AL		 2734 if (!is_error_pfn(vcpu->arch.update_pte.pfn)) {
2735 kvm_release_pfn_clean(vcpu->arch.update_pte.pfn);
2736 vcpu->arch.update_pte.pfn = bad_pfn;
d7824fff 2737 }
da4a00f0
AK		 2738}
2739
a436036b
AK		 2740int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2741{
10589a46
MT		 2742 gpa_t gpa;
2743 int r;
a436036b 2744
60f24784
AK		 2745 if (tdp_enabled)
2746 return 0;
2747
10589a46 2748 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva);
10589a46 2749
aaee2c94 2750 spin_lock(&vcpu->kvm->mmu_lock);
10589a46 2751 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
aaee2c94 2752 spin_unlock(&vcpu->kvm->mmu_lock);
10589a46 2753 return r;
a436036b 2754}
577bdc49 2755EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
a436036b 2756
22d95b12 2757void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
ebeace86 2758{
3b80fffe
IE		 2759 while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES &&
2760 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
4db35314 2761 struct kvm_mmu_page *sp;
ebeace86 2762
f05e70ac 2763 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
4db35314
AK		 2764 struct kvm_mmu_page, link);
2765 kvm_mmu_zap_page(vcpu->kvm, sp);
4cee5764 2766 ++vcpu->kvm->stat.mmu_recycled;
ebeace86
AK		 2767 }
2768}
ebeace86 2769
3067714c
AK		 2770int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code)
2771{
2772 int r;
2773 enum emulation_result er;
2774
ad312c7c 2775 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code);
3067714c
AK		 2776 if (r < 0)
2777 goto out;
2778
2779 if (!r) {
2780 r = 1;
2781 goto out;
2782 }
2783
b733bfb5
AK		 2784 r = mmu_topup_memory_caches(vcpu);
2785 if (r)
2786 goto out;
2787
3067714c 2788 er = emulate_instruction(vcpu, vcpu->run, cr2, error_code, 0);
3067714c
AK		 2789
2790 switch (er) {
2791 case EMULATE_DONE:
2792 return 1;
2793 case EMULATE_DO_MMIO:
2794 ++vcpu->stat.mmio_exits;
2795 return 0;
2796 case EMULATE_FAIL:
3f5d18a9
AK		 2797 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2798 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2799 return 0;
3067714c
AK		 2800 default:
2801 BUG();
2802 }
2803out:
3067714c
AK		 2804 return r;
2805}
2806EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
2807
a7052897
MT		 2808void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
2809{
a7052897 2810 vcpu->arch.mmu.invlpg(vcpu, gva);
a7052897
MT		 2811 kvm_mmu_flush_tlb(vcpu);
2812 ++vcpu->stat.invlpg;
2813}
2814EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
2815
18552672
JR		 2816void kvm_enable_tdp(void)
2817{
2818 tdp_enabled = true;
2819}
2820EXPORT_SYMBOL_GPL(kvm_enable_tdp);
2821
5f4cb662
JR		 2822void kvm_disable_tdp(void)
2823{
2824 tdp_enabled = false;
2825}
2826EXPORT_SYMBOL_GPL(kvm_disable_tdp);
2827
6aa8b732
AK		 2828static void free_mmu_pages(struct kvm_vcpu *vcpu)
2829{
ad312c7c 2830 free_page((unsigned long)vcpu->arch.mmu.pae_root);
6aa8b732
AK		 2831}
2832
2833static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
2834{
17ac10ad 2835 struct page *page;
6aa8b732
AK		 2836 int i;
2837
2838 ASSERT(vcpu);
2839
17ac10ad
AK		 2840 /*
2841 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
2842 * Therefore we need to allocate shadow page tables in the first
2843 * 4GB of memory, which happens to fit the DMA32 zone.
2844 */
2845 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
2846 if (!page)
2847 goto error_1;
ad312c7c 2848 vcpu->arch.mmu.pae_root = page_address(page);
17ac10ad 2849 for (i = 0; i < 4; ++i)
ad312c7c 2850 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2851
6aa8b732
AK		 2852 return 0;
2853
2854error_1:
2855 free_mmu_pages(vcpu);
2856 return -ENOMEM;
2857}
2858
8018c27b 2859int kvm_mmu_create(struct kvm_vcpu *vcpu)
6aa8b732 2860{
6aa8b732 2861 ASSERT(vcpu);
ad312c7c 2862 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2863
8018c27b
IM		 2864 return alloc_mmu_pages(vcpu);
2865}
6aa8b732 2866
8018c27b
IM		 2867int kvm_mmu_setup(struct kvm_vcpu *vcpu)
2868{
2869 ASSERT(vcpu);
ad312c7c 2870 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2c264957 2871
8018c27b 2872 return init_kvm_mmu(vcpu);
6aa8b732
AK		 2873}
2874
2875void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
2876{
2877 ASSERT(vcpu);
2878
2879 destroy_kvm_mmu(vcpu);
2880 free_mmu_pages(vcpu);
714b93da 2881 mmu_free_memory_caches(vcpu);
6aa8b732
AK		 2882}
2883
90cb0529 2884void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
6aa8b732 2885{
4db35314 2886 struct kvm_mmu_page *sp;
6aa8b732 2887
f05e70ac 2888 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
6aa8b732
AK		 2889 int i;
2890 u64 *pt;
2891
291f26bc 2892 if (!test_bit(slot, sp->slot_bitmap))
6aa8b732
AK		 2893 continue;
2894
4db35314 2895 pt = sp->spt;
6aa8b732
AK		 2896 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2897 /* avoid RMW */
9647c14c 2898 if (pt[i] & PT_WRITABLE_MASK)
6aa8b732 2899 pt[i] &= ~PT_WRITABLE_MASK;
6aa8b732 2900 }
171d595d 2901 kvm_flush_remote_tlbs(kvm);
6aa8b732 2902}
37a7d8b0 2903
90cb0529 2904void kvm_mmu_zap_all(struct kvm *kvm)
e0fa826f 2905{
4db35314 2906 struct kvm_mmu_page *sp, *node;
e0fa826f 2907
aaee2c94 2908 spin_lock(&kvm->mmu_lock);
f05e70ac 2909 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
07385413
MT		 2910 if (kvm_mmu_zap_page(kvm, sp))
2911 node = container_of(kvm->arch.active_mmu_pages.next,
2912 struct kvm_mmu_page, link);
aaee2c94 2913 spin_unlock(&kvm->mmu_lock);
e0fa826f 2914
90cb0529 2915 kvm_flush_remote_tlbs(kvm);
e0fa826f
DL		 2916}
2917
8b2cf73c 2918static void kvm_mmu_remove_one_alloc_mmu_page(struct kvm *kvm)
3ee16c81
IE		 2919{
2920 struct kvm_mmu_page *page;
2921
2922 page = container_of(kvm->arch.active_mmu_pages.prev,
2923 struct kvm_mmu_page, link);
2924 kvm_mmu_zap_page(kvm, page);
2925}
2926
2927static int mmu_shrink(int nr_to_scan, gfp_t gfp_mask)
2928{
2929 struct kvm *kvm;
2930 struct kvm *kvm_freed = NULL;
2931 int cache_count = 0;
2932
2933 spin_lock(&kvm_lock);
2934
2935 list_for_each_entry(kvm, &vm_list, vm_list) {
2936 int npages;
2937
5a4c9288
MT		 2938 if (!down_read_trylock(&kvm->slots_lock))
2939 continue;
3ee16c81
IE		 2940 spin_lock(&kvm->mmu_lock);
2941 npages = kvm->arch.n_alloc_mmu_pages -
2942 kvm->arch.n_free_mmu_pages;
2943 cache_count += npages;
2944 if (!kvm_freed && nr_to_scan > 0 && npages > 0) {
2945 kvm_mmu_remove_one_alloc_mmu_page(kvm);
2946 cache_count--;
2947 kvm_freed = kvm;
2948 }
2949 nr_to_scan--;
2950
2951 spin_unlock(&kvm->mmu_lock);
5a4c9288 2952 up_read(&kvm->slots_lock);
3ee16c81
IE		 2953 }
2954 if (kvm_freed)
2955 list_move_tail(&kvm_freed->vm_list, &vm_list);
2956
2957 spin_unlock(&kvm_lock);
2958
2959 return cache_count;
2960}
2961
2962static struct shrinker mmu_shrinker = {
2963 .shrink = mmu_shrink,
2964 .seeks = DEFAULT_SEEKS * 10,
2965};
2966
2ddfd20e 2967static void mmu_destroy_caches(void)
b5a33a75
AK		 2968{
2969 if (pte_chain_cache)
2970 kmem_cache_destroy(pte_chain_cache);
2971 if (rmap_desc_cache)
2972 kmem_cache_destroy(rmap_desc_cache);
d3d25b04
AK		 2973 if (mmu_page_header_cache)
2974 kmem_cache_destroy(mmu_page_header_cache);
b5a33a75
AK		 2975}
2976
3ee16c81
IE		 2977void kvm_mmu_module_exit(void)
2978{
2979 mmu_destroy_caches();
2980 unregister_shrinker(&mmu_shrinker);
2981}
2982
b5a33a75
AK		 2983int kvm_mmu_module_init(void)
2984{
2985 pte_chain_cache = kmem_cache_create("kvm_pte_chain",
2986 sizeof(struct kvm_pte_chain),
20c2df83 2987 0, 0, NULL);
b5a33a75
AK		 2988 if (!pte_chain_cache)
2989 goto nomem;
2990 rmap_desc_cache = kmem_cache_create("kvm_rmap_desc",
2991 sizeof(struct kvm_rmap_desc),
20c2df83 2992 0, 0, NULL);
b5a33a75
AK		 2993 if (!rmap_desc_cache)
2994 goto nomem;
2995
d3d25b04
AK		 2996 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
2997 sizeof(struct kvm_mmu_page),
20c2df83 2998 0, 0, NULL);
d3d25b04
AK		 2999 if (!mmu_page_header_cache)
3000 goto nomem;
3001
3ee16c81
IE		 3002 register_shrinker(&mmu_shrinker);
3003
b5a33a75
AK		 3004 return 0;
3005
3006nomem:
3ee16c81 3007 mmu_destroy_caches();
b5a33a75
AK		 3008 return -ENOMEM;
3009}
3010
3ad82a7e
ZX		 3011/*
3012 * Caculate mmu pages needed for kvm.
3013 */
3014unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3015{
3016 int i;
3017 unsigned int nr_mmu_pages;
3018 unsigned int nr_pages = 0;
3019
3020 for (i = 0; i < kvm->nmemslots; i++)
3021 nr_pages += kvm->memslots[i].npages;
3022
3023 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3024 nr_mmu_pages = max(nr_mmu_pages,
3025 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3026
3027 return nr_mmu_pages;
3028}
3029
2f333bcb
MT		 3030static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3031 unsigned len)
3032{
3033 if (len > buffer->len)
3034 return NULL;
3035 return buffer->ptr;
3036}
3037
3038static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3039 unsigned len)
3040{
3041 void *ret;
3042
3043 ret = pv_mmu_peek_buffer(buffer, len);
3044 if (!ret)
3045 return ret;
3046 buffer->ptr += len;
3047 buffer->len -= len;
3048 buffer->processed += len;
3049 return ret;
3050}
3051
3052static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3053 gpa_t addr, gpa_t value)
3054{
3055 int bytes = 8;
3056 int r;
3057
3058 if (!is_long_mode(vcpu) && !is_pae(vcpu))
3059 bytes = 4;
3060
3061 r = mmu_topup_memory_caches(vcpu);
3062 if (r)
3063 return r;
3064
3200f405 3065 if (!emulator_write_phys(vcpu, addr, &value, bytes))
2f333bcb
MT		 3066 return -EFAULT;
3067
3068 return 1;
3069}
3070
3071static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3072{
a8cd0244 3073 kvm_set_cr3(vcpu, vcpu->arch.cr3);
2f333bcb
MT		 3074 return 1;
3075}
3076
3077static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
3078{
3079 spin_lock(&vcpu->kvm->mmu_lock);
3080 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
3081 spin_unlock(&vcpu->kvm->mmu_lock);
3082 return 1;
3083}
3084
3085static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
3086 struct kvm_pv_mmu_op_buffer *buffer)
3087{
3088 struct kvm_mmu_op_header *header;
3089
3090 header = pv_mmu_peek_buffer(buffer, sizeof *header);
3091 if (!header)
3092 return 0;
3093 switch (header->op) {
3094 case KVM_MMU_OP_WRITE_PTE: {
3095 struct kvm_mmu_op_write_pte *wpte;
3096
3097 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
3098 if (!wpte)
3099 return 0;
3100 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
3101 wpte->pte_val);
3102 }
3103 case KVM_MMU_OP_FLUSH_TLB: {
3104 struct kvm_mmu_op_flush_tlb *ftlb;
3105
3106 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
3107 if (!ftlb)
3108 return 0;
3109 return kvm_pv_mmu_flush_tlb(vcpu);
3110 }
3111 case KVM_MMU_OP_RELEASE_PT: {
3112 struct kvm_mmu_op_release_pt *rpt;
3113
3114 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
3115 if (!rpt)
3116 return 0;
3117 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
3118 }
3119 default: return 0;
3120 }
3121}
3122
3123int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
3124 gpa_t addr, unsigned long *ret)
3125{
3126 int r;
6ad18fba 3127 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
2f333bcb 3128
6ad18fba
DH		 3129 buffer->ptr = buffer->buf;
3130 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
3131 buffer->processed = 0;
2f333bcb 3132
6ad18fba 3133 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
2f333bcb
MT		 3134 if (r)
3135 goto out;
3136
6ad18fba
DH		 3137 while (buffer->len) {
3138 r = kvm_pv_mmu_op_one(vcpu, buffer);
2f333bcb
MT		 3139 if (r < 0)
3140 goto out;
3141 if (r == 0)
3142 break;
3143 }
3144
3145 r = 1;
3146out:
6ad18fba 3147 *ret = buffer->processed;
2f333bcb
MT		 3148 return r;
3149}
3150
94d8b056
MT		 3151int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
3152{
3153 struct kvm_shadow_walk_iterator iterator;
3154 int nr_sptes = 0;
3155
3156 spin_lock(&vcpu->kvm->mmu_lock);
3157 for_each_shadow_entry(vcpu, addr, iterator) {
3158 sptes[iterator.level-1] = *iterator.sptep;
3159 nr_sptes++;
3160 if (!is_shadow_present_pte(*iterator.sptep))
3161 break;
3162 }
3163 spin_unlock(&vcpu->kvm->mmu_lock);
3164
3165 return nr_sptes;
3166}
3167EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
3168
37a7d8b0
AK		 3169#ifdef AUDIT
3170
3171static const char *audit_msg;
3172
3173static gva_t canonicalize(gva_t gva)
3174{
3175#ifdef CONFIG_X86_64
3176 gva = (long long)(gva << 16) >> 16;
3177#endif
3178 return gva;
3179}
3180
08a3732b
MT		 3181
3182typedef void (*inspect_spte_fn) (struct kvm *kvm, struct kvm_mmu_page *sp,
3183 u64 *sptep);
3184
3185static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp,
3186 inspect_spte_fn fn)
3187{
3188 int i;
3189
3190 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3191 u64 ent = sp->spt[i];
3192
3193 if (is_shadow_present_pte(ent)) {
2920d728 3194 if (!is_last_spte(ent, sp->role.level)) {
08a3732b
MT		 3195 struct kvm_mmu_page *child;
3196 child = page_header(ent & PT64_BASE_ADDR_MASK);
3197 __mmu_spte_walk(kvm, child, fn);
2920d728 3198 } else
08a3732b
MT		 3199 fn(kvm, sp, &sp->spt[i]);
3200 }
3201 }
3202}
3203
3204static void mmu_spte_walk(struct kvm_vcpu *vcpu, inspect_spte_fn fn)
3205{
3206 int i;
3207 struct kvm_mmu_page *sp;
3208
3209 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3210 return;
3211 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3212 hpa_t root = vcpu->arch.mmu.root_hpa;
3213 sp = page_header(root);
3214 __mmu_spte_walk(vcpu->kvm, sp, fn);
3215 return;
3216 }
3217 for (i = 0; i < 4; ++i) {
3218 hpa_t root = vcpu->arch.mmu.pae_root[i];
3219
3220 if (root && VALID_PAGE(root)) {
3221 root &= PT64_BASE_ADDR_MASK;
3222 sp = page_header(root);
3223 __mmu_spte_walk(vcpu->kvm, sp, fn);
3224 }
3225 }
3226 return;
3227}
3228
37a7d8b0
AK		 3229static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte,
3230 gva_t va, int level)
3231{
3232 u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK);
3233 int i;
3234 gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1));
3235
3236 for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) {
3237 u64 ent = pt[i];
3238
c7addb90 3239 if (ent == shadow_trap_nonpresent_pte)
37a7d8b0
AK		 3240 continue;
3241
3242 va = canonicalize(va);
2920d728
MT		 3243 if (is_shadow_present_pte(ent) && !is_last_spte(ent, level))
3244 audit_mappings_page(vcpu, ent, va, level - 1);
3245 else {
ad312c7c 3246 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, va);
34382539
JK		 3247 gfn_t gfn = gpa >> PAGE_SHIFT;
3248 pfn_t pfn = gfn_to_pfn(vcpu->kvm, gfn);
3249 hpa_t hpa = (hpa_t)pfn << PAGE_SHIFT;
37a7d8b0 3250
2aaf65e8
MT		 3251 if (is_error_pfn(pfn)) {
3252 kvm_release_pfn_clean(pfn);
3253 continue;
3254 }
3255
c7addb90 3256 if (is_shadow_present_pte(ent)
37a7d8b0 3257 && (ent & PT64_BASE_ADDR_MASK) != hpa)
c7addb90
AK		 3258 printk(KERN_ERR "xx audit error: (%s) levels %d"
3259 " gva %lx gpa %llx hpa %llx ent %llx %d\n",
ad312c7c 3260 audit_msg, vcpu->arch.mmu.root_level,
d77c26fc
MD		 3261 va, gpa, hpa, ent,
3262 is_shadow_present_pte(ent));
c7addb90
AK		 3263 else if (ent == shadow_notrap_nonpresent_pte
3264 && !is_error_hpa(hpa))
3265 printk(KERN_ERR "audit: (%s) notrap shadow,"
3266 " valid guest gva %lx\n", audit_msg, va);
35149e21 3267 kvm_release_pfn_clean(pfn);
c7addb90 3268
37a7d8b0
AK		 3269 }
3270 }
3271}
3272
3273static void audit_mappings(struct kvm_vcpu *vcpu)
3274{
1ea252af 3275 unsigned i;
37a7d8b0 3276
ad312c7c
ZX		 3277 if (vcpu->arch.mmu.root_level == 4)
3278 audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4);
37a7d8b0
AK		 3279 else
3280 for (i = 0; i < 4; ++i)
ad312c7c 3281 if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK)
37a7d8b0 3282 audit_mappings_page(vcpu,
ad312c7c 3283 vcpu->arch.mmu.pae_root[i],
37a7d8b0
AK		 3284 i << 30,
3285 2);
3286}
3287
3288static int count_rmaps(struct kvm_vcpu *vcpu)
3289{
3290 int nmaps = 0;
3291 int i, j, k;
3292
3293 for (i = 0; i < KVM_MEMORY_SLOTS; ++i) {
3294 struct kvm_memory_slot *m = &vcpu->kvm->memslots[i];
3295 struct kvm_rmap_desc *d;
3296
3297 for (j = 0; j < m->npages; ++j) {
290fc38d 3298 unsigned long *rmapp = &m->rmap[j];
37a7d8b0 3299
290fc38d 3300 if (!*rmapp)
37a7d8b0 3301 continue;
290fc38d 3302 if (!(*rmapp & 1)) {
37a7d8b0
AK		 3303 ++nmaps;
3304 continue;
3305 }
290fc38d 3306 d = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
37a7d8b0
AK		 3307 while (d) {
3308 for (k = 0; k < RMAP_EXT; ++k)
d555c333 3309 if (d->sptes[k])
37a7d8b0
AK		 3310 ++nmaps;
3311 else
3312 break;
3313 d = d->more;
3314 }
3315 }
3316 }
3317 return nmaps;
3318}
3319
08a3732b
MT		 3320void inspect_spte_has_rmap(struct kvm *kvm, struct kvm_mmu_page *sp, u64 *sptep)
3321{
3322 unsigned long *rmapp;
3323 struct kvm_mmu_page *rev_sp;
3324 gfn_t gfn;
3325
3326 if (*sptep & PT_WRITABLE_MASK) {
3327 rev_sp = page_header(__pa(sptep));
3328 gfn = rev_sp->gfns[sptep - rev_sp->spt];
3329
3330 if (!gfn_to_memslot(kvm, gfn)) {
3331 if (!printk_ratelimit())
3332 return;
3333 printk(KERN_ERR "%s: no memslot for gfn %ld\n",
3334 audit_msg, gfn);
3335 printk(KERN_ERR "%s: index %ld of sp (gfn=%lx)\n",
3336 audit_msg, sptep - rev_sp->spt,
3337 rev_sp->gfn);
3338 dump_stack();
3339 return;
3340 }
3341
2920d728
MT		 3342 rmapp = gfn_to_rmap(kvm, rev_sp->gfns[sptep - rev_sp->spt],
3343 is_large_pte(*sptep));
08a3732b
MT		 3344 if (!*rmapp) {
3345 if (!printk_ratelimit())
3346 return;
3347 printk(KERN_ERR "%s: no rmap for writable spte %llx\n",
3348 audit_msg, *sptep);
3349 dump_stack();
3350 }
3351 }
3352
3353}
3354
3355void audit_writable_sptes_have_rmaps(struct kvm_vcpu *vcpu)
3356{
3357 mmu_spte_walk(vcpu, inspect_spte_has_rmap);
3358}
3359
3360static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu)
37a7d8b0 3361{
4db35314 3362 struct kvm_mmu_page *sp;
37a7d8b0
AK		 3363 int i;
3364
f05e70ac 3365 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
4db35314 3366 u64 *pt = sp->spt;
37a7d8b0 3367
4db35314 3368 if (sp->role.level != PT_PAGE_TABLE_LEVEL)
37a7d8b0
AK		 3369 continue;
3370
3371 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3372 u64 ent = pt[i];
3373
3374 if (!(ent & PT_PRESENT_MASK))
3375 continue;
3376 if (!(ent & PT_WRITABLE_MASK))
3377 continue;
08a3732b 3378 inspect_spte_has_rmap(vcpu->kvm, sp, &pt[i]);
37a7d8b0
AK		 3379 }
3380 }
08a3732b 3381 return;
37a7d8b0
AK		 3382}
3383
3384static void audit_rmap(struct kvm_vcpu *vcpu)
3385{
08a3732b
MT		 3386 check_writable_mappings_rmap(vcpu);
3387 count_rmaps(vcpu);
37a7d8b0
AK		 3388}
3389
3390static void audit_write_protection(struct kvm_vcpu *vcpu)
3391{
4db35314 3392 struct kvm_mmu_page *sp;
290fc38d
IE		 3393 struct kvm_memory_slot *slot;
3394 unsigned long *rmapp;
e58b0f9e 3395 u64 *spte;
290fc38d 3396 gfn_t gfn;
37a7d8b0 3397
f05e70ac 3398 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
f6e2c02b 3399 if (sp->role.direct)
37a7d8b0 3400 continue;
e58b0f9e
MT		 3401 if (sp->unsync)
3402 continue;
37a7d8b0 3403
4db35314 3404 gfn = unalias_gfn(vcpu->kvm, sp->gfn);
2843099f 3405 slot = gfn_to_memslot_unaliased(vcpu->kvm, sp->gfn);
290fc38d 3406 rmapp = &slot->rmap[gfn - slot->base_gfn];
e58b0f9e
MT		 3407
3408 spte = rmap_next(vcpu->kvm, rmapp, NULL);
3409 while (spte) {
3410 if (*spte & PT_WRITABLE_MASK)
3411 printk(KERN_ERR "%s: (%s) shadow page has "
3412 "writable mappings: gfn %lx role %x\n",
b8688d51 3413 __func__, audit_msg, sp->gfn,
4db35314 3414 sp->role.word);
e58b0f9e
MT		 3415 spte = rmap_next(vcpu->kvm, rmapp, spte);
3416 }
37a7d8b0
AK		 3417 }
3418}
3419
3420static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg)
3421{
3422 int olddbg = dbg;
3423
3424 dbg = 0;
3425 audit_msg = msg;
3426 audit_rmap(vcpu);
3427 audit_write_protection(vcpu);
2aaf65e8
MT		 3428 if (strcmp("pre pte write", audit_msg) != 0)
3429 audit_mappings(vcpu);
08a3732b 3430 audit_writable_sptes_have_rmaps(vcpu);
37a7d8b0
AK		 3431 dbg = olddbg;
3432}
3433
3434#endif
Linux kernel - Deliverables
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