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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/i915_drm.h> | |
1da177e4 | 33 | #include "i915_drv.h" |
990bbdad | 34 | #include "i915_trace.h" |
f49f0586 | 35 | #include "intel_drv.h" |
1da177e4 | 36 | |
79e53945 | 37 | #include <linux/console.h> |
e0cd3608 | 38 | #include <linux/module.h> |
760285e7 | 39 | #include <drm/drm_crtc_helper.h> |
79e53945 | 40 | |
112b715e KH |
41 | static struct drm_driver driver; |
42 | ||
a57c774a AK |
43 | #define GEN_DEFAULT_PIPEOFFSETS \ |
44 | .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ | |
45 | PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ | |
46 | .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ | |
47 | TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ | |
48 | .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET }, \ | |
49 | .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \ | |
50 | .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } | |
51 | ||
52 | ||
9a7e8492 | 53 | static const struct intel_device_info intel_i830_info = { |
7eb552ae | 54 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 55 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 56 | .ring_mask = RENDER_RING, |
a57c774a | 57 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 KH |
58 | }; |
59 | ||
9a7e8492 | 60 | static const struct intel_device_info intel_845g_info = { |
7eb552ae | 61 | .gen = 2, .num_pipes = 1, |
31578148 | 62 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 63 | .ring_mask = RENDER_RING, |
a57c774a | 64 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 KH |
65 | }; |
66 | ||
9a7e8492 | 67 | static const struct intel_device_info intel_i85x_info = { |
7eb552ae | 68 | .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, |
5ce8ba7c | 69 | .cursor_needs_physical = 1, |
31578148 | 70 | .has_overlay = 1, .overlay_needs_physical = 1, |
fd70d52a | 71 | .has_fbc = 1, |
73ae478c | 72 | .ring_mask = RENDER_RING, |
a57c774a | 73 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 KH |
74 | }; |
75 | ||
9a7e8492 | 76 | static const struct intel_device_info intel_i865g_info = { |
7eb552ae | 77 | .gen = 2, .num_pipes = 1, |
31578148 | 78 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 79 | .ring_mask = RENDER_RING, |
a57c774a | 80 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 KH |
81 | }; |
82 | ||
9a7e8492 | 83 | static const struct intel_device_info intel_i915g_info = { |
7eb552ae | 84 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 85 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 86 | .ring_mask = RENDER_RING, |
a57c774a | 87 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 | 88 | }; |
9a7e8492 | 89 | static const struct intel_device_info intel_i915gm_info = { |
7eb552ae | 90 | .gen = 3, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 91 | .cursor_needs_physical = 1, |
31578148 | 92 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 93 | .supports_tv = 1, |
fd70d52a | 94 | .has_fbc = 1, |
73ae478c | 95 | .ring_mask = RENDER_RING, |
a57c774a | 96 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 | 97 | }; |
9a7e8492 | 98 | static const struct intel_device_info intel_i945g_info = { |
7eb552ae | 99 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, |
31578148 | 100 | .has_overlay = 1, .overlay_needs_physical = 1, |
73ae478c | 101 | .ring_mask = RENDER_RING, |
a57c774a | 102 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 | 103 | }; |
9a7e8492 | 104 | static const struct intel_device_info intel_i945gm_info = { |
7eb552ae | 105 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, |
b295d1b6 | 106 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 107 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 108 | .supports_tv = 1, |
fd70d52a | 109 | .has_fbc = 1, |
73ae478c | 110 | .ring_mask = RENDER_RING, |
a57c774a | 111 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 KH |
112 | }; |
113 | ||
9a7e8492 | 114 | static const struct intel_device_info intel_i965g_info = { |
7eb552ae | 115 | .gen = 4, .is_broadwater = 1, .num_pipes = 2, |
c96c3a8c | 116 | .has_hotplug = 1, |
31578148 | 117 | .has_overlay = 1, |
73ae478c | 118 | .ring_mask = RENDER_RING, |
a57c774a | 119 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 KH |
120 | }; |
121 | ||
9a7e8492 | 122 | static const struct intel_device_info intel_i965gm_info = { |
7eb552ae | 123 | .gen = 4, .is_crestline = 1, .num_pipes = 2, |
e3c4e5dd | 124 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 125 | .has_overlay = 1, |
a6c45cf0 | 126 | .supports_tv = 1, |
73ae478c | 127 | .ring_mask = RENDER_RING, |
a57c774a | 128 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 KH |
129 | }; |
130 | ||
9a7e8492 | 131 | static const struct intel_device_info intel_g33_info = { |
7eb552ae | 132 | .gen = 3, .is_g33 = 1, .num_pipes = 2, |
c96c3a8c | 133 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 134 | .has_overlay = 1, |
73ae478c | 135 | .ring_mask = RENDER_RING, |
a57c774a | 136 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 KH |
137 | }; |
138 | ||
9a7e8492 | 139 | static const struct intel_device_info intel_g45_info = { |
7eb552ae | 140 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, |
c96c3a8c | 141 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
73ae478c | 142 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 143 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 KH |
144 | }; |
145 | ||
9a7e8492 | 146 | static const struct intel_device_info intel_gm45_info = { |
7eb552ae | 147 | .gen = 4, .is_g4x = 1, .num_pipes = 2, |
e3c4e5dd | 148 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 149 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 150 | .supports_tv = 1, |
73ae478c | 151 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 152 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 KH |
153 | }; |
154 | ||
9a7e8492 | 155 | static const struct intel_device_info intel_pineview_info = { |
7eb552ae | 156 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 157 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 158 | .has_overlay = 1, |
a57c774a | 159 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 KH |
160 | }; |
161 | ||
9a7e8492 | 162 | static const struct intel_device_info intel_ironlake_d_info = { |
7eb552ae | 163 | .gen = 5, .num_pipes = 2, |
5a117db7 | 164 | .need_gfx_hws = 1, .has_hotplug = 1, |
73ae478c | 165 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 166 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 KH |
167 | }; |
168 | ||
9a7e8492 | 169 | static const struct intel_device_info intel_ironlake_m_info = { |
7eb552ae | 170 | .gen = 5, .is_mobile = 1, .num_pipes = 2, |
e3c4e5dd | 171 | .need_gfx_hws = 1, .has_hotplug = 1, |
c1a9f047 | 172 | .has_fbc = 1, |
73ae478c | 173 | .ring_mask = RENDER_RING | BSD_RING, |
a57c774a | 174 | GEN_DEFAULT_PIPEOFFSETS, |
cfdf1fa2 KH |
175 | }; |
176 | ||
9a7e8492 | 177 | static const struct intel_device_info intel_sandybridge_d_info = { |
7eb552ae | 178 | .gen = 6, .num_pipes = 2, |
c96c3a8c | 179 | .need_gfx_hws = 1, .has_hotplug = 1, |
cbaef0f1 | 180 | .has_fbc = 1, |
73ae478c | 181 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 182 | .has_llc = 1, |
a57c774a | 183 | GEN_DEFAULT_PIPEOFFSETS, |
f6e450a6 EA |
184 | }; |
185 | ||
9a7e8492 | 186 | static const struct intel_device_info intel_sandybridge_m_info = { |
7eb552ae | 187 | .gen = 6, .is_mobile = 1, .num_pipes = 2, |
c96c3a8c | 188 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 189 | .has_fbc = 1, |
73ae478c | 190 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, |
3d29b842 | 191 | .has_llc = 1, |
a57c774a | 192 | GEN_DEFAULT_PIPEOFFSETS, |
a13e4093 EA |
193 | }; |
194 | ||
219f4fdb BW |
195 | #define GEN7_FEATURES \ |
196 | .gen = 7, .num_pipes = 3, \ | |
197 | .need_gfx_hws = 1, .has_hotplug = 1, \ | |
cbaef0f1 | 198 | .has_fbc = 1, \ |
73ae478c | 199 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ |
ab484f8f | 200 | .has_llc = 1 |
219f4fdb | 201 | |
c76b615c | 202 | static const struct intel_device_info intel_ivybridge_d_info = { |
219f4fdb BW |
203 | GEN7_FEATURES, |
204 | .is_ivybridge = 1, | |
a57c774a | 205 | GEN_DEFAULT_PIPEOFFSETS, |
c76b615c JB |
206 | }; |
207 | ||
208 | static const struct intel_device_info intel_ivybridge_m_info = { | |
219f4fdb BW |
209 | GEN7_FEATURES, |
210 | .is_ivybridge = 1, | |
211 | .is_mobile = 1, | |
a57c774a | 212 | GEN_DEFAULT_PIPEOFFSETS, |
c76b615c JB |
213 | }; |
214 | ||
999bcdea BW |
215 | static const struct intel_device_info intel_ivybridge_q_info = { |
216 | GEN7_FEATURES, | |
217 | .is_ivybridge = 1, | |
218 | .num_pipes = 0, /* legal, last one wins */ | |
a57c774a | 219 | GEN_DEFAULT_PIPEOFFSETS, |
999bcdea BW |
220 | }; |
221 | ||
70a3eb7a | 222 | static const struct intel_device_info intel_valleyview_m_info = { |
219f4fdb BW |
223 | GEN7_FEATURES, |
224 | .is_mobile = 1, | |
225 | .num_pipes = 2, | |
70a3eb7a | 226 | .is_valleyview = 1, |
fba5d532 | 227 | .display_mmio_offset = VLV_DISPLAY_BASE, |
cbaef0f1 | 228 | .has_fbc = 0, /* legal, last one wins */ |
30ccd964 | 229 | .has_llc = 0, /* legal, last one wins */ |
a57c774a | 230 | GEN_DEFAULT_PIPEOFFSETS, |
70a3eb7a JB |
231 | }; |
232 | ||
233 | static const struct intel_device_info intel_valleyview_d_info = { | |
219f4fdb BW |
234 | GEN7_FEATURES, |
235 | .num_pipes = 2, | |
70a3eb7a | 236 | .is_valleyview = 1, |
fba5d532 | 237 | .display_mmio_offset = VLV_DISPLAY_BASE, |
cbaef0f1 | 238 | .has_fbc = 0, /* legal, last one wins */ |
30ccd964 | 239 | .has_llc = 0, /* legal, last one wins */ |
a57c774a | 240 | GEN_DEFAULT_PIPEOFFSETS, |
70a3eb7a JB |
241 | }; |
242 | ||
4cae9ae0 | 243 | static const struct intel_device_info intel_haswell_d_info = { |
219f4fdb BW |
244 | GEN7_FEATURES, |
245 | .is_haswell = 1, | |
dd93be58 | 246 | .has_ddi = 1, |
30568c45 | 247 | .has_fpga_dbg = 1, |
73ae478c | 248 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
a57c774a | 249 | GEN_DEFAULT_PIPEOFFSETS, |
4cae9ae0 ED |
250 | }; |
251 | ||
252 | static const struct intel_device_info intel_haswell_m_info = { | |
219f4fdb BW |
253 | GEN7_FEATURES, |
254 | .is_haswell = 1, | |
255 | .is_mobile = 1, | |
dd93be58 | 256 | .has_ddi = 1, |
30568c45 | 257 | .has_fpga_dbg = 1, |
73ae478c | 258 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, |
a57c774a | 259 | GEN_DEFAULT_PIPEOFFSETS, |
c76b615c JB |
260 | }; |
261 | ||
4d4dead6 | 262 | static const struct intel_device_info intel_broadwell_d_info = { |
4b30553d | 263 | .gen = 8, .num_pipes = 3, |
4d4dead6 BW |
264 | .need_gfx_hws = 1, .has_hotplug = 1, |
265 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
266 | .has_llc = 1, | |
267 | .has_ddi = 1, | |
8f94d24b | 268 | .has_fbc = 1, |
a57c774a | 269 | GEN_DEFAULT_PIPEOFFSETS, |
4d4dead6 BW |
270 | }; |
271 | ||
272 | static const struct intel_device_info intel_broadwell_m_info = { | |
4b30553d | 273 | .gen = 8, .is_mobile = 1, .num_pipes = 3, |
4d4dead6 BW |
274 | .need_gfx_hws = 1, .has_hotplug = 1, |
275 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, | |
276 | .has_llc = 1, | |
277 | .has_ddi = 1, | |
8f94d24b | 278 | .has_fbc = 1, |
a57c774a | 279 | GEN_DEFAULT_PIPEOFFSETS, |
4d4dead6 BW |
280 | }; |
281 | ||
fd3c269f ZY |
282 | static const struct intel_device_info intel_broadwell_gt3d_info = { |
283 | .gen = 8, .num_pipes = 3, | |
284 | .need_gfx_hws = 1, .has_hotplug = 1, | |
845f74a7 | 285 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
fd3c269f ZY |
286 | .has_llc = 1, |
287 | .has_ddi = 1, | |
288 | .has_fbc = 1, | |
289 | GEN_DEFAULT_PIPEOFFSETS, | |
290 | }; | |
291 | ||
292 | static const struct intel_device_info intel_broadwell_gt3m_info = { | |
293 | .gen = 8, .is_mobile = 1, .num_pipes = 3, | |
294 | .need_gfx_hws = 1, .has_hotplug = 1, | |
845f74a7 | 295 | .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, |
fd3c269f ZY |
296 | .has_llc = 1, |
297 | .has_ddi = 1, | |
298 | .has_fbc = 1, | |
299 | GEN_DEFAULT_PIPEOFFSETS, | |
300 | }; | |
301 | ||
a0a18075 JB |
302 | /* |
303 | * Make sure any device matches here are from most specific to most | |
304 | * general. For example, since the Quanta match is based on the subsystem | |
305 | * and subvendor IDs, we need it to come before the more general IVB | |
306 | * PCI ID matches, otherwise we'll use the wrong info struct above. | |
307 | */ | |
308 | #define INTEL_PCI_IDS \ | |
309 | INTEL_I830_IDS(&intel_i830_info), \ | |
310 | INTEL_I845G_IDS(&intel_845g_info), \ | |
311 | INTEL_I85X_IDS(&intel_i85x_info), \ | |
312 | INTEL_I865G_IDS(&intel_i865g_info), \ | |
313 | INTEL_I915G_IDS(&intel_i915g_info), \ | |
314 | INTEL_I915GM_IDS(&intel_i915gm_info), \ | |
315 | INTEL_I945G_IDS(&intel_i945g_info), \ | |
316 | INTEL_I945GM_IDS(&intel_i945gm_info), \ | |
317 | INTEL_I965G_IDS(&intel_i965g_info), \ | |
318 | INTEL_G33_IDS(&intel_g33_info), \ | |
319 | INTEL_I965GM_IDS(&intel_i965gm_info), \ | |
320 | INTEL_GM45_IDS(&intel_gm45_info), \ | |
321 | INTEL_G45_IDS(&intel_g45_info), \ | |
322 | INTEL_PINEVIEW_IDS(&intel_pineview_info), \ | |
323 | INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \ | |
324 | INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \ | |
325 | INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \ | |
326 | INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \ | |
327 | INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \ | |
328 | INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \ | |
329 | INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \ | |
330 | INTEL_HSW_D_IDS(&intel_haswell_d_info), \ | |
331 | INTEL_HSW_M_IDS(&intel_haswell_m_info), \ | |
332 | INTEL_VLV_M_IDS(&intel_valleyview_m_info), \ | |
4d4dead6 | 333 | INTEL_VLV_D_IDS(&intel_valleyview_d_info), \ |
fd3c269f ZY |
334 | INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \ |
335 | INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \ | |
336 | INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \ | |
337 | INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info) | |
a0a18075 | 338 | |
6103da0d | 339 | static const struct pci_device_id pciidlist[] = { /* aka */ |
a0a18075 | 340 | INTEL_PCI_IDS, |
49ae35f2 | 341 | {0, 0, 0} |
1da177e4 LT |
342 | }; |
343 | ||
79e53945 JB |
344 | #if defined(CONFIG_DRM_I915_KMS) |
345 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
346 | #endif | |
347 | ||
0206e353 | 348 | void intel_detect_pch(struct drm_device *dev) |
3bad0781 ZW |
349 | { |
350 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bcdb72ac | 351 | struct pci_dev *pch = NULL; |
3bad0781 | 352 | |
ce1bb329 BW |
353 | /* In all current cases, num_pipes is equivalent to the PCH_NOP setting |
354 | * (which really amounts to a PCH but no South Display). | |
355 | */ | |
356 | if (INTEL_INFO(dev)->num_pipes == 0) { | |
357 | dev_priv->pch_type = PCH_NOP; | |
ce1bb329 BW |
358 | return; |
359 | } | |
360 | ||
3bad0781 ZW |
361 | /* |
362 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
363 | * make graphics device passthrough work easy for VMM, that only | |
364 | * need to expose ISA bridge to let driver know the real hardware | |
365 | * underneath. This is a requirement from virtualization team. | |
6a9c4b35 RG |
366 | * |
367 | * In some virtualized environments (e.g. XEN), there is irrelevant | |
368 | * ISA bridge in the system. To work reliably, we should scan trhough | |
369 | * all the ISA bridge devices and check for the first match, instead | |
370 | * of only checking the first one. | |
3bad0781 | 371 | */ |
bcdb72ac | 372 | while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) { |
3bad0781 | 373 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { |
bcdb72ac | 374 | unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK; |
17a303ec | 375 | dev_priv->pch_id = id; |
3bad0781 | 376 | |
90711d50 JB |
377 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
378 | dev_priv->pch_type = PCH_IBX; | |
379 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
7fcb83cd | 380 | WARN_ON(!IS_GEN5(dev)); |
90711d50 | 381 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { |
3bad0781 ZW |
382 | dev_priv->pch_type = PCH_CPT; |
383 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
7fcb83cd | 384 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
c792513b JB |
385 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
386 | /* PantherPoint is CPT compatible */ | |
387 | dev_priv->pch_type = PCH_CPT; | |
492ab669 | 388 | DRM_DEBUG_KMS("Found PantherPoint PCH\n"); |
7fcb83cd | 389 | WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); |
eb877ebf ED |
390 | } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
391 | dev_priv->pch_type = PCH_LPT; | |
392 | DRM_DEBUG_KMS("Found LynxPoint PCH\n"); | |
7fcb83cd | 393 | WARN_ON(!IS_HASWELL(dev)); |
08e1413d | 394 | WARN_ON(IS_ULT(dev)); |
018f52c9 PZ |
395 | } else if (IS_BROADWELL(dev)) { |
396 | dev_priv->pch_type = PCH_LPT; | |
397 | dev_priv->pch_id = | |
398 | INTEL_PCH_LPT_LP_DEVICE_ID_TYPE; | |
399 | DRM_DEBUG_KMS("This is Broadwell, assuming " | |
400 | "LynxPoint LP PCH\n"); | |
e76e0634 BW |
401 | } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
402 | dev_priv->pch_type = PCH_LPT; | |
403 | DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); | |
404 | WARN_ON(!IS_HASWELL(dev)); | |
405 | WARN_ON(!IS_ULT(dev)); | |
bcdb72ac ID |
406 | } else |
407 | continue; | |
408 | ||
6a9c4b35 | 409 | break; |
3bad0781 | 410 | } |
3bad0781 | 411 | } |
6a9c4b35 | 412 | if (!pch) |
bcdb72ac ID |
413 | DRM_DEBUG_KMS("No PCH found.\n"); |
414 | ||
415 | pci_dev_put(pch); | |
3bad0781 ZW |
416 | } |
417 | ||
2911a35b BW |
418 | bool i915_semaphore_is_enabled(struct drm_device *dev) |
419 | { | |
420 | if (INTEL_INFO(dev)->gen < 6) | |
a08acaf2 | 421 | return false; |
2911a35b | 422 | |
d330a953 JN |
423 | if (i915.semaphores >= 0) |
424 | return i915.semaphores; | |
2911a35b | 425 | |
c923facd JN |
426 | /* Until we get further testing... */ |
427 | if (IS_GEN8(dev)) | |
428 | return false; | |
429 | ||
59de3295 | 430 | #ifdef CONFIG_INTEL_IOMMU |
2911a35b | 431 | /* Enable semaphores on SNB when IO remapping is off */ |
59de3295 DV |
432 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) |
433 | return false; | |
434 | #endif | |
2911a35b | 435 | |
a08acaf2 | 436 | return true; |
2911a35b BW |
437 | } |
438 | ||
84b79f8d | 439 | static int i915_drm_freeze(struct drm_device *dev) |
ba8bbcf6 | 440 | { |
61caf87c | 441 | struct drm_i915_private *dev_priv = dev->dev_private; |
24576d23 | 442 | struct drm_crtc *crtc; |
61caf87c | 443 | |
8a187455 PZ |
444 | intel_runtime_pm_get(dev_priv); |
445 | ||
b8efb17b ZR |
446 | /* ignore lid events during suspend */ |
447 | mutex_lock(&dev_priv->modeset_restore_lock); | |
448 | dev_priv->modeset_restore = MODESET_SUSPENDED; | |
449 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
450 | ||
c67a470b PZ |
451 | /* We do a lot of poking in a lot of registers, make sure they work |
452 | * properly. */ | |
da7e29bd | 453 | intel_display_set_init_power(dev_priv, true); |
cb10799c | 454 | |
5bcf719b DA |
455 | drm_kms_helper_poll_disable(dev); |
456 | ||
ba8bbcf6 | 457 | pci_save_state(dev->pdev); |
ba8bbcf6 | 458 | |
5669fcac | 459 | /* If KMS is active, we do the leavevt stuff here */ |
226485e9 | 460 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
db1b76ca DV |
461 | int error; |
462 | ||
45c5f202 | 463 | error = i915_gem_suspend(dev); |
84b79f8d | 464 | if (error) { |
226485e9 | 465 | dev_err(&dev->pdev->dev, |
84b79f8d RW |
466 | "GEM idle failed, resume might fail\n"); |
467 | return error; | |
468 | } | |
a261b246 | 469 | |
1a01ab3b JB |
470 | cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work); |
471 | ||
226485e9 | 472 | drm_irq_uninstall(dev); |
15239099 | 473 | dev_priv->enable_hotplug_processing = false; |
24576d23 JB |
474 | /* |
475 | * Disable CRTCs directly since we want to preserve sw state | |
476 | * for _thaw. | |
477 | */ | |
7c063c72 | 478 | mutex_lock(&dev->mode_config.mutex); |
24576d23 JB |
479 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) |
480 | dev_priv->display.crtc_disable(crtc); | |
7c063c72 | 481 | mutex_unlock(&dev->mode_config.mutex); |
7d708ee4 ID |
482 | |
483 | intel_modeset_suspend_hw(dev); | |
5669fcac JB |
484 | } |
485 | ||
828c7908 BW |
486 | i915_gem_suspend_gtt_mappings(dev); |
487 | ||
9e06dd39 JB |
488 | i915_save_state(dev); |
489 | ||
44834a67 | 490 | intel_opregion_fini(dev); |
28d85cd3 | 491 | intel_uncore_fini(dev); |
8ee1c3db | 492 | |
3fa016a0 | 493 | console_lock(); |
b6f3eff7 | 494 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED); |
3fa016a0 DA |
495 | console_unlock(); |
496 | ||
62d5d69b MK |
497 | dev_priv->suspend_count++; |
498 | ||
61caf87c | 499 | return 0; |
84b79f8d RW |
500 | } |
501 | ||
6a9ee8af | 502 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
503 | { |
504 | int error; | |
505 | ||
506 | if (!dev || !dev->dev_private) { | |
507 | DRM_ERROR("dev: %p\n", dev); | |
508 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
509 | return -ENODEV; | |
510 | } | |
511 | ||
512 | if (state.event == PM_EVENT_PRETHAW) | |
513 | return 0; | |
514 | ||
5bcf719b DA |
515 | |
516 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
517 | return 0; | |
6eecba33 | 518 | |
84b79f8d RW |
519 | error = i915_drm_freeze(dev); |
520 | if (error) | |
521 | return error; | |
522 | ||
b932ccb5 DA |
523 | if (state.event == PM_EVENT_SUSPEND) { |
524 | /* Shut down the device */ | |
525 | pci_disable_device(dev->pdev); | |
526 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
527 | } | |
ba8bbcf6 JB |
528 | |
529 | return 0; | |
530 | } | |
531 | ||
073f34d9 JB |
532 | void intel_console_resume(struct work_struct *work) |
533 | { | |
534 | struct drm_i915_private *dev_priv = | |
535 | container_of(work, struct drm_i915_private, | |
536 | console_resume_work); | |
537 | struct drm_device *dev = dev_priv->dev; | |
538 | ||
539 | console_lock(); | |
b6f3eff7 | 540 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING); |
073f34d9 JB |
541 | console_unlock(); |
542 | } | |
543 | ||
bb60b969 JB |
544 | static void intel_resume_hotplug(struct drm_device *dev) |
545 | { | |
546 | struct drm_mode_config *mode_config = &dev->mode_config; | |
547 | struct intel_encoder *encoder; | |
548 | ||
549 | mutex_lock(&mode_config->mutex); | |
550 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); | |
551 | ||
552 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
553 | if (encoder->hot_plug) | |
554 | encoder->hot_plug(encoder); | |
555 | ||
556 | mutex_unlock(&mode_config->mutex); | |
557 | ||
558 | /* Just fire off a uevent and let userspace tell us what to do */ | |
559 | drm_helper_hpd_irq_event(dev); | |
560 | } | |
561 | ||
76c4b250 | 562 | static int i915_drm_thaw_early(struct drm_device *dev) |
ba8bbcf6 | 563 | { |
5669fcac | 564 | struct drm_i915_private *dev_priv = dev->dev_private; |
8ee1c3db | 565 | |
c9f7fbf9 | 566 | intel_uncore_early_sanitize(dev); |
9d49c0ef | 567 | intel_uncore_sanitize(dev); |
76c4b250 ID |
568 | intel_power_domains_init_hw(dev_priv); |
569 | ||
570 | return 0; | |
571 | } | |
572 | ||
573 | static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings) | |
574 | { | |
575 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9d49c0ef PZ |
576 | |
577 | if (drm_core_check_feature(dev, DRIVER_MODESET) && | |
578 | restore_gtt_mappings) { | |
579 | mutex_lock(&dev->struct_mutex); | |
580 | i915_gem_restore_gtt_mappings(dev); | |
581 | mutex_unlock(&dev->struct_mutex); | |
582 | } | |
583 | ||
61caf87c | 584 | i915_restore_state(dev); |
44834a67 | 585 | intel_opregion_setup(dev); |
61caf87c | 586 | |
5669fcac JB |
587 | /* KMS EnterVT equivalent */ |
588 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
dde86e2d | 589 | intel_init_pch_refclk(dev); |
754970ee | 590 | drm_mode_config_reset(dev); |
1833b134 | 591 | |
5669fcac | 592 | mutex_lock(&dev->struct_mutex); |
074c6ada CW |
593 | if (i915_gem_init_hw(dev)) { |
594 | DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n"); | |
595 | atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); | |
596 | } | |
5669fcac | 597 | mutex_unlock(&dev->struct_mutex); |
226485e9 | 598 | |
15239099 | 599 | /* We need working interrupts for modeset enabling ... */ |
bb0f1b5c | 600 | drm_irq_install(dev, dev->pdev->irq); |
15239099 | 601 | |
1833b134 | 602 | intel_modeset_init_hw(dev); |
24576d23 JB |
603 | |
604 | drm_modeset_lock_all(dev); | |
605 | intel_modeset_setup_hw_state(dev, true); | |
606 | drm_modeset_unlock_all(dev); | |
15239099 DV |
607 | |
608 | /* | |
609 | * ... but also need to make sure that hotplug processing | |
610 | * doesn't cause havoc. Like in the driver load code we don't | |
611 | * bother with the tiny race here where we might loose hotplug | |
612 | * notifications. | |
613 | * */ | |
20afbda2 | 614 | intel_hpd_init(dev); |
15239099 | 615 | dev_priv->enable_hotplug_processing = true; |
bb60b969 JB |
616 | /* Config may have changed between suspend and resume */ |
617 | intel_resume_hotplug(dev); | |
d5bb081b | 618 | } |
1daed3fb | 619 | |
44834a67 CW |
620 | intel_opregion_init(dev); |
621 | ||
073f34d9 JB |
622 | /* |
623 | * The console lock can be pretty contented on resume due | |
624 | * to all the printk activity. Try to keep it out of the hot | |
625 | * path of resume if possible. | |
626 | */ | |
627 | if (console_trylock()) { | |
b6f3eff7 | 628 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING); |
073f34d9 JB |
629 | console_unlock(); |
630 | } else { | |
631 | schedule_work(&dev_priv->console_resume_work); | |
632 | } | |
633 | ||
b8efb17b ZR |
634 | mutex_lock(&dev_priv->modeset_restore_lock); |
635 | dev_priv->modeset_restore = MODESET_DONE; | |
636 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
8a187455 PZ |
637 | |
638 | intel_runtime_pm_put(dev_priv); | |
074c6ada | 639 | return 0; |
84b79f8d RW |
640 | } |
641 | ||
1abd02e2 JB |
642 | static int i915_drm_thaw(struct drm_device *dev) |
643 | { | |
7f16e5c1 | 644 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
828c7908 | 645 | i915_check_and_clear_faults(dev); |
1abd02e2 | 646 | |
9d49c0ef | 647 | return __i915_drm_thaw(dev, true); |
84b79f8d RW |
648 | } |
649 | ||
76c4b250 | 650 | static int i915_resume_early(struct drm_device *dev) |
84b79f8d | 651 | { |
5bcf719b DA |
652 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
653 | return 0; | |
654 | ||
76c4b250 ID |
655 | /* |
656 | * We have a resume ordering issue with the snd-hda driver also | |
657 | * requiring our device to be power up. Due to the lack of a | |
658 | * parent/child relationship we currently solve this with an early | |
659 | * resume hook. | |
660 | * | |
661 | * FIXME: This should be solved with a special hdmi sink device or | |
662 | * similar so that power domains can be employed. | |
663 | */ | |
84b79f8d RW |
664 | if (pci_enable_device(dev->pdev)) |
665 | return -EIO; | |
666 | ||
667 | pci_set_master(dev->pdev); | |
668 | ||
76c4b250 ID |
669 | return i915_drm_thaw_early(dev); |
670 | } | |
671 | ||
672 | int i915_resume(struct drm_device *dev) | |
673 | { | |
674 | struct drm_i915_private *dev_priv = dev->dev_private; | |
675 | int ret; | |
676 | ||
1abd02e2 JB |
677 | /* |
678 | * Platforms with opregion should have sane BIOS, older ones (gen3 and | |
9d49c0ef PZ |
679 | * earlier) need to restore the GTT mappings since the BIOS might clear |
680 | * all our scratch PTEs. | |
1abd02e2 | 681 | */ |
9d49c0ef | 682 | ret = __i915_drm_thaw(dev, !dev_priv->opregion.header); |
6eecba33 CW |
683 | if (ret) |
684 | return ret; | |
685 | ||
686 | drm_kms_helper_poll_enable(dev); | |
687 | return 0; | |
ba8bbcf6 JB |
688 | } |
689 | ||
76c4b250 ID |
690 | static int i915_resume_legacy(struct drm_device *dev) |
691 | { | |
692 | i915_resume_early(dev); | |
693 | i915_resume(dev); | |
694 | ||
695 | return 0; | |
696 | } | |
697 | ||
11ed50ec | 698 | /** |
f3953dcb | 699 | * i915_reset - reset chip after a hang |
11ed50ec | 700 | * @dev: drm device to reset |
11ed50ec BG |
701 | * |
702 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
703 | * reset or otherwise an error code. | |
704 | * | |
705 | * Procedure is fairly simple: | |
706 | * - reset the chip using the reset reg | |
707 | * - re-init context state | |
708 | * - re-init hardware status page | |
709 | * - re-init ring buffer | |
710 | * - re-init interrupt state | |
711 | * - re-init display | |
712 | */ | |
d4b8bb2a | 713 | int i915_reset(struct drm_device *dev) |
11ed50ec | 714 | { |
50227e1c | 715 | struct drm_i915_private *dev_priv = dev->dev_private; |
2e7c8ee7 | 716 | bool simulated; |
0573ed4a | 717 | int ret; |
11ed50ec | 718 | |
d330a953 | 719 | if (!i915.reset) |
d78cb50b CW |
720 | return 0; |
721 | ||
d54a02c0 | 722 | mutex_lock(&dev->struct_mutex); |
11ed50ec | 723 | |
069efc1d | 724 | i915_gem_reset(dev); |
77f01230 | 725 | |
2e7c8ee7 CW |
726 | simulated = dev_priv->gpu_error.stop_rings != 0; |
727 | ||
be62acb4 MK |
728 | ret = intel_gpu_reset(dev); |
729 | ||
730 | /* Also reset the gpu hangman. */ | |
731 | if (simulated) { | |
732 | DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); | |
733 | dev_priv->gpu_error.stop_rings = 0; | |
734 | if (ret == -ENODEV) { | |
f2d91a2c DV |
735 | DRM_INFO("Reset not implemented, but ignoring " |
736 | "error for simulated gpu hangs\n"); | |
be62acb4 MK |
737 | ret = 0; |
738 | } | |
2e7c8ee7 | 739 | } |
be62acb4 | 740 | |
0573ed4a | 741 | if (ret) { |
f2d91a2c | 742 | DRM_ERROR("Failed to reset chip: %i\n", ret); |
f953c935 | 743 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 744 | return ret; |
11ed50ec BG |
745 | } |
746 | ||
747 | /* Ok, now get things going again... */ | |
748 | ||
749 | /* | |
750 | * Everything depends on having the GTT running, so we need to start | |
751 | * there. Fortunately we don't need to do this unless we reset the | |
752 | * chip at a PCI level. | |
753 | * | |
754 | * Next we need to restore the context, but we don't use those | |
755 | * yet either... | |
756 | * | |
757 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
758 | * was running at the time of the reset (i.e. we weren't VT | |
759 | * switched away). | |
760 | */ | |
761 | if (drm_core_check_feature(dev, DRIVER_MODESET) || | |
db1b76ca | 762 | !dev_priv->ums.mm_suspended) { |
db1b76ca | 763 | dev_priv->ums.mm_suspended = 0; |
75a6898f | 764 | |
3d57e5bd | 765 | ret = i915_gem_init_hw(dev); |
8e88a2bd | 766 | mutex_unlock(&dev->struct_mutex); |
3d57e5bd BW |
767 | if (ret) { |
768 | DRM_ERROR("Failed hw init on reset %d\n", ret); | |
769 | return ret; | |
770 | } | |
f817586c | 771 | |
e090c53b DV |
772 | /* |
773 | * FIXME: This is horribly race against concurrent pageflip and | |
774 | * vblank wait ioctls since they can observe dev->irqs_disabled | |
775 | * being false when they shouldn't be able to. | |
776 | */ | |
11ed50ec | 777 | drm_irq_uninstall(dev); |
bb0f1b5c | 778 | drm_irq_install(dev, dev->pdev->irq); |
dd0a1aa1 JM |
779 | |
780 | /* rps/rc6 re-init is necessary to restore state lost after the | |
781 | * reset and the re-install of drm irq. Skip for ironlake per | |
782 | * previous concerns that it doesn't respond well to some forms | |
783 | * of re-init after reset. */ | |
dc1d0136 | 784 | if (INTEL_INFO(dev)->gen > 5) |
c6df39b5 | 785 | intel_reset_gt_powersave(dev); |
dd0a1aa1 | 786 | |
20afbda2 | 787 | intel_hpd_init(dev); |
bcbc324a DV |
788 | } else { |
789 | mutex_unlock(&dev->struct_mutex); | |
11ed50ec BG |
790 | } |
791 | ||
11ed50ec BG |
792 | return 0; |
793 | } | |
794 | ||
56550d94 | 795 | static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
112b715e | 796 | { |
01a06850 DV |
797 | struct intel_device_info *intel_info = |
798 | (struct intel_device_info *) ent->driver_data; | |
799 | ||
d330a953 | 800 | if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) { |
b833d685 BW |
801 | DRM_INFO("This hardware requires preliminary hardware support.\n" |
802 | "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n"); | |
803 | return -ENODEV; | |
804 | } | |
805 | ||
5fe49d86 CW |
806 | /* Only bind to function 0 of the device. Early generations |
807 | * used function 1 as a placeholder for multi-head. This causes | |
808 | * us confusion instead, especially on the systems where both | |
809 | * functions have the same PCI-ID! | |
810 | */ | |
811 | if (PCI_FUNC(pdev->devfn)) | |
812 | return -ENODEV; | |
813 | ||
24986ee0 | 814 | driver.driver_features &= ~(DRIVER_USE_AGP); |
01a06850 | 815 | |
dcdb1674 | 816 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
817 | } |
818 | ||
819 | static void | |
820 | i915_pci_remove(struct pci_dev *pdev) | |
821 | { | |
822 | struct drm_device *dev = pci_get_drvdata(pdev); | |
823 | ||
824 | drm_put_dev(dev); | |
825 | } | |
826 | ||
84b79f8d | 827 | static int i915_pm_suspend(struct device *dev) |
112b715e | 828 | { |
84b79f8d RW |
829 | struct pci_dev *pdev = to_pci_dev(dev); |
830 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
112b715e | 831 | |
84b79f8d RW |
832 | if (!drm_dev || !drm_dev->dev_private) { |
833 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
834 | return -ENODEV; | |
835 | } | |
112b715e | 836 | |
5bcf719b DA |
837 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
838 | return 0; | |
839 | ||
76c4b250 ID |
840 | return i915_drm_freeze(drm_dev); |
841 | } | |
842 | ||
843 | static int i915_pm_suspend_late(struct device *dev) | |
844 | { | |
845 | struct pci_dev *pdev = to_pci_dev(dev); | |
846 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
847 | ||
848 | /* | |
849 | * We have a suspedn ordering issue with the snd-hda driver also | |
850 | * requiring our device to be power up. Due to the lack of a | |
851 | * parent/child relationship we currently solve this with an late | |
852 | * suspend hook. | |
853 | * | |
854 | * FIXME: This should be solved with a special hdmi sink device or | |
855 | * similar so that power domains can be employed. | |
856 | */ | |
857 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
858 | return 0; | |
112b715e | 859 | |
84b79f8d RW |
860 | pci_disable_device(pdev); |
861 | pci_set_power_state(pdev, PCI_D3hot); | |
cbda12d7 | 862 | |
84b79f8d | 863 | return 0; |
cbda12d7 ZW |
864 | } |
865 | ||
76c4b250 ID |
866 | static int i915_pm_resume_early(struct device *dev) |
867 | { | |
868 | struct pci_dev *pdev = to_pci_dev(dev); | |
869 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
870 | ||
871 | return i915_resume_early(drm_dev); | |
872 | } | |
873 | ||
84b79f8d | 874 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 875 | { |
84b79f8d RW |
876 | struct pci_dev *pdev = to_pci_dev(dev); |
877 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
878 | ||
879 | return i915_resume(drm_dev); | |
cbda12d7 ZW |
880 | } |
881 | ||
84b79f8d | 882 | static int i915_pm_freeze(struct device *dev) |
cbda12d7 | 883 | { |
84b79f8d RW |
884 | struct pci_dev *pdev = to_pci_dev(dev); |
885 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
886 | ||
887 | if (!drm_dev || !drm_dev->dev_private) { | |
888 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
889 | return -ENODEV; | |
890 | } | |
891 | ||
892 | return i915_drm_freeze(drm_dev); | |
cbda12d7 ZW |
893 | } |
894 | ||
76c4b250 ID |
895 | static int i915_pm_thaw_early(struct device *dev) |
896 | { | |
897 | struct pci_dev *pdev = to_pci_dev(dev); | |
898 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
899 | ||
900 | return i915_drm_thaw_early(drm_dev); | |
901 | } | |
902 | ||
84b79f8d | 903 | static int i915_pm_thaw(struct device *dev) |
cbda12d7 | 904 | { |
84b79f8d RW |
905 | struct pci_dev *pdev = to_pci_dev(dev); |
906 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
907 | ||
908 | return i915_drm_thaw(drm_dev); | |
cbda12d7 ZW |
909 | } |
910 | ||
84b79f8d | 911 | static int i915_pm_poweroff(struct device *dev) |
cbda12d7 | 912 | { |
84b79f8d RW |
913 | struct pci_dev *pdev = to_pci_dev(dev); |
914 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
84b79f8d | 915 | |
61caf87c | 916 | return i915_drm_freeze(drm_dev); |
cbda12d7 ZW |
917 | } |
918 | ||
0ab9cfeb | 919 | static int hsw_runtime_suspend(struct drm_i915_private *dev_priv) |
97bea207 | 920 | { |
414de7a0 | 921 | hsw_enable_pc8(dev_priv); |
0ab9cfeb ID |
922 | |
923 | return 0; | |
97bea207 PZ |
924 | } |
925 | ||
0ab9cfeb | 926 | static int snb_runtime_resume(struct drm_i915_private *dev_priv) |
9a952a0d PZ |
927 | { |
928 | struct drm_device *dev = dev_priv->dev; | |
929 | ||
9a952a0d | 930 | intel_init_pch_refclk(dev); |
0ab9cfeb ID |
931 | |
932 | return 0; | |
9a952a0d PZ |
933 | } |
934 | ||
0ab9cfeb | 935 | static int hsw_runtime_resume(struct drm_i915_private *dev_priv) |
97bea207 | 936 | { |
414de7a0 | 937 | hsw_disable_pc8(dev_priv); |
0ab9cfeb ID |
938 | |
939 | return 0; | |
97bea207 PZ |
940 | } |
941 | ||
ddeea5b0 ID |
942 | /* |
943 | * Save all Gunit registers that may be lost after a D3 and a subsequent | |
944 | * S0i[R123] transition. The list of registers needing a save/restore is | |
945 | * defined in the VLV2_S0IXRegs document. This documents marks all Gunit | |
946 | * registers in the following way: | |
947 | * - Driver: saved/restored by the driver | |
948 | * - Punit : saved/restored by the Punit firmware | |
949 | * - No, w/o marking: no need to save/restore, since the register is R/O or | |
950 | * used internally by the HW in a way that doesn't depend | |
951 | * keeping the content across a suspend/resume. | |
952 | * - Debug : used for debugging | |
953 | * | |
954 | * We save/restore all registers marked with 'Driver', with the following | |
955 | * exceptions: | |
956 | * - Registers out of use, including also registers marked with 'Debug'. | |
957 | * These have no effect on the driver's operation, so we don't save/restore | |
958 | * them to reduce the overhead. | |
959 | * - Registers that are fully setup by an initialization function called from | |
960 | * the resume path. For example many clock gating and RPS/RC6 registers. | |
961 | * - Registers that provide the right functionality with their reset defaults. | |
962 | * | |
963 | * TODO: Except for registers that based on the above 3 criteria can be safely | |
964 | * ignored, we save/restore all others, practically treating the HW context as | |
965 | * a black-box for the driver. Further investigation is needed to reduce the | |
966 | * saved/restored registers even further, by following the same 3 criteria. | |
967 | */ | |
968 | static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
969 | { | |
970 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
971 | int i; | |
972 | ||
973 | /* GAM 0x4000-0x4770 */ | |
974 | s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); | |
975 | s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); | |
976 | s->arb_mode = I915_READ(ARB_MODE); | |
977 | s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); | |
978 | s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); | |
979 | ||
980 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
981 | s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4); | |
982 | ||
983 | s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); | |
984 | s->gfx_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); | |
985 | ||
986 | s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); | |
987 | s->ecochk = I915_READ(GAM_ECOCHK); | |
988 | s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7); | |
989 | s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7); | |
990 | ||
991 | s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR); | |
992 | ||
993 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
994 | s->g3dctl = I915_READ(VLV_G3DCTL); | |
995 | s->gsckgctl = I915_READ(VLV_GSCKGCTL); | |
996 | s->mbctl = I915_READ(GEN6_MBCTL); | |
997 | ||
998 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
999 | s->ucgctl1 = I915_READ(GEN6_UCGCTL1); | |
1000 | s->ucgctl3 = I915_READ(GEN6_UCGCTL3); | |
1001 | s->rcgctl1 = I915_READ(GEN6_RCGCTL1); | |
1002 | s->rcgctl2 = I915_READ(GEN6_RCGCTL2); | |
1003 | s->rstctl = I915_READ(GEN6_RSTCTL); | |
1004 | s->misccpctl = I915_READ(GEN7_MISCCPCTL); | |
1005 | ||
1006 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
1007 | s->gfxpause = I915_READ(GEN6_GFXPAUSE); | |
1008 | s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC); | |
1009 | s->rpdeuc = I915_READ(GEN6_RPDEUC); | |
1010 | s->ecobus = I915_READ(ECOBUS); | |
1011 | s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL); | |
1012 | s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT); | |
1013 | s->rp_deucsw = I915_READ(GEN6_RPDEUCSW); | |
1014 | s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR); | |
1015 | s->rcedata = I915_READ(VLV_RCEDATA); | |
1016 | s->spare2gh = I915_READ(VLV_SPAREG2H); | |
1017 | ||
1018 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
1019 | s->gt_imr = I915_READ(GTIMR); | |
1020 | s->gt_ier = I915_READ(GTIER); | |
1021 | s->pm_imr = I915_READ(GEN6_PMIMR); | |
1022 | s->pm_ier = I915_READ(GEN6_PMIER); | |
1023 | ||
1024 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
1025 | s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4); | |
1026 | ||
1027 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
1028 | s->tilectl = I915_READ(TILECTL); | |
1029 | s->gt_fifoctl = I915_READ(GTFIFOCTL); | |
1030 | s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1031 | s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1032 | s->pmwgicz = I915_READ(VLV_PMWGICZ); | |
1033 | ||
1034 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
1035 | s->gu_ctl0 = I915_READ(VLV_GU_CTL0); | |
1036 | s->gu_ctl1 = I915_READ(VLV_GU_CTL1); | |
1037 | s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); | |
1038 | ||
1039 | /* | |
1040 | * Not saving any of: | |
1041 | * DFT, 0x9800-0x9EC0 | |
1042 | * SARB, 0xB000-0xB1FC | |
1043 | * GAC, 0x5208-0x524C, 0x14000-0x14C000 | |
1044 | * PCI CFG | |
1045 | */ | |
1046 | } | |
1047 | ||
1048 | static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) | |
1049 | { | |
1050 | struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; | |
1051 | u32 val; | |
1052 | int i; | |
1053 | ||
1054 | /* GAM 0x4000-0x4770 */ | |
1055 | I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); | |
1056 | I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); | |
1057 | I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); | |
1058 | I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); | |
1059 | I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); | |
1060 | ||
1061 | for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) | |
1062 | I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]); | |
1063 | ||
1064 | I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); | |
1065 | I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count); | |
1066 | ||
1067 | I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); | |
1068 | I915_WRITE(GAM_ECOCHK, s->ecochk); | |
1069 | I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp); | |
1070 | I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp); | |
1071 | ||
1072 | I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr); | |
1073 | ||
1074 | /* MBC 0x9024-0x91D0, 0x8500 */ | |
1075 | I915_WRITE(VLV_G3DCTL, s->g3dctl); | |
1076 | I915_WRITE(VLV_GSCKGCTL, s->gsckgctl); | |
1077 | I915_WRITE(GEN6_MBCTL, s->mbctl); | |
1078 | ||
1079 | /* GCP 0x9400-0x9424, 0x8100-0x810C */ | |
1080 | I915_WRITE(GEN6_UCGCTL1, s->ucgctl1); | |
1081 | I915_WRITE(GEN6_UCGCTL3, s->ucgctl3); | |
1082 | I915_WRITE(GEN6_RCGCTL1, s->rcgctl1); | |
1083 | I915_WRITE(GEN6_RCGCTL2, s->rcgctl2); | |
1084 | I915_WRITE(GEN6_RSTCTL, s->rstctl); | |
1085 | I915_WRITE(GEN7_MISCCPCTL, s->misccpctl); | |
1086 | ||
1087 | /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ | |
1088 | I915_WRITE(GEN6_GFXPAUSE, s->gfxpause); | |
1089 | I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc); | |
1090 | I915_WRITE(GEN6_RPDEUC, s->rpdeuc); | |
1091 | I915_WRITE(ECOBUS, s->ecobus); | |
1092 | I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl); | |
1093 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout); | |
1094 | I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw); | |
1095 | I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr); | |
1096 | I915_WRITE(VLV_RCEDATA, s->rcedata); | |
1097 | I915_WRITE(VLV_SPAREG2H, s->spare2gh); | |
1098 | ||
1099 | /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ | |
1100 | I915_WRITE(GTIMR, s->gt_imr); | |
1101 | I915_WRITE(GTIER, s->gt_ier); | |
1102 | I915_WRITE(GEN6_PMIMR, s->pm_imr); | |
1103 | I915_WRITE(GEN6_PMIER, s->pm_ier); | |
1104 | ||
1105 | for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) | |
1106 | I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]); | |
1107 | ||
1108 | /* GT SA CZ domain, 0x100000-0x138124 */ | |
1109 | I915_WRITE(TILECTL, s->tilectl); | |
1110 | I915_WRITE(GTFIFOCTL, s->gt_fifoctl); | |
1111 | /* | |
1112 | * Preserve the GT allow wake and GFX force clock bit, they are not | |
1113 | * be restored, as they are used to control the s0ix suspend/resume | |
1114 | * sequence by the caller. | |
1115 | */ | |
1116 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1117 | val &= VLV_GTLC_ALLOWWAKEREQ; | |
1118 | val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ; | |
1119 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
1120 | ||
1121 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1122 | val &= VLV_GFX_CLK_FORCE_ON_BIT; | |
1123 | val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT; | |
1124 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
1125 | ||
1126 | I915_WRITE(VLV_PMWGICZ, s->pmwgicz); | |
1127 | ||
1128 | /* Gunit-Display CZ domain, 0x182028-0x1821CF */ | |
1129 | I915_WRITE(VLV_GU_CTL0, s->gu_ctl0); | |
1130 | I915_WRITE(VLV_GU_CTL1, s->gu_ctl1); | |
1131 | I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); | |
1132 | } | |
1133 | ||
650ad970 ID |
1134 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) |
1135 | { | |
1136 | u32 val; | |
1137 | int err; | |
1138 | ||
1139 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1140 | WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on); | |
1141 | ||
1142 | #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT) | |
1143 | /* Wait for a previous force-off to settle */ | |
1144 | if (force_on) { | |
8d4eee9c | 1145 | err = wait_for(!COND, 20); |
650ad970 ID |
1146 | if (err) { |
1147 | DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n", | |
1148 | I915_READ(VLV_GTLC_SURVIVABILITY_REG)); | |
1149 | return err; | |
1150 | } | |
1151 | } | |
1152 | ||
1153 | val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); | |
1154 | val &= ~VLV_GFX_CLK_FORCE_ON_BIT; | |
1155 | if (force_on) | |
1156 | val |= VLV_GFX_CLK_FORCE_ON_BIT; | |
1157 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); | |
1158 | ||
1159 | if (!force_on) | |
1160 | return 0; | |
1161 | ||
8d4eee9c | 1162 | err = wait_for(COND, 20); |
650ad970 ID |
1163 | if (err) |
1164 | DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n", | |
1165 | I915_READ(VLV_GTLC_SURVIVABILITY_REG)); | |
1166 | ||
1167 | return err; | |
1168 | #undef COND | |
1169 | } | |
1170 | ||
ddeea5b0 ID |
1171 | static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow) |
1172 | { | |
1173 | u32 val; | |
1174 | int err = 0; | |
1175 | ||
1176 | val = I915_READ(VLV_GTLC_WAKE_CTRL); | |
1177 | val &= ~VLV_GTLC_ALLOWWAKEREQ; | |
1178 | if (allow) | |
1179 | val |= VLV_GTLC_ALLOWWAKEREQ; | |
1180 | I915_WRITE(VLV_GTLC_WAKE_CTRL, val); | |
1181 | POSTING_READ(VLV_GTLC_WAKE_CTRL); | |
1182 | ||
1183 | #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \ | |
1184 | allow) | |
1185 | err = wait_for(COND, 1); | |
1186 | if (err) | |
1187 | DRM_ERROR("timeout disabling GT waking\n"); | |
1188 | return err; | |
1189 | #undef COND | |
1190 | } | |
1191 | ||
1192 | static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, | |
1193 | bool wait_for_on) | |
1194 | { | |
1195 | u32 mask; | |
1196 | u32 val; | |
1197 | int err; | |
1198 | ||
1199 | mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK; | |
1200 | val = wait_for_on ? mask : 0; | |
1201 | #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val) | |
1202 | if (COND) | |
1203 | return 0; | |
1204 | ||
1205 | DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n", | |
1206 | wait_for_on ? "on" : "off", | |
1207 | I915_READ(VLV_GTLC_PW_STATUS)); | |
1208 | ||
1209 | /* | |
1210 | * RC6 transitioning can be delayed up to 2 msec (see | |
1211 | * valleyview_enable_rps), use 3 msec for safety. | |
1212 | */ | |
1213 | err = wait_for(COND, 3); | |
1214 | if (err) | |
1215 | DRM_ERROR("timeout waiting for GT wells to go %s\n", | |
1216 | wait_for_on ? "on" : "off"); | |
1217 | ||
1218 | return err; | |
1219 | #undef COND | |
1220 | } | |
1221 | ||
1222 | static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) | |
1223 | { | |
1224 | if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) | |
1225 | return; | |
1226 | ||
1227 | DRM_ERROR("GT register access while GT waking disabled\n"); | |
1228 | I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); | |
1229 | } | |
1230 | ||
1231 | static int vlv_runtime_suspend(struct drm_i915_private *dev_priv) | |
1232 | { | |
1233 | u32 mask; | |
1234 | int err; | |
1235 | ||
1236 | /* | |
1237 | * Bspec defines the following GT well on flags as debug only, so | |
1238 | * don't treat them as hard failures. | |
1239 | */ | |
1240 | (void)vlv_wait_for_gt_wells(dev_priv, false); | |
1241 | ||
1242 | mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS; | |
1243 | WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask); | |
1244 | ||
1245 | vlv_check_no_gt_access(dev_priv); | |
1246 | ||
1247 | err = vlv_force_gfx_clock(dev_priv, true); | |
1248 | if (err) | |
1249 | goto err1; | |
1250 | ||
1251 | err = vlv_allow_gt_wake(dev_priv, false); | |
1252 | if (err) | |
1253 | goto err2; | |
1254 | vlv_save_gunit_s0ix_state(dev_priv); | |
1255 | ||
1256 | err = vlv_force_gfx_clock(dev_priv, false); | |
1257 | if (err) | |
1258 | goto err2; | |
1259 | ||
1260 | return 0; | |
1261 | ||
1262 | err2: | |
1263 | /* For safety always re-enable waking and disable gfx clock forcing */ | |
1264 | vlv_allow_gt_wake(dev_priv, true); | |
1265 | err1: | |
1266 | vlv_force_gfx_clock(dev_priv, false); | |
1267 | ||
1268 | return err; | |
1269 | } | |
1270 | ||
1271 | static int vlv_runtime_resume(struct drm_i915_private *dev_priv) | |
1272 | { | |
1273 | struct drm_device *dev = dev_priv->dev; | |
1274 | int err; | |
1275 | int ret; | |
1276 | ||
1277 | /* | |
1278 | * If any of the steps fail just try to continue, that's the best we | |
1279 | * can do at this point. Return the first error code (which will also | |
1280 | * leave RPM permanently disabled). | |
1281 | */ | |
1282 | ret = vlv_force_gfx_clock(dev_priv, true); | |
1283 | ||
1284 | vlv_restore_gunit_s0ix_state(dev_priv); | |
1285 | ||
1286 | err = vlv_allow_gt_wake(dev_priv, true); | |
1287 | if (!ret) | |
1288 | ret = err; | |
1289 | ||
1290 | err = vlv_force_gfx_clock(dev_priv, false); | |
1291 | if (!ret) | |
1292 | ret = err; | |
1293 | ||
1294 | vlv_check_no_gt_access(dev_priv); | |
1295 | ||
1296 | intel_init_clock_gating(dev); | |
1297 | i915_gem_restore_fences(dev); | |
1298 | ||
1299 | return ret; | |
1300 | } | |
1301 | ||
97bea207 | 1302 | static int intel_runtime_suspend(struct device *device) |
8a187455 PZ |
1303 | { |
1304 | struct pci_dev *pdev = to_pci_dev(device); | |
1305 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1306 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0ab9cfeb | 1307 | int ret; |
8a187455 | 1308 | |
aeab0b5a | 1309 | if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev)))) |
c6df39b5 ID |
1310 | return -ENODEV; |
1311 | ||
8a187455 | 1312 | WARN_ON(!HAS_RUNTIME_PM(dev)); |
e998c40f | 1313 | assert_force_wake_inactive(dev_priv); |
8a187455 PZ |
1314 | |
1315 | DRM_DEBUG_KMS("Suspending device\n"); | |
1316 | ||
9486db61 ID |
1317 | /* |
1318 | * rps.work can't be rearmed here, since we get here only after making | |
1319 | * sure the GPU is idle and the RPS freq is set to the minimum. See | |
1320 | * intel_mark_idle(). | |
1321 | */ | |
1322 | cancel_work_sync(&dev_priv->rps.work); | |
b5478bcd ID |
1323 | intel_runtime_pm_disable_interrupts(dev); |
1324 | ||
0ab9cfeb ID |
1325 | if (IS_GEN6(dev)) { |
1326 | ret = 0; | |
1327 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
1328 | ret = hsw_runtime_suspend(dev_priv); | |
ddeea5b0 ID |
1329 | } else if (IS_VALLEYVIEW(dev)) { |
1330 | ret = vlv_runtime_suspend(dev_priv); | |
0ab9cfeb ID |
1331 | } else { |
1332 | ret = -ENODEV; | |
6157d3c8 | 1333 | WARN_ON(1); |
0ab9cfeb ID |
1334 | } |
1335 | ||
1336 | if (ret) { | |
1337 | DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret); | |
1338 | intel_runtime_pm_restore_interrupts(dev); | |
1339 | ||
1340 | return ret; | |
1341 | } | |
a8a8bd54 | 1342 | |
48018a57 PZ |
1343 | i915_gem_release_all_mmaps(dev_priv); |
1344 | ||
16a3d6ef | 1345 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
8a187455 | 1346 | dev_priv->pm.suspended = true; |
1fb2362b KCA |
1347 | |
1348 | /* | |
1349 | * current versions of firmware which depend on this opregion | |
1350 | * notification have repurposed the D1 definition to mean | |
1351 | * "runtime suspended" vs. what you would normally expect (D3) | |
1352 | * to distinguish it from notifications that might be sent | |
1353 | * via the suspend path. | |
1354 | */ | |
1355 | intel_opregion_notify_adapter(dev, PCI_D1); | |
8a187455 | 1356 | |
a8a8bd54 | 1357 | DRM_DEBUG_KMS("Device suspended\n"); |
8a187455 PZ |
1358 | return 0; |
1359 | } | |
1360 | ||
97bea207 | 1361 | static int intel_runtime_resume(struct device *device) |
8a187455 PZ |
1362 | { |
1363 | struct pci_dev *pdev = to_pci_dev(device); | |
1364 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1365 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0ab9cfeb | 1366 | int ret; |
8a187455 PZ |
1367 | |
1368 | WARN_ON(!HAS_RUNTIME_PM(dev)); | |
1369 | ||
1370 | DRM_DEBUG_KMS("Resuming device\n"); | |
1371 | ||
cd2e9e90 | 1372 | intel_opregion_notify_adapter(dev, PCI_D0); |
8a187455 PZ |
1373 | dev_priv->pm.suspended = false; |
1374 | ||
0ab9cfeb ID |
1375 | if (IS_GEN6(dev)) { |
1376 | ret = snb_runtime_resume(dev_priv); | |
1377 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
1378 | ret = hsw_runtime_resume(dev_priv); | |
ddeea5b0 ID |
1379 | } else if (IS_VALLEYVIEW(dev)) { |
1380 | ret = vlv_runtime_resume(dev_priv); | |
0ab9cfeb | 1381 | } else { |
6157d3c8 | 1382 | WARN_ON(1); |
0ab9cfeb ID |
1383 | ret = -ENODEV; |
1384 | } | |
a8a8bd54 | 1385 | |
0ab9cfeb ID |
1386 | /* |
1387 | * No point of rolling back things in case of an error, as the best | |
1388 | * we can do is to hope that things will still work (and disable RPM). | |
1389 | */ | |
92b806d3 ID |
1390 | i915_gem_init_swizzling(dev); |
1391 | gen6_update_ring_freq(dev); | |
1392 | ||
b5478bcd | 1393 | intel_runtime_pm_restore_interrupts(dev); |
9486db61 | 1394 | intel_reset_gt_powersave(dev); |
b5478bcd | 1395 | |
0ab9cfeb ID |
1396 | if (ret) |
1397 | DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret); | |
1398 | else | |
1399 | DRM_DEBUG_KMS("Device resumed\n"); | |
1400 | ||
1401 | return ret; | |
8a187455 PZ |
1402 | } |
1403 | ||
b4b78d12 | 1404 | static const struct dev_pm_ops i915_pm_ops = { |
0206e353 | 1405 | .suspend = i915_pm_suspend, |
76c4b250 ID |
1406 | .suspend_late = i915_pm_suspend_late, |
1407 | .resume_early = i915_pm_resume_early, | |
0206e353 AJ |
1408 | .resume = i915_pm_resume, |
1409 | .freeze = i915_pm_freeze, | |
76c4b250 | 1410 | .thaw_early = i915_pm_thaw_early, |
0206e353 AJ |
1411 | .thaw = i915_pm_thaw, |
1412 | .poweroff = i915_pm_poweroff, | |
76c4b250 | 1413 | .restore_early = i915_pm_resume_early, |
0206e353 | 1414 | .restore = i915_pm_resume, |
97bea207 PZ |
1415 | .runtime_suspend = intel_runtime_suspend, |
1416 | .runtime_resume = intel_runtime_resume, | |
cbda12d7 ZW |
1417 | }; |
1418 | ||
78b68556 | 1419 | static const struct vm_operations_struct i915_gem_vm_ops = { |
de151cf6 | 1420 | .fault = i915_gem_fault, |
ab00b3e5 JB |
1421 | .open = drm_gem_vm_open, |
1422 | .close = drm_gem_vm_close, | |
de151cf6 JB |
1423 | }; |
1424 | ||
e08e96de AV |
1425 | static const struct file_operations i915_driver_fops = { |
1426 | .owner = THIS_MODULE, | |
1427 | .open = drm_open, | |
1428 | .release = drm_release, | |
1429 | .unlocked_ioctl = drm_ioctl, | |
1430 | .mmap = drm_gem_mmap, | |
1431 | .poll = drm_poll, | |
e08e96de AV |
1432 | .read = drm_read, |
1433 | #ifdef CONFIG_COMPAT | |
1434 | .compat_ioctl = i915_compat_ioctl, | |
1435 | #endif | |
1436 | .llseek = noop_llseek, | |
1437 | }; | |
1438 | ||
1da177e4 | 1439 | static struct drm_driver driver = { |
0c54781b MW |
1440 | /* Don't use MTRRs here; the Xserver or userspace app should |
1441 | * deal with them for Intel hardware. | |
792d2b9a | 1442 | */ |
673a394b | 1443 | .driver_features = |
24986ee0 | 1444 | DRIVER_USE_AGP | |
10ba5012 KH |
1445 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME | |
1446 | DRIVER_RENDER, | |
22eae947 | 1447 | .load = i915_driver_load, |
ba8bbcf6 | 1448 | .unload = i915_driver_unload, |
673a394b | 1449 | .open = i915_driver_open, |
22eae947 DA |
1450 | .lastclose = i915_driver_lastclose, |
1451 | .preclose = i915_driver_preclose, | |
673a394b | 1452 | .postclose = i915_driver_postclose, |
d8e29209 RW |
1453 | |
1454 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | |
1455 | .suspend = i915_suspend, | |
76c4b250 | 1456 | .resume = i915_resume_legacy, |
d8e29209 | 1457 | |
cda17380 | 1458 | .device_is_agp = i915_driver_device_is_agp, |
7c1c2871 DA |
1459 | .master_create = i915_master_create, |
1460 | .master_destroy = i915_master_destroy, | |
955b12de | 1461 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
1462 | .debugfs_init = i915_debugfs_init, |
1463 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 1464 | #endif |
673a394b | 1465 | .gem_free_object = i915_gem_free_object, |
de151cf6 | 1466 | .gem_vm_ops = &i915_gem_vm_ops, |
1286ff73 DV |
1467 | |
1468 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
1469 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
1470 | .gem_prime_export = i915_gem_prime_export, | |
1471 | .gem_prime_import = i915_gem_prime_import, | |
1472 | ||
ff72145b DA |
1473 | .dumb_create = i915_gem_dumb_create, |
1474 | .dumb_map_offset = i915_gem_mmap_gtt, | |
43387b37 | 1475 | .dumb_destroy = drm_gem_dumb_destroy, |
1da177e4 | 1476 | .ioctls = i915_ioctls, |
e08e96de | 1477 | .fops = &i915_driver_fops, |
22eae947 DA |
1478 | .name = DRIVER_NAME, |
1479 | .desc = DRIVER_DESC, | |
1480 | .date = DRIVER_DATE, | |
1481 | .major = DRIVER_MAJOR, | |
1482 | .minor = DRIVER_MINOR, | |
1483 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
1484 | }; |
1485 | ||
8410ea3b DA |
1486 | static struct pci_driver i915_pci_driver = { |
1487 | .name = DRIVER_NAME, | |
1488 | .id_table = pciidlist, | |
1489 | .probe = i915_pci_probe, | |
1490 | .remove = i915_pci_remove, | |
1491 | .driver.pm = &i915_pm_ops, | |
1492 | }; | |
1493 | ||
1da177e4 LT |
1494 | static int __init i915_init(void) |
1495 | { | |
1496 | driver.num_ioctls = i915_max_ioctl; | |
79e53945 JB |
1497 | |
1498 | /* | |
1499 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless | |
1500 | * explicitly disabled with the module pararmeter. | |
1501 | * | |
1502 | * Otherwise, just follow the parameter (defaulting to off). | |
1503 | * | |
1504 | * Allow optional vga_text_mode_force boot option to override | |
1505 | * the default behavior. | |
1506 | */ | |
1507 | #if defined(CONFIG_DRM_I915_KMS) | |
d330a953 | 1508 | if (i915.modeset != 0) |
79e53945 JB |
1509 | driver.driver_features |= DRIVER_MODESET; |
1510 | #endif | |
d330a953 | 1511 | if (i915.modeset == 1) |
79e53945 JB |
1512 | driver.driver_features |= DRIVER_MODESET; |
1513 | ||
1514 | #ifdef CONFIG_VGA_CONSOLE | |
d330a953 | 1515 | if (vgacon_text_force() && i915.modeset == -1) |
79e53945 JB |
1516 | driver.driver_features &= ~DRIVER_MODESET; |
1517 | #endif | |
1518 | ||
b30324ad | 1519 | if (!(driver.driver_features & DRIVER_MODESET)) { |
3885c6bb | 1520 | driver.get_vblank_timestamp = NULL; |
b30324ad DV |
1521 | #ifndef CONFIG_DRM_I915_UMS |
1522 | /* Silently fail loading to not upset userspace. */ | |
1523 | return 0; | |
1524 | #endif | |
1525 | } | |
3885c6bb | 1526 | |
8410ea3b | 1527 | return drm_pci_init(&driver, &i915_pci_driver); |
1da177e4 LT |
1528 | } |
1529 | ||
1530 | static void __exit i915_exit(void) | |
1531 | { | |
b33ecdd1 DV |
1532 | #ifndef CONFIG_DRM_I915_UMS |
1533 | if (!(driver.driver_features & DRIVER_MODESET)) | |
1534 | return; /* Never loaded a driver. */ | |
1535 | #endif | |
1536 | ||
8410ea3b | 1537 | drm_pci_exit(&driver, &i915_pci_driver); |
1da177e4 LT |
1538 | } |
1539 | ||
1540 | module_init(i915_init); | |
1541 | module_exit(i915_exit); | |
1542 | ||
b5e89ed5 DA |
1543 | MODULE_AUTHOR(DRIVER_AUTHOR); |
1544 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 1545 | MODULE_LICENSE("GPL and additional rights"); |