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drm/i915: Add quirk to disable SSC on Sony Vaio Y2
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
c1c7af60
JB		 27#include <linux/module.h>
28#include <linux/input.h>
79e53945 29#include <linux/i2c.h>
7662c8bd 30#include <linux/kernel.h>
5a0e3ad6 31#include <linux/slab.h>
9cce37f4 32#include <linux/vgaarb.h>
79e53945
JB		 33#include "drmP.h"
34#include "intel_drv.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
e5510fac 37#include "i915_trace.h"
ab2c0672 38#include "drm_dp_helper.h"
79e53945
JB		 39
40#include "drm_crtc_helper.h"
41
32f9d658
ZW		 42#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
79e53945 44bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
7662c8bd 45static void intel_update_watermarks(struct drm_device *dev);
3dec0095 46static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 47static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 48
49typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59} intel_clock_t;
60
61typedef struct {
62 int min, max;
63} intel_range_t;
64
65typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68} intel_p2_t;
69
70#define INTEL_P2_NUM 2
d4906093
ML		 71typedef struct intel_limit intel_limit_t;
72struct intel_limit {
79e53945
JB		 73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
d4906093
ML		 75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77};
79e53945 78
2377b741
JB		 79/* FDI */
80#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
81
d4906093
ML		 82static bool
83intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
84 int target, int refclk, intel_clock_t *best_clock);
85static bool
86intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
87 int target, int refclk, intel_clock_t *best_clock);
79e53945 88
a4fc5ed6
KP		 89static bool
90intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
91 int target, int refclk, intel_clock_t *best_clock);
5eb08b69 92static bool
f2b115e6
AJ		 93intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
94 int target, int refclk, intel_clock_t *best_clock);
a4fc5ed6 95
021357ac
CW		 96static inline u32 /* units of 100MHz */
97intel_fdi_link_freq(struct drm_device *dev)
98{
8b99e68c
CW		 99 if (IS_GEN5(dev)) {
100 struct drm_i915_private *dev_priv = dev->dev_private;
101 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
102 } else
103 return 27;
021357ac
CW		 104}
105
e4b36699 106static const intel_limit_t intel_limits_i8xx_dvo = {
273e27ca
EA		 107 .dot = { .min = 25000, .max = 350000 },
108 .vco = { .min = 930000, .max = 1400000 },
109 .n = { .min = 3, .max = 16 },
110 .m = { .min = 96, .max = 140 },
111 .m1 = { .min = 18, .max = 26 },
112 .m2 = { .min = 6, .max = 16 },
113 .p = { .min = 4, .max = 128 },
114 .p1 = { .min = 2, .max = 33 },
115 .p2 = { .dot_limit = 165000,
116 .p2_slow = 4, .p2_fast = 2 },
d4906093 117 .find_pll = intel_find_best_PLL,
e4b36699
KP		 118};
119
120static const intel_limit_t intel_limits_i8xx_lvds = {
273e27ca
EA		 121 .dot = { .min = 25000, .max = 350000 },
122 .vco = { .min = 930000, .max = 1400000 },
123 .n = { .min = 3, .max = 16 },
124 .m = { .min = 96, .max = 140 },
125 .m1 = { .min = 18, .max = 26 },
126 .m2 = { .min = 6, .max = 16 },
127 .p = { .min = 4, .max = 128 },
128 .p1 = { .min = 1, .max = 6 },
129 .p2 = { .dot_limit = 165000,
130 .p2_slow = 14, .p2_fast = 7 },
d4906093 131 .find_pll = intel_find_best_PLL,
e4b36699 132};
273e27ca 133
e4b36699 134static const intel_limit_t intel_limits_i9xx_sdvo = {
273e27ca
EA		 135 .dot = { .min = 20000, .max = 400000 },
136 .vco = { .min = 1400000, .max = 2800000 },
137 .n = { .min = 1, .max = 6 },
138 .m = { .min = 70, .max = 120 },
139 .m1 = { .min = 10, .max = 22 },
140 .m2 = { .min = 5, .max = 9 },
141 .p = { .min = 5, .max = 80 },
142 .p1 = { .min = 1, .max = 8 },
143 .p2 = { .dot_limit = 200000,
144 .p2_slow = 10, .p2_fast = 5 },
d4906093 145 .find_pll = intel_find_best_PLL,
e4b36699
KP		 146};
147
148static const intel_limit_t intel_limits_i9xx_lvds = {
273e27ca
EA		 149 .dot = { .min = 20000, .max = 400000 },
150 .vco = { .min = 1400000, .max = 2800000 },
151 .n = { .min = 1, .max = 6 },
152 .m = { .min = 70, .max = 120 },
153 .m1 = { .min = 10, .max = 22 },
154 .m2 = { .min = 5, .max = 9 },
155 .p = { .min = 7, .max = 98 },
156 .p1 = { .min = 1, .max = 8 },
157 .p2 = { .dot_limit = 112000,
158 .p2_slow = 14, .p2_fast = 7 },
d4906093 159 .find_pll = intel_find_best_PLL,
e4b36699
KP		 160};
161
273e27ca 162
e4b36699 163static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 164 .dot = { .min = 25000, .max = 270000 },
165 .vco = { .min = 1750000, .max = 3500000},
166 .n = { .min = 1, .max = 4 },
167 .m = { .min = 104, .max = 138 },
168 .m1 = { .min = 17, .max = 23 },
169 .m2 = { .min = 5, .max = 11 },
170 .p = { .min = 10, .max = 30 },
171 .p1 = { .min = 1, .max = 3},
172 .p2 = { .dot_limit = 270000,
173 .p2_slow = 10,
174 .p2_fast = 10
044c7c41 175 },
d4906093 176 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 177};
178
179static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 180 .dot = { .min = 22000, .max = 400000 },
181 .vco = { .min = 1750000, .max = 3500000},
182 .n = { .min = 1, .max = 4 },
183 .m = { .min = 104, .max = 138 },
184 .m1 = { .min = 16, .max = 23 },
185 .m2 = { .min = 5, .max = 11 },
186 .p = { .min = 5, .max = 80 },
187 .p1 = { .min = 1, .max = 8},
188 .p2 = { .dot_limit = 165000,
189 .p2_slow = 10, .p2_fast = 5 },
d4906093 190 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 191};
192
193static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 194 .dot = { .min = 20000, .max = 115000 },
195 .vco = { .min = 1750000, .max = 3500000 },
196 .n = { .min = 1, .max = 3 },
197 .m = { .min = 104, .max = 138 },
198 .m1 = { .min = 17, .max = 23 },
199 .m2 = { .min = 5, .max = 11 },
200 .p = { .min = 28, .max = 112 },
201 .p1 = { .min = 2, .max = 8 },
202 .p2 = { .dot_limit = 0,
203 .p2_slow = 14, .p2_fast = 14
044c7c41 204 },
d4906093 205 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 206};
207
208static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 209 .dot = { .min = 80000, .max = 224000 },
210 .vco = { .min = 1750000, .max = 3500000 },
211 .n = { .min = 1, .max = 3 },
212 .m = { .min = 104, .max = 138 },
213 .m1 = { .min = 17, .max = 23 },
214 .m2 = { .min = 5, .max = 11 },
215 .p = { .min = 14, .max = 42 },
216 .p1 = { .min = 2, .max = 6 },
217 .p2 = { .dot_limit = 0,
218 .p2_slow = 7, .p2_fast = 7
044c7c41 219 },
d4906093 220 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 221};
222
223static const intel_limit_t intel_limits_g4x_display_port = {
273e27ca
EA		 224 .dot = { .min = 161670, .max = 227000 },
225 .vco = { .min = 1750000, .max = 3500000},
226 .n = { .min = 1, .max = 2 },
227 .m = { .min = 97, .max = 108 },
228 .m1 = { .min = 0x10, .max = 0x12 },
229 .m2 = { .min = 0x05, .max = 0x06 },
230 .p = { .min = 10, .max = 20 },
231 .p1 = { .min = 1, .max = 2},
232 .p2 = { .dot_limit = 0,
233 .p2_slow = 10, .p2_fast = 10 },
a4fc5ed6 234 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 235};
236
f2b115e6 237static const intel_limit_t intel_limits_pineview_sdvo = {
273e27ca
EA		 238 .dot = { .min = 20000, .max = 400000},
239 .vco = { .min = 1700000, .max = 3500000 },
240 /* Pineview's Ncounter is a ring counter */
241 .n = { .min = 3, .max = 6 },
242 .m = { .min = 2, .max = 256 },
243 /* Pineview only has one combined m divider, which we treat as m2. */
244 .m1 = { .min = 0, .max = 0 },
245 .m2 = { .min = 0, .max = 254 },
246 .p = { .min = 5, .max = 80 },
247 .p1 = { .min = 1, .max = 8 },
248 .p2 = { .dot_limit = 200000,
249 .p2_slow = 10, .p2_fast = 5 },
6115707b 250 .find_pll = intel_find_best_PLL,
e4b36699
KP		 251};
252
f2b115e6 253static const intel_limit_t intel_limits_pineview_lvds = {
273e27ca
EA		 254 .dot = { .min = 20000, .max = 400000 },
255 .vco = { .min = 1700000, .max = 3500000 },
256 .n = { .min = 3, .max = 6 },
257 .m = { .min = 2, .max = 256 },
258 .m1 = { .min = 0, .max = 0 },
259 .m2 = { .min = 0, .max = 254 },
260 .p = { .min = 7, .max = 112 },
261 .p1 = { .min = 1, .max = 8 },
262 .p2 = { .dot_limit = 112000,
263 .p2_slow = 14, .p2_fast = 14 },
6115707b 264 .find_pll = intel_find_best_PLL,
e4b36699
KP		 265};
266
273e27ca
EA		 267/* Ironlake / Sandybridge
268 *
269 * We calculate clock using (register_value + 2) for N/M1/M2, so here
270 * the range value for them is (actual_value - 2).
271 */
b91ad0ec 272static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 5 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 10, .p2_fast = 5 },
4547668a 283 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 284};
285
b91ad0ec 286static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 3 },
290 .m = { .min = 79, .max = 118 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
294 .p1 = { .min = 2, .max = 8 },
295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 297 .find_pll = intel_g4x_find_best_PLL,
298};
299
300static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 3 },
304 .m = { .min = 79, .max = 127 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 14, .max = 56 },
308 .p1 = { .min = 2, .max = 8 },
309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 311 .find_pll = intel_g4x_find_best_PLL,
312};
313
273e27ca 314/* LVDS 100mhz refclk limits. */
b91ad0ec 315static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 316 .dot = { .min = 25000, .max = 350000 },
317 .vco = { .min = 1760000, .max = 3510000 },
318 .n = { .min = 1, .max = 2 },
319 .m = { .min = 79, .max = 126 },
320 .m1 = { .min = 12, .max = 22 },
321 .m2 = { .min = 5, .max = 9 },
322 .p = { .min = 28, .max = 112 },
323 .p1 = { .min = 2,.max = 8 },
324 .p2 = { .dot_limit = 225000,
325 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 326 .find_pll = intel_g4x_find_best_PLL,
327};
328
329static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 126 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 42 },
337 .p1 = { .min = 2,.max = 6 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 340 .find_pll = intel_g4x_find_best_PLL,
341};
342
343static const intel_limit_t intel_limits_ironlake_display_port = {
273e27ca
EA		 344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000},
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 81, .max = 90 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 10, .max = 20 },
351 .p1 = { .min = 1, .max = 2},
352 .p2 = { .dot_limit = 0,
353 .p2_slow = 10, .p2_fast = 10 },
4547668a 354 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 355};
356
1b894b59
CW		 357static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
358 int refclk)
2c07245f 359{
b91ad0ec
ZW		 360 struct drm_device *dev = crtc->dev;
361 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 362 const intel_limit_t *limit;
b91ad0ec
ZW		 363
364 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b91ad0ec
ZW		 365 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
366 LVDS_CLKB_POWER_UP) {
367 /* LVDS dual channel */
1b894b59 368 if (refclk == 100000)
b91ad0ec
ZW		 369 limit = &intel_limits_ironlake_dual_lvds_100m;
370 else
371 limit = &intel_limits_ironlake_dual_lvds;
372 } else {
1b894b59 373 if (refclk == 100000)
b91ad0ec
ZW		 374 limit = &intel_limits_ironlake_single_lvds_100m;
375 else
376 limit = &intel_limits_ironlake_single_lvds;
377 }
378 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 379 HAS_eDP)
380 limit = &intel_limits_ironlake_display_port;
2c07245f 381 else
b91ad0ec 382 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 383
384 return limit;
385}
386
044c7c41
ML		 387static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
388{
389 struct drm_device *dev = crtc->dev;
390 struct drm_i915_private *dev_priv = dev->dev_private;
391 const intel_limit_t *limit;
392
393 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
394 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
395 LVDS_CLKB_POWER_UP)
396 /* LVDS with dual channel */
e4b36699 397 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 398 else
399 /* LVDS with dual channel */
e4b36699 400 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 401 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
402 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 403 limit = &intel_limits_g4x_hdmi;
044c7c41 404 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 405 limit = &intel_limits_g4x_sdvo;
a4fc5ed6 406 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 407 limit = &intel_limits_g4x_display_port;
044c7c41 408 } else /* The option is for other outputs */
e4b36699 409 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 410
411 return limit;
412}
413
1b894b59 414static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 415{
416 struct drm_device *dev = crtc->dev;
417 const intel_limit_t *limit;
418
bad720ff 419 if (HAS_PCH_SPLIT(dev))
1b894b59 420 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 421 else if (IS_G4X(dev)) {
044c7c41 422 limit = intel_g4x_limit(crtc);
f2b115e6 423 } else if (IS_PINEVIEW(dev)) {
2177832f 424 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 425 limit = &intel_limits_pineview_lvds;
2177832f 426 else
f2b115e6 427 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 428 } else if (!IS_GEN2(dev)) {
429 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
430 limit = &intel_limits_i9xx_lvds;
431 else
432 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 433 } else {
434 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 435 limit = &intel_limits_i8xx_lvds;
79e53945 436 else
e4b36699 437 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 438 }
439 return limit;
440}
441
f2b115e6
AJ		 442/* m1 is reserved as 0 in Pineview, n is a ring counter */
443static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 444{
2177832f
SL		 445 clock->m = clock->m2 + 2;
446 clock->p = clock->p1 * clock->p2;
447 clock->vco = refclk * clock->m / clock->n;
448 clock->dot = clock->vco / clock->p;
449}
450
451static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
452{
f2b115e6
AJ		 453 if (IS_PINEVIEW(dev)) {
454 pineview_clock(refclk, clock);
2177832f
SL		 455 return;
456 }
79e53945
JB		 457 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
458 clock->p = clock->p1 * clock->p2;
459 clock->vco = refclk * clock->m / (clock->n + 2);
460 clock->dot = clock->vco / clock->p;
461}
462
79e53945
JB		 463/**
464 * Returns whether any output on the specified pipe is of the specified type
465 */
4ef69c7a 466bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 467{
4ef69c7a
CW		 468 struct drm_device *dev = crtc->dev;
469 struct drm_mode_config *mode_config = &dev->mode_config;
470 struct intel_encoder *encoder;
471
472 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
473 if (encoder->base.crtc == crtc && encoder->type == type)
474 return true;
475
476 return false;
79e53945
JB		 477}
478
7c04d1d9 479#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 480/**
481 * Returns whether the given set of divisors are valid for a given refclk with
482 * the given connectors.
483 */
484
1b894b59
CW		 485static bool intel_PLL_is_valid(struct drm_device *dev,
486 const intel_limit_t *limit,
487 const intel_clock_t *clock)
79e53945 488{
79e53945
JB		 489 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
490 INTELPllInvalid ("p1 out of range\n");
491 if (clock->p < limit->p.min || limit->p.max < clock->p)
492 INTELPllInvalid ("p out of range\n");
493 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
494 INTELPllInvalid ("m2 out of range\n");
495 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
496 INTELPllInvalid ("m1 out of range\n");
f2b115e6 497 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
79e53945
JB		 498 INTELPllInvalid ("m1 <= m2\n");
499 if (clock->m < limit->m.min || limit->m.max < clock->m)
500 INTELPllInvalid ("m out of range\n");
501 if (clock->n < limit->n.min || limit->n.max < clock->n)
502 INTELPllInvalid ("n out of range\n");
503 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
504 INTELPllInvalid ("vco out of range\n");
505 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
506 * connector, etc., rather than just a single range.
507 */
508 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
509 INTELPllInvalid ("dot out of range\n");
510
511 return true;
512}
513
d4906093
ML		 514static bool
515intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
516 int target, int refclk, intel_clock_t *best_clock)
517
79e53945
JB		 518{
519 struct drm_device *dev = crtc->dev;
520 struct drm_i915_private *dev_priv = dev->dev_private;
521 intel_clock_t clock;
79e53945
JB		 522 int err = target;
523
bc5e5718 524 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 525 (I915_READ(LVDS)) != 0) {
79e53945
JB		 526 /*
527 * For LVDS, if the panel is on, just rely on its current
528 * settings for dual-channel. We haven't figured out how to
529 * reliably set up different single/dual channel state, if we
530 * even can.
531 */
532 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
533 LVDS_CLKB_POWER_UP)
534 clock.p2 = limit->p2.p2_fast;
535 else
536 clock.p2 = limit->p2.p2_slow;
537 } else {
538 if (target < limit->p2.dot_limit)
539 clock.p2 = limit->p2.p2_slow;
540 else
541 clock.p2 = limit->p2.p2_fast;
542 }
543
544 memset (best_clock, 0, sizeof (*best_clock));
545
42158660
ZY		 546 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
547 clock.m1++) {
548 for (clock.m2 = limit->m2.min;
549 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 550 /* m1 is always 0 in Pineview */
551 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 552 break;
553 for (clock.n = limit->n.min;
554 clock.n <= limit->n.max; clock.n++) {
555 for (clock.p1 = limit->p1.min;
556 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 557 int this_err;
558
2177832f 559 intel_clock(dev, refclk, &clock);
1b894b59
CW		 560 if (!intel_PLL_is_valid(dev, limit,
561 &clock))
79e53945
JB		 562 continue;
563
564 this_err = abs(clock.dot - target);
565 if (this_err < err) {
566 *best_clock = clock;
567 err = this_err;
568 }
569 }
570 }
571 }
572 }
573
574 return (err != target);
575}
576
d4906093
ML		 577static bool
578intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
579 int target, int refclk, intel_clock_t *best_clock)
580{
581 struct drm_device *dev = crtc->dev;
582 struct drm_i915_private *dev_priv = dev->dev_private;
583 intel_clock_t clock;
584 int max_n;
585 bool found;
6ba770dc
AJ		 586 /* approximately equals target * 0.00585 */
587 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 588 found = false;
589
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 591 int lvds_reg;
592
c619eed4 593 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 594 lvds_reg = PCH_LVDS;
595 else
596 lvds_reg = LVDS;
597 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 598 LVDS_CLKB_POWER_UP)
599 clock.p2 = limit->p2.p2_fast;
600 else
601 clock.p2 = limit->p2.p2_slow;
602 } else {
603 if (target < limit->p2.dot_limit)
604 clock.p2 = limit->p2.p2_slow;
605 else
606 clock.p2 = limit->p2.p2_fast;
607 }
608
609 memset(best_clock, 0, sizeof(*best_clock));
610 max_n = limit->n.max;
f77f13e2 611 /* based on hardware requirement, prefer smaller n to precision */
d4906093 612 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 613 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 614 for (clock.m1 = limit->m1.max;
615 clock.m1 >= limit->m1.min; clock.m1--) {
616 for (clock.m2 = limit->m2.max;
617 clock.m2 >= limit->m2.min; clock.m2--) {
618 for (clock.p1 = limit->p1.max;
619 clock.p1 >= limit->p1.min; clock.p1--) {
620 int this_err;
621
2177832f 622 intel_clock(dev, refclk, &clock);
1b894b59
CW		 623 if (!intel_PLL_is_valid(dev, limit,
624 &clock))
d4906093 625 continue;
1b894b59
CW		 626
627 this_err = abs(clock.dot - target);
d4906093
ML		 628 if (this_err < err_most) {
629 *best_clock = clock;
630 err_most = this_err;
631 max_n = clock.n;
632 found = true;
633 }
634 }
635 }
636 }
637 }
2c07245f
ZW		 638 return found;
639}
640
5eb08b69 641static bool
f2b115e6
AJ		 642intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
643 int target, int refclk, intel_clock_t *best_clock)
5eb08b69
ZW		 644{
645 struct drm_device *dev = crtc->dev;
646 intel_clock_t clock;
4547668a 647
5eb08b69
ZW		 648 if (target < 200000) {
649 clock.n = 1;
650 clock.p1 = 2;
651 clock.p2 = 10;
652 clock.m1 = 12;
653 clock.m2 = 9;
654 } else {
655 clock.n = 2;
656 clock.p1 = 1;
657 clock.p2 = 10;
658 clock.m1 = 14;
659 clock.m2 = 8;
660 }
661 intel_clock(dev, refclk, &clock);
662 memcpy(best_clock, &clock, sizeof(intel_clock_t));
663 return true;
664}
665
a4fc5ed6
KP		 666/* DisplayPort has only two frequencies, 162MHz and 270MHz */
667static bool
668intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
669 int target, int refclk, intel_clock_t *best_clock)
670{
5eddb70b
CW		 671 intel_clock_t clock;
672 if (target < 200000) {
673 clock.p1 = 2;
674 clock.p2 = 10;
675 clock.n = 2;
676 clock.m1 = 23;
677 clock.m2 = 8;
678 } else {
679 clock.p1 = 1;
680 clock.p2 = 10;
681 clock.n = 1;
682 clock.m1 = 14;
683 clock.m2 = 2;
684 }
685 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
686 clock.p = (clock.p1 * clock.p2);
687 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
688 clock.vco = 0;
689 memcpy(best_clock, &clock, sizeof(intel_clock_t));
690 return true;
a4fc5ed6
KP		 691}
692
9d0498a2
JB		 693/**
694 * intel_wait_for_vblank - wait for vblank on a given pipe
695 * @dev: drm device
696 * @pipe: pipe to wait for
697 *
698 * Wait for vblank to occur on a given pipe. Needed for various bits of
699 * mode setting code.
700 */
701void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 702{
9d0498a2 703 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 704 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 705
300387c0
CW		 706 /* Clear existing vblank status. Note this will clear any other
707 * sticky status fields as well.
708 *
709 * This races with i915_driver_irq_handler() with the result
710 * that either function could miss a vblank event. Here it is not
711 * fatal, as we will either wait upon the next vblank interrupt or
712 * timeout. Generally speaking intel_wait_for_vblank() is only
713 * called during modeset at which time the GPU should be idle and
714 * should *not* be performing page flips and thus not waiting on
715 * vblanks...
716 * Currently, the result of us stealing a vblank from the irq
717 * handler is that a single frame will be skipped during swapbuffers.
718 */
719 I915_WRITE(pipestat_reg,
720 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
721
9d0498a2 722 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 723 if (wait_for(I915_READ(pipestat_reg) &
724 PIPE_VBLANK_INTERRUPT_STATUS,
725 50))
9d0498a2
JB		 726 DRM_DEBUG_KMS("vblank wait timed out\n");
727}
728
ab7ad7f6
KP		 729/*
730 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 731 * @dev: drm device
732 * @pipe: pipe to wait for
733 *
734 * After disabling a pipe, we can't wait for vblank in the usual way,
735 * spinning on the vblank interrupt status bit, since we won't actually
736 * see an interrupt when the pipe is disabled.
737 *
ab7ad7f6
KP		 738 * On Gen4 and above:
739 * wait for the pipe register state bit to turn off
740 *
741 * Otherwise:
742 * wait for the display line value to settle (it usually
743 * ends up stopping at the start of the next frame).
58e10eb9 744 *
9d0498a2 745 */
58e10eb9 746void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 747{
748 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 749
750 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 751 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 752
753 /* Wait for the Pipe State to go off */
58e10eb9
CW		 754 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
755 100))
ab7ad7f6
KP		 756 DRM_DEBUG_KMS("pipe_off wait timed out\n");
757 } else {
758 u32 last_line;
58e10eb9 759 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 760 unsigned long timeout = jiffies + msecs_to_jiffies(100);
761
762 /* Wait for the display line to settle */
763 do {
58e10eb9 764 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 765 mdelay(5);
58e10eb9 766 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 767 time_after(timeout, jiffies));
768 if (time_after(jiffies, timeout))
769 DRM_DEBUG_KMS("pipe_off wait timed out\n");
770 }
79e53945
JB		 771}
772
b24e7179
JB		 773static const char *state_string(bool enabled)
774{
775 return enabled ? "on" : "off";
776}
777
778/* Only for pre-ILK configs */
779static void assert_pll(struct drm_i915_private *dev_priv,
780 enum pipe pipe, bool state)
781{
782 int reg;
783 u32 val;
784 bool cur_state;
785
786 reg = DPLL(pipe);
787 val = I915_READ(reg);
788 cur_state = !!(val & DPLL_VCO_ENABLE);
789 WARN(cur_state != state,
790 "PLL state assertion failure (expected %s, current %s)\n",
791 state_string(state), state_string(cur_state));
792}
793#define assert_pll_enabled(d, p) assert_pll(d, p, true)
794#define assert_pll_disabled(d, p) assert_pll(d, p, false)
795
040484af
JB		 796/* For ILK+ */
797static void assert_pch_pll(struct drm_i915_private *dev_priv,
798 enum pipe pipe, bool state)
799{
800 int reg;
801 u32 val;
802 bool cur_state;
803
804 reg = PCH_DPLL(pipe);
805 val = I915_READ(reg);
806 cur_state = !!(val & DPLL_VCO_ENABLE);
807 WARN(cur_state != state,
808 "PCH PLL state assertion failure (expected %s, current %s)\n",
809 state_string(state), state_string(cur_state));
810}
811#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
812#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
813
814static void assert_fdi_tx(struct drm_i915_private *dev_priv,
815 enum pipe pipe, bool state)
816{
817 int reg;
818 u32 val;
819 bool cur_state;
820
821 reg = FDI_TX_CTL(pipe);
822 val = I915_READ(reg);
823 cur_state = !!(val & FDI_TX_ENABLE);
824 WARN(cur_state != state,
825 "FDI TX state assertion failure (expected %s, current %s)\n",
826 state_string(state), state_string(cur_state));
827}
828#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
829#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
830
831static void assert_fdi_rx(struct drm_i915_private *dev_priv,
832 enum pipe pipe, bool state)
833{
834 int reg;
835 u32 val;
836 bool cur_state;
837
838 reg = FDI_RX_CTL(pipe);
839 val = I915_READ(reg);
840 cur_state = !!(val & FDI_RX_ENABLE);
841 WARN(cur_state != state,
842 "FDI RX state assertion failure (expected %s, current %s)\n",
843 state_string(state), state_string(cur_state));
844}
845#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
846#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
847
848static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
849 enum pipe pipe)
850{
851 int reg;
852 u32 val;
853
854 /* ILK FDI PLL is always enabled */
855 if (dev_priv->info->gen == 5)
856 return;
857
858 reg = FDI_TX_CTL(pipe);
859 val = I915_READ(reg);
860 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
861}
862
863static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
864 enum pipe pipe)
865{
866 int reg;
867 u32 val;
868
869 reg = FDI_RX_CTL(pipe);
870 val = I915_READ(reg);
871 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
872}
873
ea0760cf
JB		 874static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
875 enum pipe pipe)
876{
877 int pp_reg, lvds_reg;
878 u32 val;
879 enum pipe panel_pipe = PIPE_A;
880 bool locked = locked;
881
882 if (HAS_PCH_SPLIT(dev_priv->dev)) {
883 pp_reg = PCH_PP_CONTROL;
884 lvds_reg = PCH_LVDS;
885 } else {
886 pp_reg = PP_CONTROL;
887 lvds_reg = LVDS;
888 }
889
890 val = I915_READ(pp_reg);
891 if (!(val & PANEL_POWER_ON) ||
892 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
893 locked = false;
894
895 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
896 panel_pipe = PIPE_B;
897
898 WARN(panel_pipe == pipe && locked,
899 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 900 pipe_name(pipe));
ea0760cf
JB		 901}
902
63d7bbe9
JB		 903static void assert_pipe(struct drm_i915_private *dev_priv,
904 enum pipe pipe, bool state)
b24e7179
JB		 905{
906 int reg;
907 u32 val;
63d7bbe9 908 bool cur_state;
b24e7179
JB		 909
910 reg = PIPECONF(pipe);
911 val = I915_READ(reg);
63d7bbe9
JB		 912 cur_state = !!(val & PIPECONF_ENABLE);
913 WARN(cur_state != state,
914 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 915 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179 916}
63d7bbe9
JB		 917#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
918#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
b24e7179
JB		 919
920static void assert_plane_enabled(struct drm_i915_private *dev_priv,
921 enum plane plane)
922{
923 int reg;
924 u32 val;
925
926 reg = DSPCNTR(plane);
927 val = I915_READ(reg);
928 WARN(!(val & DISPLAY_PLANE_ENABLE),
929 "plane %c assertion failure, should be active but is disabled\n",
9db4a9c7 930 plane_name(plane));
b24e7179
JB		 931}
932
933static void assert_planes_disabled(struct drm_i915_private *dev_priv,
934 enum pipe pipe)
935{
936 int reg, i;
937 u32 val;
938 int cur_pipe;
939
19ec1358
JB		 940 /* Planes are fixed to pipes on ILK+ */
941 if (HAS_PCH_SPLIT(dev_priv->dev))
942 return;
943
b24e7179
JB		 944 /* Need to check both planes against the pipe */
945 for (i = 0; i < 2; i++) {
946 reg = DSPCNTR(i);
947 val = I915_READ(reg);
948 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
949 DISPPLANE_SEL_PIPE_SHIFT;
950 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 951 "plane %c assertion failure, should be off on pipe %c but is still active\n",
952 plane_name(i), pipe_name(pipe));
b24e7179
JB		 953 }
954}
955
92f2584a
JB		 956static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
957{
958 u32 val;
959 bool enabled;
960
961 val = I915_READ(PCH_DREF_CONTROL);
962 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
963 DREF_SUPERSPREAD_SOURCE_MASK));
964 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
965}
966
967static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
968 enum pipe pipe)
969{
970 int reg;
971 u32 val;
972 bool enabled;
973
974 reg = TRANSCONF(pipe);
975 val = I915_READ(reg);
976 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 977 WARN(enabled,
978 "transcoder assertion failed, should be off on pipe %c but is still active\n",
979 pipe_name(pipe));
92f2584a
JB		 980}
981
f0575e92
KP		 982static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, enum pipe pipe,
983 int reg, u32 port_sel, u32 val)
984{
985 if ((val & DP_PORT_EN) == 0)
986 return false;
987
988 if (HAS_PCH_CPT(dev_priv->dev)) {
989 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
990 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
991 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
992 return false;
993 } else {
994 if ((val & DP_PIPE_MASK) != (pipe << 30))
995 return false;
996 }
997 return true;
998}
999
291906f1 1000static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1001 enum pipe pipe, int reg, u32 port_sel)
291906f1 1002{
47a05eca 1003 u32 val = I915_READ(reg);
f0575e92 1004 WARN(dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val),
291906f1 1005 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1006 reg, pipe_name(pipe));
291906f1
JB		 1007}
1008
1009static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1010 enum pipe pipe, int reg)
1011{
47a05eca
JB		 1012 u32 val = I915_READ(reg);
1013 WARN(HDMI_PIPE_ENABLED(val, pipe),
291906f1 1014 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1015 reg, pipe_name(pipe));
291906f1
JB		 1016}
1017
1018static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1019 enum pipe pipe)
1020{
1021 int reg;
1022 u32 val;
291906f1 1023
f0575e92
KP		 1024 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1025 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1026 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1027
1028 reg = PCH_ADPA;
1029 val = I915_READ(reg);
47a05eca 1030 WARN(ADPA_PIPE_ENABLED(val, pipe),
291906f1 1031 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1032 pipe_name(pipe));
291906f1
JB		 1033
1034 reg = PCH_LVDS;
1035 val = I915_READ(reg);
47a05eca 1036 WARN(LVDS_PIPE_ENABLED(val, pipe),
291906f1 1037 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1038 pipe_name(pipe));
291906f1
JB		 1039
1040 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1041 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1042 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1043}
1044
63d7bbe9
JB		 1045/**
1046 * intel_enable_pll - enable a PLL
1047 * @dev_priv: i915 private structure
1048 * @pipe: pipe PLL to enable
1049 *
1050 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1051 * make sure the PLL reg is writable first though, since the panel write
1052 * protect mechanism may be enabled.
1053 *
1054 * Note! This is for pre-ILK only.
1055 */
1056static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1057{
1058 int reg;
1059 u32 val;
1060
1061 /* No really, not for ILK+ */
1062 BUG_ON(dev_priv->info->gen >= 5);
1063
1064 /* PLL is protected by panel, make sure we can write it */
1065 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1066 assert_panel_unlocked(dev_priv, pipe);
1067
1068 reg = DPLL(pipe);
1069 val = I915_READ(reg);
1070 val |= DPLL_VCO_ENABLE;
1071
1072 /* We do this three times for luck */
1073 I915_WRITE(reg, val);
1074 POSTING_READ(reg);
1075 udelay(150); /* wait for warmup */
1076 I915_WRITE(reg, val);
1077 POSTING_READ(reg);
1078 udelay(150); /* wait for warmup */
1079 I915_WRITE(reg, val);
1080 POSTING_READ(reg);
1081 udelay(150); /* wait for warmup */
1082}
1083
1084/**
1085 * intel_disable_pll - disable a PLL
1086 * @dev_priv: i915 private structure
1087 * @pipe: pipe PLL to disable
1088 *
1089 * Disable the PLL for @pipe, making sure the pipe is off first.
1090 *
1091 * Note! This is for pre-ILK only.
1092 */
1093static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1094{
1095 int reg;
1096 u32 val;
1097
1098 /* Don't disable pipe A or pipe A PLLs if needed */
1099 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1100 return;
1101
1102 /* Make sure the pipe isn't still relying on us */
1103 assert_pipe_disabled(dev_priv, pipe);
1104
1105 reg = DPLL(pipe);
1106 val = I915_READ(reg);
1107 val &= ~DPLL_VCO_ENABLE;
1108 I915_WRITE(reg, val);
1109 POSTING_READ(reg);
1110}
1111
92f2584a
JB		 1112/**
1113 * intel_enable_pch_pll - enable PCH PLL
1114 * @dev_priv: i915 private structure
1115 * @pipe: pipe PLL to enable
1116 *
1117 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1118 * drives the transcoder clock.
1119 */
1120static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1121 enum pipe pipe)
1122{
1123 int reg;
1124 u32 val;
1125
1126 /* PCH only available on ILK+ */
1127 BUG_ON(dev_priv->info->gen < 5);
1128
1129 /* PCH refclock must be enabled first */
1130 assert_pch_refclk_enabled(dev_priv);
1131
1132 reg = PCH_DPLL(pipe);
1133 val = I915_READ(reg);
1134 val |= DPLL_VCO_ENABLE;
1135 I915_WRITE(reg, val);
1136 POSTING_READ(reg);
1137 udelay(200);
1138}
1139
1140static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1141 enum pipe pipe)
1142{
1143 int reg;
1144 u32 val;
1145
1146 /* PCH only available on ILK+ */
1147 BUG_ON(dev_priv->info->gen < 5);
1148
1149 /* Make sure transcoder isn't still depending on us */
1150 assert_transcoder_disabled(dev_priv, pipe);
1151
1152 reg = PCH_DPLL(pipe);
1153 val = I915_READ(reg);
1154 val &= ~DPLL_VCO_ENABLE;
1155 I915_WRITE(reg, val);
1156 POSTING_READ(reg);
1157 udelay(200);
1158}
1159
040484af
JB		 1160static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1161 enum pipe pipe)
1162{
1163 int reg;
1164 u32 val;
1165
1166 /* PCH only available on ILK+ */
1167 BUG_ON(dev_priv->info->gen < 5);
1168
1169 /* Make sure PCH DPLL is enabled */
1170 assert_pch_pll_enabled(dev_priv, pipe);
1171
1172 /* FDI must be feeding us bits for PCH ports */
1173 assert_fdi_tx_enabled(dev_priv, pipe);
1174 assert_fdi_rx_enabled(dev_priv, pipe);
1175
1176 reg = TRANSCONF(pipe);
1177 val = I915_READ(reg);
1178 /*
1179 * make the BPC in transcoder be consistent with
1180 * that in pipeconf reg.
1181 */
1182 val &= ~PIPE_BPC_MASK;
1183 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1184 I915_WRITE(reg, val | TRANS_ENABLE);
1185 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1186 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1187}
1188
1189static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1190 enum pipe pipe)
1191{
1192 int reg;
1193 u32 val;
1194
1195 /* FDI relies on the transcoder */
1196 assert_fdi_tx_disabled(dev_priv, pipe);
1197 assert_fdi_rx_disabled(dev_priv, pipe);
1198
291906f1
JB		 1199 /* Ports must be off as well */
1200 assert_pch_ports_disabled(dev_priv, pipe);
1201
040484af
JB		 1202 reg = TRANSCONF(pipe);
1203 val = I915_READ(reg);
1204 val &= ~TRANS_ENABLE;
1205 I915_WRITE(reg, val);
1206 /* wait for PCH transcoder off, transcoder state */
1207 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1208 DRM_ERROR("failed to disable transcoder\n");
1209}
1210
b24e7179 1211/**
309cfea8 1212 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1213 * @dev_priv: i915 private structure
1214 * @pipe: pipe to enable
040484af 1215 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1216 *
1217 * Enable @pipe, making sure that various hardware specific requirements
1218 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1219 *
1220 * @pipe should be %PIPE_A or %PIPE_B.
1221 *
1222 * Will wait until the pipe is actually running (i.e. first vblank) before
1223 * returning.
1224 */
040484af
JB		 1225static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1226 bool pch_port)
b24e7179
JB		 1227{
1228 int reg;
1229 u32 val;
1230
1231 /*
1232 * A pipe without a PLL won't actually be able to drive bits from
1233 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1234 * need the check.
1235 */
1236 if (!HAS_PCH_SPLIT(dev_priv->dev))
1237 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1238 else {
1239 if (pch_port) {
1240 /* if driving the PCH, we need FDI enabled */
1241 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1242 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1243 }
1244 /* FIXME: assert CPU port conditions for SNB+ */
1245 }
b24e7179
JB		 1246
1247 reg = PIPECONF(pipe);
1248 val = I915_READ(reg);
00d70b15
CW		 1249 if (val & PIPECONF_ENABLE)
1250 return;
1251
1252 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1253 intel_wait_for_vblank(dev_priv->dev, pipe);
1254}
1255
1256/**
309cfea8 1257 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1258 * @dev_priv: i915 private structure
1259 * @pipe: pipe to disable
1260 *
1261 * Disable @pipe, making sure that various hardware specific requirements
1262 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1263 *
1264 * @pipe should be %PIPE_A or %PIPE_B.
1265 *
1266 * Will wait until the pipe has shut down before returning.
1267 */
1268static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1269 enum pipe pipe)
1270{
1271 int reg;
1272 u32 val;
1273
1274 /*
1275 * Make sure planes won't keep trying to pump pixels to us,
1276 * or we might hang the display.
1277 */
1278 assert_planes_disabled(dev_priv, pipe);
1279
1280 /* Don't disable pipe A or pipe A PLLs if needed */
1281 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1282 return;
1283
1284 reg = PIPECONF(pipe);
1285 val = I915_READ(reg);
00d70b15
CW		 1286 if ((val & PIPECONF_ENABLE) == 0)
1287 return;
1288
1289 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1290 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1291}
1292
d74362c9
KP		 1293/*
1294 * Plane regs are double buffered, going from enabled->disabled needs a
1295 * trigger in order to latch. The display address reg provides this.
1296 */
1297static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1298 enum plane plane)
1299{
1300 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1301 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1302}
1303
b24e7179
JB		 1304/**
1305 * intel_enable_plane - enable a display plane on a given pipe
1306 * @dev_priv: i915 private structure
1307 * @plane: plane to enable
1308 * @pipe: pipe being fed
1309 *
1310 * Enable @plane on @pipe, making sure that @pipe is running first.
1311 */
1312static void intel_enable_plane(struct drm_i915_private *dev_priv,
1313 enum plane plane, enum pipe pipe)
1314{
1315 int reg;
1316 u32 val;
1317
1318 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1319 assert_pipe_enabled(dev_priv, pipe);
1320
1321 reg = DSPCNTR(plane);
1322 val = I915_READ(reg);
00d70b15
CW		 1323 if (val & DISPLAY_PLANE_ENABLE)
1324 return;
1325
1326 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1327 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1328 intel_wait_for_vblank(dev_priv->dev, pipe);
1329}
1330
b24e7179
JB		 1331/**
1332 * intel_disable_plane - disable a display plane
1333 * @dev_priv: i915 private structure
1334 * @plane: plane to disable
1335 * @pipe: pipe consuming the data
1336 *
1337 * Disable @plane; should be an independent operation.
1338 */
1339static void intel_disable_plane(struct drm_i915_private *dev_priv,
1340 enum plane plane, enum pipe pipe)
1341{
1342 int reg;
1343 u32 val;
1344
1345 reg = DSPCNTR(plane);
1346 val = I915_READ(reg);
00d70b15
CW		 1347 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1348 return;
1349
1350 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1351 intel_flush_display_plane(dev_priv, plane);
1352 intel_wait_for_vblank(dev_priv->dev, pipe);
1353}
1354
47a05eca 1355static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1356 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1357{
1358 u32 val = I915_READ(reg);
f0575e92
KP		 1359 if (dp_pipe_enabled(dev_priv, pipe, reg, port_sel, val)) {
1360 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1361 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1362 }
47a05eca
JB		 1363}
1364
1365static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1366 enum pipe pipe, int reg)
1367{
1368 u32 val = I915_READ(reg);
f0575e92
KP		 1369 if (HDMI_PIPE_ENABLED(val, pipe)) {
1370 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1371 reg, pipe);
47a05eca 1372 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1373 }
47a05eca
JB		 1374}
1375
1376/* Disable any ports connected to this transcoder */
1377static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1378 enum pipe pipe)
1379{
1380 u32 reg, val;
1381
1382 val = I915_READ(PCH_PP_CONTROL);
1383 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1384
f0575e92
KP		 1385 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1386 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1387 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1388
1389 reg = PCH_ADPA;
1390 val = I915_READ(reg);
1391 if (ADPA_PIPE_ENABLED(val, pipe))
1392 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1393
1394 reg = PCH_LVDS;
1395 val = I915_READ(reg);
1396 if (LVDS_PIPE_ENABLED(val, pipe)) {
1397 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1398 POSTING_READ(reg);
1399 udelay(100);
1400 }
1401
1402 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1403 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1404 disable_pch_hdmi(dev_priv, pipe, HDMID);
1405}
1406
80824003
JB		 1407static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1408{
1409 struct drm_device *dev = crtc->dev;
1410 struct drm_i915_private *dev_priv = dev->dev_private;
1411 struct drm_framebuffer *fb = crtc->fb;
1412 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1413 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003
JB		 1414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1415 int plane, i;
1416 u32 fbc_ctl, fbc_ctl2;
1417
bed4a673 1418 if (fb->pitch == dev_priv->cfb_pitch &&
05394f39 1419 obj->fence_reg == dev_priv->cfb_fence &&
bed4a673
CW		 1420 intel_crtc->plane == dev_priv->cfb_plane &&
1421 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1422 return;
1423
1424 i8xx_disable_fbc(dev);
1425
80824003
JB		 1426 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1427
1428 if (fb->pitch < dev_priv->cfb_pitch)
1429 dev_priv->cfb_pitch = fb->pitch;
1430
1431 /* FBC_CTL wants 64B units */
1432 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1433 dev_priv->cfb_fence = obj->fence_reg;
80824003
JB		 1434 dev_priv->cfb_plane = intel_crtc->plane;
1435 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1436
1437 /* Clear old tags */
1438 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1439 I915_WRITE(FBC_TAG + (i * 4), 0);
1440
1441 /* Set it up... */
1442 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
05394f39 1443 if (obj->tiling_mode != I915_TILING_NONE)
80824003
JB		 1444 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1445 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1446 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1447
1448 /* enable it... */
1449 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1450 if (IS_I945GM(dev))
49677901 1451 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
80824003
JB		 1452 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1453 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
05394f39 1454 if (obj->tiling_mode != I915_TILING_NONE)
80824003
JB		 1455 fbc_ctl |= dev_priv->cfb_fence;
1456 I915_WRITE(FBC_CONTROL, fbc_ctl);
1457
28c97730 1458 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
5eddb70b 1459 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
80824003
JB		 1460}
1461
1462void i8xx_disable_fbc(struct drm_device *dev)
1463{
1464 struct drm_i915_private *dev_priv = dev->dev_private;
1465 u32 fbc_ctl;
1466
1467 /* Disable compression */
1468 fbc_ctl = I915_READ(FBC_CONTROL);
a5cad620
CW		 1469 if ((fbc_ctl & FBC_CTL_EN) == 0)
1470 return;
1471
80824003
JB		 1472 fbc_ctl &= ~FBC_CTL_EN;
1473 I915_WRITE(FBC_CONTROL, fbc_ctl);
1474
1475 /* Wait for compressing bit to clear */
481b6af3 1476 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
913d8d11
CW		 1477 DRM_DEBUG_KMS("FBC idle timed out\n");
1478 return;
9517a92f 1479 }
80824003 1480
28c97730 1481 DRM_DEBUG_KMS("disabled FBC\n");
80824003
JB		 1482}
1483
ee5382ae 1484static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1485{
80824003
JB		 1486 struct drm_i915_private *dev_priv = dev->dev_private;
1487
1488 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1489}
1490
74dff282
JB		 1491static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1492{
1493 struct drm_device *dev = crtc->dev;
1494 struct drm_i915_private *dev_priv = dev->dev_private;
1495 struct drm_framebuffer *fb = crtc->fb;
1496 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1497 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1499 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB		 1500 unsigned long stall_watermark = 200;
1501 u32 dpfc_ctl;
1502
bed4a673
CW		 1503 dpfc_ctl = I915_READ(DPFC_CONTROL);
1504 if (dpfc_ctl & DPFC_CTL_EN) {
1505 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
05394f39 1506 dev_priv->cfb_fence == obj->fence_reg &&
bed4a673
CW		 1507 dev_priv->cfb_plane == intel_crtc->plane &&
1508 dev_priv->cfb_y == crtc->y)
1509 return;
1510
1511 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
bed4a673
CW		 1512 intel_wait_for_vblank(dev, intel_crtc->pipe);
1513 }
1514
74dff282 1515 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1516 dev_priv->cfb_fence = obj->fence_reg;
74dff282 1517 dev_priv->cfb_plane = intel_crtc->plane;
bed4a673 1518 dev_priv->cfb_y = crtc->y;
74dff282
JB		 1519
1520 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
05394f39 1521 if (obj->tiling_mode != I915_TILING_NONE) {
74dff282
JB		 1522 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1523 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1524 } else {
1525 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1526 }
1527
74dff282
JB		 1528 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1529 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1530 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1531 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1532
1533 /* enable it... */
1534 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1535
28c97730 1536 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB		 1537}
1538
1539void g4x_disable_fbc(struct drm_device *dev)
1540{
1541 struct drm_i915_private *dev_priv = dev->dev_private;
1542 u32 dpfc_ctl;
1543
1544 /* Disable compression */
1545 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW		 1546 if (dpfc_ctl & DPFC_CTL_EN) {
1547 dpfc_ctl &= ~DPFC_CTL_EN;
1548 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1549
bed4a673
CW		 1550 DRM_DEBUG_KMS("disabled FBC\n");
1551 }
74dff282
JB		 1552}
1553
ee5382ae 1554static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1555{
74dff282
JB		 1556 struct drm_i915_private *dev_priv = dev->dev_private;
1557
1558 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1559}
1560
4efe0708
JB		 1561static void sandybridge_blit_fbc_update(struct drm_device *dev)
1562{
1563 struct drm_i915_private *dev_priv = dev->dev_private;
1564 u32 blt_ecoskpd;
1565
1566 /* Make sure blitter notifies FBC of writes */
fcca7926 1567 gen6_gt_force_wake_get(dev_priv);
4efe0708
JB		 1568 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1569 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1570 GEN6_BLITTER_LOCK_SHIFT;
1571 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1572 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1573 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1574 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1575 GEN6_BLITTER_LOCK_SHIFT);
1576 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1577 POSTING_READ(GEN6_BLITTER_ECOSKPD);
fcca7926 1578 gen6_gt_force_wake_put(dev_priv);
4efe0708
JB		 1579}
1580
b52eb4dc
ZY		 1581static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1582{
1583 struct drm_device *dev = crtc->dev;
1584 struct drm_i915_private *dev_priv = dev->dev_private;
1585 struct drm_framebuffer *fb = crtc->fb;
1586 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1587 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1588 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1589 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY		 1590 unsigned long stall_watermark = 200;
1591 u32 dpfc_ctl;
1592
bed4a673
CW		 1593 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1594 if (dpfc_ctl & DPFC_CTL_EN) {
1595 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
05394f39 1596 dev_priv->cfb_fence == obj->fence_reg &&
bed4a673 1597 dev_priv->cfb_plane == intel_crtc->plane &&
05394f39 1598 dev_priv->cfb_offset == obj->gtt_offset &&
bed4a673
CW		 1599 dev_priv->cfb_y == crtc->y)
1600 return;
1601
1602 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
bed4a673
CW		 1603 intel_wait_for_vblank(dev, intel_crtc->pipe);
1604 }
1605
b52eb4dc 1606 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1607 dev_priv->cfb_fence = obj->fence_reg;
b52eb4dc 1608 dev_priv->cfb_plane = intel_crtc->plane;
05394f39 1609 dev_priv->cfb_offset = obj->gtt_offset;
bed4a673 1610 dev_priv->cfb_y = crtc->y;
b52eb4dc 1611
b52eb4dc
ZY		 1612 dpfc_ctl &= DPFC_RESERVED;
1613 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
05394f39 1614 if (obj->tiling_mode != I915_TILING_NONE) {
b52eb4dc
ZY		 1615 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1616 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1617 } else {
1618 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1619 }
1620
b52eb4dc
ZY		 1621 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1622 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1623 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1624 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1625 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1626 /* enable it... */
bed4a673 1627 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc 1628
9c04f015
YL		 1629 if (IS_GEN6(dev)) {
1630 I915_WRITE(SNB_DPFC_CTL_SA,
1631 SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1632 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
4efe0708 1633 sandybridge_blit_fbc_update(dev);
9c04f015
YL		 1634 }
1635
b52eb4dc
ZY		 1636 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1637}
1638
1639void ironlake_disable_fbc(struct drm_device *dev)
1640{
1641 struct drm_i915_private *dev_priv = dev->dev_private;
1642 u32 dpfc_ctl;
1643
1644 /* Disable compression */
1645 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW		 1646 if (dpfc_ctl & DPFC_CTL_EN) {
1647 dpfc_ctl &= ~DPFC_CTL_EN;
1648 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1649
bed4a673
CW		 1650 DRM_DEBUG_KMS("disabled FBC\n");
1651 }
b52eb4dc
ZY		 1652}
1653
1654static bool ironlake_fbc_enabled(struct drm_device *dev)
1655{
1656 struct drm_i915_private *dev_priv = dev->dev_private;
1657
1658 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1659}
1660
ee5382ae
AJ		 1661bool intel_fbc_enabled(struct drm_device *dev)
1662{
1663 struct drm_i915_private *dev_priv = dev->dev_private;
1664
1665 if (!dev_priv->display.fbc_enabled)
1666 return false;
1667
1668 return dev_priv->display.fbc_enabled(dev);
1669}
1670
1671void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1672{
1673 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1674
1675 if (!dev_priv->display.enable_fbc)
1676 return;
1677
1678 dev_priv->display.enable_fbc(crtc, interval);
1679}
1680
1681void intel_disable_fbc(struct drm_device *dev)
1682{
1683 struct drm_i915_private *dev_priv = dev->dev_private;
1684
1685 if (!dev_priv->display.disable_fbc)
1686 return;
1687
1688 dev_priv->display.disable_fbc(dev);
1689}
1690
80824003
JB		 1691/**
1692 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1693 * @dev: the drm_device
80824003
JB		 1694 *
1695 * Set up the framebuffer compression hardware at mode set time. We
1696 * enable it if possible:
1697 * - plane A only (on pre-965)
1698 * - no pixel mulitply/line duplication
1699 * - no alpha buffer discard
1700 * - no dual wide
1701 * - framebuffer <= 2048 in width, 1536 in height
1702 *
1703 * We can't assume that any compression will take place (worst case),
1704 * so the compressed buffer has to be the same size as the uncompressed
1705 * one. It also must reside (along with the line length buffer) in
1706 * stolen memory.
1707 *
1708 * We need to enable/disable FBC on a global basis.
1709 */
bed4a673 1710static void intel_update_fbc(struct drm_device *dev)
80824003 1711{
80824003 1712 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW		 1713 struct drm_crtc *crtc = NULL, *tmp_crtc;
1714 struct intel_crtc *intel_crtc;
1715 struct drm_framebuffer *fb;
80824003 1716 struct intel_framebuffer *intel_fb;
05394f39 1717 struct drm_i915_gem_object *obj;
9c928d16
JB		 1718
1719 DRM_DEBUG_KMS("\n");
80824003
JB		 1720
1721 if (!i915_powersave)
1722 return;
1723
ee5382ae 1724 if (!I915_HAS_FBC(dev))
e70236a8
JB		 1725 return;
1726
80824003
JB		 1727 /*
1728 * If FBC is already on, we just have to verify that we can
1729 * keep it that way...
1730 * Need to disable if:
9c928d16 1731 * - more than one pipe is active
80824003
JB		 1732 * - changing FBC params (stride, fence, mode)
1733 * - new fb is too large to fit in compressed buffer
1734 * - going to an unsupported config (interlace, pixel multiply, etc.)
1735 */
9c928d16 1736 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
d210246a 1737 if (tmp_crtc->enabled && tmp_crtc->fb) {
bed4a673
CW		 1738 if (crtc) {
1739 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1740 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1741 goto out_disable;
1742 }
1743 crtc = tmp_crtc;
1744 }
9c928d16 1745 }
bed4a673
CW		 1746
1747 if (!crtc || crtc->fb == NULL) {
1748 DRM_DEBUG_KMS("no output, disabling\n");
1749 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB		 1750 goto out_disable;
1751 }
bed4a673
CW		 1752
1753 intel_crtc = to_intel_crtc(crtc);
1754 fb = crtc->fb;
1755 intel_fb = to_intel_framebuffer(fb);
05394f39 1756 obj = intel_fb->obj;
bed4a673 1757
c1a9f047
JB		 1758 if (!i915_enable_fbc) {
1759 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1760 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1761 goto out_disable;
1762 }
05394f39 1763 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 1764 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 1765 "compression\n");
b5e50c3f 1766 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1767 goto out_disable;
1768 }
bed4a673
CW		 1769 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1770 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 1771 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 1772 "disabling\n");
b5e50c3f 1773 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB		 1774 goto out_disable;
1775 }
bed4a673
CW		 1776 if ((crtc->mode.hdisplay > 2048) ||
1777 (crtc->mode.vdisplay > 1536)) {
28c97730 1778 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 1779 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB		 1780 goto out_disable;
1781 }
bed4a673 1782 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 1783 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 1784 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB		 1785 goto out_disable;
1786 }
05394f39 1787 if (obj->tiling_mode != I915_TILING_X) {
28c97730 1788 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
b5e50c3f 1789 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB		 1790 goto out_disable;
1791 }
1792
c924b934
JW		 1793 /* If the kernel debugger is active, always disable compression */
1794 if (in_dbg_master())
1795 goto out_disable;
1796
bed4a673 1797 intel_enable_fbc(crtc, 500);
80824003
JB		 1798 return;
1799
1800out_disable:
80824003 1801 /* Multiple disables should be harmless */
a939406f
CW		 1802 if (intel_fbc_enabled(dev)) {
1803 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 1804 intel_disable_fbc(dev);
a939406f 1805 }
80824003
JB		 1806}
1807
127bd2ac 1808int
48b956c5 1809intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1810 struct drm_i915_gem_object *obj,
919926ae 1811 struct intel_ring_buffer *pipelined)
6b95a207 1812{
ce453d81 1813 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1814 u32 alignment;
1815 int ret;
1816
05394f39 1817 switch (obj->tiling_mode) {
6b95a207 1818 case I915_TILING_NONE:
534843da
CW		 1819 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1820 alignment = 128 * 1024;
a6c45cf0 1821 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1822 alignment = 4 * 1024;
1823 else
1824 alignment = 64 * 1024;
6b95a207
KH		 1825 break;
1826 case I915_TILING_X:
1827 /* pin() will align the object as required by fence */
1828 alignment = 0;
1829 break;
1830 case I915_TILING_Y:
1831 /* FIXME: Is this true? */
1832 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1833 return -EINVAL;
1834 default:
1835 BUG();
1836 }
1837
ce453d81 1838 dev_priv->mm.interruptible = false;
75e9e915 1839 ret = i915_gem_object_pin(obj, alignment, true);
48b956c5 1840 if (ret)
ce453d81 1841 goto err_interruptible;
6b95a207 1842
48b956c5
CW		 1843 ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1844 if (ret)
1845 goto err_unpin;
7213342d 1846
6b95a207
KH		 1847 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1848 * fence, whereas 965+ only requires a fence if using
1849 * framebuffer compression. For simplicity, we always install
1850 * a fence as the cost is not that onerous.
1851 */
05394f39 1852 if (obj->tiling_mode != I915_TILING_NONE) {
ce453d81 1853 ret = i915_gem_object_get_fence(obj, pipelined);
48b956c5
CW		 1854 if (ret)
1855 goto err_unpin;
6b95a207
KH		 1856 }
1857
ce453d81 1858 dev_priv->mm.interruptible = true;
6b95a207 1859 return 0;
48b956c5
CW		 1860
1861err_unpin:
1862 i915_gem_object_unpin(obj);
ce453d81
CW		 1863err_interruptible:
1864 dev_priv->mm.interruptible = true;
48b956c5 1865 return ret;
6b95a207
KH		 1866}
1867
81255565
JB		 1868/* Assume fb object is pinned & idle & fenced and just update base pointers */
1869static int
1870intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
21c74a8e 1871 int x, int y, enum mode_set_atomic state)
81255565
JB		 1872{
1873 struct drm_device *dev = crtc->dev;
1874 struct drm_i915_private *dev_priv = dev->dev_private;
1875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1876 struct intel_framebuffer *intel_fb;
05394f39 1877 struct drm_i915_gem_object *obj;
81255565
JB		 1878 int plane = intel_crtc->plane;
1879 unsigned long Start, Offset;
81255565 1880 u32 dspcntr;
5eddb70b 1881 u32 reg;
81255565
JB		 1882
1883 switch (plane) {
1884 case 0:
1885 case 1:
1886 break;
1887 default:
1888 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1889 return -EINVAL;
1890 }
1891
1892 intel_fb = to_intel_framebuffer(fb);
1893 obj = intel_fb->obj;
81255565 1894
5eddb70b
CW		 1895 reg = DSPCNTR(plane);
1896 dspcntr = I915_READ(reg);
81255565
JB		 1897 /* Mask out pixel format bits in case we change it */
1898 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1899 switch (fb->bits_per_pixel) {
1900 case 8:
1901 dspcntr |= DISPPLANE_8BPP;
1902 break;
1903 case 16:
1904 if (fb->depth == 15)
1905 dspcntr |= DISPPLANE_15_16BPP;
1906 else
1907 dspcntr |= DISPPLANE_16BPP;
1908 break;
1909 case 24:
1910 case 32:
1911 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1912 break;
1913 default:
1914 DRM_ERROR("Unknown color depth\n");
1915 return -EINVAL;
1916 }
a6c45cf0 1917 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1918 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1919 dspcntr |= DISPPLANE_TILED;
1920 else
1921 dspcntr &= ~DISPPLANE_TILED;
1922 }
1923
4e6cfefc 1924 if (HAS_PCH_SPLIT(dev))
81255565
JB		 1925 /* must disable */
1926 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1927
5eddb70b 1928 I915_WRITE(reg, dspcntr);
81255565 1929
05394f39 1930 Start = obj->gtt_offset;
81255565
JB		 1931 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1932
4e6cfefc
CW		 1933 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1934 Start, Offset, x, y, fb->pitch);
5eddb70b 1935 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
a6c45cf0 1936 if (INTEL_INFO(dev)->gen >= 4) {
5eddb70b
CW		 1937 I915_WRITE(DSPSURF(plane), Start);
1938 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1939 I915_WRITE(DSPADDR(plane), Offset);
1940 } else
1941 I915_WRITE(DSPADDR(plane), Start + Offset);
1942 POSTING_READ(reg);
81255565 1943
bed4a673 1944 intel_update_fbc(dev);
3dec0095 1945 intel_increase_pllclock(crtc);
81255565
JB		 1946
1947 return 0;
1948}
1949
5c3b82e2 1950static int
3c4fdcfb
KH		 1951intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1952 struct drm_framebuffer *old_fb)
79e53945
JB		 1953{
1954 struct drm_device *dev = crtc->dev;
79e53945
JB		 1955 struct drm_i915_master_private *master_priv;
1956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 1957 int ret;
79e53945
JB		 1958
1959 /* no fb bound */
1960 if (!crtc->fb) {
013a41ec 1961 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 1962 return 0;
1963 }
1964
265db958 1965 switch (intel_crtc->plane) {
5c3b82e2
CW		 1966 case 0:
1967 case 1:
1968 break;
1969 default:
013a41ec 1970 DRM_ERROR("no plane for crtc\n");
5c3b82e2 1971 return -EINVAL;
79e53945
JB		 1972 }
1973
5c3b82e2 1974 mutex_lock(&dev->struct_mutex);
265db958
CW		 1975 ret = intel_pin_and_fence_fb_obj(dev,
1976 to_intel_framebuffer(crtc->fb)->obj,
919926ae 1977 NULL);
5c3b82e2
CW		 1978 if (ret != 0) {
1979 mutex_unlock(&dev->struct_mutex);
013a41ec 1980 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 1981 return ret;
1982 }
79e53945 1983
265db958 1984 if (old_fb) {
e6c3a2a6 1985 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1986 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
265db958 1987
e6c3a2a6 1988 wait_event(dev_priv->pending_flip_queue,
01eec727 1989 atomic_read(&dev_priv->mm.wedged) ||
05394f39 1990 atomic_read(&obj->pending_flip) == 0);
85345517
CW		 1991
1992 /* Big Hammer, we also need to ensure that any pending
1993 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1994 * current scanout is retired before unpinning the old
1995 * framebuffer.
01eec727
CW		 1996 *
1997 * This should only fail upon a hung GPU, in which case we
1998 * can safely continue.
85345517 1999 */
ce453d81 2000 ret = i915_gem_object_flush_gpu(obj);
01eec727 2001 (void) ret;
265db958
CW		 2002 }
2003
21c74a8e
JW		 2004 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2005 LEAVE_ATOMIC_MODE_SET);
4e6cfefc 2006 if (ret) {
265db958 2007 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2008 mutex_unlock(&dev->struct_mutex);
013a41ec 2009 DRM_ERROR("failed to update base address\n");
4e6cfefc 2010 return ret;
79e53945 2011 }
3c4fdcfb 2012
b7f1de28
CW		 2013 if (old_fb) {
2014 intel_wait_for_vblank(dev, intel_crtc->pipe);
265db958 2015 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2016 }
652c393a 2017
5c3b82e2 2018 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2019
2020 if (!dev->primary->master)
5c3b82e2 2021 return 0;
79e53945
JB		 2022
2023 master_priv = dev->primary->master->driver_priv;
2024 if (!master_priv->sarea_priv)
5c3b82e2 2025 return 0;
79e53945 2026
265db958 2027 if (intel_crtc->pipe) {
79e53945
JB		 2028 master_priv->sarea_priv->pipeB_x = x;
2029 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2030 } else {
2031 master_priv->sarea_priv->pipeA_x = x;
2032 master_priv->sarea_priv->pipeA_y = y;
79e53945 2033 }
5c3b82e2
CW		 2034
2035 return 0;
79e53945
JB		 2036}
2037
5eddb70b 2038static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2039{
2040 struct drm_device *dev = crtc->dev;
2041 struct drm_i915_private *dev_priv = dev->dev_private;
2042 u32 dpa_ctl;
2043
28c97730 2044 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2045 dpa_ctl = I915_READ(DP_A);
2046 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2047
2048 if (clock < 200000) {
2049 u32 temp;
2050 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2051 /* workaround for 160Mhz:
2052 1) program 0x4600c bits 15:0 = 0x8124
2053 2) program 0x46010 bit 0 = 1
2054 3) program 0x46034 bit 24 = 1
2055 4) program 0x64000 bit 14 = 1
2056 */
2057 temp = I915_READ(0x4600c);
2058 temp &= 0xffff0000;
2059 I915_WRITE(0x4600c, temp | 0x8124);
2060
2061 temp = I915_READ(0x46010);
2062 I915_WRITE(0x46010, temp | 1);
2063
2064 temp = I915_READ(0x46034);
2065 I915_WRITE(0x46034, temp | (1 << 24));
2066 } else {
2067 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2068 }
2069 I915_WRITE(DP_A, dpa_ctl);
2070
5eddb70b 2071 POSTING_READ(DP_A);
32f9d658
ZW		 2072 udelay(500);
2073}
2074
5e84e1a4
ZW		 2075static void intel_fdi_normal_train(struct drm_crtc *crtc)
2076{
2077 struct drm_device *dev = crtc->dev;
2078 struct drm_i915_private *dev_priv = dev->dev_private;
2079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2080 int pipe = intel_crtc->pipe;
2081 u32 reg, temp;
2082
2083 /* enable normal train */
2084 reg = FDI_TX_CTL(pipe);
2085 temp = I915_READ(reg);
61e499bf 2086 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2087 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2088 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2089 } else {
2090 temp &= ~FDI_LINK_TRAIN_NONE;
2091 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2092 }
5e84e1a4
ZW		 2093 I915_WRITE(reg, temp);
2094
2095 reg = FDI_RX_CTL(pipe);
2096 temp = I915_READ(reg);
2097 if (HAS_PCH_CPT(dev)) {
2098 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2099 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2100 } else {
2101 temp &= ~FDI_LINK_TRAIN_NONE;
2102 temp |= FDI_LINK_TRAIN_NONE;
2103 }
2104 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2105
2106 /* wait one idle pattern time */
2107 POSTING_READ(reg);
2108 udelay(1000);
357555c0
JB		 2109
2110 /* IVB wants error correction enabled */
2111 if (IS_IVYBRIDGE(dev))
2112 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2113 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2114}
2115
8db9d77b
ZW		 2116/* The FDI link training functions for ILK/Ibexpeak. */
2117static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2118{
2119 struct drm_device *dev = crtc->dev;
2120 struct drm_i915_private *dev_priv = dev->dev_private;
2121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2122 int pipe = intel_crtc->pipe;
0fc932b8 2123 int plane = intel_crtc->plane;
5eddb70b 2124 u32 reg, temp, tries;
8db9d77b 2125
0fc932b8
JB		 2126 /* FDI needs bits from pipe & plane first */
2127 assert_pipe_enabled(dev_priv, pipe);
2128 assert_plane_enabled(dev_priv, plane);
2129
e1a44743
AJ		 2130 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2131 for train result */
5eddb70b
CW		 2132 reg = FDI_RX_IMR(pipe);
2133 temp = I915_READ(reg);
e1a44743
AJ		 2134 temp &= ~FDI_RX_SYMBOL_LOCK;
2135 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2136 I915_WRITE(reg, temp);
2137 I915_READ(reg);
e1a44743
AJ		 2138 udelay(150);
2139
8db9d77b 2140 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2141 reg = FDI_TX_CTL(pipe);
2142 temp = I915_READ(reg);
77ffb597
AJ		 2143 temp &= ~(7 << 19);
2144 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2145 temp &= ~FDI_LINK_TRAIN_NONE;
2146 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2147 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2148
5eddb70b
CW		 2149 reg = FDI_RX_CTL(pipe);
2150 temp = I915_READ(reg);
8db9d77b
ZW		 2151 temp &= ~FDI_LINK_TRAIN_NONE;
2152 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2153 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2154
2155 POSTING_READ(reg);
8db9d77b
ZW		 2156 udelay(150);
2157
5b2adf89 2158 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2159 if (HAS_PCH_IBX(dev)) {
2160 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2161 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2162 FDI_RX_PHASE_SYNC_POINTER_EN);
2163 }
5b2adf89 2164
5eddb70b 2165 reg = FDI_RX_IIR(pipe);
e1a44743 2166 for (tries = 0; tries < 5; tries++) {
5eddb70b 2167 temp = I915_READ(reg);
8db9d77b
ZW		 2168 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2169
2170 if ((temp & FDI_RX_BIT_LOCK)) {
2171 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2172 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2173 break;
2174 }
8db9d77b 2175 }
e1a44743 2176 if (tries == 5)
5eddb70b 2177 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2178
2179 /* Train 2 */
5eddb70b
CW		 2180 reg = FDI_TX_CTL(pipe);
2181 temp = I915_READ(reg);
8db9d77b
ZW		 2182 temp &= ~FDI_LINK_TRAIN_NONE;
2183 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2184 I915_WRITE(reg, temp);
8db9d77b 2185
5eddb70b
CW		 2186 reg = FDI_RX_CTL(pipe);
2187 temp = I915_READ(reg);
8db9d77b
ZW		 2188 temp &= ~FDI_LINK_TRAIN_NONE;
2189 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2190 I915_WRITE(reg, temp);
8db9d77b 2191
5eddb70b
CW		 2192 POSTING_READ(reg);
2193 udelay(150);
8db9d77b 2194
5eddb70b 2195 reg = FDI_RX_IIR(pipe);
e1a44743 2196 for (tries = 0; tries < 5; tries++) {
5eddb70b 2197 temp = I915_READ(reg);
8db9d77b
ZW		 2198 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2199
2200 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2201 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2202 DRM_DEBUG_KMS("FDI train 2 done.\n");
2203 break;
2204 }
8db9d77b 2205 }
e1a44743 2206 if (tries == 5)
5eddb70b 2207 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2208
2209 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2210
8db9d77b
ZW		 2211}
2212
311bd68e 2213static const int snb_b_fdi_train_param [] = {
8db9d77b
ZW		 2214 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2215 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2216 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2217 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2218};
2219
2220/* The FDI link training functions for SNB/Cougarpoint. */
2221static void gen6_fdi_link_train(struct drm_crtc *crtc)
2222{
2223 struct drm_device *dev = crtc->dev;
2224 struct drm_i915_private *dev_priv = dev->dev_private;
2225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2226 int pipe = intel_crtc->pipe;
5eddb70b 2227 u32 reg, temp, i;
8db9d77b 2228
e1a44743
AJ		 2229 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2230 for train result */
5eddb70b
CW		 2231 reg = FDI_RX_IMR(pipe);
2232 temp = I915_READ(reg);
e1a44743
AJ		 2233 temp &= ~FDI_RX_SYMBOL_LOCK;
2234 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2235 I915_WRITE(reg, temp);
2236
2237 POSTING_READ(reg);
e1a44743
AJ		 2238 udelay(150);
2239
8db9d77b 2240 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2241 reg = FDI_TX_CTL(pipe);
2242 temp = I915_READ(reg);
77ffb597
AJ		 2243 temp &= ~(7 << 19);
2244 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2245 temp &= ~FDI_LINK_TRAIN_NONE;
2246 temp |= FDI_LINK_TRAIN_PATTERN_1;
2247 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2248 /* SNB-B */
2249 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2250 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2251
5eddb70b
CW		 2252 reg = FDI_RX_CTL(pipe);
2253 temp = I915_READ(reg);
8db9d77b
ZW		 2254 if (HAS_PCH_CPT(dev)) {
2255 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2256 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2257 } else {
2258 temp &= ~FDI_LINK_TRAIN_NONE;
2259 temp |= FDI_LINK_TRAIN_PATTERN_1;
2260 }
5eddb70b
CW		 2261 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2262
2263 POSTING_READ(reg);
8db9d77b
ZW		 2264 udelay(150);
2265
8db9d77b 2266 for (i = 0; i < 4; i++ ) {
5eddb70b
CW		 2267 reg = FDI_TX_CTL(pipe);
2268 temp = I915_READ(reg);
8db9d77b
ZW		 2269 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2270 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2271 I915_WRITE(reg, temp);
2272
2273 POSTING_READ(reg);
8db9d77b
ZW		 2274 udelay(500);
2275
5eddb70b
CW		 2276 reg = FDI_RX_IIR(pipe);
2277 temp = I915_READ(reg);
8db9d77b
ZW		 2278 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2279
2280 if (temp & FDI_RX_BIT_LOCK) {
5eddb70b 2281 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2282 DRM_DEBUG_KMS("FDI train 1 done.\n");
2283 break;
2284 }
2285 }
2286 if (i == 4)
5eddb70b 2287 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2288
2289 /* Train 2 */
5eddb70b
CW		 2290 reg = FDI_TX_CTL(pipe);
2291 temp = I915_READ(reg);
8db9d77b
ZW		 2292 temp &= ~FDI_LINK_TRAIN_NONE;
2293 temp |= FDI_LINK_TRAIN_PATTERN_2;
2294 if (IS_GEN6(dev)) {
2295 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2296 /* SNB-B */
2297 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2298 }
5eddb70b 2299 I915_WRITE(reg, temp);
8db9d77b 2300
5eddb70b
CW		 2301 reg = FDI_RX_CTL(pipe);
2302 temp = I915_READ(reg);
8db9d77b
ZW		 2303 if (HAS_PCH_CPT(dev)) {
2304 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2305 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2306 } else {
2307 temp &= ~FDI_LINK_TRAIN_NONE;
2308 temp |= FDI_LINK_TRAIN_PATTERN_2;
2309 }
5eddb70b
CW		 2310 I915_WRITE(reg, temp);
2311
2312 POSTING_READ(reg);
8db9d77b
ZW		 2313 udelay(150);
2314
2315 for (i = 0; i < 4; i++ ) {
5eddb70b
CW		 2316 reg = FDI_TX_CTL(pipe);
2317 temp = I915_READ(reg);
8db9d77b
ZW		 2318 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2319 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2320 I915_WRITE(reg, temp);
2321
2322 POSTING_READ(reg);
8db9d77b
ZW		 2323 udelay(500);
2324
5eddb70b
CW		 2325 reg = FDI_RX_IIR(pipe);
2326 temp = I915_READ(reg);
8db9d77b
ZW		 2327 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2328
2329 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2330 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2331 DRM_DEBUG_KMS("FDI train 2 done.\n");
2332 break;
2333 }
2334 }
2335 if (i == 4)
5eddb70b 2336 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2337
2338 DRM_DEBUG_KMS("FDI train done.\n");
2339}
2340
357555c0
JB		 2341/* Manual link training for Ivy Bridge A0 parts */
2342static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2343{
2344 struct drm_device *dev = crtc->dev;
2345 struct drm_i915_private *dev_priv = dev->dev_private;
2346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2347 int pipe = intel_crtc->pipe;
2348 u32 reg, temp, i;
2349
2350 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2351 for train result */
2352 reg = FDI_RX_IMR(pipe);
2353 temp = I915_READ(reg);
2354 temp &= ~FDI_RX_SYMBOL_LOCK;
2355 temp &= ~FDI_RX_BIT_LOCK;
2356 I915_WRITE(reg, temp);
2357
2358 POSTING_READ(reg);
2359 udelay(150);
2360
2361 /* enable CPU FDI TX and PCH FDI RX */
2362 reg = FDI_TX_CTL(pipe);
2363 temp = I915_READ(reg);
2364 temp &= ~(7 << 19);
2365 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2366 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2367 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2368 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2369 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2370 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2371
2372 reg = FDI_RX_CTL(pipe);
2373 temp = I915_READ(reg);
2374 temp &= ~FDI_LINK_TRAIN_AUTO;
2375 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2376 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2377 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2378
2379 POSTING_READ(reg);
2380 udelay(150);
2381
2382 for (i = 0; i < 4; i++ ) {
2383 reg = FDI_TX_CTL(pipe);
2384 temp = I915_READ(reg);
2385 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2386 temp |= snb_b_fdi_train_param[i];
2387 I915_WRITE(reg, temp);
2388
2389 POSTING_READ(reg);
2390 udelay(500);
2391
2392 reg = FDI_RX_IIR(pipe);
2393 temp = I915_READ(reg);
2394 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2395
2396 if (temp & FDI_RX_BIT_LOCK ||
2397 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2398 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2399 DRM_DEBUG_KMS("FDI train 1 done.\n");
2400 break;
2401 }
2402 }
2403 if (i == 4)
2404 DRM_ERROR("FDI train 1 fail!\n");
2405
2406 /* Train 2 */
2407 reg = FDI_TX_CTL(pipe);
2408 temp = I915_READ(reg);
2409 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2410 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2411 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2412 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2413 I915_WRITE(reg, temp);
2414
2415 reg = FDI_RX_CTL(pipe);
2416 temp = I915_READ(reg);
2417 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2418 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2419 I915_WRITE(reg, temp);
2420
2421 POSTING_READ(reg);
2422 udelay(150);
2423
2424 for (i = 0; i < 4; i++ ) {
2425 reg = FDI_TX_CTL(pipe);
2426 temp = I915_READ(reg);
2427 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2428 temp |= snb_b_fdi_train_param[i];
2429 I915_WRITE(reg, temp);
2430
2431 POSTING_READ(reg);
2432 udelay(500);
2433
2434 reg = FDI_RX_IIR(pipe);
2435 temp = I915_READ(reg);
2436 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2437
2438 if (temp & FDI_RX_SYMBOL_LOCK) {
2439 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2440 DRM_DEBUG_KMS("FDI train 2 done.\n");
2441 break;
2442 }
2443 }
2444 if (i == 4)
2445 DRM_ERROR("FDI train 2 fail!\n");
2446
2447 DRM_DEBUG_KMS("FDI train done.\n");
2448}
2449
2450static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2451{
2452 struct drm_device *dev = crtc->dev;
2453 struct drm_i915_private *dev_priv = dev->dev_private;
2454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2455 int pipe = intel_crtc->pipe;
5eddb70b 2456 u32 reg, temp;
79e53945 2457
c64e311e 2458 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2459 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2460 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2461
c98e9dcf 2462 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2463 reg = FDI_RX_CTL(pipe);
2464 temp = I915_READ(reg);
2465 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2466 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2467 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2468 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2469
2470 POSTING_READ(reg);
c98e9dcf
JB		 2471 udelay(200);
2472
2473 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2474 temp = I915_READ(reg);
2475 I915_WRITE(reg, temp | FDI_PCDCLK);
2476
2477 POSTING_READ(reg);
c98e9dcf
JB		 2478 udelay(200);
2479
2480 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2481 reg = FDI_TX_CTL(pipe);
2482 temp = I915_READ(reg);
c98e9dcf 2483 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2484 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2485
2486 POSTING_READ(reg);
c98e9dcf 2487 udelay(100);
6be4a607 2488 }
0e23b99d
JB		 2489}
2490
0fc932b8
JB		 2491static void ironlake_fdi_disable(struct drm_crtc *crtc)
2492{
2493 struct drm_device *dev = crtc->dev;
2494 struct drm_i915_private *dev_priv = dev->dev_private;
2495 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2496 int pipe = intel_crtc->pipe;
2497 u32 reg, temp;
2498
2499 /* disable CPU FDI tx and PCH FDI rx */
2500 reg = FDI_TX_CTL(pipe);
2501 temp = I915_READ(reg);
2502 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2503 POSTING_READ(reg);
2504
2505 reg = FDI_RX_CTL(pipe);
2506 temp = I915_READ(reg);
2507 temp &= ~(0x7 << 16);
2508 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2509 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2510
2511 POSTING_READ(reg);
2512 udelay(100);
2513
2514 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2515 if (HAS_PCH_IBX(dev)) {
2516 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2517 I915_WRITE(FDI_RX_CHICKEN(pipe),
2518 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18
JB		 2519 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2520 }
0fc932b8
JB		 2521
2522 /* still set train pattern 1 */
2523 reg = FDI_TX_CTL(pipe);
2524 temp = I915_READ(reg);
2525 temp &= ~FDI_LINK_TRAIN_NONE;
2526 temp |= FDI_LINK_TRAIN_PATTERN_1;
2527 I915_WRITE(reg, temp);
2528
2529 reg = FDI_RX_CTL(pipe);
2530 temp = I915_READ(reg);
2531 if (HAS_PCH_CPT(dev)) {
2532 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2533 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2534 } else {
2535 temp &= ~FDI_LINK_TRAIN_NONE;
2536 temp |= FDI_LINK_TRAIN_PATTERN_1;
2537 }
2538 /* BPC in FDI rx is consistent with that in PIPECONF */
2539 temp &= ~(0x07 << 16);
2540 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2541 I915_WRITE(reg, temp);
2542
2543 POSTING_READ(reg);
2544 udelay(100);
2545}
2546
6b383a7f
CW		 2547/*
2548 * When we disable a pipe, we need to clear any pending scanline wait events
2549 * to avoid hanging the ring, which we assume we are waiting on.
2550 */
2551static void intel_clear_scanline_wait(struct drm_device *dev)
2552{
2553 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 2554 struct intel_ring_buffer *ring;
6b383a7f
CW		 2555 u32 tmp;
2556
2557 if (IS_GEN2(dev))
2558 /* Can't break the hang on i8xx */
2559 return;
2560
1ec14ad3 2561 ring = LP_RING(dev_priv);
8168bd48
CW		 2562 tmp = I915_READ_CTL(ring);
2563 if (tmp & RING_WAIT)
2564 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 2565}
2566
e6c3a2a6
CW		 2567static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2568{
05394f39 2569 struct drm_i915_gem_object *obj;
e6c3a2a6
CW		 2570 struct drm_i915_private *dev_priv;
2571
2572 if (crtc->fb == NULL)
2573 return;
2574
05394f39 2575 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW		 2576 dev_priv = crtc->dev->dev_private;
2577 wait_event(dev_priv->pending_flip_queue,
05394f39 2578 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW		 2579}
2580
040484af
JB		 2581static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2582{
2583 struct drm_device *dev = crtc->dev;
2584 struct drm_mode_config *mode_config = &dev->mode_config;
2585 struct intel_encoder *encoder;
2586
2587 /*
2588 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2589 * must be driven by its own crtc; no sharing is possible.
2590 */
2591 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2592 if (encoder->base.crtc != crtc)
2593 continue;
2594
2595 switch (encoder->type) {
2596 case INTEL_OUTPUT_EDP:
2597 if (!intel_encoder_is_pch_edp(&encoder->base))
2598 return false;
2599 continue;
2600 }
2601 }
2602
2603 return true;
2604}
2605
f67a559d
JB		 2606/*
2607 * Enable PCH resources required for PCH ports:
2608 * - PCH PLLs
2609 * - FDI training & RX/TX
2610 * - update transcoder timings
2611 * - DP transcoding bits
2612 * - transcoder
2613 */
2614static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2615{
2616 struct drm_device *dev = crtc->dev;
2617 struct drm_i915_private *dev_priv = dev->dev_private;
2618 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2619 int pipe = intel_crtc->pipe;
5eddb70b 2620 u32 reg, temp;
2c07245f 2621
c98e9dcf 2622 /* For PCH output, training FDI link */
674cf967 2623 dev_priv->display.fdi_link_train(crtc);
2c07245f 2624
92f2584a 2625 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 2626
c98e9dcf
JB		 2627 if (HAS_PCH_CPT(dev)) {
2628 /* Be sure PCH DPLL SEL is set */
2629 temp = I915_READ(PCH_DPLL_SEL);
5eddb70b 2630 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
c98e9dcf 2631 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
5eddb70b 2632 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
c98e9dcf
JB		 2633 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2634 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2635 }
5eddb70b 2636
d9b6cb56
JB		 2637 /* set transcoder timing, panel must allow it */
2638 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2639 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2640 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2641 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2642
5eddb70b
CW		 2643 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2644 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2645 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
8db9d77b 2646
5e84e1a4
ZW		 2647 intel_fdi_normal_train(crtc);
2648
c98e9dcf
JB		 2649 /* For PCH DP, enable TRANS_DP_CTL */
2650 if (HAS_PCH_CPT(dev) &&
2651 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5eddb70b
CW		 2652 reg = TRANS_DP_CTL(pipe);
2653 temp = I915_READ(reg);
2654 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2655 TRANS_DP_SYNC_MASK |
2656 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2657 temp |= (TRANS_DP_OUTPUT_ENABLE |
2658 TRANS_DP_ENH_FRAMING);
220cad3c 2659 temp |= TRANS_DP_8BPC;
c98e9dcf
JB		 2660
2661 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2662 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2663 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2664 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2665
2666 switch (intel_trans_dp_port_sel(crtc)) {
2667 case PCH_DP_B:
5eddb70b 2668 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2669 break;
2670 case PCH_DP_C:
5eddb70b 2671 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2672 break;
2673 case PCH_DP_D:
5eddb70b 2674 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2675 break;
2676 default:
2677 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2678 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2679 break;
32f9d658 2680 }
2c07245f 2681
5eddb70b 2682 I915_WRITE(reg, temp);
6be4a607 2683 }
b52eb4dc 2684
040484af 2685 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2686}
2687
2688static void ironlake_crtc_enable(struct drm_crtc *crtc)
2689{
2690 struct drm_device *dev = crtc->dev;
2691 struct drm_i915_private *dev_priv = dev->dev_private;
2692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2693 int pipe = intel_crtc->pipe;
2694 int plane = intel_crtc->plane;
2695 u32 temp;
2696 bool is_pch_port;
2697
2698 if (intel_crtc->active)
2699 return;
2700
2701 intel_crtc->active = true;
2702 intel_update_watermarks(dev);
2703
2704 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2705 temp = I915_READ(PCH_LVDS);
2706 if ((temp & LVDS_PORT_EN) == 0)
2707 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2708 }
2709
2710 is_pch_port = intel_crtc_driving_pch(crtc);
2711
2712 if (is_pch_port)
357555c0 2713 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 2714 else
2715 ironlake_fdi_disable(crtc);
2716
2717 /* Enable panel fitting for LVDS */
2718 if (dev_priv->pch_pf_size &&
2719 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2720 /* Force use of hard-coded filter coefficients
2721 * as some pre-programmed values are broken,
2722 * e.g. x201.
2723 */
9db4a9c7
JB		 2724 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2725 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2726 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 2727 }
2728
9c54c0dd
JB		 2729 /*
2730 * On ILK+ LUT must be loaded before the pipe is running but with
2731 * clocks enabled
2732 */
2733 intel_crtc_load_lut(crtc);
2734
f67a559d
JB		 2735 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2736 intel_enable_plane(dev_priv, plane, pipe);
2737
2738 if (is_pch_port)
2739 ironlake_pch_enable(crtc);
c98e9dcf 2740
d1ebd816 2741 mutex_lock(&dev->struct_mutex);
bed4a673 2742 intel_update_fbc(dev);
d1ebd816
BW		 2743 mutex_unlock(&dev->struct_mutex);
2744
6b383a7f 2745 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 2746}
2747
2748static void ironlake_crtc_disable(struct drm_crtc *crtc)
2749{
2750 struct drm_device *dev = crtc->dev;
2751 struct drm_i915_private *dev_priv = dev->dev_private;
2752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2753 int pipe = intel_crtc->pipe;
2754 int plane = intel_crtc->plane;
5eddb70b 2755 u32 reg, temp;
b52eb4dc 2756
f7abfe8b
CW		 2757 if (!intel_crtc->active)
2758 return;
2759
e6c3a2a6 2760 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 2761 drm_vblank_off(dev, pipe);
6b383a7f 2762 intel_crtc_update_cursor(crtc, false);
5eddb70b 2763
b24e7179 2764 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 2765
6be4a607
JB		 2766 if (dev_priv->cfb_plane == plane &&
2767 dev_priv->display.disable_fbc)
2768 dev_priv->display.disable_fbc(dev);
2c07245f 2769
b24e7179 2770 intel_disable_pipe(dev_priv, pipe);
32f9d658 2771
6be4a607 2772 /* Disable PF */
9db4a9c7
JB		 2773 I915_WRITE(PF_CTL(pipe), 0);
2774 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 2775
0fc932b8 2776 ironlake_fdi_disable(crtc);
2c07245f 2777
47a05eca
JB		 2778 /* This is a horrible layering violation; we should be doing this in
2779 * the connector/encoder ->prepare instead, but we don't always have
2780 * enough information there about the config to know whether it will
2781 * actually be necessary or just cause undesired flicker.
2782 */
2783 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 2784
040484af 2785 intel_disable_transcoder(dev_priv, pipe);
913d8d11 2786
6be4a607
JB		 2787 if (HAS_PCH_CPT(dev)) {
2788 /* disable TRANS_DP_CTL */
5eddb70b
CW		 2789 reg = TRANS_DP_CTL(pipe);
2790 temp = I915_READ(reg);
2791 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 2792 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 2793 I915_WRITE(reg, temp);
6be4a607
JB		 2794
2795 /* disable DPLL_SEL */
2796 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 2797 switch (pipe) {
2798 case 0:
2799 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2800 break;
2801 case 1:
6be4a607 2802 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 2803 break;
2804 case 2:
2805 /* FIXME: manage transcoder PLLs? */
2806 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2807 break;
2808 default:
2809 BUG(); /* wtf */
2810 }
6be4a607 2811 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 2812 }
e3421a18 2813
6be4a607 2814 /* disable PCH DPLL */
92f2584a 2815 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 2816
6be4a607 2817 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 2818 reg = FDI_RX_CTL(pipe);
2819 temp = I915_READ(reg);
2820 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 2821
6be4a607 2822 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 2823 reg = FDI_TX_CTL(pipe);
2824 temp = I915_READ(reg);
2825 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2826
2827 POSTING_READ(reg);
6be4a607 2828 udelay(100);
8db9d77b 2829
5eddb70b
CW		 2830 reg = FDI_RX_CTL(pipe);
2831 temp = I915_READ(reg);
2832 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 2833
6be4a607 2834 /* Wait for the clocks to turn off. */
5eddb70b 2835 POSTING_READ(reg);
6be4a607 2836 udelay(100);
6b383a7f 2837
f7abfe8b 2838 intel_crtc->active = false;
6b383a7f 2839 intel_update_watermarks(dev);
d1ebd816
BW		 2840
2841 mutex_lock(&dev->struct_mutex);
6b383a7f
CW		 2842 intel_update_fbc(dev);
2843 intel_clear_scanline_wait(dev);
d1ebd816 2844 mutex_unlock(&dev->struct_mutex);
6be4a607 2845}
1b3c7a47 2846
6be4a607
JB		 2847static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2848{
2849 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2850 int pipe = intel_crtc->pipe;
2851 int plane = intel_crtc->plane;
8db9d77b 2852
6be4a607
JB		 2853 /* XXX: When our outputs are all unaware of DPMS modes other than off
2854 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2855 */
2856 switch (mode) {
2857 case DRM_MODE_DPMS_ON:
2858 case DRM_MODE_DPMS_STANDBY:
2859 case DRM_MODE_DPMS_SUSPEND:
2860 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2861 ironlake_crtc_enable(crtc);
2862 break;
1b3c7a47 2863
6be4a607
JB		 2864 case DRM_MODE_DPMS_OFF:
2865 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2866 ironlake_crtc_disable(crtc);
2c07245f
ZW		 2867 break;
2868 }
2869}
2870
02e792fb
DV		 2871static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2872{
02e792fb 2873 if (!enable && intel_crtc->overlay) {
23f09ce3 2874 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 2875 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 2876
23f09ce3 2877 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 2878 dev_priv->mm.interruptible = false;
2879 (void) intel_overlay_switch_off(intel_crtc->overlay);
2880 dev_priv->mm.interruptible = true;
23f09ce3 2881 mutex_unlock(&dev->struct_mutex);
02e792fb 2882 }
02e792fb 2883
5dcdbcb0
CW		 2884 /* Let userspace switch the overlay on again. In most cases userspace
2885 * has to recompute where to put it anyway.
2886 */
02e792fb
DV		 2887}
2888
0b8765c6 2889static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 2890{
2891 struct drm_device *dev = crtc->dev;
79e53945
JB		 2892 struct drm_i915_private *dev_priv = dev->dev_private;
2893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2894 int pipe = intel_crtc->pipe;
80824003 2895 int plane = intel_crtc->plane;
79e53945 2896
f7abfe8b
CW		 2897 if (intel_crtc->active)
2898 return;
2899
2900 intel_crtc->active = true;
6b383a7f
CW		 2901 intel_update_watermarks(dev);
2902
63d7bbe9 2903 intel_enable_pll(dev_priv, pipe);
040484af 2904 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 2905 intel_enable_plane(dev_priv, plane, pipe);
79e53945 2906
0b8765c6 2907 intel_crtc_load_lut(crtc);
bed4a673 2908 intel_update_fbc(dev);
79e53945 2909
0b8765c6
JB		 2910 /* Give the overlay scaler a chance to enable if it's on this pipe */
2911 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 2912 intel_crtc_update_cursor(crtc, true);
0b8765c6 2913}
79e53945 2914
0b8765c6
JB		 2915static void i9xx_crtc_disable(struct drm_crtc *crtc)
2916{
2917 struct drm_device *dev = crtc->dev;
2918 struct drm_i915_private *dev_priv = dev->dev_private;
2919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2920 int pipe = intel_crtc->pipe;
2921 int plane = intel_crtc->plane;
b690e96c 2922
f7abfe8b
CW		 2923 if (!intel_crtc->active)
2924 return;
2925
0b8765c6 2926 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 2927 intel_crtc_wait_for_pending_flips(crtc);
2928 drm_vblank_off(dev, pipe);
0b8765c6 2929 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 2930 intel_crtc_update_cursor(crtc, false);
0b8765c6
JB		 2931
2932 if (dev_priv->cfb_plane == plane &&
2933 dev_priv->display.disable_fbc)
2934 dev_priv->display.disable_fbc(dev);
79e53945 2935
b24e7179 2936 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 2937 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 2938 intel_disable_pll(dev_priv, pipe);
0b8765c6 2939
f7abfe8b 2940 intel_crtc->active = false;
6b383a7f
CW		 2941 intel_update_fbc(dev);
2942 intel_update_watermarks(dev);
2943 intel_clear_scanline_wait(dev);
0b8765c6
JB		 2944}
2945
2946static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2947{
2948 /* XXX: When our outputs are all unaware of DPMS modes other than off
2949 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2950 */
2951 switch (mode) {
2952 case DRM_MODE_DPMS_ON:
2953 case DRM_MODE_DPMS_STANDBY:
2954 case DRM_MODE_DPMS_SUSPEND:
2955 i9xx_crtc_enable(crtc);
2956 break;
2957 case DRM_MODE_DPMS_OFF:
2958 i9xx_crtc_disable(crtc);
79e53945
JB		 2959 break;
2960 }
2c07245f
ZW		 2961}
2962
2963/**
2964 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 2965 */
2966static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2967{
2968 struct drm_device *dev = crtc->dev;
e70236a8 2969 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 2970 struct drm_i915_master_private *master_priv;
2971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2972 int pipe = intel_crtc->pipe;
2973 bool enabled;
2974
032d2a0d
CW		 2975 if (intel_crtc->dpms_mode == mode)
2976 return;
2977
65655d4a 2978 intel_crtc->dpms_mode = mode;
debcaddc 2979
e70236a8 2980 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 2981
2982 if (!dev->primary->master)
2983 return;
2984
2985 master_priv = dev->primary->master->driver_priv;
2986 if (!master_priv->sarea_priv)
2987 return;
2988
2989 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2990
2991 switch (pipe) {
2992 case 0:
2993 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2994 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2995 break;
2996 case 1:
2997 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2998 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2999 break;
3000 default:
9db4a9c7 3001 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3002 break;
3003 }
79e53945
JB		 3004}
3005
cdd59983
CW		 3006static void intel_crtc_disable(struct drm_crtc *crtc)
3007{
3008 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3009 struct drm_device *dev = crtc->dev;
3010
3011 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3012
3013 if (crtc->fb) {
3014 mutex_lock(&dev->struct_mutex);
3015 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3016 mutex_unlock(&dev->struct_mutex);
3017 }
3018}
3019
7e7d76c3
JB		 3020/* Prepare for a mode set.
3021 *
3022 * Note we could be a lot smarter here. We need to figure out which outputs
3023 * will be enabled, which disabled (in short, how the config will changes)
3024 * and perform the minimum necessary steps to accomplish that, e.g. updating
3025 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3026 * panel fitting is in the proper state, etc.
3027 */
3028static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3029{
7e7d76c3 3030 i9xx_crtc_disable(crtc);
79e53945
JB		 3031}
3032
7e7d76c3 3033static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3034{
7e7d76c3 3035 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3036}
3037
3038static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3039{
7e7d76c3 3040 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3041}
3042
3043static void ironlake_crtc_commit(struct drm_crtc *crtc)
3044{
7e7d76c3 3045 ironlake_crtc_enable(crtc);
79e53945
JB		 3046}
3047
3048void intel_encoder_prepare (struct drm_encoder *encoder)
3049{
3050 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3051 /* lvds has its own version of prepare see intel_lvds_prepare */
3052 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3053}
3054
3055void intel_encoder_commit (struct drm_encoder *encoder)
3056{
3057 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3058 /* lvds has its own version of commit see intel_lvds_commit */
3059 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3060}
3061
ea5b213a
CW		 3062void intel_encoder_destroy(struct drm_encoder *encoder)
3063{
4ef69c7a 3064 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3065
ea5b213a
CW		 3066 drm_encoder_cleanup(encoder);
3067 kfree(intel_encoder);
3068}
3069
79e53945
JB		 3070static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3071 struct drm_display_mode *mode,
3072 struct drm_display_mode *adjusted_mode)
3073{
2c07245f 3074 struct drm_device *dev = crtc->dev;
89749350 3075
bad720ff 3076 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3077 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3078 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3079 return false;
2c07245f 3080 }
89749350
CW		 3081
3082 /* XXX some encoders set the crtcinfo, others don't.
3083 * Obviously we need some form of conflict resolution here...
3084 */
3085 if (adjusted_mode->crtc_htotal == 0)
3086 drm_mode_set_crtcinfo(adjusted_mode, 0);
3087
79e53945
JB		 3088 return true;
3089}
3090
e70236a8
JB		 3091static int i945_get_display_clock_speed(struct drm_device *dev)
3092{
3093 return 400000;
3094}
79e53945 3095
e70236a8 3096static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3097{
e70236a8
JB		 3098 return 333000;
3099}
79e53945 3100
e70236a8
JB		 3101static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3102{
3103 return 200000;
3104}
79e53945 3105
e70236a8
JB		 3106static int i915gm_get_display_clock_speed(struct drm_device *dev)
3107{
3108 u16 gcfgc = 0;
79e53945 3109
e70236a8
JB		 3110 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3111
3112 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3113 return 133000;
3114 else {
3115 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3116 case GC_DISPLAY_CLOCK_333_MHZ:
3117 return 333000;
3118 default:
3119 case GC_DISPLAY_CLOCK_190_200_MHZ:
3120 return 190000;
79e53945 3121 }
e70236a8
JB		 3122 }
3123}
3124
3125static int i865_get_display_clock_speed(struct drm_device *dev)
3126{
3127 return 266000;
3128}
3129
3130static int i855_get_display_clock_speed(struct drm_device *dev)
3131{
3132 u16 hpllcc = 0;
3133 /* Assume that the hardware is in the high speed state. This
3134 * should be the default.
3135 */
3136 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3137 case GC_CLOCK_133_200:
3138 case GC_CLOCK_100_200:
3139 return 200000;
3140 case GC_CLOCK_166_250:
3141 return 250000;
3142 case GC_CLOCK_100_133:
79e53945 3143 return 133000;
e70236a8 3144 }
79e53945 3145
e70236a8
JB		 3146 /* Shouldn't happen */
3147 return 0;
3148}
79e53945 3149
e70236a8
JB		 3150static int i830_get_display_clock_speed(struct drm_device *dev)
3151{
3152 return 133000;
79e53945
JB		 3153}
3154
2c07245f
ZW		 3155struct fdi_m_n {
3156 u32 tu;
3157 u32 gmch_m;
3158 u32 gmch_n;
3159 u32 link_m;
3160 u32 link_n;
3161};
3162
3163static void
3164fdi_reduce_ratio(u32 *num, u32 *den)
3165{
3166 while (*num > 0xffffff || *den > 0xffffff) {
3167 *num >>= 1;
3168 *den >>= 1;
3169 }
3170}
3171
2c07245f 3172static void
f2b115e6
AJ		 3173ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3174 int link_clock, struct fdi_m_n *m_n)
2c07245f 3175{
2c07245f
ZW		 3176 m_n->tu = 64; /* default size */
3177
22ed1113
CW		 3178 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3179 m_n->gmch_m = bits_per_pixel * pixel_clock;
3180 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3181 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3182
22ed1113
CW		 3183 m_n->link_m = pixel_clock;
3184 m_n->link_n = link_clock;
2c07245f
ZW		 3185 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3186}
3187
3188
7662c8bd
SL		 3189struct intel_watermark_params {
3190 unsigned long fifo_size;
3191 unsigned long max_wm;
3192 unsigned long default_wm;
3193 unsigned long guard_size;
3194 unsigned long cacheline_size;
3195};
3196
f2b115e6 3197/* Pineview has different values for various configs */
d210246a 3198static const struct intel_watermark_params pineview_display_wm = {
f2b115e6
AJ		 3199 PINEVIEW_DISPLAY_FIFO,
3200 PINEVIEW_MAX_WM,
3201 PINEVIEW_DFT_WM,
3202 PINEVIEW_GUARD_WM,
3203 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3204};
d210246a 3205static const struct intel_watermark_params pineview_display_hplloff_wm = {
f2b115e6
AJ		 3206 PINEVIEW_DISPLAY_FIFO,
3207 PINEVIEW_MAX_WM,
3208 PINEVIEW_DFT_HPLLOFF_WM,
3209 PINEVIEW_GUARD_WM,
3210 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3211};
d210246a 3212static const struct intel_watermark_params pineview_cursor_wm = {
f2b115e6
AJ		 3213 PINEVIEW_CURSOR_FIFO,
3214 PINEVIEW_CURSOR_MAX_WM,
3215 PINEVIEW_CURSOR_DFT_WM,
3216 PINEVIEW_CURSOR_GUARD_WM,
3217 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 3218};
d210246a 3219static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
f2b115e6
AJ		 3220 PINEVIEW_CURSOR_FIFO,
3221 PINEVIEW_CURSOR_MAX_WM,
3222 PINEVIEW_CURSOR_DFT_WM,
3223 PINEVIEW_CURSOR_GUARD_WM,
3224 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3225};
d210246a 3226static const struct intel_watermark_params g4x_wm_info = {
0e442c60
JB		 3227 G4X_FIFO_SIZE,
3228 G4X_MAX_WM,
3229 G4X_MAX_WM,
3230 2,
3231 G4X_FIFO_LINE_SIZE,
3232};
d210246a 3233static const struct intel_watermark_params g4x_cursor_wm_info = {
4fe5e611
ZY		 3234 I965_CURSOR_FIFO,
3235 I965_CURSOR_MAX_WM,
3236 I965_CURSOR_DFT_WM,
3237 2,
3238 G4X_FIFO_LINE_SIZE,
3239};
d210246a 3240static const struct intel_watermark_params i965_cursor_wm_info = {
4fe5e611
ZY		 3241 I965_CURSOR_FIFO,
3242 I965_CURSOR_MAX_WM,
3243 I965_CURSOR_DFT_WM,
3244 2,
3245 I915_FIFO_LINE_SIZE,
3246};
d210246a 3247static const struct intel_watermark_params i945_wm_info = {
dff33cfc 3248 I945_FIFO_SIZE,
7662c8bd
SL		 3249 I915_MAX_WM,
3250 1,
dff33cfc
JB		 3251 2,
3252 I915_FIFO_LINE_SIZE
7662c8bd 3253};
d210246a 3254static const struct intel_watermark_params i915_wm_info = {
dff33cfc 3255 I915_FIFO_SIZE,
7662c8bd
SL		 3256 I915_MAX_WM,
3257 1,
dff33cfc 3258 2,
7662c8bd
SL		 3259 I915_FIFO_LINE_SIZE
3260};
d210246a 3261static const struct intel_watermark_params i855_wm_info = {
7662c8bd
SL		 3262 I855GM_FIFO_SIZE,
3263 I915_MAX_WM,
3264 1,
dff33cfc 3265 2,
7662c8bd
SL		 3266 I830_FIFO_LINE_SIZE
3267};
d210246a 3268static const struct intel_watermark_params i830_wm_info = {
7662c8bd
SL		 3269 I830_FIFO_SIZE,
3270 I915_MAX_WM,
3271 1,
dff33cfc 3272 2,
7662c8bd
SL		 3273 I830_FIFO_LINE_SIZE
3274};
3275
d210246a 3276static const struct intel_watermark_params ironlake_display_wm_info = {
7f8a8569
ZW		 3277 ILK_DISPLAY_FIFO,
3278 ILK_DISPLAY_MAXWM,
3279 ILK_DISPLAY_DFTWM,
3280 2,
3281 ILK_FIFO_LINE_SIZE
3282};
d210246a 3283static const struct intel_watermark_params ironlake_cursor_wm_info = {
c936f44d
ZY		 3284 ILK_CURSOR_FIFO,
3285 ILK_CURSOR_MAXWM,
3286 ILK_CURSOR_DFTWM,
3287 2,
3288 ILK_FIFO_LINE_SIZE
3289};
d210246a 3290static const struct intel_watermark_params ironlake_display_srwm_info = {
7f8a8569
ZW		 3291 ILK_DISPLAY_SR_FIFO,
3292 ILK_DISPLAY_MAX_SRWM,
3293 ILK_DISPLAY_DFT_SRWM,
3294 2,
3295 ILK_FIFO_LINE_SIZE
3296};
d210246a 3297static const struct intel_watermark_params ironlake_cursor_srwm_info = {
7f8a8569
ZW		 3298 ILK_CURSOR_SR_FIFO,
3299 ILK_CURSOR_MAX_SRWM,
3300 ILK_CURSOR_DFT_SRWM,
3301 2,
3302 ILK_FIFO_LINE_SIZE
3303};
3304
d210246a 3305static const struct intel_watermark_params sandybridge_display_wm_info = {
1398261a
YL		 3306 SNB_DISPLAY_FIFO,
3307 SNB_DISPLAY_MAXWM,
3308 SNB_DISPLAY_DFTWM,
3309 2,
3310 SNB_FIFO_LINE_SIZE
3311};
d210246a 3312static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1398261a
YL		 3313 SNB_CURSOR_FIFO,
3314 SNB_CURSOR_MAXWM,
3315 SNB_CURSOR_DFTWM,
3316 2,
3317 SNB_FIFO_LINE_SIZE
3318};
d210246a 3319static const struct intel_watermark_params sandybridge_display_srwm_info = {
1398261a
YL		 3320 SNB_DISPLAY_SR_FIFO,
3321 SNB_DISPLAY_MAX_SRWM,
3322 SNB_DISPLAY_DFT_SRWM,
3323 2,
3324 SNB_FIFO_LINE_SIZE
3325};
d210246a 3326static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1398261a
YL		 3327 SNB_CURSOR_SR_FIFO,
3328 SNB_CURSOR_MAX_SRWM,
3329 SNB_CURSOR_DFT_SRWM,
3330 2,
3331 SNB_FIFO_LINE_SIZE
3332};
3333
3334
dff33cfc
JB		 3335/**
3336 * intel_calculate_wm - calculate watermark level
3337 * @clock_in_khz: pixel clock
3338 * @wm: chip FIFO params
3339 * @pixel_size: display pixel size
3340 * @latency_ns: memory latency for the platform
3341 *
3342 * Calculate the watermark level (the level at which the display plane will
3343 * start fetching from memory again). Each chip has a different display
3344 * FIFO size and allocation, so the caller needs to figure that out and pass
3345 * in the correct intel_watermark_params structure.
3346 *
3347 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3348 * on the pixel size. When it reaches the watermark level, it'll start
3349 * fetching FIFO line sized based chunks from memory until the FIFO fills
3350 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3351 * will occur, and a display engine hang could result.
3352 */
7662c8bd 3353static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
d210246a
CW		 3354 const struct intel_watermark_params *wm,
3355 int fifo_size,
7662c8bd
SL		 3356 int pixel_size,
3357 unsigned long latency_ns)
3358{
390c4dd4 3359 long entries_required, wm_size;
dff33cfc 3360
d660467c
JB		 3361 /*
3362 * Note: we need to make sure we don't overflow for various clock &
3363 * latency values.
3364 * clocks go from a few thousand to several hundred thousand.
3365 * latency is usually a few thousand
3366 */
3367 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3368 1000;
8de9b311 3369 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 3370
bbb0aef5 3371 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
dff33cfc 3372
d210246a 3373 wm_size = fifo_size - (entries_required + wm->guard_size);
dff33cfc 3374
bbb0aef5 3375 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
7662c8bd 3376
390c4dd4
JB		 3377 /* Don't promote wm_size to unsigned... */
3378 if (wm_size > (long)wm->max_wm)
7662c8bd 3379 wm_size = wm->max_wm;
c3add4b6 3380 if (wm_size <= 0)
7662c8bd
SL		 3381 wm_size = wm->default_wm;
3382 return wm_size;
3383}
3384
3385struct cxsr_latency {
3386 int is_desktop;
95534263 3387 int is_ddr3;
7662c8bd
SL		 3388 unsigned long fsb_freq;
3389 unsigned long mem_freq;
3390 unsigned long display_sr;
3391 unsigned long display_hpll_disable;
3392 unsigned long cursor_sr;
3393 unsigned long cursor_hpll_disable;
3394};
3395
403c89ff 3396static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP		 3397 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3398 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3399 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3400 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3401 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3402
3403 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3404 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3405 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3406 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3407 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3408
3409 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3410 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3411 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3412 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3413 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3414
3415 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3416 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3417 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3418 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3419 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3420
3421 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3422 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3423 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3424 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3425 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3426
3427 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3428 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3429 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3430 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3431 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL		 3432};
3433
403c89ff
CW		 3434static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3435 int is_ddr3,
3436 int fsb,
3437 int mem)
7662c8bd 3438{
403c89ff 3439 const struct cxsr_latency *latency;
7662c8bd 3440 int i;
7662c8bd
SL		 3441
3442 if (fsb == 0 || mem == 0)
3443 return NULL;
3444
3445 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3446 latency = &cxsr_latency_table[i];
3447 if (is_desktop == latency->is_desktop &&
95534263 3448 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR		 3449 fsb == latency->fsb_freq && mem == latency->mem_freq)
3450 return latency;
7662c8bd 3451 }
decbbcda 3452
28c97730 3453 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR		 3454
3455 return NULL;
7662c8bd
SL		 3456}
3457
f2b115e6 3458static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL		 3459{
3460 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL		 3461
3462 /* deactivate cxsr */
3e33d94d 3463 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL		 3464}
3465
bcc24fb4
JB		 3466/*
3467 * Latency for FIFO fetches is dependent on several factors:
3468 * - memory configuration (speed, channels)
3469 * - chipset
3470 * - current MCH state
3471 * It can be fairly high in some situations, so here we assume a fairly
3472 * pessimal value. It's a tradeoff between extra memory fetches (if we
3473 * set this value too high, the FIFO will fetch frequently to stay full)
3474 * and power consumption (set it too low to save power and we might see
3475 * FIFO underruns and display "flicker").
3476 *
3477 * A value of 5us seems to be a good balance; safe for very low end
3478 * platforms but not overly aggressive on lower latency configs.
3479 */
69e302a9 3480static const int latency_ns = 5000;
7662c8bd 3481
e70236a8 3482static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB		 3483{
3484 struct drm_i915_private *dev_priv = dev->dev_private;
3485 uint32_t dsparb = I915_READ(DSPARB);
3486 int size;
3487
8de9b311
CW		 3488 size = dsparb & 0x7f;
3489 if (plane)
3490 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 3491
28c97730 3492 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3493 plane ? "B" : "A", size);
dff33cfc
JB		 3494
3495 return size;
3496}
7662c8bd 3497
e70236a8
JB		 3498static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3499{
3500 struct drm_i915_private *dev_priv = dev->dev_private;
3501 uint32_t dsparb = I915_READ(DSPARB);
3502 int size;
3503
8de9b311
CW		 3504 size = dsparb & 0x1ff;
3505 if (plane)
3506 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 3507 size >>= 1; /* Convert to cachelines */
dff33cfc 3508
28c97730 3509 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3510 plane ? "B" : "A", size);
dff33cfc
JB		 3511
3512 return size;
3513}
7662c8bd 3514
e70236a8
JB		 3515static int i845_get_fifo_size(struct drm_device *dev, int plane)
3516{
3517 struct drm_i915_private *dev_priv = dev->dev_private;
3518 uint32_t dsparb = I915_READ(DSPARB);
3519 int size;
3520
3521 size = dsparb & 0x7f;
3522 size >>= 2; /* Convert to cachelines */
3523
28c97730 3524 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW		 3525 plane ? "B" : "A",
3526 size);
e70236a8
JB		 3527
3528 return size;
3529}
3530
3531static int i830_get_fifo_size(struct drm_device *dev, int plane)
3532{
3533 struct drm_i915_private *dev_priv = dev->dev_private;
3534 uint32_t dsparb = I915_READ(DSPARB);
3535 int size;
3536
3537 size = dsparb & 0x7f;
3538 size >>= 1; /* Convert to cachelines */
3539
28c97730 3540 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3541 plane ? "B" : "A", size);
e70236a8
JB		 3542
3543 return size;
3544}
3545
d210246a
CW		 3546static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3547{
3548 struct drm_crtc *crtc, *enabled = NULL;
3549
3550 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3551 if (crtc->enabled && crtc->fb) {
3552 if (enabled)
3553 return NULL;
3554 enabled = crtc;
3555 }
3556 }
3557
3558 return enabled;
3559}
3560
3561static void pineview_update_wm(struct drm_device *dev)
d4294342
ZY		 3562{
3563 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3564 struct drm_crtc *crtc;
403c89ff 3565 const struct cxsr_latency *latency;
d4294342
ZY		 3566 u32 reg;
3567 unsigned long wm;
d4294342 3568
403c89ff 3569 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 3570 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY		 3571 if (!latency) {
3572 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3573 pineview_disable_cxsr(dev);
3574 return;
3575 }
3576
d210246a
CW		 3577 crtc = single_enabled_crtc(dev);
3578 if (crtc) {
3579 int clock = crtc->mode.clock;
3580 int pixel_size = crtc->fb->bits_per_pixel / 8;
d4294342
ZY		 3581
3582 /* Display SR */
d210246a
CW		 3583 wm = intel_calculate_wm(clock, &pineview_display_wm,
3584 pineview_display_wm.fifo_size,
d4294342
ZY		 3585 pixel_size, latency->display_sr);
3586 reg = I915_READ(DSPFW1);
3587 reg &= ~DSPFW_SR_MASK;
3588 reg |= wm << DSPFW_SR_SHIFT;
3589 I915_WRITE(DSPFW1, reg);
3590 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3591
3592 /* cursor SR */
d210246a
CW		 3593 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3594 pineview_display_wm.fifo_size,
d4294342
ZY		 3595 pixel_size, latency->cursor_sr);
3596 reg = I915_READ(DSPFW3);
3597 reg &= ~DSPFW_CURSOR_SR_MASK;
3598 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3599 I915_WRITE(DSPFW3, reg);
3600
3601 /* Display HPLL off SR */
d210246a
CW		 3602 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3603 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3604 pixel_size, latency->display_hpll_disable);
3605 reg = I915_READ(DSPFW3);
3606 reg &= ~DSPFW_HPLL_SR_MASK;
3607 reg |= wm & DSPFW_HPLL_SR_MASK;
3608 I915_WRITE(DSPFW3, reg);
3609
3610 /* cursor HPLL off SR */
d210246a
CW		 3611 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3612 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3613 pixel_size, latency->cursor_hpll_disable);
3614 reg = I915_READ(DSPFW3);
3615 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3616 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3617 I915_WRITE(DSPFW3, reg);
3618 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3619
3620 /* activate cxsr */
3e33d94d
CW		 3621 I915_WRITE(DSPFW3,
3622 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY		 3623 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3624 } else {
3625 pineview_disable_cxsr(dev);
3626 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3627 }
3628}
3629
417ae147
CW		 3630static bool g4x_compute_wm0(struct drm_device *dev,
3631 int plane,
3632 const struct intel_watermark_params *display,
3633 int display_latency_ns,
3634 const struct intel_watermark_params *cursor,
3635 int cursor_latency_ns,
3636 int *plane_wm,
3637 int *cursor_wm)
3638{
3639 struct drm_crtc *crtc;
3640 int htotal, hdisplay, clock, pixel_size;
3641 int line_time_us, line_count;
3642 int entries, tlb_miss;
3643
3644 crtc = intel_get_crtc_for_plane(dev, plane);
5c72d064
CW		 3645 if (crtc->fb == NULL || !crtc->enabled) {
3646 *cursor_wm = cursor->guard_size;
3647 *plane_wm = display->guard_size;
417ae147 3648 return false;
5c72d064 3649 }
417ae147
CW		 3650
3651 htotal = crtc->mode.htotal;
3652 hdisplay = crtc->mode.hdisplay;
3653 clock = crtc->mode.clock;
3654 pixel_size = crtc->fb->bits_per_pixel / 8;
3655
3656 /* Use the small buffer method to calculate plane watermark */
3657 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3658 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3659 if (tlb_miss > 0)
3660 entries += tlb_miss;
3661 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3662 *plane_wm = entries + display->guard_size;
3663 if (*plane_wm > (int)display->max_wm)
3664 *plane_wm = display->max_wm;
3665
3666 /* Use the large buffer method to calculate cursor watermark */
3667 line_time_us = ((htotal * 1000) / clock);
3668 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3669 entries = line_count * 64 * pixel_size;
3670 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3671 if (tlb_miss > 0)
3672 entries += tlb_miss;
3673 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3674 *cursor_wm = entries + cursor->guard_size;
3675 if (*cursor_wm > (int)cursor->max_wm)
3676 *cursor_wm = (int)cursor->max_wm;
3677
3678 return true;
3679}
3680
3681/*
3682 * Check the wm result.
3683 *
3684 * If any calculated watermark values is larger than the maximum value that
3685 * can be programmed into the associated watermark register, that watermark
3686 * must be disabled.
3687 */
3688static bool g4x_check_srwm(struct drm_device *dev,
3689 int display_wm, int cursor_wm,
3690 const struct intel_watermark_params *display,
3691 const struct intel_watermark_params *cursor)
652c393a 3692{
417ae147
CW		 3693 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3694 display_wm, cursor_wm);
652c393a 3695
417ae147 3696 if (display_wm > display->max_wm) {
bbb0aef5 3697 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 3698 display_wm, display->max_wm);
3699 return false;
3700 }
0e442c60 3701
417ae147 3702 if (cursor_wm > cursor->max_wm) {
bbb0aef5 3703 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 3704 cursor_wm, cursor->max_wm);
3705 return false;
3706 }
0e442c60 3707
417ae147
CW		 3708 if (!(display_wm || cursor_wm)) {
3709 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3710 return false;
3711 }
0e442c60 3712
417ae147
CW		 3713 return true;
3714}
0e442c60 3715
417ae147 3716static bool g4x_compute_srwm(struct drm_device *dev,
d210246a
CW		 3717 int plane,
3718 int latency_ns,
417ae147
CW		 3719 const struct intel_watermark_params *display,
3720 const struct intel_watermark_params *cursor,
3721 int *display_wm, int *cursor_wm)
3722{
d210246a
CW		 3723 struct drm_crtc *crtc;
3724 int hdisplay, htotal, pixel_size, clock;
417ae147
CW		 3725 unsigned long line_time_us;
3726 int line_count, line_size;
3727 int small, large;
3728 int entries;
0e442c60 3729
417ae147
CW		 3730 if (!latency_ns) {
3731 *display_wm = *cursor_wm = 0;
3732 return false;
3733 }
0e442c60 3734
d210246a
CW		 3735 crtc = intel_get_crtc_for_plane(dev, plane);
3736 hdisplay = crtc->mode.hdisplay;
3737 htotal = crtc->mode.htotal;
3738 clock = crtc->mode.clock;
3739 pixel_size = crtc->fb->bits_per_pixel / 8;
3740
417ae147
CW		 3741 line_time_us = (htotal * 1000) / clock;
3742 line_count = (latency_ns / line_time_us + 1000) / 1000;
3743 line_size = hdisplay * pixel_size;
0e442c60 3744
417ae147
CW		 3745 /* Use the minimum of the small and large buffer method for primary */
3746 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3747 large = line_count * line_size;
0e442c60 3748
417ae147
CW		 3749 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3750 *display_wm = entries + display->guard_size;
4fe5e611 3751
417ae147
CW		 3752 /* calculate the self-refresh watermark for display cursor */
3753 entries = line_count * pixel_size * 64;
3754 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3755 *cursor_wm = entries + cursor->guard_size;
4fe5e611 3756
417ae147
CW		 3757 return g4x_check_srwm(dev,
3758 *display_wm, *cursor_wm,
3759 display, cursor);
3760}
4fe5e611 3761
7ccb4a53 3762#define single_plane_enabled(mask) is_power_of_2(mask)
d210246a
CW		 3763
3764static void g4x_update_wm(struct drm_device *dev)
417ae147
CW		 3765{
3766 static const int sr_latency_ns = 12000;
3767 struct drm_i915_private *dev_priv = dev->dev_private;
3768 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
d210246a
CW		 3769 int plane_sr, cursor_sr;
3770 unsigned int enabled = 0;
417ae147
CW		 3771
3772 if (g4x_compute_wm0(dev, 0,
3773 &g4x_wm_info, latency_ns,
3774 &g4x_cursor_wm_info, latency_ns,
3775 &planea_wm, &cursora_wm))
d210246a 3776 enabled |= 1;
417ae147
CW		 3777
3778 if (g4x_compute_wm0(dev, 1,
3779 &g4x_wm_info, latency_ns,
3780 &g4x_cursor_wm_info, latency_ns,
3781 &planeb_wm, &cursorb_wm))
d210246a 3782 enabled |= 2;
417ae147
CW		 3783
3784 plane_sr = cursor_sr = 0;
d210246a
CW		 3785 if (single_plane_enabled(enabled) &&
3786 g4x_compute_srwm(dev, ffs(enabled) - 1,
3787 sr_latency_ns,
417ae147
CW		 3788 &g4x_wm_info,
3789 &g4x_cursor_wm_info,
3790 &plane_sr, &cursor_sr))
0e442c60 3791 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
417ae147
CW		 3792 else
3793 I915_WRITE(FW_BLC_SELF,
3794 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
0e442c60 3795
308977ac
CW		 3796 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3797 planea_wm, cursora_wm,
3798 planeb_wm, cursorb_wm,
3799 plane_sr, cursor_sr);
0e442c60 3800
417ae147
CW		 3801 I915_WRITE(DSPFW1,
3802 (plane_sr << DSPFW_SR_SHIFT) |
0e442c60 3803 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
417ae147
CW		 3804 (planeb_wm << DSPFW_PLANEB_SHIFT) |
3805 planea_wm);
3806 I915_WRITE(DSPFW2,
3807 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
0e442c60
JB		 3808 (cursora_wm << DSPFW_CURSORA_SHIFT));
3809 /* HPLL off in SR has some issues on G4x... disable it */
417ae147
CW		 3810 I915_WRITE(DSPFW3,
3811 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
0e442c60 3812 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB		 3813}
3814
d210246a 3815static void i965_update_wm(struct drm_device *dev)
7662c8bd
SL		 3816{
3817 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 3818 struct drm_crtc *crtc;
3819 int srwm = 1;
4fe5e611 3820 int cursor_sr = 16;
1dc7546d
JB		 3821
3822 /* Calc sr entries for one plane configs */
d210246a
CW		 3823 crtc = single_enabled_crtc(dev);
3824 if (crtc) {
1dc7546d 3825 /* self-refresh has much higher latency */
69e302a9 3826 static const int sr_latency_ns = 12000;
d210246a
CW		 3827 int clock = crtc->mode.clock;
3828 int htotal = crtc->mode.htotal;
3829 int hdisplay = crtc->mode.hdisplay;
3830 int pixel_size = crtc->fb->bits_per_pixel / 8;
3831 unsigned long line_time_us;
3832 int entries;
1dc7546d 3833
d210246a 3834 line_time_us = ((htotal * 1000) / clock);
1dc7546d
JB		 3835
3836 /* Use ns/us then divide to preserve precision */
d210246a
CW		 3837 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3838 pixel_size * hdisplay;
3839 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
d210246a 3840 srwm = I965_FIFO_SIZE - entries;
1dc7546d
JB		 3841 if (srwm < 0)
3842 srwm = 1;
1b07e04e 3843 srwm &= 0x1ff;
308977ac
CW		 3844 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3845 entries, srwm);
4fe5e611 3846
d210246a 3847 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 3848 pixel_size * 64;
d210246a 3849 entries = DIV_ROUND_UP(entries,
8de9b311 3850 i965_cursor_wm_info.cacheline_size);
4fe5e611 3851 cursor_sr = i965_cursor_wm_info.fifo_size -
d210246a 3852 (entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY		 3853
3854 if (cursor_sr > i965_cursor_wm_info.max_wm)
3855 cursor_sr = i965_cursor_wm_info.max_wm;
3856
3857 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3858 "cursor %d\n", srwm, cursor_sr);
3859
a6c45cf0 3860 if (IS_CRESTLINE(dev))
adcdbc66 3861 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ		 3862 } else {
3863 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 3864 if (IS_CRESTLINE(dev))
adcdbc66
JB		 3865 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3866 & ~FW_BLC_SELF_EN);
1dc7546d 3867 }
7662c8bd 3868
1dc7546d
JB		 3869 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3870 srwm);
7662c8bd
SL		 3871
3872 /* 965 has limitations... */
417ae147
CW		 3873 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
3874 (8 << 16) | (8 << 8) | (8 << 0));
7662c8bd 3875 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY		 3876 /* update cursor SR watermark */
3877 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL		 3878}
3879
d210246a 3880static void i9xx_update_wm(struct drm_device *dev)
7662c8bd
SL		 3881{
3882 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3883 const struct intel_watermark_params *wm_info;
dff33cfc
JB		 3884 uint32_t fwater_lo;
3885 uint32_t fwater_hi;
d210246a
CW		 3886 int cwm, srwm = 1;
3887 int fifo_size;
dff33cfc 3888 int planea_wm, planeb_wm;
d210246a 3889 struct drm_crtc *crtc, *enabled = NULL;
7662c8bd 3890
72557b4f 3891 if (IS_I945GM(dev))
d210246a 3892 wm_info = &i945_wm_info;
a6c45cf0 3893 else if (!IS_GEN2(dev))
d210246a 3894 wm_info = &i915_wm_info;
7662c8bd 3895 else
d210246a
CW		 3896 wm_info = &i855_wm_info;
3897
3898 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3899 crtc = intel_get_crtc_for_plane(dev, 0);
3900 if (crtc->enabled && crtc->fb) {
3901 planea_wm = intel_calculate_wm(crtc->mode.clock,
3902 wm_info, fifo_size,
3903 crtc->fb->bits_per_pixel / 8,
3904 latency_ns);
3905 enabled = crtc;
3906 } else
3907 planea_wm = fifo_size - wm_info->guard_size;
3908
3909 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3910 crtc = intel_get_crtc_for_plane(dev, 1);
3911 if (crtc->enabled && crtc->fb) {
3912 planeb_wm = intel_calculate_wm(crtc->mode.clock,
3913 wm_info, fifo_size,
3914 crtc->fb->bits_per_pixel / 8,
3915 latency_ns);
3916 if (enabled == NULL)
3917 enabled = crtc;
3918 else
3919 enabled = NULL;
3920 } else
3921 planeb_wm = fifo_size - wm_info->guard_size;
7662c8bd 3922
28c97730 3923 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL		 3924
3925 /*
3926 * Overlay gets an aggressive default since video jitter is bad.
3927 */
3928 cwm = 2;
3929
18b2190c
AL		 3930 /* Play safe and disable self-refresh before adjusting watermarks. */
3931 if (IS_I945G(dev) || IS_I945GM(dev))
3932 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
3933 else if (IS_I915GM(dev))
3934 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3935
dff33cfc 3936 /* Calc sr entries for one plane configs */
d210246a 3937 if (HAS_FW_BLC(dev) && enabled) {
dff33cfc 3938 /* self-refresh has much higher latency */
69e302a9 3939 static const int sr_latency_ns = 6000;
d210246a
CW		 3940 int clock = enabled->mode.clock;
3941 int htotal = enabled->mode.htotal;
3942 int hdisplay = enabled->mode.hdisplay;
3943 int pixel_size = enabled->fb->bits_per_pixel / 8;
3944 unsigned long line_time_us;
3945 int entries;
dff33cfc 3946
d210246a 3947 line_time_us = (htotal * 1000) / clock;
dff33cfc
JB		 3948
3949 /* Use ns/us then divide to preserve precision */
d210246a
CW		 3950 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3951 pixel_size * hdisplay;
3952 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
3953 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
3954 srwm = wm_info->fifo_size - entries;
dff33cfc
JB		 3955 if (srwm < 0)
3956 srwm = 1;
ee980b80
LP		 3957
3958 if (IS_I945G(dev) || IS_I945GM(dev))
18b2190c
AL		 3959 I915_WRITE(FW_BLC_SELF,
3960 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3961 else if (IS_I915GM(dev))
ee980b80 3962 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
7662c8bd
SL		 3963 }
3964
28c97730 3965 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 3966 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 3967
dff33cfc
JB		 3968 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3969 fwater_hi = (cwm & 0x1f);
3970
3971 /* Set request length to 8 cachelines per fetch */
3972 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3973 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL		 3974
3975 I915_WRITE(FW_BLC, fwater_lo);
3976 I915_WRITE(FW_BLC2, fwater_hi);
18b2190c 3977
d210246a
CW		 3978 if (HAS_FW_BLC(dev)) {
3979 if (enabled) {
3980 if (IS_I945G(dev) || IS_I945GM(dev))
3981 I915_WRITE(FW_BLC_SELF,
3982 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
3983 else if (IS_I915GM(dev))
3984 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3985 DRM_DEBUG_KMS("memory self refresh enabled\n");
3986 } else
3987 DRM_DEBUG_KMS("memory self refresh disabled\n");
3988 }
7662c8bd
SL		 3989}
3990
d210246a 3991static void i830_update_wm(struct drm_device *dev)
7662c8bd
SL		 3992{
3993 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 3994 struct drm_crtc *crtc;
3995 uint32_t fwater_lo;
dff33cfc 3996 int planea_wm;
7662c8bd 3997
d210246a
CW		 3998 crtc = single_enabled_crtc(dev);
3999 if (crtc == NULL)
4000 return;
7662c8bd 4001
d210246a
CW		 4002 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4003 dev_priv->display.get_fifo_size(dev, 0),
4004 crtc->fb->bits_per_pixel / 8,
4005 latency_ns);
4006 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
f3601326
JB		 4007 fwater_lo |= (3<<8) | planea_wm;
4008
28c97730 4009 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL		 4010
4011 I915_WRITE(FW_BLC, fwater_lo);
4012}
4013
7f8a8569 4014#define ILK_LP0_PLANE_LATENCY 700
c936f44d 4015#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 4016
1398261a
YL		 4017/*
4018 * Check the wm result.
4019 *
4020 * If any calculated watermark values is larger than the maximum value that
4021 * can be programmed into the associated watermark register, that watermark
4022 * must be disabled.
1398261a 4023 */
b79d4990
JB		 4024static bool ironlake_check_srwm(struct drm_device *dev, int level,
4025 int fbc_wm, int display_wm, int cursor_wm,
4026 const struct intel_watermark_params *display,
4027 const struct intel_watermark_params *cursor)
1398261a
YL		 4028{
4029 struct drm_i915_private *dev_priv = dev->dev_private;
4030
4031 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4032 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4033
4034 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4035 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4036 fbc_wm, SNB_FBC_MAX_SRWM, level);
1398261a
YL		 4037
4038 /* fbc has it's own way to disable FBC WM */
4039 I915_WRITE(DISP_ARB_CTL,
4040 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4041 return false;
4042 }
4043
b79d4990 4044 if (display_wm > display->max_wm) {
1398261a 4045 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4046 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1398261a
YL		 4047 return false;
4048 }
4049
b79d4990 4050 if (cursor_wm > cursor->max_wm) {
1398261a 4051 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4052 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1398261a
YL		 4053 return false;
4054 }
4055
4056 if (!(fbc_wm || display_wm || cursor_wm)) {
4057 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4058 return false;
4059 }
4060
4061 return true;
4062}
4063
4064/*
4065 * Compute watermark values of WM[1-3],
4066 */
d210246a
CW		 4067static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4068 int latency_ns,
b79d4990
JB		 4069 const struct intel_watermark_params *display,
4070 const struct intel_watermark_params *cursor,
4071 int *fbc_wm, int *display_wm, int *cursor_wm)
1398261a 4072{
d210246a 4073 struct drm_crtc *crtc;
1398261a 4074 unsigned long line_time_us;
d210246a 4075 int hdisplay, htotal, pixel_size, clock;
b79d4990 4076 int line_count, line_size;
1398261a
YL		 4077 int small, large;
4078 int entries;
1398261a
YL		 4079
4080 if (!latency_ns) {
4081 *fbc_wm = *display_wm = *cursor_wm = 0;
4082 return false;
4083 }
4084
d210246a
CW		 4085 crtc = intel_get_crtc_for_plane(dev, plane);
4086 hdisplay = crtc->mode.hdisplay;
4087 htotal = crtc->mode.htotal;
4088 clock = crtc->mode.clock;
4089 pixel_size = crtc->fb->bits_per_pixel / 8;
4090
1398261a
YL		 4091 line_time_us = (htotal * 1000) / clock;
4092 line_count = (latency_ns / line_time_us + 1000) / 1000;
4093 line_size = hdisplay * pixel_size;
4094
4095 /* Use the minimum of the small and large buffer method for primary */
4096 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4097 large = line_count * line_size;
4098
b79d4990
JB		 4099 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4100 *display_wm = entries + display->guard_size;
1398261a
YL		 4101
4102 /*
b79d4990 4103 * Spec says:
1398261a
YL		 4104 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4105 */
4106 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4107
4108 /* calculate the self-refresh watermark for display cursor */
4109 entries = line_count * pixel_size * 64;
b79d4990
JB		 4110 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4111 *cursor_wm = entries + cursor->guard_size;
1398261a 4112
b79d4990
JB		 4113 return ironlake_check_srwm(dev, level,
4114 *fbc_wm, *display_wm, *cursor_wm,
4115 display, cursor);
4116}
4117
d210246a 4118static void ironlake_update_wm(struct drm_device *dev)
b79d4990
JB		 4119{
4120 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4121 int fbc_wm, plane_wm, cursor_wm;
4122 unsigned int enabled;
b79d4990
JB		 4123
4124 enabled = 0;
9f405100
CW		 4125 if (g4x_compute_wm0(dev, 0,
4126 &ironlake_display_wm_info,
4127 ILK_LP0_PLANE_LATENCY,
4128 &ironlake_cursor_wm_info,
4129 ILK_LP0_CURSOR_LATENCY,
4130 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4131 I915_WRITE(WM0_PIPEA_ILK,
4132 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4133 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4134 " plane %d, " "cursor: %d\n",
4135 plane_wm, cursor_wm);
d210246a 4136 enabled |= 1;
b79d4990
JB		 4137 }
4138
9f405100
CW		 4139 if (g4x_compute_wm0(dev, 1,
4140 &ironlake_display_wm_info,
4141 ILK_LP0_PLANE_LATENCY,
4142 &ironlake_cursor_wm_info,
4143 ILK_LP0_CURSOR_LATENCY,
4144 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4145 I915_WRITE(WM0_PIPEB_ILK,
4146 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4147 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4148 " plane %d, cursor: %d\n",
4149 plane_wm, cursor_wm);
d210246a 4150 enabled |= 2;
b79d4990
JB		 4151 }
4152
4153 /*
4154 * Calculate and update the self-refresh watermark only when one
4155 * display plane is used.
4156 */
4157 I915_WRITE(WM3_LP_ILK, 0);
4158 I915_WRITE(WM2_LP_ILK, 0);
4159 I915_WRITE(WM1_LP_ILK, 0);
4160
d210246a 4161 if (!single_plane_enabled(enabled))
b79d4990 4162 return;
d210246a 4163 enabled = ffs(enabled) - 1;
b79d4990
JB		 4164
4165 /* WM1 */
d210246a
CW		 4166 if (!ironlake_compute_srwm(dev, 1, enabled,
4167 ILK_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4168 &ironlake_display_srwm_info,
4169 &ironlake_cursor_srwm_info,
4170 &fbc_wm, &plane_wm, &cursor_wm))
4171 return;
4172
4173 I915_WRITE(WM1_LP_ILK,
4174 WM1_LP_SR_EN |
4175 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4176 (fbc_wm << WM1_LP_FBC_SHIFT) |
4177 (plane_wm << WM1_LP_SR_SHIFT) |
4178 cursor_wm);
4179
4180 /* WM2 */
d210246a
CW		 4181 if (!ironlake_compute_srwm(dev, 2, enabled,
4182 ILK_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4183 &ironlake_display_srwm_info,
4184 &ironlake_cursor_srwm_info,
4185 &fbc_wm, &plane_wm, &cursor_wm))
4186 return;
4187
4188 I915_WRITE(WM2_LP_ILK,
4189 WM2_LP_EN |
4190 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4191 (fbc_wm << WM1_LP_FBC_SHIFT) |
4192 (plane_wm << WM1_LP_SR_SHIFT) |
4193 cursor_wm);
4194
4195 /*
4196 * WM3 is unsupported on ILK, probably because we don't have latency
4197 * data for that power state
4198 */
1398261a
YL		 4199}
4200
d210246a 4201static void sandybridge_update_wm(struct drm_device *dev)
1398261a
YL		 4202{
4203 struct drm_i915_private *dev_priv = dev->dev_private;
a0fa62d3 4204 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
d210246a
CW		 4205 int fbc_wm, plane_wm, cursor_wm;
4206 unsigned int enabled;
1398261a
YL		 4207
4208 enabled = 0;
9f405100
CW		 4209 if (g4x_compute_wm0(dev, 0,
4210 &sandybridge_display_wm_info, latency,
4211 &sandybridge_cursor_wm_info, latency,
4212 &plane_wm, &cursor_wm)) {
1398261a
YL		 4213 I915_WRITE(WM0_PIPEA_ILK,
4214 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4215 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4216 " plane %d, " "cursor: %d\n",
4217 plane_wm, cursor_wm);
d210246a 4218 enabled |= 1;
1398261a
YL		 4219 }
4220
9f405100
CW		 4221 if (g4x_compute_wm0(dev, 1,
4222 &sandybridge_display_wm_info, latency,
4223 &sandybridge_cursor_wm_info, latency,
4224 &plane_wm, &cursor_wm)) {
1398261a
YL		 4225 I915_WRITE(WM0_PIPEB_ILK,
4226 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4227 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4228 " plane %d, cursor: %d\n",
4229 plane_wm, cursor_wm);
d210246a 4230 enabled |= 2;
1398261a
YL		 4231 }
4232
4233 /*
4234 * Calculate and update the self-refresh watermark only when one
4235 * display plane is used.
4236 *
4237 * SNB support 3 levels of watermark.
4238 *
4239 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4240 * and disabled in the descending order
4241 *
4242 */
4243 I915_WRITE(WM3_LP_ILK, 0);
4244 I915_WRITE(WM2_LP_ILK, 0);
4245 I915_WRITE(WM1_LP_ILK, 0);
4246
d210246a 4247 if (!single_plane_enabled(enabled))
1398261a 4248 return;
d210246a 4249 enabled = ffs(enabled) - 1;
1398261a
YL		 4250
4251 /* WM1 */
d210246a
CW		 4252 if (!ironlake_compute_srwm(dev, 1, enabled,
4253 SNB_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4254 &sandybridge_display_srwm_info,
4255 &sandybridge_cursor_srwm_info,
4256 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4257 return;
4258
4259 I915_WRITE(WM1_LP_ILK,
4260 WM1_LP_SR_EN |
4261 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4262 (fbc_wm << WM1_LP_FBC_SHIFT) |
4263 (plane_wm << WM1_LP_SR_SHIFT) |
4264 cursor_wm);
4265
4266 /* WM2 */
d210246a
CW		 4267 if (!ironlake_compute_srwm(dev, 2, enabled,
4268 SNB_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4269 &sandybridge_display_srwm_info,
4270 &sandybridge_cursor_srwm_info,
4271 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4272 return;
4273
4274 I915_WRITE(WM2_LP_ILK,
4275 WM2_LP_EN |
4276 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4277 (fbc_wm << WM1_LP_FBC_SHIFT) |
4278 (plane_wm << WM1_LP_SR_SHIFT) |
4279 cursor_wm);
4280
4281 /* WM3 */
d210246a
CW		 4282 if (!ironlake_compute_srwm(dev, 3, enabled,
4283 SNB_READ_WM3_LATENCY() * 500,
b79d4990
JB		 4284 &sandybridge_display_srwm_info,
4285 &sandybridge_cursor_srwm_info,
4286 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4287 return;
4288
4289 I915_WRITE(WM3_LP_ILK,
4290 WM3_LP_EN |
4291 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4292 (fbc_wm << WM1_LP_FBC_SHIFT) |
4293 (plane_wm << WM1_LP_SR_SHIFT) |
4294 cursor_wm);
4295}
4296
7662c8bd
SL		 4297/**
4298 * intel_update_watermarks - update FIFO watermark values based on current modes
4299 *
4300 * Calculate watermark values for the various WM regs based on current mode
4301 * and plane configuration.
4302 *
4303 * There are several cases to deal with here:
4304 * - normal (i.e. non-self-refresh)
4305 * - self-refresh (SR) mode
4306 * - lines are large relative to FIFO size (buffer can hold up to 2)
4307 * - lines are small relative to FIFO size (buffer can hold more than 2
4308 * lines), so need to account for TLB latency
4309 *
4310 * The normal calculation is:
4311 * watermark = dotclock * bytes per pixel * latency
4312 * where latency is platform & configuration dependent (we assume pessimal
4313 * values here).
4314 *
4315 * The SR calculation is:
4316 * watermark = (trunc(latency/line time)+1) * surface width *
4317 * bytes per pixel
4318 * where
4319 * line time = htotal / dotclock
fa143215 4320 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL		 4321 * and latency is assumed to be high, as above.
4322 *
4323 * The final value programmed to the register should always be rounded up,
4324 * and include an extra 2 entries to account for clock crossings.
4325 *
4326 * We don't use the sprite, so we can ignore that. And on Crestline we have
4327 * to set the non-SR watermarks to 8.
5eddb70b 4328 */
7662c8bd
SL		 4329static void intel_update_watermarks(struct drm_device *dev)
4330{
e70236a8 4331 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 4332
d210246a
CW		 4333 if (dev_priv->display.update_wm)
4334 dev_priv->display.update_wm(dev);
7662c8bd
SL		 4335}
4336
a7615030
CW		 4337static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4338{
435793df
KP		 4339 return dev_priv->lvds_use_ssc && i915_panel_use_ssc
4340 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4341}
4342
f564048e
EA		 4343static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4344 struct drm_display_mode *mode,
4345 struct drm_display_mode *adjusted_mode,
4346 int x, int y,
4347 struct drm_framebuffer *old_fb)
79e53945
JB		 4348{
4349 struct drm_device *dev = crtc->dev;
4350 struct drm_i915_private *dev_priv = dev->dev_private;
4351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4352 int pipe = intel_crtc->pipe;
80824003 4353 int plane = intel_crtc->plane;
c751ce4f 4354 int refclk, num_connectors = 0;
652c393a 4355 intel_clock_t clock, reduced_clock;
5eddb70b 4356 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
652c393a 4357 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
a4fc5ed6 4358 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 4359 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 4360 struct intel_encoder *encoder;
d4906093 4361 const intel_limit_t *limit;
5c3b82e2 4362 int ret;
fae14981 4363 u32 temp;
aa9b500d 4364 u32 lvds_sync = 0;
79e53945 4365
5eddb70b
CW		 4366 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4367 if (encoder->base.crtc != crtc)
79e53945
JB		 4368 continue;
4369
5eddb70b 4370 switch (encoder->type) {
79e53945
JB		 4371 case INTEL_OUTPUT_LVDS:
4372 is_lvds = true;
4373 break;
4374 case INTEL_OUTPUT_SDVO:
7d57382e 4375 case INTEL_OUTPUT_HDMI:
79e53945 4376 is_sdvo = true;
5eddb70b 4377 if (encoder->needs_tv_clock)
e2f0ba97 4378 is_tv = true;
79e53945
JB		 4379 break;
4380 case INTEL_OUTPUT_DVO:
4381 is_dvo = true;
4382 break;
4383 case INTEL_OUTPUT_TVOUT:
4384 is_tv = true;
4385 break;
4386 case INTEL_OUTPUT_ANALOG:
4387 is_crt = true;
4388 break;
a4fc5ed6
KP		 4389 case INTEL_OUTPUT_DISPLAYPORT:
4390 is_dp = true;
4391 break;
79e53945 4392 }
43565a06 4393
c751ce4f 4394 num_connectors++;
79e53945
JB		 4395 }
4396
a7615030 4397 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 4398 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 4399 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 4400 refclk / 1000);
a6c45cf0 4401 } else if (!IS_GEN2(dev)) {
79e53945
JB		 4402 refclk = 96000;
4403 } else {
4404 refclk = 48000;
4405 }
4406
d4906093
ML		 4407 /*
4408 * Returns a set of divisors for the desired target clock with the given
4409 * refclk, or FALSE. The returned values represent the clock equation:
4410 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4411 */
1b894b59 4412 limit = intel_limit(crtc, refclk);
d4906093 4413 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 4414 if (!ok) {
4415 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4416 return -EINVAL;
79e53945
JB		 4417 }
4418
cda4b7d3 4419 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4420 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4421
ddc9003c
ZY		 4422 if (is_lvds && dev_priv->lvds_downclock_avail) {
4423 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4424 dev_priv->lvds_downclock,
4425 refclk,
4426 &reduced_clock);
18f9ed12
ZY		 4427 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4428 /*
4429 * If the different P is found, it means that we can't
4430 * switch the display clock by using the FP0/FP1.
4431 * In such case we will disable the LVDS downclock
4432 * feature.
4433 */
4434 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 4435 "LVDS clock/downclock\n");
18f9ed12
ZY		 4436 has_reduced_clock = 0;
4437 }
652c393a 4438 }
7026d4ac
ZW		 4439 /* SDVO TV has fixed PLL values depend on its clock range,
4440 this mirrors vbios setting. */
4441 if (is_sdvo && is_tv) {
4442 if (adjusted_mode->clock >= 100000
5eddb70b 4443 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4444 clock.p1 = 2;
4445 clock.p2 = 10;
4446 clock.n = 3;
4447 clock.m1 = 16;
4448 clock.m2 = 8;
4449 } else if (adjusted_mode->clock >= 140500
5eddb70b 4450 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4451 clock.p1 = 1;
4452 clock.p2 = 10;
4453 clock.n = 6;
4454 clock.m1 = 12;
4455 clock.m2 = 8;
4456 }
4457 }
4458
f2b115e6 4459 if (IS_PINEVIEW(dev)) {
2177832f 4460 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 4461 if (has_reduced_clock)
4462 fp2 = (1 << reduced_clock.n) << 16 |
4463 reduced_clock.m1 << 8 | reduced_clock.m2;
4464 } else {
2177832f 4465 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 4466 if (has_reduced_clock)
4467 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4468 reduced_clock.m2;
4469 }
79e53945 4470
929c77fb 4471 dpll = DPLL_VGA_MODE_DIS;
2c07245f 4472
a6c45cf0 4473 if (!IS_GEN2(dev)) {
79e53945
JB		 4474 if (is_lvds)
4475 dpll |= DPLLB_MODE_LVDS;
4476 else
4477 dpll |= DPLLB_MODE_DAC_SERIAL;
4478 if (is_sdvo) {
6c9547ff
CW		 4479 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4480 if (pixel_multiplier > 1) {
4481 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4482 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
6c9547ff 4483 }
79e53945 4484 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4485 }
929c77fb 4486 if (is_dp)
a4fc5ed6 4487 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945
JB		 4488
4489 /* compute bitmask from p1 value */
f2b115e6
AJ		 4490 if (IS_PINEVIEW(dev))
4491 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
2c07245f 4492 else {
2177832f 4493 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
652c393a
JB		 4494 if (IS_G4X(dev) && has_reduced_clock)
4495 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2c07245f 4496 }
79e53945
JB		 4497 switch (clock.p2) {
4498 case 5:
4499 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4500 break;
4501 case 7:
4502 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4503 break;
4504 case 10:
4505 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4506 break;
4507 case 14:
4508 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4509 break;
4510 }
929c77fb 4511 if (INTEL_INFO(dev)->gen >= 4)
79e53945
JB		 4512 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4513 } else {
4514 if (is_lvds) {
4515 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4516 } else {
4517 if (clock.p1 == 2)
4518 dpll |= PLL_P1_DIVIDE_BY_TWO;
4519 else
4520 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4521 if (clock.p2 == 4)
4522 dpll |= PLL_P2_DIVIDE_BY_4;
4523 }
4524 }
4525
43565a06
KH		 4526 if (is_sdvo && is_tv)
4527 dpll |= PLL_REF_INPUT_TVCLKINBC;
4528 else if (is_tv)
79e53945 4529 /* XXX: just matching BIOS for now */
43565a06 4530 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4531 dpll |= 3;
a7615030 4532 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4533 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4534 else
4535 dpll |= PLL_REF_INPUT_DREFCLK;
4536
4537 /* setup pipeconf */
5eddb70b 4538 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4539
4540 /* Set up the display plane register */
4541 dspcntr = DISPPLANE_GAMMA_ENABLE;
4542
f2b115e6 4543 /* Ironlake's plane is forced to pipe, bit 24 is to
2c07245f 4544 enable color space conversion */
929c77fb
EA		 4545 if (pipe == 0)
4546 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4547 else
4548 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4549
a6c45cf0 4550 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4551 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4552 * core speed.
4553 *
4554 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4555 * pipe == 0 check?
4556 */
e70236a8
JB		 4557 if (mode->clock >
4558 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4559 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4560 else
5eddb70b 4561 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4562 }
4563
929c77fb 4564 dpll |= DPLL_VCO_ENABLE;
8d86dc6a 4565
28c97730 4566 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4567 drm_mode_debug_printmodeline(mode);
4568
fae14981
EA		 4569 I915_WRITE(FP0(pipe), fp);
4570 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 4571
fae14981 4572 POSTING_READ(DPLL(pipe));
c713bb08 4573 udelay(150);
8db9d77b 4574
79e53945
JB		 4575 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4576 * This is an exception to the general rule that mode_set doesn't turn
4577 * things on.
4578 */
4579 if (is_lvds) {
fae14981 4580 temp = I915_READ(LVDS);
5eddb70b 4581 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3 4582 if (pipe == 1) {
929c77fb 4583 temp |= LVDS_PIPEB_SELECT;
b3b095b3 4584 } else {
929c77fb 4585 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 4586 }
a3e17eb8 4587 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4588 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4589 /* Set the B0-B3 data pairs corresponding to whether we're going to
4590 * set the DPLLs for dual-channel mode or not.
4591 */
4592 if (clock.p2 == 7)
5eddb70b 4593 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4594 else
5eddb70b 4595 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4596
4597 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4598 * appropriately here, but we need to look more thoroughly into how
4599 * panels behave in the two modes.
4600 */
929c77fb
EA		 4601 /* set the dithering flag on LVDS as needed */
4602 if (INTEL_INFO(dev)->gen >= 4) {
434ed097 4603 if (dev_priv->lvds_dither)
5eddb70b 4604 temp |= LVDS_ENABLE_DITHER;
434ed097 4605 else
5eddb70b 4606 temp &= ~LVDS_ENABLE_DITHER;
898822ce 4607 }
aa9b500d
BF		 4608 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4609 lvds_sync |= LVDS_HSYNC_POLARITY;
4610 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4611 lvds_sync |= LVDS_VSYNC_POLARITY;
4612 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4613 != lvds_sync) {
4614 char flags[2] = "-+";
4615 DRM_INFO("Changing LVDS panel from "
4616 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4617 flags[!(temp & LVDS_HSYNC_POLARITY)],
4618 flags[!(temp & LVDS_VSYNC_POLARITY)],
4619 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4620 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4621 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4622 temp |= lvds_sync;
4623 }
fae14981 4624 I915_WRITE(LVDS, temp);
79e53945 4625 }
434ed097 4626
929c77fb 4627 if (is_dp) {
a4fc5ed6 4628 intel_dp_set_m_n(crtc, mode, adjusted_mode);
434ed097
JB		 4629 }
4630
fae14981 4631 I915_WRITE(DPLL(pipe), dpll);
5eddb70b 4632
c713bb08 4633 /* Wait for the clocks to stabilize. */
fae14981 4634 POSTING_READ(DPLL(pipe));
c713bb08 4635 udelay(150);
32f9d658 4636
c713bb08
EA		 4637 if (INTEL_INFO(dev)->gen >= 4) {
4638 temp = 0;
4639 if (is_sdvo) {
4640 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4641 if (temp > 1)
4642 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4643 else
4644 temp = 0;
32f9d658 4645 }
c713bb08
EA		 4646 I915_WRITE(DPLL_MD(pipe), temp);
4647 } else {
4648 /* The pixel multiplier can only be updated once the
4649 * DPLL is enabled and the clocks are stable.
4650 *
4651 * So write it again.
4652 */
fae14981 4653 I915_WRITE(DPLL(pipe), dpll);
79e53945 4654 }
79e53945 4655
5eddb70b 4656 intel_crtc->lowfreq_avail = false;
652c393a 4657 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 4658 I915_WRITE(FP1(pipe), fp2);
652c393a
JB		 4659 intel_crtc->lowfreq_avail = true;
4660 if (HAS_PIPE_CXSR(dev)) {
28c97730 4661 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 4662 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4663 }
4664 } else {
fae14981 4665 I915_WRITE(FP1(pipe), fp);
652c393a 4666 if (HAS_PIPE_CXSR(dev)) {
28c97730 4667 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4668 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4669 }
4670 }
4671
734b4157
KH		 4672 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4673 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4674 /* the chip adds 2 halflines automatically */
4675 adjusted_mode->crtc_vdisplay -= 1;
4676 adjusted_mode->crtc_vtotal -= 1;
4677 adjusted_mode->crtc_vblank_start -= 1;
4678 adjusted_mode->crtc_vblank_end -= 1;
4679 adjusted_mode->crtc_vsync_end -= 1;
4680 adjusted_mode->crtc_vsync_start -= 1;
4681 } else
4682 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4683
5eddb70b
CW		 4684 I915_WRITE(HTOTAL(pipe),
4685 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4686 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4687 I915_WRITE(HBLANK(pipe),
4688 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4689 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4690 I915_WRITE(HSYNC(pipe),
4691 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4692 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4693
4694 I915_WRITE(VTOTAL(pipe),
4695 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4696 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4697 I915_WRITE(VBLANK(pipe),
4698 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4699 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4700 I915_WRITE(VSYNC(pipe),
4701 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4702 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 4703
4704 /* pipesrc and dspsize control the size that is scaled from,
4705 * which should always be the user's requested size.
79e53945 4706 */
929c77fb
EA		 4707 I915_WRITE(DSPSIZE(plane),
4708 ((mode->vdisplay - 1) << 16) |
4709 (mode->hdisplay - 1));
4710 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 4711 I915_WRITE(PIPESRC(pipe),
4712 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4713
f564048e
EA		 4714 I915_WRITE(PIPECONF(pipe), pipeconf);
4715 POSTING_READ(PIPECONF(pipe));
929c77fb 4716 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4717
4718 intel_wait_for_vblank(dev, pipe);
4719
f564048e
EA		 4720 I915_WRITE(DSPCNTR(plane), dspcntr);
4721 POSTING_READ(DSPCNTR(plane));
efc2924e 4722 intel_enable_plane(dev_priv, plane, pipe);
f564048e
EA		 4723
4724 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4725
4726 intel_update_watermarks(dev);
4727
f564048e
EA		 4728 return ret;
4729}
4730
4731static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4732 struct drm_display_mode *mode,
4733 struct drm_display_mode *adjusted_mode,
4734 int x, int y,
4735 struct drm_framebuffer *old_fb)
79e53945
JB		 4736{
4737 struct drm_device *dev = crtc->dev;
4738 struct drm_i915_private *dev_priv = dev->dev_private;
4739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4740 int pipe = intel_crtc->pipe;
80824003 4741 int plane = intel_crtc->plane;
c751ce4f 4742 int refclk, num_connectors = 0;
652c393a 4743 intel_clock_t clock, reduced_clock;
5eddb70b 4744 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4745 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4746 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
8e647a27 4747 struct intel_encoder *has_edp_encoder = NULL;
79e53945 4748 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 4749 struct intel_encoder *encoder;
d4906093 4750 const intel_limit_t *limit;
5c3b82e2 4751 int ret;
2c07245f 4752 struct fdi_m_n m_n = {0};
fae14981 4753 u32 temp;
aa9b500d 4754 u32 lvds_sync = 0;
8febb297 4755 int target_clock, pixel_multiplier, lane, link_bw, bpp, factor;
79e53945 4756
5eddb70b
CW		 4757 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4758 if (encoder->base.crtc != crtc)
79e53945
JB		 4759 continue;
4760
5eddb70b 4761 switch (encoder->type) {
79e53945
JB		 4762 case INTEL_OUTPUT_LVDS:
4763 is_lvds = true;
4764 break;
4765 case INTEL_OUTPUT_SDVO:
7d57382e 4766 case INTEL_OUTPUT_HDMI:
79e53945 4767 is_sdvo = true;
5eddb70b 4768 if (encoder->needs_tv_clock)
e2f0ba97 4769 is_tv = true;
79e53945 4770 break;
79e53945
JB		 4771 case INTEL_OUTPUT_TVOUT:
4772 is_tv = true;
4773 break;
4774 case INTEL_OUTPUT_ANALOG:
4775 is_crt = true;
4776 break;
a4fc5ed6
KP		 4777 case INTEL_OUTPUT_DISPLAYPORT:
4778 is_dp = true;
4779 break;
32f9d658 4780 case INTEL_OUTPUT_EDP:
5eddb70b 4781 has_edp_encoder = encoder;
32f9d658 4782 break;
79e53945 4783 }
43565a06 4784
c751ce4f 4785 num_connectors++;
79e53945
JB		 4786 }
4787
a7615030 4788 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 4789 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 4790 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 4791 refclk / 1000);
a07d6787 4792 } else {
79e53945 4793 refclk = 96000;
8febb297
EA		 4794 if (!has_edp_encoder ||
4795 intel_encoder_is_pch_edp(&has_edp_encoder->base))
2c07245f 4796 refclk = 120000; /* 120Mhz refclk */
79e53945
JB		 4797 }
4798
d4906093
ML		 4799 /*
4800 * Returns a set of divisors for the desired target clock with the given
4801 * refclk, or FALSE. The returned values represent the clock equation:
4802 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4803 */
1b894b59 4804 limit = intel_limit(crtc, refclk);
d4906093 4805 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 4806 if (!ok) {
4807 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4808 return -EINVAL;
79e53945
JB		 4809 }
4810
cda4b7d3 4811 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4812 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4813
ddc9003c
ZY		 4814 if (is_lvds && dev_priv->lvds_downclock_avail) {
4815 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4816 dev_priv->lvds_downclock,
4817 refclk,
4818 &reduced_clock);
18f9ed12
ZY		 4819 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4820 /*
4821 * If the different P is found, it means that we can't
4822 * switch the display clock by using the FP0/FP1.
4823 * In such case we will disable the LVDS downclock
4824 * feature.
4825 */
4826 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 4827 "LVDS clock/downclock\n");
18f9ed12
ZY		 4828 has_reduced_clock = 0;
4829 }
652c393a 4830 }
7026d4ac
ZW		 4831 /* SDVO TV has fixed PLL values depend on its clock range,
4832 this mirrors vbios setting. */
4833 if (is_sdvo && is_tv) {
4834 if (adjusted_mode->clock >= 100000
5eddb70b 4835 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4836 clock.p1 = 2;
4837 clock.p2 = 10;
4838 clock.n = 3;
4839 clock.m1 = 16;
4840 clock.m2 = 8;
4841 } else if (adjusted_mode->clock >= 140500
5eddb70b 4842 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4843 clock.p1 = 1;
4844 clock.p2 = 10;
4845 clock.n = 6;
4846 clock.m1 = 12;
4847 clock.m2 = 8;
4848 }
4849 }
4850
2c07245f 4851 /* FDI link */
8febb297
EA		 4852 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4853 lane = 0;
4854 /* CPU eDP doesn't require FDI link, so just set DP M/N
4855 according to current link config */
4856 if (has_edp_encoder &&
4857 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4858 target_clock = mode->clock;
4859 intel_edp_link_config(has_edp_encoder,
4860 &lane, &link_bw);
4861 } else {
4862 /* [e]DP over FDI requires target mode clock
4863 instead of link clock */
4864 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5eb08b69 4865 target_clock = mode->clock;
8febb297
EA		 4866 else
4867 target_clock = adjusted_mode->clock;
4868
4869 /* FDI is a binary signal running at ~2.7GHz, encoding
4870 * each output octet as 10 bits. The actual frequency
4871 * is stored as a divider into a 100MHz clock, and the
4872 * mode pixel clock is stored in units of 1KHz.
4873 * Hence the bw of each lane in terms of the mode signal
4874 * is:
4875 */
4876 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4877 }
58a27471 4878
8febb297
EA		 4879 /* determine panel color depth */
4880 temp = I915_READ(PIPECONF(pipe));
4881 temp &= ~PIPE_BPC_MASK;
4882 if (is_lvds) {
4883 /* the BPC will be 6 if it is 18-bit LVDS panel */
4884 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4885 temp |= PIPE_8BPC;
4886 else
4887 temp |= PIPE_6BPC;
4888 } else if (has_edp_encoder) {
4889 switch (dev_priv->edp.bpp/3) {
4890 case 8:
e5a95eb7 4891 temp |= PIPE_8BPC;
58a27471 4892 break;
8febb297
EA		 4893 case 10:
4894 temp |= PIPE_10BPC;
58a27471 4895 break;
8febb297
EA		 4896 case 6:
4897 temp |= PIPE_6BPC;
58a27471 4898 break;
8febb297
EA		 4899 case 12:
4900 temp |= PIPE_12BPC;
58a27471 4901 break;
77ffb597 4902 }
8febb297
EA		 4903 } else
4904 temp |= PIPE_8BPC;
4905 I915_WRITE(PIPECONF(pipe), temp);
77ffb597 4906
8febb297
EA		 4907 switch (temp & PIPE_BPC_MASK) {
4908 case PIPE_8BPC:
4909 bpp = 24;
4910 break;
4911 case PIPE_10BPC:
4912 bpp = 30;
4913 break;
4914 case PIPE_6BPC:
4915 bpp = 18;
4916 break;
4917 case PIPE_12BPC:
4918 bpp = 36;
4919 break;
4920 default:
4921 DRM_ERROR("unknown pipe bpc value\n");
4922 bpp = 24;
4923 }
77ffb597 4924
8febb297
EA		 4925 if (!lane) {
4926 /*
4927 * Account for spread spectrum to avoid
4928 * oversubscribing the link. Max center spread
4929 * is 2.5%; use 5% for safety's sake.
4930 */
4931 u32 bps = target_clock * bpp * 21 / 20;
4932 lane = bps / (link_bw * 8) + 1;
5eb08b69 4933 }
2c07245f 4934
8febb297
EA		 4935 intel_crtc->fdi_lanes = lane;
4936
4937 if (pixel_multiplier > 1)
4938 link_bw *= pixel_multiplier;
4939 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4940
c038e51e
ZW		 4941 /* Ironlake: try to setup display ref clock before DPLL
4942 * enabling. This is only under driver's control after
4943 * PCH B stepping, previous chipset stepping should be
4944 * ignoring this setting.
4945 */
8febb297
EA		 4946 temp = I915_READ(PCH_DREF_CONTROL);
4947 /* Always enable nonspread source */
4948 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4949 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4950 temp &= ~DREF_SSC_SOURCE_MASK;
4951 temp |= DREF_SSC_SOURCE_ENABLE;
4952 I915_WRITE(PCH_DREF_CONTROL, temp);
4953
4954 POSTING_READ(PCH_DREF_CONTROL);
4955 udelay(200);
fc9a2228 4956
8febb297
EA		 4957 if (has_edp_encoder) {
4958 if (intel_panel_use_ssc(dev_priv)) {
4959 temp |= DREF_SSC1_ENABLE;
fc9a2228 4960 I915_WRITE(PCH_DREF_CONTROL, temp);
8febb297 4961
fc9a2228
CW		 4962 POSTING_READ(PCH_DREF_CONTROL);
4963 udelay(200);
4964 }
8febb297
EA		 4965 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4966
4967 /* Enable CPU source on CPU attached eDP */
4968 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4969 if (intel_panel_use_ssc(dev_priv))
4970 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4971 else
4972 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4973 } else {
4974 /* Enable SSC on PCH eDP if needed */
4975 if (intel_panel_use_ssc(dev_priv)) {
4976 DRM_ERROR("enabling SSC on PCH\n");
4977 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4978 }
4979 }
4980 I915_WRITE(PCH_DREF_CONTROL, temp);
4981 POSTING_READ(PCH_DREF_CONTROL);
4982 udelay(200);
fc9a2228 4983 }
c038e51e 4984
a07d6787
EA		 4985 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4986 if (has_reduced_clock)
4987 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4988 reduced_clock.m2;
79e53945 4989
c1858123 4990 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4991 factor = 21;
4992 if (is_lvds) {
4993 if ((intel_panel_use_ssc(dev_priv) &&
4994 dev_priv->lvds_ssc_freq == 100) ||
4995 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4996 factor = 25;
4997 } else if (is_sdvo && is_tv)
4998 factor = 20;
c1858123 4999
cb0e0931 5000 if (clock.m < factor * clock.n)
8febb297 5001 fp |= FP_CB_TUNE;
2c07245f 5002
5eddb70b 5003 dpll = 0;
2c07245f 5004
a07d6787
EA		 5005 if (is_lvds)
5006 dpll |= DPLLB_MODE_LVDS;
5007 else
5008 dpll |= DPLLB_MODE_DAC_SERIAL;
5009 if (is_sdvo) {
5010 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5011 if (pixel_multiplier > 1) {
5012 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5013 }
a07d6787
EA		 5014 dpll |= DPLL_DVO_HIGH_SPEED;
5015 }
5016 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5017 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5018
a07d6787
EA		 5019 /* compute bitmask from p1 value */
5020 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5021 /* also FPA1 */
5022 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5023
5024 switch (clock.p2) {
5025 case 5:
5026 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5027 break;
5028 case 7:
5029 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5030 break;
5031 case 10:
5032 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5033 break;
5034 case 14:
5035 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5036 break;
79e53945
JB		 5037 }
5038
43565a06
KH		 5039 if (is_sdvo && is_tv)
5040 dpll |= PLL_REF_INPUT_TVCLKINBC;
5041 else if (is_tv)
79e53945 5042 /* XXX: just matching BIOS for now */
43565a06 5043 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5044 dpll |= 3;
a7615030 5045 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5046 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5047 else
5048 dpll |= PLL_REF_INPUT_DREFCLK;
5049
5050 /* setup pipeconf */
5eddb70b 5051 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5052
5053 /* Set up the display plane register */
5054 dspcntr = DISPPLANE_GAMMA_ENABLE;
5055
28c97730 5056 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 5057 drm_mode_debug_printmodeline(mode);
5058
5c5313c8
JB		 5059 /* PCH eDP needs FDI, but CPU eDP does not */
5060 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981
EA		 5061 I915_WRITE(PCH_FP0(pipe), fp);
5062 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 5063
fae14981 5064 POSTING_READ(PCH_DPLL(pipe));
79e53945
JB		 5065 udelay(150);
5066 }
5067
8db9d77b
ZW		 5068 /* enable transcoder DPLL */
5069 if (HAS_PCH_CPT(dev)) {
5070 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 5071 switch (pipe) {
5072 case 0:
5eddb70b 5073 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
9db4a9c7
JB		 5074 break;
5075 case 1:
5eddb70b 5076 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
9db4a9c7
JB		 5077 break;
5078 case 2:
5079 /* FIXME: manage transcoder PLLs? */
5080 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5081 break;
5082 default:
5083 BUG();
32f9d658 5084 }
8db9d77b 5085 I915_WRITE(PCH_DPLL_SEL, temp);
5eddb70b
CW		 5086
5087 POSTING_READ(PCH_DPLL_SEL);
8db9d77b
ZW		 5088 udelay(150);
5089 }
5090
79e53945
JB		 5091 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5092 * This is an exception to the general rule that mode_set doesn't turn
5093 * things on.
5094 */
5095 if (is_lvds) {
fae14981 5096 temp = I915_READ(PCH_LVDS);
5eddb70b 5097 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3
ZW		 5098 if (pipe == 1) {
5099 if (HAS_PCH_CPT(dev))
5eddb70b 5100 temp |= PORT_TRANS_B_SEL_CPT;
b3b095b3 5101 else
5eddb70b 5102 temp |= LVDS_PIPEB_SELECT;
b3b095b3
ZW		 5103 } else {
5104 if (HAS_PCH_CPT(dev))
5eddb70b 5105 temp &= ~PORT_TRANS_SEL_MASK;
b3b095b3 5106 else
5eddb70b 5107 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 5108 }
a3e17eb8 5109 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5110 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5111 /* Set the B0-B3 data pairs corresponding to whether we're going to
5112 * set the DPLLs for dual-channel mode or not.
5113 */
5114 if (clock.p2 == 7)
5eddb70b 5115 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5116 else
5eddb70b 5117 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5118
5119 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5120 * appropriately here, but we need to look more thoroughly into how
5121 * panels behave in the two modes.
5122 */
aa9b500d
BF		 5123 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5124 lvds_sync |= LVDS_HSYNC_POLARITY;
5125 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5126 lvds_sync |= LVDS_VSYNC_POLARITY;
5127 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5128 != lvds_sync) {
5129 char flags[2] = "-+";
5130 DRM_INFO("Changing LVDS panel from "
5131 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5132 flags[!(temp & LVDS_HSYNC_POLARITY)],
5133 flags[!(temp & LVDS_VSYNC_POLARITY)],
5134 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5135 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5136 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5137 temp |= lvds_sync;
5138 }
fae14981 5139 I915_WRITE(PCH_LVDS, temp);
79e53945 5140 }
434ed097
JB		 5141
5142 /* set the dithering flag and clear for anything other than a panel. */
8febb297
EA		 5143 pipeconf &= ~PIPECONF_DITHER_EN;
5144 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5145 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
5146 pipeconf |= PIPECONF_DITHER_EN;
5147 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
434ed097
JB		 5148 }
5149
5c5313c8 5150 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
a4fc5ed6 5151 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5152 } else {
8db9d77b 5153 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5154 I915_WRITE(TRANSDATA_M1(pipe), 0);
5155 I915_WRITE(TRANSDATA_N1(pipe), 0);
5156 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5157 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5158 }
79e53945 5159
8febb297
EA		 5160 if (!has_edp_encoder ||
5161 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981 5162 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 5163
32f9d658 5164 /* Wait for the clocks to stabilize. */
fae14981 5165 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 5166 udelay(150);
5167
8febb297
EA		 5168 /* The pixel multiplier can only be updated once the
5169 * DPLL is enabled and the clocks are stable.
5170 *
5171 * So write it again.
5172 */
fae14981 5173 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 5174 }
79e53945 5175
5eddb70b 5176 intel_crtc->lowfreq_avail = false;
652c393a 5177 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 5178 I915_WRITE(PCH_FP1(pipe), fp2);
652c393a
JB		 5179 intel_crtc->lowfreq_avail = true;
5180 if (HAS_PIPE_CXSR(dev)) {
28c97730 5181 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 5182 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5183 }
5184 } else {
fae14981 5185 I915_WRITE(PCH_FP1(pipe), fp);
652c393a 5186 if (HAS_PIPE_CXSR(dev)) {
28c97730 5187 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5188 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5189 }
5190 }
5191
734b4157
KH		 5192 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5193 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5194 /* the chip adds 2 halflines automatically */
5195 adjusted_mode->crtc_vdisplay -= 1;
5196 adjusted_mode->crtc_vtotal -= 1;
5197 adjusted_mode->crtc_vblank_start -= 1;
5198 adjusted_mode->crtc_vblank_end -= 1;
5199 adjusted_mode->crtc_vsync_end -= 1;
5200 adjusted_mode->crtc_vsync_start -= 1;
5201 } else
5202 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5203
5eddb70b
CW		 5204 I915_WRITE(HTOTAL(pipe),
5205 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5206 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5207 I915_WRITE(HBLANK(pipe),
5208 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5209 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5210 I915_WRITE(HSYNC(pipe),
5211 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5212 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5213
5214 I915_WRITE(VTOTAL(pipe),
5215 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5216 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5217 I915_WRITE(VBLANK(pipe),
5218 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5219 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5220 I915_WRITE(VSYNC(pipe),
5221 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5222 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 5223
8febb297
EA		 5224 /* pipesrc controls the size that is scaled from, which should
5225 * always be the user's requested size.
79e53945 5226 */
5eddb70b
CW		 5227 I915_WRITE(PIPESRC(pipe),
5228 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5229
8febb297
EA		 5230 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5231 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5232 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5233 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 5234
8febb297
EA		 5235 if (has_edp_encoder &&
5236 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5237 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f
ZW		 5238 }
5239
5eddb70b
CW		 5240 I915_WRITE(PIPECONF(pipe), pipeconf);
5241 POSTING_READ(PIPECONF(pipe));
79e53945 5242
9d0498a2 5243 intel_wait_for_vblank(dev, pipe);
79e53945 5244
f00a3ddf 5245 if (IS_GEN5(dev)) {
553bd149
ZW		 5246 /* enable address swizzle for tiling buffer */
5247 temp = I915_READ(DISP_ARB_CTL);
5248 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5249 }
5250
5eddb70b 5251 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 5252 POSTING_READ(DSPCNTR(plane));
79e53945 5253
5c3b82e2 5254 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 5255
5256 intel_update_watermarks(dev);
5257
1f803ee5 5258 return ret;
79e53945
JB		 5259}
5260
f564048e
EA		 5261static int intel_crtc_mode_set(struct drm_crtc *crtc,
5262 struct drm_display_mode *mode,
5263 struct drm_display_mode *adjusted_mode,
5264 int x, int y,
5265 struct drm_framebuffer *old_fb)
5266{
5267 struct drm_device *dev = crtc->dev;
5268 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5270 int pipe = intel_crtc->pipe;
f564048e
EA		 5271 int ret;
5272
0b701d27 5273 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5274
f564048e
EA		 5275 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5276 x, y, old_fb);
7662c8bd 5277
79e53945 5278 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5279
120eced9
KP		 5280 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5281
1f803ee5 5282 return ret;
79e53945
JB		 5283}
5284
5285/** Loads the palette/gamma unit for the CRTC with the prepared values */
5286void intel_crtc_load_lut(struct drm_crtc *crtc)
5287{
5288 struct drm_device *dev = crtc->dev;
5289 struct drm_i915_private *dev_priv = dev->dev_private;
5290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5291 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5292 int i;
5293
5294 /* The clocks have to be on to load the palette. */
5295 if (!crtc->enabled)
5296 return;
5297
f2b115e6 5298 /* use legacy palette for Ironlake */
bad720ff 5299 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5300 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5301
79e53945
JB		 5302 for (i = 0; i < 256; i++) {
5303 I915_WRITE(palreg + 4 * i,
5304 (intel_crtc->lut_r[i] << 16) |
5305 (intel_crtc->lut_g[i] << 8) |
5306 intel_crtc->lut_b[i]);
5307 }
5308}
5309
560b85bb
CW		 5310static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5311{
5312 struct drm_device *dev = crtc->dev;
5313 struct drm_i915_private *dev_priv = dev->dev_private;
5314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5315 bool visible = base != 0;
5316 u32 cntl;
5317
5318 if (intel_crtc->cursor_visible == visible)
5319 return;
5320
9db4a9c7 5321 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5322 if (visible) {
5323 /* On these chipsets we can only modify the base whilst
5324 * the cursor is disabled.
5325 */
9db4a9c7 5326 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5327
5328 cntl &= ~(CURSOR_FORMAT_MASK);
5329 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5330 cntl |= CURSOR_ENABLE |
5331 CURSOR_GAMMA_ENABLE |
5332 CURSOR_FORMAT_ARGB;
5333 } else
5334 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5335 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5336
5337 intel_crtc->cursor_visible = visible;
5338}
5339
5340static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5341{
5342 struct drm_device *dev = crtc->dev;
5343 struct drm_i915_private *dev_priv = dev->dev_private;
5344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5345 int pipe = intel_crtc->pipe;
5346 bool visible = base != 0;
5347
5348 if (intel_crtc->cursor_visible != visible) {
548f245b 5349 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5350 if (base) {
5351 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5352 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5353 cntl |= pipe << 28; /* Connect to correct pipe */
5354 } else {
5355 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5356 cntl |= CURSOR_MODE_DISABLE;
5357 }
9db4a9c7 5358 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5359
5360 intel_crtc->cursor_visible = visible;
5361 }
5362 /* and commit changes on next vblank */
9db4a9c7 5363 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5364}
5365
cda4b7d3 5366/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5367static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5368 bool on)
cda4b7d3
CW		 5369{
5370 struct drm_device *dev = crtc->dev;
5371 struct drm_i915_private *dev_priv = dev->dev_private;
5372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5373 int pipe = intel_crtc->pipe;
5374 int x = intel_crtc->cursor_x;
5375 int y = intel_crtc->cursor_y;
560b85bb 5376 u32 base, pos;
cda4b7d3
CW		 5377 bool visible;
5378
5379 pos = 0;
5380
6b383a7f 5381 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5382 base = intel_crtc->cursor_addr;
5383 if (x > (int) crtc->fb->width)
5384 base = 0;
5385
5386 if (y > (int) crtc->fb->height)
5387 base = 0;
5388 } else
5389 base = 0;
5390
5391 if (x < 0) {
5392 if (x + intel_crtc->cursor_width < 0)
5393 base = 0;
5394
5395 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5396 x = -x;
5397 }
5398 pos |= x << CURSOR_X_SHIFT;
5399
5400 if (y < 0) {
5401 if (y + intel_crtc->cursor_height < 0)
5402 base = 0;
5403
5404 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5405 y = -y;
5406 }
5407 pos |= y << CURSOR_Y_SHIFT;
5408
5409 visible = base != 0;
560b85bb 5410 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5411 return;
5412
9db4a9c7 5413 I915_WRITE(CURPOS(pipe), pos);
560b85bb
CW		 5414 if (IS_845G(dev) || IS_I865G(dev))
5415 i845_update_cursor(crtc, base);
5416 else
5417 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 5418
5419 if (visible)
5420 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5421}
5422
79e53945 5423static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5424 struct drm_file *file,
79e53945
JB		 5425 uint32_t handle,
5426 uint32_t width, uint32_t height)
5427{
5428 struct drm_device *dev = crtc->dev;
5429 struct drm_i915_private *dev_priv = dev->dev_private;
5430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5431 struct drm_i915_gem_object *obj;
cda4b7d3 5432 uint32_t addr;
3f8bc370 5433 int ret;
79e53945 5434
28c97730 5435 DRM_DEBUG_KMS("\n");
79e53945
JB		 5436
5437 /* if we want to turn off the cursor ignore width and height */
5438 if (!handle) {
28c97730 5439 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5440 addr = 0;
05394f39 5441 obj = NULL;
5004417d 5442 mutex_lock(&dev->struct_mutex);
3f8bc370 5443 goto finish;
79e53945
JB		 5444 }
5445
5446 /* Currently we only support 64x64 cursors */
5447 if (width != 64 || height != 64) {
5448 DRM_ERROR("we currently only support 64x64 cursors\n");
5449 return -EINVAL;
5450 }
5451
05394f39 5452 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5453 if (&obj->base == NULL)
79e53945
JB		 5454 return -ENOENT;
5455
05394f39 5456 if (obj->base.size < width * height * 4) {
79e53945 5457 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5458 ret = -ENOMEM;
5459 goto fail;
79e53945
JB		 5460 }
5461
71acb5eb 5462 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5463 mutex_lock(&dev->struct_mutex);
b295d1b6 5464 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5465 if (obj->tiling_mode) {
5466 DRM_ERROR("cursor cannot be tiled\n");
5467 ret = -EINVAL;
5468 goto fail_locked;
5469 }
5470
05394f39 5471 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
71acb5eb
DA		 5472 if (ret) {
5473 DRM_ERROR("failed to pin cursor bo\n");
7f9872e0 5474 goto fail_locked;
71acb5eb 5475 }
e7b526bb 5476
05394f39 5477 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
e7b526bb
CW		 5478 if (ret) {
5479 DRM_ERROR("failed to move cursor bo into the GTT\n");
5480 goto fail_unpin;
5481 }
5482
d9e86c0e
CW		 5483 ret = i915_gem_object_put_fence(obj);
5484 if (ret) {
5485 DRM_ERROR("failed to move cursor bo into the GTT\n");
5486 goto fail_unpin;
5487 }
5488
05394f39 5489 addr = obj->gtt_offset;
71acb5eb 5490 } else {
6eeefaf3 5491 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5492 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5493 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5494 align);
71acb5eb
DA		 5495 if (ret) {
5496 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5497 goto fail_locked;
71acb5eb 5498 }
05394f39 5499 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5500 }
5501
a6c45cf0 5502 if (IS_GEN2(dev))
14b60391
JB		 5503 I915_WRITE(CURSIZE, (height << 12) | width);
5504
3f8bc370 5505 finish:
3f8bc370 5506 if (intel_crtc->cursor_bo) {
b295d1b6 5507 if (dev_priv->info->cursor_needs_physical) {
05394f39 5508 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5509 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5510 } else
5511 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5512 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5513 }
80824003 5514
7f9872e0 5515 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5516
5517 intel_crtc->cursor_addr = addr;
05394f39 5518 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5519 intel_crtc->cursor_width = width;
5520 intel_crtc->cursor_height = height;
5521
6b383a7f 5522 intel_crtc_update_cursor(crtc, true);
3f8bc370 5523
79e53945 5524 return 0;
e7b526bb 5525fail_unpin:
05394f39 5526 i915_gem_object_unpin(obj);
7f9872e0 5527fail_locked:
34b8686e 5528 mutex_unlock(&dev->struct_mutex);
bc9025bd 5529fail:
05394f39 5530 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5531 return ret;
79e53945
JB		 5532}
5533
5534static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5535{
79e53945 5536 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5537
cda4b7d3
CW		 5538 intel_crtc->cursor_x = x;
5539 intel_crtc->cursor_y = y;
652c393a 5540
6b383a7f 5541 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5542
5543 return 0;
5544}
5545
5546/** Sets the color ramps on behalf of RandR */
5547void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5548 u16 blue, int regno)
5549{
5550 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5551
5552 intel_crtc->lut_r[regno] = red >> 8;
5553 intel_crtc->lut_g[regno] = green >> 8;
5554 intel_crtc->lut_b[regno] = blue >> 8;
5555}
5556
b8c00ac5
DA		 5557void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5558 u16 *blue, int regno)
5559{
5560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5561
5562 *red = intel_crtc->lut_r[regno] << 8;
5563 *green = intel_crtc->lut_g[regno] << 8;
5564 *blue = intel_crtc->lut_b[regno] << 8;
5565}
5566
79e53945 5567static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5568 u16 *blue, uint32_t start, uint32_t size)
79e53945 5569{
7203425a 5570 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5572
7203425a 5573 for (i = start; i < end; i++) {
79e53945
JB		 5574 intel_crtc->lut_r[i] = red[i] >> 8;
5575 intel_crtc->lut_g[i] = green[i] >> 8;
5576 intel_crtc->lut_b[i] = blue[i] >> 8;
5577 }
5578
5579 intel_crtc_load_lut(crtc);
5580}
5581
5582/**
5583 * Get a pipe with a simple mode set on it for doing load-based monitor
5584 * detection.
5585 *
5586 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5587 * its requirements. The pipe will be connected to no other encoders.
79e53945 5588 *
c751ce4f 5589 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5590 * configured for it. In the future, it could choose to temporarily disable
5591 * some outputs to free up a pipe for its use.
5592 *
5593 * \return crtc, or NULL if no pipes are available.
5594 */
5595
5596/* VESA 640x480x72Hz mode to set on the pipe */
5597static struct drm_display_mode load_detect_mode = {
5598 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5599 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5600};
5601
d2dff872
CW		 5602static struct drm_framebuffer *
5603intel_framebuffer_create(struct drm_device *dev,
5604 struct drm_mode_fb_cmd *mode_cmd,
5605 struct drm_i915_gem_object *obj)
5606{
5607 struct intel_framebuffer *intel_fb;
5608 int ret;
5609
5610 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5611 if (!intel_fb) {
5612 drm_gem_object_unreference_unlocked(&obj->base);
5613 return ERR_PTR(-ENOMEM);
5614 }
5615
5616 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5617 if (ret) {
5618 drm_gem_object_unreference_unlocked(&obj->base);
5619 kfree(intel_fb);
5620 return ERR_PTR(ret);
5621 }
5622
5623 return &intel_fb->base;
5624}
5625
5626static u32
5627intel_framebuffer_pitch_for_width(int width, int bpp)
5628{
5629 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5630 return ALIGN(pitch, 64);
5631}
5632
5633static u32
5634intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5635{
5636 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5637 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5638}
5639
5640static struct drm_framebuffer *
5641intel_framebuffer_create_for_mode(struct drm_device *dev,
5642 struct drm_display_mode *mode,
5643 int depth, int bpp)
5644{
5645 struct drm_i915_gem_object *obj;
5646 struct drm_mode_fb_cmd mode_cmd;
5647
5648 obj = i915_gem_alloc_object(dev,
5649 intel_framebuffer_size_for_mode(mode, bpp));
5650 if (obj == NULL)
5651 return ERR_PTR(-ENOMEM);
5652
5653 mode_cmd.width = mode->hdisplay;
5654 mode_cmd.height = mode->vdisplay;
5655 mode_cmd.depth = depth;
5656 mode_cmd.bpp = bpp;
5657 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
5658
5659 return intel_framebuffer_create(dev, &mode_cmd, obj);
5660}
5661
5662static struct drm_framebuffer *
5663mode_fits_in_fbdev(struct drm_device *dev,
5664 struct drm_display_mode *mode)
5665{
5666 struct drm_i915_private *dev_priv = dev->dev_private;
5667 struct drm_i915_gem_object *obj;
5668 struct drm_framebuffer *fb;
5669
5670 if (dev_priv->fbdev == NULL)
5671 return NULL;
5672
5673 obj = dev_priv->fbdev->ifb.obj;
5674 if (obj == NULL)
5675 return NULL;
5676
5677 fb = &dev_priv->fbdev->ifb.base;
5678 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
5679 fb->bits_per_pixel))
5680 return NULL;
5681
5682 if (obj->base.size < mode->vdisplay * fb->pitch)
5683 return NULL;
5684
5685 return fb;
5686}
5687
7173188d
CW		 5688bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5689 struct drm_connector *connector,
5690 struct drm_display_mode *mode,
8261b191 5691 struct intel_load_detect_pipe *old)
79e53945
JB		 5692{
5693 struct intel_crtc *intel_crtc;
5694 struct drm_crtc *possible_crtc;
4ef69c7a 5695 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5696 struct drm_crtc *crtc = NULL;
5697 struct drm_device *dev = encoder->dev;
d2dff872 5698 struct drm_framebuffer *old_fb;
79e53945
JB		 5699 int i = -1;
5700
d2dff872
CW		 5701 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5702 connector->base.id, drm_get_connector_name(connector),
5703 encoder->base.id, drm_get_encoder_name(encoder));
5704
79e53945
JB		 5705 /*
5706 * Algorithm gets a little messy:
7a5e4805 5707 *
79e53945
JB		 5708 * - if the connector already has an assigned crtc, use it (but make
5709 * sure it's on first)
7a5e4805 5710 *
79e53945
JB		 5711 * - try to find the first unused crtc that can drive this connector,
5712 * and use that if we find one
79e53945
JB		 5713 */
5714
5715 /* See if we already have a CRTC for this connector */
5716 if (encoder->crtc) {
5717 crtc = encoder->crtc;
8261b191 5718
79e53945 5719 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5720 old->dpms_mode = intel_crtc->dpms_mode;
5721 old->load_detect_temp = false;
5722
5723 /* Make sure the crtc and connector are running */
79e53945 5724 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 5725 struct drm_encoder_helper_funcs *encoder_funcs;
5726 struct drm_crtc_helper_funcs *crtc_funcs;
5727
79e53945
JB		 5728 crtc_funcs = crtc->helper_private;
5729 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 5730
5731 encoder_funcs = encoder->helper_private;
79e53945
JB		 5732 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5733 }
8261b191 5734
7173188d 5735 return true;
79e53945
JB		 5736 }
5737
5738 /* Find an unused one (if possible) */
5739 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5740 i++;
5741 if (!(encoder->possible_crtcs & (1 << i)))
5742 continue;
5743 if (!possible_crtc->enabled) {
5744 crtc = possible_crtc;
5745 break;
5746 }
79e53945
JB		 5747 }
5748
5749 /*
5750 * If we didn't find an unused CRTC, don't use any.
5751 */
5752 if (!crtc) {
7173188d
CW		 5753 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5754 return false;
79e53945
JB		 5755 }
5756
5757 encoder->crtc = crtc;
c1c43977 5758 connector->encoder = encoder;
79e53945
JB		 5759
5760 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5761 old->dpms_mode = intel_crtc->dpms_mode;
5762 old->load_detect_temp = true;
d2dff872 5763 old->release_fb = NULL;
79e53945 5764
6492711d
CW		 5765 if (!mode)
5766 mode = &load_detect_mode;
79e53945 5767
d2dff872
CW		 5768 old_fb = crtc->fb;
5769
5770 /* We need a framebuffer large enough to accommodate all accesses
5771 * that the plane may generate whilst we perform load detection.
5772 * We can not rely on the fbcon either being present (we get called
5773 * during its initialisation to detect all boot displays, or it may
5774 * not even exist) or that it is large enough to satisfy the
5775 * requested mode.
5776 */
5777 crtc->fb = mode_fits_in_fbdev(dev, mode);
5778 if (crtc->fb == NULL) {
5779 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5780 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5781 old->release_fb = crtc->fb;
5782 } else
5783 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5784 if (IS_ERR(crtc->fb)) {
5785 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5786 crtc->fb = old_fb;
5787 return false;
79e53945 5788 }
79e53945 5789
d2dff872 5790 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 5791 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5792 if (old->release_fb)
5793 old->release_fb->funcs->destroy(old->release_fb);
5794 crtc->fb = old_fb;
6492711d 5795 return false;
79e53945 5796 }
7173188d 5797
79e53945 5798 /* let the connector get through one full cycle before testing */
9d0498a2 5799 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5800
7173188d 5801 return true;
79e53945
JB		 5802}
5803
c1c43977 5804void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 5805 struct drm_connector *connector,
5806 struct intel_load_detect_pipe *old)
79e53945 5807{
4ef69c7a 5808 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5809 struct drm_device *dev = encoder->dev;
5810 struct drm_crtc *crtc = encoder->crtc;
5811 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5812 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5813
d2dff872
CW		 5814 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5815 connector->base.id, drm_get_connector_name(connector),
5816 encoder->base.id, drm_get_encoder_name(encoder));
5817
8261b191 5818 if (old->load_detect_temp) {
c1c43977 5819 connector->encoder = NULL;
79e53945 5820 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 5821
5822 if (old->release_fb)
5823 old->release_fb->funcs->destroy(old->release_fb);
5824
0622a53c 5825 return;
79e53945
JB		 5826 }
5827
c751ce4f 5828 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 5829 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5830 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 5831 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 5832 }
5833}
5834
5835/* Returns the clock of the currently programmed mode of the given pipe. */
5836static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5837{
5838 struct drm_i915_private *dev_priv = dev->dev_private;
5839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5840 int pipe = intel_crtc->pipe;
548f245b 5841 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5842 u32 fp;
5843 intel_clock_t clock;
5844
5845 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5846 fp = I915_READ(FP0(pipe));
79e53945 5847 else
39adb7a5 5848 fp = I915_READ(FP1(pipe));
79e53945
JB		 5849
5850 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5851 if (IS_PINEVIEW(dev)) {
5852 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5853 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5854 } else {
5855 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5856 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5857 }
5858
a6c45cf0 5859 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5860 if (IS_PINEVIEW(dev))
5861 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5862 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5863 else
5864 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5865 DPLL_FPA01_P1_POST_DIV_SHIFT);
5866
5867 switch (dpll & DPLL_MODE_MASK) {
5868 case DPLLB_MODE_DAC_SERIAL:
5869 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5870 5 : 10;
5871 break;
5872 case DPLLB_MODE_LVDS:
5873 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5874 7 : 14;
5875 break;
5876 default:
28c97730 5877 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5878 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5879 return 0;
5880 }
5881
5882 /* XXX: Handle the 100Mhz refclk */
2177832f 5883 intel_clock(dev, 96000, &clock);
79e53945
JB		 5884 } else {
5885 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5886
5887 if (is_lvds) {
5888 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5889 DPLL_FPA01_P1_POST_DIV_SHIFT);
5890 clock.p2 = 14;
5891
5892 if ((dpll & PLL_REF_INPUT_MASK) ==
5893 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5894 /* XXX: might not be 66MHz */
2177832f 5895 intel_clock(dev, 66000, &clock);
79e53945 5896 } else
2177832f 5897 intel_clock(dev, 48000, &clock);
79e53945
JB		 5898 } else {
5899 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5900 clock.p1 = 2;
5901 else {
5902 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5903 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5904 }
5905 if (dpll & PLL_P2_DIVIDE_BY_4)
5906 clock.p2 = 4;
5907 else
5908 clock.p2 = 2;
5909
2177832f 5910 intel_clock(dev, 48000, &clock);
79e53945
JB		 5911 }
5912 }
5913
5914 /* XXX: It would be nice to validate the clocks, but we can't reuse
5915 * i830PllIsValid() because it relies on the xf86_config connector
5916 * configuration being accurate, which it isn't necessarily.
5917 */
5918
5919 return clock.dot;
5920}
5921
5922/** Returns the currently programmed mode of the given pipe. */
5923struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5924 struct drm_crtc *crtc)
5925{
548f245b 5926 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5927 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5928 int pipe = intel_crtc->pipe;
5929 struct drm_display_mode *mode;
548f245b
JB		 5930 int htot = I915_READ(HTOTAL(pipe));
5931 int hsync = I915_READ(HSYNC(pipe));
5932 int vtot = I915_READ(VTOTAL(pipe));
5933 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5934
5935 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5936 if (!mode)
5937 return NULL;
5938
5939 mode->clock = intel_crtc_clock_get(dev, crtc);
5940 mode->hdisplay = (htot & 0xffff) + 1;
5941 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5942 mode->hsync_start = (hsync & 0xffff) + 1;
5943 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5944 mode->vdisplay = (vtot & 0xffff) + 1;
5945 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5946 mode->vsync_start = (vsync & 0xffff) + 1;
5947 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5948
5949 drm_mode_set_name(mode);
5950 drm_mode_set_crtcinfo(mode, 0);
5951
5952 return mode;
5953}
5954
652c393a
JB		 5955#define GPU_IDLE_TIMEOUT 500 /* ms */
5956
5957/* When this timer fires, we've been idle for awhile */
5958static void intel_gpu_idle_timer(unsigned long arg)
5959{
5960 struct drm_device *dev = (struct drm_device *)arg;
5961 drm_i915_private_t *dev_priv = dev->dev_private;
5962
ff7ea4c0
CW		 5963 if (!list_empty(&dev_priv->mm.active_list)) {
5964 /* Still processing requests, so just re-arm the timer. */
5965 mod_timer(&dev_priv->idle_timer, jiffies +
5966 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5967 return;
5968 }
652c393a 5969
ff7ea4c0 5970 dev_priv->busy = false;
01dfba93 5971 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5972}
5973
652c393a
JB		 5974#define CRTC_IDLE_TIMEOUT 1000 /* ms */
5975
5976static void intel_crtc_idle_timer(unsigned long arg)
5977{
5978 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5979 struct drm_crtc *crtc = &intel_crtc->base;
5980 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 5981 struct intel_framebuffer *intel_fb;
652c393a 5982
ff7ea4c0
CW		 5983 intel_fb = to_intel_framebuffer(crtc->fb);
5984 if (intel_fb && intel_fb->obj->active) {
5985 /* The framebuffer is still being accessed by the GPU. */
5986 mod_timer(&intel_crtc->idle_timer, jiffies +
5987 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5988 return;
5989 }
652c393a 5990
ff7ea4c0 5991 intel_crtc->busy = false;
01dfba93 5992 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5993}
5994
3dec0095 5995static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 5996{
5997 struct drm_device *dev = crtc->dev;
5998 drm_i915_private_t *dev_priv = dev->dev_private;
5999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6000 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6001 int dpll_reg = DPLL(pipe);
6002 int dpll;
652c393a 6003
bad720ff 6004 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6005 return;
6006
6007 if (!dev_priv->lvds_downclock_avail)
6008 return;
6009
dbdc6479 6010 dpll = I915_READ(dpll_reg);
652c393a 6011 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6012 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a
JB		 6013
6014 /* Unlock panel regs */
dbdc6479
JB		 6015 I915_WRITE(PP_CONTROL,
6016 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
652c393a
JB		 6017
6018 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6019 I915_WRITE(dpll_reg, dpll);
9d0498a2 6020 intel_wait_for_vblank(dev, pipe);
dbdc6479 6021
652c393a
JB		 6022 dpll = I915_READ(dpll_reg);
6023 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6024 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 6025
6026 /* ...and lock them again */
6027 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6028 }
6029
6030 /* Schedule downclock */
3dec0095
DV		 6031 mod_timer(&intel_crtc->idle_timer, jiffies +
6032 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 6033}
6034
6035static void intel_decrease_pllclock(struct drm_crtc *crtc)
6036{
6037 struct drm_device *dev = crtc->dev;
6038 drm_i915_private_t *dev_priv = dev->dev_private;
6039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6040 int pipe = intel_crtc->pipe;
9db4a9c7 6041 int dpll_reg = DPLL(pipe);
652c393a
JB		 6042 int dpll = I915_READ(dpll_reg);
6043
bad720ff 6044 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6045 return;
6046
6047 if (!dev_priv->lvds_downclock_avail)
6048 return;
6049
6050 /*
6051 * Since this is called by a timer, we should never get here in
6052 * the manual case.
6053 */
6054 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 6055 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a
JB		 6056
6057 /* Unlock panel regs */
4a655f04
JB		 6058 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6059 PANEL_UNLOCK_REGS);
652c393a
JB		 6060
6061 dpll |= DISPLAY_RATE_SELECT_FPA1;
6062 I915_WRITE(dpll_reg, dpll);
9d0498a2 6063 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6064 dpll = I915_READ(dpll_reg);
6065 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6066 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6067
6068 /* ...and lock them again */
6069 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6070 }
6071
6072}
6073
6074/**
6075 * intel_idle_update - adjust clocks for idleness
6076 * @work: work struct
6077 *
6078 * Either the GPU or display (or both) went idle. Check the busy status
6079 * here and adjust the CRTC and GPU clocks as necessary.
6080 */
6081static void intel_idle_update(struct work_struct *work)
6082{
6083 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6084 idle_work);
6085 struct drm_device *dev = dev_priv->dev;
6086 struct drm_crtc *crtc;
6087 struct intel_crtc *intel_crtc;
6088
6089 if (!i915_powersave)
6090 return;
6091
6092 mutex_lock(&dev->struct_mutex);
6093
7648fa99
JB		 6094 i915_update_gfx_val(dev_priv);
6095
652c393a
JB		 6096 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6097 /* Skip inactive CRTCs */
6098 if (!crtc->fb)
6099 continue;
6100
6101 intel_crtc = to_intel_crtc(crtc);
6102 if (!intel_crtc->busy)
6103 intel_decrease_pllclock(crtc);
6104 }
6105
45ac22c8 6106
652c393a
JB		 6107 mutex_unlock(&dev->struct_mutex);
6108}
6109
6110/**
6111 * intel_mark_busy - mark the GPU and possibly the display busy
6112 * @dev: drm device
6113 * @obj: object we're operating on
6114 *
6115 * Callers can use this function to indicate that the GPU is busy processing
6116 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6117 * buffer), we'll also mark the display as busy, so we know to increase its
6118 * clock frequency.
6119 */
05394f39 6120void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 6121{
6122 drm_i915_private_t *dev_priv = dev->dev_private;
6123 struct drm_crtc *crtc = NULL;
6124 struct intel_framebuffer *intel_fb;
6125 struct intel_crtc *intel_crtc;
6126
5e17ee74
ZW		 6127 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6128 return;
6129
18b2190c 6130 if (!dev_priv->busy)
28cf798f 6131 dev_priv->busy = true;
18b2190c 6132 else
28cf798f
CW		 6133 mod_timer(&dev_priv->idle_timer, jiffies +
6134 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 6135
6136 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6137 if (!crtc->fb)
6138 continue;
6139
6140 intel_crtc = to_intel_crtc(crtc);
6141 intel_fb = to_intel_framebuffer(crtc->fb);
6142 if (intel_fb->obj == obj) {
6143 if (!intel_crtc->busy) {
6144 /* Non-busy -> busy, upclock */
3dec0095 6145 intel_increase_pllclock(crtc);
652c393a
JB		 6146 intel_crtc->busy = true;
6147 } else {
6148 /* Busy -> busy, put off timer */
6149 mod_timer(&intel_crtc->idle_timer, jiffies +
6150 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6151 }
6152 }
6153 }
6154}
6155
79e53945
JB		 6156static void intel_crtc_destroy(struct drm_crtc *crtc)
6157{
6158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6159 struct drm_device *dev = crtc->dev;
6160 struct intel_unpin_work *work;
6161 unsigned long flags;
6162
6163 spin_lock_irqsave(&dev->event_lock, flags);
6164 work = intel_crtc->unpin_work;
6165 intel_crtc->unpin_work = NULL;
6166 spin_unlock_irqrestore(&dev->event_lock, flags);
6167
6168 if (work) {
6169 cancel_work_sync(&work->work);
6170 kfree(work);
6171 }
79e53945
JB		 6172
6173 drm_crtc_cleanup(crtc);
67e77c5a 6174
79e53945
JB		 6175 kfree(intel_crtc);
6176}
6177
6b95a207
KH		 6178static void intel_unpin_work_fn(struct work_struct *__work)
6179{
6180 struct intel_unpin_work *work =
6181 container_of(__work, struct intel_unpin_work, work);
6182
6183 mutex_lock(&work->dev->struct_mutex);
b1b87f6b 6184 i915_gem_object_unpin(work->old_fb_obj);
05394f39
CW		 6185 drm_gem_object_unreference(&work->pending_flip_obj->base);
6186 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6187
6b95a207
KH		 6188 mutex_unlock(&work->dev->struct_mutex);
6189 kfree(work);
6190}
6191
1afe3e9d 6192static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6193 struct drm_crtc *crtc)
6b95a207
KH		 6194{
6195 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6197 struct intel_unpin_work *work;
05394f39 6198 struct drm_i915_gem_object *obj;
6b95a207 6199 struct drm_pending_vblank_event *e;
49b14a5c 6200 struct timeval tnow, tvbl;
6b95a207
KH		 6201 unsigned long flags;
6202
6203 /* Ignore early vblank irqs */
6204 if (intel_crtc == NULL)
6205 return;
6206
49b14a5c
MK		 6207 do_gettimeofday(&tnow);
6208
6b95a207
KH		 6209 spin_lock_irqsave(&dev->event_lock, flags);
6210 work = intel_crtc->unpin_work;
6211 if (work == NULL || !work->pending) {
6212 spin_unlock_irqrestore(&dev->event_lock, flags);
6213 return;
6214 }
6215
6216 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6217
6218 if (work->event) {
6219 e = work->event;
49b14a5c 6220 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6221
6222 /* Called before vblank count and timestamps have
6223 * been updated for the vblank interval of flip
6224 * completion? Need to increment vblank count and
6225 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6226 * to account for this. We assume this happened if we
6227 * get called over 0.9 frame durations after the last
6228 * timestamped vblank.
6229 *
6230 * This calculation can not be used with vrefresh rates
6231 * below 5Hz (10Hz to be on the safe side) without
6232 * promoting to 64 integers.
0af7e4df 6233 */
49b14a5c
MK		 6234 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6235 9 * crtc->framedur_ns) {
0af7e4df 6236 e->event.sequence++;
49b14a5c
MK		 6237 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6238 crtc->framedur_ns);
0af7e4df
MK		 6239 }
6240
49b14a5c
MK		 6241 e->event.tv_sec = tvbl.tv_sec;
6242 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6243
6b95a207
KH		 6244 list_add_tail(&e->base.link,
6245 &e->base.file_priv->event_list);
6246 wake_up_interruptible(&e->base.file_priv->event_wait);
6247 }
6248
0af7e4df
MK		 6249 drm_vblank_put(dev, intel_crtc->pipe);
6250
6b95a207
KH		 6251 spin_unlock_irqrestore(&dev->event_lock, flags);
6252
05394f39 6253 obj = work->old_fb_obj;
d9e86c0e 6254
e59f2bac 6255 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6256 &obj->pending_flip.counter);
6257 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6258 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6259
6b95a207 6260 schedule_work(&work->work);
e5510fac
JB		 6261
6262 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6263}
6264
1afe3e9d
JB		 6265void intel_finish_page_flip(struct drm_device *dev, int pipe)
6266{
6267 drm_i915_private_t *dev_priv = dev->dev_private;
6268 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6269
49b14a5c 6270 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6271}
6272
6273void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6274{
6275 drm_i915_private_t *dev_priv = dev->dev_private;
6276 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6277
49b14a5c 6278 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6279}
6280
6b95a207
KH		 6281void intel_prepare_page_flip(struct drm_device *dev, int plane)
6282{
6283 drm_i915_private_t *dev_priv = dev->dev_private;
6284 struct intel_crtc *intel_crtc =
6285 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6286 unsigned long flags;
6287
6288 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6289 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6290 if ((++intel_crtc->unpin_work->pending) > 1)
6291 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6292 } else {
6293 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6294 }
6b95a207
KH		 6295 spin_unlock_irqrestore(&dev->event_lock, flags);
6296}
6297
8c9f3aaf
JB		 6298static int intel_gen2_queue_flip(struct drm_device *dev,
6299 struct drm_crtc *crtc,
6300 struct drm_framebuffer *fb,
6301 struct drm_i915_gem_object *obj)
6302{
6303 struct drm_i915_private *dev_priv = dev->dev_private;
6304 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6305 unsigned long offset;
6306 u32 flip_mask;
6307 int ret;
6308
6309 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6310 if (ret)
6311 goto out;
6312
6313 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6314 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6315
6316 ret = BEGIN_LP_RING(6);
6317 if (ret)
6318 goto out;
6319
6320 /* Can't queue multiple flips, so wait for the previous
6321 * one to finish before executing the next.
6322 */
6323 if (intel_crtc->plane)
6324 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6325 else
6326 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6327 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6328 OUT_RING(MI_NOOP);
6329 OUT_RING(MI_DISPLAY_FLIP |
6330 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6331 OUT_RING(fb->pitch);
6332 OUT_RING(obj->gtt_offset + offset);
6333 OUT_RING(MI_NOOP);
6334 ADVANCE_LP_RING();
6335out:
6336 return ret;
6337}
6338
6339static int intel_gen3_queue_flip(struct drm_device *dev,
6340 struct drm_crtc *crtc,
6341 struct drm_framebuffer *fb,
6342 struct drm_i915_gem_object *obj)
6343{
6344 struct drm_i915_private *dev_priv = dev->dev_private;
6345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6346 unsigned long offset;
6347 u32 flip_mask;
6348 int ret;
6349
6350 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6351 if (ret)
6352 goto out;
6353
6354 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6355 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6356
6357 ret = BEGIN_LP_RING(6);
6358 if (ret)
6359 goto out;
6360
6361 if (intel_crtc->plane)
6362 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6363 else
6364 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6365 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6366 OUT_RING(MI_NOOP);
6367 OUT_RING(MI_DISPLAY_FLIP_I915 |
6368 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6369 OUT_RING(fb->pitch);
6370 OUT_RING(obj->gtt_offset + offset);
6371 OUT_RING(MI_NOOP);
6372
6373 ADVANCE_LP_RING();
6374out:
6375 return ret;
6376}
6377
6378static int intel_gen4_queue_flip(struct drm_device *dev,
6379 struct drm_crtc *crtc,
6380 struct drm_framebuffer *fb,
6381 struct drm_i915_gem_object *obj)
6382{
6383 struct drm_i915_private *dev_priv = dev->dev_private;
6384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6385 uint32_t pf, pipesrc;
6386 int ret;
6387
6388 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6389 if (ret)
6390 goto out;
6391
6392 ret = BEGIN_LP_RING(4);
6393 if (ret)
6394 goto out;
6395
6396 /* i965+ uses the linear or tiled offsets from the
6397 * Display Registers (which do not change across a page-flip)
6398 * so we need only reprogram the base address.
6399 */
6400 OUT_RING(MI_DISPLAY_FLIP |
6401 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6402 OUT_RING(fb->pitch);
6403 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6404
6405 /* XXX Enabling the panel-fitter across page-flip is so far
6406 * untested on non-native modes, so ignore it for now.
6407 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6408 */
6409 pf = 0;
6410 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6411 OUT_RING(pf | pipesrc);
6412 ADVANCE_LP_RING();
6413out:
6414 return ret;
6415}
6416
6417static int intel_gen6_queue_flip(struct drm_device *dev,
6418 struct drm_crtc *crtc,
6419 struct drm_framebuffer *fb,
6420 struct drm_i915_gem_object *obj)
6421{
6422 struct drm_i915_private *dev_priv = dev->dev_private;
6423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6424 uint32_t pf, pipesrc;
6425 int ret;
6426
6427 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6428 if (ret)
6429 goto out;
6430
6431 ret = BEGIN_LP_RING(4);
6432 if (ret)
6433 goto out;
6434
6435 OUT_RING(MI_DISPLAY_FLIP |
6436 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6437 OUT_RING(fb->pitch | obj->tiling_mode);
6438 OUT_RING(obj->gtt_offset);
6439
6440 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6441 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6442 OUT_RING(pf | pipesrc);
6443 ADVANCE_LP_RING();
6444out:
6445 return ret;
6446}
6447
7c9017e5
JB		 6448/*
6449 * On gen7 we currently use the blit ring because (in early silicon at least)
6450 * the render ring doesn't give us interrpts for page flip completion, which
6451 * means clients will hang after the first flip is queued. Fortunately the
6452 * blit ring generates interrupts properly, so use it instead.
6453 */
6454static int intel_gen7_queue_flip(struct drm_device *dev,
6455 struct drm_crtc *crtc,
6456 struct drm_framebuffer *fb,
6457 struct drm_i915_gem_object *obj)
6458{
6459 struct drm_i915_private *dev_priv = dev->dev_private;
6460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6461 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6462 int ret;
6463
6464 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6465 if (ret)
6466 goto out;
6467
6468 ret = intel_ring_begin(ring, 4);
6469 if (ret)
6470 goto out;
6471
6472 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6473 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6474 intel_ring_emit(ring, (obj->gtt_offset));
6475 intel_ring_emit(ring, (MI_NOOP));
6476 intel_ring_advance(ring);
6477out:
6478 return ret;
6479}
6480
8c9f3aaf
JB		 6481static int intel_default_queue_flip(struct drm_device *dev,
6482 struct drm_crtc *crtc,
6483 struct drm_framebuffer *fb,
6484 struct drm_i915_gem_object *obj)
6485{
6486 return -ENODEV;
6487}
6488
6b95a207
KH		 6489static int intel_crtc_page_flip(struct drm_crtc *crtc,
6490 struct drm_framebuffer *fb,
6491 struct drm_pending_vblank_event *event)
6492{
6493 struct drm_device *dev = crtc->dev;
6494 struct drm_i915_private *dev_priv = dev->dev_private;
6495 struct intel_framebuffer *intel_fb;
05394f39 6496 struct drm_i915_gem_object *obj;
6b95a207
KH		 6497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6498 struct intel_unpin_work *work;
8c9f3aaf 6499 unsigned long flags;
52e68630 6500 int ret;
6b95a207
KH		 6501
6502 work = kzalloc(sizeof *work, GFP_KERNEL);
6503 if (work == NULL)
6504 return -ENOMEM;
6505
6b95a207
KH		 6506 work->event = event;
6507 work->dev = crtc->dev;
6508 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6509 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6510 INIT_WORK(&work->work, intel_unpin_work_fn);
6511
6512 /* We borrow the event spin lock for protecting unpin_work */
6513 spin_lock_irqsave(&dev->event_lock, flags);
6514 if (intel_crtc->unpin_work) {
6515 spin_unlock_irqrestore(&dev->event_lock, flags);
6516 kfree(work);
468f0b44
CW		 6517
6518 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6519 return -EBUSY;
6520 }
6521 intel_crtc->unpin_work = work;
6522 spin_unlock_irqrestore(&dev->event_lock, flags);
6523
6524 intel_fb = to_intel_framebuffer(fb);
6525 obj = intel_fb->obj;
6526
468f0b44 6527 mutex_lock(&dev->struct_mutex);
6b95a207 6528
75dfca80 6529 /* Reference the objects for the scheduled work. */
05394f39
CW		 6530 drm_gem_object_reference(&work->old_fb_obj->base);
6531 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6532
6533 crtc->fb = fb;
96b099fd
CW		 6534
6535 ret = drm_vblank_get(dev, intel_crtc->pipe);
6536 if (ret)
6537 goto cleanup_objs;
6538
e1f99ce6 6539 work->pending_flip_obj = obj;
e1f99ce6 6540
4e5359cd
SF		 6541 work->enable_stall_check = true;
6542
e1f99ce6
CW		 6543 /* Block clients from rendering to the new back buffer until
6544 * the flip occurs and the object is no longer visible.
6545 */
05394f39 6546 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6547
8c9f3aaf
JB		 6548 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6549 if (ret)
6550 goto cleanup_pending;
6b95a207
KH		 6551
6552 mutex_unlock(&dev->struct_mutex);
6553
e5510fac
JB		 6554 trace_i915_flip_request(intel_crtc->plane, obj);
6555
6b95a207 6556 return 0;
96b099fd 6557
8c9f3aaf
JB		 6558cleanup_pending:
6559 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
96b099fd 6560cleanup_objs:
05394f39
CW		 6561 drm_gem_object_unreference(&work->old_fb_obj->base);
6562 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6563 mutex_unlock(&dev->struct_mutex);
6564
6565 spin_lock_irqsave(&dev->event_lock, flags);
6566 intel_crtc->unpin_work = NULL;
6567 spin_unlock_irqrestore(&dev->event_lock, flags);
6568
6569 kfree(work);
6570
6571 return ret;
6b95a207
KH		 6572}
6573
47f1c6c9
CW		 6574static void intel_sanitize_modesetting(struct drm_device *dev,
6575 int pipe, int plane)
6576{
6577 struct drm_i915_private *dev_priv = dev->dev_private;
6578 u32 reg, val;
6579
6580 if (HAS_PCH_SPLIT(dev))
6581 return;
6582
6583 /* Who knows what state these registers were left in by the BIOS or
6584 * grub?
6585 *
6586 * If we leave the registers in a conflicting state (e.g. with the
6587 * display plane reading from the other pipe than the one we intend
6588 * to use) then when we attempt to teardown the active mode, we will
6589 * not disable the pipes and planes in the correct order -- leaving
6590 * a plane reading from a disabled pipe and possibly leading to
6591 * undefined behaviour.
6592 */
6593
6594 reg = DSPCNTR(plane);
6595 val = I915_READ(reg);
6596
6597 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6598 return;
6599 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6600 return;
6601
6602 /* This display plane is active and attached to the other CPU pipe. */
6603 pipe = !pipe;
6604
6605 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6606 intel_disable_plane(dev_priv, plane, pipe);
6607 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 6608}
79e53945 6609
f6e5b160
CW		 6610static void intel_crtc_reset(struct drm_crtc *crtc)
6611{
6612 struct drm_device *dev = crtc->dev;
6613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6614
6615 /* Reset flags back to the 'unknown' status so that they
6616 * will be correctly set on the initial modeset.
6617 */
6618 intel_crtc->dpms_mode = -1;
6619
6620 /* We need to fix up any BIOS configuration that conflicts with
6621 * our expectations.
6622 */
6623 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6624}
6625
6626static struct drm_crtc_helper_funcs intel_helper_funcs = {
6627 .dpms = intel_crtc_dpms,
6628 .mode_fixup = intel_crtc_mode_fixup,
6629 .mode_set = intel_crtc_mode_set,
6630 .mode_set_base = intel_pipe_set_base,
6631 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6632 .load_lut = intel_crtc_load_lut,
6633 .disable = intel_crtc_disable,
6634};
6635
6636static const struct drm_crtc_funcs intel_crtc_funcs = {
6637 .reset = intel_crtc_reset,
6638 .cursor_set = intel_crtc_cursor_set,
6639 .cursor_move = intel_crtc_cursor_move,
6640 .gamma_set = intel_crtc_gamma_set,
6641 .set_config = drm_crtc_helper_set_config,
6642 .destroy = intel_crtc_destroy,
6643 .page_flip = intel_crtc_page_flip,
6644};
6645
b358d0a6 6646static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 6647{
22fd0fab 6648 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 6649 struct intel_crtc *intel_crtc;
6650 int i;
6651
6652 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6653 if (intel_crtc == NULL)
6654 return;
6655
6656 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6657
6658 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 6659 for (i = 0; i < 256; i++) {
6660 intel_crtc->lut_r[i] = i;
6661 intel_crtc->lut_g[i] = i;
6662 intel_crtc->lut_b[i] = i;
6663 }
6664
80824003
JB		 6665 /* Swap pipes & planes for FBC on pre-965 */
6666 intel_crtc->pipe = pipe;
6667 intel_crtc->plane = pipe;
e2e767ab 6668 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 6669 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 6670 intel_crtc->plane = !pipe;
80824003
JB		 6671 }
6672
22fd0fab
JB		 6673 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6674 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6675 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6676 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6677
5d1d0cc8 6678 intel_crtc_reset(&intel_crtc->base);
04dbff52 6679 intel_crtc->active = true; /* force the pipe off on setup_init_config */
7e7d76c3
JB		 6680
6681 if (HAS_PCH_SPLIT(dev)) {
6682 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6683 intel_helper_funcs.commit = ironlake_crtc_commit;
6684 } else {
6685 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6686 intel_helper_funcs.commit = i9xx_crtc_commit;
6687 }
6688
79e53945
JB		 6689 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6690
652c393a
JB		 6691 intel_crtc->busy = false;
6692
6693 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6694 (unsigned long)intel_crtc);
79e53945
JB		 6695}
6696
08d7b3d1 6697int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 6698 struct drm_file *file)
08d7b3d1
CW		 6699{
6700 drm_i915_private_t *dev_priv = dev->dev_private;
6701 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 6702 struct drm_mode_object *drmmode_obj;
6703 struct intel_crtc *crtc;
08d7b3d1
CW		 6704
6705 if (!dev_priv) {
6706 DRM_ERROR("called with no initialization\n");
6707 return -EINVAL;
6708 }
6709
c05422d5
DV		 6710 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6711 DRM_MODE_OBJECT_CRTC);
08d7b3d1 6712
c05422d5 6713 if (!drmmode_obj) {
08d7b3d1
CW		 6714 DRM_ERROR("no such CRTC id\n");
6715 return -EINVAL;
6716 }
6717
c05422d5
DV		 6718 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6719 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 6720
c05422d5 6721 return 0;
08d7b3d1
CW		 6722}
6723
c5e4df33 6724static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 6725{
4ef69c7a 6726 struct intel_encoder *encoder;
79e53945 6727 int index_mask = 0;
79e53945
JB		 6728 int entry = 0;
6729
4ef69c7a
CW		 6730 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6731 if (type_mask & encoder->clone_mask)
79e53945
JB		 6732 index_mask |= (1 << entry);
6733 entry++;
6734 }
4ef69c7a 6735
79e53945
JB		 6736 return index_mask;
6737}
6738
4d302442
CW		 6739static bool has_edp_a(struct drm_device *dev)
6740{
6741 struct drm_i915_private *dev_priv = dev->dev_private;
6742
6743 if (!IS_MOBILE(dev))
6744 return false;
6745
6746 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6747 return false;
6748
6749 if (IS_GEN5(dev) &&
6750 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6751 return false;
6752
6753 return true;
6754}
6755
79e53945
JB		 6756static void intel_setup_outputs(struct drm_device *dev)
6757{
725e30ad 6758 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 6759 struct intel_encoder *encoder;
cb0953d7 6760 bool dpd_is_edp = false;
c5d1b51d 6761 bool has_lvds = false;
79e53945 6762
541998a1 6763 if (IS_MOBILE(dev) && !IS_I830(dev))
c5d1b51d
CW		 6764 has_lvds = intel_lvds_init(dev);
6765 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6766 /* disable the panel fitter on everything but LVDS */
6767 I915_WRITE(PFIT_CONTROL, 0);
6768 }
79e53945 6769
bad720ff 6770 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 6771 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 6772
4d302442 6773 if (has_edp_a(dev))
32f9d658
ZW		 6774 intel_dp_init(dev, DP_A);
6775
cb0953d7
AJ		 6776 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6777 intel_dp_init(dev, PCH_DP_D);
6778 }
6779
6780 intel_crt_init(dev);
6781
6782 if (HAS_PCH_SPLIT(dev)) {
6783 int found;
6784
30ad48b7 6785 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca
ZY		 6786 /* PCH SDVOB multiplex with HDMIB */
6787 found = intel_sdvo_init(dev, PCH_SDVOB);
30ad48b7
ZW		 6788 if (!found)
6789 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 6790 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6791 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 6792 }
6793
6794 if (I915_READ(HDMIC) & PORT_DETECTED)
6795 intel_hdmi_init(dev, HDMIC);
6796
6797 if (I915_READ(HDMID) & PORT_DETECTED)
6798 intel_hdmi_init(dev, HDMID);
6799
5eb08b69
ZW		 6800 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6801 intel_dp_init(dev, PCH_DP_C);
6802
cb0953d7 6803 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 6804 intel_dp_init(dev, PCH_DP_D);
6805
103a196f 6806 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 6807 bool found = false;
7d57382e 6808
725e30ad 6809 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 6810 DRM_DEBUG_KMS("probing SDVOB\n");
725e30ad 6811 found = intel_sdvo_init(dev, SDVOB);
b01f2c3a
JB		 6812 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6813 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 6814 intel_hdmi_init(dev, SDVOB);
b01f2c3a 6815 }
27185ae1 6816
b01f2c3a
JB		 6817 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6818 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 6819 intel_dp_init(dev, DP_B);
b01f2c3a 6820 }
725e30ad 6821 }
13520b05
KH		 6822
6823 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 6824
b01f2c3a
JB		 6825 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6826 DRM_DEBUG_KMS("probing SDVOC\n");
725e30ad 6827 found = intel_sdvo_init(dev, SDVOC);
b01f2c3a 6828 }
27185ae1
ML		 6829
6830 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6831
b01f2c3a
JB		 6832 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6833 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 6834 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 6835 }
6836 if (SUPPORTS_INTEGRATED_DP(dev)) {
6837 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 6838 intel_dp_init(dev, DP_C);
b01f2c3a 6839 }
725e30ad 6840 }
27185ae1 6841
b01f2c3a
JB		 6842 if (SUPPORTS_INTEGRATED_DP(dev) &&
6843 (I915_READ(DP_D) & DP_DETECTED)) {
6844 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 6845 intel_dp_init(dev, DP_D);
b01f2c3a 6846 }
bad720ff 6847 } else if (IS_GEN2(dev))
79e53945
JB		 6848 intel_dvo_init(dev);
6849
103a196f 6850 if (SUPPORTS_TV(dev))
79e53945
JB		 6851 intel_tv_init(dev);
6852
4ef69c7a
CW		 6853 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6854 encoder->base.possible_crtcs = encoder->crtc_mask;
6855 encoder->base.possible_clones =
6856 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 6857 }
47356eb6
CW		 6858
6859 intel_panel_setup_backlight(dev);
2c7111db
CW		 6860
6861 /* disable all the possible outputs/crtcs before entering KMS mode */
6862 drm_helper_disable_unused_functions(dev);
79e53945
JB		 6863}
6864
6865static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6866{
6867 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 6868
6869 drm_framebuffer_cleanup(fb);
05394f39 6870 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 6871
6872 kfree(intel_fb);
6873}
6874
6875static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 6876 struct drm_file *file,
79e53945
JB		 6877 unsigned int *handle)
6878{
6879 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 6880 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 6881
05394f39 6882 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 6883}
6884
6885static const struct drm_framebuffer_funcs intel_fb_funcs = {
6886 .destroy = intel_user_framebuffer_destroy,
6887 .create_handle = intel_user_framebuffer_create_handle,
6888};
6889
38651674
DA		 6890int intel_framebuffer_init(struct drm_device *dev,
6891 struct intel_framebuffer *intel_fb,
6892 struct drm_mode_fb_cmd *mode_cmd,
05394f39 6893 struct drm_i915_gem_object *obj)
79e53945 6894{
79e53945
JB		 6895 int ret;
6896
05394f39 6897 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 6898 return -EINVAL;
6899
6900 if (mode_cmd->pitch & 63)
6901 return -EINVAL;
6902
6903 switch (mode_cmd->bpp) {
6904 case 8:
6905 case 16:
6906 case 24:
6907 case 32:
6908 break;
6909 default:
6910 return -EINVAL;
6911 }
6912
79e53945
JB		 6913 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6914 if (ret) {
6915 DRM_ERROR("framebuffer init failed %d\n", ret);
6916 return ret;
6917 }
6918
6919 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 6920 intel_fb->obj = obj;
79e53945
JB		 6921 return 0;
6922}
6923
79e53945
JB		 6924static struct drm_framebuffer *
6925intel_user_framebuffer_create(struct drm_device *dev,
6926 struct drm_file *filp,
6927 struct drm_mode_fb_cmd *mode_cmd)
6928{
05394f39 6929 struct drm_i915_gem_object *obj;
79e53945 6930
05394f39 6931 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
c8725226 6932 if (&obj->base == NULL)
cce13ff7 6933 return ERR_PTR(-ENOENT);
79e53945 6934
d2dff872 6935 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 6936}
6937
79e53945 6938static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 6939 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 6940 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 6941};
6942
05394f39 6943static struct drm_i915_gem_object *
aa40d6bb 6944intel_alloc_context_page(struct drm_device *dev)
9ea8d059 6945{
05394f39 6946 struct drm_i915_gem_object *ctx;
9ea8d059
CW		 6947 int ret;
6948
2c34b850
BW		 6949 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
6950
aa40d6bb
ZN		 6951 ctx = i915_gem_alloc_object(dev, 4096);
6952 if (!ctx) {
9ea8d059
CW		 6953 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6954 return NULL;
6955 }
6956
75e9e915 6957 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW		 6958 if (ret) {
6959 DRM_ERROR("failed to pin power context: %d\n", ret);
6960 goto err_unref;
6961 }
6962
aa40d6bb 6963 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW		 6964 if (ret) {
6965 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6966 goto err_unpin;
6967 }
9ea8d059 6968
aa40d6bb 6969 return ctx;
9ea8d059
CW		 6970
6971err_unpin:
aa40d6bb 6972 i915_gem_object_unpin(ctx);
9ea8d059 6973err_unref:
05394f39 6974 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW		 6975 mutex_unlock(&dev->struct_mutex);
6976 return NULL;
6977}
6978
7648fa99
JB		 6979bool ironlake_set_drps(struct drm_device *dev, u8 val)
6980{
6981 struct drm_i915_private *dev_priv = dev->dev_private;
6982 u16 rgvswctl;
6983
6984 rgvswctl = I915_READ16(MEMSWCTL);
6985 if (rgvswctl & MEMCTL_CMD_STS) {
6986 DRM_DEBUG("gpu busy, RCS change rejected\n");
6987 return false; /* still busy with another command */
6988 }
6989
6990 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6991 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6992 I915_WRITE16(MEMSWCTL, rgvswctl);
6993 POSTING_READ16(MEMSWCTL);
6994
6995 rgvswctl |= MEMCTL_CMD_STS;
6996 I915_WRITE16(MEMSWCTL, rgvswctl);
6997
6998 return true;
6999}
7000
f97108d1
JB		 7001void ironlake_enable_drps(struct drm_device *dev)
7002{
7003 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7004 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 7005 u8 fmax, fmin, fstart, vstart;
f97108d1 7006
ea056c14
JB		 7007 /* Enable temp reporting */
7008 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7009 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7010
f97108d1
JB		 7011 /* 100ms RC evaluation intervals */
7012 I915_WRITE(RCUPEI, 100000);
7013 I915_WRITE(RCDNEI, 100000);
7014
7015 /* Set max/min thresholds to 90ms and 80ms respectively */
7016 I915_WRITE(RCBMAXAVG, 90000);
7017 I915_WRITE(RCBMINAVG, 80000);
7018
7019 I915_WRITE(MEMIHYST, 1);
7020
7021 /* Set up min, max, and cur for interrupt handling */
7022 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7023 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7024 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7025 MEMMODE_FSTART_SHIFT;
7648fa99 7026
f97108d1
JB		 7027 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7028 PXVFREQ_PX_SHIFT;
7029
80dbf4b7 7030 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB		 7031 dev_priv->fstart = fstart;
7032
80dbf4b7 7033 dev_priv->max_delay = fstart;
f97108d1
JB		 7034 dev_priv->min_delay = fmin;
7035 dev_priv->cur_delay = fstart;
7036
80dbf4b7
JB		 7037 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7038 fmax, fmin, fstart);
7648fa99 7039
f97108d1
JB		 7040 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7041
7042 /*
7043 * Interrupts will be enabled in ironlake_irq_postinstall
7044 */
7045
7046 I915_WRITE(VIDSTART, vstart);
7047 POSTING_READ(VIDSTART);
7048
7049 rgvmodectl |= MEMMODE_SWMODE_EN;
7050 I915_WRITE(MEMMODECTL, rgvmodectl);
7051
481b6af3 7052 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 7053 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB		 7054 msleep(1);
7055
7648fa99 7056 ironlake_set_drps(dev, fstart);
f97108d1 7057
7648fa99
JB		 7058 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7059 I915_READ(0x112e0);
7060 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7061 dev_priv->last_count2 = I915_READ(0x112f4);
7062 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB		 7063}
7064
7065void ironlake_disable_drps(struct drm_device *dev)
7066{
7067 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7068 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB		 7069
7070 /* Ack interrupts, disable EFC interrupt */
7071 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7072 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7073 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7074 I915_WRITE(DEIIR, DE_PCU_EVENT);
7075 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7076
7077 /* Go back to the starting frequency */
7648fa99 7078 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB		 7079 msleep(1);
7080 rgvswctl |= MEMCTL_CMD_STS;
7081 I915_WRITE(MEMSWCTL, rgvswctl);
7082 msleep(1);
7083
7084}
7085
3b8d8d91
JB		 7086void gen6_set_rps(struct drm_device *dev, u8 val)
7087{
7088 struct drm_i915_private *dev_priv = dev->dev_private;
7089 u32 swreq;
7090
7091 swreq = (val & 0x3ff) << 25;
7092 I915_WRITE(GEN6_RPNSWREQ, swreq);
7093}
7094
7095void gen6_disable_rps(struct drm_device *dev)
7096{
7097 struct drm_i915_private *dev_priv = dev->dev_private;
7098
7099 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7100 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7101 I915_WRITE(GEN6_PMIER, 0);
4912d041
BW		 7102
7103 spin_lock_irq(&dev_priv->rps_lock);
7104 dev_priv->pm_iir = 0;
7105 spin_unlock_irq(&dev_priv->rps_lock);
7106
3b8d8d91
JB		 7107 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7108}
7109
7648fa99
JB		 7110static unsigned long intel_pxfreq(u32 vidfreq)
7111{
7112 unsigned long freq;
7113 int div = (vidfreq & 0x3f0000) >> 16;
7114 int post = (vidfreq & 0x3000) >> 12;
7115 int pre = (vidfreq & 0x7);
7116
7117 if (!pre)
7118 return 0;
7119
7120 freq = ((div * 133333) / ((1<<post) * pre));
7121
7122 return freq;
7123}
7124
7125void intel_init_emon(struct drm_device *dev)
7126{
7127 struct drm_i915_private *dev_priv = dev->dev_private;
7128 u32 lcfuse;
7129 u8 pxw[16];
7130 int i;
7131
7132 /* Disable to program */
7133 I915_WRITE(ECR, 0);
7134 POSTING_READ(ECR);
7135
7136 /* Program energy weights for various events */
7137 I915_WRITE(SDEW, 0x15040d00);
7138 I915_WRITE(CSIEW0, 0x007f0000);
7139 I915_WRITE(CSIEW1, 0x1e220004);
7140 I915_WRITE(CSIEW2, 0x04000004);
7141
7142 for (i = 0; i < 5; i++)
7143 I915_WRITE(PEW + (i * 4), 0);
7144 for (i = 0; i < 3; i++)
7145 I915_WRITE(DEW + (i * 4), 0);
7146
7147 /* Program P-state weights to account for frequency power adjustment */
7148 for (i = 0; i < 16; i++) {
7149 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7150 unsigned long freq = intel_pxfreq(pxvidfreq);
7151 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7152 PXVFREQ_PX_SHIFT;
7153 unsigned long val;
7154
7155 val = vid * vid;
7156 val *= (freq / 1000);
7157 val *= 255;
7158 val /= (127*127*900);
7159 if (val > 0xff)
7160 DRM_ERROR("bad pxval: %ld\n", val);
7161 pxw[i] = val;
7162 }
7163 /* Render standby states get 0 weight */
7164 pxw[14] = 0;
7165 pxw[15] = 0;
7166
7167 for (i = 0; i < 4; i++) {
7168 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7169 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7170 I915_WRITE(PXW + (i * 4), val);
7171 }
7172
7173 /* Adjust magic regs to magic values (more experimental results) */
7174 I915_WRITE(OGW0, 0);
7175 I915_WRITE(OGW1, 0);
7176 I915_WRITE(EG0, 0x00007f00);
7177 I915_WRITE(EG1, 0x0000000e);
7178 I915_WRITE(EG2, 0x000e0000);
7179 I915_WRITE(EG3, 0x68000300);
7180 I915_WRITE(EG4, 0x42000000);
7181 I915_WRITE(EG5, 0x00140031);
7182 I915_WRITE(EG6, 0);
7183 I915_WRITE(EG7, 0);
7184
7185 for (i = 0; i < 8; i++)
7186 I915_WRITE(PXWL + (i * 4), 0);
7187
7188 /* Enable PMON + select events */
7189 I915_WRITE(ECR, 0x80000019);
7190
7191 lcfuse = I915_READ(LCFUSE02);
7192
7193 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7194}
7195
3b8d8d91 7196void gen6_enable_rps(struct drm_i915_private *dev_priv)
8fd26859 7197{
a6044e23
JB		 7198 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7199 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7df8721b 7200 u32 pcu_mbox, rc6_mask = 0;
a6044e23 7201 int cur_freq, min_freq, max_freq;
8fd26859
CW		 7202 int i;
7203
7204 /* Here begins a magic sequence of register writes to enable
7205 * auto-downclocking.
7206 *
7207 * Perhaps there might be some value in exposing these to
7208 * userspace...
7209 */
7210 I915_WRITE(GEN6_RC_STATE, 0);
d1ebd816 7211 mutex_lock(&dev_priv->dev->struct_mutex);
fcca7926 7212 gen6_gt_force_wake_get(dev_priv);
8fd26859 7213
3b8d8d91 7214 /* disable the counters and set deterministic thresholds */
8fd26859
CW		 7215 I915_WRITE(GEN6_RC_CONTROL, 0);
7216
7217 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7218 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7219 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7220 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7221 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7222
7223 for (i = 0; i < I915_NUM_RINGS; i++)
7224 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7225
7226 I915_WRITE(GEN6_RC_SLEEP, 0);
7227 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7228 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7229 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7230 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7231
7df8721b
JB		 7232 if (i915_enable_rc6)
7233 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7234 GEN6_RC_CTL_RC6_ENABLE;
7235
8fd26859 7236 I915_WRITE(GEN6_RC_CONTROL,
7df8721b 7237 rc6_mask |
9c3d2f7f 7238 GEN6_RC_CTL_EI_MODE(1) |
8fd26859
CW		 7239 GEN6_RC_CTL_HW_ENABLE);
7240
3b8d8d91 7241 I915_WRITE(GEN6_RPNSWREQ,
8fd26859
CW		 7242 GEN6_FREQUENCY(10) |
7243 GEN6_OFFSET(0) |
7244 GEN6_AGGRESSIVE_TURBO);
7245 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7246 GEN6_FREQUENCY(12));
7247
7248 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7249 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7250 18 << 24 |
7251 6 << 16);
ccab5c82
JB		 7252 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7253 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8fd26859 7254 I915_WRITE(GEN6_RP_UP_EI, 100000);
ccab5c82 7255 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8fd26859
CW		 7256 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7257 I915_WRITE(GEN6_RP_CONTROL,
7258 GEN6_RP_MEDIA_TURBO |
7259 GEN6_RP_USE_NORMAL_FREQ |
7260 GEN6_RP_MEDIA_IS_GFX |
7261 GEN6_RP_ENABLE |
ccab5c82
JB		 7262 GEN6_RP_UP_BUSY_AVG |
7263 GEN6_RP_DOWN_IDLE_CONT);
8fd26859
CW		 7264
7265 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7266 500))
7267 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7268
7269 I915_WRITE(GEN6_PCODE_DATA, 0);
7270 I915_WRITE(GEN6_PCODE_MAILBOX,
7271 GEN6_PCODE_READY |
7272 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7273 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7274 500))
7275 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7276
a6044e23
JB		 7277 min_freq = (rp_state_cap & 0xff0000) >> 16;
7278 max_freq = rp_state_cap & 0xff;
7279 cur_freq = (gt_perf_status & 0xff00) >> 8;
7280
7281 /* Check for overclock support */
7282 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7283 500))
7284 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7285 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7286 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7287 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7288 500))
7289 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7290 if (pcu_mbox & (1<<31)) { /* OC supported */
7291 max_freq = pcu_mbox & 0xff;
e281fcaa 7292 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
a6044e23
JB		 7293 }
7294
7295 /* In units of 100MHz */
7296 dev_priv->max_delay = max_freq;
7297 dev_priv->min_delay = min_freq;
7298 dev_priv->cur_delay = cur_freq;
7299
8fd26859
CW		 7300 /* requires MSI enabled */
7301 I915_WRITE(GEN6_PMIER,
7302 GEN6_PM_MBOX_EVENT |
7303 GEN6_PM_THERMAL_EVENT |
7304 GEN6_PM_RP_DOWN_TIMEOUT |
7305 GEN6_PM_RP_UP_THRESHOLD |
7306 GEN6_PM_RP_DOWN_THRESHOLD |
7307 GEN6_PM_RP_UP_EI_EXPIRED |
7308 GEN6_PM_RP_DOWN_EI_EXPIRED);
4912d041
BW		 7309 spin_lock_irq(&dev_priv->rps_lock);
7310 WARN_ON(dev_priv->pm_iir != 0);
3b8d8d91 7311 I915_WRITE(GEN6_PMIMR, 0);
4912d041 7312 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91
JB		 7313 /* enable all PM interrupts */
7314 I915_WRITE(GEN6_PMINTRMSK, 0);
8fd26859 7315
fcca7926 7316 gen6_gt_force_wake_put(dev_priv);
d1ebd816 7317 mutex_unlock(&dev_priv->dev->struct_mutex);
8fd26859
CW		 7318}
7319
6067aaea
JB		 7320static void ironlake_init_clock_gating(struct drm_device *dev)
7321{
7322 struct drm_i915_private *dev_priv = dev->dev_private;
7323 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7324
7325 /* Required for FBC */
7326 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7327 DPFCRUNIT_CLOCK_GATE_DISABLE |
7328 DPFDUNIT_CLOCK_GATE_DISABLE;
7329 /* Required for CxSR */
7330 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7331
7332 I915_WRITE(PCH_3DCGDIS0,
7333 MARIUNIT_CLOCK_GATE_DISABLE |
7334 SVSMUNIT_CLOCK_GATE_DISABLE);
7335 I915_WRITE(PCH_3DCGDIS1,
7336 VFMUNIT_CLOCK_GATE_DISABLE);
7337
7338 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7339
6067aaea
JB		 7340 /*
7341 * According to the spec the following bits should be set in
7342 * order to enable memory self-refresh
7343 * The bit 22/21 of 0x42004
7344 * The bit 5 of 0x42020
7345 * The bit 15 of 0x45000
7346 */
7347 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7348 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7349 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7350 I915_WRITE(ILK_DSPCLK_GATE,
7351 (I915_READ(ILK_DSPCLK_GATE) |
7352 ILK_DPARB_CLK_GATE));
7353 I915_WRITE(DISP_ARB_CTL,
7354 (I915_READ(DISP_ARB_CTL) |
7355 DISP_FBC_WM_DIS));
7356 I915_WRITE(WM3_LP_ILK, 0);
7357 I915_WRITE(WM2_LP_ILK, 0);
7358 I915_WRITE(WM1_LP_ILK, 0);
7359
7360 /*
7361 * Based on the document from hardware guys the following bits
7362 * should be set unconditionally in order to enable FBC.
7363 * The bit 22 of 0x42000
7364 * The bit 22 of 0x42004
7365 * The bit 7,8,9 of 0x42020.
7366 */
7367 if (IS_IRONLAKE_M(dev)) {
7368 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7369 I915_READ(ILK_DISPLAY_CHICKEN1) |
7370 ILK_FBCQ_DIS);
7371 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7372 I915_READ(ILK_DISPLAY_CHICKEN2) |
7373 ILK_DPARB_GATE);
7374 I915_WRITE(ILK_DSPCLK_GATE,
7375 I915_READ(ILK_DSPCLK_GATE) |
7376 ILK_DPFC_DIS1 |
7377 ILK_DPFC_DIS2 |
7378 ILK_CLK_FBC);
7379 }
7380
7381 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7382 I915_READ(ILK_DISPLAY_CHICKEN2) |
7383 ILK_ELPIN_409_SELECT);
7384 I915_WRITE(_3D_CHICKEN2,
7385 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7386 _3D_CHICKEN2_WM_READ_PIPELINED);
8fd26859
CW		 7387}
7388
6067aaea 7389static void gen6_init_clock_gating(struct drm_device *dev)
652c393a
JB		 7390{
7391 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 7392 int pipe;
6067aaea
JB		 7393 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7394
7395 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
652c393a 7396
6067aaea
JB		 7397 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7398 I915_READ(ILK_DISPLAY_CHICKEN2) |
7399 ILK_ELPIN_409_SELECT);
8956c8bb 7400
6067aaea
JB		 7401 I915_WRITE(WM3_LP_ILK, 0);
7402 I915_WRITE(WM2_LP_ILK, 0);
7403 I915_WRITE(WM1_LP_ILK, 0);
652c393a
JB		 7404
7405 /*
6067aaea
JB		 7406 * According to the spec the following bits should be
7407 * set in order to enable memory self-refresh and fbc:
7408 * The bit21 and bit22 of 0x42000
7409 * The bit21 and bit22 of 0x42004
7410 * The bit5 and bit7 of 0x42020
7411 * The bit14 of 0x70180
7412 * The bit14 of 0x71180
652c393a 7413 */
6067aaea
JB		 7414 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7415 I915_READ(ILK_DISPLAY_CHICKEN1) |
7416 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7417 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7418 I915_READ(ILK_DISPLAY_CHICKEN2) |
7419 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7420 I915_WRITE(ILK_DSPCLK_GATE,
7421 I915_READ(ILK_DSPCLK_GATE) |
7422 ILK_DPARB_CLK_GATE |
7423 ILK_DPFD_CLK_GATE);
8956c8bb 7424
d74362c9 7425 for_each_pipe(pipe) {
6067aaea
JB		 7426 I915_WRITE(DSPCNTR(pipe),
7427 I915_READ(DSPCNTR(pipe)) |
7428 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 7429 intel_flush_display_plane(dev_priv, pipe);
7430 }
6067aaea 7431}
8956c8bb 7432
28963a3e
JB		 7433static void ivybridge_init_clock_gating(struct drm_device *dev)
7434{
7435 struct drm_i915_private *dev_priv = dev->dev_private;
7436 int pipe;
7437 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7f8a8569 7438
28963a3e 7439 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
382b0936 7440
28963a3e
JB		 7441 I915_WRITE(WM3_LP_ILK, 0);
7442 I915_WRITE(WM2_LP_ILK, 0);
7443 I915_WRITE(WM1_LP_ILK, 0);
de6e2eaf 7444
28963a3e 7445 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
67e92af0 7446
d74362c9 7447 for_each_pipe(pipe) {
28963a3e
JB		 7448 I915_WRITE(DSPCNTR(pipe),
7449 I915_READ(DSPCNTR(pipe)) |
7450 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 7451 intel_flush_display_plane(dev_priv, pipe);
7452 }
28963a3e
JB		 7453}
7454
6067aaea
JB		 7455static void g4x_init_clock_gating(struct drm_device *dev)
7456{
7457 struct drm_i915_private *dev_priv = dev->dev_private;
7458 uint32_t dspclk_gate;
8fd26859 7459
6067aaea
JB		 7460 I915_WRITE(RENCLK_GATE_D1, 0);
7461 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7462 GS_UNIT_CLOCK_GATE_DISABLE |
7463 CL_UNIT_CLOCK_GATE_DISABLE);
7464 I915_WRITE(RAMCLK_GATE_D, 0);
7465 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7466 OVRUNIT_CLOCK_GATE_DISABLE |
7467 OVCUNIT_CLOCK_GATE_DISABLE;
7468 if (IS_GM45(dev))
7469 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7470 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7471}
1398261a 7472
6067aaea
JB		 7473static void crestline_init_clock_gating(struct drm_device *dev)
7474{
7475 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7476
6067aaea
JB		 7477 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7478 I915_WRITE(RENCLK_GATE_D2, 0);
7479 I915_WRITE(DSPCLK_GATE_D, 0);
7480 I915_WRITE(RAMCLK_GATE_D, 0);
7481 I915_WRITE16(DEUC, 0);
7482}
652c393a 7483
6067aaea
JB		 7484static void broadwater_init_clock_gating(struct drm_device *dev)
7485{
7486 struct drm_i915_private *dev_priv = dev->dev_private;
7487
7488 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7489 I965_RCC_CLOCK_GATE_DISABLE |
7490 I965_RCPB_CLOCK_GATE_DISABLE |
7491 I965_ISC_CLOCK_GATE_DISABLE |
7492 I965_FBC_CLOCK_GATE_DISABLE);
7493 I915_WRITE(RENCLK_GATE_D2, 0);
7494}
7495
7496static void gen3_init_clock_gating(struct drm_device *dev)
7497{
7498 struct drm_i915_private *dev_priv = dev->dev_private;
7499 u32 dstate = I915_READ(D_STATE);
7500
7501 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7502 DSTATE_DOT_CLOCK_GATING;
7503 I915_WRITE(D_STATE, dstate);
7504}
7505
7506static void i85x_init_clock_gating(struct drm_device *dev)
7507{
7508 struct drm_i915_private *dev_priv = dev->dev_private;
7509
7510 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7511}
7512
7513static void i830_init_clock_gating(struct drm_device *dev)
7514{
7515 struct drm_i915_private *dev_priv = dev->dev_private;
7516
7517 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
652c393a
JB		 7518}
7519
645c62a5
JB		 7520static void ibx_init_clock_gating(struct drm_device *dev)
7521{
7522 struct drm_i915_private *dev_priv = dev->dev_private;
7523
7524 /*
7525 * On Ibex Peak and Cougar Point, we need to disable clock
7526 * gating for the panel power sequencer or it will fail to
7527 * start up when no ports are active.
7528 */
7529 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7530}
7531
7532static void cpt_init_clock_gating(struct drm_device *dev)
7533{
7534 struct drm_i915_private *dev_priv = dev->dev_private;
3bcf603f 7535 int pipe;
645c62a5
JB		 7536
7537 /*
7538 * On Ibex Peak and Cougar Point, we need to disable clock
7539 * gating for the panel power sequencer or it will fail to
7540 * start up when no ports are active.
7541 */
7542 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7543 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7544 DPLS_EDP_PPS_FIX_DIS);
3bcf603f
JB		 7545 /* Without this, mode sets may fail silently on FDI */
7546 for_each_pipe(pipe)
7547 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
652c393a
JB		 7548}
7549
ac668088 7550static void ironlake_teardown_rc6(struct drm_device *dev)
0cdab21f
CW		 7551{
7552 struct drm_i915_private *dev_priv = dev->dev_private;
7553
7554 if (dev_priv->renderctx) {
ac668088
CW		 7555 i915_gem_object_unpin(dev_priv->renderctx);
7556 drm_gem_object_unreference(&dev_priv->renderctx->base);
0cdab21f
CW		 7557 dev_priv->renderctx = NULL;
7558 }
7559
7560 if (dev_priv->pwrctx) {
ac668088
CW		 7561 i915_gem_object_unpin(dev_priv->pwrctx);
7562 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7563 dev_priv->pwrctx = NULL;
7564 }
7565}
7566
7567static void ironlake_disable_rc6(struct drm_device *dev)
7568{
7569 struct drm_i915_private *dev_priv = dev->dev_private;
7570
7571 if (I915_READ(PWRCTXA)) {
7572 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7573 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7574 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7575 50);
0cdab21f
CW		 7576
7577 I915_WRITE(PWRCTXA, 0);
7578 POSTING_READ(PWRCTXA);
7579
ac668088
CW		 7580 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7581 POSTING_READ(RSTDBYCTL);
0cdab21f 7582 }
ac668088 7583
99507307 7584 ironlake_teardown_rc6(dev);
0cdab21f
CW		 7585}
7586
ac668088 7587static int ironlake_setup_rc6(struct drm_device *dev)
d5bb081b
JB		 7588{
7589 struct drm_i915_private *dev_priv = dev->dev_private;
7590
ac668088
CW		 7591 if (dev_priv->renderctx == NULL)
7592 dev_priv->renderctx = intel_alloc_context_page(dev);
7593 if (!dev_priv->renderctx)
7594 return -ENOMEM;
7595
7596 if (dev_priv->pwrctx == NULL)
7597 dev_priv->pwrctx = intel_alloc_context_page(dev);
7598 if (!dev_priv->pwrctx) {
7599 ironlake_teardown_rc6(dev);
7600 return -ENOMEM;
7601 }
7602
7603 return 0;
d5bb081b
JB		 7604}
7605
7606void ironlake_enable_rc6(struct drm_device *dev)
7607{
7608 struct drm_i915_private *dev_priv = dev->dev_private;
7609 int ret;
7610
ac668088
CW		 7611 /* rc6 disabled by default due to repeated reports of hanging during
7612 * boot and resume.
7613 */
7614 if (!i915_enable_rc6)
7615 return;
7616
2c34b850 7617 mutex_lock(&dev->struct_mutex);
ac668088 7618 ret = ironlake_setup_rc6(dev);
2c34b850
BW		 7619 if (ret) {
7620 mutex_unlock(&dev->struct_mutex);
ac668088 7621 return;
2c34b850 7622 }
ac668088 7623
d5bb081b
JB		 7624 /*
7625 * GPU can automatically power down the render unit if given a page
7626 * to save state.
7627 */
7628 ret = BEGIN_LP_RING(6);
7629 if (ret) {
ac668088 7630 ironlake_teardown_rc6(dev);
2c34b850 7631 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 7632 return;
7633 }
ac668088 7634
d5bb081b
JB		 7635 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7636 OUT_RING(MI_SET_CONTEXT);
7637 OUT_RING(dev_priv->renderctx->gtt_offset |
7638 MI_MM_SPACE_GTT |
7639 MI_SAVE_EXT_STATE_EN |
7640 MI_RESTORE_EXT_STATE_EN |
7641 MI_RESTORE_INHIBIT);
7642 OUT_RING(MI_SUSPEND_FLUSH);
7643 OUT_RING(MI_NOOP);
7644 OUT_RING(MI_FLUSH);
7645 ADVANCE_LP_RING();
7646
4a246cfc
BW		 7647 /*
7648 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
7649 * does an implicit flush, combined with MI_FLUSH above, it should be
7650 * safe to assume that renderctx is valid
7651 */
7652 ret = intel_wait_ring_idle(LP_RING(dev_priv));
7653 if (ret) {
7654 DRM_ERROR("failed to enable ironlake power power savings\n");
7655 ironlake_teardown_rc6(dev);
7656 mutex_unlock(&dev->struct_mutex);
7657 return;
7658 }
7659
d5bb081b
JB		 7660 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7661 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2c34b850 7662 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 7663}
7664
645c62a5
JB		 7665void intel_init_clock_gating(struct drm_device *dev)
7666{
7667 struct drm_i915_private *dev_priv = dev->dev_private;
7668
7669 dev_priv->display.init_clock_gating(dev);
7670
7671 if (dev_priv->display.init_pch_clock_gating)
7672 dev_priv->display.init_pch_clock_gating(dev);
7673}
ac668088 7674
e70236a8
JB		 7675/* Set up chip specific display functions */
7676static void intel_init_display(struct drm_device *dev)
7677{
7678 struct drm_i915_private *dev_priv = dev->dev_private;
7679
7680 /* We always want a DPMS function */
f564048e 7681 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 7682 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e
EA		 7683 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7684 } else {
e70236a8 7685 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e
EA		 7686 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7687 }
e70236a8 7688
ee5382ae 7689 if (I915_HAS_FBC(dev)) {
9c04f015 7690 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 7691 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7692 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7693 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7694 } else if (IS_GM45(dev)) {
74dff282
JB		 7695 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7696 dev_priv->display.enable_fbc = g4x_enable_fbc;
7697 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 7698 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 7699 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7700 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7701 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7702 }
74dff282 7703 /* 855GM needs testing */
e70236a8
JB		 7704 }
7705
7706 /* Returns the core display clock speed */
f2b115e6 7707 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
e70236a8
JB		 7708 dev_priv->display.get_display_clock_speed =
7709 i945_get_display_clock_speed;
7710 else if (IS_I915G(dev))
7711 dev_priv->display.get_display_clock_speed =
7712 i915_get_display_clock_speed;
f2b115e6 7713 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 7714 dev_priv->display.get_display_clock_speed =
7715 i9xx_misc_get_display_clock_speed;
7716 else if (IS_I915GM(dev))
7717 dev_priv->display.get_display_clock_speed =
7718 i915gm_get_display_clock_speed;
7719 else if (IS_I865G(dev))
7720 dev_priv->display.get_display_clock_speed =
7721 i865_get_display_clock_speed;
f0f8a9ce 7722 else if (IS_I85X(dev))
e70236a8
JB		 7723 dev_priv->display.get_display_clock_speed =
7724 i855_get_display_clock_speed;
7725 else /* 852, 830 */
7726 dev_priv->display.get_display_clock_speed =
7727 i830_get_display_clock_speed;
7728
7729 /* For FIFO watermark updates */
7f8a8569 7730 if (HAS_PCH_SPLIT(dev)) {
645c62a5
JB		 7731 if (HAS_PCH_IBX(dev))
7732 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
7733 else if (HAS_PCH_CPT(dev))
7734 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
7735
f00a3ddf 7736 if (IS_GEN5(dev)) {
7f8a8569
ZW		 7737 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7738 dev_priv->display.update_wm = ironlake_update_wm;
7739 else {
7740 DRM_DEBUG_KMS("Failed to get proper latency. "
7741 "Disable CxSR\n");
7742 dev_priv->display.update_wm = NULL;
1398261a 7743 }
674cf967 7744 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6067aaea 7745 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
1398261a
YL		 7746 } else if (IS_GEN6(dev)) {
7747 if (SNB_READ_WM0_LATENCY()) {
7748 dev_priv->display.update_wm = sandybridge_update_wm;
7749 } else {
7750 DRM_DEBUG_KMS("Failed to read display plane latency. "
7751 "Disable CxSR\n");
7752 dev_priv->display.update_wm = NULL;
7f8a8569 7753 }
674cf967 7754 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6067aaea 7755 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
357555c0
JB		 7756 } else if (IS_IVYBRIDGE(dev)) {
7757 /* FIXME: detect B0+ stepping and use auto training */
7758 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
fe100d4d
JB		 7759 if (SNB_READ_WM0_LATENCY()) {
7760 dev_priv->display.update_wm = sandybridge_update_wm;
7761 } else {
7762 DRM_DEBUG_KMS("Failed to read display plane latency. "
7763 "Disable CxSR\n");
7764 dev_priv->display.update_wm = NULL;
7765 }
28963a3e 7766 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6067aaea 7767
7f8a8569
ZW		 7768 } else
7769 dev_priv->display.update_wm = NULL;
7770 } else if (IS_PINEVIEW(dev)) {
d4294342 7771 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 7772 dev_priv->is_ddr3,
d4294342
ZY		 7773 dev_priv->fsb_freq,
7774 dev_priv->mem_freq)) {
7775 DRM_INFO("failed to find known CxSR latency "
95534263 7776 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 7777 "disabling CxSR\n",
95534263 7778 (dev_priv->is_ddr3 == 1) ? "3": "2",
d4294342
ZY		 7779 dev_priv->fsb_freq, dev_priv->mem_freq);
7780 /* Disable CxSR and never update its watermark again */
7781 pineview_disable_cxsr(dev);
7782 dev_priv->display.update_wm = NULL;
7783 } else
7784 dev_priv->display.update_wm = pineview_update_wm;
95e0ee92 7785 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6067aaea 7786 } else if (IS_G4X(dev)) {
e70236a8 7787 dev_priv->display.update_wm = g4x_update_wm;
6067aaea
JB		 7788 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7789 } else if (IS_GEN4(dev)) {
e70236a8 7790 dev_priv->display.update_wm = i965_update_wm;
6067aaea
JB		 7791 if (IS_CRESTLINE(dev))
7792 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7793 else if (IS_BROADWATER(dev))
7794 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7795 } else if (IS_GEN3(dev)) {
e70236a8
JB		 7796 dev_priv->display.update_wm = i9xx_update_wm;
7797 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6067aaea
JB		 7798 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7799 } else if (IS_I865G(dev)) {
7800 dev_priv->display.update_wm = i830_update_wm;
7801 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7802 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8f4695ed
AJ		 7803 } else if (IS_I85X(dev)) {
7804 dev_priv->display.update_wm = i9xx_update_wm;
7805 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6067aaea 7806 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
e70236a8 7807 } else {
8f4695ed 7808 dev_priv->display.update_wm = i830_update_wm;
6067aaea 7809 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8f4695ed 7810 if (IS_845G(dev))
e70236a8
JB		 7811 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7812 else
7813 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8 7814 }
8c9f3aaf
JB		 7815
7816 /* Default just returns -ENODEV to indicate unsupported */
7817 dev_priv->display.queue_flip = intel_default_queue_flip;
7818
7819 switch (INTEL_INFO(dev)->gen) {
7820 case 2:
7821 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7822 break;
7823
7824 case 3:
7825 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7826 break;
7827
7828 case 4:
7829 case 5:
7830 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7831 break;
7832
7833 case 6:
7834 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7835 break;
7c9017e5
JB		 7836 case 7:
7837 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7838 break;
8c9f3aaf 7839 }
e70236a8
JB		 7840}
7841
b690e96c
JB		 7842/*
7843 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7844 * resume, or other times. This quirk makes sure that's the case for
7845 * affected systems.
7846 */
7847static void quirk_pipea_force (struct drm_device *dev)
7848{
7849 struct drm_i915_private *dev_priv = dev->dev_private;
7850
7851 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7852 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7853}
7854
435793df
KP		 7855/*
7856 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7857 */
7858static void quirk_ssc_force_disable(struct drm_device *dev)
7859{
7860 struct drm_i915_private *dev_priv = dev->dev_private;
7861 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
7862}
7863
b690e96c
JB		 7864struct intel_quirk {
7865 int device;
7866 int subsystem_vendor;
7867 int subsystem_device;
7868 void (*hook)(struct drm_device *dev);
7869};
7870
7871struct intel_quirk intel_quirks[] = {
7872 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7873 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
7874 /* HP Mini needs pipe A force quirk (LP: #322104) */
7875 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
7876
7877 /* Thinkpad R31 needs pipe A force quirk */
7878 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7879 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7880 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7881
7882 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7883 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
7884 /* ThinkPad X40 needs pipe A force quirk */
7885
7886 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7887 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7888
7889 /* 855 & before need to leave pipe A & dpll A up */
7890 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7891 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 7892
7893 /* Lenovo U160 cannot use SSC on LVDS */
7894 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 7895
7896 /* Sony Vaio Y cannot use SSC on LVDS */
7897 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
b690e96c
JB		 7898};
7899
7900static void intel_init_quirks(struct drm_device *dev)
7901{
7902 struct pci_dev *d = dev->pdev;
7903 int i;
7904
7905 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7906 struct intel_quirk *q = &intel_quirks[i];
7907
7908 if (d->device == q->device &&
7909 (d->subsystem_vendor == q->subsystem_vendor ||
7910 q->subsystem_vendor == PCI_ANY_ID) &&
7911 (d->subsystem_device == q->subsystem_device ||
7912 q->subsystem_device == PCI_ANY_ID))
7913 q->hook(dev);
7914 }
7915}
7916
9cce37f4
JB		 7917/* Disable the VGA plane that we never use */
7918static void i915_disable_vga(struct drm_device *dev)
7919{
7920 struct drm_i915_private *dev_priv = dev->dev_private;
7921 u8 sr1;
7922 u32 vga_reg;
7923
7924 if (HAS_PCH_SPLIT(dev))
7925 vga_reg = CPU_VGACNTRL;
7926 else
7927 vga_reg = VGACNTRL;
7928
7929 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7930 outb(1, VGA_SR_INDEX);
7931 sr1 = inb(VGA_SR_DATA);
7932 outb(sr1 | 1<<5, VGA_SR_DATA);
7933 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7934 udelay(300);
7935
7936 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7937 POSTING_READ(vga_reg);
7938}
7939
79e53945
JB		 7940void intel_modeset_init(struct drm_device *dev)
7941{
652c393a 7942 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 7943 int i;
7944
7945 drm_mode_config_init(dev);
7946
7947 dev->mode_config.min_width = 0;
7948 dev->mode_config.min_height = 0;
7949
7950 dev->mode_config.funcs = (void *)&intel_mode_funcs;
7951
b690e96c
JB		 7952 intel_init_quirks(dev);
7953
e70236a8
JB		 7954 intel_init_display(dev);
7955
a6c45cf0
CW		 7956 if (IS_GEN2(dev)) {
7957 dev->mode_config.max_width = 2048;
7958 dev->mode_config.max_height = 2048;
7959 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 7960 dev->mode_config.max_width = 4096;
7961 dev->mode_config.max_height = 4096;
79e53945 7962 } else {
a6c45cf0
CW		 7963 dev->mode_config.max_width = 8192;
7964 dev->mode_config.max_height = 8192;
79e53945 7965 }
35c3047a 7966 dev->mode_config.fb_base = dev->agp->base;
79e53945 7967
28c97730 7968 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 7969 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 7970
a3524f1b 7971 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945
JB		 7972 intel_crtc_init(dev, i);
7973 }
7974
9cce37f4
JB		 7975 /* Just disable it once at startup */
7976 i915_disable_vga(dev);
79e53945 7977 intel_setup_outputs(dev);
652c393a 7978
645c62a5 7979 intel_init_clock_gating(dev);
9cce37f4 7980
7648fa99 7981 if (IS_IRONLAKE_M(dev)) {
f97108d1 7982 ironlake_enable_drps(dev);
7648fa99
JB		 7983 intel_init_emon(dev);
7984 }
f97108d1 7985
3b8d8d91
JB		 7986 if (IS_GEN6(dev))
7987 gen6_enable_rps(dev_priv);
7988
652c393a
JB		 7989 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7990 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7991 (unsigned long)dev);
2c7111db
CW		 7992}
7993
7994void intel_modeset_gem_init(struct drm_device *dev)
7995{
7996 if (IS_IRONLAKE_M(dev))
7997 ironlake_enable_rc6(dev);
02e792fb
DV		 7998
7999 intel_setup_overlay(dev);
79e53945
JB		 8000}
8001
8002void intel_modeset_cleanup(struct drm_device *dev)
8003{
652c393a
JB		 8004 struct drm_i915_private *dev_priv = dev->dev_private;
8005 struct drm_crtc *crtc;
8006 struct intel_crtc *intel_crtc;
8007
f87ea761 8008 drm_kms_helper_poll_fini(dev);
652c393a
JB		 8009 mutex_lock(&dev->struct_mutex);
8010
723bfd70
JB		 8011 intel_unregister_dsm_handler();
8012
8013
652c393a
JB		 8014 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8015 /* Skip inactive CRTCs */
8016 if (!crtc->fb)
8017 continue;
8018
8019 intel_crtc = to_intel_crtc(crtc);
3dec0095 8020 intel_increase_pllclock(crtc);
652c393a
JB		 8021 }
8022
e70236a8
JB		 8023 if (dev_priv->display.disable_fbc)
8024 dev_priv->display.disable_fbc(dev);
8025
f97108d1
JB		 8026 if (IS_IRONLAKE_M(dev))
8027 ironlake_disable_drps(dev);
3b8d8d91
JB		 8028 if (IS_GEN6(dev))
8029 gen6_disable_rps(dev);
f97108d1 8030
d5bb081b
JB		 8031 if (IS_IRONLAKE_M(dev))
8032 ironlake_disable_rc6(dev);
0cdab21f 8033
69341a5e
KH		 8034 mutex_unlock(&dev->struct_mutex);
8035
6c0d9350
DV		 8036 /* Disable the irq before mode object teardown, for the irq might
8037 * enqueue unpin/hotplug work. */
8038 drm_irq_uninstall(dev);
8039 cancel_work_sync(&dev_priv->hotplug_work);
8040
3dec0095
DV		 8041 /* Shut off idle work before the crtcs get freed. */
8042 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8043 intel_crtc = to_intel_crtc(crtc);
8044 del_timer_sync(&intel_crtc->idle_timer);
8045 }
8046 del_timer_sync(&dev_priv->idle_timer);
8047 cancel_work_sync(&dev_priv->idle_work);
8048
79e53945
JB		 8049 drm_mode_config_cleanup(dev);
8050}
8051
f1c79df3
ZW		 8052/*
8053 * Return which encoder is currently attached for connector.
8054 */
df0e9248 8055struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 8056{
df0e9248
CW		 8057 return &intel_attached_encoder(connector)->base;
8058}
f1c79df3 8059
df0e9248
CW		 8060void intel_connector_attach_encoder(struct intel_connector *connector,
8061 struct intel_encoder *encoder)
8062{
8063 connector->encoder = encoder;
8064 drm_mode_connector_attach_encoder(&connector->base,
8065 &encoder->base);
79e53945 8066}
28d52043
DA		 8067
8068/*
8069 * set vga decode state - true == enable VGA decode
8070 */
8071int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8072{
8073 struct drm_i915_private *dev_priv = dev->dev_private;
8074 u16 gmch_ctrl;
8075
8076 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8077 if (state)
8078 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8079 else
8080 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8081 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8082 return 0;
8083}
c4a1d9e4
CW		 8084
8085#ifdef CONFIG_DEBUG_FS
8086#include <linux/seq_file.h>
8087
8088struct intel_display_error_state {
8089 struct intel_cursor_error_state {
8090 u32 control;
8091 u32 position;
8092 u32 base;
8093 u32 size;
8094 } cursor[2];
8095
8096 struct intel_pipe_error_state {
8097 u32 conf;
8098 u32 source;
8099
8100 u32 htotal;
8101 u32 hblank;
8102 u32 hsync;
8103 u32 vtotal;
8104 u32 vblank;
8105 u32 vsync;
8106 } pipe[2];
8107
8108 struct intel_plane_error_state {
8109 u32 control;
8110 u32 stride;
8111 u32 size;
8112 u32 pos;
8113 u32 addr;
8114 u32 surface;
8115 u32 tile_offset;
8116 } plane[2];
8117};
8118
8119struct intel_display_error_state *
8120intel_display_capture_error_state(struct drm_device *dev)
8121{
8122 drm_i915_private_t *dev_priv = dev->dev_private;
8123 struct intel_display_error_state *error;
8124 int i;
8125
8126 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8127 if (error == NULL)
8128 return NULL;
8129
8130 for (i = 0; i < 2; i++) {
8131 error->cursor[i].control = I915_READ(CURCNTR(i));
8132 error->cursor[i].position = I915_READ(CURPOS(i));
8133 error->cursor[i].base = I915_READ(CURBASE(i));
8134
8135 error->plane[i].control = I915_READ(DSPCNTR(i));
8136 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8137 error->plane[i].size = I915_READ(DSPSIZE(i));
8138 error->plane[i].pos= I915_READ(DSPPOS(i));
8139 error->plane[i].addr = I915_READ(DSPADDR(i));
8140 if (INTEL_INFO(dev)->gen >= 4) {
8141 error->plane[i].surface = I915_READ(DSPSURF(i));
8142 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8143 }
8144
8145 error->pipe[i].conf = I915_READ(PIPECONF(i));
8146 error->pipe[i].source = I915_READ(PIPESRC(i));
8147 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8148 error->pipe[i].hblank = I915_READ(HBLANK(i));
8149 error->pipe[i].hsync = I915_READ(HSYNC(i));
8150 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8151 error->pipe[i].vblank = I915_READ(VBLANK(i));
8152 error->pipe[i].vsync = I915_READ(VSYNC(i));
8153 }
8154
8155 return error;
8156}
8157
8158void
8159intel_display_print_error_state(struct seq_file *m,
8160 struct drm_device *dev,
8161 struct intel_display_error_state *error)
8162{
8163 int i;
8164
8165 for (i = 0; i < 2; i++) {
8166 seq_printf(m, "Pipe [%d]:\n", i);
8167 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8168 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8169 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8170 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8171 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8172 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8173 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8174 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8175
8176 seq_printf(m, "Plane [%d]:\n", i);
8177 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8178 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8179 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8180 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8181 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8182 if (INTEL_INFO(dev)->gen >= 4) {
8183 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8184 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8185 }
8186
8187 seq_printf(m, "Cursor [%d]:\n", i);
8188 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8189 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8190 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8191 }
8192}
8193#endif
Linux kernel - Deliverables
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