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drm/i915: properly mask and or watermark values for sprites
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
23b2f8bb 27#include <linux/cpufreq.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
7662c8bd 47static void intel_update_watermarks(struct drm_device *dev);
3dec0095 48static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 49static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 50
51typedef struct {
0206e353
AJ		 52 /* given values */
53 int n;
54 int m1, m2;
55 int p1, p2;
56 /* derived values */
57 int dot;
58 int vco;
59 int m;
60 int p;
79e53945
JB		 61} intel_clock_t;
62
63typedef struct {
0206e353 64 int min, max;
79e53945
JB		 65} intel_range_t;
66
67typedef struct {
0206e353
AJ		 68 int dot_limit;
69 int p2_slow, p2_fast;
79e53945
JB		 70} intel_p2_t;
71
72#define INTEL_P2_NUM 2
d4906093
ML		 73typedef struct intel_limit intel_limit_t;
74struct intel_limit {
0206e353
AJ		 75 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 intel_p2_t p2;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 78 int, int, intel_clock_t *, intel_clock_t *);
d4906093 79};
79e53945 80
2377b741
JB		 81/* FDI */
82#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
83
d4906093
ML		 84static bool
85intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 86 int target, int refclk, intel_clock_t *match_clock,
87 intel_clock_t *best_clock);
d4906093
ML		 88static bool
89intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 90 int target, int refclk, intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
79e53945 92
a4fc5ed6
KP		 93static bool
94intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
5eb08b69 97static bool
f2b115e6 98intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
a4fc5ed6 101
021357ac
CW		 102static inline u32 /* units of 100MHz */
103intel_fdi_link_freq(struct drm_device *dev)
104{
8b99e68c
CW		 105 if (IS_GEN5(dev)) {
106 struct drm_i915_private *dev_priv = dev->dev_private;
107 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
108 } else
109 return 27;
021357ac
CW		 110}
111
e4b36699 112static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 113 .dot = { .min = 25000, .max = 350000 },
114 .vco = { .min = 930000, .max = 1400000 },
115 .n = { .min = 3, .max = 16 },
116 .m = { .min = 96, .max = 140 },
117 .m1 = { .min = 18, .max = 26 },
118 .m2 = { .min = 6, .max = 16 },
119 .p = { .min = 4, .max = 128 },
120 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 121 .p2 = { .dot_limit = 165000,
122 .p2_slow = 4, .p2_fast = 2 },
d4906093 123 .find_pll = intel_find_best_PLL,
e4b36699
KP		 124};
125
126static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 14, .p2_fast = 7 },
d4906093 137 .find_pll = intel_find_best_PLL,
e4b36699 138};
273e27ca 139
e4b36699 140static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 141 .dot = { .min = 20000, .max = 400000 },
142 .vco = { .min = 1400000, .max = 2800000 },
143 .n = { .min = 1, .max = 6 },
144 .m = { .min = 70, .max = 120 },
145 .m1 = { .min = 10, .max = 22 },
146 .m2 = { .min = 5, .max = 9 },
147 .p = { .min = 5, .max = 80 },
148 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 149 .p2 = { .dot_limit = 200000,
150 .p2_slow = 10, .p2_fast = 5 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699
KP		 152};
153
154static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 7, .max = 98 },
162 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 163 .p2 = { .dot_limit = 112000,
164 .p2_slow = 14, .p2_fast = 7 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699
KP		 166};
167
273e27ca 168
e4b36699 169static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 170 .dot = { .min = 25000, .max = 270000 },
171 .vco = { .min = 1750000, .max = 3500000},
172 .n = { .min = 1, .max = 4 },
173 .m = { .min = 104, .max = 138 },
174 .m1 = { .min = 17, .max = 23 },
175 .m2 = { .min = 5, .max = 11 },
176 .p = { .min = 10, .max = 30 },
177 .p1 = { .min = 1, .max = 3},
178 .p2 = { .dot_limit = 270000,
179 .p2_slow = 10,
180 .p2_fast = 10
044c7c41 181 },
d4906093 182 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 183};
184
185static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 186 .dot = { .min = 22000, .max = 400000 },
187 .vco = { .min = 1750000, .max = 3500000},
188 .n = { .min = 1, .max = 4 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 16, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 5, .max = 80 },
193 .p1 = { .min = 1, .max = 8},
194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 10, .p2_fast = 5 },
d4906093 196 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 200 .dot = { .min = 20000, .max = 115000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 28, .max = 112 },
207 .p1 = { .min = 2, .max = 8 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 14, .p2_fast = 14
044c7c41 210 },
d4906093 211 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 212};
213
214static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 215 .dot = { .min = 80000, .max = 224000 },
216 .vco = { .min = 1750000, .max = 3500000 },
217 .n = { .min = 1, .max = 3 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 14, .max = 42 },
222 .p1 = { .min = 2, .max = 6 },
223 .p2 = { .dot_limit = 0,
224 .p2_slow = 7, .p2_fast = 7
044c7c41 225 },
d4906093 226 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 227};
228
229static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 230 .dot = { .min = 161670, .max = 227000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 2 },
233 .m = { .min = 97, .max = 108 },
234 .m1 = { .min = 0x10, .max = 0x12 },
235 .m2 = { .min = 0x05, .max = 0x06 },
236 .p = { .min = 10, .max = 20 },
237 .p1 = { .min = 1, .max = 2},
238 .p2 = { .dot_limit = 0,
273e27ca 239 .p2_slow = 10, .p2_fast = 10 },
0206e353 240 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 241};
242
f2b115e6 243static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 244 .dot = { .min = 20000, .max = 400000},
245 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 246 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 247 .n = { .min = 3, .max = 6 },
248 .m = { .min = 2, .max = 256 },
273e27ca 249 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 250 .m1 = { .min = 0, .max = 0 },
251 .m2 = { .min = 0, .max = 254 },
252 .p = { .min = 5, .max = 80 },
253 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 254 .p2 = { .dot_limit = 200000,
255 .p2_slow = 10, .p2_fast = 5 },
6115707b 256 .find_pll = intel_find_best_PLL,
e4b36699
KP		 257};
258
f2b115e6 259static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 260 .dot = { .min = 20000, .max = 400000 },
261 .vco = { .min = 1700000, .max = 3500000 },
262 .n = { .min = 3, .max = 6 },
263 .m = { .min = 2, .max = 256 },
264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 7, .max = 112 },
267 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 268 .p2 = { .dot_limit = 112000,
269 .p2_slow = 14, .p2_fast = 14 },
6115707b 270 .find_pll = intel_find_best_PLL,
e4b36699
KP		 271};
272
273e27ca
EA		 273/* Ironlake / Sandybridge
274 *
275 * We calculate clock using (register_value + 2) for N/M1/M2, so here
276 * the range value for them is (actual_value - 2).
277 */
b91ad0ec 278static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 279 .dot = { .min = 25000, .max = 350000 },
280 .vco = { .min = 1760000, .max = 3510000 },
281 .n = { .min = 1, .max = 5 },
282 .m = { .min = 79, .max = 127 },
283 .m1 = { .min = 12, .max = 22 },
284 .m2 = { .min = 5, .max = 9 },
285 .p = { .min = 5, .max = 80 },
286 .p1 = { .min = 1, .max = 8 },
287 .p2 = { .dot_limit = 225000,
288 .p2_slow = 10, .p2_fast = 5 },
4547668a 289 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 290};
291
b91ad0ec 292static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 3 },
296 .m = { .min = 79, .max = 118 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 28, .max = 112 },
300 .p1 = { .min = 2, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 303 .find_pll = intel_g4x_find_best_PLL,
304};
305
306static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 14, .max = 56 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 317 .find_pll = intel_g4x_find_best_PLL,
318};
319
273e27ca 320/* LVDS 100mhz refclk limits. */
b91ad0ec 321static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 322 .dot = { .min = 25000, .max = 350000 },
323 .vco = { .min = 1760000, .max = 3510000 },
324 .n = { .min = 1, .max = 2 },
325 .m = { .min = 79, .max = 126 },
326 .m1 = { .min = 12, .max = 22 },
327 .m2 = { .min = 5, .max = 9 },
328 .p = { .min = 28, .max = 112 },
0206e353 329 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 330 .p2 = { .dot_limit = 225000,
331 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 332 .find_pll = intel_g4x_find_best_PLL,
333};
334
335static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 3 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 14, .max = 42 },
0206e353 343 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 346 .find_pll = intel_g4x_find_best_PLL,
347};
348
349static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000},
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 81, .max = 90 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 10, .max = 20 },
357 .p1 = { .min = 1, .max = 2},
358 .p2 = { .dot_limit = 0,
273e27ca 359 .p2_slow = 10, .p2_fast = 10 },
0206e353 360 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 361};
362
1b894b59
CW		 363static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
364 int refclk)
2c07245f 365{
b91ad0ec
ZW		 366 struct drm_device *dev = crtc->dev;
367 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 368 const intel_limit_t *limit;
b91ad0ec
ZW		 369
370 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b91ad0ec
ZW		 371 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
372 LVDS_CLKB_POWER_UP) {
373 /* LVDS dual channel */
1b894b59 374 if (refclk == 100000)
b91ad0ec
ZW		 375 limit = &intel_limits_ironlake_dual_lvds_100m;
376 else
377 limit = &intel_limits_ironlake_dual_lvds;
378 } else {
1b894b59 379 if (refclk == 100000)
b91ad0ec
ZW		 380 limit = &intel_limits_ironlake_single_lvds_100m;
381 else
382 limit = &intel_limits_ironlake_single_lvds;
383 }
384 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 385 HAS_eDP)
386 limit = &intel_limits_ironlake_display_port;
2c07245f 387 else
b91ad0ec 388 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 389
390 return limit;
391}
392
044c7c41
ML		 393static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
394{
395 struct drm_device *dev = crtc->dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 const intel_limit_t *limit;
398
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
400 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
401 LVDS_CLKB_POWER_UP)
402 /* LVDS with dual channel */
e4b36699 403 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 404 else
405 /* LVDS with dual channel */
e4b36699 406 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 407 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
408 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 409 limit = &intel_limits_g4x_hdmi;
044c7c41 410 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 411 limit = &intel_limits_g4x_sdvo;
0206e353 412 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 413 limit = &intel_limits_g4x_display_port;
044c7c41 414 } else /* The option is for other outputs */
e4b36699 415 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 416
417 return limit;
418}
419
1b894b59 420static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 421{
422 struct drm_device *dev = crtc->dev;
423 const intel_limit_t *limit;
424
bad720ff 425 if (HAS_PCH_SPLIT(dev))
1b894b59 426 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 427 else if (IS_G4X(dev)) {
044c7c41 428 limit = intel_g4x_limit(crtc);
f2b115e6 429 } else if (IS_PINEVIEW(dev)) {
2177832f 430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 431 limit = &intel_limits_pineview_lvds;
2177832f 432 else
f2b115e6 433 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 434 } else if (!IS_GEN2(dev)) {
435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
436 limit = &intel_limits_i9xx_lvds;
437 else
438 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 439 } else {
440 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 441 limit = &intel_limits_i8xx_lvds;
79e53945 442 else
e4b36699 443 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 444 }
445 return limit;
446}
447
f2b115e6
AJ		 448/* m1 is reserved as 0 in Pineview, n is a ring counter */
449static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 450{
2177832f
SL		 451 clock->m = clock->m2 + 2;
452 clock->p = clock->p1 * clock->p2;
453 clock->vco = refclk * clock->m / clock->n;
454 clock->dot = clock->vco / clock->p;
455}
456
457static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
458{
f2b115e6
AJ		 459 if (IS_PINEVIEW(dev)) {
460 pineview_clock(refclk, clock);
2177832f
SL		 461 return;
462 }
79e53945
JB		 463 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
464 clock->p = clock->p1 * clock->p2;
465 clock->vco = refclk * clock->m / (clock->n + 2);
466 clock->dot = clock->vco / clock->p;
467}
468
79e53945
JB		 469/**
470 * Returns whether any output on the specified pipe is of the specified type
471 */
4ef69c7a 472bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 473{
4ef69c7a
CW		 474 struct drm_device *dev = crtc->dev;
475 struct drm_mode_config *mode_config = &dev->mode_config;
476 struct intel_encoder *encoder;
477
478 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
479 if (encoder->base.crtc == crtc && encoder->type == type)
480 return true;
481
482 return false;
79e53945
JB		 483}
484
7c04d1d9 485#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 486/**
487 * Returns whether the given set of divisors are valid for a given refclk with
488 * the given connectors.
489 */
490
1b894b59
CW		 491static bool intel_PLL_is_valid(struct drm_device *dev,
492 const intel_limit_t *limit,
493 const intel_clock_t *clock)
79e53945 494{
79e53945 495 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 496 INTELPllInvalid("p1 out of range\n");
79e53945 497 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 498 INTELPllInvalid("p out of range\n");
79e53945 499 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 500 INTELPllInvalid("m2 out of range\n");
79e53945 501 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 502 INTELPllInvalid("m1 out of range\n");
f2b115e6 503 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 504 INTELPllInvalid("m1 <= m2\n");
79e53945 505 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 506 INTELPllInvalid("m out of range\n");
79e53945 507 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 508 INTELPllInvalid("n out of range\n");
79e53945 509 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 510 INTELPllInvalid("vco out of range\n");
79e53945
JB		 511 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
512 * connector, etc., rather than just a single range.
513 */
514 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 515 INTELPllInvalid("dot out of range\n");
79e53945
JB		 516
517 return true;
518}
519
d4906093
ML		 520static bool
521intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 522 int target, int refclk, intel_clock_t *match_clock,
523 intel_clock_t *best_clock)
d4906093 524
79e53945
JB		 525{
526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
528 intel_clock_t clock;
79e53945
JB		 529 int err = target;
530
bc5e5718 531 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 532 (I915_READ(LVDS)) != 0) {
79e53945
JB		 533 /*
534 * For LVDS, if the panel is on, just rely on its current
535 * settings for dual-channel. We haven't figured out how to
536 * reliably set up different single/dual channel state, if we
537 * even can.
538 */
539 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
540 LVDS_CLKB_POWER_UP)
541 clock.p2 = limit->p2.p2_fast;
542 else
543 clock.p2 = limit->p2.p2_slow;
544 } else {
545 if (target < limit->p2.dot_limit)
546 clock.p2 = limit->p2.p2_slow;
547 else
548 clock.p2 = limit->p2.p2_fast;
549 }
550
0206e353 551 memset(best_clock, 0, sizeof(*best_clock));
79e53945 552
42158660
ZY		 553 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
554 clock.m1++) {
555 for (clock.m2 = limit->m2.min;
556 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 557 /* m1 is always 0 in Pineview */
558 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 559 break;
560 for (clock.n = limit->n.min;
561 clock.n <= limit->n.max; clock.n++) {
562 for (clock.p1 = limit->p1.min;
563 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 564 int this_err;
565
2177832f 566 intel_clock(dev, refclk, &clock);
1b894b59
CW		 567 if (!intel_PLL_is_valid(dev, limit,
568 &clock))
79e53945 569 continue;
cec2f356
SP		 570 if (match_clock &&
571 clock.p != match_clock->p)
572 continue;
79e53945
JB		 573
574 this_err = abs(clock.dot - target);
575 if (this_err < err) {
576 *best_clock = clock;
577 err = this_err;
578 }
579 }
580 }
581 }
582 }
583
584 return (err != target);
585}
586
d4906093
ML		 587static bool
588intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 589 int target, int refclk, intel_clock_t *match_clock,
590 intel_clock_t *best_clock)
d4906093
ML		 591{
592 struct drm_device *dev = crtc->dev;
593 struct drm_i915_private *dev_priv = dev->dev_private;
594 intel_clock_t clock;
595 int max_n;
596 bool found;
6ba770dc
AJ		 597 /* approximately equals target * 0.00585 */
598 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 599 found = false;
600
601 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 602 int lvds_reg;
603
c619eed4 604 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 605 lvds_reg = PCH_LVDS;
606 else
607 lvds_reg = LVDS;
608 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 609 LVDS_CLKB_POWER_UP)
610 clock.p2 = limit->p2.p2_fast;
611 else
612 clock.p2 = limit->p2.p2_slow;
613 } else {
614 if (target < limit->p2.dot_limit)
615 clock.p2 = limit->p2.p2_slow;
616 else
617 clock.p2 = limit->p2.p2_fast;
618 }
619
620 memset(best_clock, 0, sizeof(*best_clock));
621 max_n = limit->n.max;
f77f13e2 622 /* based on hardware requirement, prefer smaller n to precision */
d4906093 623 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 624 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 625 for (clock.m1 = limit->m1.max;
626 clock.m1 >= limit->m1.min; clock.m1--) {
627 for (clock.m2 = limit->m2.max;
628 clock.m2 >= limit->m2.min; clock.m2--) {
629 for (clock.p1 = limit->p1.max;
630 clock.p1 >= limit->p1.min; clock.p1--) {
631 int this_err;
632
2177832f 633 intel_clock(dev, refclk, &clock);
1b894b59
CW		 634 if (!intel_PLL_is_valid(dev, limit,
635 &clock))
d4906093 636 continue;
cec2f356
SP		 637 if (match_clock &&
638 clock.p != match_clock->p)
639 continue;
1b894b59
CW		 640
641 this_err = abs(clock.dot - target);
d4906093
ML		 642 if (this_err < err_most) {
643 *best_clock = clock;
644 err_most = this_err;
645 max_n = clock.n;
646 found = true;
647 }
648 }
649 }
650 }
651 }
2c07245f
ZW		 652 return found;
653}
654
5eb08b69 655static bool
f2b115e6 656intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 657 int target, int refclk, intel_clock_t *match_clock,
658 intel_clock_t *best_clock)
5eb08b69
ZW		 659{
660 struct drm_device *dev = crtc->dev;
661 intel_clock_t clock;
4547668a 662
5eb08b69
ZW		 663 if (target < 200000) {
664 clock.n = 1;
665 clock.p1 = 2;
666 clock.p2 = 10;
667 clock.m1 = 12;
668 clock.m2 = 9;
669 } else {
670 clock.n = 2;
671 clock.p1 = 1;
672 clock.p2 = 10;
673 clock.m1 = 14;
674 clock.m2 = 8;
675 }
676 intel_clock(dev, refclk, &clock);
677 memcpy(best_clock, &clock, sizeof(intel_clock_t));
678 return true;
679}
680
a4fc5ed6
KP		 681/* DisplayPort has only two frequencies, 162MHz and 270MHz */
682static bool
683intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
a4fc5ed6 686{
5eddb70b
CW		 687 intel_clock_t clock;
688 if (target < 200000) {
689 clock.p1 = 2;
690 clock.p2 = 10;
691 clock.n = 2;
692 clock.m1 = 23;
693 clock.m2 = 8;
694 } else {
695 clock.p1 = 1;
696 clock.p2 = 10;
697 clock.n = 1;
698 clock.m1 = 14;
699 clock.m2 = 2;
700 }
701 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
702 clock.p = (clock.p1 * clock.p2);
703 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
704 clock.vco = 0;
705 memcpy(best_clock, &clock, sizeof(intel_clock_t));
706 return true;
a4fc5ed6
KP		 707}
708
9d0498a2
JB		 709/**
710 * intel_wait_for_vblank - wait for vblank on a given pipe
711 * @dev: drm device
712 * @pipe: pipe to wait for
713 *
714 * Wait for vblank to occur on a given pipe. Needed for various bits of
715 * mode setting code.
716 */
717void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 718{
9d0498a2 719 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 720 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 721
300387c0
CW		 722 /* Clear existing vblank status. Note this will clear any other
723 * sticky status fields as well.
724 *
725 * This races with i915_driver_irq_handler() with the result
726 * that either function could miss a vblank event. Here it is not
727 * fatal, as we will either wait upon the next vblank interrupt or
728 * timeout. Generally speaking intel_wait_for_vblank() is only
729 * called during modeset at which time the GPU should be idle and
730 * should *not* be performing page flips and thus not waiting on
731 * vblanks...
732 * Currently, the result of us stealing a vblank from the irq
733 * handler is that a single frame will be skipped during swapbuffers.
734 */
735 I915_WRITE(pipestat_reg,
736 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
737
9d0498a2 738 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 739 if (wait_for(I915_READ(pipestat_reg) &
740 PIPE_VBLANK_INTERRUPT_STATUS,
741 50))
9d0498a2
JB		 742 DRM_DEBUG_KMS("vblank wait timed out\n");
743}
744
ab7ad7f6
KP		 745/*
746 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 747 * @dev: drm device
748 * @pipe: pipe to wait for
749 *
750 * After disabling a pipe, we can't wait for vblank in the usual way,
751 * spinning on the vblank interrupt status bit, since we won't actually
752 * see an interrupt when the pipe is disabled.
753 *
ab7ad7f6
KP		 754 * On Gen4 and above:
755 * wait for the pipe register state bit to turn off
756 *
757 * Otherwise:
758 * wait for the display line value to settle (it usually
759 * ends up stopping at the start of the next frame).
58e10eb9 760 *
9d0498a2 761 */
58e10eb9 762void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 763{
764 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 765
766 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 767 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 768
769 /* Wait for the Pipe State to go off */
58e10eb9
CW		 770 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
771 100))
ab7ad7f6
KP		 772 DRM_DEBUG_KMS("pipe_off wait timed out\n");
773 } else {
774 u32 last_line;
58e10eb9 775 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 776 unsigned long timeout = jiffies + msecs_to_jiffies(100);
777
778 /* Wait for the display line to settle */
779 do {
58e10eb9 780 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 781 mdelay(5);
58e10eb9 782 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 783 time_after(timeout, jiffies));
784 if (time_after(jiffies, timeout))
785 DRM_DEBUG_KMS("pipe_off wait timed out\n");
786 }
79e53945
JB		 787}
788
b24e7179
JB		 789static const char *state_string(bool enabled)
790{
791 return enabled ? "on" : "off";
792}
793
794/* Only for pre-ILK configs */
795static void assert_pll(struct drm_i915_private *dev_priv,
796 enum pipe pipe, bool state)
797{
798 int reg;
799 u32 val;
800 bool cur_state;
801
802 reg = DPLL(pipe);
803 val = I915_READ(reg);
804 cur_state = !!(val & DPLL_VCO_ENABLE);
805 WARN(cur_state != state,
806 "PLL state assertion failure (expected %s, current %s)\n",
807 state_string(state), state_string(cur_state));
808}
809#define assert_pll_enabled(d, p) assert_pll(d, p, true)
810#define assert_pll_disabled(d, p) assert_pll(d, p, false)
811
040484af
JB		 812/* For ILK+ */
813static void assert_pch_pll(struct drm_i915_private *dev_priv,
814 enum pipe pipe, bool state)
815{
816 int reg;
817 u32 val;
818 bool cur_state;
819
d3ccbe86
JB		 820 if (HAS_PCH_CPT(dev_priv->dev)) {
821 u32 pch_dpll;
822
823 pch_dpll = I915_READ(PCH_DPLL_SEL);
824
825 /* Make sure the selected PLL is enabled to the transcoder */
826 WARN(!((pch_dpll >> (4 * pipe)) & 8),
827 "transcoder %d PLL not enabled\n", pipe);
828
829 /* Convert the transcoder pipe number to a pll pipe number */
830 pipe = (pch_dpll >> (4 * pipe)) & 1;
831 }
832
040484af
JB		 833 reg = PCH_DPLL(pipe);
834 val = I915_READ(reg);
835 cur_state = !!(val & DPLL_VCO_ENABLE);
836 WARN(cur_state != state,
837 "PCH PLL state assertion failure (expected %s, current %s)\n",
838 state_string(state), state_string(cur_state));
839}
840#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
841#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
842
843static void assert_fdi_tx(struct drm_i915_private *dev_priv,
844 enum pipe pipe, bool state)
845{
846 int reg;
847 u32 val;
848 bool cur_state;
849
850 reg = FDI_TX_CTL(pipe);
851 val = I915_READ(reg);
852 cur_state = !!(val & FDI_TX_ENABLE);
853 WARN(cur_state != state,
854 "FDI TX state assertion failure (expected %s, current %s)\n",
855 state_string(state), state_string(cur_state));
856}
857#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
858#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
859
860static void assert_fdi_rx(struct drm_i915_private *dev_priv,
861 enum pipe pipe, bool state)
862{
863 int reg;
864 u32 val;
865 bool cur_state;
866
867 reg = FDI_RX_CTL(pipe);
868 val = I915_READ(reg);
869 cur_state = !!(val & FDI_RX_ENABLE);
870 WARN(cur_state != state,
871 "FDI RX state assertion failure (expected %s, current %s)\n",
872 state_string(state), state_string(cur_state));
873}
874#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
875#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
876
877static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
878 enum pipe pipe)
879{
880 int reg;
881 u32 val;
882
883 /* ILK FDI PLL is always enabled */
884 if (dev_priv->info->gen == 5)
885 return;
886
887 reg = FDI_TX_CTL(pipe);
888 val = I915_READ(reg);
889 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
890}
891
892static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
893 enum pipe pipe)
894{
895 int reg;
896 u32 val;
897
898 reg = FDI_RX_CTL(pipe);
899 val = I915_READ(reg);
900 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
901}
902
ea0760cf
JB		 903static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
904 enum pipe pipe)
905{
906 int pp_reg, lvds_reg;
907 u32 val;
908 enum pipe panel_pipe = PIPE_A;
0de3b485 909 bool locked = true;
ea0760cf
JB		 910
911 if (HAS_PCH_SPLIT(dev_priv->dev)) {
912 pp_reg = PCH_PP_CONTROL;
913 lvds_reg = PCH_LVDS;
914 } else {
915 pp_reg = PP_CONTROL;
916 lvds_reg = LVDS;
917 }
918
919 val = I915_READ(pp_reg);
920 if (!(val & PANEL_POWER_ON) ||
921 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
922 locked = false;
923
924 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
925 panel_pipe = PIPE_B;
926
927 WARN(panel_pipe == pipe && locked,
928 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 929 pipe_name(pipe));
ea0760cf
JB		 930}
931
b840d907
JB		 932void assert_pipe(struct drm_i915_private *dev_priv,
933 enum pipe pipe, bool state)
b24e7179
JB		 934{
935 int reg;
936 u32 val;
63d7bbe9 937 bool cur_state;
b24e7179
JB		 938
939 reg = PIPECONF(pipe);
940 val = I915_READ(reg);
63d7bbe9
JB		 941 cur_state = !!(val & PIPECONF_ENABLE);
942 WARN(cur_state != state,
943 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 944 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 945}
946
931872fc
CW		 947static void assert_plane(struct drm_i915_private *dev_priv,
948 enum plane plane, bool state)
b24e7179
JB		 949{
950 int reg;
951 u32 val;
931872fc 952 bool cur_state;
b24e7179
JB		 953
954 reg = DSPCNTR(plane);
955 val = I915_READ(reg);
931872fc
CW		 956 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
957 WARN(cur_state != state,
958 "plane %c assertion failure (expected %s, current %s)\n",
959 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 960}
961
931872fc
CW		 962#define assert_plane_enabled(d, p) assert_plane(d, p, true)
963#define assert_plane_disabled(d, p) assert_plane(d, p, false)
964
b24e7179
JB		 965static void assert_planes_disabled(struct drm_i915_private *dev_priv,
966 enum pipe pipe)
967{
968 int reg, i;
969 u32 val;
970 int cur_pipe;
971
19ec1358 972 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 973 if (HAS_PCH_SPLIT(dev_priv->dev)) {
974 reg = DSPCNTR(pipe);
975 val = I915_READ(reg);
976 WARN((val & DISPLAY_PLANE_ENABLE),
977 "plane %c assertion failure, should be disabled but not\n",
978 plane_name(pipe));
19ec1358 979 return;
28c05794 980 }
19ec1358 981
b24e7179
JB		 982 /* Need to check both planes against the pipe */
983 for (i = 0; i < 2; i++) {
984 reg = DSPCNTR(i);
985 val = I915_READ(reg);
986 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
987 DISPPLANE_SEL_PIPE_SHIFT;
988 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 989 "plane %c assertion failure, should be off on pipe %c but is still active\n",
990 plane_name(i), pipe_name(pipe));
b24e7179
JB		 991 }
992}
993
92f2584a
JB		 994static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
995{
996 u32 val;
997 bool enabled;
998
999 val = I915_READ(PCH_DREF_CONTROL);
1000 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1001 DREF_SUPERSPREAD_SOURCE_MASK));
1002 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1003}
1004
1005static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1006 enum pipe pipe)
1007{
1008 int reg;
1009 u32 val;
1010 bool enabled;
1011
1012 reg = TRANSCONF(pipe);
1013 val = I915_READ(reg);
1014 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1015 WARN(enabled,
1016 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1017 pipe_name(pipe));
92f2584a
JB		 1018}
1019
4e634389
KP		 1020static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1021 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1022{
1023 if ((val & DP_PORT_EN) == 0)
1024 return false;
1025
1026 if (HAS_PCH_CPT(dev_priv->dev)) {
1027 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1028 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1029 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1030 return false;
1031 } else {
1032 if ((val & DP_PIPE_MASK) != (pipe << 30))
1033 return false;
1034 }
1035 return true;
1036}
1037
1519b995
KP		 1038static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1039 enum pipe pipe, u32 val)
1040{
1041 if ((val & PORT_ENABLE) == 0)
1042 return false;
1043
1044 if (HAS_PCH_CPT(dev_priv->dev)) {
1045 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1046 return false;
1047 } else {
1048 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1049 return false;
1050 }
1051 return true;
1052}
1053
1054static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1055 enum pipe pipe, u32 val)
1056{
1057 if ((val & LVDS_PORT_EN) == 0)
1058 return false;
1059
1060 if (HAS_PCH_CPT(dev_priv->dev)) {
1061 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1062 return false;
1063 } else {
1064 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1065 return false;
1066 }
1067 return true;
1068}
1069
1070static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1071 enum pipe pipe, u32 val)
1072{
1073 if ((val & ADPA_DAC_ENABLE) == 0)
1074 return false;
1075 if (HAS_PCH_CPT(dev_priv->dev)) {
1076 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1077 return false;
1078 } else {
1079 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1080 return false;
1081 }
1082 return true;
1083}
1084
291906f1 1085static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1086 enum pipe pipe, int reg, u32 port_sel)
291906f1 1087{
47a05eca 1088 u32 val = I915_READ(reg);
4e634389 1089 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1090 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1091 reg, pipe_name(pipe));
291906f1
JB		 1092}
1093
1094static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1095 enum pipe pipe, int reg)
1096{
47a05eca 1097 u32 val = I915_READ(reg);
1519b995 1098 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
23c99e77 1099 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1100 reg, pipe_name(pipe));
291906f1
JB		 1101}
1102
1103static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1104 enum pipe pipe)
1105{
1106 int reg;
1107 u32 val;
291906f1 1108
f0575e92
KP		 1109 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1110 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1111 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1112
1113 reg = PCH_ADPA;
1114 val = I915_READ(reg);
1519b995 1115 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1116 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1117 pipe_name(pipe));
291906f1
JB		 1118
1119 reg = PCH_LVDS;
1120 val = I915_READ(reg);
1519b995 1121 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1122 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1123 pipe_name(pipe));
291906f1
JB		 1124
1125 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1126 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1127 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1128}
1129
63d7bbe9
JB		 1130/**
1131 * intel_enable_pll - enable a PLL
1132 * @dev_priv: i915 private structure
1133 * @pipe: pipe PLL to enable
1134 *
1135 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1136 * make sure the PLL reg is writable first though, since the panel write
1137 * protect mechanism may be enabled.
1138 *
1139 * Note! This is for pre-ILK only.
1140 */
1141static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1142{
1143 int reg;
1144 u32 val;
1145
1146 /* No really, not for ILK+ */
1147 BUG_ON(dev_priv->info->gen >= 5);
1148
1149 /* PLL is protected by panel, make sure we can write it */
1150 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1151 assert_panel_unlocked(dev_priv, pipe);
1152
1153 reg = DPLL(pipe);
1154 val = I915_READ(reg);
1155 val |= DPLL_VCO_ENABLE;
1156
1157 /* We do this three times for luck */
1158 I915_WRITE(reg, val);
1159 POSTING_READ(reg);
1160 udelay(150); /* wait for warmup */
1161 I915_WRITE(reg, val);
1162 POSTING_READ(reg);
1163 udelay(150); /* wait for warmup */
1164 I915_WRITE(reg, val);
1165 POSTING_READ(reg);
1166 udelay(150); /* wait for warmup */
1167}
1168
1169/**
1170 * intel_disable_pll - disable a PLL
1171 * @dev_priv: i915 private structure
1172 * @pipe: pipe PLL to disable
1173 *
1174 * Disable the PLL for @pipe, making sure the pipe is off first.
1175 *
1176 * Note! This is for pre-ILK only.
1177 */
1178static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1179{
1180 int reg;
1181 u32 val;
1182
1183 /* Don't disable pipe A or pipe A PLLs if needed */
1184 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1185 return;
1186
1187 /* Make sure the pipe isn't still relying on us */
1188 assert_pipe_disabled(dev_priv, pipe);
1189
1190 reg = DPLL(pipe);
1191 val = I915_READ(reg);
1192 val &= ~DPLL_VCO_ENABLE;
1193 I915_WRITE(reg, val);
1194 POSTING_READ(reg);
1195}
1196
92f2584a
JB		 1197/**
1198 * intel_enable_pch_pll - enable PCH PLL
1199 * @dev_priv: i915 private structure
1200 * @pipe: pipe PLL to enable
1201 *
1202 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1203 * drives the transcoder clock.
1204 */
1205static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1206 enum pipe pipe)
1207{
1208 int reg;
1209 u32 val;
1210
4c609cb8
JB		 1211 if (pipe > 1)
1212 return;
1213
92f2584a
JB		 1214 /* PCH only available on ILK+ */
1215 BUG_ON(dev_priv->info->gen < 5);
1216
1217 /* PCH refclock must be enabled first */
1218 assert_pch_refclk_enabled(dev_priv);
1219
1220 reg = PCH_DPLL(pipe);
1221 val = I915_READ(reg);
1222 val |= DPLL_VCO_ENABLE;
1223 I915_WRITE(reg, val);
1224 POSTING_READ(reg);
1225 udelay(200);
1226}
1227
1228static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1229 enum pipe pipe)
1230{
1231 int reg;
7a419866
JB		 1232 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1233 pll_sel = TRANSC_DPLL_ENABLE;
92f2584a 1234
4c609cb8
JB		 1235 if (pipe > 1)
1236 return;
1237
92f2584a
JB		 1238 /* PCH only available on ILK+ */
1239 BUG_ON(dev_priv->info->gen < 5);
1240
1241 /* Make sure transcoder isn't still depending on us */
1242 assert_transcoder_disabled(dev_priv, pipe);
1243
7a419866
JB		 1244 if (pipe == 0)
1245 pll_sel |= TRANSC_DPLLA_SEL;
1246 else if (pipe == 1)
1247 pll_sel |= TRANSC_DPLLB_SEL;
1248
1249
1250 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1251 return;
1252
92f2584a
JB		 1253 reg = PCH_DPLL(pipe);
1254 val = I915_READ(reg);
1255 val &= ~DPLL_VCO_ENABLE;
1256 I915_WRITE(reg, val);
1257 POSTING_READ(reg);
1258 udelay(200);
1259}
1260
040484af
JB		 1261static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1262 enum pipe pipe)
1263{
1264 int reg;
1265 u32 val;
1266
1267 /* PCH only available on ILK+ */
1268 BUG_ON(dev_priv->info->gen < 5);
1269
1270 /* Make sure PCH DPLL is enabled */
1271 assert_pch_pll_enabled(dev_priv, pipe);
1272
1273 /* FDI must be feeding us bits for PCH ports */
1274 assert_fdi_tx_enabled(dev_priv, pipe);
1275 assert_fdi_rx_enabled(dev_priv, pipe);
1276
1277 reg = TRANSCONF(pipe);
1278 val = I915_READ(reg);
e9bcff5c
JB		 1279
1280 if (HAS_PCH_IBX(dev_priv->dev)) {
1281 /*
1282 * make the BPC in transcoder be consistent with
1283 * that in pipeconf reg.
1284 */
1285 val &= ~PIPE_BPC_MASK;
1286 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1287 }
040484af
JB		 1288 I915_WRITE(reg, val | TRANS_ENABLE);
1289 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1290 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1291}
1292
1293static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1294 enum pipe pipe)
1295{
1296 int reg;
1297 u32 val;
1298
1299 /* FDI relies on the transcoder */
1300 assert_fdi_tx_disabled(dev_priv, pipe);
1301 assert_fdi_rx_disabled(dev_priv, pipe);
1302
291906f1
JB		 1303 /* Ports must be off as well */
1304 assert_pch_ports_disabled(dev_priv, pipe);
1305
040484af
JB		 1306 reg = TRANSCONF(pipe);
1307 val = I915_READ(reg);
1308 val &= ~TRANS_ENABLE;
1309 I915_WRITE(reg, val);
1310 /* wait for PCH transcoder off, transcoder state */
1311 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1312 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1313}
1314
b24e7179 1315/**
309cfea8 1316 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1317 * @dev_priv: i915 private structure
1318 * @pipe: pipe to enable
040484af 1319 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1320 *
1321 * Enable @pipe, making sure that various hardware specific requirements
1322 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1323 *
1324 * @pipe should be %PIPE_A or %PIPE_B.
1325 *
1326 * Will wait until the pipe is actually running (i.e. first vblank) before
1327 * returning.
1328 */
040484af
JB		 1329static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1330 bool pch_port)
b24e7179
JB		 1331{
1332 int reg;
1333 u32 val;
1334
1335 /*
1336 * A pipe without a PLL won't actually be able to drive bits from
1337 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1338 * need the check.
1339 */
1340 if (!HAS_PCH_SPLIT(dev_priv->dev))
1341 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1342 else {
1343 if (pch_port) {
1344 /* if driving the PCH, we need FDI enabled */
1345 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1346 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1347 }
1348 /* FIXME: assert CPU port conditions for SNB+ */
1349 }
b24e7179
JB		 1350
1351 reg = PIPECONF(pipe);
1352 val = I915_READ(reg);
00d70b15
CW		 1353 if (val & PIPECONF_ENABLE)
1354 return;
1355
1356 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1357 intel_wait_for_vblank(dev_priv->dev, pipe);
1358}
1359
1360/**
309cfea8 1361 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1362 * @dev_priv: i915 private structure
1363 * @pipe: pipe to disable
1364 *
1365 * Disable @pipe, making sure that various hardware specific requirements
1366 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1367 *
1368 * @pipe should be %PIPE_A or %PIPE_B.
1369 *
1370 * Will wait until the pipe has shut down before returning.
1371 */
1372static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1373 enum pipe pipe)
1374{
1375 int reg;
1376 u32 val;
1377
1378 /*
1379 * Make sure planes won't keep trying to pump pixels to us,
1380 * or we might hang the display.
1381 */
1382 assert_planes_disabled(dev_priv, pipe);
1383
1384 /* Don't disable pipe A or pipe A PLLs if needed */
1385 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1386 return;
1387
1388 reg = PIPECONF(pipe);
1389 val = I915_READ(reg);
00d70b15
CW		 1390 if ((val & PIPECONF_ENABLE) == 0)
1391 return;
1392
1393 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1394 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1395}
1396
d74362c9
KP		 1397/*
1398 * Plane regs are double buffered, going from enabled->disabled needs a
1399 * trigger in order to latch. The display address reg provides this.
1400 */
1401static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1402 enum plane plane)
1403{
1404 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1405 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1406}
1407
b24e7179
JB		 1408/**
1409 * intel_enable_plane - enable a display plane on a given pipe
1410 * @dev_priv: i915 private structure
1411 * @plane: plane to enable
1412 * @pipe: pipe being fed
1413 *
1414 * Enable @plane on @pipe, making sure that @pipe is running first.
1415 */
1416static void intel_enable_plane(struct drm_i915_private *dev_priv,
1417 enum plane plane, enum pipe pipe)
1418{
1419 int reg;
1420 u32 val;
1421
1422 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1423 assert_pipe_enabled(dev_priv, pipe);
1424
1425 reg = DSPCNTR(plane);
1426 val = I915_READ(reg);
00d70b15
CW		 1427 if (val & DISPLAY_PLANE_ENABLE)
1428 return;
1429
1430 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1431 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1432 intel_wait_for_vblank(dev_priv->dev, pipe);
1433}
1434
b24e7179
JB		 1435/**
1436 * intel_disable_plane - disable a display plane
1437 * @dev_priv: i915 private structure
1438 * @plane: plane to disable
1439 * @pipe: pipe consuming the data
1440 *
1441 * Disable @plane; should be an independent operation.
1442 */
1443static void intel_disable_plane(struct drm_i915_private *dev_priv,
1444 enum plane plane, enum pipe pipe)
1445{
1446 int reg;
1447 u32 val;
1448
1449 reg = DSPCNTR(plane);
1450 val = I915_READ(reg);
00d70b15
CW		 1451 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1452 return;
1453
1454 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1455 intel_flush_display_plane(dev_priv, plane);
1456 intel_wait_for_vblank(dev_priv->dev, pipe);
1457}
1458
47a05eca 1459static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1460 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1461{
1462 u32 val = I915_READ(reg);
4e634389 1463 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1464 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1465 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1466 }
47a05eca
JB		 1467}
1468
1469static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1470 enum pipe pipe, int reg)
1471{
1472 u32 val = I915_READ(reg);
1519b995 1473 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1474 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1475 reg, pipe);
47a05eca 1476 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1477 }
47a05eca
JB		 1478}
1479
1480/* Disable any ports connected to this transcoder */
1481static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1482 enum pipe pipe)
1483{
1484 u32 reg, val;
1485
1486 val = I915_READ(PCH_PP_CONTROL);
1487 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1488
f0575e92
KP		 1489 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1490 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1491 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1492
1493 reg = PCH_ADPA;
1494 val = I915_READ(reg);
1519b995 1495 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1496 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1497
1498 reg = PCH_LVDS;
1499 val = I915_READ(reg);
1519b995
KP		 1500 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1501 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1502 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1503 POSTING_READ(reg);
1504 udelay(100);
1505 }
1506
1507 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1508 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1509 disable_pch_hdmi(dev_priv, pipe, HDMID);
1510}
1511
43a9539f
CW		 1512static void i8xx_disable_fbc(struct drm_device *dev)
1513{
1514 struct drm_i915_private *dev_priv = dev->dev_private;
1515 u32 fbc_ctl;
1516
1517 /* Disable compression */
1518 fbc_ctl = I915_READ(FBC_CONTROL);
1519 if ((fbc_ctl & FBC_CTL_EN) == 0)
1520 return;
1521
1522 fbc_ctl &= ~FBC_CTL_EN;
1523 I915_WRITE(FBC_CONTROL, fbc_ctl);
1524
1525 /* Wait for compressing bit to clear */
1526 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1527 DRM_DEBUG_KMS("FBC idle timed out\n");
1528 return;
1529 }
1530
1531 DRM_DEBUG_KMS("disabled FBC\n");
1532}
1533
80824003
JB		 1534static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1535{
1536 struct drm_device *dev = crtc->dev;
1537 struct drm_i915_private *dev_priv = dev->dev_private;
1538 struct drm_framebuffer *fb = crtc->fb;
1539 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1540 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003 1541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
016b9b61 1542 int cfb_pitch;
80824003
JB		 1543 int plane, i;
1544 u32 fbc_ctl, fbc_ctl2;
1545
016b9b61 1546 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
01f2c773
VS		 1547 if (fb->pitches[0] < cfb_pitch)
1548 cfb_pitch = fb->pitches[0];
80824003
JB		 1549
1550 /* FBC_CTL wants 64B units */
016b9b61
CW		 1551 cfb_pitch = (cfb_pitch / 64) - 1;
1552 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
80824003
JB		 1553
1554 /* Clear old tags */
1555 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1556 I915_WRITE(FBC_TAG + (i * 4), 0);
1557
1558 /* Set it up... */
de568510
CW		 1559 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1560 fbc_ctl2 |= plane;
80824003
JB		 1561 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1562 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1563
1564 /* enable it... */
1565 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1566 if (IS_I945GM(dev))
49677901 1567 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
016b9b61 1568 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
80824003 1569 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
016b9b61 1570 fbc_ctl |= obj->fence_reg;
80824003
JB		 1571 I915_WRITE(FBC_CONTROL, fbc_ctl);
1572
016b9b61
CW		 1573 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1574 cfb_pitch, crtc->y, intel_crtc->plane);
80824003
JB		 1575}
1576
ee5382ae 1577static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1578{
80824003
JB		 1579 struct drm_i915_private *dev_priv = dev->dev_private;
1580
1581 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1582}
1583
74dff282
JB		 1584static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1585{
1586 struct drm_device *dev = crtc->dev;
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1588 struct drm_framebuffer *fb = crtc->fb;
1589 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1590 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1592 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB		 1593 unsigned long stall_watermark = 200;
1594 u32 dpfc_ctl;
1595
74dff282 1596 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
016b9b61 1597 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
de568510 1598 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
74dff282 1599
74dff282
JB		 1600 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1601 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1602 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1603 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1604
1605 /* enable it... */
1606 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1607
28c97730 1608 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB		 1609}
1610
43a9539f 1611static void g4x_disable_fbc(struct drm_device *dev)
74dff282
JB		 1612{
1613 struct drm_i915_private *dev_priv = dev->dev_private;
1614 u32 dpfc_ctl;
1615
1616 /* Disable compression */
1617 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW		 1618 if (dpfc_ctl & DPFC_CTL_EN) {
1619 dpfc_ctl &= ~DPFC_CTL_EN;
1620 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1621
bed4a673
CW		 1622 DRM_DEBUG_KMS("disabled FBC\n");
1623 }
74dff282
JB		 1624}
1625
ee5382ae 1626static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1627{
74dff282
JB		 1628 struct drm_i915_private *dev_priv = dev->dev_private;
1629
1630 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1631}
1632
4efe0708
JB		 1633static void sandybridge_blit_fbc_update(struct drm_device *dev)
1634{
1635 struct drm_i915_private *dev_priv = dev->dev_private;
1636 u32 blt_ecoskpd;
1637
1638 /* Make sure blitter notifies FBC of writes */
fcca7926 1639 gen6_gt_force_wake_get(dev_priv);
4efe0708
JB		 1640 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1641 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1642 GEN6_BLITTER_LOCK_SHIFT;
1643 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1644 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1645 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1646 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1647 GEN6_BLITTER_LOCK_SHIFT);
1648 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1649 POSTING_READ(GEN6_BLITTER_ECOSKPD);
fcca7926 1650 gen6_gt_force_wake_put(dev_priv);
4efe0708
JB		 1651}
1652
b52eb4dc
ZY		 1653static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1654{
1655 struct drm_device *dev = crtc->dev;
1656 struct drm_i915_private *dev_priv = dev->dev_private;
1657 struct drm_framebuffer *fb = crtc->fb;
1658 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1659 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1661 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY		 1662 unsigned long stall_watermark = 200;
1663 u32 dpfc_ctl;
1664
bed4a673 1665 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
b52eb4dc
ZY		 1666 dpfc_ctl &= DPFC_RESERVED;
1667 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
9ce9d069
CW		 1668 /* Set persistent mode for front-buffer rendering, ala X. */
1669 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
016b9b61 1670 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
de568510 1671 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
b52eb4dc 1672
b52eb4dc
ZY		 1673 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1674 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1675 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1676 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1677 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1678 /* enable it... */
bed4a673 1679 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc 1680
9c04f015
YL		 1681 if (IS_GEN6(dev)) {
1682 I915_WRITE(SNB_DPFC_CTL_SA,
016b9b61 1683 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
9c04f015 1684 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
4efe0708 1685 sandybridge_blit_fbc_update(dev);
9c04f015
YL		 1686 }
1687
b52eb4dc
ZY		 1688 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1689}
1690
43a9539f 1691static void ironlake_disable_fbc(struct drm_device *dev)
b52eb4dc
ZY		 1692{
1693 struct drm_i915_private *dev_priv = dev->dev_private;
1694 u32 dpfc_ctl;
1695
1696 /* Disable compression */
1697 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW		 1698 if (dpfc_ctl & DPFC_CTL_EN) {
1699 dpfc_ctl &= ~DPFC_CTL_EN;
1700 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1701
bed4a673
CW		 1702 DRM_DEBUG_KMS("disabled FBC\n");
1703 }
b52eb4dc
ZY		 1704}
1705
1706static bool ironlake_fbc_enabled(struct drm_device *dev)
1707{
1708 struct drm_i915_private *dev_priv = dev->dev_private;
1709
1710 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1711}
1712
ee5382ae
AJ		 1713bool intel_fbc_enabled(struct drm_device *dev)
1714{
1715 struct drm_i915_private *dev_priv = dev->dev_private;
1716
1717 if (!dev_priv->display.fbc_enabled)
1718 return false;
1719
1720 return dev_priv->display.fbc_enabled(dev);
1721}
1722
1630fe75
CW		 1723static void intel_fbc_work_fn(struct work_struct *__work)
1724{
1725 struct intel_fbc_work *work =
1726 container_of(to_delayed_work(__work),
1727 struct intel_fbc_work, work);
1728 struct drm_device *dev = work->crtc->dev;
1729 struct drm_i915_private *dev_priv = dev->dev_private;
1730
1731 mutex_lock(&dev->struct_mutex);
1732 if (work == dev_priv->fbc_work) {
1733 /* Double check that we haven't switched fb without cancelling
1734 * the prior work.
1735 */
016b9b61 1736 if (work->crtc->fb == work->fb) {
1630fe75
CW		 1737 dev_priv->display.enable_fbc(work->crtc,
1738 work->interval);
1739
016b9b61
CW		 1740 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1741 dev_priv->cfb_fb = work->crtc->fb->base.id;
1742 dev_priv->cfb_y = work->crtc->y;
1743 }
1744
1630fe75
CW		 1745 dev_priv->fbc_work = NULL;
1746 }
1747 mutex_unlock(&dev->struct_mutex);
1748
1749 kfree(work);
1750}
1751
1752static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1753{
1754 if (dev_priv->fbc_work == NULL)
1755 return;
1756
1757 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1758
1759 /* Synchronisation is provided by struct_mutex and checking of
1760 * dev_priv->fbc_work, so we can perform the cancellation
1761 * entirely asynchronously.
1762 */
1763 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1764 /* tasklet was killed before being run, clean up */
1765 kfree(dev_priv->fbc_work);
1766
1767 /* Mark the work as no longer wanted so that if it does
1768 * wake-up (because the work was already running and waiting
1769 * for our mutex), it will discover that is no longer
1770 * necessary to run.
1771 */
1772 dev_priv->fbc_work = NULL;
1773}
1774
43a9539f 1775static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
ee5382ae 1776{
1630fe75
CW		 1777 struct intel_fbc_work *work;
1778 struct drm_device *dev = crtc->dev;
1779 struct drm_i915_private *dev_priv = dev->dev_private;
ee5382ae
AJ		 1780
1781 if (!dev_priv->display.enable_fbc)
1782 return;
1783
1630fe75
CW		 1784 intel_cancel_fbc_work(dev_priv);
1785
1786 work = kzalloc(sizeof *work, GFP_KERNEL);
1787 if (work == NULL) {
1788 dev_priv->display.enable_fbc(crtc, interval);
1789 return;
1790 }
1791
1792 work->crtc = crtc;
1793 work->fb = crtc->fb;
1794 work->interval = interval;
1795 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1796
1797 dev_priv->fbc_work = work;
1798
1799 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1800
1801 /* Delay the actual enabling to let pageflipping cease and the
016b9b61
CW		 1802 * display to settle before starting the compression. Note that
1803 * this delay also serves a second purpose: it allows for a
1804 * vblank to pass after disabling the FBC before we attempt
1805 * to modify the control registers.
1630fe75
CW		 1806 *
1807 * A more complicated solution would involve tracking vblanks
1808 * following the termination of the page-flipping sequence
1809 * and indeed performing the enable as a co-routine and not
1810 * waiting synchronously upon the vblank.
1811 */
1812 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
ee5382ae
AJ		 1813}
1814
1815void intel_disable_fbc(struct drm_device *dev)
1816{
1817 struct drm_i915_private *dev_priv = dev->dev_private;
1818
1630fe75
CW		 1819 intel_cancel_fbc_work(dev_priv);
1820
ee5382ae
AJ		 1821 if (!dev_priv->display.disable_fbc)
1822 return;
1823
1824 dev_priv->display.disable_fbc(dev);
016b9b61 1825 dev_priv->cfb_plane = -1;
ee5382ae
AJ		 1826}
1827
80824003
JB		 1828/**
1829 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1830 * @dev: the drm_device
80824003
JB		 1831 *
1832 * Set up the framebuffer compression hardware at mode set time. We
1833 * enable it if possible:
1834 * - plane A only (on pre-965)
1835 * - no pixel mulitply/line duplication
1836 * - no alpha buffer discard
1837 * - no dual wide
1838 * - framebuffer <= 2048 in width, 1536 in height
1839 *
1840 * We can't assume that any compression will take place (worst case),
1841 * so the compressed buffer has to be the same size as the uncompressed
1842 * one. It also must reside (along with the line length buffer) in
1843 * stolen memory.
1844 *
1845 * We need to enable/disable FBC on a global basis.
1846 */
bed4a673 1847static void intel_update_fbc(struct drm_device *dev)
80824003 1848{
80824003 1849 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW		 1850 struct drm_crtc *crtc = NULL, *tmp_crtc;
1851 struct intel_crtc *intel_crtc;
1852 struct drm_framebuffer *fb;
80824003 1853 struct intel_framebuffer *intel_fb;
05394f39 1854 struct drm_i915_gem_object *obj;
cd0de039 1855 int enable_fbc;
9c928d16
JB		 1856
1857 DRM_DEBUG_KMS("\n");
80824003
JB		 1858
1859 if (!i915_powersave)
1860 return;
1861
ee5382ae 1862 if (!I915_HAS_FBC(dev))
e70236a8
JB		 1863 return;
1864
80824003
JB		 1865 /*
1866 * If FBC is already on, we just have to verify that we can
1867 * keep it that way...
1868 * Need to disable if:
9c928d16 1869 * - more than one pipe is active
80824003
JB		 1870 * - changing FBC params (stride, fence, mode)
1871 * - new fb is too large to fit in compressed buffer
1872 * - going to an unsupported config (interlace, pixel multiply, etc.)
1873 */
9c928d16 1874 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
d210246a 1875 if (tmp_crtc->enabled && tmp_crtc->fb) {
bed4a673
CW		 1876 if (crtc) {
1877 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1878 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1879 goto out_disable;
1880 }
1881 crtc = tmp_crtc;
1882 }
9c928d16 1883 }
bed4a673
CW		 1884
1885 if (!crtc || crtc->fb == NULL) {
1886 DRM_DEBUG_KMS("no output, disabling\n");
1887 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB		 1888 goto out_disable;
1889 }
bed4a673
CW		 1890
1891 intel_crtc = to_intel_crtc(crtc);
1892 fb = crtc->fb;
1893 intel_fb = to_intel_framebuffer(fb);
05394f39 1894 obj = intel_fb->obj;
bed4a673 1895
cd0de039
KP		 1896 enable_fbc = i915_enable_fbc;
1897 if (enable_fbc < 0) {
1898 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1899 enable_fbc = 1;
1900 if (INTEL_INFO(dev)->gen <= 5)
1901 enable_fbc = 0;
1902 }
1903 if (!enable_fbc) {
1904 DRM_DEBUG_KMS("fbc disabled per module param\n");
c1a9f047
JB		 1905 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1906 goto out_disable;
1907 }
05394f39 1908 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 1909 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 1910 "compression\n");
b5e50c3f 1911 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1912 goto out_disable;
1913 }
bed4a673
CW		 1914 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1915 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 1916 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 1917 "disabling\n");
b5e50c3f 1918 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB		 1919 goto out_disable;
1920 }
bed4a673
CW		 1921 if ((crtc->mode.hdisplay > 2048) ||
1922 (crtc->mode.vdisplay > 1536)) {
28c97730 1923 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 1924 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB		 1925 goto out_disable;
1926 }
bed4a673 1927 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 1928 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 1929 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB		 1930 goto out_disable;
1931 }
de568510
CW		 1932
1933 /* The use of a CPU fence is mandatory in order to detect writes
1934 * by the CPU to the scanout and trigger updates to the FBC.
1935 */
1936 if (obj->tiling_mode != I915_TILING_X ||
1937 obj->fence_reg == I915_FENCE_REG_NONE) {
1938 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
b5e50c3f 1939 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB		 1940 goto out_disable;
1941 }
1942
c924b934
JW		 1943 /* If the kernel debugger is active, always disable compression */
1944 if (in_dbg_master())
1945 goto out_disable;
1946
016b9b61
CW		 1947 /* If the scanout has not changed, don't modify the FBC settings.
1948 * Note that we make the fundamental assumption that the fb->obj
1949 * cannot be unpinned (and have its GTT offset and fence revoked)
1950 * without first being decoupled from the scanout and FBC disabled.
1951 */
1952 if (dev_priv->cfb_plane == intel_crtc->plane &&
1953 dev_priv->cfb_fb == fb->base.id &&
1954 dev_priv->cfb_y == crtc->y)
1955 return;
1956
1957 if (intel_fbc_enabled(dev)) {
1958 /* We update FBC along two paths, after changing fb/crtc
1959 * configuration (modeswitching) and after page-flipping
1960 * finishes. For the latter, we know that not only did
1961 * we disable the FBC at the start of the page-flip
1962 * sequence, but also more than one vblank has passed.
1963 *
1964 * For the former case of modeswitching, it is possible
1965 * to switch between two FBC valid configurations
1966 * instantaneously so we do need to disable the FBC
1967 * before we can modify its control registers. We also
1968 * have to wait for the next vblank for that to take
1969 * effect. However, since we delay enabling FBC we can
1970 * assume that a vblank has passed since disabling and
1971 * that we can safely alter the registers in the deferred
1972 * callback.
1973 *
1974 * In the scenario that we go from a valid to invalid
1975 * and then back to valid FBC configuration we have
1976 * no strict enforcement that a vblank occurred since
1977 * disabling the FBC. However, along all current pipe
1978 * disabling paths we do need to wait for a vblank at
1979 * some point. And we wait before enabling FBC anyway.
1980 */
1981 DRM_DEBUG_KMS("disabling active FBC for update\n");
1982 intel_disable_fbc(dev);
1983 }
1984
bed4a673 1985 intel_enable_fbc(crtc, 500);
80824003
JB		 1986 return;
1987
1988out_disable:
80824003 1989 /* Multiple disables should be harmless */
a939406f
CW		 1990 if (intel_fbc_enabled(dev)) {
1991 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 1992 intel_disable_fbc(dev);
a939406f 1993 }
80824003
JB		 1994}
1995
127bd2ac 1996int
48b956c5 1997intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1998 struct drm_i915_gem_object *obj,
919926ae 1999 struct intel_ring_buffer *pipelined)
6b95a207 2000{
ce453d81 2001 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 2002 u32 alignment;
2003 int ret;
2004
05394f39 2005 switch (obj->tiling_mode) {
6b95a207 2006 case I915_TILING_NONE:
534843da
CW		 2007 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2008 alignment = 128 * 1024;
a6c45cf0 2009 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2010 alignment = 4 * 1024;
2011 else
2012 alignment = 64 * 1024;
6b95a207
KH		 2013 break;
2014 case I915_TILING_X:
2015 /* pin() will align the object as required by fence */
2016 alignment = 0;
2017 break;
2018 case I915_TILING_Y:
2019 /* FIXME: Is this true? */
2020 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2021 return -EINVAL;
2022 default:
2023 BUG();
2024 }
2025
ce453d81 2026 dev_priv->mm.interruptible = false;
2da3b9b9 2027 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 2028 if (ret)
ce453d81 2029 goto err_interruptible;
6b95a207
KH		 2030
2031 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2032 * fence, whereas 965+ only requires a fence if using
2033 * framebuffer compression. For simplicity, we always install
2034 * a fence as the cost is not that onerous.
2035 */
05394f39 2036 if (obj->tiling_mode != I915_TILING_NONE) {
ce453d81 2037 ret = i915_gem_object_get_fence(obj, pipelined);
48b956c5
CW		 2038 if (ret)
2039 goto err_unpin;
6b95a207
KH		 2040 }
2041
ce453d81 2042 dev_priv->mm.interruptible = true;
6b95a207 2043 return 0;
48b956c5
CW		 2044
2045err_unpin:
2046 i915_gem_object_unpin(obj);
ce453d81
CW		 2047err_interruptible:
2048 dev_priv->mm.interruptible = true;
48b956c5 2049 return ret;
6b95a207
KH		 2050}
2051
17638cd6
JB		 2052static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2053 int x, int y)
81255565
JB		 2054{
2055 struct drm_device *dev = crtc->dev;
2056 struct drm_i915_private *dev_priv = dev->dev_private;
2057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2058 struct intel_framebuffer *intel_fb;
05394f39 2059 struct drm_i915_gem_object *obj;
81255565
JB		 2060 int plane = intel_crtc->plane;
2061 unsigned long Start, Offset;
81255565 2062 u32 dspcntr;
5eddb70b 2063 u32 reg;
81255565
JB		 2064
2065 switch (plane) {
2066 case 0:
2067 case 1:
2068 break;
2069 default:
2070 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2071 return -EINVAL;
2072 }
2073
2074 intel_fb = to_intel_framebuffer(fb);
2075 obj = intel_fb->obj;
81255565 2076
5eddb70b
CW		 2077 reg = DSPCNTR(plane);
2078 dspcntr = I915_READ(reg);
81255565
JB		 2079 /* Mask out pixel format bits in case we change it */
2080 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2081 switch (fb->bits_per_pixel) {
2082 case 8:
2083 dspcntr |= DISPPLANE_8BPP;
2084 break;
2085 case 16:
2086 if (fb->depth == 15)
2087 dspcntr |= DISPPLANE_15_16BPP;
2088 else
2089 dspcntr |= DISPPLANE_16BPP;
2090 break;
2091 case 24:
2092 case 32:
2093 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2094 break;
2095 default:
17638cd6 2096 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2097 return -EINVAL;
2098 }
a6c45cf0 2099 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2100 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2101 dspcntr |= DISPPLANE_TILED;
2102 else
2103 dspcntr &= ~DISPPLANE_TILED;
2104 }
2105
5eddb70b 2106 I915_WRITE(reg, dspcntr);
81255565 2107
05394f39 2108 Start = obj->gtt_offset;
01f2c773 2109 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2110
4e6cfefc 2111 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 2112 Start, Offset, x, y, fb->pitches[0]);
2113 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2114 if (INTEL_INFO(dev)->gen >= 4) {
5eddb70b
CW		 2115 I915_WRITE(DSPSURF(plane), Start);
2116 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2117 I915_WRITE(DSPADDR(plane), Offset);
2118 } else
2119 I915_WRITE(DSPADDR(plane), Start + Offset);
2120 POSTING_READ(reg);
81255565 2121
17638cd6
JB		 2122 return 0;
2123}
2124
2125static int ironlake_update_plane(struct drm_crtc *crtc,
2126 struct drm_framebuffer *fb, int x, int y)
2127{
2128 struct drm_device *dev = crtc->dev;
2129 struct drm_i915_private *dev_priv = dev->dev_private;
2130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2131 struct intel_framebuffer *intel_fb;
2132 struct drm_i915_gem_object *obj;
2133 int plane = intel_crtc->plane;
2134 unsigned long Start, Offset;
2135 u32 dspcntr;
2136 u32 reg;
2137
2138 switch (plane) {
2139 case 0:
2140 case 1:
27f8227b 2141 case 2:
17638cd6
JB		 2142 break;
2143 default:
2144 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2145 return -EINVAL;
2146 }
2147
2148 intel_fb = to_intel_framebuffer(fb);
2149 obj = intel_fb->obj;
2150
2151 reg = DSPCNTR(plane);
2152 dspcntr = I915_READ(reg);
2153 /* Mask out pixel format bits in case we change it */
2154 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2155 switch (fb->bits_per_pixel) {
2156 case 8:
2157 dspcntr |= DISPPLANE_8BPP;
2158 break;
2159 case 16:
2160 if (fb->depth != 16)
2161 return -EINVAL;
2162
2163 dspcntr |= DISPPLANE_16BPP;
2164 break;
2165 case 24:
2166 case 32:
2167 if (fb->depth == 24)
2168 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2169 else if (fb->depth == 30)
2170 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2171 else
2172 return -EINVAL;
2173 break;
2174 default:
2175 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2176 return -EINVAL;
2177 }
2178
2179 if (obj->tiling_mode != I915_TILING_NONE)
2180 dspcntr |= DISPPLANE_TILED;
2181 else
2182 dspcntr &= ~DISPPLANE_TILED;
2183
2184 /* must disable */
2185 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2186
2187 I915_WRITE(reg, dspcntr);
2188
2189 Start = obj->gtt_offset;
01f2c773 2190 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
17638cd6
JB		 2191
2192 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 2193 Start, Offset, x, y, fb->pitches[0]);
2194 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
17638cd6
JB		 2195 I915_WRITE(DSPSURF(plane), Start);
2196 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2197 I915_WRITE(DSPADDR(plane), Offset);
2198 POSTING_READ(reg);
2199
2200 return 0;
2201}
2202
2203/* Assume fb object is pinned & idle & fenced and just update base pointers */
2204static int
2205intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2206 int x, int y, enum mode_set_atomic state)
2207{
2208 struct drm_device *dev = crtc->dev;
2209 struct drm_i915_private *dev_priv = dev->dev_private;
2210 int ret;
2211
2212 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2213 if (ret)
2214 return ret;
2215
bed4a673 2216 intel_update_fbc(dev);
3dec0095 2217 intel_increase_pllclock(crtc);
81255565
JB		 2218
2219 return 0;
2220}
2221
5c3b82e2 2222static int
3c4fdcfb
KH		 2223intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2224 struct drm_framebuffer *old_fb)
79e53945
JB		 2225{
2226 struct drm_device *dev = crtc->dev;
79e53945
JB		 2227 struct drm_i915_master_private *master_priv;
2228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2229 int ret;
79e53945
JB		 2230
2231 /* no fb bound */
2232 if (!crtc->fb) {
a5071c2f 2233 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2234 return 0;
2235 }
2236
265db958 2237 switch (intel_crtc->plane) {
5c3b82e2
CW		 2238 case 0:
2239 case 1:
2240 break;
27f8227b
JB		 2241 case 2:
2242 if (IS_IVYBRIDGE(dev))
2243 break;
2244 /* fall through otherwise */
5c3b82e2 2245 default:
a5071c2f 2246 DRM_ERROR("no plane for crtc\n");
5c3b82e2 2247 return -EINVAL;
79e53945
JB		 2248 }
2249
5c3b82e2 2250 mutex_lock(&dev->struct_mutex);
265db958
CW		 2251 ret = intel_pin_and_fence_fb_obj(dev,
2252 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2253 NULL);
5c3b82e2
CW		 2254 if (ret != 0) {
2255 mutex_unlock(&dev->struct_mutex);
a5071c2f 2256 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2257 return ret;
2258 }
79e53945 2259
265db958 2260 if (old_fb) {
e6c3a2a6 2261 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 2262 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
265db958 2263
e6c3a2a6 2264 wait_event(dev_priv->pending_flip_queue,
01eec727 2265 atomic_read(&dev_priv->mm.wedged) ||
05394f39 2266 atomic_read(&obj->pending_flip) == 0);
85345517
CW		 2267
2268 /* Big Hammer, we also need to ensure that any pending
2269 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2270 * current scanout is retired before unpinning the old
2271 * framebuffer.
01eec727
CW		 2272 *
2273 * This should only fail upon a hung GPU, in which case we
2274 * can safely continue.
85345517 2275 */
a8198eea 2276 ret = i915_gem_object_finish_gpu(obj);
01eec727 2277 (void) ret;
265db958
CW		 2278 }
2279
21c74a8e
JW		 2280 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2281 LEAVE_ATOMIC_MODE_SET);
4e6cfefc 2282 if (ret) {
265db958 2283 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2284 mutex_unlock(&dev->struct_mutex);
a5071c2f 2285 DRM_ERROR("failed to update base address\n");
4e6cfefc 2286 return ret;
79e53945 2287 }
3c4fdcfb 2288
b7f1de28
CW		 2289 if (old_fb) {
2290 intel_wait_for_vblank(dev, intel_crtc->pipe);
265db958 2291 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2292 }
652c393a 2293
5c3b82e2 2294 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2295
2296 if (!dev->primary->master)
5c3b82e2 2297 return 0;
79e53945
JB		 2298
2299 master_priv = dev->primary->master->driver_priv;
2300 if (!master_priv->sarea_priv)
5c3b82e2 2301 return 0;
79e53945 2302
265db958 2303 if (intel_crtc->pipe) {
79e53945
JB		 2304 master_priv->sarea_priv->pipeB_x = x;
2305 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2306 } else {
2307 master_priv->sarea_priv->pipeA_x = x;
2308 master_priv->sarea_priv->pipeA_y = y;
79e53945 2309 }
5c3b82e2
CW		 2310
2311 return 0;
79e53945
JB		 2312}
2313
5eddb70b 2314static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2315{
2316 struct drm_device *dev = crtc->dev;
2317 struct drm_i915_private *dev_priv = dev->dev_private;
2318 u32 dpa_ctl;
2319
28c97730 2320 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2321 dpa_ctl = I915_READ(DP_A);
2322 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2323
2324 if (clock < 200000) {
2325 u32 temp;
2326 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2327 /* workaround for 160Mhz:
2328 1) program 0x4600c bits 15:0 = 0x8124
2329 2) program 0x46010 bit 0 = 1
2330 3) program 0x46034 bit 24 = 1
2331 4) program 0x64000 bit 14 = 1
2332 */
2333 temp = I915_READ(0x4600c);
2334 temp &= 0xffff0000;
2335 I915_WRITE(0x4600c, temp | 0x8124);
2336
2337 temp = I915_READ(0x46010);
2338 I915_WRITE(0x46010, temp | 1);
2339
2340 temp = I915_READ(0x46034);
2341 I915_WRITE(0x46034, temp | (1 << 24));
2342 } else {
2343 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2344 }
2345 I915_WRITE(DP_A, dpa_ctl);
2346
5eddb70b 2347 POSTING_READ(DP_A);
32f9d658
ZW		 2348 udelay(500);
2349}
2350
5e84e1a4
ZW		 2351static void intel_fdi_normal_train(struct drm_crtc *crtc)
2352{
2353 struct drm_device *dev = crtc->dev;
2354 struct drm_i915_private *dev_priv = dev->dev_private;
2355 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2356 int pipe = intel_crtc->pipe;
2357 u32 reg, temp;
2358
2359 /* enable normal train */
2360 reg = FDI_TX_CTL(pipe);
2361 temp = I915_READ(reg);
61e499bf 2362 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2363 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2364 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2365 } else {
2366 temp &= ~FDI_LINK_TRAIN_NONE;
2367 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2368 }
5e84e1a4
ZW		 2369 I915_WRITE(reg, temp);
2370
2371 reg = FDI_RX_CTL(pipe);
2372 temp = I915_READ(reg);
2373 if (HAS_PCH_CPT(dev)) {
2374 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2375 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2376 } else {
2377 temp &= ~FDI_LINK_TRAIN_NONE;
2378 temp |= FDI_LINK_TRAIN_NONE;
2379 }
2380 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2381
2382 /* wait one idle pattern time */
2383 POSTING_READ(reg);
2384 udelay(1000);
357555c0
JB		 2385
2386 /* IVB wants error correction enabled */
2387 if (IS_IVYBRIDGE(dev))
2388 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2389 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2390}
2391
291427f5
JB		 2392static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2393{
2394 struct drm_i915_private *dev_priv = dev->dev_private;
2395 u32 flags = I915_READ(SOUTH_CHICKEN1);
2396
2397 flags |= FDI_PHASE_SYNC_OVR(pipe);
2398 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2399 flags |= FDI_PHASE_SYNC_EN(pipe);
2400 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2401 POSTING_READ(SOUTH_CHICKEN1);
2402}
2403
8db9d77b
ZW		 2404/* The FDI link training functions for ILK/Ibexpeak. */
2405static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2406{
2407 struct drm_device *dev = crtc->dev;
2408 struct drm_i915_private *dev_priv = dev->dev_private;
2409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2410 int pipe = intel_crtc->pipe;
0fc932b8 2411 int plane = intel_crtc->plane;
5eddb70b 2412 u32 reg, temp, tries;
8db9d77b 2413
0fc932b8
JB		 2414 /* FDI needs bits from pipe & plane first */
2415 assert_pipe_enabled(dev_priv, pipe);
2416 assert_plane_enabled(dev_priv, plane);
2417
e1a44743
AJ		 2418 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2419 for train result */
5eddb70b
CW		 2420 reg = FDI_RX_IMR(pipe);
2421 temp = I915_READ(reg);
e1a44743
AJ		 2422 temp &= ~FDI_RX_SYMBOL_LOCK;
2423 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2424 I915_WRITE(reg, temp);
2425 I915_READ(reg);
e1a44743
AJ		 2426 udelay(150);
2427
8db9d77b 2428 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2429 reg = FDI_TX_CTL(pipe);
2430 temp = I915_READ(reg);
77ffb597
AJ		 2431 temp &= ~(7 << 19);
2432 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2433 temp &= ~FDI_LINK_TRAIN_NONE;
2434 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2435 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2436
5eddb70b
CW		 2437 reg = FDI_RX_CTL(pipe);
2438 temp = I915_READ(reg);
8db9d77b
ZW		 2439 temp &= ~FDI_LINK_TRAIN_NONE;
2440 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2441 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2442
2443 POSTING_READ(reg);
8db9d77b
ZW		 2444 udelay(150);
2445
5b2adf89 2446 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2447 if (HAS_PCH_IBX(dev)) {
2448 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2449 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2450 FDI_RX_PHASE_SYNC_POINTER_EN);
2451 }
5b2adf89 2452
5eddb70b 2453 reg = FDI_RX_IIR(pipe);
e1a44743 2454 for (tries = 0; tries < 5; tries++) {
5eddb70b 2455 temp = I915_READ(reg);
8db9d77b
ZW		 2456 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2457
2458 if ((temp & FDI_RX_BIT_LOCK)) {
2459 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2460 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2461 break;
2462 }
8db9d77b 2463 }
e1a44743 2464 if (tries == 5)
5eddb70b 2465 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2466
2467 /* Train 2 */
5eddb70b
CW		 2468 reg = FDI_TX_CTL(pipe);
2469 temp = I915_READ(reg);
8db9d77b
ZW		 2470 temp &= ~FDI_LINK_TRAIN_NONE;
2471 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2472 I915_WRITE(reg, temp);
8db9d77b 2473
5eddb70b
CW		 2474 reg = FDI_RX_CTL(pipe);
2475 temp = I915_READ(reg);
8db9d77b
ZW		 2476 temp &= ~FDI_LINK_TRAIN_NONE;
2477 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2478 I915_WRITE(reg, temp);
8db9d77b 2479
5eddb70b
CW		 2480 POSTING_READ(reg);
2481 udelay(150);
8db9d77b 2482
5eddb70b 2483 reg = FDI_RX_IIR(pipe);
e1a44743 2484 for (tries = 0; tries < 5; tries++) {
5eddb70b 2485 temp = I915_READ(reg);
8db9d77b
ZW		 2486 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2487
2488 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2489 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2490 DRM_DEBUG_KMS("FDI train 2 done.\n");
2491 break;
2492 }
8db9d77b 2493 }
e1a44743 2494 if (tries == 5)
5eddb70b 2495 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2496
2497 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2498
8db9d77b
ZW		 2499}
2500
0206e353 2501static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2502 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2503 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2504 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2505 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2506};
2507
2508/* The FDI link training functions for SNB/Cougarpoint. */
2509static void gen6_fdi_link_train(struct drm_crtc *crtc)
2510{
2511 struct drm_device *dev = crtc->dev;
2512 struct drm_i915_private *dev_priv = dev->dev_private;
2513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2514 int pipe = intel_crtc->pipe;
5eddb70b 2515 u32 reg, temp, i;
8db9d77b 2516
e1a44743
AJ		 2517 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2518 for train result */
5eddb70b
CW		 2519 reg = FDI_RX_IMR(pipe);
2520 temp = I915_READ(reg);
e1a44743
AJ		 2521 temp &= ~FDI_RX_SYMBOL_LOCK;
2522 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2523 I915_WRITE(reg, temp);
2524
2525 POSTING_READ(reg);
e1a44743
AJ		 2526 udelay(150);
2527
8db9d77b 2528 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2529 reg = FDI_TX_CTL(pipe);
2530 temp = I915_READ(reg);
77ffb597
AJ		 2531 temp &= ~(7 << 19);
2532 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2533 temp &= ~FDI_LINK_TRAIN_NONE;
2534 temp |= FDI_LINK_TRAIN_PATTERN_1;
2535 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2536 /* SNB-B */
2537 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2538 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2539
5eddb70b
CW		 2540 reg = FDI_RX_CTL(pipe);
2541 temp = I915_READ(reg);
8db9d77b
ZW		 2542 if (HAS_PCH_CPT(dev)) {
2543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2545 } else {
2546 temp &= ~FDI_LINK_TRAIN_NONE;
2547 temp |= FDI_LINK_TRAIN_PATTERN_1;
2548 }
5eddb70b
CW		 2549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2550
2551 POSTING_READ(reg);
8db9d77b
ZW		 2552 udelay(150);
2553
291427f5
JB		 2554 if (HAS_PCH_CPT(dev))
2555 cpt_phase_pointer_enable(dev, pipe);
2556
0206e353 2557 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2558 reg = FDI_TX_CTL(pipe);
2559 temp = I915_READ(reg);
8db9d77b
ZW		 2560 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2561 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2562 I915_WRITE(reg, temp);
2563
2564 POSTING_READ(reg);
8db9d77b
ZW		 2565 udelay(500);
2566
5eddb70b
CW		 2567 reg = FDI_RX_IIR(pipe);
2568 temp = I915_READ(reg);
8db9d77b
ZW		 2569 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2570
2571 if (temp & FDI_RX_BIT_LOCK) {
5eddb70b 2572 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2573 DRM_DEBUG_KMS("FDI train 1 done.\n");
2574 break;
2575 }
2576 }
2577 if (i == 4)
5eddb70b 2578 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2579
2580 /* Train 2 */
5eddb70b
CW		 2581 reg = FDI_TX_CTL(pipe);
2582 temp = I915_READ(reg);
8db9d77b
ZW		 2583 temp &= ~FDI_LINK_TRAIN_NONE;
2584 temp |= FDI_LINK_TRAIN_PATTERN_2;
2585 if (IS_GEN6(dev)) {
2586 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2587 /* SNB-B */
2588 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2589 }
5eddb70b 2590 I915_WRITE(reg, temp);
8db9d77b 2591
5eddb70b
CW		 2592 reg = FDI_RX_CTL(pipe);
2593 temp = I915_READ(reg);
8db9d77b
ZW		 2594 if (HAS_PCH_CPT(dev)) {
2595 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2596 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2597 } else {
2598 temp &= ~FDI_LINK_TRAIN_NONE;
2599 temp |= FDI_LINK_TRAIN_PATTERN_2;
2600 }
5eddb70b
CW		 2601 I915_WRITE(reg, temp);
2602
2603 POSTING_READ(reg);
8db9d77b
ZW		 2604 udelay(150);
2605
0206e353 2606 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2607 reg = FDI_TX_CTL(pipe);
2608 temp = I915_READ(reg);
8db9d77b
ZW		 2609 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2610 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2611 I915_WRITE(reg, temp);
2612
2613 POSTING_READ(reg);
8db9d77b
ZW		 2614 udelay(500);
2615
5eddb70b
CW		 2616 reg = FDI_RX_IIR(pipe);
2617 temp = I915_READ(reg);
8db9d77b
ZW		 2618 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2619
2620 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2621 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2622 DRM_DEBUG_KMS("FDI train 2 done.\n");
2623 break;
2624 }
2625 }
2626 if (i == 4)
5eddb70b 2627 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2628
2629 DRM_DEBUG_KMS("FDI train done.\n");
2630}
2631
357555c0
JB		 2632/* Manual link training for Ivy Bridge A0 parts */
2633static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2634{
2635 struct drm_device *dev = crtc->dev;
2636 struct drm_i915_private *dev_priv = dev->dev_private;
2637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2638 int pipe = intel_crtc->pipe;
2639 u32 reg, temp, i;
2640
2641 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2642 for train result */
2643 reg = FDI_RX_IMR(pipe);
2644 temp = I915_READ(reg);
2645 temp &= ~FDI_RX_SYMBOL_LOCK;
2646 temp &= ~FDI_RX_BIT_LOCK;
2647 I915_WRITE(reg, temp);
2648
2649 POSTING_READ(reg);
2650 udelay(150);
2651
2652 /* enable CPU FDI TX and PCH FDI RX */
2653 reg = FDI_TX_CTL(pipe);
2654 temp = I915_READ(reg);
2655 temp &= ~(7 << 19);
2656 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2657 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2658 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2659 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2660 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2661 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2662 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2663
2664 reg = FDI_RX_CTL(pipe);
2665 temp = I915_READ(reg);
2666 temp &= ~FDI_LINK_TRAIN_AUTO;
2667 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2668 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2669 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2670 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2671
2672 POSTING_READ(reg);
2673 udelay(150);
2674
291427f5
JB		 2675 if (HAS_PCH_CPT(dev))
2676 cpt_phase_pointer_enable(dev, pipe);
2677
0206e353 2678 for (i = 0; i < 4; i++) {
357555c0
JB		 2679 reg = FDI_TX_CTL(pipe);
2680 temp = I915_READ(reg);
2681 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2682 temp |= snb_b_fdi_train_param[i];
2683 I915_WRITE(reg, temp);
2684
2685 POSTING_READ(reg);
2686 udelay(500);
2687
2688 reg = FDI_RX_IIR(pipe);
2689 temp = I915_READ(reg);
2690 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2691
2692 if (temp & FDI_RX_BIT_LOCK ||
2693 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2694 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2695 DRM_DEBUG_KMS("FDI train 1 done.\n");
2696 break;
2697 }
2698 }
2699 if (i == 4)
2700 DRM_ERROR("FDI train 1 fail!\n");
2701
2702 /* Train 2 */
2703 reg = FDI_TX_CTL(pipe);
2704 temp = I915_READ(reg);
2705 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2706 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2707 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2708 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2709 I915_WRITE(reg, temp);
2710
2711 reg = FDI_RX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2714 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2715 I915_WRITE(reg, temp);
2716
2717 POSTING_READ(reg);
2718 udelay(150);
2719
0206e353 2720 for (i = 0; i < 4; i++) {
357555c0
JB		 2721 reg = FDI_TX_CTL(pipe);
2722 temp = I915_READ(reg);
2723 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2724 temp |= snb_b_fdi_train_param[i];
2725 I915_WRITE(reg, temp);
2726
2727 POSTING_READ(reg);
2728 udelay(500);
2729
2730 reg = FDI_RX_IIR(pipe);
2731 temp = I915_READ(reg);
2732 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2733
2734 if (temp & FDI_RX_SYMBOL_LOCK) {
2735 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2736 DRM_DEBUG_KMS("FDI train 2 done.\n");
2737 break;
2738 }
2739 }
2740 if (i == 4)
2741 DRM_ERROR("FDI train 2 fail!\n");
2742
2743 DRM_DEBUG_KMS("FDI train done.\n");
2744}
2745
2746static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2747{
2748 struct drm_device *dev = crtc->dev;
2749 struct drm_i915_private *dev_priv = dev->dev_private;
2750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2751 int pipe = intel_crtc->pipe;
5eddb70b 2752 u32 reg, temp;
79e53945 2753
c64e311e 2754 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2755 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2756 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2757
c98e9dcf 2758 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2759 reg = FDI_RX_CTL(pipe);
2760 temp = I915_READ(reg);
2761 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2762 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2763 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2764 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2765
2766 POSTING_READ(reg);
c98e9dcf
JB		 2767 udelay(200);
2768
2769 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2770 temp = I915_READ(reg);
2771 I915_WRITE(reg, temp | FDI_PCDCLK);
2772
2773 POSTING_READ(reg);
c98e9dcf
JB		 2774 udelay(200);
2775
2776 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2777 reg = FDI_TX_CTL(pipe);
2778 temp = I915_READ(reg);
c98e9dcf 2779 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2780 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2781
2782 POSTING_READ(reg);
c98e9dcf 2783 udelay(100);
6be4a607 2784 }
0e23b99d
JB		 2785}
2786
291427f5
JB		 2787static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2788{
2789 struct drm_i915_private *dev_priv = dev->dev_private;
2790 u32 flags = I915_READ(SOUTH_CHICKEN1);
2791
2792 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2793 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2794 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2795 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2796 POSTING_READ(SOUTH_CHICKEN1);
2797}
0fc932b8
JB		 2798static void ironlake_fdi_disable(struct drm_crtc *crtc)
2799{
2800 struct drm_device *dev = crtc->dev;
2801 struct drm_i915_private *dev_priv = dev->dev_private;
2802 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2803 int pipe = intel_crtc->pipe;
2804 u32 reg, temp;
2805
2806 /* disable CPU FDI tx and PCH FDI rx */
2807 reg = FDI_TX_CTL(pipe);
2808 temp = I915_READ(reg);
2809 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2810 POSTING_READ(reg);
2811
2812 reg = FDI_RX_CTL(pipe);
2813 temp = I915_READ(reg);
2814 temp &= ~(0x7 << 16);
2815 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2816 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2817
2818 POSTING_READ(reg);
2819 udelay(100);
2820
2821 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2822 if (HAS_PCH_IBX(dev)) {
2823 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2824 I915_WRITE(FDI_RX_CHICKEN(pipe),
2825 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2826 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2827 } else if (HAS_PCH_CPT(dev)) {
2828 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2829 }
0fc932b8
JB		 2830
2831 /* still set train pattern 1 */
2832 reg = FDI_TX_CTL(pipe);
2833 temp = I915_READ(reg);
2834 temp &= ~FDI_LINK_TRAIN_NONE;
2835 temp |= FDI_LINK_TRAIN_PATTERN_1;
2836 I915_WRITE(reg, temp);
2837
2838 reg = FDI_RX_CTL(pipe);
2839 temp = I915_READ(reg);
2840 if (HAS_PCH_CPT(dev)) {
2841 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2842 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2843 } else {
2844 temp &= ~FDI_LINK_TRAIN_NONE;
2845 temp |= FDI_LINK_TRAIN_PATTERN_1;
2846 }
2847 /* BPC in FDI rx is consistent with that in PIPECONF */
2848 temp &= ~(0x07 << 16);
2849 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2850 I915_WRITE(reg, temp);
2851
2852 POSTING_READ(reg);
2853 udelay(100);
2854}
2855
6b383a7f
CW		 2856/*
2857 * When we disable a pipe, we need to clear any pending scanline wait events
2858 * to avoid hanging the ring, which we assume we are waiting on.
2859 */
2860static void intel_clear_scanline_wait(struct drm_device *dev)
2861{
2862 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 2863 struct intel_ring_buffer *ring;
6b383a7f
CW		 2864 u32 tmp;
2865
2866 if (IS_GEN2(dev))
2867 /* Can't break the hang on i8xx */
2868 return;
2869
1ec14ad3 2870 ring = LP_RING(dev_priv);
8168bd48
CW		 2871 tmp = I915_READ_CTL(ring);
2872 if (tmp & RING_WAIT)
2873 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 2874}
2875
e6c3a2a6
CW		 2876static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2877{
05394f39 2878 struct drm_i915_gem_object *obj;
e6c3a2a6
CW		 2879 struct drm_i915_private *dev_priv;
2880
2881 if (crtc->fb == NULL)
2882 return;
2883
05394f39 2884 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW		 2885 dev_priv = crtc->dev->dev_private;
2886 wait_event(dev_priv->pending_flip_queue,
05394f39 2887 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW		 2888}
2889
040484af
JB		 2890static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2891{
2892 struct drm_device *dev = crtc->dev;
2893 struct drm_mode_config *mode_config = &dev->mode_config;
2894 struct intel_encoder *encoder;
2895
2896 /*
2897 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2898 * must be driven by its own crtc; no sharing is possible.
2899 */
2900 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2901 if (encoder->base.crtc != crtc)
2902 continue;
2903
2904 switch (encoder->type) {
2905 case INTEL_OUTPUT_EDP:
2906 if (!intel_encoder_is_pch_edp(&encoder->base))
2907 return false;
2908 continue;
2909 }
2910 }
2911
2912 return true;
2913}
2914
f67a559d
JB		 2915/*
2916 * Enable PCH resources required for PCH ports:
2917 * - PCH PLLs
2918 * - FDI training & RX/TX
2919 * - update transcoder timings
2920 * - DP transcoding bits
2921 * - transcoder
2922 */
2923static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2924{
2925 struct drm_device *dev = crtc->dev;
2926 struct drm_i915_private *dev_priv = dev->dev_private;
2927 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2928 int pipe = intel_crtc->pipe;
4b645f14 2929 u32 reg, temp, transc_sel;
2c07245f 2930
c98e9dcf 2931 /* For PCH output, training FDI link */
674cf967 2932 dev_priv->display.fdi_link_train(crtc);
2c07245f 2933
92f2584a 2934 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 2935
c98e9dcf 2936 if (HAS_PCH_CPT(dev)) {
4b645f14
JB		 2937 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2938 TRANSC_DPLLB_SEL;
2939
c98e9dcf
JB		 2940 /* Be sure PCH DPLL SEL is set */
2941 temp = I915_READ(PCH_DPLL_SEL);
d64311ab
JB		 2942 if (pipe == 0) {
2943 temp &= ~(TRANSA_DPLLB_SEL);
c98e9dcf 2944 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
d64311ab
JB		 2945 } else if (pipe == 1) {
2946 temp &= ~(TRANSB_DPLLB_SEL);
c98e9dcf 2947 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
d64311ab
JB		 2948 } else if (pipe == 2) {
2949 temp &= ~(TRANSC_DPLLB_SEL);
4b645f14 2950 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
d64311ab 2951 }
c98e9dcf 2952 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2953 }
5eddb70b 2954
d9b6cb56
JB		 2955 /* set transcoder timing, panel must allow it */
2956 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2957 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2958 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2959 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2960
5eddb70b
CW		 2961 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2962 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2963 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
8db9d77b 2964
5e84e1a4
ZW		 2965 intel_fdi_normal_train(crtc);
2966
c98e9dcf
JB		 2967 /* For PCH DP, enable TRANS_DP_CTL */
2968 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2969 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2970 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 2971 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 2972 reg = TRANS_DP_CTL(pipe);
2973 temp = I915_READ(reg);
2974 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2975 TRANS_DP_SYNC_MASK |
2976 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2977 temp |= (TRANS_DP_OUTPUT_ENABLE |
2978 TRANS_DP_ENH_FRAMING);
9325c9f0 2979 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2980
2981 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2982 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2983 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2984 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2985
2986 switch (intel_trans_dp_port_sel(crtc)) {
2987 case PCH_DP_B:
5eddb70b 2988 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2989 break;
2990 case PCH_DP_C:
5eddb70b 2991 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2992 break;
2993 case PCH_DP_D:
5eddb70b 2994 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2995 break;
2996 default:
2997 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2998 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2999 break;
32f9d658 3000 }
2c07245f 3001
5eddb70b 3002 I915_WRITE(reg, temp);
6be4a607 3003 }
b52eb4dc 3004
040484af 3005 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3006}
3007
d4270e57
JB		 3008void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3009{
3010 struct drm_i915_private *dev_priv = dev->dev_private;
3011 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3012 u32 temp;
3013
3014 temp = I915_READ(dslreg);
3015 udelay(500);
3016 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3017 /* Without this, mode sets may fail silently on FDI */
3018 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3019 udelay(250);
3020 I915_WRITE(tc2reg, 0);
3021 if (wait_for(I915_READ(dslreg) != temp, 5))
3022 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3023 }
3024}
3025
f67a559d
JB		 3026static void ironlake_crtc_enable(struct drm_crtc *crtc)
3027{
3028 struct drm_device *dev = crtc->dev;
3029 struct drm_i915_private *dev_priv = dev->dev_private;
3030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031 int pipe = intel_crtc->pipe;
3032 int plane = intel_crtc->plane;
3033 u32 temp;
3034 bool is_pch_port;
3035
3036 if (intel_crtc->active)
3037 return;
3038
3039 intel_crtc->active = true;
3040 intel_update_watermarks(dev);
3041
3042 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3043 temp = I915_READ(PCH_LVDS);
3044 if ((temp & LVDS_PORT_EN) == 0)
3045 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3046 }
3047
3048 is_pch_port = intel_crtc_driving_pch(crtc);
3049
3050 if (is_pch_port)
357555c0 3051 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 3052 else
3053 ironlake_fdi_disable(crtc);
3054
3055 /* Enable panel fitting for LVDS */
3056 if (dev_priv->pch_pf_size &&
3057 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3058 /* Force use of hard-coded filter coefficients
3059 * as some pre-programmed values are broken,
3060 * e.g. x201.
3061 */
9db4a9c7
JB		 3062 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3063 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3064 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3065 }
3066
9c54c0dd
JB		 3067 /*
3068 * On ILK+ LUT must be loaded before the pipe is running but with
3069 * clocks enabled
3070 */
3071 intel_crtc_load_lut(crtc);
3072
f67a559d
JB		 3073 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3074 intel_enable_plane(dev_priv, plane, pipe);
3075
3076 if (is_pch_port)
3077 ironlake_pch_enable(crtc);
c98e9dcf 3078
d1ebd816 3079 mutex_lock(&dev->struct_mutex);
bed4a673 3080 intel_update_fbc(dev);
d1ebd816
BW		 3081 mutex_unlock(&dev->struct_mutex);
3082
6b383a7f 3083 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 3084}
3085
3086static void ironlake_crtc_disable(struct drm_crtc *crtc)
3087{
3088 struct drm_device *dev = crtc->dev;
3089 struct drm_i915_private *dev_priv = dev->dev_private;
3090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3091 int pipe = intel_crtc->pipe;
3092 int plane = intel_crtc->plane;
5eddb70b 3093 u32 reg, temp;
b52eb4dc 3094
f7abfe8b
CW		 3095 if (!intel_crtc->active)
3096 return;
3097
e6c3a2a6 3098 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3099 drm_vblank_off(dev, pipe);
6b383a7f 3100 intel_crtc_update_cursor(crtc, false);
5eddb70b 3101
b24e7179 3102 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3103
973d04f9
CW		 3104 if (dev_priv->cfb_plane == plane)
3105 intel_disable_fbc(dev);
2c07245f 3106
b24e7179 3107 intel_disable_pipe(dev_priv, pipe);
32f9d658 3108
6be4a607 3109 /* Disable PF */
9db4a9c7
JB		 3110 I915_WRITE(PF_CTL(pipe), 0);
3111 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3112
0fc932b8 3113 ironlake_fdi_disable(crtc);
2c07245f 3114
47a05eca
JB		 3115 /* This is a horrible layering violation; we should be doing this in
3116 * the connector/encoder ->prepare instead, but we don't always have
3117 * enough information there about the config to know whether it will
3118 * actually be necessary or just cause undesired flicker.
3119 */
3120 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 3121
040484af 3122 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3123
6be4a607
JB		 3124 if (HAS_PCH_CPT(dev)) {
3125 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3126 reg = TRANS_DP_CTL(pipe);
3127 temp = I915_READ(reg);
3128 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3129 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3130 I915_WRITE(reg, temp);
6be4a607
JB		 3131
3132 /* disable DPLL_SEL */
3133 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3134 switch (pipe) {
3135 case 0:
d64311ab 3136 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3137 break;
3138 case 1:
6be4a607 3139 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3140 break;
3141 case 2:
4b645f14 3142 /* C shares PLL A or B */
d64311ab 3143 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3144 break;
3145 default:
3146 BUG(); /* wtf */
3147 }
6be4a607 3148 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3149 }
e3421a18 3150
6be4a607 3151 /* disable PCH DPLL */
4b645f14
JB		 3152 if (!intel_crtc->no_pll)
3153 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 3154
6be4a607 3155 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 3156 reg = FDI_RX_CTL(pipe);
3157 temp = I915_READ(reg);
3158 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 3159
6be4a607 3160 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 3161 reg = FDI_TX_CTL(pipe);
3162 temp = I915_READ(reg);
3163 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3164
3165 POSTING_READ(reg);
6be4a607 3166 udelay(100);
8db9d77b 3167
5eddb70b
CW		 3168 reg = FDI_RX_CTL(pipe);
3169 temp = I915_READ(reg);
3170 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 3171
6be4a607 3172 /* Wait for the clocks to turn off. */
5eddb70b 3173 POSTING_READ(reg);
6be4a607 3174 udelay(100);
6b383a7f 3175
f7abfe8b 3176 intel_crtc->active = false;
6b383a7f 3177 intel_update_watermarks(dev);
d1ebd816
BW		 3178
3179 mutex_lock(&dev->struct_mutex);
6b383a7f
CW		 3180 intel_update_fbc(dev);
3181 intel_clear_scanline_wait(dev);
d1ebd816 3182 mutex_unlock(&dev->struct_mutex);
6be4a607 3183}
1b3c7a47 3184
6be4a607
JB		 3185static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3186{
3187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3188 int pipe = intel_crtc->pipe;
3189 int plane = intel_crtc->plane;
8db9d77b 3190
6be4a607
JB		 3191 /* XXX: When our outputs are all unaware of DPMS modes other than off
3192 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3193 */
3194 switch (mode) {
3195 case DRM_MODE_DPMS_ON:
3196 case DRM_MODE_DPMS_STANDBY:
3197 case DRM_MODE_DPMS_SUSPEND:
3198 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3199 ironlake_crtc_enable(crtc);
3200 break;
1b3c7a47 3201
6be4a607
JB		 3202 case DRM_MODE_DPMS_OFF:
3203 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3204 ironlake_crtc_disable(crtc);
2c07245f
ZW		 3205 break;
3206 }
3207}
3208
02e792fb
DV		 3209static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3210{
02e792fb 3211 if (!enable && intel_crtc->overlay) {
23f09ce3 3212 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3213 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3214
23f09ce3 3215 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3216 dev_priv->mm.interruptible = false;
3217 (void) intel_overlay_switch_off(intel_crtc->overlay);
3218 dev_priv->mm.interruptible = true;
23f09ce3 3219 mutex_unlock(&dev->struct_mutex);
02e792fb 3220 }
02e792fb 3221
5dcdbcb0
CW		 3222 /* Let userspace switch the overlay on again. In most cases userspace
3223 * has to recompute where to put it anyway.
3224 */
02e792fb
DV		 3225}
3226
0b8765c6 3227static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3228{
3229 struct drm_device *dev = crtc->dev;
79e53945
JB		 3230 struct drm_i915_private *dev_priv = dev->dev_private;
3231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3232 int pipe = intel_crtc->pipe;
80824003 3233 int plane = intel_crtc->plane;
79e53945 3234
f7abfe8b
CW		 3235 if (intel_crtc->active)
3236 return;
3237
3238 intel_crtc->active = true;
6b383a7f
CW		 3239 intel_update_watermarks(dev);
3240
63d7bbe9 3241 intel_enable_pll(dev_priv, pipe);
040484af 3242 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3243 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3244
0b8765c6 3245 intel_crtc_load_lut(crtc);
bed4a673 3246 intel_update_fbc(dev);
79e53945 3247
0b8765c6
JB		 3248 /* Give the overlay scaler a chance to enable if it's on this pipe */
3249 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3250 intel_crtc_update_cursor(crtc, true);
0b8765c6 3251}
79e53945 3252
0b8765c6
JB		 3253static void i9xx_crtc_disable(struct drm_crtc *crtc)
3254{
3255 struct drm_device *dev = crtc->dev;
3256 struct drm_i915_private *dev_priv = dev->dev_private;
3257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3258 int pipe = intel_crtc->pipe;
3259 int plane = intel_crtc->plane;
b690e96c 3260
f7abfe8b
CW		 3261 if (!intel_crtc->active)
3262 return;
3263
0b8765c6 3264 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3265 intel_crtc_wait_for_pending_flips(crtc);
3266 drm_vblank_off(dev, pipe);
0b8765c6 3267 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3268 intel_crtc_update_cursor(crtc, false);
0b8765c6 3269
973d04f9
CW		 3270 if (dev_priv->cfb_plane == plane)
3271 intel_disable_fbc(dev);
79e53945 3272
b24e7179 3273 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3274 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3275 intel_disable_pll(dev_priv, pipe);
0b8765c6 3276
f7abfe8b 3277 intel_crtc->active = false;
6b383a7f
CW		 3278 intel_update_fbc(dev);
3279 intel_update_watermarks(dev);
3280 intel_clear_scanline_wait(dev);
0b8765c6
JB		 3281}
3282
3283static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3284{
3285 /* XXX: When our outputs are all unaware of DPMS modes other than off
3286 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3287 */
3288 switch (mode) {
3289 case DRM_MODE_DPMS_ON:
3290 case DRM_MODE_DPMS_STANDBY:
3291 case DRM_MODE_DPMS_SUSPEND:
3292 i9xx_crtc_enable(crtc);
3293 break;
3294 case DRM_MODE_DPMS_OFF:
3295 i9xx_crtc_disable(crtc);
79e53945
JB		 3296 break;
3297 }
2c07245f
ZW		 3298}
3299
3300/**
3301 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3302 */
3303static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3304{
3305 struct drm_device *dev = crtc->dev;
e70236a8 3306 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3307 struct drm_i915_master_private *master_priv;
3308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3309 int pipe = intel_crtc->pipe;
3310 bool enabled;
3311
032d2a0d
CW		 3312 if (intel_crtc->dpms_mode == mode)
3313 return;
3314
65655d4a 3315 intel_crtc->dpms_mode = mode;
debcaddc 3316
e70236a8 3317 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3318
3319 if (!dev->primary->master)
3320 return;
3321
3322 master_priv = dev->primary->master->driver_priv;
3323 if (!master_priv->sarea_priv)
3324 return;
3325
3326 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3327
3328 switch (pipe) {
3329 case 0:
3330 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3331 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3332 break;
3333 case 1:
3334 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3335 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3336 break;
3337 default:
9db4a9c7 3338 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3339 break;
3340 }
79e53945
JB		 3341}
3342
cdd59983
CW		 3343static void intel_crtc_disable(struct drm_crtc *crtc)
3344{
3345 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3346 struct drm_device *dev = crtc->dev;
3347
3348 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
931872fc
CW		 3349 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3350 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3351
3352 if (crtc->fb) {
3353 mutex_lock(&dev->struct_mutex);
3354 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3355 mutex_unlock(&dev->struct_mutex);
3356 }
3357}
3358
7e7d76c3
JB		 3359/* Prepare for a mode set.
3360 *
3361 * Note we could be a lot smarter here. We need to figure out which outputs
3362 * will be enabled, which disabled (in short, how the config will changes)
3363 * and perform the minimum necessary steps to accomplish that, e.g. updating
3364 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3365 * panel fitting is in the proper state, etc.
3366 */
3367static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3368{
7e7d76c3 3369 i9xx_crtc_disable(crtc);
79e53945
JB		 3370}
3371
7e7d76c3 3372static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3373{
7e7d76c3 3374 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3375}
3376
3377static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3378{
7e7d76c3 3379 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3380}
3381
3382static void ironlake_crtc_commit(struct drm_crtc *crtc)
3383{
7e7d76c3 3384 ironlake_crtc_enable(crtc);
79e53945
JB		 3385}
3386
0206e353 3387void intel_encoder_prepare(struct drm_encoder *encoder)
79e53945
JB		 3388{
3389 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3390 /* lvds has its own version of prepare see intel_lvds_prepare */
3391 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3392}
3393
0206e353 3394void intel_encoder_commit(struct drm_encoder *encoder)
79e53945
JB		 3395{
3396 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
d4270e57
JB		 3397 struct drm_device *dev = encoder->dev;
3398 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3399 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3400
79e53945
JB		 3401 /* lvds has its own version of commit see intel_lvds_commit */
3402 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
d4270e57
JB		 3403
3404 if (HAS_PCH_CPT(dev))
3405 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
79e53945
JB		 3406}
3407
ea5b213a
CW		 3408void intel_encoder_destroy(struct drm_encoder *encoder)
3409{
4ef69c7a 3410 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3411
ea5b213a
CW		 3412 drm_encoder_cleanup(encoder);
3413 kfree(intel_encoder);
3414}
3415
79e53945
JB		 3416static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3417 struct drm_display_mode *mode,
3418 struct drm_display_mode *adjusted_mode)
3419{
2c07245f 3420 struct drm_device *dev = crtc->dev;
89749350 3421
bad720ff 3422 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3423 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3424 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3425 return false;
2c07245f 3426 }
89749350
CW		 3427
3428 /* XXX some encoders set the crtcinfo, others don't.
3429 * Obviously we need some form of conflict resolution here...
3430 */
3431 if (adjusted_mode->crtc_htotal == 0)
3432 drm_mode_set_crtcinfo(adjusted_mode, 0);
3433
79e53945
JB		 3434 return true;
3435}
3436
e70236a8
JB		 3437static int i945_get_display_clock_speed(struct drm_device *dev)
3438{
3439 return 400000;
3440}
79e53945 3441
e70236a8 3442static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3443{
e70236a8
JB		 3444 return 333000;
3445}
79e53945 3446
e70236a8
JB		 3447static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3448{
3449 return 200000;
3450}
79e53945 3451
e70236a8
JB		 3452static int i915gm_get_display_clock_speed(struct drm_device *dev)
3453{
3454 u16 gcfgc = 0;
79e53945 3455
e70236a8
JB		 3456 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3457
3458 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3459 return 133000;
3460 else {
3461 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3462 case GC_DISPLAY_CLOCK_333_MHZ:
3463 return 333000;
3464 default:
3465 case GC_DISPLAY_CLOCK_190_200_MHZ:
3466 return 190000;
79e53945 3467 }
e70236a8
JB		 3468 }
3469}
3470
3471static int i865_get_display_clock_speed(struct drm_device *dev)
3472{
3473 return 266000;
3474}
3475
3476static int i855_get_display_clock_speed(struct drm_device *dev)
3477{
3478 u16 hpllcc = 0;
3479 /* Assume that the hardware is in the high speed state. This
3480 * should be the default.
3481 */
3482 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3483 case GC_CLOCK_133_200:
3484 case GC_CLOCK_100_200:
3485 return 200000;
3486 case GC_CLOCK_166_250:
3487 return 250000;
3488 case GC_CLOCK_100_133:
79e53945 3489 return 133000;
e70236a8 3490 }
79e53945 3491
e70236a8
JB		 3492 /* Shouldn't happen */
3493 return 0;
3494}
79e53945 3495
e70236a8
JB		 3496static int i830_get_display_clock_speed(struct drm_device *dev)
3497{
3498 return 133000;
79e53945
JB		 3499}
3500
2c07245f
ZW		 3501struct fdi_m_n {
3502 u32 tu;
3503 u32 gmch_m;
3504 u32 gmch_n;
3505 u32 link_m;
3506 u32 link_n;
3507};
3508
3509static void
3510fdi_reduce_ratio(u32 *num, u32 *den)
3511{
3512 while (*num > 0xffffff || *den > 0xffffff) {
3513 *num >>= 1;
3514 *den >>= 1;
3515 }
3516}
3517
2c07245f 3518static void
f2b115e6
AJ		 3519ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3520 int link_clock, struct fdi_m_n *m_n)
2c07245f 3521{
2c07245f
ZW		 3522 m_n->tu = 64; /* default size */
3523
22ed1113
CW		 3524 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3525 m_n->gmch_m = bits_per_pixel * pixel_clock;
3526 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3527 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3528
22ed1113
CW		 3529 m_n->link_m = pixel_clock;
3530 m_n->link_n = link_clock;
2c07245f
ZW		 3531 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3532}
3533
3534
7662c8bd
SL		 3535struct intel_watermark_params {
3536 unsigned long fifo_size;
3537 unsigned long max_wm;
3538 unsigned long default_wm;
3539 unsigned long guard_size;
3540 unsigned long cacheline_size;
3541};
3542
f2b115e6 3543/* Pineview has different values for various configs */
d210246a 3544static const struct intel_watermark_params pineview_display_wm = {
f2b115e6
AJ		 3545 PINEVIEW_DISPLAY_FIFO,
3546 PINEVIEW_MAX_WM,
3547 PINEVIEW_DFT_WM,
3548 PINEVIEW_GUARD_WM,
3549 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3550};
d210246a 3551static const struct intel_watermark_params pineview_display_hplloff_wm = {
f2b115e6
AJ		 3552 PINEVIEW_DISPLAY_FIFO,
3553 PINEVIEW_MAX_WM,
3554 PINEVIEW_DFT_HPLLOFF_WM,
3555 PINEVIEW_GUARD_WM,
3556 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3557};
d210246a 3558static const struct intel_watermark_params pineview_cursor_wm = {
f2b115e6
AJ		 3559 PINEVIEW_CURSOR_FIFO,
3560 PINEVIEW_CURSOR_MAX_WM,
3561 PINEVIEW_CURSOR_DFT_WM,
3562 PINEVIEW_CURSOR_GUARD_WM,
3563 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 3564};
d210246a 3565static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
f2b115e6
AJ		 3566 PINEVIEW_CURSOR_FIFO,
3567 PINEVIEW_CURSOR_MAX_WM,
3568 PINEVIEW_CURSOR_DFT_WM,
3569 PINEVIEW_CURSOR_GUARD_WM,
3570 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3571};
d210246a 3572static const struct intel_watermark_params g4x_wm_info = {
0e442c60
JB		 3573 G4X_FIFO_SIZE,
3574 G4X_MAX_WM,
3575 G4X_MAX_WM,
3576 2,
3577 G4X_FIFO_LINE_SIZE,
3578};
d210246a 3579static const struct intel_watermark_params g4x_cursor_wm_info = {
4fe5e611
ZY		 3580 I965_CURSOR_FIFO,
3581 I965_CURSOR_MAX_WM,
3582 I965_CURSOR_DFT_WM,
3583 2,
3584 G4X_FIFO_LINE_SIZE,
3585};
d210246a 3586static const struct intel_watermark_params i965_cursor_wm_info = {
4fe5e611
ZY		 3587 I965_CURSOR_FIFO,
3588 I965_CURSOR_MAX_WM,
3589 I965_CURSOR_DFT_WM,
3590 2,
3591 I915_FIFO_LINE_SIZE,
3592};
d210246a 3593static const struct intel_watermark_params i945_wm_info = {
dff33cfc 3594 I945_FIFO_SIZE,
7662c8bd
SL		 3595 I915_MAX_WM,
3596 1,
dff33cfc
JB		 3597 2,
3598 I915_FIFO_LINE_SIZE
7662c8bd 3599};
d210246a 3600static const struct intel_watermark_params i915_wm_info = {
dff33cfc 3601 I915_FIFO_SIZE,
7662c8bd
SL		 3602 I915_MAX_WM,
3603 1,
dff33cfc 3604 2,
7662c8bd
SL		 3605 I915_FIFO_LINE_SIZE
3606};
d210246a 3607static const struct intel_watermark_params i855_wm_info = {
7662c8bd
SL		 3608 I855GM_FIFO_SIZE,
3609 I915_MAX_WM,
3610 1,
dff33cfc 3611 2,
7662c8bd
SL		 3612 I830_FIFO_LINE_SIZE
3613};
d210246a 3614static const struct intel_watermark_params i830_wm_info = {
7662c8bd
SL		 3615 I830_FIFO_SIZE,
3616 I915_MAX_WM,
3617 1,
dff33cfc 3618 2,
7662c8bd
SL		 3619 I830_FIFO_LINE_SIZE
3620};
3621
d210246a 3622static const struct intel_watermark_params ironlake_display_wm_info = {
7f8a8569
ZW		 3623 ILK_DISPLAY_FIFO,
3624 ILK_DISPLAY_MAXWM,
3625 ILK_DISPLAY_DFTWM,
3626 2,
3627 ILK_FIFO_LINE_SIZE
3628};
d210246a 3629static const struct intel_watermark_params ironlake_cursor_wm_info = {
c936f44d
ZY		 3630 ILK_CURSOR_FIFO,
3631 ILK_CURSOR_MAXWM,
3632 ILK_CURSOR_DFTWM,
3633 2,
3634 ILK_FIFO_LINE_SIZE
3635};
d210246a 3636static const struct intel_watermark_params ironlake_display_srwm_info = {
7f8a8569
ZW		 3637 ILK_DISPLAY_SR_FIFO,
3638 ILK_DISPLAY_MAX_SRWM,
3639 ILK_DISPLAY_DFT_SRWM,
3640 2,
3641 ILK_FIFO_LINE_SIZE
3642};
d210246a 3643static const struct intel_watermark_params ironlake_cursor_srwm_info = {
7f8a8569
ZW		 3644 ILK_CURSOR_SR_FIFO,
3645 ILK_CURSOR_MAX_SRWM,
3646 ILK_CURSOR_DFT_SRWM,
3647 2,
3648 ILK_FIFO_LINE_SIZE
3649};
3650
d210246a 3651static const struct intel_watermark_params sandybridge_display_wm_info = {
1398261a
YL		 3652 SNB_DISPLAY_FIFO,
3653 SNB_DISPLAY_MAXWM,
3654 SNB_DISPLAY_DFTWM,
3655 2,
3656 SNB_FIFO_LINE_SIZE
3657};
d210246a 3658static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1398261a
YL		 3659 SNB_CURSOR_FIFO,
3660 SNB_CURSOR_MAXWM,
3661 SNB_CURSOR_DFTWM,
3662 2,
3663 SNB_FIFO_LINE_SIZE
3664};
d210246a 3665static const struct intel_watermark_params sandybridge_display_srwm_info = {
1398261a
YL		 3666 SNB_DISPLAY_SR_FIFO,
3667 SNB_DISPLAY_MAX_SRWM,
3668 SNB_DISPLAY_DFT_SRWM,
3669 2,
3670 SNB_FIFO_LINE_SIZE
3671};
d210246a 3672static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1398261a
YL		 3673 SNB_CURSOR_SR_FIFO,
3674 SNB_CURSOR_MAX_SRWM,
3675 SNB_CURSOR_DFT_SRWM,
3676 2,
3677 SNB_FIFO_LINE_SIZE
3678};
3679
3680
dff33cfc
JB		 3681/**
3682 * intel_calculate_wm - calculate watermark level
3683 * @clock_in_khz: pixel clock
3684 * @wm: chip FIFO params
3685 * @pixel_size: display pixel size
3686 * @latency_ns: memory latency for the platform
3687 *
3688 * Calculate the watermark level (the level at which the display plane will
3689 * start fetching from memory again). Each chip has a different display
3690 * FIFO size and allocation, so the caller needs to figure that out and pass
3691 * in the correct intel_watermark_params structure.
3692 *
3693 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3694 * on the pixel size. When it reaches the watermark level, it'll start
3695 * fetching FIFO line sized based chunks from memory until the FIFO fills
3696 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3697 * will occur, and a display engine hang could result.
3698 */
7662c8bd 3699static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
d210246a
CW		 3700 const struct intel_watermark_params *wm,
3701 int fifo_size,
7662c8bd
SL		 3702 int pixel_size,
3703 unsigned long latency_ns)
3704{
390c4dd4 3705 long entries_required, wm_size;
dff33cfc 3706
d660467c
JB		 3707 /*
3708 * Note: we need to make sure we don't overflow for various clock &
3709 * latency values.
3710 * clocks go from a few thousand to several hundred thousand.
3711 * latency is usually a few thousand
3712 */
3713 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3714 1000;
8de9b311 3715 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 3716
bbb0aef5 3717 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
dff33cfc 3718
d210246a 3719 wm_size = fifo_size - (entries_required + wm->guard_size);
dff33cfc 3720
bbb0aef5 3721 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
7662c8bd 3722
390c4dd4
JB		 3723 /* Don't promote wm_size to unsigned... */
3724 if (wm_size > (long)wm->max_wm)
7662c8bd 3725 wm_size = wm->max_wm;
c3add4b6 3726 if (wm_size <= 0)
7662c8bd
SL		 3727 wm_size = wm->default_wm;
3728 return wm_size;
3729}
3730
3731struct cxsr_latency {
3732 int is_desktop;
95534263 3733 int is_ddr3;
7662c8bd
SL		 3734 unsigned long fsb_freq;
3735 unsigned long mem_freq;
3736 unsigned long display_sr;
3737 unsigned long display_hpll_disable;
3738 unsigned long cursor_sr;
3739 unsigned long cursor_hpll_disable;
3740};
3741
403c89ff 3742static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP		 3743 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3744 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3745 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3746 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3747 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3748
3749 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3750 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3751 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3752 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3753 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3754
3755 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3756 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3757 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3758 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3759 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3760
3761 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3762 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3763 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3764 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3765 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3766
3767 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3768 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3769 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3770 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3771 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3772
3773 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3774 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3775 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3776 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3777 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL		 3778};
3779
403c89ff
CW		 3780static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3781 int is_ddr3,
3782 int fsb,
3783 int mem)
7662c8bd 3784{
403c89ff 3785 const struct cxsr_latency *latency;
7662c8bd 3786 int i;
7662c8bd
SL		 3787
3788 if (fsb == 0 || mem == 0)
3789 return NULL;
3790
3791 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3792 latency = &cxsr_latency_table[i];
3793 if (is_desktop == latency->is_desktop &&
95534263 3794 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR		 3795 fsb == latency->fsb_freq && mem == latency->mem_freq)
3796 return latency;
7662c8bd 3797 }
decbbcda 3798
28c97730 3799 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR		 3800
3801 return NULL;
7662c8bd
SL		 3802}
3803
f2b115e6 3804static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL		 3805{
3806 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL		 3807
3808 /* deactivate cxsr */
3e33d94d 3809 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL		 3810}
3811
bcc24fb4
JB		 3812/*
3813 * Latency for FIFO fetches is dependent on several factors:
3814 * - memory configuration (speed, channels)
3815 * - chipset
3816 * - current MCH state
3817 * It can be fairly high in some situations, so here we assume a fairly
3818 * pessimal value. It's a tradeoff between extra memory fetches (if we
3819 * set this value too high, the FIFO will fetch frequently to stay full)
3820 * and power consumption (set it too low to save power and we might see
3821 * FIFO underruns and display "flicker").
3822 *
3823 * A value of 5us seems to be a good balance; safe for very low end
3824 * platforms but not overly aggressive on lower latency configs.
3825 */
69e302a9 3826static const int latency_ns = 5000;
7662c8bd 3827
e70236a8 3828static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB		 3829{
3830 struct drm_i915_private *dev_priv = dev->dev_private;
3831 uint32_t dsparb = I915_READ(DSPARB);
3832 int size;
3833
8de9b311
CW		 3834 size = dsparb & 0x7f;
3835 if (plane)
3836 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 3837
28c97730 3838 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3839 plane ? "B" : "A", size);
dff33cfc
JB		 3840
3841 return size;
3842}
7662c8bd 3843
e70236a8
JB		 3844static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3845{
3846 struct drm_i915_private *dev_priv = dev->dev_private;
3847 uint32_t dsparb = I915_READ(DSPARB);
3848 int size;
3849
8de9b311
CW		 3850 size = dsparb & 0x1ff;
3851 if (plane)
3852 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 3853 size >>= 1; /* Convert to cachelines */
dff33cfc 3854
28c97730 3855 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3856 plane ? "B" : "A", size);
dff33cfc
JB		 3857
3858 return size;
3859}
7662c8bd 3860
e70236a8
JB		 3861static int i845_get_fifo_size(struct drm_device *dev, int plane)
3862{
3863 struct drm_i915_private *dev_priv = dev->dev_private;
3864 uint32_t dsparb = I915_READ(DSPARB);
3865 int size;
3866
3867 size = dsparb & 0x7f;
3868 size >>= 2; /* Convert to cachelines */
3869
28c97730 3870 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW		 3871 plane ? "B" : "A",
3872 size);
e70236a8
JB		 3873
3874 return size;
3875}
3876
3877static int i830_get_fifo_size(struct drm_device *dev, int plane)
3878{
3879 struct drm_i915_private *dev_priv = dev->dev_private;
3880 uint32_t dsparb = I915_READ(DSPARB);
3881 int size;
3882
3883 size = dsparb & 0x7f;
3884 size >>= 1; /* Convert to cachelines */
3885
28c97730 3886 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3887 plane ? "B" : "A", size);
e70236a8
JB		 3888
3889 return size;
3890}
3891
d210246a
CW		 3892static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3893{
3894 struct drm_crtc *crtc, *enabled = NULL;
3895
3896 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3897 if (crtc->enabled && crtc->fb) {
3898 if (enabled)
3899 return NULL;
3900 enabled = crtc;
3901 }
3902 }
3903
3904 return enabled;
3905}
3906
3907static void pineview_update_wm(struct drm_device *dev)
d4294342
ZY		 3908{
3909 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3910 struct drm_crtc *crtc;
403c89ff 3911 const struct cxsr_latency *latency;
d4294342
ZY		 3912 u32 reg;
3913 unsigned long wm;
d4294342 3914
403c89ff 3915 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 3916 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY		 3917 if (!latency) {
3918 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3919 pineview_disable_cxsr(dev);
3920 return;
3921 }
3922
d210246a
CW		 3923 crtc = single_enabled_crtc(dev);
3924 if (crtc) {
3925 int clock = crtc->mode.clock;
3926 int pixel_size = crtc->fb->bits_per_pixel / 8;
d4294342
ZY		 3927
3928 /* Display SR */
d210246a
CW		 3929 wm = intel_calculate_wm(clock, &pineview_display_wm,
3930 pineview_display_wm.fifo_size,
d4294342
ZY		 3931 pixel_size, latency->display_sr);
3932 reg = I915_READ(DSPFW1);
3933 reg &= ~DSPFW_SR_MASK;
3934 reg |= wm << DSPFW_SR_SHIFT;
3935 I915_WRITE(DSPFW1, reg);
3936 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3937
3938 /* cursor SR */
d210246a
CW		 3939 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3940 pineview_display_wm.fifo_size,
d4294342
ZY		 3941 pixel_size, latency->cursor_sr);
3942 reg = I915_READ(DSPFW3);
3943 reg &= ~DSPFW_CURSOR_SR_MASK;
3944 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3945 I915_WRITE(DSPFW3, reg);
3946
3947 /* Display HPLL off SR */
d210246a
CW		 3948 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3949 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3950 pixel_size, latency->display_hpll_disable);
3951 reg = I915_READ(DSPFW3);
3952 reg &= ~DSPFW_HPLL_SR_MASK;
3953 reg |= wm & DSPFW_HPLL_SR_MASK;
3954 I915_WRITE(DSPFW3, reg);
3955
3956 /* cursor HPLL off SR */
d210246a
CW		 3957 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3958 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3959 pixel_size, latency->cursor_hpll_disable);
3960 reg = I915_READ(DSPFW3);
3961 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3962 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3963 I915_WRITE(DSPFW3, reg);
3964 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3965
3966 /* activate cxsr */
3e33d94d
CW		 3967 I915_WRITE(DSPFW3,
3968 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY		 3969 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3970 } else {
3971 pineview_disable_cxsr(dev);
3972 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3973 }
3974}
3975
417ae147
CW		 3976static bool g4x_compute_wm0(struct drm_device *dev,
3977 int plane,
3978 const struct intel_watermark_params *display,
3979 int display_latency_ns,
3980 const struct intel_watermark_params *cursor,
3981 int cursor_latency_ns,
3982 int *plane_wm,
3983 int *cursor_wm)
3984{
3985 struct drm_crtc *crtc;
3986 int htotal, hdisplay, clock, pixel_size;
3987 int line_time_us, line_count;
3988 int entries, tlb_miss;
3989
3990 crtc = intel_get_crtc_for_plane(dev, plane);
5c72d064
CW		 3991 if (crtc->fb == NULL || !crtc->enabled) {
3992 *cursor_wm = cursor->guard_size;
3993 *plane_wm = display->guard_size;
417ae147 3994 return false;
5c72d064 3995 }
417ae147
CW		 3996
3997 htotal = crtc->mode.htotal;
3998 hdisplay = crtc->mode.hdisplay;
3999 clock = crtc->mode.clock;
4000 pixel_size = crtc->fb->bits_per_pixel / 8;
4001
4002 /* Use the small buffer method to calculate plane watermark */
4003 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4004 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4005 if (tlb_miss > 0)
4006 entries += tlb_miss;
4007 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4008 *plane_wm = entries + display->guard_size;
4009 if (*plane_wm > (int)display->max_wm)
4010 *plane_wm = display->max_wm;
4011
4012 /* Use the large buffer method to calculate cursor watermark */
4013 line_time_us = ((htotal * 1000) / clock);
4014 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4015 entries = line_count * 64 * pixel_size;
4016 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4017 if (tlb_miss > 0)
4018 entries += tlb_miss;
4019 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4020 *cursor_wm = entries + cursor->guard_size;
4021 if (*cursor_wm > (int)cursor->max_wm)
4022 *cursor_wm = (int)cursor->max_wm;
4023
4024 return true;
4025}
4026
4027/*
4028 * Check the wm result.
4029 *
4030 * If any calculated watermark values is larger than the maximum value that
4031 * can be programmed into the associated watermark register, that watermark
4032 * must be disabled.
4033 */
4034static bool g4x_check_srwm(struct drm_device *dev,
4035 int display_wm, int cursor_wm,
4036 const struct intel_watermark_params *display,
4037 const struct intel_watermark_params *cursor)
652c393a 4038{
417ae147
CW		 4039 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4040 display_wm, cursor_wm);
652c393a 4041
417ae147 4042 if (display_wm > display->max_wm) {
bbb0aef5 4043 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 4044 display_wm, display->max_wm);
4045 return false;
4046 }
0e442c60 4047
417ae147 4048 if (cursor_wm > cursor->max_wm) {
bbb0aef5 4049 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 4050 cursor_wm, cursor->max_wm);
4051 return false;
4052 }
0e442c60 4053
417ae147
CW		 4054 if (!(display_wm || cursor_wm)) {
4055 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4056 return false;
4057 }
0e442c60 4058
417ae147
CW		 4059 return true;
4060}
0e442c60 4061
417ae147 4062static bool g4x_compute_srwm(struct drm_device *dev,
d210246a
CW		 4063 int plane,
4064 int latency_ns,
417ae147
CW		 4065 const struct intel_watermark_params *display,
4066 const struct intel_watermark_params *cursor,
4067 int *display_wm, int *cursor_wm)
4068{
d210246a
CW		 4069 struct drm_crtc *crtc;
4070 int hdisplay, htotal, pixel_size, clock;
417ae147
CW		 4071 unsigned long line_time_us;
4072 int line_count, line_size;
4073 int small, large;
4074 int entries;
0e442c60 4075
417ae147
CW		 4076 if (!latency_ns) {
4077 *display_wm = *cursor_wm = 0;
4078 return false;
4079 }
0e442c60 4080
d210246a
CW		 4081 crtc = intel_get_crtc_for_plane(dev, plane);
4082 hdisplay = crtc->mode.hdisplay;
4083 htotal = crtc->mode.htotal;
4084 clock = crtc->mode.clock;
4085 pixel_size = crtc->fb->bits_per_pixel / 8;
4086
417ae147
CW		 4087 line_time_us = (htotal * 1000) / clock;
4088 line_count = (latency_ns / line_time_us + 1000) / 1000;
4089 line_size = hdisplay * pixel_size;
0e442c60 4090
417ae147
CW		 4091 /* Use the minimum of the small and large buffer method for primary */
4092 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4093 large = line_count * line_size;
0e442c60 4094
417ae147
CW		 4095 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4096 *display_wm = entries + display->guard_size;
4fe5e611 4097
417ae147
CW		 4098 /* calculate the self-refresh watermark for display cursor */
4099 entries = line_count * pixel_size * 64;
4100 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4101 *cursor_wm = entries + cursor->guard_size;
4fe5e611 4102
417ae147
CW		 4103 return g4x_check_srwm(dev,
4104 *display_wm, *cursor_wm,
4105 display, cursor);
4106}
4fe5e611 4107
7ccb4a53 4108#define single_plane_enabled(mask) is_power_of_2(mask)
d210246a
CW		 4109
4110static void g4x_update_wm(struct drm_device *dev)
417ae147
CW		 4111{
4112 static const int sr_latency_ns = 12000;
4113 struct drm_i915_private *dev_priv = dev->dev_private;
4114 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
d210246a
CW		 4115 int plane_sr, cursor_sr;
4116 unsigned int enabled = 0;
417ae147
CW		 4117
4118 if (g4x_compute_wm0(dev, 0,
4119 &g4x_wm_info, latency_ns,
4120 &g4x_cursor_wm_info, latency_ns,
4121 &planea_wm, &cursora_wm))
d210246a 4122 enabled |= 1;
417ae147
CW		 4123
4124 if (g4x_compute_wm0(dev, 1,
4125 &g4x_wm_info, latency_ns,
4126 &g4x_cursor_wm_info, latency_ns,
4127 &planeb_wm, &cursorb_wm))
d210246a 4128 enabled |= 2;
417ae147
CW		 4129
4130 plane_sr = cursor_sr = 0;
d210246a
CW		 4131 if (single_plane_enabled(enabled) &&
4132 g4x_compute_srwm(dev, ffs(enabled) - 1,
4133 sr_latency_ns,
417ae147
CW		 4134 &g4x_wm_info,
4135 &g4x_cursor_wm_info,
4136 &plane_sr, &cursor_sr))
0e442c60 4137 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
417ae147
CW		 4138 else
4139 I915_WRITE(FW_BLC_SELF,
4140 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
0e442c60 4141
308977ac
CW		 4142 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4143 planea_wm, cursora_wm,
4144 planeb_wm, cursorb_wm,
4145 plane_sr, cursor_sr);
0e442c60 4146
417ae147
CW		 4147 I915_WRITE(DSPFW1,
4148 (plane_sr << DSPFW_SR_SHIFT) |
0e442c60 4149 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
417ae147
CW		 4150 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4151 planea_wm);
4152 I915_WRITE(DSPFW2,
4153 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
0e442c60
JB		 4154 (cursora_wm << DSPFW_CURSORA_SHIFT));
4155 /* HPLL off in SR has some issues on G4x... disable it */
417ae147
CW		 4156 I915_WRITE(DSPFW3,
4157 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
0e442c60 4158 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB		 4159}
4160
d210246a 4161static void i965_update_wm(struct drm_device *dev)
7662c8bd
SL		 4162{
4163 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4164 struct drm_crtc *crtc;
4165 int srwm = 1;
4fe5e611 4166 int cursor_sr = 16;
1dc7546d
JB		 4167
4168 /* Calc sr entries for one plane configs */
d210246a
CW		 4169 crtc = single_enabled_crtc(dev);
4170 if (crtc) {
1dc7546d 4171 /* self-refresh has much higher latency */
69e302a9 4172 static const int sr_latency_ns = 12000;
d210246a
CW		 4173 int clock = crtc->mode.clock;
4174 int htotal = crtc->mode.htotal;
4175 int hdisplay = crtc->mode.hdisplay;
4176 int pixel_size = crtc->fb->bits_per_pixel / 8;
4177 unsigned long line_time_us;
4178 int entries;
1dc7546d 4179
d210246a 4180 line_time_us = ((htotal * 1000) / clock);
1dc7546d
JB		 4181
4182 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4183 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4184 pixel_size * hdisplay;
4185 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
d210246a 4186 srwm = I965_FIFO_SIZE - entries;
1dc7546d
JB		 4187 if (srwm < 0)
4188 srwm = 1;
1b07e04e 4189 srwm &= 0x1ff;
308977ac
CW		 4190 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4191 entries, srwm);
4fe5e611 4192
d210246a 4193 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 4194 pixel_size * 64;
d210246a 4195 entries = DIV_ROUND_UP(entries,
8de9b311 4196 i965_cursor_wm_info.cacheline_size);
4fe5e611 4197 cursor_sr = i965_cursor_wm_info.fifo_size -
d210246a 4198 (entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY		 4199
4200 if (cursor_sr > i965_cursor_wm_info.max_wm)
4201 cursor_sr = i965_cursor_wm_info.max_wm;
4202
4203 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4204 "cursor %d\n", srwm, cursor_sr);
4205
a6c45cf0 4206 if (IS_CRESTLINE(dev))
adcdbc66 4207 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ		 4208 } else {
4209 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 4210 if (IS_CRESTLINE(dev))
adcdbc66
JB		 4211 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4212 & ~FW_BLC_SELF_EN);
1dc7546d 4213 }
7662c8bd 4214
1dc7546d
JB		 4215 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4216 srwm);
7662c8bd
SL		 4217
4218 /* 965 has limitations... */
417ae147
CW		 4219 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4220 (8 << 16) | (8 << 8) | (8 << 0));
7662c8bd 4221 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY		 4222 /* update cursor SR watermark */
4223 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL		 4224}
4225
d210246a 4226static void i9xx_update_wm(struct drm_device *dev)
7662c8bd
SL		 4227{
4228 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 4229 const struct intel_watermark_params *wm_info;
dff33cfc
JB		 4230 uint32_t fwater_lo;
4231 uint32_t fwater_hi;
d210246a
CW		 4232 int cwm, srwm = 1;
4233 int fifo_size;
dff33cfc 4234 int planea_wm, planeb_wm;
d210246a 4235 struct drm_crtc *crtc, *enabled = NULL;
7662c8bd 4236
72557b4f 4237 if (IS_I945GM(dev))
d210246a 4238 wm_info = &i945_wm_info;
a6c45cf0 4239 else if (!IS_GEN2(dev))
d210246a 4240 wm_info = &i915_wm_info;
7662c8bd 4241 else
d210246a
CW		 4242 wm_info = &i855_wm_info;
4243
4244 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4245 crtc = intel_get_crtc_for_plane(dev, 0);
4246 if (crtc->enabled && crtc->fb) {
4247 planea_wm = intel_calculate_wm(crtc->mode.clock,
4248 wm_info, fifo_size,
4249 crtc->fb->bits_per_pixel / 8,
4250 latency_ns);
4251 enabled = crtc;
4252 } else
4253 planea_wm = fifo_size - wm_info->guard_size;
4254
4255 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4256 crtc = intel_get_crtc_for_plane(dev, 1);
4257 if (crtc->enabled && crtc->fb) {
4258 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4259 wm_info, fifo_size,
4260 crtc->fb->bits_per_pixel / 8,
4261 latency_ns);
4262 if (enabled == NULL)
4263 enabled = crtc;
4264 else
4265 enabled = NULL;
4266 } else
4267 planeb_wm = fifo_size - wm_info->guard_size;
7662c8bd 4268
28c97730 4269 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL		 4270
4271 /*
4272 * Overlay gets an aggressive default since video jitter is bad.
4273 */
4274 cwm = 2;
4275
18b2190c
AL		 4276 /* Play safe and disable self-refresh before adjusting watermarks. */
4277 if (IS_I945G(dev) || IS_I945GM(dev))
4278 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4279 else if (IS_I915GM(dev))
4280 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4281
dff33cfc 4282 /* Calc sr entries for one plane configs */
d210246a 4283 if (HAS_FW_BLC(dev) && enabled) {
dff33cfc 4284 /* self-refresh has much higher latency */
69e302a9 4285 static const int sr_latency_ns = 6000;
d210246a
CW		 4286 int clock = enabled->mode.clock;
4287 int htotal = enabled->mode.htotal;
4288 int hdisplay = enabled->mode.hdisplay;
4289 int pixel_size = enabled->fb->bits_per_pixel / 8;
4290 unsigned long line_time_us;
4291 int entries;
dff33cfc 4292
d210246a 4293 line_time_us = (htotal * 1000) / clock;
dff33cfc
JB		 4294
4295 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4296 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4297 pixel_size * hdisplay;
4298 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4299 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4300 srwm = wm_info->fifo_size - entries;
dff33cfc
JB		 4301 if (srwm < 0)
4302 srwm = 1;
ee980b80
LP		 4303
4304 if (IS_I945G(dev) || IS_I945GM(dev))
18b2190c
AL		 4305 I915_WRITE(FW_BLC_SELF,
4306 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4307 else if (IS_I915GM(dev))
ee980b80 4308 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
7662c8bd
SL		 4309 }
4310
28c97730 4311 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 4312 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 4313
dff33cfc
JB		 4314 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4315 fwater_hi = (cwm & 0x1f);
4316
4317 /* Set request length to 8 cachelines per fetch */
4318 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4319 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL		 4320
4321 I915_WRITE(FW_BLC, fwater_lo);
4322 I915_WRITE(FW_BLC2, fwater_hi);
18b2190c 4323
d210246a
CW		 4324 if (HAS_FW_BLC(dev)) {
4325 if (enabled) {
4326 if (IS_I945G(dev) || IS_I945GM(dev))
4327 I915_WRITE(FW_BLC_SELF,
4328 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4329 else if (IS_I915GM(dev))
4330 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4331 DRM_DEBUG_KMS("memory self refresh enabled\n");
4332 } else
4333 DRM_DEBUG_KMS("memory self refresh disabled\n");
4334 }
7662c8bd
SL		 4335}
4336
d210246a 4337static void i830_update_wm(struct drm_device *dev)
7662c8bd
SL		 4338{
4339 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4340 struct drm_crtc *crtc;
4341 uint32_t fwater_lo;
dff33cfc 4342 int planea_wm;
7662c8bd 4343
d210246a
CW		 4344 crtc = single_enabled_crtc(dev);
4345 if (crtc == NULL)
4346 return;
7662c8bd 4347
d210246a
CW		 4348 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4349 dev_priv->display.get_fifo_size(dev, 0),
4350 crtc->fb->bits_per_pixel / 8,
4351 latency_ns);
4352 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
f3601326
JB		 4353 fwater_lo |= (3<<8) | planea_wm;
4354
28c97730 4355 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL		 4356
4357 I915_WRITE(FW_BLC, fwater_lo);
4358}
4359
7f8a8569 4360#define ILK_LP0_PLANE_LATENCY 700
c936f44d 4361#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 4362
1398261a
YL		 4363/*
4364 * Check the wm result.
4365 *
4366 * If any calculated watermark values is larger than the maximum value that
4367 * can be programmed into the associated watermark register, that watermark
4368 * must be disabled.
1398261a 4369 */
b79d4990
JB		 4370static bool ironlake_check_srwm(struct drm_device *dev, int level,
4371 int fbc_wm, int display_wm, int cursor_wm,
4372 const struct intel_watermark_params *display,
4373 const struct intel_watermark_params *cursor)
1398261a
YL		 4374{
4375 struct drm_i915_private *dev_priv = dev->dev_private;
4376
4377 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4378 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4379
4380 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4381 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4382 fbc_wm, SNB_FBC_MAX_SRWM, level);
1398261a
YL		 4383
4384 /* fbc has it's own way to disable FBC WM */
4385 I915_WRITE(DISP_ARB_CTL,
4386 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4387 return false;
4388 }
4389
b79d4990 4390 if (display_wm > display->max_wm) {
1398261a 4391 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4392 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1398261a
YL		 4393 return false;
4394 }
4395
b79d4990 4396 if (cursor_wm > cursor->max_wm) {
1398261a 4397 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4398 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1398261a
YL		 4399 return false;
4400 }
4401
4402 if (!(fbc_wm || display_wm || cursor_wm)) {
4403 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4404 return false;
4405 }
4406
4407 return true;
4408}
4409
4410/*
4411 * Compute watermark values of WM[1-3],
4412 */
d210246a
CW		 4413static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4414 int latency_ns,
b79d4990
JB		 4415 const struct intel_watermark_params *display,
4416 const struct intel_watermark_params *cursor,
4417 int *fbc_wm, int *display_wm, int *cursor_wm)
1398261a 4418{
d210246a 4419 struct drm_crtc *crtc;
1398261a 4420 unsigned long line_time_us;
d210246a 4421 int hdisplay, htotal, pixel_size, clock;
b79d4990 4422 int line_count, line_size;
1398261a
YL		 4423 int small, large;
4424 int entries;
1398261a
YL		 4425
4426 if (!latency_ns) {
4427 *fbc_wm = *display_wm = *cursor_wm = 0;
4428 return false;
4429 }
4430
d210246a
CW		 4431 crtc = intel_get_crtc_for_plane(dev, plane);
4432 hdisplay = crtc->mode.hdisplay;
4433 htotal = crtc->mode.htotal;
4434 clock = crtc->mode.clock;
4435 pixel_size = crtc->fb->bits_per_pixel / 8;
4436
1398261a
YL		 4437 line_time_us = (htotal * 1000) / clock;
4438 line_count = (latency_ns / line_time_us + 1000) / 1000;
4439 line_size = hdisplay * pixel_size;
4440
4441 /* Use the minimum of the small and large buffer method for primary */
4442 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4443 large = line_count * line_size;
4444
b79d4990
JB		 4445 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4446 *display_wm = entries + display->guard_size;
1398261a
YL		 4447
4448 /*
b79d4990 4449 * Spec says:
1398261a
YL		 4450 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4451 */
4452 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4453
4454 /* calculate the self-refresh watermark for display cursor */
4455 entries = line_count * pixel_size * 64;
b79d4990
JB		 4456 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4457 *cursor_wm = entries + cursor->guard_size;
1398261a 4458
b79d4990
JB		 4459 return ironlake_check_srwm(dev, level,
4460 *fbc_wm, *display_wm, *cursor_wm,
4461 display, cursor);
4462}
4463
d210246a 4464static void ironlake_update_wm(struct drm_device *dev)
b79d4990
JB		 4465{
4466 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4467 int fbc_wm, plane_wm, cursor_wm;
4468 unsigned int enabled;
b79d4990
JB		 4469
4470 enabled = 0;
9f405100
CW		 4471 if (g4x_compute_wm0(dev, 0,
4472 &ironlake_display_wm_info,
4473 ILK_LP0_PLANE_LATENCY,
4474 &ironlake_cursor_wm_info,
4475 ILK_LP0_CURSOR_LATENCY,
4476 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4477 I915_WRITE(WM0_PIPEA_ILK,
4478 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4479 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4480 " plane %d, " "cursor: %d\n",
4481 plane_wm, cursor_wm);
d210246a 4482 enabled |= 1;
b79d4990
JB		 4483 }
4484
9f405100
CW		 4485 if (g4x_compute_wm0(dev, 1,
4486 &ironlake_display_wm_info,
4487 ILK_LP0_PLANE_LATENCY,
4488 &ironlake_cursor_wm_info,
4489 ILK_LP0_CURSOR_LATENCY,
4490 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4491 I915_WRITE(WM0_PIPEB_ILK,
4492 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4493 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4494 " plane %d, cursor: %d\n",
4495 plane_wm, cursor_wm);
d210246a 4496 enabled |= 2;
b79d4990
JB		 4497 }
4498
4499 /*
4500 * Calculate and update the self-refresh watermark only when one
4501 * display plane is used.
4502 */
4503 I915_WRITE(WM3_LP_ILK, 0);
4504 I915_WRITE(WM2_LP_ILK, 0);
4505 I915_WRITE(WM1_LP_ILK, 0);
4506
d210246a 4507 if (!single_plane_enabled(enabled))
b79d4990 4508 return;
d210246a 4509 enabled = ffs(enabled) - 1;
b79d4990
JB		 4510
4511 /* WM1 */
d210246a
CW		 4512 if (!ironlake_compute_srwm(dev, 1, enabled,
4513 ILK_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4514 &ironlake_display_srwm_info,
4515 &ironlake_cursor_srwm_info,
4516 &fbc_wm, &plane_wm, &cursor_wm))
4517 return;
4518
4519 I915_WRITE(WM1_LP_ILK,
4520 WM1_LP_SR_EN |
4521 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4522 (fbc_wm << WM1_LP_FBC_SHIFT) |
4523 (plane_wm << WM1_LP_SR_SHIFT) |
4524 cursor_wm);
4525
4526 /* WM2 */
d210246a
CW		 4527 if (!ironlake_compute_srwm(dev, 2, enabled,
4528 ILK_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4529 &ironlake_display_srwm_info,
4530 &ironlake_cursor_srwm_info,
4531 &fbc_wm, &plane_wm, &cursor_wm))
4532 return;
4533
4534 I915_WRITE(WM2_LP_ILK,
4535 WM2_LP_EN |
4536 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4537 (fbc_wm << WM1_LP_FBC_SHIFT) |
4538 (plane_wm << WM1_LP_SR_SHIFT) |
4539 cursor_wm);
4540
4541 /*
4542 * WM3 is unsupported on ILK, probably because we don't have latency
4543 * data for that power state
4544 */
1398261a
YL		 4545}
4546
b840d907 4547void sandybridge_update_wm(struct drm_device *dev)
1398261a
YL		 4548{
4549 struct drm_i915_private *dev_priv = dev->dev_private;
a0fa62d3 4550 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
47842649 4551 u32 val;
d210246a
CW		 4552 int fbc_wm, plane_wm, cursor_wm;
4553 unsigned int enabled;
1398261a
YL		 4554
4555 enabled = 0;
9f405100
CW		 4556 if (g4x_compute_wm0(dev, 0,
4557 &sandybridge_display_wm_info, latency,
4558 &sandybridge_cursor_wm_info, latency,
4559 &plane_wm, &cursor_wm)) {
47842649
JB		 4560 val = I915_READ(WM0_PIPEA_ILK);
4561 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4562 I915_WRITE(WM0_PIPEA_ILK, val |
4563 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1398261a
YL		 4564 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4565 " plane %d, " "cursor: %d\n",
4566 plane_wm, cursor_wm);
d210246a 4567 enabled |= 1;
1398261a
YL		 4568 }
4569
9f405100
CW		 4570 if (g4x_compute_wm0(dev, 1,
4571 &sandybridge_display_wm_info, latency,
4572 &sandybridge_cursor_wm_info, latency,
4573 &plane_wm, &cursor_wm)) {
47842649
JB		 4574 val = I915_READ(WM0_PIPEB_ILK);
4575 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4576 I915_WRITE(WM0_PIPEB_ILK, val |
4577 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1398261a
YL		 4578 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4579 " plane %d, cursor: %d\n",
4580 plane_wm, cursor_wm);
d210246a 4581 enabled |= 2;
1398261a
YL		 4582 }
4583
d6c892df
JB		 4584 /* IVB has 3 pipes */
4585 if (IS_IVYBRIDGE(dev) &&
4586 g4x_compute_wm0(dev, 2,
4587 &sandybridge_display_wm_info, latency,
4588 &sandybridge_cursor_wm_info, latency,
4589 &plane_wm, &cursor_wm)) {
47842649
JB		 4590 val = I915_READ(WM0_PIPEC_IVB);
4591 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4592 I915_WRITE(WM0_PIPEC_IVB, val |
4593 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
d6c892df
JB		 4594 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4595 " plane %d, cursor: %d\n",
4596 plane_wm, cursor_wm);
4597 enabled |= 3;
4598 }
4599
1398261a
YL		 4600 /*
4601 * Calculate and update the self-refresh watermark only when one
4602 * display plane is used.
4603 *
4604 * SNB support 3 levels of watermark.
4605 *
4606 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4607 * and disabled in the descending order
4608 *
4609 */
4610 I915_WRITE(WM3_LP_ILK, 0);
4611 I915_WRITE(WM2_LP_ILK, 0);
4612 I915_WRITE(WM1_LP_ILK, 0);
4613
b840d907
JB		 4614 if (!single_plane_enabled(enabled) ||
4615 dev_priv->sprite_scaling_enabled)
1398261a 4616 return;
d210246a 4617 enabled = ffs(enabled) - 1;
1398261a
YL		 4618
4619 /* WM1 */
d210246a
CW		 4620 if (!ironlake_compute_srwm(dev, 1, enabled,
4621 SNB_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4622 &sandybridge_display_srwm_info,
4623 &sandybridge_cursor_srwm_info,
4624 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4625 return;
4626
4627 I915_WRITE(WM1_LP_ILK,
4628 WM1_LP_SR_EN |
4629 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4630 (fbc_wm << WM1_LP_FBC_SHIFT) |
4631 (plane_wm << WM1_LP_SR_SHIFT) |
4632 cursor_wm);
4633
4634 /* WM2 */
d210246a
CW		 4635 if (!ironlake_compute_srwm(dev, 2, enabled,
4636 SNB_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4637 &sandybridge_display_srwm_info,
4638 &sandybridge_cursor_srwm_info,
4639 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4640 return;
4641
4642 I915_WRITE(WM2_LP_ILK,
4643 WM2_LP_EN |
4644 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4645 (fbc_wm << WM1_LP_FBC_SHIFT) |
4646 (plane_wm << WM1_LP_SR_SHIFT) |
4647 cursor_wm);
4648
4649 /* WM3 */
d210246a
CW		 4650 if (!ironlake_compute_srwm(dev, 3, enabled,
4651 SNB_READ_WM3_LATENCY() * 500,
b79d4990
JB		 4652 &sandybridge_display_srwm_info,
4653 &sandybridge_cursor_srwm_info,
4654 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4655 return;
4656
4657 I915_WRITE(WM3_LP_ILK,
4658 WM3_LP_EN |
4659 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4660 (fbc_wm << WM1_LP_FBC_SHIFT) |
4661 (plane_wm << WM1_LP_SR_SHIFT) |
4662 cursor_wm);
4663}
4664
b840d907
JB		 4665static bool
4666sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4667 uint32_t sprite_width, int pixel_size,
4668 const struct intel_watermark_params *display,
4669 int display_latency_ns, int *sprite_wm)
4670{
4671 struct drm_crtc *crtc;
4672 int clock;
4673 int entries, tlb_miss;
4674
4675 crtc = intel_get_crtc_for_plane(dev, plane);
4676 if (crtc->fb == NULL || !crtc->enabled) {
4677 *sprite_wm = display->guard_size;
4678 return false;
4679 }
4680
4681 clock = crtc->mode.clock;
4682
4683 /* Use the small buffer method to calculate the sprite watermark */
4684 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4685 tlb_miss = display->fifo_size*display->cacheline_size -
4686 sprite_width * 8;
4687 if (tlb_miss > 0)
4688 entries += tlb_miss;
4689 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4690 *sprite_wm = entries + display->guard_size;
4691 if (*sprite_wm > (int)display->max_wm)
4692 *sprite_wm = display->max_wm;
4693
4694 return true;
4695}
4696
4697static bool
4698sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4699 uint32_t sprite_width, int pixel_size,
4700 const struct intel_watermark_params *display,
4701 int latency_ns, int *sprite_wm)
4702{
4703 struct drm_crtc *crtc;
4704 unsigned long line_time_us;
4705 int clock;
4706 int line_count, line_size;
4707 int small, large;
4708 int entries;
4709
4710 if (!latency_ns) {
4711 *sprite_wm = 0;
4712 return false;
4713 }
4714
4715 crtc = intel_get_crtc_for_plane(dev, plane);
4716 clock = crtc->mode.clock;
4717
4718 line_time_us = (sprite_width * 1000) / clock;
4719 line_count = (latency_ns / line_time_us + 1000) / 1000;
4720 line_size = sprite_width * pixel_size;
4721
4722 /* Use the minimum of the small and large buffer method for primary */
4723 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4724 large = line_count * line_size;
4725
4726 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4727 *sprite_wm = entries + display->guard_size;
4728
4729 return *sprite_wm > 0x3ff ? false : true;
4730}
4731
4732static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4733 uint32_t sprite_width, int pixel_size)
4734{
4735 struct drm_i915_private *dev_priv = dev->dev_private;
4736 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
47842649 4737 u32 val;
b840d907
JB		 4738 int sprite_wm, reg;
4739 int ret;
4740
4741 switch (pipe) {
4742 case 0:
4743 reg = WM0_PIPEA_ILK;
4744 break;
4745 case 1:
4746 reg = WM0_PIPEB_ILK;
4747 break;
4748 case 2:
4749 reg = WM0_PIPEC_IVB;
4750 break;
4751 default:
4752 return; /* bad pipe */
4753 }
4754
4755 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4756 &sandybridge_display_wm_info,
4757 latency, &sprite_wm);
4758 if (!ret) {
4759 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4760 pipe);
4761 return;
4762 }
4763
47842649
JB		 4764 val = I915_READ(reg);
4765 val &= ~WM0_PIPE_SPRITE_MASK;
4766 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
b840d907
JB		 4767 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4768
4769
4770 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4771 pixel_size,
4772 &sandybridge_display_srwm_info,
4773 SNB_READ_WM1_LATENCY() * 500,
4774 &sprite_wm);
4775 if (!ret) {
4776 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4777 pipe);
4778 return;
4779 }
4780 I915_WRITE(WM1S_LP_ILK, sprite_wm);
4781
4782 /* Only IVB has two more LP watermarks for sprite */
4783 if (!IS_IVYBRIDGE(dev))
4784 return;
4785
4786 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4787 pixel_size,
4788 &sandybridge_display_srwm_info,
4789 SNB_READ_WM2_LATENCY() * 500,
4790 &sprite_wm);
4791 if (!ret) {
4792 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4793 pipe);
4794 return;
4795 }
4796 I915_WRITE(WM2S_LP_IVB, sprite_wm);
4797
4798 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4799 pixel_size,
4800 &sandybridge_display_srwm_info,
4801 SNB_READ_WM3_LATENCY() * 500,
4802 &sprite_wm);
4803 if (!ret) {
4804 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4805 pipe);
4806 return;
4807 }
4808 I915_WRITE(WM3S_LP_IVB, sprite_wm);
4809}
4810
7662c8bd
SL		 4811/**
4812 * intel_update_watermarks - update FIFO watermark values based on current modes
4813 *
4814 * Calculate watermark values for the various WM regs based on current mode
4815 * and plane configuration.
4816 *
4817 * There are several cases to deal with here:
4818 * - normal (i.e. non-self-refresh)
4819 * - self-refresh (SR) mode
4820 * - lines are large relative to FIFO size (buffer can hold up to 2)
4821 * - lines are small relative to FIFO size (buffer can hold more than 2
4822 * lines), so need to account for TLB latency
4823 *
4824 * The normal calculation is:
4825 * watermark = dotclock * bytes per pixel * latency
4826 * where latency is platform & configuration dependent (we assume pessimal
4827 * values here).
4828 *
4829 * The SR calculation is:
4830 * watermark = (trunc(latency/line time)+1) * surface width *
4831 * bytes per pixel
4832 * where
4833 * line time = htotal / dotclock
fa143215 4834 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL		 4835 * and latency is assumed to be high, as above.
4836 *
4837 * The final value programmed to the register should always be rounded up,
4838 * and include an extra 2 entries to account for clock crossings.
4839 *
4840 * We don't use the sprite, so we can ignore that. And on Crestline we have
4841 * to set the non-SR watermarks to 8.
5eddb70b 4842 */
7662c8bd
SL		 4843static void intel_update_watermarks(struct drm_device *dev)
4844{
e70236a8 4845 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 4846
d210246a
CW		 4847 if (dev_priv->display.update_wm)
4848 dev_priv->display.update_wm(dev);
7662c8bd
SL		 4849}
4850
b840d907
JB		 4851void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4852 uint32_t sprite_width, int pixel_size)
4853{
4854 struct drm_i915_private *dev_priv = dev->dev_private;
4855
4856 if (dev_priv->display.update_sprite_wm)
4857 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4858 pixel_size);
4859}
4860
a7615030
CW		 4861static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4862{
72bbe58c
KP		 4863 if (i915_panel_use_ssc >= 0)
4864 return i915_panel_use_ssc != 0;
4865 return dev_priv->lvds_use_ssc
435793df 4866 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4867}
4868
5a354204
JB		 4869/**
4870 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4871 * @crtc: CRTC structure
3b5c78a3 4872 * @mode: requested mode
5a354204
JB		 4873 *
4874 * A pipe may be connected to one or more outputs. Based on the depth of the
4875 * attached framebuffer, choose a good color depth to use on the pipe.
4876 *
4877 * If possible, match the pipe depth to the fb depth. In some cases, this
4878 * isn't ideal, because the connected output supports a lesser or restricted
4879 * set of depths. Resolve that here:
4880 * LVDS typically supports only 6bpc, so clamp down in that case
4881 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4882 * Displays may support a restricted set as well, check EDID and clamp as
4883 * appropriate.
3b5c78a3 4884 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4885 *
4886 * RETURNS:
4887 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4888 * true if they don't match).
4889 */
4890static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3b5c78a3
AJ		 4891 unsigned int *pipe_bpp,
4892 struct drm_display_mode *mode)
5a354204
JB		 4893{
4894 struct drm_device *dev = crtc->dev;
4895 struct drm_i915_private *dev_priv = dev->dev_private;
4896 struct drm_encoder *encoder;
4897 struct drm_connector *connector;
4898 unsigned int display_bpc = UINT_MAX, bpc;
4899
4900 /* Walk the encoders & connectors on this crtc, get min bpc */
4901 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4902 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4903
4904 if (encoder->crtc != crtc)
4905 continue;
4906
4907 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4908 unsigned int lvds_bpc;
4909
4910 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4911 LVDS_A3_POWER_UP)
4912 lvds_bpc = 8;
4913 else
4914 lvds_bpc = 6;
4915
4916 if (lvds_bpc < display_bpc) {
82820490 4917 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4918 display_bpc = lvds_bpc;
4919 }
4920 continue;
4921 }
4922
4923 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4924 /* Use VBT settings if we have an eDP panel */
4925 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4926
4927 if (edp_bpc < display_bpc) {
82820490 4928 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5a354204
JB		 4929 display_bpc = edp_bpc;
4930 }
4931 continue;
4932 }
4933
4934 /* Not one of the known troublemakers, check the EDID */
4935 list_for_each_entry(connector, &dev->mode_config.connector_list,
4936 head) {
4937 if (connector->encoder != encoder)
4938 continue;
4939
62ac41a6
JB		 4940 /* Don't use an invalid EDID bpc value */
4941 if (connector->display_info.bpc &&
4942 connector->display_info.bpc < display_bpc) {
82820490 4943 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4944 display_bpc = connector->display_info.bpc;
4945 }
4946 }
4947
4948 /*
4949 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4950 * through, clamp it down. (Note: >12bpc will be caught below.)
4951 */
4952 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4953 if (display_bpc > 8 && display_bpc < 12) {
82820490 4954 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4955 display_bpc = 12;
4956 } else {
82820490 4957 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4958 display_bpc = 8;
4959 }
4960 }
4961 }
4962
3b5c78a3
AJ		 4963 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4964 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4965 display_bpc = 6;
4966 }
4967
5a354204
JB		 4968 /*
4969 * We could just drive the pipe at the highest bpc all the time and
4970 * enable dithering as needed, but that costs bandwidth. So choose
4971 * the minimum value that expresses the full color range of the fb but
4972 * also stays within the max display bpc discovered above.
4973 */
4974
4975 switch (crtc->fb->depth) {
4976 case 8:
4977 bpc = 8; /* since we go through a colormap */
4978 break;
4979 case 15:
4980 case 16:
4981 bpc = 6; /* min is 18bpp */
4982 break;
4983 case 24:
578393cd 4984 bpc = 8;
5a354204
JB		 4985 break;
4986 case 30:
578393cd 4987 bpc = 10;
5a354204
JB		 4988 break;
4989 case 48:
578393cd 4990 bpc = 12;
5a354204
JB		 4991 break;
4992 default:
4993 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4994 bpc = min((unsigned int)8, display_bpc);
4995 break;
4996 }
4997
578393cd
KP		 4998 display_bpc = min(display_bpc, bpc);
4999
82820490
AJ		 5000 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5001 bpc, display_bpc);
5a354204 5002
578393cd 5003 *pipe_bpp = display_bpc * 3;
5a354204
JB		 5004
5005 return display_bpc != bpc;
5006}
5007
c65d77d8
JB		 5008static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5009{
5010 struct drm_device *dev = crtc->dev;
5011 struct drm_i915_private *dev_priv = dev->dev_private;
5012 int refclk;
5013
5014 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5015 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5016 refclk = dev_priv->lvds_ssc_freq * 1000;
5017 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5018 refclk / 1000);
5019 } else if (!IS_GEN2(dev)) {
5020 refclk = 96000;
5021 } else {
5022 refclk = 48000;
5023 }
5024
5025 return refclk;
5026}
5027
5028static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5029 intel_clock_t *clock)
5030{
5031 /* SDVO TV has fixed PLL values depend on its clock range,
5032 this mirrors vbios setting. */
5033 if (adjusted_mode->clock >= 100000
5034 && adjusted_mode->clock < 140500) {
5035 clock->p1 = 2;
5036 clock->p2 = 10;
5037 clock->n = 3;
5038 clock->m1 = 16;
5039 clock->m2 = 8;
5040 } else if (adjusted_mode->clock >= 140500
5041 && adjusted_mode->clock <= 200000) {
5042 clock->p1 = 1;
5043 clock->p2 = 10;
5044 clock->n = 6;
5045 clock->m1 = 12;
5046 clock->m2 = 8;
5047 }
5048}
5049
a7516a05
JB		 5050static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5051 intel_clock_t *clock,
5052 intel_clock_t *reduced_clock)
5053{
5054 struct drm_device *dev = crtc->dev;
5055 struct drm_i915_private *dev_priv = dev->dev_private;
5056 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5057 int pipe = intel_crtc->pipe;
5058 u32 fp, fp2 = 0;
5059
5060 if (IS_PINEVIEW(dev)) {
5061 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5062 if (reduced_clock)
5063 fp2 = (1 << reduced_clock->n) << 16 |
5064 reduced_clock->m1 << 8 | reduced_clock->m2;
5065 } else {
5066 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5067 if (reduced_clock)
5068 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5069 reduced_clock->m2;
5070 }
5071
5072 I915_WRITE(FP0(pipe), fp);
5073
5074 intel_crtc->lowfreq_avail = false;
5075 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5076 reduced_clock && i915_powersave) {
5077 I915_WRITE(FP1(pipe), fp2);
5078 intel_crtc->lowfreq_avail = true;
5079 } else {
5080 I915_WRITE(FP1(pipe), fp);
5081 }
5082}
5083
f564048e
EA		 5084static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5085 struct drm_display_mode *mode,
5086 struct drm_display_mode *adjusted_mode,
5087 int x, int y,
5088 struct drm_framebuffer *old_fb)
79e53945
JB		 5089{
5090 struct drm_device *dev = crtc->dev;
5091 struct drm_i915_private *dev_priv = dev->dev_private;
5092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5093 int pipe = intel_crtc->pipe;
80824003 5094 int plane = intel_crtc->plane;
c751ce4f 5095 int refclk, num_connectors = 0;
652c393a 5096 intel_clock_t clock, reduced_clock;
a7516a05 5097 u32 dpll, dspcntr, pipeconf;
652c393a 5098 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
a4fc5ed6 5099 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 5100 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 5101 struct intel_encoder *encoder;
d4906093 5102 const intel_limit_t *limit;
5c3b82e2 5103 int ret;
fae14981 5104 u32 temp;
aa9b500d 5105 u32 lvds_sync = 0;
79e53945 5106
5eddb70b
CW		 5107 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5108 if (encoder->base.crtc != crtc)
79e53945
JB		 5109 continue;
5110
5eddb70b 5111 switch (encoder->type) {
79e53945
JB		 5112 case INTEL_OUTPUT_LVDS:
5113 is_lvds = true;
5114 break;
5115 case INTEL_OUTPUT_SDVO:
7d57382e 5116 case INTEL_OUTPUT_HDMI:
79e53945 5117 is_sdvo = true;
5eddb70b 5118 if (encoder->needs_tv_clock)
e2f0ba97 5119 is_tv = true;
79e53945
JB		 5120 break;
5121 case INTEL_OUTPUT_DVO:
5122 is_dvo = true;
5123 break;
5124 case INTEL_OUTPUT_TVOUT:
5125 is_tv = true;
5126 break;
5127 case INTEL_OUTPUT_ANALOG:
5128 is_crt = true;
5129 break;
a4fc5ed6
KP		 5130 case INTEL_OUTPUT_DISPLAYPORT:
5131 is_dp = true;
5132 break;
79e53945 5133 }
43565a06 5134
c751ce4f 5135 num_connectors++;
79e53945
JB		 5136 }
5137
c65d77d8 5138 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 5139
d4906093
ML		 5140 /*
5141 * Returns a set of divisors for the desired target clock with the given
5142 * refclk, or FALSE. The returned values represent the clock equation:
5143 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5144 */
1b894b59 5145 limit = intel_limit(crtc, refclk);
cec2f356
SP		 5146 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5147 &clock);
79e53945
JB		 5148 if (!ok) {
5149 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 5150 return -EINVAL;
79e53945
JB		 5151 }
5152
cda4b7d3 5153 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 5154 intel_crtc_update_cursor(crtc, true);
cda4b7d3 5155
ddc9003c 5156 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5157 /*
5158 * Ensure we match the reduced clock's P to the target clock.
5159 * If the clocks don't match, we can't switch the display clock
5160 * by using the FP0/FP1. In such case we will disable the LVDS
5161 * downclock feature.
5162 */
ddc9003c 5163 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 5164 dev_priv->lvds_downclock,
5165 refclk,
cec2f356 5166 &clock,
5eddb70b 5167 &reduced_clock);
652c393a 5168 }
c65d77d8
JB		 5169
5170 if (is_sdvo && is_tv)
5171 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 5172
a7516a05
JB		 5173 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5174 &reduced_clock : NULL);
79e53945 5175
929c77fb 5176 dpll = DPLL_VGA_MODE_DIS;
2c07245f 5177
a6c45cf0 5178 if (!IS_GEN2(dev)) {
79e53945
JB		 5179 if (is_lvds)
5180 dpll |= DPLLB_MODE_LVDS;
5181 else
5182 dpll |= DPLLB_MODE_DAC_SERIAL;
5183 if (is_sdvo) {
6c9547ff
CW		 5184 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5185 if (pixel_multiplier > 1) {
5186 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5187 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
6c9547ff 5188 }
79e53945 5189 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5190 }
929c77fb 5191 if (is_dp)
a4fc5ed6 5192 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945
JB		 5193
5194 /* compute bitmask from p1 value */
f2b115e6
AJ		 5195 if (IS_PINEVIEW(dev))
5196 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
2c07245f 5197 else {
2177832f 5198 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
652c393a
JB		 5199 if (IS_G4X(dev) && has_reduced_clock)
5200 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2c07245f 5201 }
79e53945
JB		 5202 switch (clock.p2) {
5203 case 5:
5204 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5205 break;
5206 case 7:
5207 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5208 break;
5209 case 10:
5210 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5211 break;
5212 case 14:
5213 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5214 break;
5215 }
929c77fb 5216 if (INTEL_INFO(dev)->gen >= 4)
79e53945
JB		 5217 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5218 } else {
5219 if (is_lvds) {
5220 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5221 } else {
5222 if (clock.p1 == 2)
5223 dpll |= PLL_P1_DIVIDE_BY_TWO;
5224 else
5225 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5226 if (clock.p2 == 4)
5227 dpll |= PLL_P2_DIVIDE_BY_4;
5228 }
5229 }
5230
43565a06
KH		 5231 if (is_sdvo && is_tv)
5232 dpll |= PLL_REF_INPUT_TVCLKINBC;
5233 else if (is_tv)
79e53945 5234 /* XXX: just matching BIOS for now */
43565a06 5235 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5236 dpll |= 3;
a7615030 5237 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5238 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5239 else
5240 dpll |= PLL_REF_INPUT_DREFCLK;
5241
5242 /* setup pipeconf */
5eddb70b 5243 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5244
5245 /* Set up the display plane register */
5246 dspcntr = DISPPLANE_GAMMA_ENABLE;
5247
929c77fb
EA		 5248 if (pipe == 0)
5249 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5250 else
5251 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 5252
a6c45cf0 5253 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 5254 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5255 * core speed.
5256 *
5257 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5258 * pipe == 0 check?
5259 */
e70236a8
JB		 5260 if (mode->clock >
5261 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 5262 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 5263 else
5eddb70b 5264 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 5265 }
5266
3b5c78a3
AJ		 5267 /* default to 8bpc */
5268 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5269 if (is_dp) {
5270 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5271 pipeconf |= PIPECONF_BPP_6 |
5272 PIPECONF_DITHER_EN |
5273 PIPECONF_DITHER_TYPE_SP;
5274 }
5275 }
5276
929c77fb 5277 dpll |= DPLL_VCO_ENABLE;
8d86dc6a 5278
28c97730 5279 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 5280 drm_mode_debug_printmodeline(mode);
5281
fae14981 5282 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 5283
fae14981 5284 POSTING_READ(DPLL(pipe));
c713bb08 5285 udelay(150);
8db9d77b 5286
79e53945
JB		 5287 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5288 * This is an exception to the general rule that mode_set doesn't turn
5289 * things on.
5290 */
5291 if (is_lvds) {
fae14981 5292 temp = I915_READ(LVDS);
5eddb70b 5293 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3 5294 if (pipe == 1) {
929c77fb 5295 temp |= LVDS_PIPEB_SELECT;
b3b095b3 5296 } else {
929c77fb 5297 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 5298 }
a3e17eb8 5299 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5300 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5301 /* Set the B0-B3 data pairs corresponding to whether we're going to
5302 * set the DPLLs for dual-channel mode or not.
5303 */
5304 if (clock.p2 == 7)
5eddb70b 5305 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5306 else
5eddb70b 5307 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5308
5309 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5310 * appropriately here, but we need to look more thoroughly into how
5311 * panels behave in the two modes.
5312 */
929c77fb
EA		 5313 /* set the dithering flag on LVDS as needed */
5314 if (INTEL_INFO(dev)->gen >= 4) {
434ed097 5315 if (dev_priv->lvds_dither)
5eddb70b 5316 temp |= LVDS_ENABLE_DITHER;
434ed097 5317 else
5eddb70b 5318 temp &= ~LVDS_ENABLE_DITHER;
898822ce 5319 }
aa9b500d
BF		 5320 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5321 lvds_sync |= LVDS_HSYNC_POLARITY;
5322 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5323 lvds_sync |= LVDS_VSYNC_POLARITY;
5324 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5325 != lvds_sync) {
5326 char flags[2] = "-+";
5327 DRM_INFO("Changing LVDS panel from "
5328 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5329 flags[!(temp & LVDS_HSYNC_POLARITY)],
5330 flags[!(temp & LVDS_VSYNC_POLARITY)],
5331 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5332 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5333 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5334 temp |= lvds_sync;
5335 }
fae14981 5336 I915_WRITE(LVDS, temp);
79e53945 5337 }
434ed097 5338
929c77fb 5339 if (is_dp) {
a4fc5ed6 5340 intel_dp_set_m_n(crtc, mode, adjusted_mode);
434ed097
JB		 5341 }
5342
fae14981 5343 I915_WRITE(DPLL(pipe), dpll);
5eddb70b 5344
c713bb08 5345 /* Wait for the clocks to stabilize. */
fae14981 5346 POSTING_READ(DPLL(pipe));
c713bb08 5347 udelay(150);
32f9d658 5348
c713bb08
EA		 5349 if (INTEL_INFO(dev)->gen >= 4) {
5350 temp = 0;
5351 if (is_sdvo) {
5352 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5353 if (temp > 1)
5354 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5355 else
5356 temp = 0;
32f9d658 5357 }
c713bb08
EA		 5358 I915_WRITE(DPLL_MD(pipe), temp);
5359 } else {
5360 /* The pixel multiplier can only be updated once the
5361 * DPLL is enabled and the clocks are stable.
5362 *
5363 * So write it again.
5364 */
fae14981 5365 I915_WRITE(DPLL(pipe), dpll);
79e53945 5366 }
79e53945 5367
a7516a05
JB		 5368 if (HAS_PIPE_CXSR(dev)) {
5369 if (intel_crtc->lowfreq_avail) {
28c97730 5370 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 5371 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 5372 } else {
28c97730 5373 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5374 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5375 }
5376 }
5377
734b4157
KH		 5378 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5379 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5380 /* the chip adds 2 halflines automatically */
5381 adjusted_mode->crtc_vdisplay -= 1;
5382 adjusted_mode->crtc_vtotal -= 1;
5383 adjusted_mode->crtc_vblank_start -= 1;
5384 adjusted_mode->crtc_vblank_end -= 1;
5385 adjusted_mode->crtc_vsync_end -= 1;
5386 adjusted_mode->crtc_vsync_start -= 1;
5387 } else
59df7b17 5388 pipeconf &= ~PIPECONF_INTERLACE_MASK; /* progressive */
734b4157 5389
5eddb70b
CW		 5390 I915_WRITE(HTOTAL(pipe),
5391 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5392 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5393 I915_WRITE(HBLANK(pipe),
5394 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5395 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5396 I915_WRITE(HSYNC(pipe),
5397 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5398 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5399
5400 I915_WRITE(VTOTAL(pipe),
5401 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5402 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5403 I915_WRITE(VBLANK(pipe),
5404 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5405 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5406 I915_WRITE(VSYNC(pipe),
5407 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5408 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 5409
5410 /* pipesrc and dspsize control the size that is scaled from,
5411 * which should always be the user's requested size.
79e53945 5412 */
929c77fb
EA		 5413 I915_WRITE(DSPSIZE(plane),
5414 ((mode->vdisplay - 1) << 16) |
5415 (mode->hdisplay - 1));
5416 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 5417 I915_WRITE(PIPESRC(pipe),
5418 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5419
f564048e
EA		 5420 I915_WRITE(PIPECONF(pipe), pipeconf);
5421 POSTING_READ(PIPECONF(pipe));
929c77fb 5422 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 5423
5424 intel_wait_for_vblank(dev, pipe);
5425
f564048e
EA		 5426 I915_WRITE(DSPCNTR(plane), dspcntr);
5427 POSTING_READ(DSPCNTR(plane));
284d9529 5428 intel_enable_plane(dev_priv, plane, pipe);
f564048e
EA		 5429
5430 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5431
5432 intel_update_watermarks(dev);
5433
f564048e
EA		 5434 return ret;
5435}
5436
9fb526db
KP		 5437/*
5438 * Initialize reference clocks when the driver loads
5439 */
5440void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5441{
5442 struct drm_i915_private *dev_priv = dev->dev_private;
5443 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5444 struct intel_encoder *encoder;
13d83a67
JB		 5445 u32 temp;
5446 bool has_lvds = false;
199e5d79
KP		 5447 bool has_cpu_edp = false;
5448 bool has_pch_edp = false;
5449 bool has_panel = false;
99eb6a01
KP		 5450 bool has_ck505 = false;
5451 bool can_ssc = false;
13d83a67
JB		 5452
5453 /* We need to take the global config into account */
199e5d79
KP		 5454 list_for_each_entry(encoder, &mode_config->encoder_list,
5455 base.head) {
5456 switch (encoder->type) {
5457 case INTEL_OUTPUT_LVDS:
5458 has_panel = true;
5459 has_lvds = true;
5460 break;
5461 case INTEL_OUTPUT_EDP:
5462 has_panel = true;
5463 if (intel_encoder_is_pch_edp(&encoder->base))
5464 has_pch_edp = true;
5465 else
5466 has_cpu_edp = true;
5467 break;
13d83a67
JB		 5468 }
5469 }
5470
99eb6a01
KP		 5471 if (HAS_PCH_IBX(dev)) {
5472 has_ck505 = dev_priv->display_clock_mode;
5473 can_ssc = has_ck505;
5474 } else {
5475 has_ck505 = false;
5476 can_ssc = true;
5477 }
5478
5479 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5480 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5481 has_ck505);
13d83a67
JB		 5482
5483 /* Ironlake: try to setup display ref clock before DPLL
5484 * enabling. This is only under driver's control after
5485 * PCH B stepping, previous chipset stepping should be
5486 * ignoring this setting.
5487 */
5488 temp = I915_READ(PCH_DREF_CONTROL);
5489 /* Always enable nonspread source */
5490 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5491
99eb6a01
KP		 5492 if (has_ck505)
5493 temp |= DREF_NONSPREAD_CK505_ENABLE;
5494 else
5495 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5496
199e5d79
KP		 5497 if (has_panel) {
5498 temp &= ~DREF_SSC_SOURCE_MASK;
5499 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5500
199e5d79 5501 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5502 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5503 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 5504 temp |= DREF_SSC1_ENABLE;
13d83a67 5505 }
199e5d79
KP		 5506
5507 /* Get SSC going before enabling the outputs */
5508 I915_WRITE(PCH_DREF_CONTROL, temp);
5509 POSTING_READ(PCH_DREF_CONTROL);
5510 udelay(200);
5511
13d83a67
JB		 5512 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5513
5514 /* Enable CPU source on CPU attached eDP */
199e5d79 5515 if (has_cpu_edp) {
99eb6a01 5516 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5517 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 5518 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5519 }
13d83a67
JB		 5520 else
5521 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 5522 } else
5523 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5524
5525 I915_WRITE(PCH_DREF_CONTROL, temp);
5526 POSTING_READ(PCH_DREF_CONTROL);
5527 udelay(200);
5528 } else {
5529 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5530
5531 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5532
5533 /* Turn off CPU output */
5534 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5535
5536 I915_WRITE(PCH_DREF_CONTROL, temp);
5537 POSTING_READ(PCH_DREF_CONTROL);
5538 udelay(200);
5539
5540 /* Turn off the SSC source */
5541 temp &= ~DREF_SSC_SOURCE_MASK;
5542 temp |= DREF_SSC_SOURCE_DISABLE;
5543
5544 /* Turn off SSC1 */
5545 temp &= ~ DREF_SSC1_ENABLE;
5546
13d83a67
JB		 5547 I915_WRITE(PCH_DREF_CONTROL, temp);
5548 POSTING_READ(PCH_DREF_CONTROL);
5549 udelay(200);
5550 }
5551}
5552
d9d444cb
JB		 5553static int ironlake_get_refclk(struct drm_crtc *crtc)
5554{
5555 struct drm_device *dev = crtc->dev;
5556 struct drm_i915_private *dev_priv = dev->dev_private;
5557 struct intel_encoder *encoder;
5558 struct drm_mode_config *mode_config = &dev->mode_config;
5559 struct intel_encoder *edp_encoder = NULL;
5560 int num_connectors = 0;
5561 bool is_lvds = false;
5562
5563 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5564 if (encoder->base.crtc != crtc)
5565 continue;
5566
5567 switch (encoder->type) {
5568 case INTEL_OUTPUT_LVDS:
5569 is_lvds = true;
5570 break;
5571 case INTEL_OUTPUT_EDP:
5572 edp_encoder = encoder;
5573 break;
5574 }
5575 num_connectors++;
5576 }
5577
5578 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5579 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5580 dev_priv->lvds_ssc_freq);
5581 return dev_priv->lvds_ssc_freq * 1000;
5582 }
5583
5584 return 120000;
5585}
5586
f564048e
EA		 5587static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5588 struct drm_display_mode *mode,
5589 struct drm_display_mode *adjusted_mode,
5590 int x, int y,
5591 struct drm_framebuffer *old_fb)
79e53945
JB		 5592{
5593 struct drm_device *dev = crtc->dev;
5594 struct drm_i915_private *dev_priv = dev->dev_private;
5595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5596 int pipe = intel_crtc->pipe;
80824003 5597 int plane = intel_crtc->plane;
c751ce4f 5598 int refclk, num_connectors = 0;
652c393a 5599 intel_clock_t clock, reduced_clock;
5eddb70b 5600 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 5601 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 5602 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
8e647a27 5603 struct intel_encoder *has_edp_encoder = NULL;
79e53945 5604 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 5605 struct intel_encoder *encoder;
d4906093 5606 const intel_limit_t *limit;
5c3b82e2 5607 int ret;
2c07245f 5608 struct fdi_m_n m_n = {0};
fae14981 5609 u32 temp;
aa9b500d 5610 u32 lvds_sync = 0;
5a354204
JB		 5611 int target_clock, pixel_multiplier, lane, link_bw, factor;
5612 unsigned int pipe_bpp;
5613 bool dither;
79e53945 5614
5eddb70b
CW		 5615 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5616 if (encoder->base.crtc != crtc)
79e53945
JB		 5617 continue;
5618
5eddb70b 5619 switch (encoder->type) {
79e53945
JB		 5620 case INTEL_OUTPUT_LVDS:
5621 is_lvds = true;
5622 break;
5623 case INTEL_OUTPUT_SDVO:
7d57382e 5624 case INTEL_OUTPUT_HDMI:
79e53945 5625 is_sdvo = true;
5eddb70b 5626 if (encoder->needs_tv_clock)
e2f0ba97 5627 is_tv = true;
79e53945 5628 break;
79e53945
JB		 5629 case INTEL_OUTPUT_TVOUT:
5630 is_tv = true;
5631 break;
5632 case INTEL_OUTPUT_ANALOG:
5633 is_crt = true;
5634 break;
a4fc5ed6
KP		 5635 case INTEL_OUTPUT_DISPLAYPORT:
5636 is_dp = true;
5637 break;
32f9d658 5638 case INTEL_OUTPUT_EDP:
5eddb70b 5639 has_edp_encoder = encoder;
32f9d658 5640 break;
79e53945 5641 }
43565a06 5642
c751ce4f 5643 num_connectors++;
79e53945
JB		 5644 }
5645
d9d444cb 5646 refclk = ironlake_get_refclk(crtc);
79e53945 5647
d4906093
ML		 5648 /*
5649 * Returns a set of divisors for the desired target clock with the given
5650 * refclk, or FALSE. The returned values represent the clock equation:
5651 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5652 */
1b894b59 5653 limit = intel_limit(crtc, refclk);
cec2f356
SP		 5654 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5655 &clock);
79e53945
JB		 5656 if (!ok) {
5657 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 5658 return -EINVAL;
79e53945
JB		 5659 }
5660
cda4b7d3 5661 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 5662 intel_crtc_update_cursor(crtc, true);
cda4b7d3 5663
ddc9003c 5664 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5665 /*
5666 * Ensure we match the reduced clock's P to the target clock.
5667 * If the clocks don't match, we can't switch the display clock
5668 * by using the FP0/FP1. In such case we will disable the LVDS
5669 * downclock feature.
5670 */
ddc9003c 5671 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 5672 dev_priv->lvds_downclock,
5673 refclk,
cec2f356 5674 &clock,
5eddb70b 5675 &reduced_clock);
652c393a 5676 }
7026d4ac
ZW		 5677 /* SDVO TV has fixed PLL values depend on its clock range,
5678 this mirrors vbios setting. */
5679 if (is_sdvo && is_tv) {
5680 if (adjusted_mode->clock >= 100000
5eddb70b 5681 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 5682 clock.p1 = 2;
5683 clock.p2 = 10;
5684 clock.n = 3;
5685 clock.m1 = 16;
5686 clock.m2 = 8;
5687 } else if (adjusted_mode->clock >= 140500
5eddb70b 5688 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 5689 clock.p1 = 1;
5690 clock.p2 = 10;
5691 clock.n = 6;
5692 clock.m1 = 12;
5693 clock.m2 = 8;
5694 }
5695 }
5696
2c07245f 5697 /* FDI link */
8febb297
EA		 5698 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5699 lane = 0;
5700 /* CPU eDP doesn't require FDI link, so just set DP M/N
5701 according to current link config */
5702 if (has_edp_encoder &&
5703 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5704 target_clock = mode->clock;
5705 intel_edp_link_config(has_edp_encoder,
5706 &lane, &link_bw);
5707 } else {
5708 /* [e]DP over FDI requires target mode clock
5709 instead of link clock */
5710 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5eb08b69 5711 target_clock = mode->clock;
8febb297
EA		 5712 else
5713 target_clock = adjusted_mode->clock;
5714
5715 /* FDI is a binary signal running at ~2.7GHz, encoding
5716 * each output octet as 10 bits. The actual frequency
5717 * is stored as a divider into a 100MHz clock, and the
5718 * mode pixel clock is stored in units of 1KHz.
5719 * Hence the bw of each lane in terms of the mode signal
5720 * is:
5721 */
5722 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5723 }
58a27471 5724
8febb297
EA		 5725 /* determine panel color depth */
5726 temp = I915_READ(PIPECONF(pipe));
5727 temp &= ~PIPE_BPC_MASK;
3b5c78a3 5728 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5a354204
JB		 5729 switch (pipe_bpp) {
5730 case 18:
5731 temp |= PIPE_6BPC;
8febb297 5732 break;
5a354204
JB		 5733 case 24:
5734 temp |= PIPE_8BPC;
8febb297 5735 break;
5a354204
JB		 5736 case 30:
5737 temp |= PIPE_10BPC;
8febb297 5738 break;
5a354204
JB		 5739 case 36:
5740 temp |= PIPE_12BPC;
8febb297
EA		 5741 break;
5742 default:
62ac41a6
JB		 5743 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5744 pipe_bpp);
5a354204
JB		 5745 temp |= PIPE_8BPC;
5746 pipe_bpp = 24;
5747 break;
8febb297 5748 }
77ffb597 5749
5a354204
JB		 5750 intel_crtc->bpp = pipe_bpp;
5751 I915_WRITE(PIPECONF(pipe), temp);
5752
8febb297
EA		 5753 if (!lane) {
5754 /*
5755 * Account for spread spectrum to avoid
5756 * oversubscribing the link. Max center spread
5757 * is 2.5%; use 5% for safety's sake.
5758 */
5a354204 5759 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 5760 lane = bps / (link_bw * 8) + 1;
5eb08b69 5761 }
2c07245f 5762
8febb297
EA		 5763 intel_crtc->fdi_lanes = lane;
5764
5765 if (pixel_multiplier > 1)
5766 link_bw *= pixel_multiplier;
5a354204
JB		 5767 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5768 &m_n);
8febb297 5769
a07d6787
EA		 5770 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5771 if (has_reduced_clock)
5772 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5773 reduced_clock.m2;
79e53945 5774
c1858123 5775 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5776 factor = 21;
5777 if (is_lvds) {
5778 if ((intel_panel_use_ssc(dev_priv) &&
5779 dev_priv->lvds_ssc_freq == 100) ||
5780 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5781 factor = 25;
5782 } else if (is_sdvo && is_tv)
5783 factor = 20;
c1858123 5784
cb0e0931 5785 if (clock.m < factor * clock.n)
8febb297 5786 fp |= FP_CB_TUNE;
2c07245f 5787
5eddb70b 5788 dpll = 0;
2c07245f 5789
a07d6787
EA		 5790 if (is_lvds)
5791 dpll |= DPLLB_MODE_LVDS;
5792 else
5793 dpll |= DPLLB_MODE_DAC_SERIAL;
5794 if (is_sdvo) {
5795 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5796 if (pixel_multiplier > 1) {
5797 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5798 }
a07d6787
EA		 5799 dpll |= DPLL_DVO_HIGH_SPEED;
5800 }
5801 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5802 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5803
a07d6787
EA		 5804 /* compute bitmask from p1 value */
5805 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5806 /* also FPA1 */
5807 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5808
5809 switch (clock.p2) {
5810 case 5:
5811 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5812 break;
5813 case 7:
5814 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5815 break;
5816 case 10:
5817 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5818 break;
5819 case 14:
5820 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5821 break;
79e53945
JB		 5822 }
5823
43565a06
KH		 5824 if (is_sdvo && is_tv)
5825 dpll |= PLL_REF_INPUT_TVCLKINBC;
5826 else if (is_tv)
79e53945 5827 /* XXX: just matching BIOS for now */
43565a06 5828 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5829 dpll |= 3;
a7615030 5830 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5831 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5832 else
5833 dpll |= PLL_REF_INPUT_DREFCLK;
5834
5835 /* setup pipeconf */
5eddb70b 5836 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5837
5838 /* Set up the display plane register */
5839 dspcntr = DISPPLANE_GAMMA_ENABLE;
5840
f7cb34d4 5841 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5842 drm_mode_debug_printmodeline(mode);
5843
5c5313c8 5844 /* PCH eDP needs FDI, but CPU eDP does not */
4b645f14
JB		 5845 if (!intel_crtc->no_pll) {
5846 if (!has_edp_encoder ||
5847 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5848 I915_WRITE(PCH_FP0(pipe), fp);
5849 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5850
5851 POSTING_READ(PCH_DPLL(pipe));
5852 udelay(150);
5853 }
5854 } else {
5855 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5856 fp == I915_READ(PCH_FP0(0))) {
5857 intel_crtc->use_pll_a = true;
5858 DRM_DEBUG_KMS("using pipe a dpll\n");
5859 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5860 fp == I915_READ(PCH_FP0(1))) {
5861 intel_crtc->use_pll_a = false;
5862 DRM_DEBUG_KMS("using pipe b dpll\n");
5863 } else {
5864 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5865 return -EINVAL;
5866 }
79e53945
JB		 5867 }
5868
5869 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5870 * This is an exception to the general rule that mode_set doesn't turn
5871 * things on.
5872 */
5873 if (is_lvds) {
fae14981 5874 temp = I915_READ(PCH_LVDS);
5eddb70b 5875 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4b645f14
JB		 5876 if (HAS_PCH_CPT(dev))
5877 temp |= PORT_TRANS_SEL_CPT(pipe);
5878 else if (pipe == 1)
5879 temp |= LVDS_PIPEB_SELECT;
5880 else
5881 temp &= ~LVDS_PIPEB_SELECT;
5882
a3e17eb8 5883 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5884 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5885 /* Set the B0-B3 data pairs corresponding to whether we're going to
5886 * set the DPLLs for dual-channel mode or not.
5887 */
5888 if (clock.p2 == 7)
5eddb70b 5889 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5890 else
5eddb70b 5891 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5892
5893 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5894 * appropriately here, but we need to look more thoroughly into how
5895 * panels behave in the two modes.
5896 */
aa9b500d
BF		 5897 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5898 lvds_sync |= LVDS_HSYNC_POLARITY;
5899 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5900 lvds_sync |= LVDS_VSYNC_POLARITY;
5901 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5902 != lvds_sync) {
5903 char flags[2] = "-+";
5904 DRM_INFO("Changing LVDS panel from "
5905 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5906 flags[!(temp & LVDS_HSYNC_POLARITY)],
5907 flags[!(temp & LVDS_VSYNC_POLARITY)],
5908 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5909 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5910 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5911 temp |= lvds_sync;
5912 }
fae14981 5913 I915_WRITE(PCH_LVDS, temp);
79e53945 5914 }
434ed097 5915
8febb297
EA		 5916 pipeconf &= ~PIPECONF_DITHER_EN;
5917 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 5918 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 5919 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 5920 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 5921 }
5c5313c8 5922 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
a4fc5ed6 5923 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5924 } else {
8db9d77b 5925 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5926 I915_WRITE(TRANSDATA_M1(pipe), 0);
5927 I915_WRITE(TRANSDATA_N1(pipe), 0);
5928 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5929 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5930 }
79e53945 5931
4b645f14
JB		 5932 if (!intel_crtc->no_pll &&
5933 (!has_edp_encoder ||
5934 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
fae14981 5935 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 5936
32f9d658 5937 /* Wait for the clocks to stabilize. */
fae14981 5938 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 5939 udelay(150);
5940
8febb297
EA		 5941 /* The pixel multiplier can only be updated once the
5942 * DPLL is enabled and the clocks are stable.
5943 *
5944 * So write it again.
5945 */
fae14981 5946 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 5947 }
79e53945 5948
5eddb70b 5949 intel_crtc->lowfreq_avail = false;
4b645f14
JB		 5950 if (!intel_crtc->no_pll) {
5951 if (is_lvds && has_reduced_clock && i915_powersave) {
5952 I915_WRITE(PCH_FP1(pipe), fp2);
5953 intel_crtc->lowfreq_avail = true;
5954 if (HAS_PIPE_CXSR(dev)) {
5955 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5956 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5957 }
5958 } else {
5959 I915_WRITE(PCH_FP1(pipe), fp);
5960 if (HAS_PIPE_CXSR(dev)) {
5961 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5962 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5963 }
652c393a
JB		 5964 }
5965 }
5966
734b4157
KH		 5967 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5968 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5969 /* the chip adds 2 halflines automatically */
5970 adjusted_mode->crtc_vdisplay -= 1;
5971 adjusted_mode->crtc_vtotal -= 1;
5972 adjusted_mode->crtc_vblank_start -= 1;
5973 adjusted_mode->crtc_vblank_end -= 1;
5974 adjusted_mode->crtc_vsync_end -= 1;
5975 adjusted_mode->crtc_vsync_start -= 1;
5976 } else
5977 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5978
5eddb70b
CW		 5979 I915_WRITE(HTOTAL(pipe),
5980 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5981 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5982 I915_WRITE(HBLANK(pipe),
5983 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5984 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5985 I915_WRITE(HSYNC(pipe),
5986 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5987 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5988
5989 I915_WRITE(VTOTAL(pipe),
5990 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5991 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5992 I915_WRITE(VBLANK(pipe),
5993 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5994 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5995 I915_WRITE(VSYNC(pipe),
5996 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5997 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 5998
8febb297
EA		 5999 /* pipesrc controls the size that is scaled from, which should
6000 * always be the user's requested size.
79e53945 6001 */
5eddb70b
CW		 6002 I915_WRITE(PIPESRC(pipe),
6003 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 6004
8febb297
EA		 6005 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
6006 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
6007 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
6008 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 6009
8febb297
EA		 6010 if (has_edp_encoder &&
6011 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6012 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f
ZW		 6013 }
6014
5eddb70b
CW		 6015 I915_WRITE(PIPECONF(pipe), pipeconf);
6016 POSTING_READ(PIPECONF(pipe));
79e53945 6017
9d0498a2 6018 intel_wait_for_vblank(dev, pipe);
79e53945 6019
f00a3ddf 6020 if (IS_GEN5(dev)) {
553bd149
ZW		 6021 /* enable address swizzle for tiling buffer */
6022 temp = I915_READ(DISP_ARB_CTL);
6023 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
6024 }
6025
5eddb70b 6026 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 6027 POSTING_READ(DSPCNTR(plane));
79e53945 6028
5c3b82e2 6029 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 6030
6031 intel_update_watermarks(dev);
6032
1f803ee5 6033 return ret;
79e53945
JB		 6034}
6035
f564048e
EA		 6036static int intel_crtc_mode_set(struct drm_crtc *crtc,
6037 struct drm_display_mode *mode,
6038 struct drm_display_mode *adjusted_mode,
6039 int x, int y,
6040 struct drm_framebuffer *old_fb)
6041{
6042 struct drm_device *dev = crtc->dev;
6043 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 6044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6045 int pipe = intel_crtc->pipe;
f564048e
EA		 6046 int ret;
6047
0b701d27 6048 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6049
f564048e
EA		 6050 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6051 x, y, old_fb);
79e53945 6052 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6053
d8e70a25
JB		 6054 if (ret)
6055 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6056 else
6057 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
120eced9 6058
1f803ee5 6059 return ret;
79e53945
JB		 6060}
6061
3a9627f4
WF		 6062static bool intel_eld_uptodate(struct drm_connector *connector,
6063 int reg_eldv, uint32_t bits_eldv,
6064 int reg_elda, uint32_t bits_elda,
6065 int reg_edid)
6066{
6067 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6068 uint8_t *eld = connector->eld;
6069 uint32_t i;
6070
6071 i = I915_READ(reg_eldv);
6072 i &= bits_eldv;
6073
6074 if (!eld[0])
6075 return !i;
6076
6077 if (!i)
6078 return false;
6079
6080 i = I915_READ(reg_elda);
6081 i &= ~bits_elda;
6082 I915_WRITE(reg_elda, i);
6083
6084 for (i = 0; i < eld[2]; i++)
6085 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6086 return false;
6087
6088 return true;
6089}
6090
e0dac65e
WF		 6091static void g4x_write_eld(struct drm_connector *connector,
6092 struct drm_crtc *crtc)
6093{
6094 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6095 uint8_t *eld = connector->eld;
6096 uint32_t eldv;
6097 uint32_t len;
6098 uint32_t i;
6099
6100 i = I915_READ(G4X_AUD_VID_DID);
6101
6102 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6103 eldv = G4X_ELDV_DEVCL_DEVBLC;
6104 else
6105 eldv = G4X_ELDV_DEVCTG;
6106
3a9627f4
WF		 6107 if (intel_eld_uptodate(connector,
6108 G4X_AUD_CNTL_ST, eldv,
6109 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6110 G4X_HDMIW_HDMIEDID))
6111 return;
6112
e0dac65e
WF		 6113 i = I915_READ(G4X_AUD_CNTL_ST);
6114 i &= ~(eldv | G4X_ELD_ADDR);
6115 len = (i >> 9) & 0x1f; /* ELD buffer size */
6116 I915_WRITE(G4X_AUD_CNTL_ST, i);
6117
6118 if (!eld[0])
6119 return;
6120
6121 len = min_t(uint8_t, eld[2], len);
6122 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6123 for (i = 0; i < len; i++)
6124 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6125
6126 i = I915_READ(G4X_AUD_CNTL_ST);
6127 i |= eldv;
6128 I915_WRITE(G4X_AUD_CNTL_ST, i);
6129}
6130
6131static void ironlake_write_eld(struct drm_connector *connector,
6132 struct drm_crtc *crtc)
6133{
6134 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6135 uint8_t *eld = connector->eld;
6136 uint32_t eldv;
6137 uint32_t i;
6138 int len;
6139 int hdmiw_hdmiedid;
6140 int aud_cntl_st;
6141 int aud_cntrl_st2;
6142
b3f33cbf 6143 if (HAS_PCH_IBX(connector->dev)) {
1202b4c6
WF		 6144 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
6145 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6146 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6147 } else {
1202b4c6
WF		 6148 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
6149 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6150 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6151 }
6152
6153 i = to_intel_crtc(crtc)->pipe;
6154 hdmiw_hdmiedid += i * 0x100;
6155 aud_cntl_st += i * 0x100;
6156
6157 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6158
6159 i = I915_READ(aud_cntl_st);
6160 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
6161 if (!i) {
6162 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6163 /* operate blindly on all ports */
1202b4c6
WF		 6164 eldv = IBX_ELD_VALIDB;
6165 eldv |= IBX_ELD_VALIDB << 4;
6166 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6167 } else {
6168 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6169 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6170 }
6171
3a9627f4
WF		 6172 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6173 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6174 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
e0dac65e
WF		 6175 }
6176
3a9627f4
WF		 6177 if (intel_eld_uptodate(connector,
6178 aud_cntrl_st2, eldv,
6179 aud_cntl_st, IBX_ELD_ADDRESS,
6180 hdmiw_hdmiedid))
6181 return;
6182
e0dac65e
WF		 6183 i = I915_READ(aud_cntrl_st2);
6184 i &= ~eldv;
6185 I915_WRITE(aud_cntrl_st2, i);
6186
6187 if (!eld[0])
6188 return;
6189
e0dac65e 6190 i = I915_READ(aud_cntl_st);
1202b4c6 6191 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6192 I915_WRITE(aud_cntl_st, i);
6193
6194 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6195 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6196 for (i = 0; i < len; i++)
6197 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6198
6199 i = I915_READ(aud_cntrl_st2);
6200 i |= eldv;
6201 I915_WRITE(aud_cntrl_st2, i);
6202}
6203
6204void intel_write_eld(struct drm_encoder *encoder,
6205 struct drm_display_mode *mode)
6206{
6207 struct drm_crtc *crtc = encoder->crtc;
6208 struct drm_connector *connector;
6209 struct drm_device *dev = encoder->dev;
6210 struct drm_i915_private *dev_priv = dev->dev_private;
6211
6212 connector = drm_select_eld(encoder, mode);
6213 if (!connector)
6214 return;
6215
6216 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6217 connector->base.id,
6218 drm_get_connector_name(connector),
6219 connector->encoder->base.id,
6220 drm_get_encoder_name(connector->encoder));
6221
6222 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6223
6224 if (dev_priv->display.write_eld)
6225 dev_priv->display.write_eld(connector, crtc);
6226}
6227
79e53945
JB		 6228/** Loads the palette/gamma unit for the CRTC with the prepared values */
6229void intel_crtc_load_lut(struct drm_crtc *crtc)
6230{
6231 struct drm_device *dev = crtc->dev;
6232 struct drm_i915_private *dev_priv = dev->dev_private;
6233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6234 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6235 int i;
6236
6237 /* The clocks have to be on to load the palette. */
6238 if (!crtc->enabled)
6239 return;
6240
f2b115e6 6241 /* use legacy palette for Ironlake */
bad720ff 6242 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6243 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6244
79e53945
JB		 6245 for (i = 0; i < 256; i++) {
6246 I915_WRITE(palreg + 4 * i,
6247 (intel_crtc->lut_r[i] << 16) |
6248 (intel_crtc->lut_g[i] << 8) |
6249 intel_crtc->lut_b[i]);
6250 }
6251}
6252
560b85bb
CW		 6253static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6254{
6255 struct drm_device *dev = crtc->dev;
6256 struct drm_i915_private *dev_priv = dev->dev_private;
6257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6258 bool visible = base != 0;
6259 u32 cntl;
6260
6261 if (intel_crtc->cursor_visible == visible)
6262 return;
6263
9db4a9c7 6264 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6265 if (visible) {
6266 /* On these chipsets we can only modify the base whilst
6267 * the cursor is disabled.
6268 */
9db4a9c7 6269 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6270
6271 cntl &= ~(CURSOR_FORMAT_MASK);
6272 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6273 cntl |= CURSOR_ENABLE |
6274 CURSOR_GAMMA_ENABLE |
6275 CURSOR_FORMAT_ARGB;
6276 } else
6277 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6278 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6279
6280 intel_crtc->cursor_visible = visible;
6281}
6282
6283static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6284{
6285 struct drm_device *dev = crtc->dev;
6286 struct drm_i915_private *dev_priv = dev->dev_private;
6287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6288 int pipe = intel_crtc->pipe;
6289 bool visible = base != 0;
6290
6291 if (intel_crtc->cursor_visible != visible) {
548f245b 6292 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6293 if (base) {
6294 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6295 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6296 cntl |= pipe << 28; /* Connect to correct pipe */
6297 } else {
6298 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6299 cntl |= CURSOR_MODE_DISABLE;
6300 }
9db4a9c7 6301 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6302
6303 intel_crtc->cursor_visible = visible;
6304 }
6305 /* and commit changes on next vblank */
9db4a9c7 6306 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6307}
6308
65a21cd6
JB		 6309static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6310{
6311 struct drm_device *dev = crtc->dev;
6312 struct drm_i915_private *dev_priv = dev->dev_private;
6313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6314 int pipe = intel_crtc->pipe;
6315 bool visible = base != 0;
6316
6317 if (intel_crtc->cursor_visible != visible) {
6318 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6319 if (base) {
6320 cntl &= ~CURSOR_MODE;
6321 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6322 } else {
6323 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6324 cntl |= CURSOR_MODE_DISABLE;
6325 }
6326 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6327
6328 intel_crtc->cursor_visible = visible;
6329 }
6330 /* and commit changes on next vblank */
6331 I915_WRITE(CURBASE_IVB(pipe), base);
6332}
6333
cda4b7d3 6334/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6335static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6336 bool on)
cda4b7d3
CW		 6337{
6338 struct drm_device *dev = crtc->dev;
6339 struct drm_i915_private *dev_priv = dev->dev_private;
6340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6341 int pipe = intel_crtc->pipe;
6342 int x = intel_crtc->cursor_x;
6343 int y = intel_crtc->cursor_y;
560b85bb 6344 u32 base, pos;
cda4b7d3
CW		 6345 bool visible;
6346
6347 pos = 0;
6348
6b383a7f 6349 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6350 base = intel_crtc->cursor_addr;
6351 if (x > (int) crtc->fb->width)
6352 base = 0;
6353
6354 if (y > (int) crtc->fb->height)
6355 base = 0;
6356 } else
6357 base = 0;
6358
6359 if (x < 0) {
6360 if (x + intel_crtc->cursor_width < 0)
6361 base = 0;
6362
6363 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6364 x = -x;
6365 }
6366 pos |= x << CURSOR_X_SHIFT;
6367
6368 if (y < 0) {
6369 if (y + intel_crtc->cursor_height < 0)
6370 base = 0;
6371
6372 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6373 y = -y;
6374 }
6375 pos |= y << CURSOR_Y_SHIFT;
6376
6377 visible = base != 0;
560b85bb 6378 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6379 return;
6380
65a21cd6
JB		 6381 if (IS_IVYBRIDGE(dev)) {
6382 I915_WRITE(CURPOS_IVB(pipe), pos);
6383 ivb_update_cursor(crtc, base);
6384 } else {
6385 I915_WRITE(CURPOS(pipe), pos);
6386 if (IS_845G(dev) || IS_I865G(dev))
6387 i845_update_cursor(crtc, base);
6388 else
6389 i9xx_update_cursor(crtc, base);
6390 }
cda4b7d3
CW		 6391
6392 if (visible)
6393 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6394}
6395
79e53945 6396static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6397 struct drm_file *file,
79e53945
JB		 6398 uint32_t handle,
6399 uint32_t width, uint32_t height)
6400{
6401 struct drm_device *dev = crtc->dev;
6402 struct drm_i915_private *dev_priv = dev->dev_private;
6403 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6404 struct drm_i915_gem_object *obj;
cda4b7d3 6405 uint32_t addr;
3f8bc370 6406 int ret;
79e53945 6407
28c97730 6408 DRM_DEBUG_KMS("\n");
79e53945
JB		 6409
6410 /* if we want to turn off the cursor ignore width and height */
6411 if (!handle) {
28c97730 6412 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6413 addr = 0;
05394f39 6414 obj = NULL;
5004417d 6415 mutex_lock(&dev->struct_mutex);
3f8bc370 6416 goto finish;
79e53945
JB		 6417 }
6418
6419 /* Currently we only support 64x64 cursors */
6420 if (width != 64 || height != 64) {
6421 DRM_ERROR("we currently only support 64x64 cursors\n");
6422 return -EINVAL;
6423 }
6424
05394f39 6425 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6426 if (&obj->base == NULL)
79e53945
JB		 6427 return -ENOENT;
6428
05394f39 6429 if (obj->base.size < width * height * 4) {
79e53945 6430 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6431 ret = -ENOMEM;
6432 goto fail;
79e53945
JB		 6433 }
6434
71acb5eb 6435 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6436 mutex_lock(&dev->struct_mutex);
b295d1b6 6437 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6438 if (obj->tiling_mode) {
6439 DRM_ERROR("cursor cannot be tiled\n");
6440 ret = -EINVAL;
6441 goto fail_locked;
6442 }
6443
2da3b9b9 6444 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6445 if (ret) {
6446 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6447 goto fail_locked;
e7b526bb
CW		 6448 }
6449
d9e86c0e
CW		 6450 ret = i915_gem_object_put_fence(obj);
6451 if (ret) {
2da3b9b9 6452 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6453 goto fail_unpin;
6454 }
6455
05394f39 6456 addr = obj->gtt_offset;
71acb5eb 6457 } else {
6eeefaf3 6458 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6459 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6460 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6461 align);
71acb5eb
DA		 6462 if (ret) {
6463 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6464 goto fail_locked;
71acb5eb 6465 }
05394f39 6466 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6467 }
6468
a6c45cf0 6469 if (IS_GEN2(dev))
14b60391
JB		 6470 I915_WRITE(CURSIZE, (height << 12) | width);
6471
3f8bc370 6472 finish:
3f8bc370 6473 if (intel_crtc->cursor_bo) {
b295d1b6 6474 if (dev_priv->info->cursor_needs_physical) {
05394f39 6475 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6476 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6477 } else
6478 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6479 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6480 }
80824003 6481
7f9872e0 6482 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6483
6484 intel_crtc->cursor_addr = addr;
05394f39 6485 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6486 intel_crtc->cursor_width = width;
6487 intel_crtc->cursor_height = height;
6488
6b383a7f 6489 intel_crtc_update_cursor(crtc, true);
3f8bc370 6490
79e53945 6491 return 0;
e7b526bb 6492fail_unpin:
05394f39 6493 i915_gem_object_unpin(obj);
7f9872e0 6494fail_locked:
34b8686e 6495 mutex_unlock(&dev->struct_mutex);
bc9025bd 6496fail:
05394f39 6497 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6498 return ret;
79e53945
JB		 6499}
6500
6501static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6502{
79e53945 6503 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6504
cda4b7d3
CW		 6505 intel_crtc->cursor_x = x;
6506 intel_crtc->cursor_y = y;
652c393a 6507
6b383a7f 6508 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6509
6510 return 0;
6511}
6512
6513/** Sets the color ramps on behalf of RandR */
6514void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6515 u16 blue, int regno)
6516{
6517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6518
6519 intel_crtc->lut_r[regno] = red >> 8;
6520 intel_crtc->lut_g[regno] = green >> 8;
6521 intel_crtc->lut_b[regno] = blue >> 8;
6522}
6523
b8c00ac5
DA		 6524void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6525 u16 *blue, int regno)
6526{
6527 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6528
6529 *red = intel_crtc->lut_r[regno] << 8;
6530 *green = intel_crtc->lut_g[regno] << 8;
6531 *blue = intel_crtc->lut_b[regno] << 8;
6532}
6533
79e53945 6534static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6535 u16 *blue, uint32_t start, uint32_t size)
79e53945 6536{
7203425a 6537 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6539
7203425a 6540 for (i = start; i < end; i++) {
79e53945
JB		 6541 intel_crtc->lut_r[i] = red[i] >> 8;
6542 intel_crtc->lut_g[i] = green[i] >> 8;
6543 intel_crtc->lut_b[i] = blue[i] >> 8;
6544 }
6545
6546 intel_crtc_load_lut(crtc);
6547}
6548
6549/**
6550 * Get a pipe with a simple mode set on it for doing load-based monitor
6551 * detection.
6552 *
6553 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6554 * its requirements. The pipe will be connected to no other encoders.
79e53945 6555 *
c751ce4f 6556 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6557 * configured for it. In the future, it could choose to temporarily disable
6558 * some outputs to free up a pipe for its use.
6559 *
6560 * \return crtc, or NULL if no pipes are available.
6561 */
6562
6563/* VESA 640x480x72Hz mode to set on the pipe */
6564static struct drm_display_mode load_detect_mode = {
6565 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6566 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6567};
6568
d2dff872
CW		 6569static struct drm_framebuffer *
6570intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6571 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6572 struct drm_i915_gem_object *obj)
6573{
6574 struct intel_framebuffer *intel_fb;
6575 int ret;
6576
6577 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6578 if (!intel_fb) {
6579 drm_gem_object_unreference_unlocked(&obj->base);
6580 return ERR_PTR(-ENOMEM);
6581 }
6582
6583 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6584 if (ret) {
6585 drm_gem_object_unreference_unlocked(&obj->base);
6586 kfree(intel_fb);
6587 return ERR_PTR(ret);
6588 }
6589
6590 return &intel_fb->base;
6591}
6592
6593static u32
6594intel_framebuffer_pitch_for_width(int width, int bpp)
6595{
6596 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6597 return ALIGN(pitch, 64);
6598}
6599
6600static u32
6601intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6602{
6603 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6604 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6605}
6606
6607static struct drm_framebuffer *
6608intel_framebuffer_create_for_mode(struct drm_device *dev,
6609 struct drm_display_mode *mode,
6610 int depth, int bpp)
6611{
6612 struct drm_i915_gem_object *obj;
308e5bcb 6613 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 6614
6615 obj = i915_gem_alloc_object(dev,
6616 intel_framebuffer_size_for_mode(mode, bpp));
6617 if (obj == NULL)
6618 return ERR_PTR(-ENOMEM);
6619
6620 mode_cmd.width = mode->hdisplay;
6621 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6622 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6623 bpp);
6624 mode_cmd.pixel_format = 0;
d2dff872
CW		 6625
6626 return intel_framebuffer_create(dev, &mode_cmd, obj);
6627}
6628
6629static struct drm_framebuffer *
6630mode_fits_in_fbdev(struct drm_device *dev,
6631 struct drm_display_mode *mode)
6632{
6633 struct drm_i915_private *dev_priv = dev->dev_private;
6634 struct drm_i915_gem_object *obj;
6635 struct drm_framebuffer *fb;
6636
6637 if (dev_priv->fbdev == NULL)
6638 return NULL;
6639
6640 obj = dev_priv->fbdev->ifb.obj;
6641 if (obj == NULL)
6642 return NULL;
6643
6644 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6645 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6646 fb->bits_per_pixel))
d2dff872
CW		 6647 return NULL;
6648
01f2c773 6649 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6650 return NULL;
6651
6652 return fb;
6653}
6654
7173188d
CW		 6655bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6656 struct drm_connector *connector,
6657 struct drm_display_mode *mode,
8261b191 6658 struct intel_load_detect_pipe *old)
79e53945
JB		 6659{
6660 struct intel_crtc *intel_crtc;
6661 struct drm_crtc *possible_crtc;
4ef69c7a 6662 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6663 struct drm_crtc *crtc = NULL;
6664 struct drm_device *dev = encoder->dev;
d2dff872 6665 struct drm_framebuffer *old_fb;
79e53945
JB		 6666 int i = -1;
6667
d2dff872
CW		 6668 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6669 connector->base.id, drm_get_connector_name(connector),
6670 encoder->base.id, drm_get_encoder_name(encoder));
6671
79e53945
JB		 6672 /*
6673 * Algorithm gets a little messy:
7a5e4805 6674 *
79e53945
JB		 6675 * - if the connector already has an assigned crtc, use it (but make
6676 * sure it's on first)
7a5e4805 6677 *
79e53945
JB		 6678 * - try to find the first unused crtc that can drive this connector,
6679 * and use that if we find one
79e53945
JB		 6680 */
6681
6682 /* See if we already have a CRTC for this connector */
6683 if (encoder->crtc) {
6684 crtc = encoder->crtc;
8261b191 6685
79e53945 6686 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6687 old->dpms_mode = intel_crtc->dpms_mode;
6688 old->load_detect_temp = false;
6689
6690 /* Make sure the crtc and connector are running */
79e53945 6691 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 6692 struct drm_encoder_helper_funcs *encoder_funcs;
6693 struct drm_crtc_helper_funcs *crtc_funcs;
6694
79e53945
JB		 6695 crtc_funcs = crtc->helper_private;
6696 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 6697
6698 encoder_funcs = encoder->helper_private;
79e53945
JB		 6699 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6700 }
8261b191 6701
7173188d 6702 return true;
79e53945
JB		 6703 }
6704
6705 /* Find an unused one (if possible) */
6706 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6707 i++;
6708 if (!(encoder->possible_crtcs & (1 << i)))
6709 continue;
6710 if (!possible_crtc->enabled) {
6711 crtc = possible_crtc;
6712 break;
6713 }
79e53945
JB		 6714 }
6715
6716 /*
6717 * If we didn't find an unused CRTC, don't use any.
6718 */
6719 if (!crtc) {
7173188d
CW		 6720 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6721 return false;
79e53945
JB		 6722 }
6723
6724 encoder->crtc = crtc;
c1c43977 6725 connector->encoder = encoder;
79e53945
JB		 6726
6727 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6728 old->dpms_mode = intel_crtc->dpms_mode;
6729 old->load_detect_temp = true;
d2dff872 6730 old->release_fb = NULL;
79e53945 6731
6492711d
CW		 6732 if (!mode)
6733 mode = &load_detect_mode;
79e53945 6734
d2dff872
CW		 6735 old_fb = crtc->fb;
6736
6737 /* We need a framebuffer large enough to accommodate all accesses
6738 * that the plane may generate whilst we perform load detection.
6739 * We can not rely on the fbcon either being present (we get called
6740 * during its initialisation to detect all boot displays, or it may
6741 * not even exist) or that it is large enough to satisfy the
6742 * requested mode.
6743 */
6744 crtc->fb = mode_fits_in_fbdev(dev, mode);
6745 if (crtc->fb == NULL) {
6746 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6747 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6748 old->release_fb = crtc->fb;
6749 } else
6750 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6751 if (IS_ERR(crtc->fb)) {
6752 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6753 crtc->fb = old_fb;
6754 return false;
79e53945 6755 }
79e53945 6756
d2dff872 6757 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 6758 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6759 if (old->release_fb)
6760 old->release_fb->funcs->destroy(old->release_fb);
6761 crtc->fb = old_fb;
6492711d 6762 return false;
79e53945 6763 }
7173188d 6764
79e53945 6765 /* let the connector get through one full cycle before testing */
9d0498a2 6766 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6767
7173188d 6768 return true;
79e53945
JB		 6769}
6770
c1c43977 6771void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 6772 struct drm_connector *connector,
6773 struct intel_load_detect_pipe *old)
79e53945 6774{
4ef69c7a 6775 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6776 struct drm_device *dev = encoder->dev;
6777 struct drm_crtc *crtc = encoder->crtc;
6778 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6779 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6780
d2dff872
CW		 6781 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6782 connector->base.id, drm_get_connector_name(connector),
6783 encoder->base.id, drm_get_encoder_name(encoder));
6784
8261b191 6785 if (old->load_detect_temp) {
c1c43977 6786 connector->encoder = NULL;
79e53945 6787 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 6788
6789 if (old->release_fb)
6790 old->release_fb->funcs->destroy(old->release_fb);
6791
0622a53c 6792 return;
79e53945
JB		 6793 }
6794
c751ce4f 6795 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 6796 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6797 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 6798 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 6799 }
6800}
6801
6802/* Returns the clock of the currently programmed mode of the given pipe. */
6803static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6804{
6805 struct drm_i915_private *dev_priv = dev->dev_private;
6806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6807 int pipe = intel_crtc->pipe;
548f245b 6808 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6809 u32 fp;
6810 intel_clock_t clock;
6811
6812 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6813 fp = I915_READ(FP0(pipe));
79e53945 6814 else
39adb7a5 6815 fp = I915_READ(FP1(pipe));
79e53945
JB		 6816
6817 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6818 if (IS_PINEVIEW(dev)) {
6819 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6820 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6821 } else {
6822 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6823 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6824 }
6825
a6c45cf0 6826 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6827 if (IS_PINEVIEW(dev))
6828 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6829 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6830 else
6831 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6832 DPLL_FPA01_P1_POST_DIV_SHIFT);
6833
6834 switch (dpll & DPLL_MODE_MASK) {
6835 case DPLLB_MODE_DAC_SERIAL:
6836 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6837 5 : 10;
6838 break;
6839 case DPLLB_MODE_LVDS:
6840 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6841 7 : 14;
6842 break;
6843 default:
28c97730 6844 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6845 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6846 return 0;
6847 }
6848
6849 /* XXX: Handle the 100Mhz refclk */
2177832f 6850 intel_clock(dev, 96000, &clock);
79e53945
JB		 6851 } else {
6852 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6853
6854 if (is_lvds) {
6855 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6856 DPLL_FPA01_P1_POST_DIV_SHIFT);
6857 clock.p2 = 14;
6858
6859 if ((dpll & PLL_REF_INPUT_MASK) ==
6860 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6861 /* XXX: might not be 66MHz */
2177832f 6862 intel_clock(dev, 66000, &clock);
79e53945 6863 } else
2177832f 6864 intel_clock(dev, 48000, &clock);
79e53945
JB		 6865 } else {
6866 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6867 clock.p1 = 2;
6868 else {
6869 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6870 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6871 }
6872 if (dpll & PLL_P2_DIVIDE_BY_4)
6873 clock.p2 = 4;
6874 else
6875 clock.p2 = 2;
6876
2177832f 6877 intel_clock(dev, 48000, &clock);
79e53945
JB		 6878 }
6879 }
6880
6881 /* XXX: It would be nice to validate the clocks, but we can't reuse
6882 * i830PllIsValid() because it relies on the xf86_config connector
6883 * configuration being accurate, which it isn't necessarily.
6884 */
6885
6886 return clock.dot;
6887}
6888
6889/** Returns the currently programmed mode of the given pipe. */
6890struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6891 struct drm_crtc *crtc)
6892{
548f245b 6893 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 6894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6895 int pipe = intel_crtc->pipe;
6896 struct drm_display_mode *mode;
548f245b
JB		 6897 int htot = I915_READ(HTOTAL(pipe));
6898 int hsync = I915_READ(HSYNC(pipe));
6899 int vtot = I915_READ(VTOTAL(pipe));
6900 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 6901
6902 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6903 if (!mode)
6904 return NULL;
6905
6906 mode->clock = intel_crtc_clock_get(dev, crtc);
6907 mode->hdisplay = (htot & 0xffff) + 1;
6908 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6909 mode->hsync_start = (hsync & 0xffff) + 1;
6910 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6911 mode->vdisplay = (vtot & 0xffff) + 1;
6912 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6913 mode->vsync_start = (vsync & 0xffff) + 1;
6914 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6915
6916 drm_mode_set_name(mode);
6917 drm_mode_set_crtcinfo(mode, 0);
6918
6919 return mode;
6920}
6921
652c393a
JB		 6922#define GPU_IDLE_TIMEOUT 500 /* ms */
6923
6924/* When this timer fires, we've been idle for awhile */
6925static void intel_gpu_idle_timer(unsigned long arg)
6926{
6927 struct drm_device *dev = (struct drm_device *)arg;
6928 drm_i915_private_t *dev_priv = dev->dev_private;
6929
ff7ea4c0
CW		 6930 if (!list_empty(&dev_priv->mm.active_list)) {
6931 /* Still processing requests, so just re-arm the timer. */
6932 mod_timer(&dev_priv->idle_timer, jiffies +
6933 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6934 return;
6935 }
652c393a 6936
ff7ea4c0 6937 dev_priv->busy = false;
01dfba93 6938 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6939}
6940
652c393a
JB		 6941#define CRTC_IDLE_TIMEOUT 1000 /* ms */
6942
6943static void intel_crtc_idle_timer(unsigned long arg)
6944{
6945 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6946 struct drm_crtc *crtc = &intel_crtc->base;
6947 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 6948 struct intel_framebuffer *intel_fb;
652c393a 6949
ff7ea4c0
CW		 6950 intel_fb = to_intel_framebuffer(crtc->fb);
6951 if (intel_fb && intel_fb->obj->active) {
6952 /* The framebuffer is still being accessed by the GPU. */
6953 mod_timer(&intel_crtc->idle_timer, jiffies +
6954 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6955 return;
6956 }
652c393a 6957
ff7ea4c0 6958 intel_crtc->busy = false;
01dfba93 6959 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6960}
6961
3dec0095 6962static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6963{
6964 struct drm_device *dev = crtc->dev;
6965 drm_i915_private_t *dev_priv = dev->dev_private;
6966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6967 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6968 int dpll_reg = DPLL(pipe);
6969 int dpll;
652c393a 6970
bad720ff 6971 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6972 return;
6973
6974 if (!dev_priv->lvds_downclock_avail)
6975 return;
6976
dbdc6479 6977 dpll = I915_READ(dpll_reg);
652c393a 6978 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6979 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a
JB		 6980
6981 /* Unlock panel regs */
dbdc6479
JB		 6982 I915_WRITE(PP_CONTROL,
6983 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
652c393a
JB		 6984
6985 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6986 I915_WRITE(dpll_reg, dpll);
9d0498a2 6987 intel_wait_for_vblank(dev, pipe);
dbdc6479 6988
652c393a
JB		 6989 dpll = I915_READ(dpll_reg);
6990 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6991 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 6992
6993 /* ...and lock them again */
6994 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6995 }
6996
6997 /* Schedule downclock */
3dec0095
DV		 6998 mod_timer(&intel_crtc->idle_timer, jiffies +
6999 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 7000}
7001
7002static void intel_decrease_pllclock(struct drm_crtc *crtc)
7003{
7004 struct drm_device *dev = crtc->dev;
7005 drm_i915_private_t *dev_priv = dev->dev_private;
7006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7007 int pipe = intel_crtc->pipe;
9db4a9c7 7008 int dpll_reg = DPLL(pipe);
652c393a
JB		 7009 int dpll = I915_READ(dpll_reg);
7010
bad720ff 7011 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7012 return;
7013
7014 if (!dev_priv->lvds_downclock_avail)
7015 return;
7016
7017 /*
7018 * Since this is called by a timer, we should never get here in
7019 * the manual case.
7020 */
7021 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 7022 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a
JB		 7023
7024 /* Unlock panel regs */
4a655f04
JB		 7025 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
7026 PANEL_UNLOCK_REGS);
652c393a
JB		 7027
7028 dpll |= DISPLAY_RATE_SELECT_FPA1;
7029 I915_WRITE(dpll_reg, dpll);
9d0498a2 7030 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7031 dpll = I915_READ(dpll_reg);
7032 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7033 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7034
7035 /* ...and lock them again */
7036 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
7037 }
7038
7039}
7040
7041/**
7042 * intel_idle_update - adjust clocks for idleness
7043 * @work: work struct
7044 *
7045 * Either the GPU or display (or both) went idle. Check the busy status
7046 * here and adjust the CRTC and GPU clocks as necessary.
7047 */
7048static void intel_idle_update(struct work_struct *work)
7049{
7050 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
7051 idle_work);
7052 struct drm_device *dev = dev_priv->dev;
7053 struct drm_crtc *crtc;
7054 struct intel_crtc *intel_crtc;
7055
7056 if (!i915_powersave)
7057 return;
7058
7059 mutex_lock(&dev->struct_mutex);
7060
7648fa99
JB		 7061 i915_update_gfx_val(dev_priv);
7062
652c393a
JB		 7063 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7064 /* Skip inactive CRTCs */
7065 if (!crtc->fb)
7066 continue;
7067
7068 intel_crtc = to_intel_crtc(crtc);
7069 if (!intel_crtc->busy)
7070 intel_decrease_pllclock(crtc);
7071 }
7072
45ac22c8 7073
652c393a
JB		 7074 mutex_unlock(&dev->struct_mutex);
7075}
7076
7077/**
7078 * intel_mark_busy - mark the GPU and possibly the display busy
7079 * @dev: drm device
7080 * @obj: object we're operating on
7081 *
7082 * Callers can use this function to indicate that the GPU is busy processing
7083 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
7084 * buffer), we'll also mark the display as busy, so we know to increase its
7085 * clock frequency.
7086 */
05394f39 7087void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 7088{
7089 drm_i915_private_t *dev_priv = dev->dev_private;
7090 struct drm_crtc *crtc = NULL;
7091 struct intel_framebuffer *intel_fb;
7092 struct intel_crtc *intel_crtc;
7093
5e17ee74
ZW		 7094 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7095 return;
7096
18b2190c 7097 if (!dev_priv->busy)
28cf798f 7098 dev_priv->busy = true;
18b2190c 7099 else
28cf798f
CW		 7100 mod_timer(&dev_priv->idle_timer, jiffies +
7101 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 7102
7103 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7104 if (!crtc->fb)
7105 continue;
7106
7107 intel_crtc = to_intel_crtc(crtc);
7108 intel_fb = to_intel_framebuffer(crtc->fb);
7109 if (intel_fb->obj == obj) {
7110 if (!intel_crtc->busy) {
7111 /* Non-busy -> busy, upclock */
3dec0095 7112 intel_increase_pllclock(crtc);
652c393a
JB		 7113 intel_crtc->busy = true;
7114 } else {
7115 /* Busy -> busy, put off timer */
7116 mod_timer(&intel_crtc->idle_timer, jiffies +
7117 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7118 }
7119 }
7120 }
7121}
7122
79e53945
JB		 7123static void intel_crtc_destroy(struct drm_crtc *crtc)
7124{
7125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7126 struct drm_device *dev = crtc->dev;
7127 struct intel_unpin_work *work;
7128 unsigned long flags;
7129
7130 spin_lock_irqsave(&dev->event_lock, flags);
7131 work = intel_crtc->unpin_work;
7132 intel_crtc->unpin_work = NULL;
7133 spin_unlock_irqrestore(&dev->event_lock, flags);
7134
7135 if (work) {
7136 cancel_work_sync(&work->work);
7137 kfree(work);
7138 }
79e53945
JB		 7139
7140 drm_crtc_cleanup(crtc);
67e77c5a 7141
79e53945
JB		 7142 kfree(intel_crtc);
7143}
7144
6b95a207
KH		 7145static void intel_unpin_work_fn(struct work_struct *__work)
7146{
7147 struct intel_unpin_work *work =
7148 container_of(__work, struct intel_unpin_work, work);
7149
7150 mutex_lock(&work->dev->struct_mutex);
b1b87f6b 7151 i915_gem_object_unpin(work->old_fb_obj);
05394f39
CW		 7152 drm_gem_object_unreference(&work->pending_flip_obj->base);
7153 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7154
7782de3b 7155 intel_update_fbc(work->dev);
6b95a207
KH		 7156 mutex_unlock(&work->dev->struct_mutex);
7157 kfree(work);
7158}
7159
1afe3e9d 7160static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7161 struct drm_crtc *crtc)
6b95a207
KH		 7162{
7163 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7165 struct intel_unpin_work *work;
05394f39 7166 struct drm_i915_gem_object *obj;
6b95a207 7167 struct drm_pending_vblank_event *e;
49b14a5c 7168 struct timeval tnow, tvbl;
6b95a207
KH		 7169 unsigned long flags;
7170
7171 /* Ignore early vblank irqs */
7172 if (intel_crtc == NULL)
7173 return;
7174
49b14a5c
MK		 7175 do_gettimeofday(&tnow);
7176
6b95a207
KH		 7177 spin_lock_irqsave(&dev->event_lock, flags);
7178 work = intel_crtc->unpin_work;
7179 if (work == NULL || !work->pending) {
7180 spin_unlock_irqrestore(&dev->event_lock, flags);
7181 return;
7182 }
7183
7184 intel_crtc->unpin_work = NULL;
6b95a207
KH		 7185
7186 if (work->event) {
7187 e = work->event;
49b14a5c 7188 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 7189
7190 /* Called before vblank count and timestamps have
7191 * been updated for the vblank interval of flip
7192 * completion? Need to increment vblank count and
7193 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 7194 * to account for this. We assume this happened if we
7195 * get called over 0.9 frame durations after the last
7196 * timestamped vblank.
7197 *
7198 * This calculation can not be used with vrefresh rates
7199 * below 5Hz (10Hz to be on the safe side) without
7200 * promoting to 64 integers.
0af7e4df 7201 */
49b14a5c
MK		 7202 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7203 9 * crtc->framedur_ns) {
0af7e4df 7204 e->event.sequence++;
49b14a5c
MK		 7205 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7206 crtc->framedur_ns);
0af7e4df
MK		 7207 }
7208
49b14a5c
MK		 7209 e->event.tv_sec = tvbl.tv_sec;
7210 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 7211
6b95a207
KH		 7212 list_add_tail(&e->base.link,
7213 &e->base.file_priv->event_list);
7214 wake_up_interruptible(&e->base.file_priv->event_wait);
7215 }
7216
0af7e4df
MK		 7217 drm_vblank_put(dev, intel_crtc->pipe);
7218
6b95a207
KH		 7219 spin_unlock_irqrestore(&dev->event_lock, flags);
7220
05394f39 7221 obj = work->old_fb_obj;
d9e86c0e 7222
e59f2bac 7223 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 7224 &obj->pending_flip.counter);
7225 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 7226 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 7227
6b95a207 7228 schedule_work(&work->work);
e5510fac
JB		 7229
7230 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7231}
7232
1afe3e9d
JB		 7233void intel_finish_page_flip(struct drm_device *dev, int pipe)
7234{
7235 drm_i915_private_t *dev_priv = dev->dev_private;
7236 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7237
49b14a5c 7238 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7239}
7240
7241void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7242{
7243 drm_i915_private_t *dev_priv = dev->dev_private;
7244 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7245
49b14a5c 7246 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7247}
7248
6b95a207
KH		 7249void intel_prepare_page_flip(struct drm_device *dev, int plane)
7250{
7251 drm_i915_private_t *dev_priv = dev->dev_private;
7252 struct intel_crtc *intel_crtc =
7253 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7254 unsigned long flags;
7255
7256 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 7257 if (intel_crtc->unpin_work) {
4e5359cd
SF		 7258 if ((++intel_crtc->unpin_work->pending) > 1)
7259 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 7260 } else {
7261 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7262 }
6b95a207
KH		 7263 spin_unlock_irqrestore(&dev->event_lock, flags);
7264}
7265
8c9f3aaf
JB		 7266static int intel_gen2_queue_flip(struct drm_device *dev,
7267 struct drm_crtc *crtc,
7268 struct drm_framebuffer *fb,
7269 struct drm_i915_gem_object *obj)
7270{
7271 struct drm_i915_private *dev_priv = dev->dev_private;
7272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7273 unsigned long offset;
7274 u32 flip_mask;
7275 int ret;
7276
7277 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7278 if (ret)
7279 goto out;
7280
7281 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 7282 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf
JB		 7283
7284 ret = BEGIN_LP_RING(6);
7285 if (ret)
7286 goto out;
7287
7288 /* Can't queue multiple flips, so wait for the previous
7289 * one to finish before executing the next.
7290 */
7291 if (intel_crtc->plane)
7292 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7293 else
7294 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7295 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7296 OUT_RING(MI_NOOP);
7297 OUT_RING(MI_DISPLAY_FLIP |
7298 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7299 OUT_RING(fb->pitches[0]);
8c9f3aaf 7300 OUT_RING(obj->gtt_offset + offset);
c6a32fcb 7301 OUT_RING(0); /* aux display base address, unused */
8c9f3aaf
JB		 7302 ADVANCE_LP_RING();
7303out:
7304 return ret;
7305}
7306
7307static int intel_gen3_queue_flip(struct drm_device *dev,
7308 struct drm_crtc *crtc,
7309 struct drm_framebuffer *fb,
7310 struct drm_i915_gem_object *obj)
7311{
7312 struct drm_i915_private *dev_priv = dev->dev_private;
7313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7314 unsigned long offset;
7315 u32 flip_mask;
7316 int ret;
7317
7318 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7319 if (ret)
7320 goto out;
7321
7322 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 7323 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf
JB		 7324
7325 ret = BEGIN_LP_RING(6);
7326 if (ret)
7327 goto out;
7328
7329 if (intel_crtc->plane)
7330 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7331 else
7332 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7333 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7334 OUT_RING(MI_NOOP);
7335 OUT_RING(MI_DISPLAY_FLIP_I915 |
7336 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7337 OUT_RING(fb->pitches[0]);
8c9f3aaf
JB		 7338 OUT_RING(obj->gtt_offset + offset);
7339 OUT_RING(MI_NOOP);
7340
7341 ADVANCE_LP_RING();
7342out:
7343 return ret;
7344}
7345
7346static int intel_gen4_queue_flip(struct drm_device *dev,
7347 struct drm_crtc *crtc,
7348 struct drm_framebuffer *fb,
7349 struct drm_i915_gem_object *obj)
7350{
7351 struct drm_i915_private *dev_priv = dev->dev_private;
7352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7353 uint32_t pf, pipesrc;
7354 int ret;
7355
7356 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7357 if (ret)
7358 goto out;
7359
7360 ret = BEGIN_LP_RING(4);
7361 if (ret)
7362 goto out;
7363
7364 /* i965+ uses the linear or tiled offsets from the
7365 * Display Registers (which do not change across a page-flip)
7366 * so we need only reprogram the base address.
7367 */
7368 OUT_RING(MI_DISPLAY_FLIP |
7369 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7370 OUT_RING(fb->pitches[0]);
8c9f3aaf
JB		 7371 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7372
7373 /* XXX Enabling the panel-fitter across page-flip is so far
7374 * untested on non-native modes, so ignore it for now.
7375 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7376 */
7377 pf = 0;
7378 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7379 OUT_RING(pf | pipesrc);
7380 ADVANCE_LP_RING();
7381out:
7382 return ret;
7383}
7384
7385static int intel_gen6_queue_flip(struct drm_device *dev,
7386 struct drm_crtc *crtc,
7387 struct drm_framebuffer *fb,
7388 struct drm_i915_gem_object *obj)
7389{
7390 struct drm_i915_private *dev_priv = dev->dev_private;
7391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7392 uint32_t pf, pipesrc;
7393 int ret;
7394
7395 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7396 if (ret)
7397 goto out;
7398
7399 ret = BEGIN_LP_RING(4);
7400 if (ret)
7401 goto out;
7402
7403 OUT_RING(MI_DISPLAY_FLIP |
7404 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7405 OUT_RING(fb->pitches[0] | obj->tiling_mode);
8c9f3aaf
JB		 7406 OUT_RING(obj->gtt_offset);
7407
7408 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7409 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7410 OUT_RING(pf | pipesrc);
7411 ADVANCE_LP_RING();
7412out:
7413 return ret;
7414}
7415
7c9017e5
JB		 7416/*
7417 * On gen7 we currently use the blit ring because (in early silicon at least)
7418 * the render ring doesn't give us interrpts for page flip completion, which
7419 * means clients will hang after the first flip is queued. Fortunately the
7420 * blit ring generates interrupts properly, so use it instead.
7421 */
7422static int intel_gen7_queue_flip(struct drm_device *dev,
7423 struct drm_crtc *crtc,
7424 struct drm_framebuffer *fb,
7425 struct drm_i915_gem_object *obj)
7426{
7427 struct drm_i915_private *dev_priv = dev->dev_private;
7428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7429 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7430 int ret;
7431
7432 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7433 if (ret)
7434 goto out;
7435
7436 ret = intel_ring_begin(ring, 4);
7437 if (ret)
7438 goto out;
7439
7440 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
01f2c773 7441 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7c9017e5
JB		 7442 intel_ring_emit(ring, (obj->gtt_offset));
7443 intel_ring_emit(ring, (MI_NOOP));
7444 intel_ring_advance(ring);
7445out:
7446 return ret;
7447}
7448
8c9f3aaf
JB		 7449static int intel_default_queue_flip(struct drm_device *dev,
7450 struct drm_crtc *crtc,
7451 struct drm_framebuffer *fb,
7452 struct drm_i915_gem_object *obj)
7453{
7454 return -ENODEV;
7455}
7456
6b95a207
KH		 7457static int intel_crtc_page_flip(struct drm_crtc *crtc,
7458 struct drm_framebuffer *fb,
7459 struct drm_pending_vblank_event *event)
7460{
7461 struct drm_device *dev = crtc->dev;
7462 struct drm_i915_private *dev_priv = dev->dev_private;
7463 struct intel_framebuffer *intel_fb;
05394f39 7464 struct drm_i915_gem_object *obj;
6b95a207
KH		 7465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7466 struct intel_unpin_work *work;
8c9f3aaf 7467 unsigned long flags;
52e68630 7468 int ret;
6b95a207
KH		 7469
7470 work = kzalloc(sizeof *work, GFP_KERNEL);
7471 if (work == NULL)
7472 return -ENOMEM;
7473
6b95a207
KH		 7474 work->event = event;
7475 work->dev = crtc->dev;
7476 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7477 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7478 INIT_WORK(&work->work, intel_unpin_work_fn);
7479
7317c75e
JB		 7480 ret = drm_vblank_get(dev, intel_crtc->pipe);
7481 if (ret)
7482 goto free_work;
7483
6b95a207
KH		 7484 /* We borrow the event spin lock for protecting unpin_work */
7485 spin_lock_irqsave(&dev->event_lock, flags);
7486 if (intel_crtc->unpin_work) {
7487 spin_unlock_irqrestore(&dev->event_lock, flags);
7488 kfree(work);
7317c75e 7489 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7490
7491 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7492 return -EBUSY;
7493 }
7494 intel_crtc->unpin_work = work;
7495 spin_unlock_irqrestore(&dev->event_lock, flags);
7496
7497 intel_fb = to_intel_framebuffer(fb);
7498 obj = intel_fb->obj;
7499
468f0b44 7500 mutex_lock(&dev->struct_mutex);
6b95a207 7501
75dfca80 7502 /* Reference the objects for the scheduled work. */
05394f39
CW		 7503 drm_gem_object_reference(&work->old_fb_obj->base);
7504 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7505
7506 crtc->fb = fb;
96b099fd 7507
e1f99ce6 7508 work->pending_flip_obj = obj;
e1f99ce6 7509
4e5359cd
SF		 7510 work->enable_stall_check = true;
7511
e1f99ce6
CW		 7512 /* Block clients from rendering to the new back buffer until
7513 * the flip occurs and the object is no longer visible.
7514 */
05394f39 7515 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 7516
8c9f3aaf
JB		 7517 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7518 if (ret)
7519 goto cleanup_pending;
6b95a207 7520
7782de3b 7521 intel_disable_fbc(dev);
6b95a207
KH		 7522 mutex_unlock(&dev->struct_mutex);
7523
e5510fac
JB		 7524 trace_i915_flip_request(intel_crtc->plane, obj);
7525
6b95a207 7526 return 0;
96b099fd 7527
8c9f3aaf
JB		 7528cleanup_pending:
7529 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 7530 drm_gem_object_unreference(&work->old_fb_obj->base);
7531 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7532 mutex_unlock(&dev->struct_mutex);
7533
7534 spin_lock_irqsave(&dev->event_lock, flags);
7535 intel_crtc->unpin_work = NULL;
7536 spin_unlock_irqrestore(&dev->event_lock, flags);
7537
7317c75e
JB		 7538 drm_vblank_put(dev, intel_crtc->pipe);
7539free_work:
96b099fd
CW		 7540 kfree(work);
7541
7542 return ret;
6b95a207
KH		 7543}
7544
47f1c6c9
CW		 7545static void intel_sanitize_modesetting(struct drm_device *dev,
7546 int pipe, int plane)
7547{
7548 struct drm_i915_private *dev_priv = dev->dev_private;
7549 u32 reg, val;
7550
7551 if (HAS_PCH_SPLIT(dev))
7552 return;
7553
7554 /* Who knows what state these registers were left in by the BIOS or
7555 * grub?
7556 *
7557 * If we leave the registers in a conflicting state (e.g. with the
7558 * display plane reading from the other pipe than the one we intend
7559 * to use) then when we attempt to teardown the active mode, we will
7560 * not disable the pipes and planes in the correct order -- leaving
7561 * a plane reading from a disabled pipe and possibly leading to
7562 * undefined behaviour.
7563 */
7564
7565 reg = DSPCNTR(plane);
7566 val = I915_READ(reg);
7567
7568 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7569 return;
7570 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7571 return;
7572
7573 /* This display plane is active and attached to the other CPU pipe. */
7574 pipe = !pipe;
7575
7576 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 7577 intel_disable_plane(dev_priv, plane, pipe);
7578 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 7579}
79e53945 7580
f6e5b160
CW		 7581static void intel_crtc_reset(struct drm_crtc *crtc)
7582{
7583 struct drm_device *dev = crtc->dev;
7584 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7585
7586 /* Reset flags back to the 'unknown' status so that they
7587 * will be correctly set on the initial modeset.
7588 */
7589 intel_crtc->dpms_mode = -1;
7590
7591 /* We need to fix up any BIOS configuration that conflicts with
7592 * our expectations.
7593 */
7594 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7595}
7596
7597static struct drm_crtc_helper_funcs intel_helper_funcs = {
7598 .dpms = intel_crtc_dpms,
7599 .mode_fixup = intel_crtc_mode_fixup,
7600 .mode_set = intel_crtc_mode_set,
7601 .mode_set_base = intel_pipe_set_base,
7602 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7603 .load_lut = intel_crtc_load_lut,
7604 .disable = intel_crtc_disable,
7605};
7606
7607static const struct drm_crtc_funcs intel_crtc_funcs = {
7608 .reset = intel_crtc_reset,
7609 .cursor_set = intel_crtc_cursor_set,
7610 .cursor_move = intel_crtc_cursor_move,
7611 .gamma_set = intel_crtc_gamma_set,
7612 .set_config = drm_crtc_helper_set_config,
7613 .destroy = intel_crtc_destroy,
7614 .page_flip = intel_crtc_page_flip,
7615};
7616
b358d0a6 7617static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 7618{
22fd0fab 7619 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 7620 struct intel_crtc *intel_crtc;
7621 int i;
7622
7623 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7624 if (intel_crtc == NULL)
7625 return;
7626
7627 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7628
7629 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7630 for (i = 0; i < 256; i++) {
7631 intel_crtc->lut_r[i] = i;
7632 intel_crtc->lut_g[i] = i;
7633 intel_crtc->lut_b[i] = i;
7634 }
7635
80824003
JB		 7636 /* Swap pipes & planes for FBC on pre-965 */
7637 intel_crtc->pipe = pipe;
7638 intel_crtc->plane = pipe;
e2e767ab 7639 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7640 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7641 intel_crtc->plane = !pipe;
80824003
JB		 7642 }
7643
22fd0fab
JB		 7644 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7645 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7646 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7647 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7648
5d1d0cc8 7649 intel_crtc_reset(&intel_crtc->base);
04dbff52 7650 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 7651 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 7652
7653 if (HAS_PCH_SPLIT(dev)) {
4b645f14
JB		 7654 if (pipe == 2 && IS_IVYBRIDGE(dev))
7655 intel_crtc->no_pll = true;
7e7d76c3
JB		 7656 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7657 intel_helper_funcs.commit = ironlake_crtc_commit;
7658 } else {
7659 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7660 intel_helper_funcs.commit = i9xx_crtc_commit;
7661 }
7662
79e53945
JB		 7663 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7664
652c393a
JB		 7665 intel_crtc->busy = false;
7666
7667 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7668 (unsigned long)intel_crtc);
79e53945
JB		 7669}
7670
08d7b3d1 7671int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7672 struct drm_file *file)
08d7b3d1
CW		 7673{
7674 drm_i915_private_t *dev_priv = dev->dev_private;
7675 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 7676 struct drm_mode_object *drmmode_obj;
7677 struct intel_crtc *crtc;
08d7b3d1
CW		 7678
7679 if (!dev_priv) {
7680 DRM_ERROR("called with no initialization\n");
7681 return -EINVAL;
7682 }
7683
c05422d5
DV		 7684 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7685 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7686
c05422d5 7687 if (!drmmode_obj) {
08d7b3d1
CW		 7688 DRM_ERROR("no such CRTC id\n");
7689 return -EINVAL;
7690 }
7691
c05422d5
DV		 7692 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7693 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7694
c05422d5 7695 return 0;
08d7b3d1
CW		 7696}
7697
c5e4df33 7698static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 7699{
4ef69c7a 7700 struct intel_encoder *encoder;
79e53945 7701 int index_mask = 0;
79e53945
JB		 7702 int entry = 0;
7703
4ef69c7a
CW		 7704 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7705 if (type_mask & encoder->clone_mask)
79e53945
JB		 7706 index_mask |= (1 << entry);
7707 entry++;
7708 }
4ef69c7a 7709
79e53945
JB		 7710 return index_mask;
7711}
7712
4d302442
CW		 7713static bool has_edp_a(struct drm_device *dev)
7714{
7715 struct drm_i915_private *dev_priv = dev->dev_private;
7716
7717 if (!IS_MOBILE(dev))
7718 return false;
7719
7720 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7721 return false;
7722
7723 if (IS_GEN5(dev) &&
7724 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7725 return false;
7726
7727 return true;
7728}
7729
79e53945
JB		 7730static void intel_setup_outputs(struct drm_device *dev)
7731{
725e30ad 7732 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 7733 struct intel_encoder *encoder;
cb0953d7 7734 bool dpd_is_edp = false;
c5d1b51d 7735 bool has_lvds = false;
79e53945 7736
541998a1 7737 if (IS_MOBILE(dev) && !IS_I830(dev))
c5d1b51d
CW		 7738 has_lvds = intel_lvds_init(dev);
7739 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7740 /* disable the panel fitter on everything but LVDS */
7741 I915_WRITE(PFIT_CONTROL, 0);
7742 }
79e53945 7743
bad720ff 7744 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 7745 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 7746
4d302442 7747 if (has_edp_a(dev))
32f9d658
ZW		 7748 intel_dp_init(dev, DP_A);
7749
cb0953d7
AJ		 7750 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7751 intel_dp_init(dev, PCH_DP_D);
7752 }
7753
7754 intel_crt_init(dev);
7755
7756 if (HAS_PCH_SPLIT(dev)) {
7757 int found;
7758
30ad48b7 7759 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca
ZY		 7760 /* PCH SDVOB multiplex with HDMIB */
7761 found = intel_sdvo_init(dev, PCH_SDVOB);
30ad48b7
ZW		 7762 if (!found)
7763 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 7764 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7765 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 7766 }
7767
7768 if (I915_READ(HDMIC) & PORT_DETECTED)
7769 intel_hdmi_init(dev, HDMIC);
7770
7771 if (I915_READ(HDMID) & PORT_DETECTED)
7772 intel_hdmi_init(dev, HDMID);
7773
5eb08b69
ZW		 7774 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7775 intel_dp_init(dev, PCH_DP_C);
7776
cb0953d7 7777 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 7778 intel_dp_init(dev, PCH_DP_D);
7779
103a196f 7780 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 7781 bool found = false;
7d57382e 7782
725e30ad 7783 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 7784 DRM_DEBUG_KMS("probing SDVOB\n");
725e30ad 7785 found = intel_sdvo_init(dev, SDVOB);
b01f2c3a
JB		 7786 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7787 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 7788 intel_hdmi_init(dev, SDVOB);
b01f2c3a 7789 }
27185ae1 7790
b01f2c3a
JB		 7791 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7792 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 7793 intel_dp_init(dev, DP_B);
b01f2c3a 7794 }
725e30ad 7795 }
13520b05
KH		 7796
7797 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 7798
b01f2c3a
JB		 7799 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7800 DRM_DEBUG_KMS("probing SDVOC\n");
725e30ad 7801 found = intel_sdvo_init(dev, SDVOC);
b01f2c3a 7802 }
27185ae1
ML		 7803
7804 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7805
b01f2c3a
JB		 7806 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7807 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 7808 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 7809 }
7810 if (SUPPORTS_INTEGRATED_DP(dev)) {
7811 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 7812 intel_dp_init(dev, DP_C);
b01f2c3a 7813 }
725e30ad 7814 }
27185ae1 7815
b01f2c3a
JB		 7816 if (SUPPORTS_INTEGRATED_DP(dev) &&
7817 (I915_READ(DP_D) & DP_DETECTED)) {
7818 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 7819 intel_dp_init(dev, DP_D);
b01f2c3a 7820 }
bad720ff 7821 } else if (IS_GEN2(dev))
79e53945
JB		 7822 intel_dvo_init(dev);
7823
103a196f 7824 if (SUPPORTS_TV(dev))
79e53945
JB		 7825 intel_tv_init(dev);
7826
4ef69c7a
CW		 7827 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7828 encoder->base.possible_crtcs = encoder->crtc_mask;
7829 encoder->base.possible_clones =
7830 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 7831 }
47356eb6 7832
2c7111db
CW		 7833 /* disable all the possible outputs/crtcs before entering KMS mode */
7834 drm_helper_disable_unused_functions(dev);
9fb526db
KP		 7835
7836 if (HAS_PCH_SPLIT(dev))
7837 ironlake_init_pch_refclk(dev);
79e53945
JB		 7838}
7839
7840static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7841{
7842 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 7843
7844 drm_framebuffer_cleanup(fb);
05394f39 7845 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 7846
7847 kfree(intel_fb);
7848}
7849
7850static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 7851 struct drm_file *file,
79e53945
JB		 7852 unsigned int *handle)
7853{
7854 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 7855 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 7856
05394f39 7857 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 7858}
7859
7860static const struct drm_framebuffer_funcs intel_fb_funcs = {
7861 .destroy = intel_user_framebuffer_destroy,
7862 .create_handle = intel_user_framebuffer_create_handle,
7863};
7864
38651674
DA		 7865int intel_framebuffer_init(struct drm_device *dev,
7866 struct intel_framebuffer *intel_fb,
308e5bcb 7867 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 7868 struct drm_i915_gem_object *obj)
79e53945 7869{
79e53945
JB		 7870 int ret;
7871
05394f39 7872 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 7873 return -EINVAL;
7874
308e5bcb 7875 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 7876 return -EINVAL;
7877
308e5bcb 7878 switch (mode_cmd->pixel_format) {
04b3924d
VS		 7879 case DRM_FORMAT_RGB332:
7880 case DRM_FORMAT_RGB565:
7881 case DRM_FORMAT_XRGB8888:
7882 case DRM_FORMAT_ARGB8888:
7883 case DRM_FORMAT_XRGB2101010:
7884 case DRM_FORMAT_ARGB2101010:
308e5bcb 7885 /* RGB formats are common across chipsets */
b5626747 7886 break;
04b3924d
VS		 7887 case DRM_FORMAT_YUYV:
7888 case DRM_FORMAT_UYVY:
7889 case DRM_FORMAT_YVYU:
7890 case DRM_FORMAT_VYUY:
57cd6508
CW		 7891 break;
7892 default:
308e5bcb 7893 DRM_ERROR("unsupported pixel format\n");
57cd6508
CW		 7894 return -EINVAL;
7895 }
7896
79e53945
JB		 7897 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7898 if (ret) {
7899 DRM_ERROR("framebuffer init failed %d\n", ret);
7900 return ret;
7901 }
7902
7903 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 7904 intel_fb->obj = obj;
79e53945
JB		 7905 return 0;
7906}
7907
79e53945
JB		 7908static struct drm_framebuffer *
7909intel_user_framebuffer_create(struct drm_device *dev,
7910 struct drm_file *filp,
308e5bcb 7911 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 7912{
05394f39 7913 struct drm_i915_gem_object *obj;
79e53945 7914
308e5bcb
JB		 7915 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7916 mode_cmd->handles[0]));
c8725226 7917 if (&obj->base == NULL)
cce13ff7 7918 return ERR_PTR(-ENOENT);
79e53945 7919
d2dff872 7920 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 7921}
7922
79e53945 7923static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 7924 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 7925 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 7926};
7927
05394f39 7928static struct drm_i915_gem_object *
aa40d6bb 7929intel_alloc_context_page(struct drm_device *dev)
9ea8d059 7930{
05394f39 7931 struct drm_i915_gem_object *ctx;
9ea8d059
CW		 7932 int ret;
7933
2c34b850
BW		 7934 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7935
aa40d6bb
ZN		 7936 ctx = i915_gem_alloc_object(dev, 4096);
7937 if (!ctx) {
9ea8d059
CW		 7938 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7939 return NULL;
7940 }
7941
75e9e915 7942 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW		 7943 if (ret) {
7944 DRM_ERROR("failed to pin power context: %d\n", ret);
7945 goto err_unref;
7946 }
7947
aa40d6bb 7948 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW		 7949 if (ret) {
7950 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7951 goto err_unpin;
7952 }
9ea8d059 7953
aa40d6bb 7954 return ctx;
9ea8d059
CW		 7955
7956err_unpin:
aa40d6bb 7957 i915_gem_object_unpin(ctx);
9ea8d059 7958err_unref:
05394f39 7959 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW		 7960 mutex_unlock(&dev->struct_mutex);
7961 return NULL;
7962}
7963
7648fa99
JB		 7964bool ironlake_set_drps(struct drm_device *dev, u8 val)
7965{
7966 struct drm_i915_private *dev_priv = dev->dev_private;
7967 u16 rgvswctl;
7968
7969 rgvswctl = I915_READ16(MEMSWCTL);
7970 if (rgvswctl & MEMCTL_CMD_STS) {
7971 DRM_DEBUG("gpu busy, RCS change rejected\n");
7972 return false; /* still busy with another command */
7973 }
7974
7975 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7976 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7977 I915_WRITE16(MEMSWCTL, rgvswctl);
7978 POSTING_READ16(MEMSWCTL);
7979
7980 rgvswctl |= MEMCTL_CMD_STS;
7981 I915_WRITE16(MEMSWCTL, rgvswctl);
7982
7983 return true;
7984}
7985
f97108d1
JB		 7986void ironlake_enable_drps(struct drm_device *dev)
7987{
7988 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7989 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 7990 u8 fmax, fmin, fstart, vstart;
f97108d1 7991
ea056c14
JB		 7992 /* Enable temp reporting */
7993 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7994 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7995
f97108d1
JB		 7996 /* 100ms RC evaluation intervals */
7997 I915_WRITE(RCUPEI, 100000);
7998 I915_WRITE(RCDNEI, 100000);
7999
8000 /* Set max/min thresholds to 90ms and 80ms respectively */
8001 I915_WRITE(RCBMAXAVG, 90000);
8002 I915_WRITE(RCBMINAVG, 80000);
8003
8004 I915_WRITE(MEMIHYST, 1);
8005
8006 /* Set up min, max, and cur for interrupt handling */
8007 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
8008 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
8009 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
8010 MEMMODE_FSTART_SHIFT;
7648fa99 8011
f97108d1
JB		 8012 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
8013 PXVFREQ_PX_SHIFT;
8014
80dbf4b7 8015 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB		 8016 dev_priv->fstart = fstart;
8017
80dbf4b7 8018 dev_priv->max_delay = fstart;
f97108d1
JB		 8019 dev_priv->min_delay = fmin;
8020 dev_priv->cur_delay = fstart;
8021
80dbf4b7
JB		 8022 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8023 fmax, fmin, fstart);
7648fa99 8024
f97108d1
JB		 8025 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8026
8027 /*
8028 * Interrupts will be enabled in ironlake_irq_postinstall
8029 */
8030
8031 I915_WRITE(VIDSTART, vstart);
8032 POSTING_READ(VIDSTART);
8033
8034 rgvmodectl |= MEMMODE_SWMODE_EN;
8035 I915_WRITE(MEMMODECTL, rgvmodectl);
8036
481b6af3 8037 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 8038 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB		 8039 msleep(1);
8040
7648fa99 8041 ironlake_set_drps(dev, fstart);
f97108d1 8042
7648fa99
JB		 8043 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8044 I915_READ(0x112e0);
8045 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8046 dev_priv->last_count2 = I915_READ(0x112f4);
8047 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB		 8048}
8049
8050void ironlake_disable_drps(struct drm_device *dev)
8051{
8052 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 8053 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB		 8054
8055 /* Ack interrupts, disable EFC interrupt */
8056 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8057 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8058 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8059 I915_WRITE(DEIIR, DE_PCU_EVENT);
8060 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8061
8062 /* Go back to the starting frequency */
7648fa99 8063 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB		 8064 msleep(1);
8065 rgvswctl |= MEMCTL_CMD_STS;
8066 I915_WRITE(MEMSWCTL, rgvswctl);
8067 msleep(1);
8068
8069}
8070
3b8d8d91
JB		 8071void gen6_set_rps(struct drm_device *dev, u8 val)
8072{
8073 struct drm_i915_private *dev_priv = dev->dev_private;
8074 u32 swreq;
8075
8076 swreq = (val & 0x3ff) << 25;
8077 I915_WRITE(GEN6_RPNSWREQ, swreq);
8078}
8079
8080void gen6_disable_rps(struct drm_device *dev)
8081{
8082 struct drm_i915_private *dev_priv = dev->dev_private;
8083
8084 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8085 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8086 I915_WRITE(GEN6_PMIER, 0);
6fdd4d98
DV		 8087 /* Complete PM interrupt masking here doesn't race with the rps work
8088 * item again unmasking PM interrupts because that is using a different
8089 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8090 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
4912d041
BW		 8091
8092 spin_lock_irq(&dev_priv->rps_lock);
8093 dev_priv->pm_iir = 0;
8094 spin_unlock_irq(&dev_priv->rps_lock);
8095
3b8d8d91
JB		 8096 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8097}
8098
7648fa99
JB		 8099static unsigned long intel_pxfreq(u32 vidfreq)
8100{
8101 unsigned long freq;
8102 int div = (vidfreq & 0x3f0000) >> 16;
8103 int post = (vidfreq & 0x3000) >> 12;
8104 int pre = (vidfreq & 0x7);
8105
8106 if (!pre)
8107 return 0;
8108
8109 freq = ((div * 133333) / ((1<<post) * pre));
8110
8111 return freq;
8112}
8113
8114void intel_init_emon(struct drm_device *dev)
8115{
8116 struct drm_i915_private *dev_priv = dev->dev_private;
8117 u32 lcfuse;
8118 u8 pxw[16];
8119 int i;
8120
8121 /* Disable to program */
8122 I915_WRITE(ECR, 0);
8123 POSTING_READ(ECR);
8124
8125 /* Program energy weights for various events */
8126 I915_WRITE(SDEW, 0x15040d00);
8127 I915_WRITE(CSIEW0, 0x007f0000);
8128 I915_WRITE(CSIEW1, 0x1e220004);
8129 I915_WRITE(CSIEW2, 0x04000004);
8130
8131 for (i = 0; i < 5; i++)
8132 I915_WRITE(PEW + (i * 4), 0);
8133 for (i = 0; i < 3; i++)
8134 I915_WRITE(DEW + (i * 4), 0);
8135
8136 /* Program P-state weights to account for frequency power adjustment */
8137 for (i = 0; i < 16; i++) {
8138 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8139 unsigned long freq = intel_pxfreq(pxvidfreq);
8140 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8141 PXVFREQ_PX_SHIFT;
8142 unsigned long val;
8143
8144 val = vid * vid;
8145 val *= (freq / 1000);
8146 val *= 255;
8147 val /= (127*127*900);
8148 if (val > 0xff)
8149 DRM_ERROR("bad pxval: %ld\n", val);
8150 pxw[i] = val;
8151 }
8152 /* Render standby states get 0 weight */
8153 pxw[14] = 0;
8154 pxw[15] = 0;
8155
8156 for (i = 0; i < 4; i++) {
8157 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8158 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8159 I915_WRITE(PXW + (i * 4), val);
8160 }
8161
8162 /* Adjust magic regs to magic values (more experimental results) */
8163 I915_WRITE(OGW0, 0);
8164 I915_WRITE(OGW1, 0);
8165 I915_WRITE(EG0, 0x00007f00);
8166 I915_WRITE(EG1, 0x0000000e);
8167 I915_WRITE(EG2, 0x000e0000);
8168 I915_WRITE(EG3, 0x68000300);
8169 I915_WRITE(EG4, 0x42000000);
8170 I915_WRITE(EG5, 0x00140031);
8171 I915_WRITE(EG6, 0);
8172 I915_WRITE(EG7, 0);
8173
8174 for (i = 0; i < 8; i++)
8175 I915_WRITE(PXWL + (i * 4), 0);
8176
8177 /* Enable PMON + select events */
8178 I915_WRITE(ECR, 0x80000019);
8179
8180 lcfuse = I915_READ(LCFUSE02);
8181
8182 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8183}
8184
c0f372b3
KP		 8185static bool intel_enable_rc6(struct drm_device *dev)
8186{
8187 /*
8188 * Respect the kernel parameter if it is set
8189 */
8190 if (i915_enable_rc6 >= 0)
8191 return i915_enable_rc6;
8192
8193 /*
8194 * Disable RC6 on Ironlake
8195 */
8196 if (INTEL_INFO(dev)->gen == 5)
8197 return 0;
8198
8199 /*
8200 * Enable rc6 on Sandybridge if DMA remapping is disabled
8201 */
8202 if (INTEL_INFO(dev)->gen == 6) {
8203 DRM_DEBUG_DRIVER("Sandybridge: intel_iommu_enabled %s -- RC6 %sabled\n",
8204 intel_iommu_enabled ? "true" : "false",
8205 !intel_iommu_enabled ? "en" : "dis");
8206 return !intel_iommu_enabled;
8207 }
8208 DRM_DEBUG_DRIVER("RC6 enabled\n");
8209 return 1;
8210}
8211
3b8d8d91 8212void gen6_enable_rps(struct drm_i915_private *dev_priv)
8fd26859 8213{
a6044e23
JB		 8214 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8215 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7df8721b 8216 u32 pcu_mbox, rc6_mask = 0;
a6044e23 8217 int cur_freq, min_freq, max_freq;
8fd26859
CW		 8218 int i;
8219
8220 /* Here begins a magic sequence of register writes to enable
8221 * auto-downclocking.
8222 *
8223 * Perhaps there might be some value in exposing these to
8224 * userspace...
8225 */
8226 I915_WRITE(GEN6_RC_STATE, 0);
d1ebd816 8227 mutex_lock(&dev_priv->dev->struct_mutex);
fcca7926 8228 gen6_gt_force_wake_get(dev_priv);
8fd26859 8229
3b8d8d91 8230 /* disable the counters and set deterministic thresholds */
8fd26859
CW		 8231 I915_WRITE(GEN6_RC_CONTROL, 0);
8232
8233 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8234 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8235 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8236 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8237 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8238
8239 for (i = 0; i < I915_NUM_RINGS; i++)
8240 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8241
8242 I915_WRITE(GEN6_RC_SLEEP, 0);
8243 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8244 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8245 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8246 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8247
c0f372b3 8248 if (intel_enable_rc6(dev_priv->dev))
7df8721b
JB		 8249 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
8250 GEN6_RC_CTL_RC6_ENABLE;
8251
8fd26859 8252 I915_WRITE(GEN6_RC_CONTROL,
7df8721b 8253 rc6_mask |
9c3d2f7f 8254 GEN6_RC_CTL_EI_MODE(1) |
8fd26859
CW		 8255 GEN6_RC_CTL_HW_ENABLE);
8256
3b8d8d91 8257 I915_WRITE(GEN6_RPNSWREQ,
8fd26859
CW		 8258 GEN6_FREQUENCY(10) |
8259 GEN6_OFFSET(0) |
8260 GEN6_AGGRESSIVE_TURBO);
8261 I915_WRITE(GEN6_RC_VIDEO_FREQ,
8262 GEN6_FREQUENCY(12));
8263
8264 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8265 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8266 18 << 24 |
8267 6 << 16);
ccab5c82
JB		 8268 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8269 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8fd26859 8270 I915_WRITE(GEN6_RP_UP_EI, 100000);
ccab5c82 8271 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8fd26859
CW		 8272 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8273 I915_WRITE(GEN6_RP_CONTROL,
8274 GEN6_RP_MEDIA_TURBO |
6ed55ee7 8275 GEN6_RP_MEDIA_HW_MODE |
8fd26859
CW		 8276 GEN6_RP_MEDIA_IS_GFX |
8277 GEN6_RP_ENABLE |
ccab5c82
JB		 8278 GEN6_RP_UP_BUSY_AVG |
8279 GEN6_RP_DOWN_IDLE_CONT);
8fd26859
CW		 8280
8281 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8282 500))
8283 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8284
8285 I915_WRITE(GEN6_PCODE_DATA, 0);
8286 I915_WRITE(GEN6_PCODE_MAILBOX,
8287 GEN6_PCODE_READY |
8288 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8289 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8290 500))
8291 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8292
a6044e23
JB		 8293 min_freq = (rp_state_cap & 0xff0000) >> 16;
8294 max_freq = rp_state_cap & 0xff;
8295 cur_freq = (gt_perf_status & 0xff00) >> 8;
8296
8297 /* Check for overclock support */
8298 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8299 500))
8300 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8301 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8302 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8303 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8304 500))
8305 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8306 if (pcu_mbox & (1<<31)) { /* OC supported */
8307 max_freq = pcu_mbox & 0xff;
e281fcaa 8308 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
a6044e23
JB		 8309 }
8310
8311 /* In units of 100MHz */
8312 dev_priv->max_delay = max_freq;
8313 dev_priv->min_delay = min_freq;
8314 dev_priv->cur_delay = cur_freq;
8315
8fd26859
CW		 8316 /* requires MSI enabled */
8317 I915_WRITE(GEN6_PMIER,
8318 GEN6_PM_MBOX_EVENT |
8319 GEN6_PM_THERMAL_EVENT |
8320 GEN6_PM_RP_DOWN_TIMEOUT |
8321 GEN6_PM_RP_UP_THRESHOLD |
8322 GEN6_PM_RP_DOWN_THRESHOLD |
8323 GEN6_PM_RP_UP_EI_EXPIRED |
8324 GEN6_PM_RP_DOWN_EI_EXPIRED);
4912d041
BW		 8325 spin_lock_irq(&dev_priv->rps_lock);
8326 WARN_ON(dev_priv->pm_iir != 0);
3b8d8d91 8327 I915_WRITE(GEN6_PMIMR, 0);
4912d041 8328 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91
JB		 8329 /* enable all PM interrupts */
8330 I915_WRITE(GEN6_PMINTRMSK, 0);
8fd26859 8331
fcca7926 8332 gen6_gt_force_wake_put(dev_priv);
d1ebd816 8333 mutex_unlock(&dev_priv->dev->struct_mutex);
8fd26859
CW		 8334}
8335
23b2f8bb
JB		 8336void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8337{
8338 int min_freq = 15;
8339 int gpu_freq, ia_freq, max_ia_freq;
8340 int scaling_factor = 180;
8341
8342 max_ia_freq = cpufreq_quick_get_max(0);
8343 /*
8344 * Default to measured freq if none found, PCU will ensure we don't go
8345 * over
8346 */
8347 if (!max_ia_freq)
8348 max_ia_freq = tsc_khz;
8349
8350 /* Convert from kHz to MHz */
8351 max_ia_freq /= 1000;
8352
8353 mutex_lock(&dev_priv->dev->struct_mutex);
8354
8355 /*
8356 * For each potential GPU frequency, load a ring frequency we'd like
8357 * to use for memory access. We do this by specifying the IA frequency
8358 * the PCU should use as a reference to determine the ring frequency.
8359 */
8360 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8361 gpu_freq--) {
8362 int diff = dev_priv->max_delay - gpu_freq;
8363
8364 /*
8365 * For GPU frequencies less than 750MHz, just use the lowest
8366 * ring freq.
8367 */
8368 if (gpu_freq < min_freq)
8369 ia_freq = 800;
8370 else
8371 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8372 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8373
8374 I915_WRITE(GEN6_PCODE_DATA,
8375 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8376 gpu_freq);
8377 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8378 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8379 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8380 GEN6_PCODE_READY) == 0, 10)) {
8381 DRM_ERROR("pcode write of freq table timed out\n");
8382 continue;
8383 }
8384 }
8385
8386 mutex_unlock(&dev_priv->dev->struct_mutex);
8387}
8388
6067aaea
JB		 8389static void ironlake_init_clock_gating(struct drm_device *dev)
8390{
8391 struct drm_i915_private *dev_priv = dev->dev_private;
8392 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8393
8394 /* Required for FBC */
8395 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8396 DPFCRUNIT_CLOCK_GATE_DISABLE |
8397 DPFDUNIT_CLOCK_GATE_DISABLE;
8398 /* Required for CxSR */
8399 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8400
8401 I915_WRITE(PCH_3DCGDIS0,
8402 MARIUNIT_CLOCK_GATE_DISABLE |
8403 SVSMUNIT_CLOCK_GATE_DISABLE);
8404 I915_WRITE(PCH_3DCGDIS1,
8405 VFMUNIT_CLOCK_GATE_DISABLE);
8406
8407 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8408
6067aaea
JB		 8409 /*
8410 * According to the spec the following bits should be set in
8411 * order to enable memory self-refresh
8412 * The bit 22/21 of 0x42004
8413 * The bit 5 of 0x42020
8414 * The bit 15 of 0x45000
8415 */
8416 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8417 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8418 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8419 I915_WRITE(ILK_DSPCLK_GATE,
8420 (I915_READ(ILK_DSPCLK_GATE) |
8421 ILK_DPARB_CLK_GATE));
8422 I915_WRITE(DISP_ARB_CTL,
8423 (I915_READ(DISP_ARB_CTL) |
8424 DISP_FBC_WM_DIS));
8425 I915_WRITE(WM3_LP_ILK, 0);
8426 I915_WRITE(WM2_LP_ILK, 0);
8427 I915_WRITE(WM1_LP_ILK, 0);
8428
8429 /*
8430 * Based on the document from hardware guys the following bits
8431 * should be set unconditionally in order to enable FBC.
8432 * The bit 22 of 0x42000
8433 * The bit 22 of 0x42004
8434 * The bit 7,8,9 of 0x42020.
8435 */
8436 if (IS_IRONLAKE_M(dev)) {
8437 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8438 I915_READ(ILK_DISPLAY_CHICKEN1) |
8439 ILK_FBCQ_DIS);
8440 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8441 I915_READ(ILK_DISPLAY_CHICKEN2) |
8442 ILK_DPARB_GATE);
8443 I915_WRITE(ILK_DSPCLK_GATE,
8444 I915_READ(ILK_DSPCLK_GATE) |
8445 ILK_DPFC_DIS1 |
8446 ILK_DPFC_DIS2 |
8447 ILK_CLK_FBC);
8448 }
8449
8450 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8451 I915_READ(ILK_DISPLAY_CHICKEN2) |
8452 ILK_ELPIN_409_SELECT);
8453 I915_WRITE(_3D_CHICKEN2,
8454 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8455 _3D_CHICKEN2_WM_READ_PIPELINED);
8fd26859
CW		 8456}
8457
6067aaea 8458static void gen6_init_clock_gating(struct drm_device *dev)
652c393a
JB		 8459{
8460 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 8461 int pipe;
6067aaea
JB		 8462 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8463
8464 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
652c393a 8465
6067aaea
JB		 8466 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8467 I915_READ(ILK_DISPLAY_CHICKEN2) |
8468 ILK_ELPIN_409_SELECT);
8956c8bb 8469
6067aaea
JB		 8470 I915_WRITE(WM3_LP_ILK, 0);
8471 I915_WRITE(WM2_LP_ILK, 0);
8472 I915_WRITE(WM1_LP_ILK, 0);
652c393a 8473
406478dc
EA		 8474 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8475 * gating disable must be set. Failure to set it results in
8476 * flickering pixels due to Z write ordering failures after
8477 * some amount of runtime in the Mesa "fire" demo, and Unigine
8478 * Sanctuary and Tropics, and apparently anything else with
8479 * alpha test or pixel discard.
9ca1d10d
EA		 8480 *
8481 * According to the spec, bit 11 (RCCUNIT) must also be set,
8482 * but we didn't debug actual testcases to find it out.
406478dc 8483 */
9ca1d10d
EA		 8484 I915_WRITE(GEN6_UCGCTL2,
8485 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8486 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
406478dc 8487
652c393a 8488 /*
6067aaea
JB		 8489 * According to the spec the following bits should be
8490 * set in order to enable memory self-refresh and fbc:
8491 * The bit21 and bit22 of 0x42000
8492 * The bit21 and bit22 of 0x42004
8493 * The bit5 and bit7 of 0x42020
8494 * The bit14 of 0x70180
8495 * The bit14 of 0x71180
652c393a 8496 */
6067aaea
JB		 8497 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8498 I915_READ(ILK_DISPLAY_CHICKEN1) |
8499 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8500 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8501 I915_READ(ILK_DISPLAY_CHICKEN2) |
8502 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8503 I915_WRITE(ILK_DSPCLK_GATE,
8504 I915_READ(ILK_DSPCLK_GATE) |
8505 ILK_DPARB_CLK_GATE |
8506 ILK_DPFD_CLK_GATE);
8956c8bb 8507
d74362c9 8508 for_each_pipe(pipe) {
6067aaea
JB		 8509 I915_WRITE(DSPCNTR(pipe),
8510 I915_READ(DSPCNTR(pipe)) |
8511 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 8512 intel_flush_display_plane(dev_priv, pipe);
8513 }
6067aaea 8514}
8956c8bb 8515
28963a3e
JB		 8516static void ivybridge_init_clock_gating(struct drm_device *dev)
8517{
8518 struct drm_i915_private *dev_priv = dev->dev_private;
8519 int pipe;
8520 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7f8a8569 8521
28963a3e 8522 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
382b0936 8523
28963a3e
JB		 8524 I915_WRITE(WM3_LP_ILK, 0);
8525 I915_WRITE(WM2_LP_ILK, 0);
8526 I915_WRITE(WM1_LP_ILK, 0);
de6e2eaf 8527
28963a3e 8528 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
67e92af0 8529
116ac8d2
EA		 8530 I915_WRITE(IVB_CHICKEN3,
8531 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8532 CHICKEN3_DGMG_DONE_FIX_DISABLE);
8533
d74362c9 8534 for_each_pipe(pipe) {
28963a3e
JB		 8535 I915_WRITE(DSPCNTR(pipe),
8536 I915_READ(DSPCNTR(pipe)) |
8537 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 8538 intel_flush_display_plane(dev_priv, pipe);
8539 }
28963a3e
JB		 8540}
8541
6067aaea
JB		 8542static void g4x_init_clock_gating(struct drm_device *dev)
8543{
8544 struct drm_i915_private *dev_priv = dev->dev_private;
8545 uint32_t dspclk_gate;
8fd26859 8546
6067aaea
JB		 8547 I915_WRITE(RENCLK_GATE_D1, 0);
8548 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8549 GS_UNIT_CLOCK_GATE_DISABLE |
8550 CL_UNIT_CLOCK_GATE_DISABLE);
8551 I915_WRITE(RAMCLK_GATE_D, 0);
8552 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8553 OVRUNIT_CLOCK_GATE_DISABLE |
8554 OVCUNIT_CLOCK_GATE_DISABLE;
8555 if (IS_GM45(dev))
8556 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8557 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8558}
1398261a 8559
6067aaea
JB		 8560static void crestline_init_clock_gating(struct drm_device *dev)
8561{
8562 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 8563
6067aaea
JB		 8564 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8565 I915_WRITE(RENCLK_GATE_D2, 0);
8566 I915_WRITE(DSPCLK_GATE_D, 0);
8567 I915_WRITE(RAMCLK_GATE_D, 0);
8568 I915_WRITE16(DEUC, 0);
8569}
652c393a 8570
6067aaea
JB		 8571static void broadwater_init_clock_gating(struct drm_device *dev)
8572{
8573 struct drm_i915_private *dev_priv = dev->dev_private;
8574
8575 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8576 I965_RCC_CLOCK_GATE_DISABLE |
8577 I965_RCPB_CLOCK_GATE_DISABLE |
8578 I965_ISC_CLOCK_GATE_DISABLE |
8579 I965_FBC_CLOCK_GATE_DISABLE);
8580 I915_WRITE(RENCLK_GATE_D2, 0);
8581}
8582
8583static void gen3_init_clock_gating(struct drm_device *dev)
8584{
8585 struct drm_i915_private *dev_priv = dev->dev_private;
8586 u32 dstate = I915_READ(D_STATE);
8587
8588 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8589 DSTATE_DOT_CLOCK_GATING;
8590 I915_WRITE(D_STATE, dstate);
8591}
8592
8593static void i85x_init_clock_gating(struct drm_device *dev)
8594{
8595 struct drm_i915_private *dev_priv = dev->dev_private;
8596
8597 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8598}
8599
8600static void i830_init_clock_gating(struct drm_device *dev)
8601{
8602 struct drm_i915_private *dev_priv = dev->dev_private;
8603
8604 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
652c393a
JB		 8605}
8606
645c62a5
JB		 8607static void ibx_init_clock_gating(struct drm_device *dev)
8608{
8609 struct drm_i915_private *dev_priv = dev->dev_private;
8610
8611 /*
8612 * On Ibex Peak and Cougar Point, we need to disable clock
8613 * gating for the panel power sequencer or it will fail to
8614 * start up when no ports are active.
8615 */
8616 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8617}
8618
8619static void cpt_init_clock_gating(struct drm_device *dev)
8620{
8621 struct drm_i915_private *dev_priv = dev->dev_private;
3bcf603f 8622 int pipe;
645c62a5
JB		 8623
8624 /*
8625 * On Ibex Peak and Cougar Point, we need to disable clock
8626 * gating for the panel power sequencer or it will fail to
8627 * start up when no ports are active.
8628 */
8629 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8630 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8631 DPLS_EDP_PPS_FIX_DIS);
3bcf603f
JB		 8632 /* Without this, mode sets may fail silently on FDI */
8633 for_each_pipe(pipe)
8634 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
652c393a
JB		 8635}
8636
ac668088 8637static void ironlake_teardown_rc6(struct drm_device *dev)
0cdab21f
CW		 8638{
8639 struct drm_i915_private *dev_priv = dev->dev_private;
8640
8641 if (dev_priv->renderctx) {
ac668088
CW		 8642 i915_gem_object_unpin(dev_priv->renderctx);
8643 drm_gem_object_unreference(&dev_priv->renderctx->base);
0cdab21f
CW		 8644 dev_priv->renderctx = NULL;
8645 }
8646
8647 if (dev_priv->pwrctx) {
ac668088
CW		 8648 i915_gem_object_unpin(dev_priv->pwrctx);
8649 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8650 dev_priv->pwrctx = NULL;
8651 }
8652}
8653
8654static void ironlake_disable_rc6(struct drm_device *dev)
8655{
8656 struct drm_i915_private *dev_priv = dev->dev_private;
8657
8658 if (I915_READ(PWRCTXA)) {
8659 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8660 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8661 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8662 50);
0cdab21f
CW		 8663
8664 I915_WRITE(PWRCTXA, 0);
8665 POSTING_READ(PWRCTXA);
8666
ac668088
CW		 8667 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8668 POSTING_READ(RSTDBYCTL);
0cdab21f 8669 }
ac668088 8670
99507307 8671 ironlake_teardown_rc6(dev);
0cdab21f
CW		 8672}
8673
ac668088 8674static int ironlake_setup_rc6(struct drm_device *dev)
d5bb081b
JB		 8675{
8676 struct drm_i915_private *dev_priv = dev->dev_private;
8677
ac668088
CW		 8678 if (dev_priv->renderctx == NULL)
8679 dev_priv->renderctx = intel_alloc_context_page(dev);
8680 if (!dev_priv->renderctx)
8681 return -ENOMEM;
8682
8683 if (dev_priv->pwrctx == NULL)
8684 dev_priv->pwrctx = intel_alloc_context_page(dev);
8685 if (!dev_priv->pwrctx) {
8686 ironlake_teardown_rc6(dev);
8687 return -ENOMEM;
8688 }
8689
8690 return 0;
d5bb081b
JB		 8691}
8692
8693void ironlake_enable_rc6(struct drm_device *dev)
8694{
8695 struct drm_i915_private *dev_priv = dev->dev_private;
8696 int ret;
8697
ac668088
CW		 8698 /* rc6 disabled by default due to repeated reports of hanging during
8699 * boot and resume.
8700 */
c0f372b3 8701 if (!intel_enable_rc6(dev))
ac668088
CW		 8702 return;
8703
2c34b850 8704 mutex_lock(&dev->struct_mutex);
ac668088 8705 ret = ironlake_setup_rc6(dev);
2c34b850
BW		 8706 if (ret) {
8707 mutex_unlock(&dev->struct_mutex);
ac668088 8708 return;
2c34b850 8709 }
ac668088 8710
d5bb081b
JB		 8711 /*
8712 * GPU can automatically power down the render unit if given a page
8713 * to save state.
8714 */
8715 ret = BEGIN_LP_RING(6);
8716 if (ret) {
ac668088 8717 ironlake_teardown_rc6(dev);
2c34b850 8718 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8719 return;
8720 }
ac668088 8721
d5bb081b
JB		 8722 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8723 OUT_RING(MI_SET_CONTEXT);
8724 OUT_RING(dev_priv->renderctx->gtt_offset |
8725 MI_MM_SPACE_GTT |
8726 MI_SAVE_EXT_STATE_EN |
8727 MI_RESTORE_EXT_STATE_EN |
8728 MI_RESTORE_INHIBIT);
8729 OUT_RING(MI_SUSPEND_FLUSH);
8730 OUT_RING(MI_NOOP);
8731 OUT_RING(MI_FLUSH);
8732 ADVANCE_LP_RING();
8733
4a246cfc
BW		 8734 /*
8735 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8736 * does an implicit flush, combined with MI_FLUSH above, it should be
8737 * safe to assume that renderctx is valid
8738 */
8739 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8740 if (ret) {
8741 DRM_ERROR("failed to enable ironlake power power savings\n");
8742 ironlake_teardown_rc6(dev);
8743 mutex_unlock(&dev->struct_mutex);
8744 return;
8745 }
8746
d5bb081b
JB		 8747 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8748 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2c34b850 8749 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8750}
8751
645c62a5
JB		 8752void intel_init_clock_gating(struct drm_device *dev)
8753{
8754 struct drm_i915_private *dev_priv = dev->dev_private;
8755
8756 dev_priv->display.init_clock_gating(dev);
8757
8758 if (dev_priv->display.init_pch_clock_gating)
8759 dev_priv->display.init_pch_clock_gating(dev);
8760}
ac668088 8761
e70236a8
JB		 8762/* Set up chip specific display functions */
8763static void intel_init_display(struct drm_device *dev)
8764{
8765 struct drm_i915_private *dev_priv = dev->dev_private;
8766
8767 /* We always want a DPMS function */
f564048e 8768 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 8769 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 8770 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
17638cd6 8771 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8772 } else {
e70236a8 8773 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 8774 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
17638cd6 8775 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8776 }
e70236a8 8777
ee5382ae 8778 if (I915_HAS_FBC(dev)) {
9c04f015 8779 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 8780 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8781 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8782 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8783 } else if (IS_GM45(dev)) {
74dff282
JB		 8784 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8785 dev_priv->display.enable_fbc = g4x_enable_fbc;
8786 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 8787 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 8788 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8789 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8790 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8791 }
74dff282 8792 /* 855GM needs testing */
e70236a8
JB		 8793 }
8794
8795 /* Returns the core display clock speed */
0206e353 8796 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8797 dev_priv->display.get_display_clock_speed =
8798 i945_get_display_clock_speed;
8799 else if (IS_I915G(dev))
8800 dev_priv->display.get_display_clock_speed =
8801 i915_get_display_clock_speed;
f2b115e6 8802 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8803 dev_priv->display.get_display_clock_speed =
8804 i9xx_misc_get_display_clock_speed;
8805 else if (IS_I915GM(dev))
8806 dev_priv->display.get_display_clock_speed =
8807 i915gm_get_display_clock_speed;
8808 else if (IS_I865G(dev))
8809 dev_priv->display.get_display_clock_speed =
8810 i865_get_display_clock_speed;
f0f8a9ce 8811 else if (IS_I85X(dev))
e70236a8
JB		 8812 dev_priv->display.get_display_clock_speed =
8813 i855_get_display_clock_speed;
8814 else /* 852, 830 */
8815 dev_priv->display.get_display_clock_speed =
8816 i830_get_display_clock_speed;
8817
8818 /* For FIFO watermark updates */
7f8a8569 8819 if (HAS_PCH_SPLIT(dev)) {
8d715f00
KP		 8820 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8821 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8822
8823 /* IVB configs may use multi-threaded forcewake */
8824 if (IS_IVYBRIDGE(dev)) {
8825 u32 ecobus;
8826
c7dffff7
KP		 8827 /* A small trick here - if the bios hasn't configured MT forcewake,
8828 * and if the device is in RC6, then force_wake_mt_get will not wake
8829 * the device and the ECOBUS read will return zero. Which will be
8830 * (correctly) interpreted by the test below as MT forcewake being
8831 * disabled.
8832 */
8d715f00
KP		 8833 mutex_lock(&dev->struct_mutex);
8834 __gen6_gt_force_wake_mt_get(dev_priv);
c7dffff7 8835 ecobus = I915_READ_NOTRACE(ECOBUS);
8d715f00
KP		 8836 __gen6_gt_force_wake_mt_put(dev_priv);
8837 mutex_unlock(&dev->struct_mutex);
8838
8839 if (ecobus & FORCEWAKE_MT_ENABLE) {
8840 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8841 dev_priv->display.force_wake_get =
8842 __gen6_gt_force_wake_mt_get;
8843 dev_priv->display.force_wake_put =
8844 __gen6_gt_force_wake_mt_put;
8845 }
8846 }
8847
645c62a5
JB		 8848 if (HAS_PCH_IBX(dev))
8849 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8850 else if (HAS_PCH_CPT(dev))
8851 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8852
f00a3ddf 8853 if (IS_GEN5(dev)) {
7f8a8569
ZW		 8854 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8855 dev_priv->display.update_wm = ironlake_update_wm;
8856 else {
8857 DRM_DEBUG_KMS("Failed to get proper latency. "
8858 "Disable CxSR\n");
8859 dev_priv->display.update_wm = NULL;
1398261a 8860 }
674cf967 8861 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6067aaea 8862 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
e0dac65e 8863 dev_priv->display.write_eld = ironlake_write_eld;
1398261a
YL		 8864 } else if (IS_GEN6(dev)) {
8865 if (SNB_READ_WM0_LATENCY()) {
8866 dev_priv->display.update_wm = sandybridge_update_wm;
b840d907 8867 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
1398261a
YL		 8868 } else {
8869 DRM_DEBUG_KMS("Failed to read display plane latency. "
8870 "Disable CxSR\n");
8871 dev_priv->display.update_wm = NULL;
7f8a8569 8872 }
674cf967 8873 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6067aaea 8874 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
e0dac65e 8875 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8876 } else if (IS_IVYBRIDGE(dev)) {
8877 /* FIXME: detect B0+ stepping and use auto training */
8878 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
fe100d4d
JB		 8879 if (SNB_READ_WM0_LATENCY()) {
8880 dev_priv->display.update_wm = sandybridge_update_wm;
b840d907 8881 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
fe100d4d
JB		 8882 } else {
8883 DRM_DEBUG_KMS("Failed to read display plane latency. "
8884 "Disable CxSR\n");
8885 dev_priv->display.update_wm = NULL;
8886 }
28963a3e 8887 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
e0dac65e 8888 dev_priv->display.write_eld = ironlake_write_eld;
7f8a8569
ZW		 8889 } else
8890 dev_priv->display.update_wm = NULL;
8891 } else if (IS_PINEVIEW(dev)) {
d4294342 8892 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 8893 dev_priv->is_ddr3,
d4294342
ZY		 8894 dev_priv->fsb_freq,
8895 dev_priv->mem_freq)) {
8896 DRM_INFO("failed to find known CxSR latency "
95534263 8897 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 8898 "disabling CxSR\n",
0206e353 8899 (dev_priv->is_ddr3 == 1) ? "3" : "2",
d4294342
ZY		 8900 dev_priv->fsb_freq, dev_priv->mem_freq);
8901 /* Disable CxSR and never update its watermark again */
8902 pineview_disable_cxsr(dev);
8903 dev_priv->display.update_wm = NULL;
8904 } else
8905 dev_priv->display.update_wm = pineview_update_wm;
95e0ee92 8906 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6067aaea 8907 } else if (IS_G4X(dev)) {
e0dac65e 8908 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8909 dev_priv->display.update_wm = g4x_update_wm;
6067aaea
JB		 8910 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8911 } else if (IS_GEN4(dev)) {
e70236a8 8912 dev_priv->display.update_wm = i965_update_wm;
6067aaea
JB		 8913 if (IS_CRESTLINE(dev))
8914 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8915 else if (IS_BROADWATER(dev))
8916 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8917 } else if (IS_GEN3(dev)) {
e70236a8
JB		 8918 dev_priv->display.update_wm = i9xx_update_wm;
8919 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6067aaea
JB		 8920 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8921 } else if (IS_I865G(dev)) {
8922 dev_priv->display.update_wm = i830_update_wm;
8923 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8924 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8f4695ed
AJ		 8925 } else if (IS_I85X(dev)) {
8926 dev_priv->display.update_wm = i9xx_update_wm;
8927 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6067aaea 8928 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
e70236a8 8929 } else {
8f4695ed 8930 dev_priv->display.update_wm = i830_update_wm;
6067aaea 8931 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8f4695ed 8932 if (IS_845G(dev))
e70236a8
JB		 8933 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8934 else
8935 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8 8936 }
8c9f3aaf
JB		 8937
8938 /* Default just returns -ENODEV to indicate unsupported */
8939 dev_priv->display.queue_flip = intel_default_queue_flip;
8940
8941 switch (INTEL_INFO(dev)->gen) {
8942 case 2:
8943 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8944 break;
8945
8946 case 3:
8947 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8948 break;
8949
8950 case 4:
8951 case 5:
8952 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8953 break;
8954
8955 case 6:
8956 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8957 break;
7c9017e5
JB		 8958 case 7:
8959 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8960 break;
8c9f3aaf 8961 }
e70236a8
JB		 8962}
8963
b690e96c
JB		 8964/*
8965 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8966 * resume, or other times. This quirk makes sure that's the case for
8967 * affected systems.
8968 */
0206e353 8969static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8970{
8971 struct drm_i915_private *dev_priv = dev->dev_private;
8972
8973 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8974 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8975}
8976
435793df
KP		 8977/*
8978 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8979 */
8980static void quirk_ssc_force_disable(struct drm_device *dev)
8981{
8982 struct drm_i915_private *dev_priv = dev->dev_private;
8983 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8984}
8985
b690e96c
JB		 8986struct intel_quirk {
8987 int device;
8988 int subsystem_vendor;
8989 int subsystem_device;
8990 void (*hook)(struct drm_device *dev);
8991};
8992
8993struct intel_quirk intel_quirks[] = {
8994 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8995 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8996 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8997 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c
JB		 8998
8999 /* Thinkpad R31 needs pipe A force quirk */
9000 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
9001 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9002 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9003
9004 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
9005 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
9006 /* ThinkPad X40 needs pipe A force quirk */
9007
9008 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9009 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9010
9011 /* 855 & before need to leave pipe A & dpll A up */
9012 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9013 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9014
9015 /* Lenovo U160 cannot use SSC on LVDS */
9016 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9017
9018 /* Sony Vaio Y cannot use SSC on LVDS */
9019 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
b690e96c
JB		 9020};
9021
9022static void intel_init_quirks(struct drm_device *dev)
9023{
9024 struct pci_dev *d = dev->pdev;
9025 int i;
9026
9027 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9028 struct intel_quirk *q = &intel_quirks[i];
9029
9030 if (d->device == q->device &&
9031 (d->subsystem_vendor == q->subsystem_vendor ||
9032 q->subsystem_vendor == PCI_ANY_ID) &&
9033 (d->subsystem_device == q->subsystem_device ||
9034 q->subsystem_device == PCI_ANY_ID))
9035 q->hook(dev);
9036 }
9037}
9038
9cce37f4
JB		 9039/* Disable the VGA plane that we never use */
9040static void i915_disable_vga(struct drm_device *dev)
9041{
9042 struct drm_i915_private *dev_priv = dev->dev_private;
9043 u8 sr1;
9044 u32 vga_reg;
9045
9046 if (HAS_PCH_SPLIT(dev))
9047 vga_reg = CPU_VGACNTRL;
9048 else
9049 vga_reg = VGACNTRL;
9050
9051 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9052 outb(1, VGA_SR_INDEX);
9053 sr1 = inb(VGA_SR_DATA);
9054 outb(sr1 | 1<<5, VGA_SR_DATA);
9055 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9056 udelay(300);
9057
9058 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9059 POSTING_READ(vga_reg);
9060}
9061
79e53945
JB		 9062void intel_modeset_init(struct drm_device *dev)
9063{
652c393a 9064 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 9065 int i, ret;
79e53945
JB		 9066
9067 drm_mode_config_init(dev);
9068
9069 dev->mode_config.min_width = 0;
9070 dev->mode_config.min_height = 0;
9071
9072 dev->mode_config.funcs = (void *)&intel_mode_funcs;
9073
b690e96c
JB		 9074 intel_init_quirks(dev);
9075
e70236a8
JB		 9076 intel_init_display(dev);
9077
a6c45cf0
CW		 9078 if (IS_GEN2(dev)) {
9079 dev->mode_config.max_width = 2048;
9080 dev->mode_config.max_height = 2048;
9081 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9082 dev->mode_config.max_width = 4096;
9083 dev->mode_config.max_height = 4096;
79e53945 9084 } else {
a6c45cf0
CW		 9085 dev->mode_config.max_width = 8192;
9086 dev->mode_config.max_height = 8192;
79e53945 9087 }
35c3047a 9088 dev->mode_config.fb_base = dev->agp->base;
79e53945 9089
28c97730 9090 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 9091 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 9092
a3524f1b 9093 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 9094 intel_crtc_init(dev, i);
b840d907
JB		 9095 if (HAS_PCH_SPLIT(dev)) {
9096 ret = intel_plane_init(dev, i);
9097 if (ret)
9098 DRM_ERROR("plane %d init failed: %d\n",
9099 i, ret);
9100 }
79e53945
JB		 9101 }
9102
9cce37f4
JB		 9103 /* Just disable it once at startup */
9104 i915_disable_vga(dev);
79e53945 9105 intel_setup_outputs(dev);
652c393a 9106
645c62a5 9107 intel_init_clock_gating(dev);
9cce37f4 9108
7648fa99 9109 if (IS_IRONLAKE_M(dev)) {
f97108d1 9110 ironlake_enable_drps(dev);
7648fa99
JB		 9111 intel_init_emon(dev);
9112 }
f97108d1 9113
1c70c0ce 9114 if (IS_GEN6(dev) || IS_GEN7(dev)) {
3b8d8d91 9115 gen6_enable_rps(dev_priv);
23b2f8bb
JB		 9116 gen6_update_ring_freq(dev_priv);
9117 }
3b8d8d91 9118
652c393a
JB		 9119 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9120 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9121 (unsigned long)dev);
2c7111db
CW		 9122}
9123
9124void intel_modeset_gem_init(struct drm_device *dev)
9125{
9126 if (IS_IRONLAKE_M(dev))
9127 ironlake_enable_rc6(dev);
02e792fb
DV		 9128
9129 intel_setup_overlay(dev);
79e53945
JB		 9130}
9131
9132void intel_modeset_cleanup(struct drm_device *dev)
9133{
652c393a
JB		 9134 struct drm_i915_private *dev_priv = dev->dev_private;
9135 struct drm_crtc *crtc;
9136 struct intel_crtc *intel_crtc;
9137
f87ea761 9138 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9139 mutex_lock(&dev->struct_mutex);
9140
723bfd70
JB		 9141 intel_unregister_dsm_handler();
9142
9143
652c393a
JB		 9144 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9145 /* Skip inactive CRTCs */
9146 if (!crtc->fb)
9147 continue;
9148
9149 intel_crtc = to_intel_crtc(crtc);
3dec0095 9150 intel_increase_pllclock(crtc);
652c393a
JB		 9151 }
9152
973d04f9 9153 intel_disable_fbc(dev);
e70236a8 9154
f97108d1
JB		 9155 if (IS_IRONLAKE_M(dev))
9156 ironlake_disable_drps(dev);
1c70c0ce 9157 if (IS_GEN6(dev) || IS_GEN7(dev))
3b8d8d91 9158 gen6_disable_rps(dev);
f97108d1 9159
d5bb081b
JB		 9160 if (IS_IRONLAKE_M(dev))
9161 ironlake_disable_rc6(dev);
0cdab21f 9162
69341a5e
KH		 9163 mutex_unlock(&dev->struct_mutex);
9164
6c0d9350
DV		 9165 /* Disable the irq before mode object teardown, for the irq might
9166 * enqueue unpin/hotplug work. */
9167 drm_irq_uninstall(dev);
9168 cancel_work_sync(&dev_priv->hotplug_work);
6fdd4d98 9169 cancel_work_sync(&dev_priv->rps_work);
6c0d9350 9170
1630fe75
CW		 9171 /* flush any delayed tasks or pending work */
9172 flush_scheduled_work();
9173
3dec0095
DV		 9174 /* Shut off idle work before the crtcs get freed. */
9175 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9176 intel_crtc = to_intel_crtc(crtc);
9177 del_timer_sync(&intel_crtc->idle_timer);
9178 }
9179 del_timer_sync(&dev_priv->idle_timer);
9180 cancel_work_sync(&dev_priv->idle_work);
9181
79e53945
JB		 9182 drm_mode_config_cleanup(dev);
9183}
9184
f1c79df3
ZW		 9185/*
9186 * Return which encoder is currently attached for connector.
9187 */
df0e9248 9188struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9189{
df0e9248
CW		 9190 return &intel_attached_encoder(connector)->base;
9191}
f1c79df3 9192
df0e9248
CW		 9193void intel_connector_attach_encoder(struct intel_connector *connector,
9194 struct intel_encoder *encoder)
9195{
9196 connector->encoder = encoder;
9197 drm_mode_connector_attach_encoder(&connector->base,
9198 &encoder->base);
79e53945 9199}
28d52043
DA		 9200
9201/*
9202 * set vga decode state - true == enable VGA decode
9203 */
9204int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9205{
9206 struct drm_i915_private *dev_priv = dev->dev_private;
9207 u16 gmch_ctrl;
9208
9209 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9210 if (state)
9211 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9212 else
9213 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9214 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9215 return 0;
9216}
c4a1d9e4
CW		 9217
9218#ifdef CONFIG_DEBUG_FS
9219#include <linux/seq_file.h>
9220
9221struct intel_display_error_state {
9222 struct intel_cursor_error_state {
9223 u32 control;
9224 u32 position;
9225 u32 base;
9226 u32 size;
9227 } cursor[2];
9228
9229 struct intel_pipe_error_state {
9230 u32 conf;
9231 u32 source;
9232
9233 u32 htotal;
9234 u32 hblank;
9235 u32 hsync;
9236 u32 vtotal;
9237 u32 vblank;
9238 u32 vsync;
9239 } pipe[2];
9240
9241 struct intel_plane_error_state {
9242 u32 control;
9243 u32 stride;
9244 u32 size;
9245 u32 pos;
9246 u32 addr;
9247 u32 surface;
9248 u32 tile_offset;
9249 } plane[2];
9250};
9251
9252struct intel_display_error_state *
9253intel_display_capture_error_state(struct drm_device *dev)
9254{
0206e353 9255 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9256 struct intel_display_error_state *error;
9257 int i;
9258
9259 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9260 if (error == NULL)
9261 return NULL;
9262
9263 for (i = 0; i < 2; i++) {
9264 error->cursor[i].control = I915_READ(CURCNTR(i));
9265 error->cursor[i].position = I915_READ(CURPOS(i));
9266 error->cursor[i].base = I915_READ(CURBASE(i));
9267
9268 error->plane[i].control = I915_READ(DSPCNTR(i));
9269 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9270 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9271 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9272 error->plane[i].addr = I915_READ(DSPADDR(i));
9273 if (INTEL_INFO(dev)->gen >= 4) {
9274 error->plane[i].surface = I915_READ(DSPSURF(i));
9275 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9276 }
9277
9278 error->pipe[i].conf = I915_READ(PIPECONF(i));
9279 error->pipe[i].source = I915_READ(PIPESRC(i));
9280 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9281 error->pipe[i].hblank = I915_READ(HBLANK(i));
9282 error->pipe[i].hsync = I915_READ(HSYNC(i));
9283 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9284 error->pipe[i].vblank = I915_READ(VBLANK(i));
9285 error->pipe[i].vsync = I915_READ(VSYNC(i));
9286 }
9287
9288 return error;
9289}
9290
9291void
9292intel_display_print_error_state(struct seq_file *m,
9293 struct drm_device *dev,
9294 struct intel_display_error_state *error)
9295{
9296 int i;
9297
9298 for (i = 0; i < 2; i++) {
9299 seq_printf(m, "Pipe [%d]:\n", i);
9300 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9301 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9302 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9303 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9304 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9305 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9306 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9307 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9308
9309 seq_printf(m, "Plane [%d]:\n", i);
9310 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9311 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9312 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9313 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9314 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9315 if (INTEL_INFO(dev)->gen >= 4) {
9316 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9317 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9318 }
9319
9320 seq_printf(m, "Cursor [%d]:\n", i);
9321 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9322 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9323 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9324 }
9325}
9326#endif
Linux kernel - Deliverables
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