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drm/i915: Allow SSC parameter to override VBT value
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
23b2f8bb 27#include <linux/cpufreq.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
79e53945
JB		 34#include "drmP.h"
35#include "intel_drv.h"
36#include "i915_drm.h"
37#include "i915_drv.h"
e5510fac 38#include "i915_trace.h"
ab2c0672 39#include "drm_dp_helper.h"
79e53945
JB		 40
41#include "drm_crtc_helper.h"
42
32f9d658
ZW		 43#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
44
79e53945 45bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
7662c8bd 46static void intel_update_watermarks(struct drm_device *dev);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
60} intel_clock_t;
61
62typedef struct {
63 int min, max;
64} intel_range_t;
65
66typedef struct {
67 int dot_limit;
68 int p2_slow, p2_fast;
69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
79e53945
JB		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
d4906093
ML		 76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *);
78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *best_clock);
86static bool
87intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
88 int target, int refclk, intel_clock_t *best_clock);
79e53945 89
a4fc5ed6
KP		 90static bool
91intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
92 int target, int refclk, intel_clock_t *best_clock);
5eb08b69 93static bool
f2b115e6
AJ		 94intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
95 int target, int refclk, intel_clock_t *best_clock);
a4fc5ed6 96
021357ac
CW		 97static inline u32 /* units of 100MHz */
98intel_fdi_link_freq(struct drm_device *dev)
99{
8b99e68c
CW		 100 if (IS_GEN5(dev)) {
101 struct drm_i915_private *dev_priv = dev->dev_private;
102 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
103 } else
104 return 27;
021357ac
CW		 105}
106
e4b36699 107static const intel_limit_t intel_limits_i8xx_dvo = {
273e27ca
EA		 108 .dot = { .min = 25000, .max = 350000 },
109 .vco = { .min = 930000, .max = 1400000 },
110 .n = { .min = 3, .max = 16 },
111 .m = { .min = 96, .max = 140 },
112 .m1 = { .min = 18, .max = 26 },
113 .m2 = { .min = 6, .max = 16 },
114 .p = { .min = 4, .max = 128 },
115 .p1 = { .min = 2, .max = 33 },
116 .p2 = { .dot_limit = 165000,
117 .p2_slow = 4, .p2_fast = 2 },
d4906093 118 .find_pll = intel_find_best_PLL,
e4b36699
KP		 119};
120
121static const intel_limit_t intel_limits_i8xx_lvds = {
273e27ca
EA		 122 .dot = { .min = 25000, .max = 350000 },
123 .vco = { .min = 930000, .max = 1400000 },
124 .n = { .min = 3, .max = 16 },
125 .m = { .min = 96, .max = 140 },
126 .m1 = { .min = 18, .max = 26 },
127 .m2 = { .min = 6, .max = 16 },
128 .p = { .min = 4, .max = 128 },
129 .p1 = { .min = 1, .max = 6 },
130 .p2 = { .dot_limit = 165000,
131 .p2_slow = 14, .p2_fast = 7 },
d4906093 132 .find_pll = intel_find_best_PLL,
e4b36699 133};
273e27ca 134
e4b36699 135static const intel_limit_t intel_limits_i9xx_sdvo = {
273e27ca
EA		 136 .dot = { .min = 20000, .max = 400000 },
137 .vco = { .min = 1400000, .max = 2800000 },
138 .n = { .min = 1, .max = 6 },
139 .m = { .min = 70, .max = 120 },
140 .m1 = { .min = 10, .max = 22 },
141 .m2 = { .min = 5, .max = 9 },
142 .p = { .min = 5, .max = 80 },
143 .p1 = { .min = 1, .max = 8 },
144 .p2 = { .dot_limit = 200000,
145 .p2_slow = 10, .p2_fast = 5 },
d4906093 146 .find_pll = intel_find_best_PLL,
e4b36699
KP		 147};
148
149static const intel_limit_t intel_limits_i9xx_lvds = {
273e27ca
EA		 150 .dot = { .min = 20000, .max = 400000 },
151 .vco = { .min = 1400000, .max = 2800000 },
152 .n = { .min = 1, .max = 6 },
153 .m = { .min = 70, .max = 120 },
154 .m1 = { .min = 10, .max = 22 },
155 .m2 = { .min = 5, .max = 9 },
156 .p = { .min = 7, .max = 98 },
157 .p1 = { .min = 1, .max = 8 },
158 .p2 = { .dot_limit = 112000,
159 .p2_slow = 14, .p2_fast = 7 },
d4906093 160 .find_pll = intel_find_best_PLL,
e4b36699
KP		 161};
162
273e27ca 163
e4b36699 164static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 165 .dot = { .min = 25000, .max = 270000 },
166 .vco = { .min = 1750000, .max = 3500000},
167 .n = { .min = 1, .max = 4 },
168 .m = { .min = 104, .max = 138 },
169 .m1 = { .min = 17, .max = 23 },
170 .m2 = { .min = 5, .max = 11 },
171 .p = { .min = 10, .max = 30 },
172 .p1 = { .min = 1, .max = 3},
173 .p2 = { .dot_limit = 270000,
174 .p2_slow = 10,
175 .p2_fast = 10
044c7c41 176 },
d4906093 177 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 178};
179
180static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 181 .dot = { .min = 22000, .max = 400000 },
182 .vco = { .min = 1750000, .max = 3500000},
183 .n = { .min = 1, .max = 4 },
184 .m = { .min = 104, .max = 138 },
185 .m1 = { .min = 16, .max = 23 },
186 .m2 = { .min = 5, .max = 11 },
187 .p = { .min = 5, .max = 80 },
188 .p1 = { .min = 1, .max = 8},
189 .p2 = { .dot_limit = 165000,
190 .p2_slow = 10, .p2_fast = 5 },
d4906093 191 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 192};
193
194static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 195 .dot = { .min = 20000, .max = 115000 },
196 .vco = { .min = 1750000, .max = 3500000 },
197 .n = { .min = 1, .max = 3 },
198 .m = { .min = 104, .max = 138 },
199 .m1 = { .min = 17, .max = 23 },
200 .m2 = { .min = 5, .max = 11 },
201 .p = { .min = 28, .max = 112 },
202 .p1 = { .min = 2, .max = 8 },
203 .p2 = { .dot_limit = 0,
204 .p2_slow = 14, .p2_fast = 14
044c7c41 205 },
d4906093 206 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 207};
208
209static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 210 .dot = { .min = 80000, .max = 224000 },
211 .vco = { .min = 1750000, .max = 3500000 },
212 .n = { .min = 1, .max = 3 },
213 .m = { .min = 104, .max = 138 },
214 .m1 = { .min = 17, .max = 23 },
215 .m2 = { .min = 5, .max = 11 },
216 .p = { .min = 14, .max = 42 },
217 .p1 = { .min = 2, .max = 6 },
218 .p2 = { .dot_limit = 0,
219 .p2_slow = 7, .p2_fast = 7
044c7c41 220 },
d4906093 221 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 222};
223
224static const intel_limit_t intel_limits_g4x_display_port = {
273e27ca
EA		 225 .dot = { .min = 161670, .max = 227000 },
226 .vco = { .min = 1750000, .max = 3500000},
227 .n = { .min = 1, .max = 2 },
228 .m = { .min = 97, .max = 108 },
229 .m1 = { .min = 0x10, .max = 0x12 },
230 .m2 = { .min = 0x05, .max = 0x06 },
231 .p = { .min = 10, .max = 20 },
232 .p1 = { .min = 1, .max = 2},
233 .p2 = { .dot_limit = 0,
234 .p2_slow = 10, .p2_fast = 10 },
a4fc5ed6 235 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 236};
237
f2b115e6 238static const intel_limit_t intel_limits_pineview_sdvo = {
273e27ca
EA		 239 .dot = { .min = 20000, .max = 400000},
240 .vco = { .min = 1700000, .max = 3500000 },
241 /* Pineview's Ncounter is a ring counter */
242 .n = { .min = 3, .max = 6 },
243 .m = { .min = 2, .max = 256 },
244 /* Pineview only has one combined m divider, which we treat as m2. */
245 .m1 = { .min = 0, .max = 0 },
246 .m2 = { .min = 0, .max = 254 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8 },
249 .p2 = { .dot_limit = 200000,
250 .p2_slow = 10, .p2_fast = 5 },
6115707b 251 .find_pll = intel_find_best_PLL,
e4b36699
KP		 252};
253
f2b115e6 254static const intel_limit_t intel_limits_pineview_lvds = {
273e27ca
EA		 255 .dot = { .min = 20000, .max = 400000 },
256 .vco = { .min = 1700000, .max = 3500000 },
257 .n = { .min = 3, .max = 6 },
258 .m = { .min = 2, .max = 256 },
259 .m1 = { .min = 0, .max = 0 },
260 .m2 = { .min = 0, .max = 254 },
261 .p = { .min = 7, .max = 112 },
262 .p1 = { .min = 1, .max = 8 },
263 .p2 = { .dot_limit = 112000,
264 .p2_slow = 14, .p2_fast = 14 },
6115707b 265 .find_pll = intel_find_best_PLL,
e4b36699
KP		 266};
267
273e27ca
EA		 268/* Ironlake / Sandybridge
269 *
270 * We calculate clock using (register_value + 2) for N/M1/M2, so here
271 * the range value for them is (actual_value - 2).
272 */
b91ad0ec 273static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 5 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 10, .p2_fast = 5 },
4547668a 284 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 285};
286
b91ad0ec 287static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 3 },
291 .m = { .min = 79, .max = 118 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
295 .p1 = { .min = 2, .max = 8 },
296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 298 .find_pll = intel_g4x_find_best_PLL,
299};
300
301static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 302 .dot = { .min = 25000, .max = 350000 },
303 .vco = { .min = 1760000, .max = 3510000 },
304 .n = { .min = 1, .max = 3 },
305 .m = { .min = 79, .max = 127 },
306 .m1 = { .min = 12, .max = 22 },
307 .m2 = { .min = 5, .max = 9 },
308 .p = { .min = 14, .max = 56 },
309 .p1 = { .min = 2, .max = 8 },
310 .p2 = { .dot_limit = 225000,
311 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 312 .find_pll = intel_g4x_find_best_PLL,
313};
314
273e27ca 315/* LVDS 100mhz refclk limits. */
b91ad0ec 316static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 2 },
320 .m = { .min = 79, .max = 126 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2,.max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 327 .find_pll = intel_g4x_find_best_PLL,
328};
329
330static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 331 .dot = { .min = 25000, .max = 350000 },
332 .vco = { .min = 1760000, .max = 3510000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 79, .max = 126 },
335 .m1 = { .min = 12, .max = 22 },
336 .m2 = { .min = 5, .max = 9 },
337 .p = { .min = 14, .max = 42 },
338 .p1 = { .min = 2,.max = 6 },
339 .p2 = { .dot_limit = 225000,
340 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 341 .find_pll = intel_g4x_find_best_PLL,
342};
343
344static const intel_limit_t intel_limits_ironlake_display_port = {
273e27ca
EA		 345 .dot = { .min = 25000, .max = 350000 },
346 .vco = { .min = 1760000, .max = 3510000},
347 .n = { .min = 1, .max = 2 },
348 .m = { .min = 81, .max = 90 },
349 .m1 = { .min = 12, .max = 22 },
350 .m2 = { .min = 5, .max = 9 },
351 .p = { .min = 10, .max = 20 },
352 .p1 = { .min = 1, .max = 2},
353 .p2 = { .dot_limit = 0,
354 .p2_slow = 10, .p2_fast = 10 },
4547668a 355 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 356};
357
1b894b59
CW		 358static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
359 int refclk)
2c07245f 360{
b91ad0ec
ZW		 361 struct drm_device *dev = crtc->dev;
362 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 363 const intel_limit_t *limit;
b91ad0ec
ZW		 364
365 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b91ad0ec
ZW		 366 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
367 LVDS_CLKB_POWER_UP) {
368 /* LVDS dual channel */
1b894b59 369 if (refclk == 100000)
b91ad0ec
ZW		 370 limit = &intel_limits_ironlake_dual_lvds_100m;
371 else
372 limit = &intel_limits_ironlake_dual_lvds;
373 } else {
1b894b59 374 if (refclk == 100000)
b91ad0ec
ZW		 375 limit = &intel_limits_ironlake_single_lvds_100m;
376 else
377 limit = &intel_limits_ironlake_single_lvds;
378 }
379 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 380 HAS_eDP)
381 limit = &intel_limits_ironlake_display_port;
2c07245f 382 else
b91ad0ec 383 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 384
385 return limit;
386}
387
044c7c41
ML		 388static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
389{
390 struct drm_device *dev = crtc->dev;
391 struct drm_i915_private *dev_priv = dev->dev_private;
392 const intel_limit_t *limit;
393
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
395 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
396 LVDS_CLKB_POWER_UP)
397 /* LVDS with dual channel */
e4b36699 398 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 399 else
400 /* LVDS with dual channel */
e4b36699 401 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 402 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
403 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 404 limit = &intel_limits_g4x_hdmi;
044c7c41 405 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 406 limit = &intel_limits_g4x_sdvo;
a4fc5ed6 407 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 408 limit = &intel_limits_g4x_display_port;
044c7c41 409 } else /* The option is for other outputs */
e4b36699 410 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 411
412 return limit;
413}
414
1b894b59 415static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 416{
417 struct drm_device *dev = crtc->dev;
418 const intel_limit_t *limit;
419
bad720ff 420 if (HAS_PCH_SPLIT(dev))
1b894b59 421 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 422 else if (IS_G4X(dev)) {
044c7c41 423 limit = intel_g4x_limit(crtc);
f2b115e6 424 } else if (IS_PINEVIEW(dev)) {
2177832f 425 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 426 limit = &intel_limits_pineview_lvds;
2177832f 427 else
f2b115e6 428 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 429 } else if (!IS_GEN2(dev)) {
430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
431 limit = &intel_limits_i9xx_lvds;
432 else
433 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 434 } else {
435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 436 limit = &intel_limits_i8xx_lvds;
79e53945 437 else
e4b36699 438 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 439 }
440 return limit;
441}
442
f2b115e6
AJ		 443/* m1 is reserved as 0 in Pineview, n is a ring counter */
444static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 445{
2177832f
SL		 446 clock->m = clock->m2 + 2;
447 clock->p = clock->p1 * clock->p2;
448 clock->vco = refclk * clock->m / clock->n;
449 clock->dot = clock->vco / clock->p;
450}
451
452static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
453{
f2b115e6
AJ		 454 if (IS_PINEVIEW(dev)) {
455 pineview_clock(refclk, clock);
2177832f
SL		 456 return;
457 }
79e53945
JB		 458 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
459 clock->p = clock->p1 * clock->p2;
460 clock->vco = refclk * clock->m / (clock->n + 2);
461 clock->dot = clock->vco / clock->p;
462}
463
79e53945
JB		 464/**
465 * Returns whether any output on the specified pipe is of the specified type
466 */
4ef69c7a 467bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 468{
4ef69c7a
CW		 469 struct drm_device *dev = crtc->dev;
470 struct drm_mode_config *mode_config = &dev->mode_config;
471 struct intel_encoder *encoder;
472
473 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
474 if (encoder->base.crtc == crtc && encoder->type == type)
475 return true;
476
477 return false;
79e53945
JB		 478}
479
7c04d1d9 480#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 481/**
482 * Returns whether the given set of divisors are valid for a given refclk with
483 * the given connectors.
484 */
485
1b894b59
CW		 486static bool intel_PLL_is_valid(struct drm_device *dev,
487 const intel_limit_t *limit,
488 const intel_clock_t *clock)
79e53945 489{
79e53945
JB		 490 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
491 INTELPllInvalid ("p1 out of range\n");
492 if (clock->p < limit->p.min || limit->p.max < clock->p)
493 INTELPllInvalid ("p out of range\n");
494 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
495 INTELPllInvalid ("m2 out of range\n");
496 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
497 INTELPllInvalid ("m1 out of range\n");
f2b115e6 498 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
79e53945
JB		 499 INTELPllInvalid ("m1 <= m2\n");
500 if (clock->m < limit->m.min || limit->m.max < clock->m)
501 INTELPllInvalid ("m out of range\n");
502 if (clock->n < limit->n.min || limit->n.max < clock->n)
503 INTELPllInvalid ("n out of range\n");
504 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
505 INTELPllInvalid ("vco out of range\n");
506 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
507 * connector, etc., rather than just a single range.
508 */
509 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
510 INTELPllInvalid ("dot out of range\n");
511
512 return true;
513}
514
d4906093
ML		 515static bool
516intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
517 int target, int refclk, intel_clock_t *best_clock)
518
79e53945
JB		 519{
520 struct drm_device *dev = crtc->dev;
521 struct drm_i915_private *dev_priv = dev->dev_private;
522 intel_clock_t clock;
79e53945
JB		 523 int err = target;
524
bc5e5718 525 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 526 (I915_READ(LVDS)) != 0) {
79e53945
JB		 527 /*
528 * For LVDS, if the panel is on, just rely on its current
529 * settings for dual-channel. We haven't figured out how to
530 * reliably set up different single/dual channel state, if we
531 * even can.
532 */
533 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
534 LVDS_CLKB_POWER_UP)
535 clock.p2 = limit->p2.p2_fast;
536 else
537 clock.p2 = limit->p2.p2_slow;
538 } else {
539 if (target < limit->p2.dot_limit)
540 clock.p2 = limit->p2.p2_slow;
541 else
542 clock.p2 = limit->p2.p2_fast;
543 }
544
545 memset (best_clock, 0, sizeof (*best_clock));
546
42158660
ZY		 547 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
548 clock.m1++) {
549 for (clock.m2 = limit->m2.min;
550 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 551 /* m1 is always 0 in Pineview */
552 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 553 break;
554 for (clock.n = limit->n.min;
555 clock.n <= limit->n.max; clock.n++) {
556 for (clock.p1 = limit->p1.min;
557 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 558 int this_err;
559
2177832f 560 intel_clock(dev, refclk, &clock);
1b894b59
CW		 561 if (!intel_PLL_is_valid(dev, limit,
562 &clock))
79e53945
JB		 563 continue;
564
565 this_err = abs(clock.dot - target);
566 if (this_err < err) {
567 *best_clock = clock;
568 err = this_err;
569 }
570 }
571 }
572 }
573 }
574
575 return (err != target);
576}
577
d4906093
ML		 578static bool
579intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
580 int target, int refclk, intel_clock_t *best_clock)
581{
582 struct drm_device *dev = crtc->dev;
583 struct drm_i915_private *dev_priv = dev->dev_private;
584 intel_clock_t clock;
585 int max_n;
586 bool found;
6ba770dc
AJ		 587 /* approximately equals target * 0.00585 */
588 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 589 found = false;
590
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 592 int lvds_reg;
593
c619eed4 594 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 595 lvds_reg = PCH_LVDS;
596 else
597 lvds_reg = LVDS;
598 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 599 LVDS_CLKB_POWER_UP)
600 clock.p2 = limit->p2.p2_fast;
601 else
602 clock.p2 = limit->p2.p2_slow;
603 } else {
604 if (target < limit->p2.dot_limit)
605 clock.p2 = limit->p2.p2_slow;
606 else
607 clock.p2 = limit->p2.p2_fast;
608 }
609
610 memset(best_clock, 0, sizeof(*best_clock));
611 max_n = limit->n.max;
f77f13e2 612 /* based on hardware requirement, prefer smaller n to precision */
d4906093 613 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 614 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 615 for (clock.m1 = limit->m1.max;
616 clock.m1 >= limit->m1.min; clock.m1--) {
617 for (clock.m2 = limit->m2.max;
618 clock.m2 >= limit->m2.min; clock.m2--) {
619 for (clock.p1 = limit->p1.max;
620 clock.p1 >= limit->p1.min; clock.p1--) {
621 int this_err;
622
2177832f 623 intel_clock(dev, refclk, &clock);
1b894b59
CW		 624 if (!intel_PLL_is_valid(dev, limit,
625 &clock))
d4906093 626 continue;
1b894b59
CW		 627
628 this_err = abs(clock.dot - target);
d4906093
ML		 629 if (this_err < err_most) {
630 *best_clock = clock;
631 err_most = this_err;
632 max_n = clock.n;
633 found = true;
634 }
635 }
636 }
637 }
638 }
2c07245f
ZW		 639 return found;
640}
641
5eb08b69 642static bool
f2b115e6
AJ		 643intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
644 int target, int refclk, intel_clock_t *best_clock)
5eb08b69
ZW		 645{
646 struct drm_device *dev = crtc->dev;
647 intel_clock_t clock;
4547668a 648
5eb08b69
ZW		 649 if (target < 200000) {
650 clock.n = 1;
651 clock.p1 = 2;
652 clock.p2 = 10;
653 clock.m1 = 12;
654 clock.m2 = 9;
655 } else {
656 clock.n = 2;
657 clock.p1 = 1;
658 clock.p2 = 10;
659 clock.m1 = 14;
660 clock.m2 = 8;
661 }
662 intel_clock(dev, refclk, &clock);
663 memcpy(best_clock, &clock, sizeof(intel_clock_t));
664 return true;
665}
666
a4fc5ed6
KP		 667/* DisplayPort has only two frequencies, 162MHz and 270MHz */
668static bool
669intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *best_clock)
671{
5eddb70b
CW		 672 intel_clock_t clock;
673 if (target < 200000) {
674 clock.p1 = 2;
675 clock.p2 = 10;
676 clock.n = 2;
677 clock.m1 = 23;
678 clock.m2 = 8;
679 } else {
680 clock.p1 = 1;
681 clock.p2 = 10;
682 clock.n = 1;
683 clock.m1 = 14;
684 clock.m2 = 2;
685 }
686 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
687 clock.p = (clock.p1 * clock.p2);
688 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
689 clock.vco = 0;
690 memcpy(best_clock, &clock, sizeof(intel_clock_t));
691 return true;
a4fc5ed6
KP		 692}
693
9d0498a2
JB		 694/**
695 * intel_wait_for_vblank - wait for vblank on a given pipe
696 * @dev: drm device
697 * @pipe: pipe to wait for
698 *
699 * Wait for vblank to occur on a given pipe. Needed for various bits of
700 * mode setting code.
701 */
702void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 703{
9d0498a2 704 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 705 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 706
300387c0
CW		 707 /* Clear existing vblank status. Note this will clear any other
708 * sticky status fields as well.
709 *
710 * This races with i915_driver_irq_handler() with the result
711 * that either function could miss a vblank event. Here it is not
712 * fatal, as we will either wait upon the next vblank interrupt or
713 * timeout. Generally speaking intel_wait_for_vblank() is only
714 * called during modeset at which time the GPU should be idle and
715 * should *not* be performing page flips and thus not waiting on
716 * vblanks...
717 * Currently, the result of us stealing a vblank from the irq
718 * handler is that a single frame will be skipped during swapbuffers.
719 */
720 I915_WRITE(pipestat_reg,
721 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
722
9d0498a2 723 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 724 if (wait_for(I915_READ(pipestat_reg) &
725 PIPE_VBLANK_INTERRUPT_STATUS,
726 50))
9d0498a2
JB		 727 DRM_DEBUG_KMS("vblank wait timed out\n");
728}
729
ab7ad7f6
KP		 730/*
731 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 732 * @dev: drm device
733 * @pipe: pipe to wait for
734 *
735 * After disabling a pipe, we can't wait for vblank in the usual way,
736 * spinning on the vblank interrupt status bit, since we won't actually
737 * see an interrupt when the pipe is disabled.
738 *
ab7ad7f6
KP		 739 * On Gen4 and above:
740 * wait for the pipe register state bit to turn off
741 *
742 * Otherwise:
743 * wait for the display line value to settle (it usually
744 * ends up stopping at the start of the next frame).
58e10eb9 745 *
9d0498a2 746 */
58e10eb9 747void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 748{
749 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 750
751 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 752 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 753
754 /* Wait for the Pipe State to go off */
58e10eb9
CW		 755 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
756 100))
ab7ad7f6
KP		 757 DRM_DEBUG_KMS("pipe_off wait timed out\n");
758 } else {
759 u32 last_line;
58e10eb9 760 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 761 unsigned long timeout = jiffies + msecs_to_jiffies(100);
762
763 /* Wait for the display line to settle */
764 do {
58e10eb9 765 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 766 mdelay(5);
58e10eb9 767 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 768 time_after(timeout, jiffies));
769 if (time_after(jiffies, timeout))
770 DRM_DEBUG_KMS("pipe_off wait timed out\n");
771 }
79e53945
JB		 772}
773
b24e7179
JB		 774static const char *state_string(bool enabled)
775{
776 return enabled ? "on" : "off";
777}
778
779/* Only for pre-ILK configs */
780static void assert_pll(struct drm_i915_private *dev_priv,
781 enum pipe pipe, bool state)
782{
783 int reg;
784 u32 val;
785 bool cur_state;
786
787 reg = DPLL(pipe);
788 val = I915_READ(reg);
789 cur_state = !!(val & DPLL_VCO_ENABLE);
790 WARN(cur_state != state,
791 "PLL state assertion failure (expected %s, current %s)\n",
792 state_string(state), state_string(cur_state));
793}
794#define assert_pll_enabled(d, p) assert_pll(d, p, true)
795#define assert_pll_disabled(d, p) assert_pll(d, p, false)
796
040484af
JB		 797/* For ILK+ */
798static void assert_pch_pll(struct drm_i915_private *dev_priv,
799 enum pipe pipe, bool state)
800{
801 int reg;
802 u32 val;
803 bool cur_state;
804
805 reg = PCH_DPLL(pipe);
806 val = I915_READ(reg);
807 cur_state = !!(val & DPLL_VCO_ENABLE);
808 WARN(cur_state != state,
809 "PCH PLL state assertion failure (expected %s, current %s)\n",
810 state_string(state), state_string(cur_state));
811}
812#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
813#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
814
815static void assert_fdi_tx(struct drm_i915_private *dev_priv,
816 enum pipe pipe, bool state)
817{
818 int reg;
819 u32 val;
820 bool cur_state;
821
822 reg = FDI_TX_CTL(pipe);
823 val = I915_READ(reg);
824 cur_state = !!(val & FDI_TX_ENABLE);
825 WARN(cur_state != state,
826 "FDI TX state assertion failure (expected %s, current %s)\n",
827 state_string(state), state_string(cur_state));
828}
829#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
830#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
831
832static void assert_fdi_rx(struct drm_i915_private *dev_priv,
833 enum pipe pipe, bool state)
834{
835 int reg;
836 u32 val;
837 bool cur_state;
838
839 reg = FDI_RX_CTL(pipe);
840 val = I915_READ(reg);
841 cur_state = !!(val & FDI_RX_ENABLE);
842 WARN(cur_state != state,
843 "FDI RX state assertion failure (expected %s, current %s)\n",
844 state_string(state), state_string(cur_state));
845}
846#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
847#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
848
849static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
850 enum pipe pipe)
851{
852 int reg;
853 u32 val;
854
855 /* ILK FDI PLL is always enabled */
856 if (dev_priv->info->gen == 5)
857 return;
858
859 reg = FDI_TX_CTL(pipe);
860 val = I915_READ(reg);
861 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
862}
863
864static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
865 enum pipe pipe)
866{
867 int reg;
868 u32 val;
869
870 reg = FDI_RX_CTL(pipe);
871 val = I915_READ(reg);
872 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
873}
874
ea0760cf
JB		 875static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
876 enum pipe pipe)
877{
878 int pp_reg, lvds_reg;
879 u32 val;
880 enum pipe panel_pipe = PIPE_A;
0de3b485 881 bool locked = true;
ea0760cf
JB		 882
883 if (HAS_PCH_SPLIT(dev_priv->dev)) {
884 pp_reg = PCH_PP_CONTROL;
885 lvds_reg = PCH_LVDS;
886 } else {
887 pp_reg = PP_CONTROL;
888 lvds_reg = LVDS;
889 }
890
891 val = I915_READ(pp_reg);
892 if (!(val & PANEL_POWER_ON) ||
893 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
894 locked = false;
895
896 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
897 panel_pipe = PIPE_B;
898
899 WARN(panel_pipe == pipe && locked,
900 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 901 pipe_name(pipe));
ea0760cf
JB		 902}
903
63d7bbe9
JB		 904static void assert_pipe(struct drm_i915_private *dev_priv,
905 enum pipe pipe, bool state)
b24e7179
JB		 906{
907 int reg;
908 u32 val;
63d7bbe9 909 bool cur_state;
b24e7179
JB		 910
911 reg = PIPECONF(pipe);
912 val = I915_READ(reg);
63d7bbe9
JB		 913 cur_state = !!(val & PIPECONF_ENABLE);
914 WARN(cur_state != state,
915 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 916 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179 917}
63d7bbe9
JB		 918#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
919#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
b24e7179
JB		 920
921static void assert_plane_enabled(struct drm_i915_private *dev_priv,
922 enum plane plane)
923{
924 int reg;
925 u32 val;
926
927 reg = DSPCNTR(plane);
928 val = I915_READ(reg);
929 WARN(!(val & DISPLAY_PLANE_ENABLE),
930 "plane %c assertion failure, should be active but is disabled\n",
9db4a9c7 931 plane_name(plane));
b24e7179
JB		 932}
933
934static void assert_planes_disabled(struct drm_i915_private *dev_priv,
935 enum pipe pipe)
936{
937 int reg, i;
938 u32 val;
939 int cur_pipe;
940
19ec1358
JB		 941 /* Planes are fixed to pipes on ILK+ */
942 if (HAS_PCH_SPLIT(dev_priv->dev))
943 return;
944
b24e7179
JB		 945 /* Need to check both planes against the pipe */
946 for (i = 0; i < 2; i++) {
947 reg = DSPCNTR(i);
948 val = I915_READ(reg);
949 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
950 DISPPLANE_SEL_PIPE_SHIFT;
951 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 952 "plane %c assertion failure, should be off on pipe %c but is still active\n",
953 plane_name(i), pipe_name(pipe));
b24e7179
JB		 954 }
955}
956
92f2584a
JB		 957static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
958{
959 u32 val;
960 bool enabled;
961
962 val = I915_READ(PCH_DREF_CONTROL);
963 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
964 DREF_SUPERSPREAD_SOURCE_MASK));
965 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
966}
967
968static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
969 enum pipe pipe)
970{
971 int reg;
972 u32 val;
973 bool enabled;
974
975 reg = TRANSCONF(pipe);
976 val = I915_READ(reg);
977 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 978 WARN(enabled,
979 "transcoder assertion failed, should be off on pipe %c but is still active\n",
980 pipe_name(pipe));
92f2584a
JB		 981}
982
4e634389
KP		 983static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
984 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 985{
986 if ((val & DP_PORT_EN) == 0)
987 return false;
988
989 if (HAS_PCH_CPT(dev_priv->dev)) {
990 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
991 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
992 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
993 return false;
994 } else {
995 if ((val & DP_PIPE_MASK) != (pipe << 30))
996 return false;
997 }
998 return true;
999}
1000
1519b995
KP		 1001static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1002 enum pipe pipe, u32 val)
1003{
1004 if ((val & PORT_ENABLE) == 0)
1005 return false;
1006
1007 if (HAS_PCH_CPT(dev_priv->dev)) {
1008 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1009 return false;
1010 } else {
1011 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1012 return false;
1013 }
1014 return true;
1015}
1016
1017static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1018 enum pipe pipe, u32 val)
1019{
1020 if ((val & LVDS_PORT_EN) == 0)
1021 return false;
1022
1023 if (HAS_PCH_CPT(dev_priv->dev)) {
1024 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1025 return false;
1026 } else {
1027 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1028 return false;
1029 }
1030 return true;
1031}
1032
1033static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1034 enum pipe pipe, u32 val)
1035{
1036 if ((val & ADPA_DAC_ENABLE) == 0)
1037 return false;
1038 if (HAS_PCH_CPT(dev_priv->dev)) {
1039 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1040 return false;
1041 } else {
1042 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1043 return false;
1044 }
1045 return true;
1046}
1047
291906f1 1048static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1049 enum pipe pipe, int reg, u32 port_sel)
291906f1 1050{
47a05eca 1051 u32 val = I915_READ(reg);
4e634389 1052 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1053 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1054 reg, pipe_name(pipe));
291906f1
JB		 1055}
1056
1057static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1058 enum pipe pipe, int reg)
1059{
47a05eca 1060 u32 val = I915_READ(reg);
1519b995 1061 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
291906f1 1062 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1063 reg, pipe_name(pipe));
291906f1
JB		 1064}
1065
1066static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1067 enum pipe pipe)
1068{
1069 int reg;
1070 u32 val;
291906f1 1071
f0575e92
KP		 1072 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1073 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1074 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1075
1076 reg = PCH_ADPA;
1077 val = I915_READ(reg);
1519b995 1078 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1079 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1080 pipe_name(pipe));
291906f1
JB		 1081
1082 reg = PCH_LVDS;
1083 val = I915_READ(reg);
1519b995 1084 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1085 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1086 pipe_name(pipe));
291906f1
JB		 1087
1088 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1089 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1090 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1091}
1092
63d7bbe9
JB		 1093/**
1094 * intel_enable_pll - enable a PLL
1095 * @dev_priv: i915 private structure
1096 * @pipe: pipe PLL to enable
1097 *
1098 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1099 * make sure the PLL reg is writable first though, since the panel write
1100 * protect mechanism may be enabled.
1101 *
1102 * Note! This is for pre-ILK only.
1103 */
1104static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1105{
1106 int reg;
1107 u32 val;
1108
1109 /* No really, not for ILK+ */
1110 BUG_ON(dev_priv->info->gen >= 5);
1111
1112 /* PLL is protected by panel, make sure we can write it */
1113 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1114 assert_panel_unlocked(dev_priv, pipe);
1115
1116 reg = DPLL(pipe);
1117 val = I915_READ(reg);
1118 val |= DPLL_VCO_ENABLE;
1119
1120 /* We do this three times for luck */
1121 I915_WRITE(reg, val);
1122 POSTING_READ(reg);
1123 udelay(150); /* wait for warmup */
1124 I915_WRITE(reg, val);
1125 POSTING_READ(reg);
1126 udelay(150); /* wait for warmup */
1127 I915_WRITE(reg, val);
1128 POSTING_READ(reg);
1129 udelay(150); /* wait for warmup */
1130}
1131
1132/**
1133 * intel_disable_pll - disable a PLL
1134 * @dev_priv: i915 private structure
1135 * @pipe: pipe PLL to disable
1136 *
1137 * Disable the PLL for @pipe, making sure the pipe is off first.
1138 *
1139 * Note! This is for pre-ILK only.
1140 */
1141static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1142{
1143 int reg;
1144 u32 val;
1145
1146 /* Don't disable pipe A or pipe A PLLs if needed */
1147 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1148 return;
1149
1150 /* Make sure the pipe isn't still relying on us */
1151 assert_pipe_disabled(dev_priv, pipe);
1152
1153 reg = DPLL(pipe);
1154 val = I915_READ(reg);
1155 val &= ~DPLL_VCO_ENABLE;
1156 I915_WRITE(reg, val);
1157 POSTING_READ(reg);
1158}
1159
92f2584a
JB		 1160/**
1161 * intel_enable_pch_pll - enable PCH PLL
1162 * @dev_priv: i915 private structure
1163 * @pipe: pipe PLL to enable
1164 *
1165 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1166 * drives the transcoder clock.
1167 */
1168static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1169 enum pipe pipe)
1170{
1171 int reg;
1172 u32 val;
1173
1174 /* PCH only available on ILK+ */
1175 BUG_ON(dev_priv->info->gen < 5);
1176
1177 /* PCH refclock must be enabled first */
1178 assert_pch_refclk_enabled(dev_priv);
1179
1180 reg = PCH_DPLL(pipe);
1181 val = I915_READ(reg);
1182 val |= DPLL_VCO_ENABLE;
1183 I915_WRITE(reg, val);
1184 POSTING_READ(reg);
1185 udelay(200);
1186}
1187
1188static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int reg;
1192 u32 val;
1193
1194 /* PCH only available on ILK+ */
1195 BUG_ON(dev_priv->info->gen < 5);
1196
1197 /* Make sure transcoder isn't still depending on us */
1198 assert_transcoder_disabled(dev_priv, pipe);
1199
1200 reg = PCH_DPLL(pipe);
1201 val = I915_READ(reg);
1202 val &= ~DPLL_VCO_ENABLE;
1203 I915_WRITE(reg, val);
1204 POSTING_READ(reg);
1205 udelay(200);
1206}
1207
040484af
JB		 1208static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1209 enum pipe pipe)
1210{
1211 int reg;
1212 u32 val;
1213
1214 /* PCH only available on ILK+ */
1215 BUG_ON(dev_priv->info->gen < 5);
1216
1217 /* Make sure PCH DPLL is enabled */
1218 assert_pch_pll_enabled(dev_priv, pipe);
1219
1220 /* FDI must be feeding us bits for PCH ports */
1221 assert_fdi_tx_enabled(dev_priv, pipe);
1222 assert_fdi_rx_enabled(dev_priv, pipe);
1223
1224 reg = TRANSCONF(pipe);
1225 val = I915_READ(reg);
e9bcff5c
JB		 1226
1227 if (HAS_PCH_IBX(dev_priv->dev)) {
1228 /*
1229 * make the BPC in transcoder be consistent with
1230 * that in pipeconf reg.
1231 */
1232 val &= ~PIPE_BPC_MASK;
1233 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1234 }
040484af
JB		 1235 I915_WRITE(reg, val | TRANS_ENABLE);
1236 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1237 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1238}
1239
1240static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1241 enum pipe pipe)
1242{
1243 int reg;
1244 u32 val;
1245
1246 /* FDI relies on the transcoder */
1247 assert_fdi_tx_disabled(dev_priv, pipe);
1248 assert_fdi_rx_disabled(dev_priv, pipe);
1249
291906f1
JB		 1250 /* Ports must be off as well */
1251 assert_pch_ports_disabled(dev_priv, pipe);
1252
040484af
JB		 1253 reg = TRANSCONF(pipe);
1254 val = I915_READ(reg);
1255 val &= ~TRANS_ENABLE;
1256 I915_WRITE(reg, val);
1257 /* wait for PCH transcoder off, transcoder state */
1258 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1259 DRM_ERROR("failed to disable transcoder\n");
1260}
1261
b24e7179 1262/**
309cfea8 1263 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1264 * @dev_priv: i915 private structure
1265 * @pipe: pipe to enable
040484af 1266 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1267 *
1268 * Enable @pipe, making sure that various hardware specific requirements
1269 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1270 *
1271 * @pipe should be %PIPE_A or %PIPE_B.
1272 *
1273 * Will wait until the pipe is actually running (i.e. first vblank) before
1274 * returning.
1275 */
040484af
JB		 1276static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1277 bool pch_port)
b24e7179
JB		 1278{
1279 int reg;
1280 u32 val;
1281
1282 /*
1283 * A pipe without a PLL won't actually be able to drive bits from
1284 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1285 * need the check.
1286 */
1287 if (!HAS_PCH_SPLIT(dev_priv->dev))
1288 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1289 else {
1290 if (pch_port) {
1291 /* if driving the PCH, we need FDI enabled */
1292 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1293 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1294 }
1295 /* FIXME: assert CPU port conditions for SNB+ */
1296 }
b24e7179
JB		 1297
1298 reg = PIPECONF(pipe);
1299 val = I915_READ(reg);
00d70b15
CW		 1300 if (val & PIPECONF_ENABLE)
1301 return;
1302
1303 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1304 intel_wait_for_vblank(dev_priv->dev, pipe);
1305}
1306
1307/**
309cfea8 1308 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1309 * @dev_priv: i915 private structure
1310 * @pipe: pipe to disable
1311 *
1312 * Disable @pipe, making sure that various hardware specific requirements
1313 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1314 *
1315 * @pipe should be %PIPE_A or %PIPE_B.
1316 *
1317 * Will wait until the pipe has shut down before returning.
1318 */
1319static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1320 enum pipe pipe)
1321{
1322 int reg;
1323 u32 val;
1324
1325 /*
1326 * Make sure planes won't keep trying to pump pixels to us,
1327 * or we might hang the display.
1328 */
1329 assert_planes_disabled(dev_priv, pipe);
1330
1331 /* Don't disable pipe A or pipe A PLLs if needed */
1332 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1333 return;
1334
1335 reg = PIPECONF(pipe);
1336 val = I915_READ(reg);
00d70b15
CW		 1337 if ((val & PIPECONF_ENABLE) == 0)
1338 return;
1339
1340 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1341 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1342}
1343
d74362c9
KP		 1344/*
1345 * Plane regs are double buffered, going from enabled->disabled needs a
1346 * trigger in order to latch. The display address reg provides this.
1347 */
1348static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1349 enum plane plane)
1350{
1351 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1352 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1353}
1354
b24e7179
JB		 1355/**
1356 * intel_enable_plane - enable a display plane on a given pipe
1357 * @dev_priv: i915 private structure
1358 * @plane: plane to enable
1359 * @pipe: pipe being fed
1360 *
1361 * Enable @plane on @pipe, making sure that @pipe is running first.
1362 */
1363static void intel_enable_plane(struct drm_i915_private *dev_priv,
1364 enum plane plane, enum pipe pipe)
1365{
1366 int reg;
1367 u32 val;
1368
1369 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1370 assert_pipe_enabled(dev_priv, pipe);
1371
1372 reg = DSPCNTR(plane);
1373 val = I915_READ(reg);
00d70b15
CW		 1374 if (val & DISPLAY_PLANE_ENABLE)
1375 return;
1376
1377 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1378 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1379 intel_wait_for_vblank(dev_priv->dev, pipe);
1380}
1381
b24e7179
JB		 1382/**
1383 * intel_disable_plane - disable a display plane
1384 * @dev_priv: i915 private structure
1385 * @plane: plane to disable
1386 * @pipe: pipe consuming the data
1387 *
1388 * Disable @plane; should be an independent operation.
1389 */
1390static void intel_disable_plane(struct drm_i915_private *dev_priv,
1391 enum plane plane, enum pipe pipe)
1392{
1393 int reg;
1394 u32 val;
1395
1396 reg = DSPCNTR(plane);
1397 val = I915_READ(reg);
00d70b15
CW		 1398 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1399 return;
1400
1401 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1402 intel_flush_display_plane(dev_priv, plane);
1403 intel_wait_for_vblank(dev_priv->dev, pipe);
1404}
1405
47a05eca 1406static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1407 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1408{
1409 u32 val = I915_READ(reg);
4e634389 1410 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1411 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1412 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1413 }
47a05eca
JB		 1414}
1415
1416static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1417 enum pipe pipe, int reg)
1418{
1419 u32 val = I915_READ(reg);
1519b995 1420 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1421 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1422 reg, pipe);
47a05eca 1423 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1424 }
47a05eca
JB		 1425}
1426
1427/* Disable any ports connected to this transcoder */
1428static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1429 enum pipe pipe)
1430{
1431 u32 reg, val;
1432
1433 val = I915_READ(PCH_PP_CONTROL);
1434 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1435
f0575e92
KP		 1436 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1437 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1438 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1439
1440 reg = PCH_ADPA;
1441 val = I915_READ(reg);
1519b995 1442 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1443 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1444
1445 reg = PCH_LVDS;
1446 val = I915_READ(reg);
1519b995
KP		 1447 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1448 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1449 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1450 POSTING_READ(reg);
1451 udelay(100);
1452 }
1453
1454 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1455 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1456 disable_pch_hdmi(dev_priv, pipe, HDMID);
1457}
1458
43a9539f
CW		 1459static void i8xx_disable_fbc(struct drm_device *dev)
1460{
1461 struct drm_i915_private *dev_priv = dev->dev_private;
1462 u32 fbc_ctl;
1463
1464 /* Disable compression */
1465 fbc_ctl = I915_READ(FBC_CONTROL);
1466 if ((fbc_ctl & FBC_CTL_EN) == 0)
1467 return;
1468
1469 fbc_ctl &= ~FBC_CTL_EN;
1470 I915_WRITE(FBC_CONTROL, fbc_ctl);
1471
1472 /* Wait for compressing bit to clear */
1473 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1474 DRM_DEBUG_KMS("FBC idle timed out\n");
1475 return;
1476 }
1477
1478 DRM_DEBUG_KMS("disabled FBC\n");
1479}
1480
80824003
JB		 1481static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1482{
1483 struct drm_device *dev = crtc->dev;
1484 struct drm_i915_private *dev_priv = dev->dev_private;
1485 struct drm_framebuffer *fb = crtc->fb;
1486 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1487 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003 1488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
016b9b61 1489 int cfb_pitch;
80824003
JB		 1490 int plane, i;
1491 u32 fbc_ctl, fbc_ctl2;
1492
016b9b61
CW		 1493 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1494 if (fb->pitch < cfb_pitch)
1495 cfb_pitch = fb->pitch;
80824003
JB		 1496
1497 /* FBC_CTL wants 64B units */
016b9b61
CW		 1498 cfb_pitch = (cfb_pitch / 64) - 1;
1499 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
80824003
JB		 1500
1501 /* Clear old tags */
1502 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1503 I915_WRITE(FBC_TAG + (i * 4), 0);
1504
1505 /* Set it up... */
de568510
CW		 1506 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1507 fbc_ctl2 |= plane;
80824003
JB		 1508 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1509 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1510
1511 /* enable it... */
1512 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1513 if (IS_I945GM(dev))
49677901 1514 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
016b9b61 1515 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
80824003 1516 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
016b9b61 1517 fbc_ctl |= obj->fence_reg;
80824003
JB		 1518 I915_WRITE(FBC_CONTROL, fbc_ctl);
1519
016b9b61
CW		 1520 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1521 cfb_pitch, crtc->y, intel_crtc->plane);
80824003
JB		 1522}
1523
ee5382ae 1524static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1525{
80824003
JB		 1526 struct drm_i915_private *dev_priv = dev->dev_private;
1527
1528 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1529}
1530
74dff282
JB		 1531static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1532{
1533 struct drm_device *dev = crtc->dev;
1534 struct drm_i915_private *dev_priv = dev->dev_private;
1535 struct drm_framebuffer *fb = crtc->fb;
1536 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1537 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1539 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB		 1540 unsigned long stall_watermark = 200;
1541 u32 dpfc_ctl;
1542
74dff282 1543 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
016b9b61 1544 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
de568510 1545 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
74dff282 1546
74dff282
JB		 1547 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1548 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1549 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1550 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1551
1552 /* enable it... */
1553 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1554
28c97730 1555 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB		 1556}
1557
43a9539f 1558static void g4x_disable_fbc(struct drm_device *dev)
74dff282
JB		 1559{
1560 struct drm_i915_private *dev_priv = dev->dev_private;
1561 u32 dpfc_ctl;
1562
1563 /* Disable compression */
1564 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW		 1565 if (dpfc_ctl & DPFC_CTL_EN) {
1566 dpfc_ctl &= ~DPFC_CTL_EN;
1567 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1568
bed4a673
CW		 1569 DRM_DEBUG_KMS("disabled FBC\n");
1570 }
74dff282
JB		 1571}
1572
ee5382ae 1573static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1574{
74dff282
JB		 1575 struct drm_i915_private *dev_priv = dev->dev_private;
1576
1577 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1578}
1579
4efe0708
JB		 1580static void sandybridge_blit_fbc_update(struct drm_device *dev)
1581{
1582 struct drm_i915_private *dev_priv = dev->dev_private;
1583 u32 blt_ecoskpd;
1584
1585 /* Make sure blitter notifies FBC of writes */
fcca7926 1586 gen6_gt_force_wake_get(dev_priv);
4efe0708
JB		 1587 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1588 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1589 GEN6_BLITTER_LOCK_SHIFT;
1590 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1591 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1592 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1593 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1594 GEN6_BLITTER_LOCK_SHIFT);
1595 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1596 POSTING_READ(GEN6_BLITTER_ECOSKPD);
fcca7926 1597 gen6_gt_force_wake_put(dev_priv);
4efe0708
JB		 1598}
1599
b52eb4dc
ZY		 1600static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1601{
1602 struct drm_device *dev = crtc->dev;
1603 struct drm_i915_private *dev_priv = dev->dev_private;
1604 struct drm_framebuffer *fb = crtc->fb;
1605 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1606 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1608 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY		 1609 unsigned long stall_watermark = 200;
1610 u32 dpfc_ctl;
1611
bed4a673 1612 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
b52eb4dc
ZY		 1613 dpfc_ctl &= DPFC_RESERVED;
1614 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
9ce9d069
CW		 1615 /* Set persistent mode for front-buffer rendering, ala X. */
1616 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
016b9b61 1617 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
de568510 1618 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
b52eb4dc 1619
b52eb4dc
ZY		 1620 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1621 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1622 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1623 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1624 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1625 /* enable it... */
bed4a673 1626 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc 1627
9c04f015
YL		 1628 if (IS_GEN6(dev)) {
1629 I915_WRITE(SNB_DPFC_CTL_SA,
016b9b61 1630 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
9c04f015 1631 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
4efe0708 1632 sandybridge_blit_fbc_update(dev);
9c04f015
YL		 1633 }
1634
b52eb4dc
ZY		 1635 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1636}
1637
43a9539f 1638static void ironlake_disable_fbc(struct drm_device *dev)
b52eb4dc
ZY		 1639{
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 u32 dpfc_ctl;
1642
1643 /* Disable compression */
1644 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW		 1645 if (dpfc_ctl & DPFC_CTL_EN) {
1646 dpfc_ctl &= ~DPFC_CTL_EN;
1647 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1648
bed4a673
CW		 1649 DRM_DEBUG_KMS("disabled FBC\n");
1650 }
b52eb4dc
ZY		 1651}
1652
1653static bool ironlake_fbc_enabled(struct drm_device *dev)
1654{
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656
1657 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1658}
1659
ee5382ae
AJ		 1660bool intel_fbc_enabled(struct drm_device *dev)
1661{
1662 struct drm_i915_private *dev_priv = dev->dev_private;
1663
1664 if (!dev_priv->display.fbc_enabled)
1665 return false;
1666
1667 return dev_priv->display.fbc_enabled(dev);
1668}
1669
1630fe75
CW		 1670static void intel_fbc_work_fn(struct work_struct *__work)
1671{
1672 struct intel_fbc_work *work =
1673 container_of(to_delayed_work(__work),
1674 struct intel_fbc_work, work);
1675 struct drm_device *dev = work->crtc->dev;
1676 struct drm_i915_private *dev_priv = dev->dev_private;
1677
1678 mutex_lock(&dev->struct_mutex);
1679 if (work == dev_priv->fbc_work) {
1680 /* Double check that we haven't switched fb without cancelling
1681 * the prior work.
1682 */
016b9b61 1683 if (work->crtc->fb == work->fb) {
1630fe75
CW		 1684 dev_priv->display.enable_fbc(work->crtc,
1685 work->interval);
1686
016b9b61
CW		 1687 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1688 dev_priv->cfb_fb = work->crtc->fb->base.id;
1689 dev_priv->cfb_y = work->crtc->y;
1690 }
1691
1630fe75
CW		 1692 dev_priv->fbc_work = NULL;
1693 }
1694 mutex_unlock(&dev->struct_mutex);
1695
1696 kfree(work);
1697}
1698
1699static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1700{
1701 if (dev_priv->fbc_work == NULL)
1702 return;
1703
1704 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1705
1706 /* Synchronisation is provided by struct_mutex and checking of
1707 * dev_priv->fbc_work, so we can perform the cancellation
1708 * entirely asynchronously.
1709 */
1710 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1711 /* tasklet was killed before being run, clean up */
1712 kfree(dev_priv->fbc_work);
1713
1714 /* Mark the work as no longer wanted so that if it does
1715 * wake-up (because the work was already running and waiting
1716 * for our mutex), it will discover that is no longer
1717 * necessary to run.
1718 */
1719 dev_priv->fbc_work = NULL;
1720}
1721
43a9539f 1722static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
ee5382ae 1723{
1630fe75
CW		 1724 struct intel_fbc_work *work;
1725 struct drm_device *dev = crtc->dev;
1726 struct drm_i915_private *dev_priv = dev->dev_private;
ee5382ae
AJ		 1727
1728 if (!dev_priv->display.enable_fbc)
1729 return;
1730
1630fe75
CW		 1731 intel_cancel_fbc_work(dev_priv);
1732
1733 work = kzalloc(sizeof *work, GFP_KERNEL);
1734 if (work == NULL) {
1735 dev_priv->display.enable_fbc(crtc, interval);
1736 return;
1737 }
1738
1739 work->crtc = crtc;
1740 work->fb = crtc->fb;
1741 work->interval = interval;
1742 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1743
1744 dev_priv->fbc_work = work;
1745
1746 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1747
1748 /* Delay the actual enabling to let pageflipping cease and the
016b9b61
CW		 1749 * display to settle before starting the compression. Note that
1750 * this delay also serves a second purpose: it allows for a
1751 * vblank to pass after disabling the FBC before we attempt
1752 * to modify the control registers.
1630fe75
CW		 1753 *
1754 * A more complicated solution would involve tracking vblanks
1755 * following the termination of the page-flipping sequence
1756 * and indeed performing the enable as a co-routine and not
1757 * waiting synchronously upon the vblank.
1758 */
1759 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
ee5382ae
AJ		 1760}
1761
1762void intel_disable_fbc(struct drm_device *dev)
1763{
1764 struct drm_i915_private *dev_priv = dev->dev_private;
1765
1630fe75
CW		 1766 intel_cancel_fbc_work(dev_priv);
1767
ee5382ae
AJ		 1768 if (!dev_priv->display.disable_fbc)
1769 return;
1770
1771 dev_priv->display.disable_fbc(dev);
016b9b61 1772 dev_priv->cfb_plane = -1;
ee5382ae
AJ		 1773}
1774
80824003
JB		 1775/**
1776 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1777 * @dev: the drm_device
80824003
JB		 1778 *
1779 * Set up the framebuffer compression hardware at mode set time. We
1780 * enable it if possible:
1781 * - plane A only (on pre-965)
1782 * - no pixel mulitply/line duplication
1783 * - no alpha buffer discard
1784 * - no dual wide
1785 * - framebuffer <= 2048 in width, 1536 in height
1786 *
1787 * We can't assume that any compression will take place (worst case),
1788 * so the compressed buffer has to be the same size as the uncompressed
1789 * one. It also must reside (along with the line length buffer) in
1790 * stolen memory.
1791 *
1792 * We need to enable/disable FBC on a global basis.
1793 */
bed4a673 1794static void intel_update_fbc(struct drm_device *dev)
80824003 1795{
80824003 1796 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW		 1797 struct drm_crtc *crtc = NULL, *tmp_crtc;
1798 struct intel_crtc *intel_crtc;
1799 struct drm_framebuffer *fb;
80824003 1800 struct intel_framebuffer *intel_fb;
05394f39 1801 struct drm_i915_gem_object *obj;
cd0de039 1802 int enable_fbc;
9c928d16
JB		 1803
1804 DRM_DEBUG_KMS("\n");
80824003
JB		 1805
1806 if (!i915_powersave)
1807 return;
1808
ee5382ae 1809 if (!I915_HAS_FBC(dev))
e70236a8
JB		 1810 return;
1811
80824003
JB		 1812 /*
1813 * If FBC is already on, we just have to verify that we can
1814 * keep it that way...
1815 * Need to disable if:
9c928d16 1816 * - more than one pipe is active
80824003
JB		 1817 * - changing FBC params (stride, fence, mode)
1818 * - new fb is too large to fit in compressed buffer
1819 * - going to an unsupported config (interlace, pixel multiply, etc.)
1820 */
9c928d16 1821 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
d210246a 1822 if (tmp_crtc->enabled && tmp_crtc->fb) {
bed4a673
CW		 1823 if (crtc) {
1824 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1825 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1826 goto out_disable;
1827 }
1828 crtc = tmp_crtc;
1829 }
9c928d16 1830 }
bed4a673
CW		 1831
1832 if (!crtc || crtc->fb == NULL) {
1833 DRM_DEBUG_KMS("no output, disabling\n");
1834 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB		 1835 goto out_disable;
1836 }
bed4a673
CW		 1837
1838 intel_crtc = to_intel_crtc(crtc);
1839 fb = crtc->fb;
1840 intel_fb = to_intel_framebuffer(fb);
05394f39 1841 obj = intel_fb->obj;
bed4a673 1842
cd0de039
KP		 1843 enable_fbc = i915_enable_fbc;
1844 if (enable_fbc < 0) {
1845 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1846 enable_fbc = 1;
1847 if (INTEL_INFO(dev)->gen <= 5)
1848 enable_fbc = 0;
1849 }
1850 if (!enable_fbc) {
1851 DRM_DEBUG_KMS("fbc disabled per module param\n");
c1a9f047
JB		 1852 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1853 goto out_disable;
1854 }
05394f39 1855 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 1856 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 1857 "compression\n");
b5e50c3f 1858 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1859 goto out_disable;
1860 }
bed4a673
CW		 1861 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1862 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 1863 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 1864 "disabling\n");
b5e50c3f 1865 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB		 1866 goto out_disable;
1867 }
bed4a673
CW		 1868 if ((crtc->mode.hdisplay > 2048) ||
1869 (crtc->mode.vdisplay > 1536)) {
28c97730 1870 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 1871 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB		 1872 goto out_disable;
1873 }
bed4a673 1874 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 1875 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 1876 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB		 1877 goto out_disable;
1878 }
de568510
CW		 1879
1880 /* The use of a CPU fence is mandatory in order to detect writes
1881 * by the CPU to the scanout and trigger updates to the FBC.
1882 */
1883 if (obj->tiling_mode != I915_TILING_X ||
1884 obj->fence_reg == I915_FENCE_REG_NONE) {
1885 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
b5e50c3f 1886 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB		 1887 goto out_disable;
1888 }
1889
c924b934
JW		 1890 /* If the kernel debugger is active, always disable compression */
1891 if (in_dbg_master())
1892 goto out_disable;
1893
016b9b61
CW		 1894 /* If the scanout has not changed, don't modify the FBC settings.
1895 * Note that we make the fundamental assumption that the fb->obj
1896 * cannot be unpinned (and have its GTT offset and fence revoked)
1897 * without first being decoupled from the scanout and FBC disabled.
1898 */
1899 if (dev_priv->cfb_plane == intel_crtc->plane &&
1900 dev_priv->cfb_fb == fb->base.id &&
1901 dev_priv->cfb_y == crtc->y)
1902 return;
1903
1904 if (intel_fbc_enabled(dev)) {
1905 /* We update FBC along two paths, after changing fb/crtc
1906 * configuration (modeswitching) and after page-flipping
1907 * finishes. For the latter, we know that not only did
1908 * we disable the FBC at the start of the page-flip
1909 * sequence, but also more than one vblank has passed.
1910 *
1911 * For the former case of modeswitching, it is possible
1912 * to switch between two FBC valid configurations
1913 * instantaneously so we do need to disable the FBC
1914 * before we can modify its control registers. We also
1915 * have to wait for the next vblank for that to take
1916 * effect. However, since we delay enabling FBC we can
1917 * assume that a vblank has passed since disabling and
1918 * that we can safely alter the registers in the deferred
1919 * callback.
1920 *
1921 * In the scenario that we go from a valid to invalid
1922 * and then back to valid FBC configuration we have
1923 * no strict enforcement that a vblank occurred since
1924 * disabling the FBC. However, along all current pipe
1925 * disabling paths we do need to wait for a vblank at
1926 * some point. And we wait before enabling FBC anyway.
1927 */
1928 DRM_DEBUG_KMS("disabling active FBC for update\n");
1929 intel_disable_fbc(dev);
1930 }
1931
bed4a673 1932 intel_enable_fbc(crtc, 500);
80824003
JB		 1933 return;
1934
1935out_disable:
80824003 1936 /* Multiple disables should be harmless */
a939406f
CW		 1937 if (intel_fbc_enabled(dev)) {
1938 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 1939 intel_disable_fbc(dev);
a939406f 1940 }
80824003
JB		 1941}
1942
127bd2ac 1943int
48b956c5 1944intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1945 struct drm_i915_gem_object *obj,
919926ae 1946 struct intel_ring_buffer *pipelined)
6b95a207 1947{
ce453d81 1948 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1949 u32 alignment;
1950 int ret;
1951
05394f39 1952 switch (obj->tiling_mode) {
6b95a207 1953 case I915_TILING_NONE:
534843da
CW		 1954 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1955 alignment = 128 * 1024;
a6c45cf0 1956 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1957 alignment = 4 * 1024;
1958 else
1959 alignment = 64 * 1024;
6b95a207
KH		 1960 break;
1961 case I915_TILING_X:
1962 /* pin() will align the object as required by fence */
1963 alignment = 0;
1964 break;
1965 case I915_TILING_Y:
1966 /* FIXME: Is this true? */
1967 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1968 return -EINVAL;
1969 default:
1970 BUG();
1971 }
1972
ce453d81 1973 dev_priv->mm.interruptible = false;
2da3b9b9 1974 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1975 if (ret)
ce453d81 1976 goto err_interruptible;
6b95a207
KH		 1977
1978 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1979 * fence, whereas 965+ only requires a fence if using
1980 * framebuffer compression. For simplicity, we always install
1981 * a fence as the cost is not that onerous.
1982 */
05394f39 1983 if (obj->tiling_mode != I915_TILING_NONE) {
ce453d81 1984 ret = i915_gem_object_get_fence(obj, pipelined);
48b956c5
CW		 1985 if (ret)
1986 goto err_unpin;
6b95a207
KH		 1987 }
1988
ce453d81 1989 dev_priv->mm.interruptible = true;
6b95a207 1990 return 0;
48b956c5
CW		 1991
1992err_unpin:
1993 i915_gem_object_unpin(obj);
ce453d81
CW		 1994err_interruptible:
1995 dev_priv->mm.interruptible = true;
48b956c5 1996 return ret;
6b95a207
KH		 1997}
1998
17638cd6
JB		 1999static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2000 int x, int y)
81255565
JB		 2001{
2002 struct drm_device *dev = crtc->dev;
2003 struct drm_i915_private *dev_priv = dev->dev_private;
2004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2005 struct intel_framebuffer *intel_fb;
05394f39 2006 struct drm_i915_gem_object *obj;
81255565
JB		 2007 int plane = intel_crtc->plane;
2008 unsigned long Start, Offset;
81255565 2009 u32 dspcntr;
5eddb70b 2010 u32 reg;
81255565
JB		 2011
2012 switch (plane) {
2013 case 0:
2014 case 1:
2015 break;
2016 default:
2017 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2018 return -EINVAL;
2019 }
2020
2021 intel_fb = to_intel_framebuffer(fb);
2022 obj = intel_fb->obj;
81255565 2023
5eddb70b
CW		 2024 reg = DSPCNTR(plane);
2025 dspcntr = I915_READ(reg);
81255565
JB		 2026 /* Mask out pixel format bits in case we change it */
2027 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2028 switch (fb->bits_per_pixel) {
2029 case 8:
2030 dspcntr |= DISPPLANE_8BPP;
2031 break;
2032 case 16:
2033 if (fb->depth == 15)
2034 dspcntr |= DISPPLANE_15_16BPP;
2035 else
2036 dspcntr |= DISPPLANE_16BPP;
2037 break;
2038 case 24:
2039 case 32:
2040 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2041 break;
2042 default:
17638cd6 2043 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2044 return -EINVAL;
2045 }
a6c45cf0 2046 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2047 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2048 dspcntr |= DISPPLANE_TILED;
2049 else
2050 dspcntr &= ~DISPPLANE_TILED;
2051 }
2052
5eddb70b 2053 I915_WRITE(reg, dspcntr);
81255565 2054
05394f39 2055 Start = obj->gtt_offset;
81255565
JB		 2056 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2057
4e6cfefc
CW		 2058 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2059 Start, Offset, x, y, fb->pitch);
5eddb70b 2060 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
a6c45cf0 2061 if (INTEL_INFO(dev)->gen >= 4) {
5eddb70b
CW		 2062 I915_WRITE(DSPSURF(plane), Start);
2063 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2064 I915_WRITE(DSPADDR(plane), Offset);
2065 } else
2066 I915_WRITE(DSPADDR(plane), Start + Offset);
2067 POSTING_READ(reg);
81255565 2068
17638cd6
JB		 2069 return 0;
2070}
2071
2072static int ironlake_update_plane(struct drm_crtc *crtc,
2073 struct drm_framebuffer *fb, int x, int y)
2074{
2075 struct drm_device *dev = crtc->dev;
2076 struct drm_i915_private *dev_priv = dev->dev_private;
2077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2078 struct intel_framebuffer *intel_fb;
2079 struct drm_i915_gem_object *obj;
2080 int plane = intel_crtc->plane;
2081 unsigned long Start, Offset;
2082 u32 dspcntr;
2083 u32 reg;
2084
2085 switch (plane) {
2086 case 0:
2087 case 1:
2088 break;
2089 default:
2090 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2091 return -EINVAL;
2092 }
2093
2094 intel_fb = to_intel_framebuffer(fb);
2095 obj = intel_fb->obj;
2096
2097 reg = DSPCNTR(plane);
2098 dspcntr = I915_READ(reg);
2099 /* Mask out pixel format bits in case we change it */
2100 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2101 switch (fb->bits_per_pixel) {
2102 case 8:
2103 dspcntr |= DISPPLANE_8BPP;
2104 break;
2105 case 16:
2106 if (fb->depth != 16)
2107 return -EINVAL;
2108
2109 dspcntr |= DISPPLANE_16BPP;
2110 break;
2111 case 24:
2112 case 32:
2113 if (fb->depth == 24)
2114 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2115 else if (fb->depth == 30)
2116 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2117 else
2118 return -EINVAL;
2119 break;
2120 default:
2121 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2122 return -EINVAL;
2123 }
2124
2125 if (obj->tiling_mode != I915_TILING_NONE)
2126 dspcntr |= DISPPLANE_TILED;
2127 else
2128 dspcntr &= ~DISPPLANE_TILED;
2129
2130 /* must disable */
2131 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2132
2133 I915_WRITE(reg, dspcntr);
2134
2135 Start = obj->gtt_offset;
2136 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2137
2138 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2139 Start, Offset, x, y, fb->pitch);
2140 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2141 I915_WRITE(DSPSURF(plane), Start);
2142 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2143 I915_WRITE(DSPADDR(plane), Offset);
2144 POSTING_READ(reg);
2145
2146 return 0;
2147}
2148
2149/* Assume fb object is pinned & idle & fenced and just update base pointers */
2150static int
2151intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2152 int x, int y, enum mode_set_atomic state)
2153{
2154 struct drm_device *dev = crtc->dev;
2155 struct drm_i915_private *dev_priv = dev->dev_private;
2156 int ret;
2157
2158 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2159 if (ret)
2160 return ret;
2161
bed4a673 2162 intel_update_fbc(dev);
3dec0095 2163 intel_increase_pllclock(crtc);
81255565
JB		 2164
2165 return 0;
2166}
2167
5c3b82e2 2168static int
3c4fdcfb
KH		 2169intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2170 struct drm_framebuffer *old_fb)
79e53945
JB		 2171{
2172 struct drm_device *dev = crtc->dev;
79e53945
JB		 2173 struct drm_i915_master_private *master_priv;
2174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2175 int ret;
79e53945
JB		 2176
2177 /* no fb bound */
2178 if (!crtc->fb) {
a5071c2f 2179 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2180 return 0;
2181 }
2182
265db958 2183 switch (intel_crtc->plane) {
5c3b82e2
CW		 2184 case 0:
2185 case 1:
2186 break;
2187 default:
a5071c2f 2188 DRM_ERROR("no plane for crtc\n");
5c3b82e2 2189 return -EINVAL;
79e53945
JB		 2190 }
2191
5c3b82e2 2192 mutex_lock(&dev->struct_mutex);
265db958
CW		 2193 ret = intel_pin_and_fence_fb_obj(dev,
2194 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2195 NULL);
5c3b82e2
CW		 2196 if (ret != 0) {
2197 mutex_unlock(&dev->struct_mutex);
a5071c2f 2198 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2199 return ret;
2200 }
79e53945 2201
265db958 2202 if (old_fb) {
e6c3a2a6 2203 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 2204 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
265db958 2205
e6c3a2a6 2206 wait_event(dev_priv->pending_flip_queue,
01eec727 2207 atomic_read(&dev_priv->mm.wedged) ||
05394f39 2208 atomic_read(&obj->pending_flip) == 0);
85345517
CW		 2209
2210 /* Big Hammer, we also need to ensure that any pending
2211 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2212 * current scanout is retired before unpinning the old
2213 * framebuffer.
01eec727
CW		 2214 *
2215 * This should only fail upon a hung GPU, in which case we
2216 * can safely continue.
85345517 2217 */
a8198eea 2218 ret = i915_gem_object_finish_gpu(obj);
01eec727 2219 (void) ret;
265db958
CW		 2220 }
2221
21c74a8e
JW		 2222 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2223 LEAVE_ATOMIC_MODE_SET);
4e6cfefc 2224 if (ret) {
265db958 2225 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2226 mutex_unlock(&dev->struct_mutex);
a5071c2f 2227 DRM_ERROR("failed to update base address\n");
4e6cfefc 2228 return ret;
79e53945 2229 }
3c4fdcfb 2230
b7f1de28
CW		 2231 if (old_fb) {
2232 intel_wait_for_vblank(dev, intel_crtc->pipe);
265db958 2233 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2234 }
652c393a 2235
5c3b82e2 2236 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2237
2238 if (!dev->primary->master)
5c3b82e2 2239 return 0;
79e53945
JB		 2240
2241 master_priv = dev->primary->master->driver_priv;
2242 if (!master_priv->sarea_priv)
5c3b82e2 2243 return 0;
79e53945 2244
265db958 2245 if (intel_crtc->pipe) {
79e53945
JB		 2246 master_priv->sarea_priv->pipeB_x = x;
2247 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2248 } else {
2249 master_priv->sarea_priv->pipeA_x = x;
2250 master_priv->sarea_priv->pipeA_y = y;
79e53945 2251 }
5c3b82e2
CW		 2252
2253 return 0;
79e53945
JB		 2254}
2255
5eddb70b 2256static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2257{
2258 struct drm_device *dev = crtc->dev;
2259 struct drm_i915_private *dev_priv = dev->dev_private;
2260 u32 dpa_ctl;
2261
28c97730 2262 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2263 dpa_ctl = I915_READ(DP_A);
2264 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2265
2266 if (clock < 200000) {
2267 u32 temp;
2268 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2269 /* workaround for 160Mhz:
2270 1) program 0x4600c bits 15:0 = 0x8124
2271 2) program 0x46010 bit 0 = 1
2272 3) program 0x46034 bit 24 = 1
2273 4) program 0x64000 bit 14 = 1
2274 */
2275 temp = I915_READ(0x4600c);
2276 temp &= 0xffff0000;
2277 I915_WRITE(0x4600c, temp | 0x8124);
2278
2279 temp = I915_READ(0x46010);
2280 I915_WRITE(0x46010, temp | 1);
2281
2282 temp = I915_READ(0x46034);
2283 I915_WRITE(0x46034, temp | (1 << 24));
2284 } else {
2285 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2286 }
2287 I915_WRITE(DP_A, dpa_ctl);
2288
5eddb70b 2289 POSTING_READ(DP_A);
32f9d658
ZW		 2290 udelay(500);
2291}
2292
5e84e1a4
ZW		 2293static void intel_fdi_normal_train(struct drm_crtc *crtc)
2294{
2295 struct drm_device *dev = crtc->dev;
2296 struct drm_i915_private *dev_priv = dev->dev_private;
2297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2298 int pipe = intel_crtc->pipe;
2299 u32 reg, temp;
2300
2301 /* enable normal train */
2302 reg = FDI_TX_CTL(pipe);
2303 temp = I915_READ(reg);
61e499bf 2304 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2305 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2306 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2307 } else {
2308 temp &= ~FDI_LINK_TRAIN_NONE;
2309 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2310 }
5e84e1a4
ZW		 2311 I915_WRITE(reg, temp);
2312
2313 reg = FDI_RX_CTL(pipe);
2314 temp = I915_READ(reg);
2315 if (HAS_PCH_CPT(dev)) {
2316 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2317 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2318 } else {
2319 temp &= ~FDI_LINK_TRAIN_NONE;
2320 temp |= FDI_LINK_TRAIN_NONE;
2321 }
2322 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2323
2324 /* wait one idle pattern time */
2325 POSTING_READ(reg);
2326 udelay(1000);
357555c0
JB		 2327
2328 /* IVB wants error correction enabled */
2329 if (IS_IVYBRIDGE(dev))
2330 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2331 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2332}
2333
291427f5
JB		 2334static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2335{
2336 struct drm_i915_private *dev_priv = dev->dev_private;
2337 u32 flags = I915_READ(SOUTH_CHICKEN1);
2338
2339 flags |= FDI_PHASE_SYNC_OVR(pipe);
2340 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2341 flags |= FDI_PHASE_SYNC_EN(pipe);
2342 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2343 POSTING_READ(SOUTH_CHICKEN1);
2344}
2345
8db9d77b
ZW		 2346/* The FDI link training functions for ILK/Ibexpeak. */
2347static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2348{
2349 struct drm_device *dev = crtc->dev;
2350 struct drm_i915_private *dev_priv = dev->dev_private;
2351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2352 int pipe = intel_crtc->pipe;
0fc932b8 2353 int plane = intel_crtc->plane;
5eddb70b 2354 u32 reg, temp, tries;
8db9d77b 2355
0fc932b8
JB		 2356 /* FDI needs bits from pipe & plane first */
2357 assert_pipe_enabled(dev_priv, pipe);
2358 assert_plane_enabled(dev_priv, plane);
2359
e1a44743
AJ		 2360 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2361 for train result */
5eddb70b
CW		 2362 reg = FDI_RX_IMR(pipe);
2363 temp = I915_READ(reg);
e1a44743
AJ		 2364 temp &= ~FDI_RX_SYMBOL_LOCK;
2365 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2366 I915_WRITE(reg, temp);
2367 I915_READ(reg);
e1a44743
AJ		 2368 udelay(150);
2369
8db9d77b 2370 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2371 reg = FDI_TX_CTL(pipe);
2372 temp = I915_READ(reg);
77ffb597
AJ		 2373 temp &= ~(7 << 19);
2374 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2375 temp &= ~FDI_LINK_TRAIN_NONE;
2376 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2377 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2378
5eddb70b
CW		 2379 reg = FDI_RX_CTL(pipe);
2380 temp = I915_READ(reg);
8db9d77b
ZW		 2381 temp &= ~FDI_LINK_TRAIN_NONE;
2382 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2383 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2384
2385 POSTING_READ(reg);
8db9d77b
ZW		 2386 udelay(150);
2387
5b2adf89 2388 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2389 if (HAS_PCH_IBX(dev)) {
2390 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2391 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2392 FDI_RX_PHASE_SYNC_POINTER_EN);
2393 }
5b2adf89 2394
5eddb70b 2395 reg = FDI_RX_IIR(pipe);
e1a44743 2396 for (tries = 0; tries < 5; tries++) {
5eddb70b 2397 temp = I915_READ(reg);
8db9d77b
ZW		 2398 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2399
2400 if ((temp & FDI_RX_BIT_LOCK)) {
2401 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2402 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2403 break;
2404 }
8db9d77b 2405 }
e1a44743 2406 if (tries == 5)
5eddb70b 2407 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2408
2409 /* Train 2 */
5eddb70b
CW		 2410 reg = FDI_TX_CTL(pipe);
2411 temp = I915_READ(reg);
8db9d77b
ZW		 2412 temp &= ~FDI_LINK_TRAIN_NONE;
2413 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2414 I915_WRITE(reg, temp);
8db9d77b 2415
5eddb70b
CW		 2416 reg = FDI_RX_CTL(pipe);
2417 temp = I915_READ(reg);
8db9d77b
ZW		 2418 temp &= ~FDI_LINK_TRAIN_NONE;
2419 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2420 I915_WRITE(reg, temp);
8db9d77b 2421
5eddb70b
CW		 2422 POSTING_READ(reg);
2423 udelay(150);
8db9d77b 2424
5eddb70b 2425 reg = FDI_RX_IIR(pipe);
e1a44743 2426 for (tries = 0; tries < 5; tries++) {
5eddb70b 2427 temp = I915_READ(reg);
8db9d77b
ZW		 2428 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2429
2430 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2431 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2432 DRM_DEBUG_KMS("FDI train 2 done.\n");
2433 break;
2434 }
8db9d77b 2435 }
e1a44743 2436 if (tries == 5)
5eddb70b 2437 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2438
2439 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2440
8db9d77b
ZW		 2441}
2442
311bd68e 2443static const int snb_b_fdi_train_param [] = {
8db9d77b
ZW		 2444 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2445 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2446 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2447 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2448};
2449
2450/* The FDI link training functions for SNB/Cougarpoint. */
2451static void gen6_fdi_link_train(struct drm_crtc *crtc)
2452{
2453 struct drm_device *dev = crtc->dev;
2454 struct drm_i915_private *dev_priv = dev->dev_private;
2455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2456 int pipe = intel_crtc->pipe;
5eddb70b 2457 u32 reg, temp, i;
8db9d77b 2458
e1a44743
AJ		 2459 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2460 for train result */
5eddb70b
CW		 2461 reg = FDI_RX_IMR(pipe);
2462 temp = I915_READ(reg);
e1a44743
AJ		 2463 temp &= ~FDI_RX_SYMBOL_LOCK;
2464 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2465 I915_WRITE(reg, temp);
2466
2467 POSTING_READ(reg);
e1a44743
AJ		 2468 udelay(150);
2469
8db9d77b 2470 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2471 reg = FDI_TX_CTL(pipe);
2472 temp = I915_READ(reg);
77ffb597
AJ		 2473 temp &= ~(7 << 19);
2474 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2475 temp &= ~FDI_LINK_TRAIN_NONE;
2476 temp |= FDI_LINK_TRAIN_PATTERN_1;
2477 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2478 /* SNB-B */
2479 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2480 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2481
5eddb70b
CW		 2482 reg = FDI_RX_CTL(pipe);
2483 temp = I915_READ(reg);
8db9d77b
ZW		 2484 if (HAS_PCH_CPT(dev)) {
2485 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2486 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2487 } else {
2488 temp &= ~FDI_LINK_TRAIN_NONE;
2489 temp |= FDI_LINK_TRAIN_PATTERN_1;
2490 }
5eddb70b
CW		 2491 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2492
2493 POSTING_READ(reg);
8db9d77b
ZW		 2494 udelay(150);
2495
291427f5
JB		 2496 if (HAS_PCH_CPT(dev))
2497 cpt_phase_pointer_enable(dev, pipe);
2498
8db9d77b 2499 for (i = 0; i < 4; i++ ) {
5eddb70b
CW		 2500 reg = FDI_TX_CTL(pipe);
2501 temp = I915_READ(reg);
8db9d77b
ZW		 2502 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2503 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2504 I915_WRITE(reg, temp);
2505
2506 POSTING_READ(reg);
8db9d77b
ZW		 2507 udelay(500);
2508
5eddb70b
CW		 2509 reg = FDI_RX_IIR(pipe);
2510 temp = I915_READ(reg);
8db9d77b
ZW		 2511 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2512
2513 if (temp & FDI_RX_BIT_LOCK) {
5eddb70b 2514 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2515 DRM_DEBUG_KMS("FDI train 1 done.\n");
2516 break;
2517 }
2518 }
2519 if (i == 4)
5eddb70b 2520 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2521
2522 /* Train 2 */
5eddb70b
CW		 2523 reg = FDI_TX_CTL(pipe);
2524 temp = I915_READ(reg);
8db9d77b
ZW		 2525 temp &= ~FDI_LINK_TRAIN_NONE;
2526 temp |= FDI_LINK_TRAIN_PATTERN_2;
2527 if (IS_GEN6(dev)) {
2528 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2529 /* SNB-B */
2530 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2531 }
5eddb70b 2532 I915_WRITE(reg, temp);
8db9d77b 2533
5eddb70b
CW		 2534 reg = FDI_RX_CTL(pipe);
2535 temp = I915_READ(reg);
8db9d77b
ZW		 2536 if (HAS_PCH_CPT(dev)) {
2537 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2538 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2539 } else {
2540 temp &= ~FDI_LINK_TRAIN_NONE;
2541 temp |= FDI_LINK_TRAIN_PATTERN_2;
2542 }
5eddb70b
CW		 2543 I915_WRITE(reg, temp);
2544
2545 POSTING_READ(reg);
8db9d77b
ZW		 2546 udelay(150);
2547
2548 for (i = 0; i < 4; i++ ) {
5eddb70b
CW		 2549 reg = FDI_TX_CTL(pipe);
2550 temp = I915_READ(reg);
8db9d77b
ZW		 2551 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2552 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2553 I915_WRITE(reg, temp);
2554
2555 POSTING_READ(reg);
8db9d77b
ZW		 2556 udelay(500);
2557
5eddb70b
CW		 2558 reg = FDI_RX_IIR(pipe);
2559 temp = I915_READ(reg);
8db9d77b
ZW		 2560 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2561
2562 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2563 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2564 DRM_DEBUG_KMS("FDI train 2 done.\n");
2565 break;
2566 }
2567 }
2568 if (i == 4)
5eddb70b 2569 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2570
2571 DRM_DEBUG_KMS("FDI train done.\n");
2572}
2573
357555c0
JB		 2574/* Manual link training for Ivy Bridge A0 parts */
2575static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2576{
2577 struct drm_device *dev = crtc->dev;
2578 struct drm_i915_private *dev_priv = dev->dev_private;
2579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2580 int pipe = intel_crtc->pipe;
2581 u32 reg, temp, i;
2582
2583 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2584 for train result */
2585 reg = FDI_RX_IMR(pipe);
2586 temp = I915_READ(reg);
2587 temp &= ~FDI_RX_SYMBOL_LOCK;
2588 temp &= ~FDI_RX_BIT_LOCK;
2589 I915_WRITE(reg, temp);
2590
2591 POSTING_READ(reg);
2592 udelay(150);
2593
2594 /* enable CPU FDI TX and PCH FDI RX */
2595 reg = FDI_TX_CTL(pipe);
2596 temp = I915_READ(reg);
2597 temp &= ~(7 << 19);
2598 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2599 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2600 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2601 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2602 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2603 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2604
2605 reg = FDI_RX_CTL(pipe);
2606 temp = I915_READ(reg);
2607 temp &= ~FDI_LINK_TRAIN_AUTO;
2608 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2609 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2610 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2611
2612 POSTING_READ(reg);
2613 udelay(150);
2614
291427f5
JB		 2615 if (HAS_PCH_CPT(dev))
2616 cpt_phase_pointer_enable(dev, pipe);
2617
357555c0
JB		 2618 for (i = 0; i < 4; i++ ) {
2619 reg = FDI_TX_CTL(pipe);
2620 temp = I915_READ(reg);
2621 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2622 temp |= snb_b_fdi_train_param[i];
2623 I915_WRITE(reg, temp);
2624
2625 POSTING_READ(reg);
2626 udelay(500);
2627
2628 reg = FDI_RX_IIR(pipe);
2629 temp = I915_READ(reg);
2630 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2631
2632 if (temp & FDI_RX_BIT_LOCK ||
2633 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2634 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2635 DRM_DEBUG_KMS("FDI train 1 done.\n");
2636 break;
2637 }
2638 }
2639 if (i == 4)
2640 DRM_ERROR("FDI train 1 fail!\n");
2641
2642 /* Train 2 */
2643 reg = FDI_TX_CTL(pipe);
2644 temp = I915_READ(reg);
2645 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2646 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2647 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2648 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2649 I915_WRITE(reg, temp);
2650
2651 reg = FDI_RX_CTL(pipe);
2652 temp = I915_READ(reg);
2653 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2654 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2655 I915_WRITE(reg, temp);
2656
2657 POSTING_READ(reg);
2658 udelay(150);
2659
2660 for (i = 0; i < 4; i++ ) {
2661 reg = FDI_TX_CTL(pipe);
2662 temp = I915_READ(reg);
2663 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2664 temp |= snb_b_fdi_train_param[i];
2665 I915_WRITE(reg, temp);
2666
2667 POSTING_READ(reg);
2668 udelay(500);
2669
2670 reg = FDI_RX_IIR(pipe);
2671 temp = I915_READ(reg);
2672 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2673
2674 if (temp & FDI_RX_SYMBOL_LOCK) {
2675 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2676 DRM_DEBUG_KMS("FDI train 2 done.\n");
2677 break;
2678 }
2679 }
2680 if (i == 4)
2681 DRM_ERROR("FDI train 2 fail!\n");
2682
2683 DRM_DEBUG_KMS("FDI train done.\n");
2684}
2685
2686static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2687{
2688 struct drm_device *dev = crtc->dev;
2689 struct drm_i915_private *dev_priv = dev->dev_private;
2690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2691 int pipe = intel_crtc->pipe;
5eddb70b 2692 u32 reg, temp;
79e53945 2693
c64e311e 2694 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2695 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2696 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2697
c98e9dcf 2698 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2699 reg = FDI_RX_CTL(pipe);
2700 temp = I915_READ(reg);
2701 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2702 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2703 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2704 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2705
2706 POSTING_READ(reg);
c98e9dcf
JB		 2707 udelay(200);
2708
2709 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2710 temp = I915_READ(reg);
2711 I915_WRITE(reg, temp | FDI_PCDCLK);
2712
2713 POSTING_READ(reg);
c98e9dcf
JB		 2714 udelay(200);
2715
2716 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2717 reg = FDI_TX_CTL(pipe);
2718 temp = I915_READ(reg);
c98e9dcf 2719 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2720 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2721
2722 POSTING_READ(reg);
c98e9dcf 2723 udelay(100);
6be4a607 2724 }
0e23b99d
JB		 2725}
2726
291427f5
JB		 2727static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2728{
2729 struct drm_i915_private *dev_priv = dev->dev_private;
2730 u32 flags = I915_READ(SOUTH_CHICKEN1);
2731
2732 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2733 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2734 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2735 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2736 POSTING_READ(SOUTH_CHICKEN1);
2737}
0fc932b8
JB		 2738static void ironlake_fdi_disable(struct drm_crtc *crtc)
2739{
2740 struct drm_device *dev = crtc->dev;
2741 struct drm_i915_private *dev_priv = dev->dev_private;
2742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2743 int pipe = intel_crtc->pipe;
2744 u32 reg, temp;
2745
2746 /* disable CPU FDI tx and PCH FDI rx */
2747 reg = FDI_TX_CTL(pipe);
2748 temp = I915_READ(reg);
2749 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2750 POSTING_READ(reg);
2751
2752 reg = FDI_RX_CTL(pipe);
2753 temp = I915_READ(reg);
2754 temp &= ~(0x7 << 16);
2755 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2756 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2757
2758 POSTING_READ(reg);
2759 udelay(100);
2760
2761 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2762 if (HAS_PCH_IBX(dev)) {
2763 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2764 I915_WRITE(FDI_RX_CHICKEN(pipe),
2765 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2766 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2767 } else if (HAS_PCH_CPT(dev)) {
2768 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2769 }
0fc932b8
JB		 2770
2771 /* still set train pattern 1 */
2772 reg = FDI_TX_CTL(pipe);
2773 temp = I915_READ(reg);
2774 temp &= ~FDI_LINK_TRAIN_NONE;
2775 temp |= FDI_LINK_TRAIN_PATTERN_1;
2776 I915_WRITE(reg, temp);
2777
2778 reg = FDI_RX_CTL(pipe);
2779 temp = I915_READ(reg);
2780 if (HAS_PCH_CPT(dev)) {
2781 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2782 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2783 } else {
2784 temp &= ~FDI_LINK_TRAIN_NONE;
2785 temp |= FDI_LINK_TRAIN_PATTERN_1;
2786 }
2787 /* BPC in FDI rx is consistent with that in PIPECONF */
2788 temp &= ~(0x07 << 16);
2789 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2790 I915_WRITE(reg, temp);
2791
2792 POSTING_READ(reg);
2793 udelay(100);
2794}
2795
6b383a7f
CW		 2796/*
2797 * When we disable a pipe, we need to clear any pending scanline wait events
2798 * to avoid hanging the ring, which we assume we are waiting on.
2799 */
2800static void intel_clear_scanline_wait(struct drm_device *dev)
2801{
2802 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 2803 struct intel_ring_buffer *ring;
6b383a7f
CW		 2804 u32 tmp;
2805
2806 if (IS_GEN2(dev))
2807 /* Can't break the hang on i8xx */
2808 return;
2809
1ec14ad3 2810 ring = LP_RING(dev_priv);
8168bd48
CW		 2811 tmp = I915_READ_CTL(ring);
2812 if (tmp & RING_WAIT)
2813 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 2814}
2815
e6c3a2a6
CW		 2816static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2817{
05394f39 2818 struct drm_i915_gem_object *obj;
e6c3a2a6
CW		 2819 struct drm_i915_private *dev_priv;
2820
2821 if (crtc->fb == NULL)
2822 return;
2823
05394f39 2824 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW		 2825 dev_priv = crtc->dev->dev_private;
2826 wait_event(dev_priv->pending_flip_queue,
05394f39 2827 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW		 2828}
2829
040484af
JB		 2830static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2831{
2832 struct drm_device *dev = crtc->dev;
2833 struct drm_mode_config *mode_config = &dev->mode_config;
2834 struct intel_encoder *encoder;
2835
2836 /*
2837 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2838 * must be driven by its own crtc; no sharing is possible.
2839 */
2840 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2841 if (encoder->base.crtc != crtc)
2842 continue;
2843
2844 switch (encoder->type) {
2845 case INTEL_OUTPUT_EDP:
2846 if (!intel_encoder_is_pch_edp(&encoder->base))
2847 return false;
2848 continue;
2849 }
2850 }
2851
2852 return true;
2853}
2854
f67a559d
JB		 2855/*
2856 * Enable PCH resources required for PCH ports:
2857 * - PCH PLLs
2858 * - FDI training & RX/TX
2859 * - update transcoder timings
2860 * - DP transcoding bits
2861 * - transcoder
2862 */
2863static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2864{
2865 struct drm_device *dev = crtc->dev;
2866 struct drm_i915_private *dev_priv = dev->dev_private;
2867 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2868 int pipe = intel_crtc->pipe;
5eddb70b 2869 u32 reg, temp;
2c07245f 2870
c98e9dcf 2871 /* For PCH output, training FDI link */
674cf967 2872 dev_priv->display.fdi_link_train(crtc);
2c07245f 2873
92f2584a 2874 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 2875
c98e9dcf
JB		 2876 if (HAS_PCH_CPT(dev)) {
2877 /* Be sure PCH DPLL SEL is set */
2878 temp = I915_READ(PCH_DPLL_SEL);
5eddb70b 2879 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
c98e9dcf 2880 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
5eddb70b 2881 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
c98e9dcf
JB		 2882 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2883 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2884 }
5eddb70b 2885
d9b6cb56
JB		 2886 /* set transcoder timing, panel must allow it */
2887 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2888 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2889 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2890 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2891
5eddb70b
CW		 2892 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2893 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2894 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
8db9d77b 2895
5e84e1a4
ZW		 2896 intel_fdi_normal_train(crtc);
2897
c98e9dcf
JB		 2898 /* For PCH DP, enable TRANS_DP_CTL */
2899 if (HAS_PCH_CPT(dev) &&
2900 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
9325c9f0 2901 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 2902 reg = TRANS_DP_CTL(pipe);
2903 temp = I915_READ(reg);
2904 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2905 TRANS_DP_SYNC_MASK |
2906 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2907 temp |= (TRANS_DP_OUTPUT_ENABLE |
2908 TRANS_DP_ENH_FRAMING);
9325c9f0 2909 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2910
2911 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2912 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2913 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2914 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2915
2916 switch (intel_trans_dp_port_sel(crtc)) {
2917 case PCH_DP_B:
5eddb70b 2918 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2919 break;
2920 case PCH_DP_C:
5eddb70b 2921 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2922 break;
2923 case PCH_DP_D:
5eddb70b 2924 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2925 break;
2926 default:
2927 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2928 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2929 break;
32f9d658 2930 }
2c07245f 2931
5eddb70b 2932 I915_WRITE(reg, temp);
6be4a607 2933 }
b52eb4dc 2934
040484af 2935 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2936}
2937
2938static void ironlake_crtc_enable(struct drm_crtc *crtc)
2939{
2940 struct drm_device *dev = crtc->dev;
2941 struct drm_i915_private *dev_priv = dev->dev_private;
2942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2943 int pipe = intel_crtc->pipe;
2944 int plane = intel_crtc->plane;
2945 u32 temp;
2946 bool is_pch_port;
2947
2948 if (intel_crtc->active)
2949 return;
2950
2951 intel_crtc->active = true;
2952 intel_update_watermarks(dev);
2953
2954 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2955 temp = I915_READ(PCH_LVDS);
2956 if ((temp & LVDS_PORT_EN) == 0)
2957 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2958 }
2959
2960 is_pch_port = intel_crtc_driving_pch(crtc);
2961
2962 if (is_pch_port)
357555c0 2963 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 2964 else
2965 ironlake_fdi_disable(crtc);
2966
2967 /* Enable panel fitting for LVDS */
2968 if (dev_priv->pch_pf_size &&
2969 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2970 /* Force use of hard-coded filter coefficients
2971 * as some pre-programmed values are broken,
2972 * e.g. x201.
2973 */
9db4a9c7
JB		 2974 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2975 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2976 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 2977 }
2978
9c54c0dd
JB		 2979 /*
2980 * On ILK+ LUT must be loaded before the pipe is running but with
2981 * clocks enabled
2982 */
2983 intel_crtc_load_lut(crtc);
2984
f67a559d
JB		 2985 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2986 intel_enable_plane(dev_priv, plane, pipe);
2987
2988 if (is_pch_port)
2989 ironlake_pch_enable(crtc);
c98e9dcf 2990
d1ebd816 2991 mutex_lock(&dev->struct_mutex);
bed4a673 2992 intel_update_fbc(dev);
d1ebd816
BW		 2993 mutex_unlock(&dev->struct_mutex);
2994
6b383a7f 2995 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 2996}
2997
2998static void ironlake_crtc_disable(struct drm_crtc *crtc)
2999{
3000 struct drm_device *dev = crtc->dev;
3001 struct drm_i915_private *dev_priv = dev->dev_private;
3002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3003 int pipe = intel_crtc->pipe;
3004 int plane = intel_crtc->plane;
5eddb70b 3005 u32 reg, temp;
b52eb4dc 3006
f7abfe8b
CW		 3007 if (!intel_crtc->active)
3008 return;
3009
e6c3a2a6 3010 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3011 drm_vblank_off(dev, pipe);
6b383a7f 3012 intel_crtc_update_cursor(crtc, false);
5eddb70b 3013
b24e7179 3014 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3015
973d04f9
CW		 3016 if (dev_priv->cfb_plane == plane)
3017 intel_disable_fbc(dev);
2c07245f 3018
b24e7179 3019 intel_disable_pipe(dev_priv, pipe);
32f9d658 3020
6be4a607 3021 /* Disable PF */
9db4a9c7
JB		 3022 I915_WRITE(PF_CTL(pipe), 0);
3023 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3024
0fc932b8 3025 ironlake_fdi_disable(crtc);
2c07245f 3026
47a05eca
JB		 3027 /* This is a horrible layering violation; we should be doing this in
3028 * the connector/encoder ->prepare instead, but we don't always have
3029 * enough information there about the config to know whether it will
3030 * actually be necessary or just cause undesired flicker.
3031 */
3032 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 3033
040484af 3034 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3035
6be4a607
JB		 3036 if (HAS_PCH_CPT(dev)) {
3037 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3038 reg = TRANS_DP_CTL(pipe);
3039 temp = I915_READ(reg);
3040 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3041 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3042 I915_WRITE(reg, temp);
6be4a607
JB		 3043
3044 /* disable DPLL_SEL */
3045 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3046 switch (pipe) {
3047 case 0:
3048 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3049 break;
3050 case 1:
6be4a607 3051 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3052 break;
3053 case 2:
3054 /* FIXME: manage transcoder PLLs? */
3055 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3056 break;
3057 default:
3058 BUG(); /* wtf */
3059 }
6be4a607 3060 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3061 }
e3421a18 3062
6be4a607 3063 /* disable PCH DPLL */
92f2584a 3064 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 3065
6be4a607 3066 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 3067 reg = FDI_RX_CTL(pipe);
3068 temp = I915_READ(reg);
3069 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 3070
6be4a607 3071 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 3072 reg = FDI_TX_CTL(pipe);
3073 temp = I915_READ(reg);
3074 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3075
3076 POSTING_READ(reg);
6be4a607 3077 udelay(100);
8db9d77b 3078
5eddb70b
CW		 3079 reg = FDI_RX_CTL(pipe);
3080 temp = I915_READ(reg);
3081 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 3082
6be4a607 3083 /* Wait for the clocks to turn off. */
5eddb70b 3084 POSTING_READ(reg);
6be4a607 3085 udelay(100);
6b383a7f 3086
f7abfe8b 3087 intel_crtc->active = false;
6b383a7f 3088 intel_update_watermarks(dev);
d1ebd816
BW		 3089
3090 mutex_lock(&dev->struct_mutex);
6b383a7f
CW		 3091 intel_update_fbc(dev);
3092 intel_clear_scanline_wait(dev);
d1ebd816 3093 mutex_unlock(&dev->struct_mutex);
6be4a607 3094}
1b3c7a47 3095
6be4a607
JB		 3096static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3097{
3098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3099 int pipe = intel_crtc->pipe;
3100 int plane = intel_crtc->plane;
8db9d77b 3101
6be4a607
JB		 3102 /* XXX: When our outputs are all unaware of DPMS modes other than off
3103 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3104 */
3105 switch (mode) {
3106 case DRM_MODE_DPMS_ON:
3107 case DRM_MODE_DPMS_STANDBY:
3108 case DRM_MODE_DPMS_SUSPEND:
3109 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3110 ironlake_crtc_enable(crtc);
3111 break;
1b3c7a47 3112
6be4a607
JB		 3113 case DRM_MODE_DPMS_OFF:
3114 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3115 ironlake_crtc_disable(crtc);
2c07245f
ZW		 3116 break;
3117 }
3118}
3119
02e792fb
DV		 3120static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3121{
02e792fb 3122 if (!enable && intel_crtc->overlay) {
23f09ce3 3123 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3124 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3125
23f09ce3 3126 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3127 dev_priv->mm.interruptible = false;
3128 (void) intel_overlay_switch_off(intel_crtc->overlay);
3129 dev_priv->mm.interruptible = true;
23f09ce3 3130 mutex_unlock(&dev->struct_mutex);
02e792fb 3131 }
02e792fb 3132
5dcdbcb0
CW		 3133 /* Let userspace switch the overlay on again. In most cases userspace
3134 * has to recompute where to put it anyway.
3135 */
02e792fb
DV		 3136}
3137
0b8765c6 3138static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3139{
3140 struct drm_device *dev = crtc->dev;
79e53945
JB		 3141 struct drm_i915_private *dev_priv = dev->dev_private;
3142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3143 int pipe = intel_crtc->pipe;
80824003 3144 int plane = intel_crtc->plane;
79e53945 3145
f7abfe8b
CW		 3146 if (intel_crtc->active)
3147 return;
3148
3149 intel_crtc->active = true;
6b383a7f
CW		 3150 intel_update_watermarks(dev);
3151
63d7bbe9 3152 intel_enable_pll(dev_priv, pipe);
040484af 3153 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3154 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3155
0b8765c6 3156 intel_crtc_load_lut(crtc);
bed4a673 3157 intel_update_fbc(dev);
79e53945 3158
0b8765c6
JB		 3159 /* Give the overlay scaler a chance to enable if it's on this pipe */
3160 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3161 intel_crtc_update_cursor(crtc, true);
0b8765c6 3162}
79e53945 3163
0b8765c6
JB		 3164static void i9xx_crtc_disable(struct drm_crtc *crtc)
3165{
3166 struct drm_device *dev = crtc->dev;
3167 struct drm_i915_private *dev_priv = dev->dev_private;
3168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3169 int pipe = intel_crtc->pipe;
3170 int plane = intel_crtc->plane;
b690e96c 3171
f7abfe8b
CW		 3172 if (!intel_crtc->active)
3173 return;
3174
0b8765c6 3175 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3176 intel_crtc_wait_for_pending_flips(crtc);
3177 drm_vblank_off(dev, pipe);
0b8765c6 3178 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3179 intel_crtc_update_cursor(crtc, false);
0b8765c6 3180
973d04f9
CW		 3181 if (dev_priv->cfb_plane == plane)
3182 intel_disable_fbc(dev);
79e53945 3183
b24e7179 3184 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3185 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3186 intel_disable_pll(dev_priv, pipe);
0b8765c6 3187
f7abfe8b 3188 intel_crtc->active = false;
6b383a7f
CW		 3189 intel_update_fbc(dev);
3190 intel_update_watermarks(dev);
3191 intel_clear_scanline_wait(dev);
0b8765c6
JB		 3192}
3193
3194static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3195{
3196 /* XXX: When our outputs are all unaware of DPMS modes other than off
3197 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3198 */
3199 switch (mode) {
3200 case DRM_MODE_DPMS_ON:
3201 case DRM_MODE_DPMS_STANDBY:
3202 case DRM_MODE_DPMS_SUSPEND:
3203 i9xx_crtc_enable(crtc);
3204 break;
3205 case DRM_MODE_DPMS_OFF:
3206 i9xx_crtc_disable(crtc);
79e53945
JB		 3207 break;
3208 }
2c07245f
ZW		 3209}
3210
3211/**
3212 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3213 */
3214static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3215{
3216 struct drm_device *dev = crtc->dev;
e70236a8 3217 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3218 struct drm_i915_master_private *master_priv;
3219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3220 int pipe = intel_crtc->pipe;
3221 bool enabled;
3222
032d2a0d
CW		 3223 if (intel_crtc->dpms_mode == mode)
3224 return;
3225
65655d4a 3226 intel_crtc->dpms_mode = mode;
debcaddc 3227
e70236a8 3228 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3229
3230 if (!dev->primary->master)
3231 return;
3232
3233 master_priv = dev->primary->master->driver_priv;
3234 if (!master_priv->sarea_priv)
3235 return;
3236
3237 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3238
3239 switch (pipe) {
3240 case 0:
3241 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3242 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3243 break;
3244 case 1:
3245 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3246 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3247 break;
3248 default:
9db4a9c7 3249 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3250 break;
3251 }
79e53945
JB		 3252}
3253
cdd59983
CW		 3254static void intel_crtc_disable(struct drm_crtc *crtc)
3255{
3256 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3257 struct drm_device *dev = crtc->dev;
3258
3259 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3260
3261 if (crtc->fb) {
3262 mutex_lock(&dev->struct_mutex);
3263 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3264 mutex_unlock(&dev->struct_mutex);
3265 }
3266}
3267
7e7d76c3
JB		 3268/* Prepare for a mode set.
3269 *
3270 * Note we could be a lot smarter here. We need to figure out which outputs
3271 * will be enabled, which disabled (in short, how the config will changes)
3272 * and perform the minimum necessary steps to accomplish that, e.g. updating
3273 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3274 * panel fitting is in the proper state, etc.
3275 */
3276static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3277{
7e7d76c3 3278 i9xx_crtc_disable(crtc);
79e53945
JB		 3279}
3280
7e7d76c3 3281static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3282{
7e7d76c3 3283 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3284}
3285
3286static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3287{
7e7d76c3 3288 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3289}
3290
3291static void ironlake_crtc_commit(struct drm_crtc *crtc)
3292{
7e7d76c3 3293 ironlake_crtc_enable(crtc);
79e53945
JB		 3294}
3295
3296void intel_encoder_prepare (struct drm_encoder *encoder)
3297{
3298 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3299 /* lvds has its own version of prepare see intel_lvds_prepare */
3300 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3301}
3302
3303void intel_encoder_commit (struct drm_encoder *encoder)
3304{
3305 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3306 /* lvds has its own version of commit see intel_lvds_commit */
3307 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3308}
3309
ea5b213a
CW		 3310void intel_encoder_destroy(struct drm_encoder *encoder)
3311{
4ef69c7a 3312 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3313
ea5b213a
CW		 3314 drm_encoder_cleanup(encoder);
3315 kfree(intel_encoder);
3316}
3317
79e53945
JB		 3318static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3319 struct drm_display_mode *mode,
3320 struct drm_display_mode *adjusted_mode)
3321{
2c07245f 3322 struct drm_device *dev = crtc->dev;
89749350 3323
bad720ff 3324 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3325 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3326 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3327 return false;
2c07245f 3328 }
89749350
CW		 3329
3330 /* XXX some encoders set the crtcinfo, others don't.
3331 * Obviously we need some form of conflict resolution here...
3332 */
3333 if (adjusted_mode->crtc_htotal == 0)
3334 drm_mode_set_crtcinfo(adjusted_mode, 0);
3335
79e53945
JB		 3336 return true;
3337}
3338
e70236a8
JB		 3339static int i945_get_display_clock_speed(struct drm_device *dev)
3340{
3341 return 400000;
3342}
79e53945 3343
e70236a8 3344static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3345{
e70236a8
JB		 3346 return 333000;
3347}
79e53945 3348
e70236a8
JB		 3349static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3350{
3351 return 200000;
3352}
79e53945 3353
e70236a8
JB		 3354static int i915gm_get_display_clock_speed(struct drm_device *dev)
3355{
3356 u16 gcfgc = 0;
79e53945 3357
e70236a8
JB		 3358 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3359
3360 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3361 return 133000;
3362 else {
3363 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3364 case GC_DISPLAY_CLOCK_333_MHZ:
3365 return 333000;
3366 default:
3367 case GC_DISPLAY_CLOCK_190_200_MHZ:
3368 return 190000;
79e53945 3369 }
e70236a8
JB		 3370 }
3371}
3372
3373static int i865_get_display_clock_speed(struct drm_device *dev)
3374{
3375 return 266000;
3376}
3377
3378static int i855_get_display_clock_speed(struct drm_device *dev)
3379{
3380 u16 hpllcc = 0;
3381 /* Assume that the hardware is in the high speed state. This
3382 * should be the default.
3383 */
3384 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3385 case GC_CLOCK_133_200:
3386 case GC_CLOCK_100_200:
3387 return 200000;
3388 case GC_CLOCK_166_250:
3389 return 250000;
3390 case GC_CLOCK_100_133:
79e53945 3391 return 133000;
e70236a8 3392 }
79e53945 3393
e70236a8
JB		 3394 /* Shouldn't happen */
3395 return 0;
3396}
79e53945 3397
e70236a8
JB		 3398static int i830_get_display_clock_speed(struct drm_device *dev)
3399{
3400 return 133000;
79e53945
JB		 3401}
3402
2c07245f
ZW		 3403struct fdi_m_n {
3404 u32 tu;
3405 u32 gmch_m;
3406 u32 gmch_n;
3407 u32 link_m;
3408 u32 link_n;
3409};
3410
3411static void
3412fdi_reduce_ratio(u32 *num, u32 *den)
3413{
3414 while (*num > 0xffffff || *den > 0xffffff) {
3415 *num >>= 1;
3416 *den >>= 1;
3417 }
3418}
3419
2c07245f 3420static void
f2b115e6
AJ		 3421ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3422 int link_clock, struct fdi_m_n *m_n)
2c07245f 3423{
2c07245f
ZW		 3424 m_n->tu = 64; /* default size */
3425
22ed1113
CW		 3426 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3427 m_n->gmch_m = bits_per_pixel * pixel_clock;
3428 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3429 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3430
22ed1113
CW		 3431 m_n->link_m = pixel_clock;
3432 m_n->link_n = link_clock;
2c07245f
ZW		 3433 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3434}
3435
3436
7662c8bd
SL		 3437struct intel_watermark_params {
3438 unsigned long fifo_size;
3439 unsigned long max_wm;
3440 unsigned long default_wm;
3441 unsigned long guard_size;
3442 unsigned long cacheline_size;
3443};
3444
f2b115e6 3445/* Pineview has different values for various configs */
d210246a 3446static const struct intel_watermark_params pineview_display_wm = {
f2b115e6
AJ		 3447 PINEVIEW_DISPLAY_FIFO,
3448 PINEVIEW_MAX_WM,
3449 PINEVIEW_DFT_WM,
3450 PINEVIEW_GUARD_WM,
3451 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3452};
d210246a 3453static const struct intel_watermark_params pineview_display_hplloff_wm = {
f2b115e6
AJ		 3454 PINEVIEW_DISPLAY_FIFO,
3455 PINEVIEW_MAX_WM,
3456 PINEVIEW_DFT_HPLLOFF_WM,
3457 PINEVIEW_GUARD_WM,
3458 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3459};
d210246a 3460static const struct intel_watermark_params pineview_cursor_wm = {
f2b115e6
AJ		 3461 PINEVIEW_CURSOR_FIFO,
3462 PINEVIEW_CURSOR_MAX_WM,
3463 PINEVIEW_CURSOR_DFT_WM,
3464 PINEVIEW_CURSOR_GUARD_WM,
3465 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 3466};
d210246a 3467static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
f2b115e6
AJ		 3468 PINEVIEW_CURSOR_FIFO,
3469 PINEVIEW_CURSOR_MAX_WM,
3470 PINEVIEW_CURSOR_DFT_WM,
3471 PINEVIEW_CURSOR_GUARD_WM,
3472 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3473};
d210246a 3474static const struct intel_watermark_params g4x_wm_info = {
0e442c60
JB		 3475 G4X_FIFO_SIZE,
3476 G4X_MAX_WM,
3477 G4X_MAX_WM,
3478 2,
3479 G4X_FIFO_LINE_SIZE,
3480};
d210246a 3481static const struct intel_watermark_params g4x_cursor_wm_info = {
4fe5e611
ZY		 3482 I965_CURSOR_FIFO,
3483 I965_CURSOR_MAX_WM,
3484 I965_CURSOR_DFT_WM,
3485 2,
3486 G4X_FIFO_LINE_SIZE,
3487};
d210246a 3488static const struct intel_watermark_params i965_cursor_wm_info = {
4fe5e611
ZY		 3489 I965_CURSOR_FIFO,
3490 I965_CURSOR_MAX_WM,
3491 I965_CURSOR_DFT_WM,
3492 2,
3493 I915_FIFO_LINE_SIZE,
3494};
d210246a 3495static const struct intel_watermark_params i945_wm_info = {
dff33cfc 3496 I945_FIFO_SIZE,
7662c8bd
SL		 3497 I915_MAX_WM,
3498 1,
dff33cfc
JB		 3499 2,
3500 I915_FIFO_LINE_SIZE
7662c8bd 3501};
d210246a 3502static const struct intel_watermark_params i915_wm_info = {
dff33cfc 3503 I915_FIFO_SIZE,
7662c8bd
SL		 3504 I915_MAX_WM,
3505 1,
dff33cfc 3506 2,
7662c8bd
SL		 3507 I915_FIFO_LINE_SIZE
3508};
d210246a 3509static const struct intel_watermark_params i855_wm_info = {
7662c8bd
SL		 3510 I855GM_FIFO_SIZE,
3511 I915_MAX_WM,
3512 1,
dff33cfc 3513 2,
7662c8bd
SL		 3514 I830_FIFO_LINE_SIZE
3515};
d210246a 3516static const struct intel_watermark_params i830_wm_info = {
7662c8bd
SL		 3517 I830_FIFO_SIZE,
3518 I915_MAX_WM,
3519 1,
dff33cfc 3520 2,
7662c8bd
SL		 3521 I830_FIFO_LINE_SIZE
3522};
3523
d210246a 3524static const struct intel_watermark_params ironlake_display_wm_info = {
7f8a8569
ZW		 3525 ILK_DISPLAY_FIFO,
3526 ILK_DISPLAY_MAXWM,
3527 ILK_DISPLAY_DFTWM,
3528 2,
3529 ILK_FIFO_LINE_SIZE
3530};
d210246a 3531static const struct intel_watermark_params ironlake_cursor_wm_info = {
c936f44d
ZY		 3532 ILK_CURSOR_FIFO,
3533 ILK_CURSOR_MAXWM,
3534 ILK_CURSOR_DFTWM,
3535 2,
3536 ILK_FIFO_LINE_SIZE
3537};
d210246a 3538static const struct intel_watermark_params ironlake_display_srwm_info = {
7f8a8569
ZW		 3539 ILK_DISPLAY_SR_FIFO,
3540 ILK_DISPLAY_MAX_SRWM,
3541 ILK_DISPLAY_DFT_SRWM,
3542 2,
3543 ILK_FIFO_LINE_SIZE
3544};
d210246a 3545static const struct intel_watermark_params ironlake_cursor_srwm_info = {
7f8a8569
ZW		 3546 ILK_CURSOR_SR_FIFO,
3547 ILK_CURSOR_MAX_SRWM,
3548 ILK_CURSOR_DFT_SRWM,
3549 2,
3550 ILK_FIFO_LINE_SIZE
3551};
3552
d210246a 3553static const struct intel_watermark_params sandybridge_display_wm_info = {
1398261a
YL		 3554 SNB_DISPLAY_FIFO,
3555 SNB_DISPLAY_MAXWM,
3556 SNB_DISPLAY_DFTWM,
3557 2,
3558 SNB_FIFO_LINE_SIZE
3559};
d210246a 3560static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1398261a
YL		 3561 SNB_CURSOR_FIFO,
3562 SNB_CURSOR_MAXWM,
3563 SNB_CURSOR_DFTWM,
3564 2,
3565 SNB_FIFO_LINE_SIZE
3566};
d210246a 3567static const struct intel_watermark_params sandybridge_display_srwm_info = {
1398261a
YL		 3568 SNB_DISPLAY_SR_FIFO,
3569 SNB_DISPLAY_MAX_SRWM,
3570 SNB_DISPLAY_DFT_SRWM,
3571 2,
3572 SNB_FIFO_LINE_SIZE
3573};
d210246a 3574static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1398261a
YL		 3575 SNB_CURSOR_SR_FIFO,
3576 SNB_CURSOR_MAX_SRWM,
3577 SNB_CURSOR_DFT_SRWM,
3578 2,
3579 SNB_FIFO_LINE_SIZE
3580};
3581
3582
dff33cfc
JB		 3583/**
3584 * intel_calculate_wm - calculate watermark level
3585 * @clock_in_khz: pixel clock
3586 * @wm: chip FIFO params
3587 * @pixel_size: display pixel size
3588 * @latency_ns: memory latency for the platform
3589 *
3590 * Calculate the watermark level (the level at which the display plane will
3591 * start fetching from memory again). Each chip has a different display
3592 * FIFO size and allocation, so the caller needs to figure that out and pass
3593 * in the correct intel_watermark_params structure.
3594 *
3595 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3596 * on the pixel size. When it reaches the watermark level, it'll start
3597 * fetching FIFO line sized based chunks from memory until the FIFO fills
3598 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3599 * will occur, and a display engine hang could result.
3600 */
7662c8bd 3601static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
d210246a
CW		 3602 const struct intel_watermark_params *wm,
3603 int fifo_size,
7662c8bd
SL		 3604 int pixel_size,
3605 unsigned long latency_ns)
3606{
390c4dd4 3607 long entries_required, wm_size;
dff33cfc 3608
d660467c
JB		 3609 /*
3610 * Note: we need to make sure we don't overflow for various clock &
3611 * latency values.
3612 * clocks go from a few thousand to several hundred thousand.
3613 * latency is usually a few thousand
3614 */
3615 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3616 1000;
8de9b311 3617 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 3618
bbb0aef5 3619 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
dff33cfc 3620
d210246a 3621 wm_size = fifo_size - (entries_required + wm->guard_size);
dff33cfc 3622
bbb0aef5 3623 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
7662c8bd 3624
390c4dd4
JB		 3625 /* Don't promote wm_size to unsigned... */
3626 if (wm_size > (long)wm->max_wm)
7662c8bd 3627 wm_size = wm->max_wm;
c3add4b6 3628 if (wm_size <= 0)
7662c8bd
SL		 3629 wm_size = wm->default_wm;
3630 return wm_size;
3631}
3632
3633struct cxsr_latency {
3634 int is_desktop;
95534263 3635 int is_ddr3;
7662c8bd
SL		 3636 unsigned long fsb_freq;
3637 unsigned long mem_freq;
3638 unsigned long display_sr;
3639 unsigned long display_hpll_disable;
3640 unsigned long cursor_sr;
3641 unsigned long cursor_hpll_disable;
3642};
3643
403c89ff 3644static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP		 3645 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3646 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3647 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3648 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3649 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3650
3651 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3652 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3653 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3654 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3655 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3656
3657 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3658 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3659 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3660 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3661 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3662
3663 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3664 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3665 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3666 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3667 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3668
3669 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3670 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3671 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3672 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3673 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3674
3675 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3676 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3677 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3678 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3679 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL		 3680};
3681
403c89ff
CW		 3682static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3683 int is_ddr3,
3684 int fsb,
3685 int mem)
7662c8bd 3686{
403c89ff 3687 const struct cxsr_latency *latency;
7662c8bd 3688 int i;
7662c8bd
SL		 3689
3690 if (fsb == 0 || mem == 0)
3691 return NULL;
3692
3693 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3694 latency = &cxsr_latency_table[i];
3695 if (is_desktop == latency->is_desktop &&
95534263 3696 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR		 3697 fsb == latency->fsb_freq && mem == latency->mem_freq)
3698 return latency;
7662c8bd 3699 }
decbbcda 3700
28c97730 3701 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR		 3702
3703 return NULL;
7662c8bd
SL		 3704}
3705
f2b115e6 3706static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL		 3707{
3708 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL		 3709
3710 /* deactivate cxsr */
3e33d94d 3711 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL		 3712}
3713
bcc24fb4
JB		 3714/*
3715 * Latency for FIFO fetches is dependent on several factors:
3716 * - memory configuration (speed, channels)
3717 * - chipset
3718 * - current MCH state
3719 * It can be fairly high in some situations, so here we assume a fairly
3720 * pessimal value. It's a tradeoff between extra memory fetches (if we
3721 * set this value too high, the FIFO will fetch frequently to stay full)
3722 * and power consumption (set it too low to save power and we might see
3723 * FIFO underruns and display "flicker").
3724 *
3725 * A value of 5us seems to be a good balance; safe for very low end
3726 * platforms but not overly aggressive on lower latency configs.
3727 */
69e302a9 3728static const int latency_ns = 5000;
7662c8bd 3729
e70236a8 3730static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB		 3731{
3732 struct drm_i915_private *dev_priv = dev->dev_private;
3733 uint32_t dsparb = I915_READ(DSPARB);
3734 int size;
3735
8de9b311
CW		 3736 size = dsparb & 0x7f;
3737 if (plane)
3738 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 3739
28c97730 3740 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3741 plane ? "B" : "A", size);
dff33cfc
JB		 3742
3743 return size;
3744}
7662c8bd 3745
e70236a8
JB		 3746static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3747{
3748 struct drm_i915_private *dev_priv = dev->dev_private;
3749 uint32_t dsparb = I915_READ(DSPARB);
3750 int size;
3751
8de9b311
CW		 3752 size = dsparb & 0x1ff;
3753 if (plane)
3754 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 3755 size >>= 1; /* Convert to cachelines */
dff33cfc 3756
28c97730 3757 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3758 plane ? "B" : "A", size);
dff33cfc
JB		 3759
3760 return size;
3761}
7662c8bd 3762
e70236a8
JB		 3763static int i845_get_fifo_size(struct drm_device *dev, int plane)
3764{
3765 struct drm_i915_private *dev_priv = dev->dev_private;
3766 uint32_t dsparb = I915_READ(DSPARB);
3767 int size;
3768
3769 size = dsparb & 0x7f;
3770 size >>= 2; /* Convert to cachelines */
3771
28c97730 3772 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW		 3773 plane ? "B" : "A",
3774 size);
e70236a8
JB		 3775
3776 return size;
3777}
3778
3779static int i830_get_fifo_size(struct drm_device *dev, int plane)
3780{
3781 struct drm_i915_private *dev_priv = dev->dev_private;
3782 uint32_t dsparb = I915_READ(DSPARB);
3783 int size;
3784
3785 size = dsparb & 0x7f;
3786 size >>= 1; /* Convert to cachelines */
3787
28c97730 3788 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3789 plane ? "B" : "A", size);
e70236a8
JB		 3790
3791 return size;
3792}
3793
d210246a
CW		 3794static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3795{
3796 struct drm_crtc *crtc, *enabled = NULL;
3797
3798 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3799 if (crtc->enabled && crtc->fb) {
3800 if (enabled)
3801 return NULL;
3802 enabled = crtc;
3803 }
3804 }
3805
3806 return enabled;
3807}
3808
3809static void pineview_update_wm(struct drm_device *dev)
d4294342
ZY		 3810{
3811 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3812 struct drm_crtc *crtc;
403c89ff 3813 const struct cxsr_latency *latency;
d4294342
ZY		 3814 u32 reg;
3815 unsigned long wm;
d4294342 3816
403c89ff 3817 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 3818 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY		 3819 if (!latency) {
3820 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3821 pineview_disable_cxsr(dev);
3822 return;
3823 }
3824
d210246a
CW		 3825 crtc = single_enabled_crtc(dev);
3826 if (crtc) {
3827 int clock = crtc->mode.clock;
3828 int pixel_size = crtc->fb->bits_per_pixel / 8;
d4294342
ZY		 3829
3830 /* Display SR */
d210246a
CW		 3831 wm = intel_calculate_wm(clock, &pineview_display_wm,
3832 pineview_display_wm.fifo_size,
d4294342
ZY		 3833 pixel_size, latency->display_sr);
3834 reg = I915_READ(DSPFW1);
3835 reg &= ~DSPFW_SR_MASK;
3836 reg |= wm << DSPFW_SR_SHIFT;
3837 I915_WRITE(DSPFW1, reg);
3838 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3839
3840 /* cursor SR */
d210246a
CW		 3841 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3842 pineview_display_wm.fifo_size,
d4294342
ZY		 3843 pixel_size, latency->cursor_sr);
3844 reg = I915_READ(DSPFW3);
3845 reg &= ~DSPFW_CURSOR_SR_MASK;
3846 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3847 I915_WRITE(DSPFW3, reg);
3848
3849 /* Display HPLL off SR */
d210246a
CW		 3850 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3851 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3852 pixel_size, latency->display_hpll_disable);
3853 reg = I915_READ(DSPFW3);
3854 reg &= ~DSPFW_HPLL_SR_MASK;
3855 reg |= wm & DSPFW_HPLL_SR_MASK;
3856 I915_WRITE(DSPFW3, reg);
3857
3858 /* cursor HPLL off SR */
d210246a
CW		 3859 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3860 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3861 pixel_size, latency->cursor_hpll_disable);
3862 reg = I915_READ(DSPFW3);
3863 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3864 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3865 I915_WRITE(DSPFW3, reg);
3866 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3867
3868 /* activate cxsr */
3e33d94d
CW		 3869 I915_WRITE(DSPFW3,
3870 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY		 3871 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3872 } else {
3873 pineview_disable_cxsr(dev);
3874 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3875 }
3876}
3877
417ae147
CW		 3878static bool g4x_compute_wm0(struct drm_device *dev,
3879 int plane,
3880 const struct intel_watermark_params *display,
3881 int display_latency_ns,
3882 const struct intel_watermark_params *cursor,
3883 int cursor_latency_ns,
3884 int *plane_wm,
3885 int *cursor_wm)
3886{
3887 struct drm_crtc *crtc;
3888 int htotal, hdisplay, clock, pixel_size;
3889 int line_time_us, line_count;
3890 int entries, tlb_miss;
3891
3892 crtc = intel_get_crtc_for_plane(dev, plane);
5c72d064
CW		 3893 if (crtc->fb == NULL || !crtc->enabled) {
3894 *cursor_wm = cursor->guard_size;
3895 *plane_wm = display->guard_size;
417ae147 3896 return false;
5c72d064 3897 }
417ae147
CW		 3898
3899 htotal = crtc->mode.htotal;
3900 hdisplay = crtc->mode.hdisplay;
3901 clock = crtc->mode.clock;
3902 pixel_size = crtc->fb->bits_per_pixel / 8;
3903
3904 /* Use the small buffer method to calculate plane watermark */
3905 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3906 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3907 if (tlb_miss > 0)
3908 entries += tlb_miss;
3909 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3910 *plane_wm = entries + display->guard_size;
3911 if (*plane_wm > (int)display->max_wm)
3912 *plane_wm = display->max_wm;
3913
3914 /* Use the large buffer method to calculate cursor watermark */
3915 line_time_us = ((htotal * 1000) / clock);
3916 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3917 entries = line_count * 64 * pixel_size;
3918 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3919 if (tlb_miss > 0)
3920 entries += tlb_miss;
3921 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3922 *cursor_wm = entries + cursor->guard_size;
3923 if (*cursor_wm > (int)cursor->max_wm)
3924 *cursor_wm = (int)cursor->max_wm;
3925
3926 return true;
3927}
3928
3929/*
3930 * Check the wm result.
3931 *
3932 * If any calculated watermark values is larger than the maximum value that
3933 * can be programmed into the associated watermark register, that watermark
3934 * must be disabled.
3935 */
3936static bool g4x_check_srwm(struct drm_device *dev,
3937 int display_wm, int cursor_wm,
3938 const struct intel_watermark_params *display,
3939 const struct intel_watermark_params *cursor)
652c393a 3940{
417ae147
CW		 3941 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3942 display_wm, cursor_wm);
652c393a 3943
417ae147 3944 if (display_wm > display->max_wm) {
bbb0aef5 3945 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 3946 display_wm, display->max_wm);
3947 return false;
3948 }
0e442c60 3949
417ae147 3950 if (cursor_wm > cursor->max_wm) {
bbb0aef5 3951 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 3952 cursor_wm, cursor->max_wm);
3953 return false;
3954 }
0e442c60 3955
417ae147
CW		 3956 if (!(display_wm || cursor_wm)) {
3957 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3958 return false;
3959 }
0e442c60 3960
417ae147
CW		 3961 return true;
3962}
0e442c60 3963
417ae147 3964static bool g4x_compute_srwm(struct drm_device *dev,
d210246a
CW		 3965 int plane,
3966 int latency_ns,
417ae147
CW		 3967 const struct intel_watermark_params *display,
3968 const struct intel_watermark_params *cursor,
3969 int *display_wm, int *cursor_wm)
3970{
d210246a
CW		 3971 struct drm_crtc *crtc;
3972 int hdisplay, htotal, pixel_size, clock;
417ae147
CW		 3973 unsigned long line_time_us;
3974 int line_count, line_size;
3975 int small, large;
3976 int entries;
0e442c60 3977
417ae147
CW		 3978 if (!latency_ns) {
3979 *display_wm = *cursor_wm = 0;
3980 return false;
3981 }
0e442c60 3982
d210246a
CW		 3983 crtc = intel_get_crtc_for_plane(dev, plane);
3984 hdisplay = crtc->mode.hdisplay;
3985 htotal = crtc->mode.htotal;
3986 clock = crtc->mode.clock;
3987 pixel_size = crtc->fb->bits_per_pixel / 8;
3988
417ae147
CW		 3989 line_time_us = (htotal * 1000) / clock;
3990 line_count = (latency_ns / line_time_us + 1000) / 1000;
3991 line_size = hdisplay * pixel_size;
0e442c60 3992
417ae147
CW		 3993 /* Use the minimum of the small and large buffer method for primary */
3994 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3995 large = line_count * line_size;
0e442c60 3996
417ae147
CW		 3997 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3998 *display_wm = entries + display->guard_size;
4fe5e611 3999
417ae147
CW		 4000 /* calculate the self-refresh watermark for display cursor */
4001 entries = line_count * pixel_size * 64;
4002 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4003 *cursor_wm = entries + cursor->guard_size;
4fe5e611 4004
417ae147
CW		 4005 return g4x_check_srwm(dev,
4006 *display_wm, *cursor_wm,
4007 display, cursor);
4008}
4fe5e611 4009
7ccb4a53 4010#define single_plane_enabled(mask) is_power_of_2(mask)
d210246a
CW		 4011
4012static void g4x_update_wm(struct drm_device *dev)
417ae147
CW		 4013{
4014 static const int sr_latency_ns = 12000;
4015 struct drm_i915_private *dev_priv = dev->dev_private;
4016 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
d210246a
CW		 4017 int plane_sr, cursor_sr;
4018 unsigned int enabled = 0;
417ae147
CW		 4019
4020 if (g4x_compute_wm0(dev, 0,
4021 &g4x_wm_info, latency_ns,
4022 &g4x_cursor_wm_info, latency_ns,
4023 &planea_wm, &cursora_wm))
d210246a 4024 enabled |= 1;
417ae147
CW		 4025
4026 if (g4x_compute_wm0(dev, 1,
4027 &g4x_wm_info, latency_ns,
4028 &g4x_cursor_wm_info, latency_ns,
4029 &planeb_wm, &cursorb_wm))
d210246a 4030 enabled |= 2;
417ae147
CW		 4031
4032 plane_sr = cursor_sr = 0;
d210246a
CW		 4033 if (single_plane_enabled(enabled) &&
4034 g4x_compute_srwm(dev, ffs(enabled) - 1,
4035 sr_latency_ns,
417ae147
CW		 4036 &g4x_wm_info,
4037 &g4x_cursor_wm_info,
4038 &plane_sr, &cursor_sr))
0e442c60 4039 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
417ae147
CW		 4040 else
4041 I915_WRITE(FW_BLC_SELF,
4042 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
0e442c60 4043
308977ac
CW		 4044 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4045 planea_wm, cursora_wm,
4046 planeb_wm, cursorb_wm,
4047 plane_sr, cursor_sr);
0e442c60 4048
417ae147
CW		 4049 I915_WRITE(DSPFW1,
4050 (plane_sr << DSPFW_SR_SHIFT) |
0e442c60 4051 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
417ae147
CW		 4052 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4053 planea_wm);
4054 I915_WRITE(DSPFW2,
4055 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
0e442c60
JB		 4056 (cursora_wm << DSPFW_CURSORA_SHIFT));
4057 /* HPLL off in SR has some issues on G4x... disable it */
417ae147
CW		 4058 I915_WRITE(DSPFW3,
4059 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
0e442c60 4060 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB		 4061}
4062
d210246a 4063static void i965_update_wm(struct drm_device *dev)
7662c8bd
SL		 4064{
4065 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4066 struct drm_crtc *crtc;
4067 int srwm = 1;
4fe5e611 4068 int cursor_sr = 16;
1dc7546d
JB		 4069
4070 /* Calc sr entries for one plane configs */
d210246a
CW		 4071 crtc = single_enabled_crtc(dev);
4072 if (crtc) {
1dc7546d 4073 /* self-refresh has much higher latency */
69e302a9 4074 static const int sr_latency_ns = 12000;
d210246a
CW		 4075 int clock = crtc->mode.clock;
4076 int htotal = crtc->mode.htotal;
4077 int hdisplay = crtc->mode.hdisplay;
4078 int pixel_size = crtc->fb->bits_per_pixel / 8;
4079 unsigned long line_time_us;
4080 int entries;
1dc7546d 4081
d210246a 4082 line_time_us = ((htotal * 1000) / clock);
1dc7546d
JB		 4083
4084 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4085 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4086 pixel_size * hdisplay;
4087 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
d210246a 4088 srwm = I965_FIFO_SIZE - entries;
1dc7546d
JB		 4089 if (srwm < 0)
4090 srwm = 1;
1b07e04e 4091 srwm &= 0x1ff;
308977ac
CW		 4092 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4093 entries, srwm);
4fe5e611 4094
d210246a 4095 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 4096 pixel_size * 64;
d210246a 4097 entries = DIV_ROUND_UP(entries,
8de9b311 4098 i965_cursor_wm_info.cacheline_size);
4fe5e611 4099 cursor_sr = i965_cursor_wm_info.fifo_size -
d210246a 4100 (entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY		 4101
4102 if (cursor_sr > i965_cursor_wm_info.max_wm)
4103 cursor_sr = i965_cursor_wm_info.max_wm;
4104
4105 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4106 "cursor %d\n", srwm, cursor_sr);
4107
a6c45cf0 4108 if (IS_CRESTLINE(dev))
adcdbc66 4109 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ		 4110 } else {
4111 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 4112 if (IS_CRESTLINE(dev))
adcdbc66
JB		 4113 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4114 & ~FW_BLC_SELF_EN);
1dc7546d 4115 }
7662c8bd 4116
1dc7546d
JB		 4117 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4118 srwm);
7662c8bd
SL		 4119
4120 /* 965 has limitations... */
417ae147
CW		 4121 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4122 (8 << 16) | (8 << 8) | (8 << 0));
7662c8bd 4123 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY		 4124 /* update cursor SR watermark */
4125 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL		 4126}
4127
d210246a 4128static void i9xx_update_wm(struct drm_device *dev)
7662c8bd
SL		 4129{
4130 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 4131 const struct intel_watermark_params *wm_info;
dff33cfc
JB		 4132 uint32_t fwater_lo;
4133 uint32_t fwater_hi;
d210246a
CW		 4134 int cwm, srwm = 1;
4135 int fifo_size;
dff33cfc 4136 int planea_wm, planeb_wm;
d210246a 4137 struct drm_crtc *crtc, *enabled = NULL;
7662c8bd 4138
72557b4f 4139 if (IS_I945GM(dev))
d210246a 4140 wm_info = &i945_wm_info;
a6c45cf0 4141 else if (!IS_GEN2(dev))
d210246a 4142 wm_info = &i915_wm_info;
7662c8bd 4143 else
d210246a
CW		 4144 wm_info = &i855_wm_info;
4145
4146 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4147 crtc = intel_get_crtc_for_plane(dev, 0);
4148 if (crtc->enabled && crtc->fb) {
4149 planea_wm = intel_calculate_wm(crtc->mode.clock,
4150 wm_info, fifo_size,
4151 crtc->fb->bits_per_pixel / 8,
4152 latency_ns);
4153 enabled = crtc;
4154 } else
4155 planea_wm = fifo_size - wm_info->guard_size;
4156
4157 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4158 crtc = intel_get_crtc_for_plane(dev, 1);
4159 if (crtc->enabled && crtc->fb) {
4160 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4161 wm_info, fifo_size,
4162 crtc->fb->bits_per_pixel / 8,
4163 latency_ns);
4164 if (enabled == NULL)
4165 enabled = crtc;
4166 else
4167 enabled = NULL;
4168 } else
4169 planeb_wm = fifo_size - wm_info->guard_size;
7662c8bd 4170
28c97730 4171 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL		 4172
4173 /*
4174 * Overlay gets an aggressive default since video jitter is bad.
4175 */
4176 cwm = 2;
4177
18b2190c
AL		 4178 /* Play safe and disable self-refresh before adjusting watermarks. */
4179 if (IS_I945G(dev) || IS_I945GM(dev))
4180 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4181 else if (IS_I915GM(dev))
4182 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4183
dff33cfc 4184 /* Calc sr entries for one plane configs */
d210246a 4185 if (HAS_FW_BLC(dev) && enabled) {
dff33cfc 4186 /* self-refresh has much higher latency */
69e302a9 4187 static const int sr_latency_ns = 6000;
d210246a
CW		 4188 int clock = enabled->mode.clock;
4189 int htotal = enabled->mode.htotal;
4190 int hdisplay = enabled->mode.hdisplay;
4191 int pixel_size = enabled->fb->bits_per_pixel / 8;
4192 unsigned long line_time_us;
4193 int entries;
dff33cfc 4194
d210246a 4195 line_time_us = (htotal * 1000) / clock;
dff33cfc
JB		 4196
4197 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4198 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4199 pixel_size * hdisplay;
4200 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4201 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4202 srwm = wm_info->fifo_size - entries;
dff33cfc
JB		 4203 if (srwm < 0)
4204 srwm = 1;
ee980b80
LP		 4205
4206 if (IS_I945G(dev) || IS_I945GM(dev))
18b2190c
AL		 4207 I915_WRITE(FW_BLC_SELF,
4208 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4209 else if (IS_I915GM(dev))
ee980b80 4210 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
7662c8bd
SL		 4211 }
4212
28c97730 4213 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 4214 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 4215
dff33cfc
JB		 4216 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4217 fwater_hi = (cwm & 0x1f);
4218
4219 /* Set request length to 8 cachelines per fetch */
4220 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4221 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL		 4222
4223 I915_WRITE(FW_BLC, fwater_lo);
4224 I915_WRITE(FW_BLC2, fwater_hi);
18b2190c 4225
d210246a
CW		 4226 if (HAS_FW_BLC(dev)) {
4227 if (enabled) {
4228 if (IS_I945G(dev) || IS_I945GM(dev))
4229 I915_WRITE(FW_BLC_SELF,
4230 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4231 else if (IS_I915GM(dev))
4232 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4233 DRM_DEBUG_KMS("memory self refresh enabled\n");
4234 } else
4235 DRM_DEBUG_KMS("memory self refresh disabled\n");
4236 }
7662c8bd
SL		 4237}
4238
d210246a 4239static void i830_update_wm(struct drm_device *dev)
7662c8bd
SL		 4240{
4241 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4242 struct drm_crtc *crtc;
4243 uint32_t fwater_lo;
dff33cfc 4244 int planea_wm;
7662c8bd 4245
d210246a
CW		 4246 crtc = single_enabled_crtc(dev);
4247 if (crtc == NULL)
4248 return;
7662c8bd 4249
d210246a
CW		 4250 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4251 dev_priv->display.get_fifo_size(dev, 0),
4252 crtc->fb->bits_per_pixel / 8,
4253 latency_ns);
4254 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
f3601326
JB		 4255 fwater_lo |= (3<<8) | planea_wm;
4256
28c97730 4257 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL		 4258
4259 I915_WRITE(FW_BLC, fwater_lo);
4260}
4261
7f8a8569 4262#define ILK_LP0_PLANE_LATENCY 700
c936f44d 4263#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 4264
1398261a
YL		 4265/*
4266 * Check the wm result.
4267 *
4268 * If any calculated watermark values is larger than the maximum value that
4269 * can be programmed into the associated watermark register, that watermark
4270 * must be disabled.
1398261a 4271 */
b79d4990
JB		 4272static bool ironlake_check_srwm(struct drm_device *dev, int level,
4273 int fbc_wm, int display_wm, int cursor_wm,
4274 const struct intel_watermark_params *display,
4275 const struct intel_watermark_params *cursor)
1398261a
YL		 4276{
4277 struct drm_i915_private *dev_priv = dev->dev_private;
4278
4279 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4280 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4281
4282 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4283 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4284 fbc_wm, SNB_FBC_MAX_SRWM, level);
1398261a
YL		 4285
4286 /* fbc has it's own way to disable FBC WM */
4287 I915_WRITE(DISP_ARB_CTL,
4288 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4289 return false;
4290 }
4291
b79d4990 4292 if (display_wm > display->max_wm) {
1398261a 4293 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4294 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1398261a
YL		 4295 return false;
4296 }
4297
b79d4990 4298 if (cursor_wm > cursor->max_wm) {
1398261a 4299 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4300 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1398261a
YL		 4301 return false;
4302 }
4303
4304 if (!(fbc_wm || display_wm || cursor_wm)) {
4305 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4306 return false;
4307 }
4308
4309 return true;
4310}
4311
4312/*
4313 * Compute watermark values of WM[1-3],
4314 */
d210246a
CW		 4315static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4316 int latency_ns,
b79d4990
JB		 4317 const struct intel_watermark_params *display,
4318 const struct intel_watermark_params *cursor,
4319 int *fbc_wm, int *display_wm, int *cursor_wm)
1398261a 4320{
d210246a 4321 struct drm_crtc *crtc;
1398261a 4322 unsigned long line_time_us;
d210246a 4323 int hdisplay, htotal, pixel_size, clock;
b79d4990 4324 int line_count, line_size;
1398261a
YL		 4325 int small, large;
4326 int entries;
1398261a
YL		 4327
4328 if (!latency_ns) {
4329 *fbc_wm = *display_wm = *cursor_wm = 0;
4330 return false;
4331 }
4332
d210246a
CW		 4333 crtc = intel_get_crtc_for_plane(dev, plane);
4334 hdisplay = crtc->mode.hdisplay;
4335 htotal = crtc->mode.htotal;
4336 clock = crtc->mode.clock;
4337 pixel_size = crtc->fb->bits_per_pixel / 8;
4338
1398261a
YL		 4339 line_time_us = (htotal * 1000) / clock;
4340 line_count = (latency_ns / line_time_us + 1000) / 1000;
4341 line_size = hdisplay * pixel_size;
4342
4343 /* Use the minimum of the small and large buffer method for primary */
4344 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4345 large = line_count * line_size;
4346
b79d4990
JB		 4347 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4348 *display_wm = entries + display->guard_size;
1398261a
YL		 4349
4350 /*
b79d4990 4351 * Spec says:
1398261a
YL		 4352 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4353 */
4354 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4355
4356 /* calculate the self-refresh watermark for display cursor */
4357 entries = line_count * pixel_size * 64;
b79d4990
JB		 4358 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4359 *cursor_wm = entries + cursor->guard_size;
1398261a 4360
b79d4990
JB		 4361 return ironlake_check_srwm(dev, level,
4362 *fbc_wm, *display_wm, *cursor_wm,
4363 display, cursor);
4364}
4365
d210246a 4366static void ironlake_update_wm(struct drm_device *dev)
b79d4990
JB		 4367{
4368 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4369 int fbc_wm, plane_wm, cursor_wm;
4370 unsigned int enabled;
b79d4990
JB		 4371
4372 enabled = 0;
9f405100
CW		 4373 if (g4x_compute_wm0(dev, 0,
4374 &ironlake_display_wm_info,
4375 ILK_LP0_PLANE_LATENCY,
4376 &ironlake_cursor_wm_info,
4377 ILK_LP0_CURSOR_LATENCY,
4378 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4379 I915_WRITE(WM0_PIPEA_ILK,
4380 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4381 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4382 " plane %d, " "cursor: %d\n",
4383 plane_wm, cursor_wm);
d210246a 4384 enabled |= 1;
b79d4990
JB		 4385 }
4386
9f405100
CW		 4387 if (g4x_compute_wm0(dev, 1,
4388 &ironlake_display_wm_info,
4389 ILK_LP0_PLANE_LATENCY,
4390 &ironlake_cursor_wm_info,
4391 ILK_LP0_CURSOR_LATENCY,
4392 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4393 I915_WRITE(WM0_PIPEB_ILK,
4394 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4395 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4396 " plane %d, cursor: %d\n",
4397 plane_wm, cursor_wm);
d210246a 4398 enabled |= 2;
b79d4990
JB		 4399 }
4400
4401 /*
4402 * Calculate and update the self-refresh watermark only when one
4403 * display plane is used.
4404 */
4405 I915_WRITE(WM3_LP_ILK, 0);
4406 I915_WRITE(WM2_LP_ILK, 0);
4407 I915_WRITE(WM1_LP_ILK, 0);
4408
d210246a 4409 if (!single_plane_enabled(enabled))
b79d4990 4410 return;
d210246a 4411 enabled = ffs(enabled) - 1;
b79d4990
JB		 4412
4413 /* WM1 */
d210246a
CW		 4414 if (!ironlake_compute_srwm(dev, 1, enabled,
4415 ILK_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4416 &ironlake_display_srwm_info,
4417 &ironlake_cursor_srwm_info,
4418 &fbc_wm, &plane_wm, &cursor_wm))
4419 return;
4420
4421 I915_WRITE(WM1_LP_ILK,
4422 WM1_LP_SR_EN |
4423 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4424 (fbc_wm << WM1_LP_FBC_SHIFT) |
4425 (plane_wm << WM1_LP_SR_SHIFT) |
4426 cursor_wm);
4427
4428 /* WM2 */
d210246a
CW		 4429 if (!ironlake_compute_srwm(dev, 2, enabled,
4430 ILK_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4431 &ironlake_display_srwm_info,
4432 &ironlake_cursor_srwm_info,
4433 &fbc_wm, &plane_wm, &cursor_wm))
4434 return;
4435
4436 I915_WRITE(WM2_LP_ILK,
4437 WM2_LP_EN |
4438 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4439 (fbc_wm << WM1_LP_FBC_SHIFT) |
4440 (plane_wm << WM1_LP_SR_SHIFT) |
4441 cursor_wm);
4442
4443 /*
4444 * WM3 is unsupported on ILK, probably because we don't have latency
4445 * data for that power state
4446 */
1398261a
YL		 4447}
4448
d210246a 4449static void sandybridge_update_wm(struct drm_device *dev)
1398261a
YL		 4450{
4451 struct drm_i915_private *dev_priv = dev->dev_private;
a0fa62d3 4452 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
d210246a
CW		 4453 int fbc_wm, plane_wm, cursor_wm;
4454 unsigned int enabled;
1398261a
YL		 4455
4456 enabled = 0;
9f405100
CW		 4457 if (g4x_compute_wm0(dev, 0,
4458 &sandybridge_display_wm_info, latency,
4459 &sandybridge_cursor_wm_info, latency,
4460 &plane_wm, &cursor_wm)) {
1398261a
YL		 4461 I915_WRITE(WM0_PIPEA_ILK,
4462 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4463 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4464 " plane %d, " "cursor: %d\n",
4465 plane_wm, cursor_wm);
d210246a 4466 enabled |= 1;
1398261a
YL		 4467 }
4468
9f405100
CW		 4469 if (g4x_compute_wm0(dev, 1,
4470 &sandybridge_display_wm_info, latency,
4471 &sandybridge_cursor_wm_info, latency,
4472 &plane_wm, &cursor_wm)) {
1398261a
YL		 4473 I915_WRITE(WM0_PIPEB_ILK,
4474 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4475 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4476 " plane %d, cursor: %d\n",
4477 plane_wm, cursor_wm);
d210246a 4478 enabled |= 2;
1398261a
YL		 4479 }
4480
4481 /*
4482 * Calculate and update the self-refresh watermark only when one
4483 * display plane is used.
4484 *
4485 * SNB support 3 levels of watermark.
4486 *
4487 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4488 * and disabled in the descending order
4489 *
4490 */
4491 I915_WRITE(WM3_LP_ILK, 0);
4492 I915_WRITE(WM2_LP_ILK, 0);
4493 I915_WRITE(WM1_LP_ILK, 0);
4494
d210246a 4495 if (!single_plane_enabled(enabled))
1398261a 4496 return;
d210246a 4497 enabled = ffs(enabled) - 1;
1398261a
YL		 4498
4499 /* WM1 */
d210246a
CW		 4500 if (!ironlake_compute_srwm(dev, 1, enabled,
4501 SNB_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4502 &sandybridge_display_srwm_info,
4503 &sandybridge_cursor_srwm_info,
4504 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4505 return;
4506
4507 I915_WRITE(WM1_LP_ILK,
4508 WM1_LP_SR_EN |
4509 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4510 (fbc_wm << WM1_LP_FBC_SHIFT) |
4511 (plane_wm << WM1_LP_SR_SHIFT) |
4512 cursor_wm);
4513
4514 /* WM2 */
d210246a
CW		 4515 if (!ironlake_compute_srwm(dev, 2, enabled,
4516 SNB_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4517 &sandybridge_display_srwm_info,
4518 &sandybridge_cursor_srwm_info,
4519 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4520 return;
4521
4522 I915_WRITE(WM2_LP_ILK,
4523 WM2_LP_EN |
4524 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4525 (fbc_wm << WM1_LP_FBC_SHIFT) |
4526 (plane_wm << WM1_LP_SR_SHIFT) |
4527 cursor_wm);
4528
4529 /* WM3 */
d210246a
CW		 4530 if (!ironlake_compute_srwm(dev, 3, enabled,
4531 SNB_READ_WM3_LATENCY() * 500,
b79d4990
JB		 4532 &sandybridge_display_srwm_info,
4533 &sandybridge_cursor_srwm_info,
4534 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4535 return;
4536
4537 I915_WRITE(WM3_LP_ILK,
4538 WM3_LP_EN |
4539 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4540 (fbc_wm << WM1_LP_FBC_SHIFT) |
4541 (plane_wm << WM1_LP_SR_SHIFT) |
4542 cursor_wm);
4543}
4544
7662c8bd
SL		 4545/**
4546 * intel_update_watermarks - update FIFO watermark values based on current modes
4547 *
4548 * Calculate watermark values for the various WM regs based on current mode
4549 * and plane configuration.
4550 *
4551 * There are several cases to deal with here:
4552 * - normal (i.e. non-self-refresh)
4553 * - self-refresh (SR) mode
4554 * - lines are large relative to FIFO size (buffer can hold up to 2)
4555 * - lines are small relative to FIFO size (buffer can hold more than 2
4556 * lines), so need to account for TLB latency
4557 *
4558 * The normal calculation is:
4559 * watermark = dotclock * bytes per pixel * latency
4560 * where latency is platform & configuration dependent (we assume pessimal
4561 * values here).
4562 *
4563 * The SR calculation is:
4564 * watermark = (trunc(latency/line time)+1) * surface width *
4565 * bytes per pixel
4566 * where
4567 * line time = htotal / dotclock
fa143215 4568 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL		 4569 * and latency is assumed to be high, as above.
4570 *
4571 * The final value programmed to the register should always be rounded up,
4572 * and include an extra 2 entries to account for clock crossings.
4573 *
4574 * We don't use the sprite, so we can ignore that. And on Crestline we have
4575 * to set the non-SR watermarks to 8.
5eddb70b 4576 */
7662c8bd
SL		 4577static void intel_update_watermarks(struct drm_device *dev)
4578{
e70236a8 4579 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 4580
d210246a
CW		 4581 if (dev_priv->display.update_wm)
4582 dev_priv->display.update_wm(dev);
7662c8bd
SL		 4583}
4584
a7615030
CW		 4585static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4586{
72bbe58c
KP		 4587 if (i915_panel_use_ssc >= 0)
4588 return i915_panel_use_ssc != 0;
4589 return dev_priv->lvds_use_ssc
435793df 4590 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4591}
4592
5a354204
JB		 4593/**
4594 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4595 * @crtc: CRTC structure
4596 *
4597 * A pipe may be connected to one or more outputs. Based on the depth of the
4598 * attached framebuffer, choose a good color depth to use on the pipe.
4599 *
4600 * If possible, match the pipe depth to the fb depth. In some cases, this
4601 * isn't ideal, because the connected output supports a lesser or restricted
4602 * set of depths. Resolve that here:
4603 * LVDS typically supports only 6bpc, so clamp down in that case
4604 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4605 * Displays may support a restricted set as well, check EDID and clamp as
4606 * appropriate.
4607 *
4608 * RETURNS:
4609 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4610 * true if they don't match).
4611 */
4612static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4613 unsigned int *pipe_bpp)
4614{
4615 struct drm_device *dev = crtc->dev;
4616 struct drm_i915_private *dev_priv = dev->dev_private;
4617 struct drm_encoder *encoder;
4618 struct drm_connector *connector;
4619 unsigned int display_bpc = UINT_MAX, bpc;
4620
4621 /* Walk the encoders & connectors on this crtc, get min bpc */
4622 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4623 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4624
4625 if (encoder->crtc != crtc)
4626 continue;
4627
4628 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4629 unsigned int lvds_bpc;
4630
4631 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4632 LVDS_A3_POWER_UP)
4633 lvds_bpc = 8;
4634 else
4635 lvds_bpc = 6;
4636
4637 if (lvds_bpc < display_bpc) {
4638 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4639 display_bpc = lvds_bpc;
4640 }
4641 continue;
4642 }
4643
4644 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4645 /* Use VBT settings if we have an eDP panel */
4646 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4647
4648 if (edp_bpc < display_bpc) {
4649 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4650 display_bpc = edp_bpc;
4651 }
4652 continue;
4653 }
4654
4655 /* Not one of the known troublemakers, check the EDID */
4656 list_for_each_entry(connector, &dev->mode_config.connector_list,
4657 head) {
4658 if (connector->encoder != encoder)
4659 continue;
4660
62ac41a6
JB		 4661 /* Don't use an invalid EDID bpc value */
4662 if (connector->display_info.bpc &&
4663 connector->display_info.bpc < display_bpc) {
5a354204
JB		 4664 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4665 display_bpc = connector->display_info.bpc;
4666 }
4667 }
4668
4669 /*
4670 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4671 * through, clamp it down. (Note: >12bpc will be caught below.)
4672 */
4673 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4674 if (display_bpc > 8 && display_bpc < 12) {
4675 DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
4676 display_bpc = 12;
4677 } else {
4678 DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
4679 display_bpc = 8;
4680 }
4681 }
4682 }
4683
4684 /*
4685 * We could just drive the pipe at the highest bpc all the time and
4686 * enable dithering as needed, but that costs bandwidth. So choose
4687 * the minimum value that expresses the full color range of the fb but
4688 * also stays within the max display bpc discovered above.
4689 */
4690
4691 switch (crtc->fb->depth) {
4692 case 8:
4693 bpc = 8; /* since we go through a colormap */
4694 break;
4695 case 15:
4696 case 16:
4697 bpc = 6; /* min is 18bpp */
4698 break;
4699 case 24:
7cd015a0 4700 bpc = 8;
5a354204
JB		 4701 break;
4702 case 30:
7cd015a0 4703 bpc = 10;
5a354204
JB		 4704 break;
4705 case 48:
7cd015a0 4706 bpc = 12;
5a354204
JB		 4707 break;
4708 default:
4709 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4710 bpc = min((unsigned int)8, display_bpc);
4711 break;
4712 }
4713
7cd015a0
KP		 4714 display_bpc = min(display_bpc, bpc);
4715
5a354204
JB		 4716 DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
4717 bpc, display_bpc);
4718
7cd015a0 4719 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4720
4721 return display_bpc != bpc;
4722}
4723
f564048e
EA		 4724static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4725 struct drm_display_mode *mode,
4726 struct drm_display_mode *adjusted_mode,
4727 int x, int y,
4728 struct drm_framebuffer *old_fb)
79e53945
JB		 4729{
4730 struct drm_device *dev = crtc->dev;
4731 struct drm_i915_private *dev_priv = dev->dev_private;
4732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4733 int pipe = intel_crtc->pipe;
80824003 4734 int plane = intel_crtc->plane;
c751ce4f 4735 int refclk, num_connectors = 0;
652c393a 4736 intel_clock_t clock, reduced_clock;
5eddb70b 4737 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
652c393a 4738 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
a4fc5ed6 4739 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 4740 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 4741 struct intel_encoder *encoder;
d4906093 4742 const intel_limit_t *limit;
5c3b82e2 4743 int ret;
fae14981 4744 u32 temp;
aa9b500d 4745 u32 lvds_sync = 0;
79e53945 4746
5eddb70b
CW		 4747 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4748 if (encoder->base.crtc != crtc)
79e53945
JB		 4749 continue;
4750
5eddb70b 4751 switch (encoder->type) {
79e53945
JB		 4752 case INTEL_OUTPUT_LVDS:
4753 is_lvds = true;
4754 break;
4755 case INTEL_OUTPUT_SDVO:
7d57382e 4756 case INTEL_OUTPUT_HDMI:
79e53945 4757 is_sdvo = true;
5eddb70b 4758 if (encoder->needs_tv_clock)
e2f0ba97 4759 is_tv = true;
79e53945
JB		 4760 break;
4761 case INTEL_OUTPUT_DVO:
4762 is_dvo = true;
4763 break;
4764 case INTEL_OUTPUT_TVOUT:
4765 is_tv = true;
4766 break;
4767 case INTEL_OUTPUT_ANALOG:
4768 is_crt = true;
4769 break;
a4fc5ed6
KP		 4770 case INTEL_OUTPUT_DISPLAYPORT:
4771 is_dp = true;
4772 break;
79e53945 4773 }
43565a06 4774
c751ce4f 4775 num_connectors++;
79e53945
JB		 4776 }
4777
a7615030 4778 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 4779 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 4780 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 4781 refclk / 1000);
a6c45cf0 4782 } else if (!IS_GEN2(dev)) {
79e53945
JB		 4783 refclk = 96000;
4784 } else {
4785 refclk = 48000;
4786 }
4787
d4906093
ML		 4788 /*
4789 * Returns a set of divisors for the desired target clock with the given
4790 * refclk, or FALSE. The returned values represent the clock equation:
4791 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4792 */
1b894b59 4793 limit = intel_limit(crtc, refclk);
d4906093 4794 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 4795 if (!ok) {
4796 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4797 return -EINVAL;
79e53945
JB		 4798 }
4799
cda4b7d3 4800 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4801 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4802
ddc9003c
ZY		 4803 if (is_lvds && dev_priv->lvds_downclock_avail) {
4804 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4805 dev_priv->lvds_downclock,
4806 refclk,
4807 &reduced_clock);
18f9ed12
ZY		 4808 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4809 /*
4810 * If the different P is found, it means that we can't
4811 * switch the display clock by using the FP0/FP1.
4812 * In such case we will disable the LVDS downclock
4813 * feature.
4814 */
4815 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 4816 "LVDS clock/downclock\n");
18f9ed12
ZY		 4817 has_reduced_clock = 0;
4818 }
652c393a 4819 }
7026d4ac
ZW		 4820 /* SDVO TV has fixed PLL values depend on its clock range,
4821 this mirrors vbios setting. */
4822 if (is_sdvo && is_tv) {
4823 if (adjusted_mode->clock >= 100000
5eddb70b 4824 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4825 clock.p1 = 2;
4826 clock.p2 = 10;
4827 clock.n = 3;
4828 clock.m1 = 16;
4829 clock.m2 = 8;
4830 } else if (adjusted_mode->clock >= 140500
5eddb70b 4831 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4832 clock.p1 = 1;
4833 clock.p2 = 10;
4834 clock.n = 6;
4835 clock.m1 = 12;
4836 clock.m2 = 8;
4837 }
4838 }
4839
f2b115e6 4840 if (IS_PINEVIEW(dev)) {
2177832f 4841 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 4842 if (has_reduced_clock)
4843 fp2 = (1 << reduced_clock.n) << 16 |
4844 reduced_clock.m1 << 8 | reduced_clock.m2;
4845 } else {
2177832f 4846 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 4847 if (has_reduced_clock)
4848 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4849 reduced_clock.m2;
4850 }
79e53945 4851
929c77fb 4852 dpll = DPLL_VGA_MODE_DIS;
2c07245f 4853
a6c45cf0 4854 if (!IS_GEN2(dev)) {
79e53945
JB		 4855 if (is_lvds)
4856 dpll |= DPLLB_MODE_LVDS;
4857 else
4858 dpll |= DPLLB_MODE_DAC_SERIAL;
4859 if (is_sdvo) {
6c9547ff
CW		 4860 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4861 if (pixel_multiplier > 1) {
4862 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4863 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
6c9547ff 4864 }
79e53945 4865 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4866 }
929c77fb 4867 if (is_dp)
a4fc5ed6 4868 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945
JB		 4869
4870 /* compute bitmask from p1 value */
f2b115e6
AJ		 4871 if (IS_PINEVIEW(dev))
4872 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
2c07245f 4873 else {
2177832f 4874 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
652c393a
JB		 4875 if (IS_G4X(dev) && has_reduced_clock)
4876 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2c07245f 4877 }
79e53945
JB		 4878 switch (clock.p2) {
4879 case 5:
4880 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4881 break;
4882 case 7:
4883 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4884 break;
4885 case 10:
4886 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4887 break;
4888 case 14:
4889 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4890 break;
4891 }
929c77fb 4892 if (INTEL_INFO(dev)->gen >= 4)
79e53945
JB		 4893 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4894 } else {
4895 if (is_lvds) {
4896 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4897 } else {
4898 if (clock.p1 == 2)
4899 dpll |= PLL_P1_DIVIDE_BY_TWO;
4900 else
4901 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4902 if (clock.p2 == 4)
4903 dpll |= PLL_P2_DIVIDE_BY_4;
4904 }
4905 }
4906
43565a06
KH		 4907 if (is_sdvo && is_tv)
4908 dpll |= PLL_REF_INPUT_TVCLKINBC;
4909 else if (is_tv)
79e53945 4910 /* XXX: just matching BIOS for now */
43565a06 4911 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4912 dpll |= 3;
a7615030 4913 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4914 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4915 else
4916 dpll |= PLL_REF_INPUT_DREFCLK;
4917
4918 /* setup pipeconf */
5eddb70b 4919 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4920
4921 /* Set up the display plane register */
4922 dspcntr = DISPPLANE_GAMMA_ENABLE;
4923
f2b115e6 4924 /* Ironlake's plane is forced to pipe, bit 24 is to
2c07245f 4925 enable color space conversion */
929c77fb
EA		 4926 if (pipe == 0)
4927 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4928 else
4929 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4930
a6c45cf0 4931 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4932 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4933 * core speed.
4934 *
4935 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4936 * pipe == 0 check?
4937 */
e70236a8
JB		 4938 if (mode->clock >
4939 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4940 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4941 else
5eddb70b 4942 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4943 }
4944
929c77fb 4945 dpll |= DPLL_VCO_ENABLE;
8d86dc6a 4946
28c97730 4947 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4948 drm_mode_debug_printmodeline(mode);
4949
fae14981
EA		 4950 I915_WRITE(FP0(pipe), fp);
4951 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 4952
fae14981 4953 POSTING_READ(DPLL(pipe));
c713bb08 4954 udelay(150);
8db9d77b 4955
79e53945
JB		 4956 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4957 * This is an exception to the general rule that mode_set doesn't turn
4958 * things on.
4959 */
4960 if (is_lvds) {
fae14981 4961 temp = I915_READ(LVDS);
5eddb70b 4962 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3 4963 if (pipe == 1) {
929c77fb 4964 temp |= LVDS_PIPEB_SELECT;
b3b095b3 4965 } else {
929c77fb 4966 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 4967 }
a3e17eb8 4968 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4969 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4970 /* Set the B0-B3 data pairs corresponding to whether we're going to
4971 * set the DPLLs for dual-channel mode or not.
4972 */
4973 if (clock.p2 == 7)
5eddb70b 4974 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4975 else
5eddb70b 4976 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4977
4978 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4979 * appropriately here, but we need to look more thoroughly into how
4980 * panels behave in the two modes.
4981 */
929c77fb
EA		 4982 /* set the dithering flag on LVDS as needed */
4983 if (INTEL_INFO(dev)->gen >= 4) {
434ed097 4984 if (dev_priv->lvds_dither)
5eddb70b 4985 temp |= LVDS_ENABLE_DITHER;
434ed097 4986 else
5eddb70b 4987 temp &= ~LVDS_ENABLE_DITHER;
898822ce 4988 }
aa9b500d
BF		 4989 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4990 lvds_sync |= LVDS_HSYNC_POLARITY;
4991 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4992 lvds_sync |= LVDS_VSYNC_POLARITY;
4993 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4994 != lvds_sync) {
4995 char flags[2] = "-+";
4996 DRM_INFO("Changing LVDS panel from "
4997 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4998 flags[!(temp & LVDS_HSYNC_POLARITY)],
4999 flags[!(temp & LVDS_VSYNC_POLARITY)],
5000 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5001 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5002 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5003 temp |= lvds_sync;
5004 }
fae14981 5005 I915_WRITE(LVDS, temp);
79e53945 5006 }
434ed097 5007
929c77fb 5008 if (is_dp) {
a4fc5ed6 5009 intel_dp_set_m_n(crtc, mode, adjusted_mode);
434ed097
JB		 5010 }
5011
fae14981 5012 I915_WRITE(DPLL(pipe), dpll);
5eddb70b 5013
c713bb08 5014 /* Wait for the clocks to stabilize. */
fae14981 5015 POSTING_READ(DPLL(pipe));
c713bb08 5016 udelay(150);
32f9d658 5017
c713bb08
EA		 5018 if (INTEL_INFO(dev)->gen >= 4) {
5019 temp = 0;
5020 if (is_sdvo) {
5021 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5022 if (temp > 1)
5023 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5024 else
5025 temp = 0;
32f9d658 5026 }
c713bb08
EA		 5027 I915_WRITE(DPLL_MD(pipe), temp);
5028 } else {
5029 /* The pixel multiplier can only be updated once the
5030 * DPLL is enabled and the clocks are stable.
5031 *
5032 * So write it again.
5033 */
fae14981 5034 I915_WRITE(DPLL(pipe), dpll);
79e53945 5035 }
79e53945 5036
5eddb70b 5037 intel_crtc->lowfreq_avail = false;
652c393a 5038 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 5039 I915_WRITE(FP1(pipe), fp2);
652c393a
JB		 5040 intel_crtc->lowfreq_avail = true;
5041 if (HAS_PIPE_CXSR(dev)) {
28c97730 5042 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 5043 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5044 }
5045 } else {
fae14981 5046 I915_WRITE(FP1(pipe), fp);
652c393a 5047 if (HAS_PIPE_CXSR(dev)) {
28c97730 5048 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5049 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5050 }
5051 }
5052
734b4157
KH		 5053 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5054 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5055 /* the chip adds 2 halflines automatically */
5056 adjusted_mode->crtc_vdisplay -= 1;
5057 adjusted_mode->crtc_vtotal -= 1;
5058 adjusted_mode->crtc_vblank_start -= 1;
5059 adjusted_mode->crtc_vblank_end -= 1;
5060 adjusted_mode->crtc_vsync_end -= 1;
5061 adjusted_mode->crtc_vsync_start -= 1;
5062 } else
5063 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5064
5eddb70b
CW		 5065 I915_WRITE(HTOTAL(pipe),
5066 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5067 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5068 I915_WRITE(HBLANK(pipe),
5069 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5070 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5071 I915_WRITE(HSYNC(pipe),
5072 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5073 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5074
5075 I915_WRITE(VTOTAL(pipe),
5076 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5077 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5078 I915_WRITE(VBLANK(pipe),
5079 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5080 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5081 I915_WRITE(VSYNC(pipe),
5082 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5083 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 5084
5085 /* pipesrc and dspsize control the size that is scaled from,
5086 * which should always be the user's requested size.
79e53945 5087 */
929c77fb
EA		 5088 I915_WRITE(DSPSIZE(plane),
5089 ((mode->vdisplay - 1) << 16) |
5090 (mode->hdisplay - 1));
5091 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 5092 I915_WRITE(PIPESRC(pipe),
5093 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5094
f564048e
EA		 5095 I915_WRITE(PIPECONF(pipe), pipeconf);
5096 POSTING_READ(PIPECONF(pipe));
929c77fb 5097 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 5098
5099 intel_wait_for_vblank(dev, pipe);
5100
f564048e
EA		 5101 I915_WRITE(DSPCNTR(plane), dspcntr);
5102 POSTING_READ(DSPCNTR(plane));
284d9529 5103 intel_enable_plane(dev_priv, plane, pipe);
f564048e
EA		 5104
5105 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5106
5107 intel_update_watermarks(dev);
5108
f564048e
EA		 5109 return ret;
5110}
5111
13d83a67
JB		 5112static void ironlake_update_pch_refclk(struct drm_device *dev)
5113{
5114 struct drm_i915_private *dev_priv = dev->dev_private;
5115 struct drm_mode_config *mode_config = &dev->mode_config;
5116 struct drm_crtc *crtc;
5117 struct intel_encoder *encoder;
5118 struct intel_encoder *has_edp_encoder = NULL;
5119 u32 temp;
5120 bool has_lvds = false;
5121
5122 /* We need to take the global config into account */
5123 list_for_each_entry(crtc, &mode_config->crtc_list, head) {
5124 if (!crtc->enabled)
5125 continue;
5126
5127 list_for_each_entry(encoder, &mode_config->encoder_list,
5128 base.head) {
5129 if (encoder->base.crtc != crtc)
5130 continue;
5131
5132 switch (encoder->type) {
5133 case INTEL_OUTPUT_LVDS:
5134 has_lvds = true;
5135 case INTEL_OUTPUT_EDP:
5136 has_edp_encoder = encoder;
5137 break;
5138 }
5139 }
5140 }
5141
5142 /* Ironlake: try to setup display ref clock before DPLL
5143 * enabling. This is only under driver's control after
5144 * PCH B stepping, previous chipset stepping should be
5145 * ignoring this setting.
5146 */
5147 temp = I915_READ(PCH_DREF_CONTROL);
5148 /* Always enable nonspread source */
5149 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5150 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5151 temp &= ~DREF_SSC_SOURCE_MASK;
5152 temp |= DREF_SSC_SOURCE_ENABLE;
5153 I915_WRITE(PCH_DREF_CONTROL, temp);
5154
5155 POSTING_READ(PCH_DREF_CONTROL);
5156 udelay(200);
5157
5158 if (has_edp_encoder) {
5159 if (intel_panel_use_ssc(dev_priv)) {
5160 temp |= DREF_SSC1_ENABLE;
5161 I915_WRITE(PCH_DREF_CONTROL, temp);
5162
5163 POSTING_READ(PCH_DREF_CONTROL);
5164 udelay(200);
5165 }
5166 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5167
5168 /* Enable CPU source on CPU attached eDP */
5169 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5170 if (intel_panel_use_ssc(dev_priv))
5171 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5172 else
5173 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5174 } else {
5175 /* Enable SSC on PCH eDP if needed */
5176 if (intel_panel_use_ssc(dev_priv)) {
5177 DRM_ERROR("enabling SSC on PCH\n");
5178 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
5179 }
5180 }
5181 I915_WRITE(PCH_DREF_CONTROL, temp);
5182 POSTING_READ(PCH_DREF_CONTROL);
5183 udelay(200);
5184 }
5185}
5186
f564048e
EA		 5187static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5188 struct drm_display_mode *mode,
5189 struct drm_display_mode *adjusted_mode,
5190 int x, int y,
5191 struct drm_framebuffer *old_fb)
79e53945
JB		 5192{
5193 struct drm_device *dev = crtc->dev;
5194 struct drm_i915_private *dev_priv = dev->dev_private;
5195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5196 int pipe = intel_crtc->pipe;
80824003 5197 int plane = intel_crtc->plane;
c751ce4f 5198 int refclk, num_connectors = 0;
652c393a 5199 intel_clock_t clock, reduced_clock;
5eddb70b 5200 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 5201 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 5202 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
8e647a27 5203 struct intel_encoder *has_edp_encoder = NULL;
79e53945 5204 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 5205 struct intel_encoder *encoder;
d4906093 5206 const intel_limit_t *limit;
5c3b82e2 5207 int ret;
2c07245f 5208 struct fdi_m_n m_n = {0};
fae14981 5209 u32 temp;
aa9b500d 5210 u32 lvds_sync = 0;
5a354204
JB		 5211 int target_clock, pixel_multiplier, lane, link_bw, factor;
5212 unsigned int pipe_bpp;
5213 bool dither;
79e53945 5214
5eddb70b
CW		 5215 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5216 if (encoder->base.crtc != crtc)
79e53945
JB		 5217 continue;
5218
5eddb70b 5219 switch (encoder->type) {
79e53945
JB		 5220 case INTEL_OUTPUT_LVDS:
5221 is_lvds = true;
5222 break;
5223 case INTEL_OUTPUT_SDVO:
7d57382e 5224 case INTEL_OUTPUT_HDMI:
79e53945 5225 is_sdvo = true;
5eddb70b 5226 if (encoder->needs_tv_clock)
e2f0ba97 5227 is_tv = true;
79e53945 5228 break;
79e53945
JB		 5229 case INTEL_OUTPUT_TVOUT:
5230 is_tv = true;
5231 break;
5232 case INTEL_OUTPUT_ANALOG:
5233 is_crt = true;
5234 break;
a4fc5ed6
KP		 5235 case INTEL_OUTPUT_DISPLAYPORT:
5236 is_dp = true;
5237 break;
32f9d658 5238 case INTEL_OUTPUT_EDP:
5eddb70b 5239 has_edp_encoder = encoder;
32f9d658 5240 break;
79e53945 5241 }
43565a06 5242
c751ce4f 5243 num_connectors++;
79e53945
JB		 5244 }
5245
a7615030 5246 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 5247 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 5248 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 5249 refclk / 1000);
a07d6787 5250 } else {
79e53945 5251 refclk = 96000;
8febb297
EA		 5252 if (!has_edp_encoder ||
5253 intel_encoder_is_pch_edp(&has_edp_encoder->base))
2c07245f 5254 refclk = 120000; /* 120Mhz refclk */
79e53945
JB		 5255 }
5256
d4906093
ML		 5257 /*
5258 * Returns a set of divisors for the desired target clock with the given
5259 * refclk, or FALSE. The returned values represent the clock equation:
5260 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5261 */
1b894b59 5262 limit = intel_limit(crtc, refclk);
d4906093 5263 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 5264 if (!ok) {
5265 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 5266 return -EINVAL;
79e53945
JB		 5267 }
5268
cda4b7d3 5269 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 5270 intel_crtc_update_cursor(crtc, true);
cda4b7d3 5271
ddc9003c
ZY		 5272 if (is_lvds && dev_priv->lvds_downclock_avail) {
5273 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 5274 dev_priv->lvds_downclock,
5275 refclk,
5276 &reduced_clock);
18f9ed12
ZY		 5277 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5278 /*
5279 * If the different P is found, it means that we can't
5280 * switch the display clock by using the FP0/FP1.
5281 * In such case we will disable the LVDS downclock
5282 * feature.
5283 */
5284 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 5285 "LVDS clock/downclock\n");
18f9ed12
ZY		 5286 has_reduced_clock = 0;
5287 }
652c393a 5288 }
7026d4ac
ZW		 5289 /* SDVO TV has fixed PLL values depend on its clock range,
5290 this mirrors vbios setting. */
5291 if (is_sdvo && is_tv) {
5292 if (adjusted_mode->clock >= 100000
5eddb70b 5293 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 5294 clock.p1 = 2;
5295 clock.p2 = 10;
5296 clock.n = 3;
5297 clock.m1 = 16;
5298 clock.m2 = 8;
5299 } else if (adjusted_mode->clock >= 140500
5eddb70b 5300 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 5301 clock.p1 = 1;
5302 clock.p2 = 10;
5303 clock.n = 6;
5304 clock.m1 = 12;
5305 clock.m2 = 8;
5306 }
5307 }
5308
2c07245f 5309 /* FDI link */
8febb297
EA		 5310 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5311 lane = 0;
5312 /* CPU eDP doesn't require FDI link, so just set DP M/N
5313 according to current link config */
5314 if (has_edp_encoder &&
5315 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5316 target_clock = mode->clock;
5317 intel_edp_link_config(has_edp_encoder,
5318 &lane, &link_bw);
5319 } else {
5320 /* [e]DP over FDI requires target mode clock
5321 instead of link clock */
5322 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5eb08b69 5323 target_clock = mode->clock;
8febb297
EA		 5324 else
5325 target_clock = adjusted_mode->clock;
5326
5327 /* FDI is a binary signal running at ~2.7GHz, encoding
5328 * each output octet as 10 bits. The actual frequency
5329 * is stored as a divider into a 100MHz clock, and the
5330 * mode pixel clock is stored in units of 1KHz.
5331 * Hence the bw of each lane in terms of the mode signal
5332 * is:
5333 */
5334 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5335 }
58a27471 5336
8febb297
EA		 5337 /* determine panel color depth */
5338 temp = I915_READ(PIPECONF(pipe));
5339 temp &= ~PIPE_BPC_MASK;
5a354204
JB		 5340 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
5341 switch (pipe_bpp) {
5342 case 18:
5343 temp |= PIPE_6BPC;
8febb297 5344 break;
5a354204
JB		 5345 case 24:
5346 temp |= PIPE_8BPC;
8febb297 5347 break;
5a354204
JB		 5348 case 30:
5349 temp |= PIPE_10BPC;
8febb297 5350 break;
5a354204
JB		 5351 case 36:
5352 temp |= PIPE_12BPC;
8febb297
EA		 5353 break;
5354 default:
62ac41a6
JB		 5355 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5356 pipe_bpp);
5a354204
JB		 5357 temp |= PIPE_8BPC;
5358 pipe_bpp = 24;
5359 break;
8febb297 5360 }
77ffb597 5361
5a354204
JB		 5362 intel_crtc->bpp = pipe_bpp;
5363 I915_WRITE(PIPECONF(pipe), temp);
5364
8febb297
EA		 5365 if (!lane) {
5366 /*
5367 * Account for spread spectrum to avoid
5368 * oversubscribing the link. Max center spread
5369 * is 2.5%; use 5% for safety's sake.
5370 */
5a354204 5371 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 5372 lane = bps / (link_bw * 8) + 1;
5eb08b69 5373 }
2c07245f 5374
8febb297
EA		 5375 intel_crtc->fdi_lanes = lane;
5376
5377 if (pixel_multiplier > 1)
5378 link_bw *= pixel_multiplier;
5a354204
JB		 5379 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5380 &m_n);
8febb297 5381
13d83a67 5382 ironlake_update_pch_refclk(dev);
c038e51e 5383
a07d6787
EA		 5384 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5385 if (has_reduced_clock)
5386 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5387 reduced_clock.m2;
79e53945 5388
c1858123 5389 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5390 factor = 21;
5391 if (is_lvds) {
5392 if ((intel_panel_use_ssc(dev_priv) &&
5393 dev_priv->lvds_ssc_freq == 100) ||
5394 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5395 factor = 25;
5396 } else if (is_sdvo && is_tv)
5397 factor = 20;
c1858123 5398
cb0e0931 5399 if (clock.m < factor * clock.n)
8febb297 5400 fp |= FP_CB_TUNE;
2c07245f 5401
5eddb70b 5402 dpll = 0;
2c07245f 5403
a07d6787
EA		 5404 if (is_lvds)
5405 dpll |= DPLLB_MODE_LVDS;
5406 else
5407 dpll |= DPLLB_MODE_DAC_SERIAL;
5408 if (is_sdvo) {
5409 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5410 if (pixel_multiplier > 1) {
5411 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5412 }
a07d6787
EA		 5413 dpll |= DPLL_DVO_HIGH_SPEED;
5414 }
5415 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5416 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5417
a07d6787
EA		 5418 /* compute bitmask from p1 value */
5419 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5420 /* also FPA1 */
5421 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5422
5423 switch (clock.p2) {
5424 case 5:
5425 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5426 break;
5427 case 7:
5428 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5429 break;
5430 case 10:
5431 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5432 break;
5433 case 14:
5434 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5435 break;
79e53945
JB		 5436 }
5437
43565a06
KH		 5438 if (is_sdvo && is_tv)
5439 dpll |= PLL_REF_INPUT_TVCLKINBC;
5440 else if (is_tv)
79e53945 5441 /* XXX: just matching BIOS for now */
43565a06 5442 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5443 dpll |= 3;
a7615030 5444 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5445 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5446 else
5447 dpll |= PLL_REF_INPUT_DREFCLK;
5448
5449 /* setup pipeconf */
5eddb70b 5450 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5451
5452 /* Set up the display plane register */
5453 dspcntr = DISPPLANE_GAMMA_ENABLE;
5454
28c97730 5455 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 5456 drm_mode_debug_printmodeline(mode);
5457
5c5313c8
JB		 5458 /* PCH eDP needs FDI, but CPU eDP does not */
5459 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981
EA		 5460 I915_WRITE(PCH_FP0(pipe), fp);
5461 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 5462
fae14981 5463 POSTING_READ(PCH_DPLL(pipe));
79e53945
JB		 5464 udelay(150);
5465 }
5466
8db9d77b
ZW		 5467 /* enable transcoder DPLL */
5468 if (HAS_PCH_CPT(dev)) {
5469 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 5470 switch (pipe) {
5471 case 0:
5eddb70b 5472 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
9db4a9c7
JB		 5473 break;
5474 case 1:
5eddb70b 5475 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
9db4a9c7
JB		 5476 break;
5477 case 2:
5478 /* FIXME: manage transcoder PLLs? */
5479 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5480 break;
5481 default:
5482 BUG();
32f9d658 5483 }
8db9d77b 5484 I915_WRITE(PCH_DPLL_SEL, temp);
5eddb70b
CW		 5485
5486 POSTING_READ(PCH_DPLL_SEL);
8db9d77b
ZW		 5487 udelay(150);
5488 }
5489
79e53945
JB		 5490 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5491 * This is an exception to the general rule that mode_set doesn't turn
5492 * things on.
5493 */
5494 if (is_lvds) {
fae14981 5495 temp = I915_READ(PCH_LVDS);
5eddb70b 5496 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3
ZW		 5497 if (pipe == 1) {
5498 if (HAS_PCH_CPT(dev))
5eddb70b 5499 temp |= PORT_TRANS_B_SEL_CPT;
b3b095b3 5500 else
5eddb70b 5501 temp |= LVDS_PIPEB_SELECT;
b3b095b3
ZW		 5502 } else {
5503 if (HAS_PCH_CPT(dev))
5eddb70b 5504 temp &= ~PORT_TRANS_SEL_MASK;
b3b095b3 5505 else
5eddb70b 5506 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 5507 }
a3e17eb8 5508 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5509 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5510 /* Set the B0-B3 data pairs corresponding to whether we're going to
5511 * set the DPLLs for dual-channel mode or not.
5512 */
5513 if (clock.p2 == 7)
5eddb70b 5514 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5515 else
5eddb70b 5516 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5517
5518 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5519 * appropriately here, but we need to look more thoroughly into how
5520 * panels behave in the two modes.
5521 */
aa9b500d
BF		 5522 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5523 lvds_sync |= LVDS_HSYNC_POLARITY;
5524 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5525 lvds_sync |= LVDS_VSYNC_POLARITY;
5526 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5527 != lvds_sync) {
5528 char flags[2] = "-+";
5529 DRM_INFO("Changing LVDS panel from "
5530 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5531 flags[!(temp & LVDS_HSYNC_POLARITY)],
5532 flags[!(temp & LVDS_VSYNC_POLARITY)],
5533 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5534 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5535 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5536 temp |= lvds_sync;
5537 }
fae14981 5538 I915_WRITE(PCH_LVDS, temp);
79e53945 5539 }
434ed097 5540
8febb297
EA		 5541 pipeconf &= ~PIPECONF_DITHER_EN;
5542 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 5543 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297
EA		 5544 pipeconf |= PIPECONF_DITHER_EN;
5545 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
434ed097 5546 }
5c5313c8 5547 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
a4fc5ed6 5548 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5549 } else {
8db9d77b 5550 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5551 I915_WRITE(TRANSDATA_M1(pipe), 0);
5552 I915_WRITE(TRANSDATA_N1(pipe), 0);
5553 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5554 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5555 }
79e53945 5556
8febb297
EA		 5557 if (!has_edp_encoder ||
5558 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981 5559 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 5560
32f9d658 5561 /* Wait for the clocks to stabilize. */
fae14981 5562 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 5563 udelay(150);
5564
8febb297
EA		 5565 /* The pixel multiplier can only be updated once the
5566 * DPLL is enabled and the clocks are stable.
5567 *
5568 * So write it again.
5569 */
fae14981 5570 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 5571 }
79e53945 5572
5eddb70b 5573 intel_crtc->lowfreq_avail = false;
652c393a 5574 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 5575 I915_WRITE(PCH_FP1(pipe), fp2);
652c393a
JB		 5576 intel_crtc->lowfreq_avail = true;
5577 if (HAS_PIPE_CXSR(dev)) {
28c97730 5578 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 5579 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5580 }
5581 } else {
fae14981 5582 I915_WRITE(PCH_FP1(pipe), fp);
652c393a 5583 if (HAS_PIPE_CXSR(dev)) {
28c97730 5584 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5585 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5586 }
5587 }
5588
734b4157
KH		 5589 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5590 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5591 /* the chip adds 2 halflines automatically */
5592 adjusted_mode->crtc_vdisplay -= 1;
5593 adjusted_mode->crtc_vtotal -= 1;
5594 adjusted_mode->crtc_vblank_start -= 1;
5595 adjusted_mode->crtc_vblank_end -= 1;
5596 adjusted_mode->crtc_vsync_end -= 1;
5597 adjusted_mode->crtc_vsync_start -= 1;
5598 } else
5599 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5600
5eddb70b
CW		 5601 I915_WRITE(HTOTAL(pipe),
5602 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5603 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5604 I915_WRITE(HBLANK(pipe),
5605 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5606 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5607 I915_WRITE(HSYNC(pipe),
5608 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5609 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5610
5611 I915_WRITE(VTOTAL(pipe),
5612 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5613 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5614 I915_WRITE(VBLANK(pipe),
5615 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5616 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5617 I915_WRITE(VSYNC(pipe),
5618 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5619 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 5620
8febb297
EA		 5621 /* pipesrc controls the size that is scaled from, which should
5622 * always be the user's requested size.
79e53945 5623 */
5eddb70b
CW		 5624 I915_WRITE(PIPESRC(pipe),
5625 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5626
8febb297
EA		 5627 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5628 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5629 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5630 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 5631
8febb297
EA		 5632 if (has_edp_encoder &&
5633 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5634 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f
ZW		 5635 }
5636
5eddb70b
CW		 5637 I915_WRITE(PIPECONF(pipe), pipeconf);
5638 POSTING_READ(PIPECONF(pipe));
79e53945 5639
9d0498a2 5640 intel_wait_for_vblank(dev, pipe);
79e53945 5641
f00a3ddf 5642 if (IS_GEN5(dev)) {
553bd149
ZW		 5643 /* enable address swizzle for tiling buffer */
5644 temp = I915_READ(DISP_ARB_CTL);
5645 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5646 }
5647
5eddb70b 5648 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 5649 POSTING_READ(DSPCNTR(plane));
79e53945 5650
5c3b82e2 5651 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 5652
5653 intel_update_watermarks(dev);
5654
1f803ee5 5655 return ret;
79e53945
JB		 5656}
5657
f564048e
EA		 5658static int intel_crtc_mode_set(struct drm_crtc *crtc,
5659 struct drm_display_mode *mode,
5660 struct drm_display_mode *adjusted_mode,
5661 int x, int y,
5662 struct drm_framebuffer *old_fb)
5663{
5664 struct drm_device *dev = crtc->dev;
5665 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5667 int pipe = intel_crtc->pipe;
f564048e
EA		 5668 int ret;
5669
0b701d27 5670 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5671
f564048e
EA		 5672 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5673 x, y, old_fb);
7662c8bd 5674
79e53945 5675 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5676
120eced9
KP		 5677 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5678
1f803ee5 5679 return ret;
79e53945
JB		 5680}
5681
5682/** Loads the palette/gamma unit for the CRTC with the prepared values */
5683void intel_crtc_load_lut(struct drm_crtc *crtc)
5684{
5685 struct drm_device *dev = crtc->dev;
5686 struct drm_i915_private *dev_priv = dev->dev_private;
5687 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5688 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5689 int i;
5690
5691 /* The clocks have to be on to load the palette. */
5692 if (!crtc->enabled)
5693 return;
5694
f2b115e6 5695 /* use legacy palette for Ironlake */
bad720ff 5696 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5697 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5698
79e53945
JB		 5699 for (i = 0; i < 256; i++) {
5700 I915_WRITE(palreg + 4 * i,
5701 (intel_crtc->lut_r[i] << 16) |
5702 (intel_crtc->lut_g[i] << 8) |
5703 intel_crtc->lut_b[i]);
5704 }
5705}
5706
560b85bb
CW		 5707static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5708{
5709 struct drm_device *dev = crtc->dev;
5710 struct drm_i915_private *dev_priv = dev->dev_private;
5711 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5712 bool visible = base != 0;
5713 u32 cntl;
5714
5715 if (intel_crtc->cursor_visible == visible)
5716 return;
5717
9db4a9c7 5718 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5719 if (visible) {
5720 /* On these chipsets we can only modify the base whilst
5721 * the cursor is disabled.
5722 */
9db4a9c7 5723 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5724
5725 cntl &= ~(CURSOR_FORMAT_MASK);
5726 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5727 cntl |= CURSOR_ENABLE |
5728 CURSOR_GAMMA_ENABLE |
5729 CURSOR_FORMAT_ARGB;
5730 } else
5731 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5732 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5733
5734 intel_crtc->cursor_visible = visible;
5735}
5736
5737static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5738{
5739 struct drm_device *dev = crtc->dev;
5740 struct drm_i915_private *dev_priv = dev->dev_private;
5741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5742 int pipe = intel_crtc->pipe;
5743 bool visible = base != 0;
5744
5745 if (intel_crtc->cursor_visible != visible) {
548f245b 5746 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5747 if (base) {
5748 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5749 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5750 cntl |= pipe << 28; /* Connect to correct pipe */
5751 } else {
5752 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5753 cntl |= CURSOR_MODE_DISABLE;
5754 }
9db4a9c7 5755 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5756
5757 intel_crtc->cursor_visible = visible;
5758 }
5759 /* and commit changes on next vblank */
9db4a9c7 5760 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5761}
5762
cda4b7d3 5763/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5764static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5765 bool on)
cda4b7d3
CW		 5766{
5767 struct drm_device *dev = crtc->dev;
5768 struct drm_i915_private *dev_priv = dev->dev_private;
5769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5770 int pipe = intel_crtc->pipe;
5771 int x = intel_crtc->cursor_x;
5772 int y = intel_crtc->cursor_y;
560b85bb 5773 u32 base, pos;
cda4b7d3
CW		 5774 bool visible;
5775
5776 pos = 0;
5777
6b383a7f 5778 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5779 base = intel_crtc->cursor_addr;
5780 if (x > (int) crtc->fb->width)
5781 base = 0;
5782
5783 if (y > (int) crtc->fb->height)
5784 base = 0;
5785 } else
5786 base = 0;
5787
5788 if (x < 0) {
5789 if (x + intel_crtc->cursor_width < 0)
5790 base = 0;
5791
5792 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5793 x = -x;
5794 }
5795 pos |= x << CURSOR_X_SHIFT;
5796
5797 if (y < 0) {
5798 if (y + intel_crtc->cursor_height < 0)
5799 base = 0;
5800
5801 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5802 y = -y;
5803 }
5804 pos |= y << CURSOR_Y_SHIFT;
5805
5806 visible = base != 0;
560b85bb 5807 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5808 return;
5809
9db4a9c7 5810 I915_WRITE(CURPOS(pipe), pos);
560b85bb
CW		 5811 if (IS_845G(dev) || IS_I865G(dev))
5812 i845_update_cursor(crtc, base);
5813 else
5814 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 5815
5816 if (visible)
5817 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5818}
5819
79e53945 5820static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5821 struct drm_file *file,
79e53945
JB		 5822 uint32_t handle,
5823 uint32_t width, uint32_t height)
5824{
5825 struct drm_device *dev = crtc->dev;
5826 struct drm_i915_private *dev_priv = dev->dev_private;
5827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5828 struct drm_i915_gem_object *obj;
cda4b7d3 5829 uint32_t addr;
3f8bc370 5830 int ret;
79e53945 5831
28c97730 5832 DRM_DEBUG_KMS("\n");
79e53945
JB		 5833
5834 /* if we want to turn off the cursor ignore width and height */
5835 if (!handle) {
28c97730 5836 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5837 addr = 0;
05394f39 5838 obj = NULL;
5004417d 5839 mutex_lock(&dev->struct_mutex);
3f8bc370 5840 goto finish;
79e53945
JB		 5841 }
5842
5843 /* Currently we only support 64x64 cursors */
5844 if (width != 64 || height != 64) {
5845 DRM_ERROR("we currently only support 64x64 cursors\n");
5846 return -EINVAL;
5847 }
5848
05394f39 5849 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5850 if (&obj->base == NULL)
79e53945
JB		 5851 return -ENOENT;
5852
05394f39 5853 if (obj->base.size < width * height * 4) {
79e53945 5854 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5855 ret = -ENOMEM;
5856 goto fail;
79e53945
JB		 5857 }
5858
71acb5eb 5859 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5860 mutex_lock(&dev->struct_mutex);
b295d1b6 5861 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5862 if (obj->tiling_mode) {
5863 DRM_ERROR("cursor cannot be tiled\n");
5864 ret = -EINVAL;
5865 goto fail_locked;
5866 }
5867
2da3b9b9 5868 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 5869 if (ret) {
5870 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 5871 goto fail_locked;
e7b526bb
CW		 5872 }
5873
d9e86c0e
CW		 5874 ret = i915_gem_object_put_fence(obj);
5875 if (ret) {
2da3b9b9 5876 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 5877 goto fail_unpin;
5878 }
5879
05394f39 5880 addr = obj->gtt_offset;
71acb5eb 5881 } else {
6eeefaf3 5882 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5883 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5884 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5885 align);
71acb5eb
DA		 5886 if (ret) {
5887 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5888 goto fail_locked;
71acb5eb 5889 }
05394f39 5890 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5891 }
5892
a6c45cf0 5893 if (IS_GEN2(dev))
14b60391
JB		 5894 I915_WRITE(CURSIZE, (height << 12) | width);
5895
3f8bc370 5896 finish:
3f8bc370 5897 if (intel_crtc->cursor_bo) {
b295d1b6 5898 if (dev_priv->info->cursor_needs_physical) {
05394f39 5899 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5900 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5901 } else
5902 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5903 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5904 }
80824003 5905
7f9872e0 5906 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5907
5908 intel_crtc->cursor_addr = addr;
05394f39 5909 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5910 intel_crtc->cursor_width = width;
5911 intel_crtc->cursor_height = height;
5912
6b383a7f 5913 intel_crtc_update_cursor(crtc, true);
3f8bc370 5914
79e53945 5915 return 0;
e7b526bb 5916fail_unpin:
05394f39 5917 i915_gem_object_unpin(obj);
7f9872e0 5918fail_locked:
34b8686e 5919 mutex_unlock(&dev->struct_mutex);
bc9025bd 5920fail:
05394f39 5921 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5922 return ret;
79e53945
JB		 5923}
5924
5925static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5926{
79e53945 5927 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5928
cda4b7d3
CW		 5929 intel_crtc->cursor_x = x;
5930 intel_crtc->cursor_y = y;
652c393a 5931
6b383a7f 5932 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5933
5934 return 0;
5935}
5936
5937/** Sets the color ramps on behalf of RandR */
5938void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5939 u16 blue, int regno)
5940{
5941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5942
5943 intel_crtc->lut_r[regno] = red >> 8;
5944 intel_crtc->lut_g[regno] = green >> 8;
5945 intel_crtc->lut_b[regno] = blue >> 8;
5946}
5947
b8c00ac5
DA		 5948void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5949 u16 *blue, int regno)
5950{
5951 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5952
5953 *red = intel_crtc->lut_r[regno] << 8;
5954 *green = intel_crtc->lut_g[regno] << 8;
5955 *blue = intel_crtc->lut_b[regno] << 8;
5956}
5957
79e53945 5958static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5959 u16 *blue, uint32_t start, uint32_t size)
79e53945 5960{
7203425a 5961 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5963
7203425a 5964 for (i = start; i < end; i++) {
79e53945
JB		 5965 intel_crtc->lut_r[i] = red[i] >> 8;
5966 intel_crtc->lut_g[i] = green[i] >> 8;
5967 intel_crtc->lut_b[i] = blue[i] >> 8;
5968 }
5969
5970 intel_crtc_load_lut(crtc);
5971}
5972
5973/**
5974 * Get a pipe with a simple mode set on it for doing load-based monitor
5975 * detection.
5976 *
5977 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5978 * its requirements. The pipe will be connected to no other encoders.
79e53945 5979 *
c751ce4f 5980 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5981 * configured for it. In the future, it could choose to temporarily disable
5982 * some outputs to free up a pipe for its use.
5983 *
5984 * \return crtc, or NULL if no pipes are available.
5985 */
5986
5987/* VESA 640x480x72Hz mode to set on the pipe */
5988static struct drm_display_mode load_detect_mode = {
5989 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5990 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5991};
5992
d2dff872
CW		 5993static struct drm_framebuffer *
5994intel_framebuffer_create(struct drm_device *dev,
5995 struct drm_mode_fb_cmd *mode_cmd,
5996 struct drm_i915_gem_object *obj)
5997{
5998 struct intel_framebuffer *intel_fb;
5999 int ret;
6000
6001 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6002 if (!intel_fb) {
6003 drm_gem_object_unreference_unlocked(&obj->base);
6004 return ERR_PTR(-ENOMEM);
6005 }
6006
6007 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6008 if (ret) {
6009 drm_gem_object_unreference_unlocked(&obj->base);
6010 kfree(intel_fb);
6011 return ERR_PTR(ret);
6012 }
6013
6014 return &intel_fb->base;
6015}
6016
6017static u32
6018intel_framebuffer_pitch_for_width(int width, int bpp)
6019{
6020 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6021 return ALIGN(pitch, 64);
6022}
6023
6024static u32
6025intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6026{
6027 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6028 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6029}
6030
6031static struct drm_framebuffer *
6032intel_framebuffer_create_for_mode(struct drm_device *dev,
6033 struct drm_display_mode *mode,
6034 int depth, int bpp)
6035{
6036 struct drm_i915_gem_object *obj;
6037 struct drm_mode_fb_cmd mode_cmd;
6038
6039 obj = i915_gem_alloc_object(dev,
6040 intel_framebuffer_size_for_mode(mode, bpp));
6041 if (obj == NULL)
6042 return ERR_PTR(-ENOMEM);
6043
6044 mode_cmd.width = mode->hdisplay;
6045 mode_cmd.height = mode->vdisplay;
6046 mode_cmd.depth = depth;
6047 mode_cmd.bpp = bpp;
6048 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
6049
6050 return intel_framebuffer_create(dev, &mode_cmd, obj);
6051}
6052
6053static struct drm_framebuffer *
6054mode_fits_in_fbdev(struct drm_device *dev,
6055 struct drm_display_mode *mode)
6056{
6057 struct drm_i915_private *dev_priv = dev->dev_private;
6058 struct drm_i915_gem_object *obj;
6059 struct drm_framebuffer *fb;
6060
6061 if (dev_priv->fbdev == NULL)
6062 return NULL;
6063
6064 obj = dev_priv->fbdev->ifb.obj;
6065 if (obj == NULL)
6066 return NULL;
6067
6068 fb = &dev_priv->fbdev->ifb.base;
6069 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
6070 fb->bits_per_pixel))
6071 return NULL;
6072
6073 if (obj->base.size < mode->vdisplay * fb->pitch)
6074 return NULL;
6075
6076 return fb;
6077}
6078
7173188d
CW		 6079bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6080 struct drm_connector *connector,
6081 struct drm_display_mode *mode,
8261b191 6082 struct intel_load_detect_pipe *old)
79e53945
JB		 6083{
6084 struct intel_crtc *intel_crtc;
6085 struct drm_crtc *possible_crtc;
4ef69c7a 6086 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6087 struct drm_crtc *crtc = NULL;
6088 struct drm_device *dev = encoder->dev;
d2dff872 6089 struct drm_framebuffer *old_fb;
79e53945
JB		 6090 int i = -1;
6091
d2dff872
CW		 6092 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6093 connector->base.id, drm_get_connector_name(connector),
6094 encoder->base.id, drm_get_encoder_name(encoder));
6095
79e53945
JB		 6096 /*
6097 * Algorithm gets a little messy:
7a5e4805 6098 *
79e53945
JB		 6099 * - if the connector already has an assigned crtc, use it (but make
6100 * sure it's on first)
7a5e4805 6101 *
79e53945
JB		 6102 * - try to find the first unused crtc that can drive this connector,
6103 * and use that if we find one
79e53945
JB		 6104 */
6105
6106 /* See if we already have a CRTC for this connector */
6107 if (encoder->crtc) {
6108 crtc = encoder->crtc;
8261b191 6109
79e53945 6110 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6111 old->dpms_mode = intel_crtc->dpms_mode;
6112 old->load_detect_temp = false;
6113
6114 /* Make sure the crtc and connector are running */
79e53945 6115 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 6116 struct drm_encoder_helper_funcs *encoder_funcs;
6117 struct drm_crtc_helper_funcs *crtc_funcs;
6118
79e53945
JB		 6119 crtc_funcs = crtc->helper_private;
6120 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 6121
6122 encoder_funcs = encoder->helper_private;
79e53945
JB		 6123 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6124 }
8261b191 6125
7173188d 6126 return true;
79e53945
JB		 6127 }
6128
6129 /* Find an unused one (if possible) */
6130 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6131 i++;
6132 if (!(encoder->possible_crtcs & (1 << i)))
6133 continue;
6134 if (!possible_crtc->enabled) {
6135 crtc = possible_crtc;
6136 break;
6137 }
79e53945
JB		 6138 }
6139
6140 /*
6141 * If we didn't find an unused CRTC, don't use any.
6142 */
6143 if (!crtc) {
7173188d
CW		 6144 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6145 return false;
79e53945
JB		 6146 }
6147
6148 encoder->crtc = crtc;
c1c43977 6149 connector->encoder = encoder;
79e53945
JB		 6150
6151 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6152 old->dpms_mode = intel_crtc->dpms_mode;
6153 old->load_detect_temp = true;
d2dff872 6154 old->release_fb = NULL;
79e53945 6155
6492711d
CW		 6156 if (!mode)
6157 mode = &load_detect_mode;
79e53945 6158
d2dff872
CW		 6159 old_fb = crtc->fb;
6160
6161 /* We need a framebuffer large enough to accommodate all accesses
6162 * that the plane may generate whilst we perform load detection.
6163 * We can not rely on the fbcon either being present (we get called
6164 * during its initialisation to detect all boot displays, or it may
6165 * not even exist) or that it is large enough to satisfy the
6166 * requested mode.
6167 */
6168 crtc->fb = mode_fits_in_fbdev(dev, mode);
6169 if (crtc->fb == NULL) {
6170 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6171 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6172 old->release_fb = crtc->fb;
6173 } else
6174 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6175 if (IS_ERR(crtc->fb)) {
6176 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6177 crtc->fb = old_fb;
6178 return false;
79e53945 6179 }
79e53945 6180
d2dff872 6181 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 6182 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6183 if (old->release_fb)
6184 old->release_fb->funcs->destroy(old->release_fb);
6185 crtc->fb = old_fb;
6492711d 6186 return false;
79e53945 6187 }
7173188d 6188
79e53945 6189 /* let the connector get through one full cycle before testing */
9d0498a2 6190 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6191
7173188d 6192 return true;
79e53945
JB		 6193}
6194
c1c43977 6195void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 6196 struct drm_connector *connector,
6197 struct intel_load_detect_pipe *old)
79e53945 6198{
4ef69c7a 6199 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6200 struct drm_device *dev = encoder->dev;
6201 struct drm_crtc *crtc = encoder->crtc;
6202 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6203 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6204
d2dff872
CW		 6205 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6206 connector->base.id, drm_get_connector_name(connector),
6207 encoder->base.id, drm_get_encoder_name(encoder));
6208
8261b191 6209 if (old->load_detect_temp) {
c1c43977 6210 connector->encoder = NULL;
79e53945 6211 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 6212
6213 if (old->release_fb)
6214 old->release_fb->funcs->destroy(old->release_fb);
6215
0622a53c 6216 return;
79e53945
JB		 6217 }
6218
c751ce4f 6219 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 6220 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6221 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 6222 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 6223 }
6224}
6225
6226/* Returns the clock of the currently programmed mode of the given pipe. */
6227static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6228{
6229 struct drm_i915_private *dev_priv = dev->dev_private;
6230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6231 int pipe = intel_crtc->pipe;
548f245b 6232 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6233 u32 fp;
6234 intel_clock_t clock;
6235
6236 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6237 fp = I915_READ(FP0(pipe));
79e53945 6238 else
39adb7a5 6239 fp = I915_READ(FP1(pipe));
79e53945
JB		 6240
6241 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6242 if (IS_PINEVIEW(dev)) {
6243 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6244 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6245 } else {
6246 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6247 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6248 }
6249
a6c45cf0 6250 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6251 if (IS_PINEVIEW(dev))
6252 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6253 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6254 else
6255 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6256 DPLL_FPA01_P1_POST_DIV_SHIFT);
6257
6258 switch (dpll & DPLL_MODE_MASK) {
6259 case DPLLB_MODE_DAC_SERIAL:
6260 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6261 5 : 10;
6262 break;
6263 case DPLLB_MODE_LVDS:
6264 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6265 7 : 14;
6266 break;
6267 default:
28c97730 6268 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6269 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6270 return 0;
6271 }
6272
6273 /* XXX: Handle the 100Mhz refclk */
2177832f 6274 intel_clock(dev, 96000, &clock);
79e53945
JB		 6275 } else {
6276 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6277
6278 if (is_lvds) {
6279 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6280 DPLL_FPA01_P1_POST_DIV_SHIFT);
6281 clock.p2 = 14;
6282
6283 if ((dpll & PLL_REF_INPUT_MASK) ==
6284 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6285 /* XXX: might not be 66MHz */
2177832f 6286 intel_clock(dev, 66000, &clock);
79e53945 6287 } else
2177832f 6288 intel_clock(dev, 48000, &clock);
79e53945
JB		 6289 } else {
6290 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6291 clock.p1 = 2;
6292 else {
6293 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6294 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6295 }
6296 if (dpll & PLL_P2_DIVIDE_BY_4)
6297 clock.p2 = 4;
6298 else
6299 clock.p2 = 2;
6300
2177832f 6301 intel_clock(dev, 48000, &clock);
79e53945
JB		 6302 }
6303 }
6304
6305 /* XXX: It would be nice to validate the clocks, but we can't reuse
6306 * i830PllIsValid() because it relies on the xf86_config connector
6307 * configuration being accurate, which it isn't necessarily.
6308 */
6309
6310 return clock.dot;
6311}
6312
6313/** Returns the currently programmed mode of the given pipe. */
6314struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6315 struct drm_crtc *crtc)
6316{
548f245b 6317 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 6318 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6319 int pipe = intel_crtc->pipe;
6320 struct drm_display_mode *mode;
548f245b
JB		 6321 int htot = I915_READ(HTOTAL(pipe));
6322 int hsync = I915_READ(HSYNC(pipe));
6323 int vtot = I915_READ(VTOTAL(pipe));
6324 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 6325
6326 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6327 if (!mode)
6328 return NULL;
6329
6330 mode->clock = intel_crtc_clock_get(dev, crtc);
6331 mode->hdisplay = (htot & 0xffff) + 1;
6332 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6333 mode->hsync_start = (hsync & 0xffff) + 1;
6334 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6335 mode->vdisplay = (vtot & 0xffff) + 1;
6336 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6337 mode->vsync_start = (vsync & 0xffff) + 1;
6338 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6339
6340 drm_mode_set_name(mode);
6341 drm_mode_set_crtcinfo(mode, 0);
6342
6343 return mode;
6344}
6345
652c393a
JB		 6346#define GPU_IDLE_TIMEOUT 500 /* ms */
6347
6348/* When this timer fires, we've been idle for awhile */
6349static void intel_gpu_idle_timer(unsigned long arg)
6350{
6351 struct drm_device *dev = (struct drm_device *)arg;
6352 drm_i915_private_t *dev_priv = dev->dev_private;
6353
ff7ea4c0
CW		 6354 if (!list_empty(&dev_priv->mm.active_list)) {
6355 /* Still processing requests, so just re-arm the timer. */
6356 mod_timer(&dev_priv->idle_timer, jiffies +
6357 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6358 return;
6359 }
652c393a 6360
ff7ea4c0 6361 dev_priv->busy = false;
01dfba93 6362 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6363}
6364
652c393a
JB		 6365#define CRTC_IDLE_TIMEOUT 1000 /* ms */
6366
6367static void intel_crtc_idle_timer(unsigned long arg)
6368{
6369 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6370 struct drm_crtc *crtc = &intel_crtc->base;
6371 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 6372 struct intel_framebuffer *intel_fb;
652c393a 6373
ff7ea4c0
CW		 6374 intel_fb = to_intel_framebuffer(crtc->fb);
6375 if (intel_fb && intel_fb->obj->active) {
6376 /* The framebuffer is still being accessed by the GPU. */
6377 mod_timer(&intel_crtc->idle_timer, jiffies +
6378 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6379 return;
6380 }
652c393a 6381
ff7ea4c0 6382 intel_crtc->busy = false;
01dfba93 6383 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6384}
6385
3dec0095 6386static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6387{
6388 struct drm_device *dev = crtc->dev;
6389 drm_i915_private_t *dev_priv = dev->dev_private;
6390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6391 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6392 int dpll_reg = DPLL(pipe);
6393 int dpll;
652c393a 6394
bad720ff 6395 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6396 return;
6397
6398 if (!dev_priv->lvds_downclock_avail)
6399 return;
6400
dbdc6479 6401 dpll = I915_READ(dpll_reg);
652c393a 6402 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6403 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a
JB		 6404
6405 /* Unlock panel regs */
dbdc6479
JB		 6406 I915_WRITE(PP_CONTROL,
6407 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
652c393a
JB		 6408
6409 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6410 I915_WRITE(dpll_reg, dpll);
9d0498a2 6411 intel_wait_for_vblank(dev, pipe);
dbdc6479 6412
652c393a
JB		 6413 dpll = I915_READ(dpll_reg);
6414 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6415 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 6416
6417 /* ...and lock them again */
6418 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6419 }
6420
6421 /* Schedule downclock */
3dec0095
DV		 6422 mod_timer(&intel_crtc->idle_timer, jiffies +
6423 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 6424}
6425
6426static void intel_decrease_pllclock(struct drm_crtc *crtc)
6427{
6428 struct drm_device *dev = crtc->dev;
6429 drm_i915_private_t *dev_priv = dev->dev_private;
6430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6431 int pipe = intel_crtc->pipe;
9db4a9c7 6432 int dpll_reg = DPLL(pipe);
652c393a
JB		 6433 int dpll = I915_READ(dpll_reg);
6434
bad720ff 6435 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6436 return;
6437
6438 if (!dev_priv->lvds_downclock_avail)
6439 return;
6440
6441 /*
6442 * Since this is called by a timer, we should never get here in
6443 * the manual case.
6444 */
6445 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 6446 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a
JB		 6447
6448 /* Unlock panel regs */
4a655f04
JB		 6449 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6450 PANEL_UNLOCK_REGS);
652c393a
JB		 6451
6452 dpll |= DISPLAY_RATE_SELECT_FPA1;
6453 I915_WRITE(dpll_reg, dpll);
9d0498a2 6454 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6455 dpll = I915_READ(dpll_reg);
6456 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6457 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6458
6459 /* ...and lock them again */
6460 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6461 }
6462
6463}
6464
6465/**
6466 * intel_idle_update - adjust clocks for idleness
6467 * @work: work struct
6468 *
6469 * Either the GPU or display (or both) went idle. Check the busy status
6470 * here and adjust the CRTC and GPU clocks as necessary.
6471 */
6472static void intel_idle_update(struct work_struct *work)
6473{
6474 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6475 idle_work);
6476 struct drm_device *dev = dev_priv->dev;
6477 struct drm_crtc *crtc;
6478 struct intel_crtc *intel_crtc;
6479
6480 if (!i915_powersave)
6481 return;
6482
6483 mutex_lock(&dev->struct_mutex);
6484
7648fa99
JB		 6485 i915_update_gfx_val(dev_priv);
6486
652c393a
JB		 6487 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6488 /* Skip inactive CRTCs */
6489 if (!crtc->fb)
6490 continue;
6491
6492 intel_crtc = to_intel_crtc(crtc);
6493 if (!intel_crtc->busy)
6494 intel_decrease_pllclock(crtc);
6495 }
6496
45ac22c8 6497
652c393a
JB		 6498 mutex_unlock(&dev->struct_mutex);
6499}
6500
6501/**
6502 * intel_mark_busy - mark the GPU and possibly the display busy
6503 * @dev: drm device
6504 * @obj: object we're operating on
6505 *
6506 * Callers can use this function to indicate that the GPU is busy processing
6507 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6508 * buffer), we'll also mark the display as busy, so we know to increase its
6509 * clock frequency.
6510 */
05394f39 6511void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 6512{
6513 drm_i915_private_t *dev_priv = dev->dev_private;
6514 struct drm_crtc *crtc = NULL;
6515 struct intel_framebuffer *intel_fb;
6516 struct intel_crtc *intel_crtc;
6517
5e17ee74
ZW		 6518 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6519 return;
6520
18b2190c 6521 if (!dev_priv->busy)
28cf798f 6522 dev_priv->busy = true;
18b2190c 6523 else
28cf798f
CW		 6524 mod_timer(&dev_priv->idle_timer, jiffies +
6525 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 6526
6527 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6528 if (!crtc->fb)
6529 continue;
6530
6531 intel_crtc = to_intel_crtc(crtc);
6532 intel_fb = to_intel_framebuffer(crtc->fb);
6533 if (intel_fb->obj == obj) {
6534 if (!intel_crtc->busy) {
6535 /* Non-busy -> busy, upclock */
3dec0095 6536 intel_increase_pllclock(crtc);
652c393a
JB		 6537 intel_crtc->busy = true;
6538 } else {
6539 /* Busy -> busy, put off timer */
6540 mod_timer(&intel_crtc->idle_timer, jiffies +
6541 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6542 }
6543 }
6544 }
6545}
6546
79e53945
JB		 6547static void intel_crtc_destroy(struct drm_crtc *crtc)
6548{
6549 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6550 struct drm_device *dev = crtc->dev;
6551 struct intel_unpin_work *work;
6552 unsigned long flags;
6553
6554 spin_lock_irqsave(&dev->event_lock, flags);
6555 work = intel_crtc->unpin_work;
6556 intel_crtc->unpin_work = NULL;
6557 spin_unlock_irqrestore(&dev->event_lock, flags);
6558
6559 if (work) {
6560 cancel_work_sync(&work->work);
6561 kfree(work);
6562 }
79e53945
JB		 6563
6564 drm_crtc_cleanup(crtc);
67e77c5a 6565
79e53945
JB		 6566 kfree(intel_crtc);
6567}
6568
6b95a207
KH		 6569static void intel_unpin_work_fn(struct work_struct *__work)
6570{
6571 struct intel_unpin_work *work =
6572 container_of(__work, struct intel_unpin_work, work);
6573
6574 mutex_lock(&work->dev->struct_mutex);
b1b87f6b 6575 i915_gem_object_unpin(work->old_fb_obj);
05394f39
CW		 6576 drm_gem_object_unreference(&work->pending_flip_obj->base);
6577 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6578
7782de3b 6579 intel_update_fbc(work->dev);
6b95a207
KH		 6580 mutex_unlock(&work->dev->struct_mutex);
6581 kfree(work);
6582}
6583
1afe3e9d 6584static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6585 struct drm_crtc *crtc)
6b95a207
KH		 6586{
6587 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6588 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6589 struct intel_unpin_work *work;
05394f39 6590 struct drm_i915_gem_object *obj;
6b95a207 6591 struct drm_pending_vblank_event *e;
49b14a5c 6592 struct timeval tnow, tvbl;
6b95a207
KH		 6593 unsigned long flags;
6594
6595 /* Ignore early vblank irqs */
6596 if (intel_crtc == NULL)
6597 return;
6598
49b14a5c
MK		 6599 do_gettimeofday(&tnow);
6600
6b95a207
KH		 6601 spin_lock_irqsave(&dev->event_lock, flags);
6602 work = intel_crtc->unpin_work;
6603 if (work == NULL || !work->pending) {
6604 spin_unlock_irqrestore(&dev->event_lock, flags);
6605 return;
6606 }
6607
6608 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6609
6610 if (work->event) {
6611 e = work->event;
49b14a5c 6612 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6613
6614 /* Called before vblank count and timestamps have
6615 * been updated for the vblank interval of flip
6616 * completion? Need to increment vblank count and
6617 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6618 * to account for this. We assume this happened if we
6619 * get called over 0.9 frame durations after the last
6620 * timestamped vblank.
6621 *
6622 * This calculation can not be used with vrefresh rates
6623 * below 5Hz (10Hz to be on the safe side) without
6624 * promoting to 64 integers.
0af7e4df 6625 */
49b14a5c
MK		 6626 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6627 9 * crtc->framedur_ns) {
0af7e4df 6628 e->event.sequence++;
49b14a5c
MK		 6629 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6630 crtc->framedur_ns);
0af7e4df
MK		 6631 }
6632
49b14a5c
MK		 6633 e->event.tv_sec = tvbl.tv_sec;
6634 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6635
6b95a207
KH		 6636 list_add_tail(&e->base.link,
6637 &e->base.file_priv->event_list);
6638 wake_up_interruptible(&e->base.file_priv->event_wait);
6639 }
6640
0af7e4df
MK		 6641 drm_vblank_put(dev, intel_crtc->pipe);
6642
6b95a207
KH		 6643 spin_unlock_irqrestore(&dev->event_lock, flags);
6644
05394f39 6645 obj = work->old_fb_obj;
d9e86c0e 6646
e59f2bac 6647 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6648 &obj->pending_flip.counter);
6649 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6650 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6651
6b95a207 6652 schedule_work(&work->work);
e5510fac
JB		 6653
6654 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6655}
6656
1afe3e9d
JB		 6657void intel_finish_page_flip(struct drm_device *dev, int pipe)
6658{
6659 drm_i915_private_t *dev_priv = dev->dev_private;
6660 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6661
49b14a5c 6662 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6663}
6664
6665void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6666{
6667 drm_i915_private_t *dev_priv = dev->dev_private;
6668 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6669
49b14a5c 6670 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6671}
6672
6b95a207
KH		 6673void intel_prepare_page_flip(struct drm_device *dev, int plane)
6674{
6675 drm_i915_private_t *dev_priv = dev->dev_private;
6676 struct intel_crtc *intel_crtc =
6677 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6678 unsigned long flags;
6679
6680 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6681 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6682 if ((++intel_crtc->unpin_work->pending) > 1)
6683 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6684 } else {
6685 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6686 }
6b95a207
KH		 6687 spin_unlock_irqrestore(&dev->event_lock, flags);
6688}
6689
8c9f3aaf
JB		 6690static int intel_gen2_queue_flip(struct drm_device *dev,
6691 struct drm_crtc *crtc,
6692 struct drm_framebuffer *fb,
6693 struct drm_i915_gem_object *obj)
6694{
6695 struct drm_i915_private *dev_priv = dev->dev_private;
6696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6697 unsigned long offset;
6698 u32 flip_mask;
6699 int ret;
6700
6701 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6702 if (ret)
6703 goto out;
6704
6705 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6706 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6707
6708 ret = BEGIN_LP_RING(6);
6709 if (ret)
6710 goto out;
6711
6712 /* Can't queue multiple flips, so wait for the previous
6713 * one to finish before executing the next.
6714 */
6715 if (intel_crtc->plane)
6716 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6717 else
6718 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6719 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6720 OUT_RING(MI_NOOP);
6721 OUT_RING(MI_DISPLAY_FLIP |
6722 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6723 OUT_RING(fb->pitch);
6724 OUT_RING(obj->gtt_offset + offset);
6725 OUT_RING(MI_NOOP);
6726 ADVANCE_LP_RING();
6727out:
6728 return ret;
6729}
6730
6731static int intel_gen3_queue_flip(struct drm_device *dev,
6732 struct drm_crtc *crtc,
6733 struct drm_framebuffer *fb,
6734 struct drm_i915_gem_object *obj)
6735{
6736 struct drm_i915_private *dev_priv = dev->dev_private;
6737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6738 unsigned long offset;
6739 u32 flip_mask;
6740 int ret;
6741
6742 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6743 if (ret)
6744 goto out;
6745
6746 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6747 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6748
6749 ret = BEGIN_LP_RING(6);
6750 if (ret)
6751 goto out;
6752
6753 if (intel_crtc->plane)
6754 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6755 else
6756 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6757 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6758 OUT_RING(MI_NOOP);
6759 OUT_RING(MI_DISPLAY_FLIP_I915 |
6760 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6761 OUT_RING(fb->pitch);
6762 OUT_RING(obj->gtt_offset + offset);
6763 OUT_RING(MI_NOOP);
6764
6765 ADVANCE_LP_RING();
6766out:
6767 return ret;
6768}
6769
6770static int intel_gen4_queue_flip(struct drm_device *dev,
6771 struct drm_crtc *crtc,
6772 struct drm_framebuffer *fb,
6773 struct drm_i915_gem_object *obj)
6774{
6775 struct drm_i915_private *dev_priv = dev->dev_private;
6776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6777 uint32_t pf, pipesrc;
6778 int ret;
6779
6780 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6781 if (ret)
6782 goto out;
6783
6784 ret = BEGIN_LP_RING(4);
6785 if (ret)
6786 goto out;
6787
6788 /* i965+ uses the linear or tiled offsets from the
6789 * Display Registers (which do not change across a page-flip)
6790 * so we need only reprogram the base address.
6791 */
6792 OUT_RING(MI_DISPLAY_FLIP |
6793 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6794 OUT_RING(fb->pitch);
6795 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6796
6797 /* XXX Enabling the panel-fitter across page-flip is so far
6798 * untested on non-native modes, so ignore it for now.
6799 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6800 */
6801 pf = 0;
6802 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6803 OUT_RING(pf | pipesrc);
6804 ADVANCE_LP_RING();
6805out:
6806 return ret;
6807}
6808
6809static int intel_gen6_queue_flip(struct drm_device *dev,
6810 struct drm_crtc *crtc,
6811 struct drm_framebuffer *fb,
6812 struct drm_i915_gem_object *obj)
6813{
6814 struct drm_i915_private *dev_priv = dev->dev_private;
6815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6816 uint32_t pf, pipesrc;
6817 int ret;
6818
6819 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6820 if (ret)
6821 goto out;
6822
6823 ret = BEGIN_LP_RING(4);
6824 if (ret)
6825 goto out;
6826
6827 OUT_RING(MI_DISPLAY_FLIP |
6828 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6829 OUT_RING(fb->pitch | obj->tiling_mode);
6830 OUT_RING(obj->gtt_offset);
6831
6832 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6833 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6834 OUT_RING(pf | pipesrc);
6835 ADVANCE_LP_RING();
6836out:
6837 return ret;
6838}
6839
7c9017e5
JB		 6840/*
6841 * On gen7 we currently use the blit ring because (in early silicon at least)
6842 * the render ring doesn't give us interrpts for page flip completion, which
6843 * means clients will hang after the first flip is queued. Fortunately the
6844 * blit ring generates interrupts properly, so use it instead.
6845 */
6846static int intel_gen7_queue_flip(struct drm_device *dev,
6847 struct drm_crtc *crtc,
6848 struct drm_framebuffer *fb,
6849 struct drm_i915_gem_object *obj)
6850{
6851 struct drm_i915_private *dev_priv = dev->dev_private;
6852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6853 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6854 int ret;
6855
6856 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6857 if (ret)
6858 goto out;
6859
6860 ret = intel_ring_begin(ring, 4);
6861 if (ret)
6862 goto out;
6863
6864 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6865 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6866 intel_ring_emit(ring, (obj->gtt_offset));
6867 intel_ring_emit(ring, (MI_NOOP));
6868 intel_ring_advance(ring);
6869out:
6870 return ret;
6871}
6872
8c9f3aaf
JB		 6873static int intel_default_queue_flip(struct drm_device *dev,
6874 struct drm_crtc *crtc,
6875 struct drm_framebuffer *fb,
6876 struct drm_i915_gem_object *obj)
6877{
6878 return -ENODEV;
6879}
6880
6b95a207
KH		 6881static int intel_crtc_page_flip(struct drm_crtc *crtc,
6882 struct drm_framebuffer *fb,
6883 struct drm_pending_vblank_event *event)
6884{
6885 struct drm_device *dev = crtc->dev;
6886 struct drm_i915_private *dev_priv = dev->dev_private;
6887 struct intel_framebuffer *intel_fb;
05394f39 6888 struct drm_i915_gem_object *obj;
6b95a207
KH		 6889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6890 struct intel_unpin_work *work;
8c9f3aaf 6891 unsigned long flags;
52e68630 6892 int ret;
6b95a207
KH		 6893
6894 work = kzalloc(sizeof *work, GFP_KERNEL);
6895 if (work == NULL)
6896 return -ENOMEM;
6897
6b95a207
KH		 6898 work->event = event;
6899 work->dev = crtc->dev;
6900 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6901 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6902 INIT_WORK(&work->work, intel_unpin_work_fn);
6903
6904 /* We borrow the event spin lock for protecting unpin_work */
6905 spin_lock_irqsave(&dev->event_lock, flags);
6906 if (intel_crtc->unpin_work) {
6907 spin_unlock_irqrestore(&dev->event_lock, flags);
6908 kfree(work);
468f0b44
CW		 6909
6910 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6911 return -EBUSY;
6912 }
6913 intel_crtc->unpin_work = work;
6914 spin_unlock_irqrestore(&dev->event_lock, flags);
6915
6916 intel_fb = to_intel_framebuffer(fb);
6917 obj = intel_fb->obj;
6918
468f0b44 6919 mutex_lock(&dev->struct_mutex);
6b95a207 6920
75dfca80 6921 /* Reference the objects for the scheduled work. */
05394f39
CW		 6922 drm_gem_object_reference(&work->old_fb_obj->base);
6923 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6924
6925 crtc->fb = fb;
96b099fd
CW		 6926
6927 ret = drm_vblank_get(dev, intel_crtc->pipe);
6928 if (ret)
6929 goto cleanup_objs;
6930
e1f99ce6 6931 work->pending_flip_obj = obj;
e1f99ce6 6932
4e5359cd
SF		 6933 work->enable_stall_check = true;
6934
e1f99ce6
CW		 6935 /* Block clients from rendering to the new back buffer until
6936 * the flip occurs and the object is no longer visible.
6937 */
05394f39 6938 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6939
8c9f3aaf
JB		 6940 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6941 if (ret)
6942 goto cleanup_pending;
6b95a207 6943
7782de3b 6944 intel_disable_fbc(dev);
6b95a207
KH		 6945 mutex_unlock(&dev->struct_mutex);
6946
e5510fac
JB		 6947 trace_i915_flip_request(intel_crtc->plane, obj);
6948
6b95a207 6949 return 0;
96b099fd 6950
8c9f3aaf
JB		 6951cleanup_pending:
6952 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
96b099fd 6953cleanup_objs:
05394f39
CW		 6954 drm_gem_object_unreference(&work->old_fb_obj->base);
6955 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6956 mutex_unlock(&dev->struct_mutex);
6957
6958 spin_lock_irqsave(&dev->event_lock, flags);
6959 intel_crtc->unpin_work = NULL;
6960 spin_unlock_irqrestore(&dev->event_lock, flags);
6961
6962 kfree(work);
6963
6964 return ret;
6b95a207
KH		 6965}
6966
47f1c6c9
CW		 6967static void intel_sanitize_modesetting(struct drm_device *dev,
6968 int pipe, int plane)
6969{
6970 struct drm_i915_private *dev_priv = dev->dev_private;
6971 u32 reg, val;
6972
6973 if (HAS_PCH_SPLIT(dev))
6974 return;
6975
6976 /* Who knows what state these registers were left in by the BIOS or
6977 * grub?
6978 *
6979 * If we leave the registers in a conflicting state (e.g. with the
6980 * display plane reading from the other pipe than the one we intend
6981 * to use) then when we attempt to teardown the active mode, we will
6982 * not disable the pipes and planes in the correct order -- leaving
6983 * a plane reading from a disabled pipe and possibly leading to
6984 * undefined behaviour.
6985 */
6986
6987 reg = DSPCNTR(plane);
6988 val = I915_READ(reg);
6989
6990 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6991 return;
6992 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6993 return;
6994
6995 /* This display plane is active and attached to the other CPU pipe. */
6996 pipe = !pipe;
6997
6998 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6999 intel_disable_plane(dev_priv, plane, pipe);
7000 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 7001}
79e53945 7002
f6e5b160
CW		 7003static void intel_crtc_reset(struct drm_crtc *crtc)
7004{
7005 struct drm_device *dev = crtc->dev;
7006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7007
7008 /* Reset flags back to the 'unknown' status so that they
7009 * will be correctly set on the initial modeset.
7010 */
7011 intel_crtc->dpms_mode = -1;
7012
7013 /* We need to fix up any BIOS configuration that conflicts with
7014 * our expectations.
7015 */
7016 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7017}
7018
7019static struct drm_crtc_helper_funcs intel_helper_funcs = {
7020 .dpms = intel_crtc_dpms,
7021 .mode_fixup = intel_crtc_mode_fixup,
7022 .mode_set = intel_crtc_mode_set,
7023 .mode_set_base = intel_pipe_set_base,
7024 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7025 .load_lut = intel_crtc_load_lut,
7026 .disable = intel_crtc_disable,
7027};
7028
7029static const struct drm_crtc_funcs intel_crtc_funcs = {
7030 .reset = intel_crtc_reset,
7031 .cursor_set = intel_crtc_cursor_set,
7032 .cursor_move = intel_crtc_cursor_move,
7033 .gamma_set = intel_crtc_gamma_set,
7034 .set_config = drm_crtc_helper_set_config,
7035 .destroy = intel_crtc_destroy,
7036 .page_flip = intel_crtc_page_flip,
7037};
7038
b358d0a6 7039static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 7040{
22fd0fab 7041 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 7042 struct intel_crtc *intel_crtc;
7043 int i;
7044
7045 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7046 if (intel_crtc == NULL)
7047 return;
7048
7049 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7050
7051 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7052 for (i = 0; i < 256; i++) {
7053 intel_crtc->lut_r[i] = i;
7054 intel_crtc->lut_g[i] = i;
7055 intel_crtc->lut_b[i] = i;
7056 }
7057
80824003
JB		 7058 /* Swap pipes & planes for FBC on pre-965 */
7059 intel_crtc->pipe = pipe;
7060 intel_crtc->plane = pipe;
e2e767ab 7061 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7062 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7063 intel_crtc->plane = !pipe;
80824003
JB		 7064 }
7065
22fd0fab
JB		 7066 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7067 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7068 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7069 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7070
5d1d0cc8 7071 intel_crtc_reset(&intel_crtc->base);
04dbff52 7072 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 7073 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 7074
7075 if (HAS_PCH_SPLIT(dev)) {
7076 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7077 intel_helper_funcs.commit = ironlake_crtc_commit;
7078 } else {
7079 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7080 intel_helper_funcs.commit = i9xx_crtc_commit;
7081 }
7082
79e53945
JB		 7083 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7084
652c393a
JB		 7085 intel_crtc->busy = false;
7086
7087 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7088 (unsigned long)intel_crtc);
79e53945
JB		 7089}
7090
08d7b3d1 7091int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7092 struct drm_file *file)
08d7b3d1
CW		 7093{
7094 drm_i915_private_t *dev_priv = dev->dev_private;
7095 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 7096 struct drm_mode_object *drmmode_obj;
7097 struct intel_crtc *crtc;
08d7b3d1
CW		 7098
7099 if (!dev_priv) {
7100 DRM_ERROR("called with no initialization\n");
7101 return -EINVAL;
7102 }
7103
c05422d5
DV		 7104 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7105 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7106
c05422d5 7107 if (!drmmode_obj) {
08d7b3d1
CW		 7108 DRM_ERROR("no such CRTC id\n");
7109 return -EINVAL;
7110 }
7111
c05422d5
DV		 7112 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7113 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7114
c05422d5 7115 return 0;
08d7b3d1
CW		 7116}
7117
c5e4df33 7118static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 7119{
4ef69c7a 7120 struct intel_encoder *encoder;
79e53945 7121 int index_mask = 0;
79e53945
JB		 7122 int entry = 0;
7123
4ef69c7a
CW		 7124 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7125 if (type_mask & encoder->clone_mask)
79e53945
JB		 7126 index_mask |= (1 << entry);
7127 entry++;
7128 }
4ef69c7a 7129
79e53945
JB		 7130 return index_mask;
7131}
7132
4d302442
CW		 7133static bool has_edp_a(struct drm_device *dev)
7134{
7135 struct drm_i915_private *dev_priv = dev->dev_private;
7136
7137 if (!IS_MOBILE(dev))
7138 return false;
7139
7140 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7141 return false;
7142
7143 if (IS_GEN5(dev) &&
7144 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7145 return false;
7146
7147 return true;
7148}
7149
79e53945
JB		 7150static void intel_setup_outputs(struct drm_device *dev)
7151{
725e30ad 7152 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 7153 struct intel_encoder *encoder;
cb0953d7 7154 bool dpd_is_edp = false;
c5d1b51d 7155 bool has_lvds = false;
79e53945 7156
541998a1 7157 if (IS_MOBILE(dev) && !IS_I830(dev))
c5d1b51d
CW		 7158 has_lvds = intel_lvds_init(dev);
7159 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7160 /* disable the panel fitter on everything but LVDS */
7161 I915_WRITE(PFIT_CONTROL, 0);
7162 }
79e53945 7163
bad720ff 7164 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 7165 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 7166
4d302442 7167 if (has_edp_a(dev))
32f9d658
ZW		 7168 intel_dp_init(dev, DP_A);
7169
cb0953d7
AJ		 7170 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7171 intel_dp_init(dev, PCH_DP_D);
7172 }
7173
7174 intel_crt_init(dev);
7175
7176 if (HAS_PCH_SPLIT(dev)) {
7177 int found;
7178
30ad48b7 7179 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca
ZY		 7180 /* PCH SDVOB multiplex with HDMIB */
7181 found = intel_sdvo_init(dev, PCH_SDVOB);
30ad48b7
ZW		 7182 if (!found)
7183 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 7184 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7185 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 7186 }
7187
7188 if (I915_READ(HDMIC) & PORT_DETECTED)
7189 intel_hdmi_init(dev, HDMIC);
7190
7191 if (I915_READ(HDMID) & PORT_DETECTED)
7192 intel_hdmi_init(dev, HDMID);
7193
5eb08b69
ZW		 7194 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7195 intel_dp_init(dev, PCH_DP_C);
7196
cb0953d7 7197 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 7198 intel_dp_init(dev, PCH_DP_D);
7199
103a196f 7200 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 7201 bool found = false;
7d57382e 7202
725e30ad 7203 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 7204 DRM_DEBUG_KMS("probing SDVOB\n");
725e30ad 7205 found = intel_sdvo_init(dev, SDVOB);
b01f2c3a
JB		 7206 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7207 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 7208 intel_hdmi_init(dev, SDVOB);
b01f2c3a 7209 }
27185ae1 7210
b01f2c3a
JB		 7211 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7212 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 7213 intel_dp_init(dev, DP_B);
b01f2c3a 7214 }
725e30ad 7215 }
13520b05
KH		 7216
7217 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 7218
b01f2c3a
JB		 7219 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7220 DRM_DEBUG_KMS("probing SDVOC\n");
725e30ad 7221 found = intel_sdvo_init(dev, SDVOC);
b01f2c3a 7222 }
27185ae1
ML		 7223
7224 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7225
b01f2c3a
JB		 7226 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7227 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 7228 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 7229 }
7230 if (SUPPORTS_INTEGRATED_DP(dev)) {
7231 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 7232 intel_dp_init(dev, DP_C);
b01f2c3a 7233 }
725e30ad 7234 }
27185ae1 7235
b01f2c3a
JB		 7236 if (SUPPORTS_INTEGRATED_DP(dev) &&
7237 (I915_READ(DP_D) & DP_DETECTED)) {
7238 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 7239 intel_dp_init(dev, DP_D);
b01f2c3a 7240 }
bad720ff 7241 } else if (IS_GEN2(dev))
79e53945
JB		 7242 intel_dvo_init(dev);
7243
103a196f 7244 if (SUPPORTS_TV(dev))
79e53945
JB		 7245 intel_tv_init(dev);
7246
4ef69c7a
CW		 7247 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7248 encoder->base.possible_crtcs = encoder->crtc_mask;
7249 encoder->base.possible_clones =
7250 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 7251 }
47356eb6 7252
2c7111db
CW		 7253 /* disable all the possible outputs/crtcs before entering KMS mode */
7254 drm_helper_disable_unused_functions(dev);
79e53945
JB		 7255}
7256
7257static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7258{
7259 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 7260
7261 drm_framebuffer_cleanup(fb);
05394f39 7262 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 7263
7264 kfree(intel_fb);
7265}
7266
7267static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 7268 struct drm_file *file,
79e53945
JB		 7269 unsigned int *handle)
7270{
7271 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 7272 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 7273
05394f39 7274 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 7275}
7276
7277static const struct drm_framebuffer_funcs intel_fb_funcs = {
7278 .destroy = intel_user_framebuffer_destroy,
7279 .create_handle = intel_user_framebuffer_create_handle,
7280};
7281
38651674
DA		 7282int intel_framebuffer_init(struct drm_device *dev,
7283 struct intel_framebuffer *intel_fb,
7284 struct drm_mode_fb_cmd *mode_cmd,
05394f39 7285 struct drm_i915_gem_object *obj)
79e53945 7286{
79e53945
JB		 7287 int ret;
7288
05394f39 7289 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 7290 return -EINVAL;
7291
7292 if (mode_cmd->pitch & 63)
7293 return -EINVAL;
7294
7295 switch (mode_cmd->bpp) {
7296 case 8:
7297 case 16:
b5626747
JB		 7298 /* Only pre-ILK can handle 5:5:5 */
7299 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7300 return -EINVAL;
7301 break;
7302
57cd6508
CW		 7303 case 24:
7304 case 32:
7305 break;
7306 default:
7307 return -EINVAL;
7308 }
7309
79e53945
JB		 7310 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7311 if (ret) {
7312 DRM_ERROR("framebuffer init failed %d\n", ret);
7313 return ret;
7314 }
7315
7316 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 7317 intel_fb->obj = obj;
79e53945
JB		 7318 return 0;
7319}
7320
79e53945
JB		 7321static struct drm_framebuffer *
7322intel_user_framebuffer_create(struct drm_device *dev,
7323 struct drm_file *filp,
7324 struct drm_mode_fb_cmd *mode_cmd)
7325{
05394f39 7326 struct drm_i915_gem_object *obj;
79e53945 7327
05394f39 7328 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
c8725226 7329 if (&obj->base == NULL)
cce13ff7 7330 return ERR_PTR(-ENOENT);
79e53945 7331
d2dff872 7332 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 7333}
7334
79e53945 7335static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 7336 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 7337 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 7338};
7339
05394f39 7340static struct drm_i915_gem_object *
aa40d6bb 7341intel_alloc_context_page(struct drm_device *dev)
9ea8d059 7342{
05394f39 7343 struct drm_i915_gem_object *ctx;
9ea8d059
CW		 7344 int ret;
7345
2c34b850
BW		 7346 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7347
aa40d6bb
ZN		 7348 ctx = i915_gem_alloc_object(dev, 4096);
7349 if (!ctx) {
9ea8d059
CW		 7350 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7351 return NULL;
7352 }
7353
75e9e915 7354 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW		 7355 if (ret) {
7356 DRM_ERROR("failed to pin power context: %d\n", ret);
7357 goto err_unref;
7358 }
7359
aa40d6bb 7360 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW		 7361 if (ret) {
7362 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7363 goto err_unpin;
7364 }
9ea8d059 7365
aa40d6bb 7366 return ctx;
9ea8d059
CW		 7367
7368err_unpin:
aa40d6bb 7369 i915_gem_object_unpin(ctx);
9ea8d059 7370err_unref:
05394f39 7371 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW		 7372 mutex_unlock(&dev->struct_mutex);
7373 return NULL;
7374}
7375
7648fa99
JB		 7376bool ironlake_set_drps(struct drm_device *dev, u8 val)
7377{
7378 struct drm_i915_private *dev_priv = dev->dev_private;
7379 u16 rgvswctl;
7380
7381 rgvswctl = I915_READ16(MEMSWCTL);
7382 if (rgvswctl & MEMCTL_CMD_STS) {
7383 DRM_DEBUG("gpu busy, RCS change rejected\n");
7384 return false; /* still busy with another command */
7385 }
7386
7387 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7388 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7389 I915_WRITE16(MEMSWCTL, rgvswctl);
7390 POSTING_READ16(MEMSWCTL);
7391
7392 rgvswctl |= MEMCTL_CMD_STS;
7393 I915_WRITE16(MEMSWCTL, rgvswctl);
7394
7395 return true;
7396}
7397
f97108d1
JB		 7398void ironlake_enable_drps(struct drm_device *dev)
7399{
7400 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7401 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 7402 u8 fmax, fmin, fstart, vstart;
f97108d1 7403
ea056c14
JB		 7404 /* Enable temp reporting */
7405 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7406 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7407
f97108d1
JB		 7408 /* 100ms RC evaluation intervals */
7409 I915_WRITE(RCUPEI, 100000);
7410 I915_WRITE(RCDNEI, 100000);
7411
7412 /* Set max/min thresholds to 90ms and 80ms respectively */
7413 I915_WRITE(RCBMAXAVG, 90000);
7414 I915_WRITE(RCBMINAVG, 80000);
7415
7416 I915_WRITE(MEMIHYST, 1);
7417
7418 /* Set up min, max, and cur for interrupt handling */
7419 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7420 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7421 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7422 MEMMODE_FSTART_SHIFT;
7648fa99 7423
f97108d1
JB		 7424 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7425 PXVFREQ_PX_SHIFT;
7426
80dbf4b7 7427 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB		 7428 dev_priv->fstart = fstart;
7429
80dbf4b7 7430 dev_priv->max_delay = fstart;
f97108d1
JB		 7431 dev_priv->min_delay = fmin;
7432 dev_priv->cur_delay = fstart;
7433
80dbf4b7
JB		 7434 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7435 fmax, fmin, fstart);
7648fa99 7436
f97108d1
JB		 7437 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7438
7439 /*
7440 * Interrupts will be enabled in ironlake_irq_postinstall
7441 */
7442
7443 I915_WRITE(VIDSTART, vstart);
7444 POSTING_READ(VIDSTART);
7445
7446 rgvmodectl |= MEMMODE_SWMODE_EN;
7447 I915_WRITE(MEMMODECTL, rgvmodectl);
7448
481b6af3 7449 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 7450 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB		 7451 msleep(1);
7452
7648fa99 7453 ironlake_set_drps(dev, fstart);
f97108d1 7454
7648fa99
JB		 7455 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7456 I915_READ(0x112e0);
7457 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7458 dev_priv->last_count2 = I915_READ(0x112f4);
7459 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB		 7460}
7461
7462void ironlake_disable_drps(struct drm_device *dev)
7463{
7464 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7465 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB		 7466
7467 /* Ack interrupts, disable EFC interrupt */
7468 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7469 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7470 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7471 I915_WRITE(DEIIR, DE_PCU_EVENT);
7472 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7473
7474 /* Go back to the starting frequency */
7648fa99 7475 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB		 7476 msleep(1);
7477 rgvswctl |= MEMCTL_CMD_STS;
7478 I915_WRITE(MEMSWCTL, rgvswctl);
7479 msleep(1);
7480
7481}
7482
3b8d8d91
JB		 7483void gen6_set_rps(struct drm_device *dev, u8 val)
7484{
7485 struct drm_i915_private *dev_priv = dev->dev_private;
7486 u32 swreq;
7487
7488 swreq = (val & 0x3ff) << 25;
7489 I915_WRITE(GEN6_RPNSWREQ, swreq);
7490}
7491
7492void gen6_disable_rps(struct drm_device *dev)
7493{
7494 struct drm_i915_private *dev_priv = dev->dev_private;
7495
7496 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7497 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7498 I915_WRITE(GEN6_PMIER, 0);
4912d041
BW		 7499
7500 spin_lock_irq(&dev_priv->rps_lock);
7501 dev_priv->pm_iir = 0;
7502 spin_unlock_irq(&dev_priv->rps_lock);
7503
3b8d8d91
JB		 7504 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7505}
7506
7648fa99
JB		 7507static unsigned long intel_pxfreq(u32 vidfreq)
7508{
7509 unsigned long freq;
7510 int div = (vidfreq & 0x3f0000) >> 16;
7511 int post = (vidfreq & 0x3000) >> 12;
7512 int pre = (vidfreq & 0x7);
7513
7514 if (!pre)
7515 return 0;
7516
7517 freq = ((div * 133333) / ((1<<post) * pre));
7518
7519 return freq;
7520}
7521
7522void intel_init_emon(struct drm_device *dev)
7523{
7524 struct drm_i915_private *dev_priv = dev->dev_private;
7525 u32 lcfuse;
7526 u8 pxw[16];
7527 int i;
7528
7529 /* Disable to program */
7530 I915_WRITE(ECR, 0);
7531 POSTING_READ(ECR);
7532
7533 /* Program energy weights for various events */
7534 I915_WRITE(SDEW, 0x15040d00);
7535 I915_WRITE(CSIEW0, 0x007f0000);
7536 I915_WRITE(CSIEW1, 0x1e220004);
7537 I915_WRITE(CSIEW2, 0x04000004);
7538
7539 for (i = 0; i < 5; i++)
7540 I915_WRITE(PEW + (i * 4), 0);
7541 for (i = 0; i < 3; i++)
7542 I915_WRITE(DEW + (i * 4), 0);
7543
7544 /* Program P-state weights to account for frequency power adjustment */
7545 for (i = 0; i < 16; i++) {
7546 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7547 unsigned long freq = intel_pxfreq(pxvidfreq);
7548 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7549 PXVFREQ_PX_SHIFT;
7550 unsigned long val;
7551
7552 val = vid * vid;
7553 val *= (freq / 1000);
7554 val *= 255;
7555 val /= (127*127*900);
7556 if (val > 0xff)
7557 DRM_ERROR("bad pxval: %ld\n", val);
7558 pxw[i] = val;
7559 }
7560 /* Render standby states get 0 weight */
7561 pxw[14] = 0;
7562 pxw[15] = 0;
7563
7564 for (i = 0; i < 4; i++) {
7565 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7566 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7567 I915_WRITE(PXW + (i * 4), val);
7568 }
7569
7570 /* Adjust magic regs to magic values (more experimental results) */
7571 I915_WRITE(OGW0, 0);
7572 I915_WRITE(OGW1, 0);
7573 I915_WRITE(EG0, 0x00007f00);
7574 I915_WRITE(EG1, 0x0000000e);
7575 I915_WRITE(EG2, 0x000e0000);
7576 I915_WRITE(EG3, 0x68000300);
7577 I915_WRITE(EG4, 0x42000000);
7578 I915_WRITE(EG5, 0x00140031);
7579 I915_WRITE(EG6, 0);
7580 I915_WRITE(EG7, 0);
7581
7582 for (i = 0; i < 8; i++)
7583 I915_WRITE(PXWL + (i * 4), 0);
7584
7585 /* Enable PMON + select events */
7586 I915_WRITE(ECR, 0x80000019);
7587
7588 lcfuse = I915_READ(LCFUSE02);
7589
7590 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7591}
7592
3b8d8d91 7593void gen6_enable_rps(struct drm_i915_private *dev_priv)
8fd26859 7594{
a6044e23
JB		 7595 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7596 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7df8721b 7597 u32 pcu_mbox, rc6_mask = 0;
a6044e23 7598 int cur_freq, min_freq, max_freq;
8fd26859
CW		 7599 int i;
7600
7601 /* Here begins a magic sequence of register writes to enable
7602 * auto-downclocking.
7603 *
7604 * Perhaps there might be some value in exposing these to
7605 * userspace...
7606 */
7607 I915_WRITE(GEN6_RC_STATE, 0);
d1ebd816 7608 mutex_lock(&dev_priv->dev->struct_mutex);
fcca7926 7609 gen6_gt_force_wake_get(dev_priv);
8fd26859 7610
3b8d8d91 7611 /* disable the counters and set deterministic thresholds */
8fd26859
CW		 7612 I915_WRITE(GEN6_RC_CONTROL, 0);
7613
7614 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7615 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7616 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7617 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7618 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7619
7620 for (i = 0; i < I915_NUM_RINGS; i++)
7621 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7622
7623 I915_WRITE(GEN6_RC_SLEEP, 0);
7624 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7625 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7626 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7627 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7628
7df8721b
JB		 7629 if (i915_enable_rc6)
7630 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7631 GEN6_RC_CTL_RC6_ENABLE;
7632
8fd26859 7633 I915_WRITE(GEN6_RC_CONTROL,
7df8721b 7634 rc6_mask |
9c3d2f7f 7635 GEN6_RC_CTL_EI_MODE(1) |
8fd26859
CW		 7636 GEN6_RC_CTL_HW_ENABLE);
7637
3b8d8d91 7638 I915_WRITE(GEN6_RPNSWREQ,
8fd26859
CW		 7639 GEN6_FREQUENCY(10) |
7640 GEN6_OFFSET(0) |
7641 GEN6_AGGRESSIVE_TURBO);
7642 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7643 GEN6_FREQUENCY(12));
7644
7645 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7646 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7647 18 << 24 |
7648 6 << 16);
ccab5c82
JB		 7649 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7650 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8fd26859 7651 I915_WRITE(GEN6_RP_UP_EI, 100000);
ccab5c82 7652 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8fd26859
CW		 7653 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7654 I915_WRITE(GEN6_RP_CONTROL,
7655 GEN6_RP_MEDIA_TURBO |
7656 GEN6_RP_USE_NORMAL_FREQ |
7657 GEN6_RP_MEDIA_IS_GFX |
7658 GEN6_RP_ENABLE |
ccab5c82
JB		 7659 GEN6_RP_UP_BUSY_AVG |
7660 GEN6_RP_DOWN_IDLE_CONT);
8fd26859
CW		 7661
7662 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7663 500))
7664 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7665
7666 I915_WRITE(GEN6_PCODE_DATA, 0);
7667 I915_WRITE(GEN6_PCODE_MAILBOX,
7668 GEN6_PCODE_READY |
7669 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7670 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7671 500))
7672 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7673
a6044e23
JB		 7674 min_freq = (rp_state_cap & 0xff0000) >> 16;
7675 max_freq = rp_state_cap & 0xff;
7676 cur_freq = (gt_perf_status & 0xff00) >> 8;
7677
7678 /* Check for overclock support */
7679 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7680 500))
7681 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7682 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7683 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7684 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7685 500))
7686 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7687 if (pcu_mbox & (1<<31)) { /* OC supported */
7688 max_freq = pcu_mbox & 0xff;
e281fcaa 7689 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
a6044e23
JB		 7690 }
7691
7692 /* In units of 100MHz */
7693 dev_priv->max_delay = max_freq;
7694 dev_priv->min_delay = min_freq;
7695 dev_priv->cur_delay = cur_freq;
7696
8fd26859
CW		 7697 /* requires MSI enabled */
7698 I915_WRITE(GEN6_PMIER,
7699 GEN6_PM_MBOX_EVENT |
7700 GEN6_PM_THERMAL_EVENT |
7701 GEN6_PM_RP_DOWN_TIMEOUT |
7702 GEN6_PM_RP_UP_THRESHOLD |
7703 GEN6_PM_RP_DOWN_THRESHOLD |
7704 GEN6_PM_RP_UP_EI_EXPIRED |
7705 GEN6_PM_RP_DOWN_EI_EXPIRED);
4912d041
BW		 7706 spin_lock_irq(&dev_priv->rps_lock);
7707 WARN_ON(dev_priv->pm_iir != 0);
3b8d8d91 7708 I915_WRITE(GEN6_PMIMR, 0);
4912d041 7709 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91
JB		 7710 /* enable all PM interrupts */
7711 I915_WRITE(GEN6_PMINTRMSK, 0);
8fd26859 7712
fcca7926 7713 gen6_gt_force_wake_put(dev_priv);
d1ebd816 7714 mutex_unlock(&dev_priv->dev->struct_mutex);
8fd26859
CW		 7715}
7716
23b2f8bb
JB		 7717void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7718{
7719 int min_freq = 15;
7720 int gpu_freq, ia_freq, max_ia_freq;
7721 int scaling_factor = 180;
7722
7723 max_ia_freq = cpufreq_quick_get_max(0);
7724 /*
7725 * Default to measured freq if none found, PCU will ensure we don't go
7726 * over
7727 */
7728 if (!max_ia_freq)
7729 max_ia_freq = tsc_khz;
7730
7731 /* Convert from kHz to MHz */
7732 max_ia_freq /= 1000;
7733
7734 mutex_lock(&dev_priv->dev->struct_mutex);
7735
7736 /*
7737 * For each potential GPU frequency, load a ring frequency we'd like
7738 * to use for memory access. We do this by specifying the IA frequency
7739 * the PCU should use as a reference to determine the ring frequency.
7740 */
7741 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
7742 gpu_freq--) {
7743 int diff = dev_priv->max_delay - gpu_freq;
7744
7745 /*
7746 * For GPU frequencies less than 750MHz, just use the lowest
7747 * ring freq.
7748 */
7749 if (gpu_freq < min_freq)
7750 ia_freq = 800;
7751 else
7752 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
7753 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
7754
7755 I915_WRITE(GEN6_PCODE_DATA,
7756 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
7757 gpu_freq);
7758 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
7759 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7760 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
7761 GEN6_PCODE_READY) == 0, 10)) {
7762 DRM_ERROR("pcode write of freq table timed out\n");
7763 continue;
7764 }
7765 }
7766
7767 mutex_unlock(&dev_priv->dev->struct_mutex);
7768}
7769
6067aaea
JB		 7770static void ironlake_init_clock_gating(struct drm_device *dev)
7771{
7772 struct drm_i915_private *dev_priv = dev->dev_private;
7773 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7774
7775 /* Required for FBC */
7776 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7777 DPFCRUNIT_CLOCK_GATE_DISABLE |
7778 DPFDUNIT_CLOCK_GATE_DISABLE;
7779 /* Required for CxSR */
7780 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7781
7782 I915_WRITE(PCH_3DCGDIS0,
7783 MARIUNIT_CLOCK_GATE_DISABLE |
7784 SVSMUNIT_CLOCK_GATE_DISABLE);
7785 I915_WRITE(PCH_3DCGDIS1,
7786 VFMUNIT_CLOCK_GATE_DISABLE);
7787
7788 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7789
6067aaea
JB		 7790 /*
7791 * According to the spec the following bits should be set in
7792 * order to enable memory self-refresh
7793 * The bit 22/21 of 0x42004
7794 * The bit 5 of 0x42020
7795 * The bit 15 of 0x45000
7796 */
7797 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7798 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7799 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7800 I915_WRITE(ILK_DSPCLK_GATE,
7801 (I915_READ(ILK_DSPCLK_GATE) |
7802 ILK_DPARB_CLK_GATE));
7803 I915_WRITE(DISP_ARB_CTL,
7804 (I915_READ(DISP_ARB_CTL) |
7805 DISP_FBC_WM_DIS));
7806 I915_WRITE(WM3_LP_ILK, 0);
7807 I915_WRITE(WM2_LP_ILK, 0);
7808 I915_WRITE(WM1_LP_ILK, 0);
7809
7810 /*
7811 * Based on the document from hardware guys the following bits
7812 * should be set unconditionally in order to enable FBC.
7813 * The bit 22 of 0x42000
7814 * The bit 22 of 0x42004
7815 * The bit 7,8,9 of 0x42020.
7816 */
7817 if (IS_IRONLAKE_M(dev)) {
7818 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7819 I915_READ(ILK_DISPLAY_CHICKEN1) |
7820 ILK_FBCQ_DIS);
7821 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7822 I915_READ(ILK_DISPLAY_CHICKEN2) |
7823 ILK_DPARB_GATE);
7824 I915_WRITE(ILK_DSPCLK_GATE,
7825 I915_READ(ILK_DSPCLK_GATE) |
7826 ILK_DPFC_DIS1 |
7827 ILK_DPFC_DIS2 |
7828 ILK_CLK_FBC);
7829 }
7830
7831 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7832 I915_READ(ILK_DISPLAY_CHICKEN2) |
7833 ILK_ELPIN_409_SELECT);
7834 I915_WRITE(_3D_CHICKEN2,
7835 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7836 _3D_CHICKEN2_WM_READ_PIPELINED);
8fd26859
CW		 7837}
7838
6067aaea 7839static void gen6_init_clock_gating(struct drm_device *dev)
652c393a
JB		 7840{
7841 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 7842 int pipe;
6067aaea
JB		 7843 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7844
7845 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
652c393a 7846
6067aaea
JB		 7847 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7848 I915_READ(ILK_DISPLAY_CHICKEN2) |
7849 ILK_ELPIN_409_SELECT);
8956c8bb 7850
6067aaea
JB		 7851 I915_WRITE(WM3_LP_ILK, 0);
7852 I915_WRITE(WM2_LP_ILK, 0);
7853 I915_WRITE(WM1_LP_ILK, 0);
652c393a
JB		 7854
7855 /*
6067aaea
JB		 7856 * According to the spec the following bits should be
7857 * set in order to enable memory self-refresh and fbc:
7858 * The bit21 and bit22 of 0x42000
7859 * The bit21 and bit22 of 0x42004
7860 * The bit5 and bit7 of 0x42020
7861 * The bit14 of 0x70180
7862 * The bit14 of 0x71180
652c393a 7863 */
6067aaea
JB		 7864 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7865 I915_READ(ILK_DISPLAY_CHICKEN1) |
7866 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7867 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7868 I915_READ(ILK_DISPLAY_CHICKEN2) |
7869 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7870 I915_WRITE(ILK_DSPCLK_GATE,
7871 I915_READ(ILK_DSPCLK_GATE) |
7872 ILK_DPARB_CLK_GATE |
7873 ILK_DPFD_CLK_GATE);
8956c8bb 7874
d74362c9 7875 for_each_pipe(pipe) {
6067aaea
JB		 7876 I915_WRITE(DSPCNTR(pipe),
7877 I915_READ(DSPCNTR(pipe)) |
7878 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 7879 intel_flush_display_plane(dev_priv, pipe);
7880 }
6067aaea 7881}
8956c8bb 7882
28963a3e
JB		 7883static void ivybridge_init_clock_gating(struct drm_device *dev)
7884{
7885 struct drm_i915_private *dev_priv = dev->dev_private;
7886 int pipe;
7887 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7f8a8569 7888
28963a3e 7889 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
382b0936 7890
28963a3e
JB		 7891 I915_WRITE(WM3_LP_ILK, 0);
7892 I915_WRITE(WM2_LP_ILK, 0);
7893 I915_WRITE(WM1_LP_ILK, 0);
de6e2eaf 7894
28963a3e 7895 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
67e92af0 7896
d74362c9 7897 for_each_pipe(pipe) {
28963a3e
JB		 7898 I915_WRITE(DSPCNTR(pipe),
7899 I915_READ(DSPCNTR(pipe)) |
7900 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 7901 intel_flush_display_plane(dev_priv, pipe);
7902 }
28963a3e
JB		 7903}
7904
6067aaea
JB		 7905static void g4x_init_clock_gating(struct drm_device *dev)
7906{
7907 struct drm_i915_private *dev_priv = dev->dev_private;
7908 uint32_t dspclk_gate;
8fd26859 7909
6067aaea
JB		 7910 I915_WRITE(RENCLK_GATE_D1, 0);
7911 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7912 GS_UNIT_CLOCK_GATE_DISABLE |
7913 CL_UNIT_CLOCK_GATE_DISABLE);
7914 I915_WRITE(RAMCLK_GATE_D, 0);
7915 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7916 OVRUNIT_CLOCK_GATE_DISABLE |
7917 OVCUNIT_CLOCK_GATE_DISABLE;
7918 if (IS_GM45(dev))
7919 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7920 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7921}
1398261a 7922
6067aaea
JB		 7923static void crestline_init_clock_gating(struct drm_device *dev)
7924{
7925 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7926
6067aaea
JB		 7927 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7928 I915_WRITE(RENCLK_GATE_D2, 0);
7929 I915_WRITE(DSPCLK_GATE_D, 0);
7930 I915_WRITE(RAMCLK_GATE_D, 0);
7931 I915_WRITE16(DEUC, 0);
7932}
652c393a 7933
6067aaea
JB		 7934static void broadwater_init_clock_gating(struct drm_device *dev)
7935{
7936 struct drm_i915_private *dev_priv = dev->dev_private;
7937
7938 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7939 I965_RCC_CLOCK_GATE_DISABLE |
7940 I965_RCPB_CLOCK_GATE_DISABLE |
7941 I965_ISC_CLOCK_GATE_DISABLE |
7942 I965_FBC_CLOCK_GATE_DISABLE);
7943 I915_WRITE(RENCLK_GATE_D2, 0);
7944}
7945
7946static void gen3_init_clock_gating(struct drm_device *dev)
7947{
7948 struct drm_i915_private *dev_priv = dev->dev_private;
7949 u32 dstate = I915_READ(D_STATE);
7950
7951 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7952 DSTATE_DOT_CLOCK_GATING;
7953 I915_WRITE(D_STATE, dstate);
7954}
7955
7956static void i85x_init_clock_gating(struct drm_device *dev)
7957{
7958 struct drm_i915_private *dev_priv = dev->dev_private;
7959
7960 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7961}
7962
7963static void i830_init_clock_gating(struct drm_device *dev)
7964{
7965 struct drm_i915_private *dev_priv = dev->dev_private;
7966
7967 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
652c393a
JB		 7968}
7969
645c62a5
JB		 7970static void ibx_init_clock_gating(struct drm_device *dev)
7971{
7972 struct drm_i915_private *dev_priv = dev->dev_private;
7973
7974 /*
7975 * On Ibex Peak and Cougar Point, we need to disable clock
7976 * gating for the panel power sequencer or it will fail to
7977 * start up when no ports are active.
7978 */
7979 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7980}
7981
7982static void cpt_init_clock_gating(struct drm_device *dev)
7983{
7984 struct drm_i915_private *dev_priv = dev->dev_private;
3bcf603f 7985 int pipe;
645c62a5
JB		 7986
7987 /*
7988 * On Ibex Peak and Cougar Point, we need to disable clock
7989 * gating for the panel power sequencer or it will fail to
7990 * start up when no ports are active.
7991 */
7992 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7993 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7994 DPLS_EDP_PPS_FIX_DIS);
3bcf603f
JB		 7995 /* Without this, mode sets may fail silently on FDI */
7996 for_each_pipe(pipe)
7997 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
652c393a
JB		 7998}
7999
ac668088 8000static void ironlake_teardown_rc6(struct drm_device *dev)
0cdab21f
CW		 8001{
8002 struct drm_i915_private *dev_priv = dev->dev_private;
8003
8004 if (dev_priv->renderctx) {
ac668088
CW		 8005 i915_gem_object_unpin(dev_priv->renderctx);
8006 drm_gem_object_unreference(&dev_priv->renderctx->base);
0cdab21f
CW		 8007 dev_priv->renderctx = NULL;
8008 }
8009
8010 if (dev_priv->pwrctx) {
ac668088
CW		 8011 i915_gem_object_unpin(dev_priv->pwrctx);
8012 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8013 dev_priv->pwrctx = NULL;
8014 }
8015}
8016
8017static void ironlake_disable_rc6(struct drm_device *dev)
8018{
8019 struct drm_i915_private *dev_priv = dev->dev_private;
8020
8021 if (I915_READ(PWRCTXA)) {
8022 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8023 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8024 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8025 50);
0cdab21f
CW		 8026
8027 I915_WRITE(PWRCTXA, 0);
8028 POSTING_READ(PWRCTXA);
8029
ac668088
CW		 8030 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8031 POSTING_READ(RSTDBYCTL);
0cdab21f 8032 }
ac668088 8033
99507307 8034 ironlake_teardown_rc6(dev);
0cdab21f
CW		 8035}
8036
ac668088 8037static int ironlake_setup_rc6(struct drm_device *dev)
d5bb081b
JB		 8038{
8039 struct drm_i915_private *dev_priv = dev->dev_private;
8040
ac668088
CW		 8041 if (dev_priv->renderctx == NULL)
8042 dev_priv->renderctx = intel_alloc_context_page(dev);
8043 if (!dev_priv->renderctx)
8044 return -ENOMEM;
8045
8046 if (dev_priv->pwrctx == NULL)
8047 dev_priv->pwrctx = intel_alloc_context_page(dev);
8048 if (!dev_priv->pwrctx) {
8049 ironlake_teardown_rc6(dev);
8050 return -ENOMEM;
8051 }
8052
8053 return 0;
d5bb081b
JB		 8054}
8055
8056void ironlake_enable_rc6(struct drm_device *dev)
8057{
8058 struct drm_i915_private *dev_priv = dev->dev_private;
8059 int ret;
8060
ac668088
CW		 8061 /* rc6 disabled by default due to repeated reports of hanging during
8062 * boot and resume.
8063 */
8064 if (!i915_enable_rc6)
8065 return;
8066
2c34b850 8067 mutex_lock(&dev->struct_mutex);
ac668088 8068 ret = ironlake_setup_rc6(dev);
2c34b850
BW		 8069 if (ret) {
8070 mutex_unlock(&dev->struct_mutex);
ac668088 8071 return;
2c34b850 8072 }
ac668088 8073
d5bb081b
JB		 8074 /*
8075 * GPU can automatically power down the render unit if given a page
8076 * to save state.
8077 */
8078 ret = BEGIN_LP_RING(6);
8079 if (ret) {
ac668088 8080 ironlake_teardown_rc6(dev);
2c34b850 8081 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8082 return;
8083 }
ac668088 8084
d5bb081b
JB		 8085 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8086 OUT_RING(MI_SET_CONTEXT);
8087 OUT_RING(dev_priv->renderctx->gtt_offset |
8088 MI_MM_SPACE_GTT |
8089 MI_SAVE_EXT_STATE_EN |
8090 MI_RESTORE_EXT_STATE_EN |
8091 MI_RESTORE_INHIBIT);
8092 OUT_RING(MI_SUSPEND_FLUSH);
8093 OUT_RING(MI_NOOP);
8094 OUT_RING(MI_FLUSH);
8095 ADVANCE_LP_RING();
8096
4a246cfc
BW		 8097 /*
8098 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8099 * does an implicit flush, combined with MI_FLUSH above, it should be
8100 * safe to assume that renderctx is valid
8101 */
8102 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8103 if (ret) {
8104 DRM_ERROR("failed to enable ironlake power power savings\n");
8105 ironlake_teardown_rc6(dev);
8106 mutex_unlock(&dev->struct_mutex);
8107 return;
8108 }
8109
d5bb081b
JB		 8110 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8111 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2c34b850 8112 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8113}
8114
645c62a5
JB		 8115void intel_init_clock_gating(struct drm_device *dev)
8116{
8117 struct drm_i915_private *dev_priv = dev->dev_private;
8118
8119 dev_priv->display.init_clock_gating(dev);
8120
8121 if (dev_priv->display.init_pch_clock_gating)
8122 dev_priv->display.init_pch_clock_gating(dev);
8123}
ac668088 8124
e70236a8
JB		 8125/* Set up chip specific display functions */
8126static void intel_init_display(struct drm_device *dev)
8127{
8128 struct drm_i915_private *dev_priv = dev->dev_private;
8129
8130 /* We always want a DPMS function */
f564048e 8131 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 8132 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 8133 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
17638cd6 8134 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8135 } else {
e70236a8 8136 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 8137 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
17638cd6 8138 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8139 }
e70236a8 8140
ee5382ae 8141 if (I915_HAS_FBC(dev)) {
9c04f015 8142 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 8143 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8144 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8145 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8146 } else if (IS_GM45(dev)) {
74dff282
JB		 8147 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8148 dev_priv->display.enable_fbc = g4x_enable_fbc;
8149 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 8150 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 8151 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8152 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8153 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8154 }
74dff282 8155 /* 855GM needs testing */
e70236a8
JB		 8156 }
8157
8158 /* Returns the core display clock speed */
f2b115e6 8159 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
e70236a8
JB		 8160 dev_priv->display.get_display_clock_speed =
8161 i945_get_display_clock_speed;
8162 else if (IS_I915G(dev))
8163 dev_priv->display.get_display_clock_speed =
8164 i915_get_display_clock_speed;
f2b115e6 8165 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8166 dev_priv->display.get_display_clock_speed =
8167 i9xx_misc_get_display_clock_speed;
8168 else if (IS_I915GM(dev))
8169 dev_priv->display.get_display_clock_speed =
8170 i915gm_get_display_clock_speed;
8171 else if (IS_I865G(dev))
8172 dev_priv->display.get_display_clock_speed =
8173 i865_get_display_clock_speed;
f0f8a9ce 8174 else if (IS_I85X(dev))
e70236a8
JB		 8175 dev_priv->display.get_display_clock_speed =
8176 i855_get_display_clock_speed;
8177 else /* 852, 830 */
8178 dev_priv->display.get_display_clock_speed =
8179 i830_get_display_clock_speed;
8180
8181 /* For FIFO watermark updates */
7f8a8569 8182 if (HAS_PCH_SPLIT(dev)) {
645c62a5
JB		 8183 if (HAS_PCH_IBX(dev))
8184 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8185 else if (HAS_PCH_CPT(dev))
8186 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8187
f00a3ddf 8188 if (IS_GEN5(dev)) {
7f8a8569
ZW		 8189 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8190 dev_priv->display.update_wm = ironlake_update_wm;
8191 else {
8192 DRM_DEBUG_KMS("Failed to get proper latency. "
8193 "Disable CxSR\n");
8194 dev_priv->display.update_wm = NULL;
1398261a 8195 }
674cf967 8196 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6067aaea 8197 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
1398261a
YL		 8198 } else if (IS_GEN6(dev)) {
8199 if (SNB_READ_WM0_LATENCY()) {
8200 dev_priv->display.update_wm = sandybridge_update_wm;
8201 } else {
8202 DRM_DEBUG_KMS("Failed to read display plane latency. "
8203 "Disable CxSR\n");
8204 dev_priv->display.update_wm = NULL;
7f8a8569 8205 }
674cf967 8206 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6067aaea 8207 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
357555c0
JB		 8208 } else if (IS_IVYBRIDGE(dev)) {
8209 /* FIXME: detect B0+ stepping and use auto training */
8210 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
fe100d4d
JB		 8211 if (SNB_READ_WM0_LATENCY()) {
8212 dev_priv->display.update_wm = sandybridge_update_wm;
8213 } else {
8214 DRM_DEBUG_KMS("Failed to read display plane latency. "
8215 "Disable CxSR\n");
8216 dev_priv->display.update_wm = NULL;
8217 }
28963a3e 8218 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6067aaea 8219
7f8a8569
ZW		 8220 } else
8221 dev_priv->display.update_wm = NULL;
8222 } else if (IS_PINEVIEW(dev)) {
d4294342 8223 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 8224 dev_priv->is_ddr3,
d4294342
ZY		 8225 dev_priv->fsb_freq,
8226 dev_priv->mem_freq)) {
8227 DRM_INFO("failed to find known CxSR latency "
95534263 8228 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 8229 "disabling CxSR\n",
95534263 8230 (dev_priv->is_ddr3 == 1) ? "3": "2",
d4294342
ZY		 8231 dev_priv->fsb_freq, dev_priv->mem_freq);
8232 /* Disable CxSR and never update its watermark again */
8233 pineview_disable_cxsr(dev);
8234 dev_priv->display.update_wm = NULL;
8235 } else
8236 dev_priv->display.update_wm = pineview_update_wm;
95e0ee92 8237 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6067aaea 8238 } else if (IS_G4X(dev)) {
e70236a8 8239 dev_priv->display.update_wm = g4x_update_wm;
6067aaea
JB		 8240 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8241 } else if (IS_GEN4(dev)) {
e70236a8 8242 dev_priv->display.update_wm = i965_update_wm;
6067aaea
JB		 8243 if (IS_CRESTLINE(dev))
8244 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8245 else if (IS_BROADWATER(dev))
8246 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8247 } else if (IS_GEN3(dev)) {
e70236a8
JB		 8248 dev_priv->display.update_wm = i9xx_update_wm;
8249 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6067aaea
JB		 8250 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8251 } else if (IS_I865G(dev)) {
8252 dev_priv->display.update_wm = i830_update_wm;
8253 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8254 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8f4695ed
AJ		 8255 } else if (IS_I85X(dev)) {
8256 dev_priv->display.update_wm = i9xx_update_wm;
8257 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6067aaea 8258 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
e70236a8 8259 } else {
8f4695ed 8260 dev_priv->display.update_wm = i830_update_wm;
6067aaea 8261 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8f4695ed 8262 if (IS_845G(dev))
e70236a8
JB		 8263 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8264 else
8265 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8 8266 }
8c9f3aaf
JB		 8267
8268 /* Default just returns -ENODEV to indicate unsupported */
8269 dev_priv->display.queue_flip = intel_default_queue_flip;
8270
8271 switch (INTEL_INFO(dev)->gen) {
8272 case 2:
8273 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8274 break;
8275
8276 case 3:
8277 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8278 break;
8279
8280 case 4:
8281 case 5:
8282 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8283 break;
8284
8285 case 6:
8286 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8287 break;
7c9017e5
JB		 8288 case 7:
8289 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8290 break;
8c9f3aaf 8291 }
e70236a8
JB		 8292}
8293
b690e96c
JB		 8294/*
8295 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8296 * resume, or other times. This quirk makes sure that's the case for
8297 * affected systems.
8298 */
8299static void quirk_pipea_force (struct drm_device *dev)
8300{
8301 struct drm_i915_private *dev_priv = dev->dev_private;
8302
8303 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8304 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8305}
8306
435793df
KP		 8307/*
8308 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8309 */
8310static void quirk_ssc_force_disable(struct drm_device *dev)
8311{
8312 struct drm_i915_private *dev_priv = dev->dev_private;
8313 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8314}
8315
b690e96c
JB		 8316struct intel_quirk {
8317 int device;
8318 int subsystem_vendor;
8319 int subsystem_device;
8320 void (*hook)(struct drm_device *dev);
8321};
8322
8323struct intel_quirk intel_quirks[] = {
8324 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8325 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8326 /* HP Mini needs pipe A force quirk (LP: #322104) */
8327 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
8328
8329 /* Thinkpad R31 needs pipe A force quirk */
8330 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8331 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8332 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8333
8334 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8335 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
8336 /* ThinkPad X40 needs pipe A force quirk */
8337
8338 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8339 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8340
8341 /* 855 & before need to leave pipe A & dpll A up */
8342 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8343 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8344
8345 /* Lenovo U160 cannot use SSC on LVDS */
8346 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8347
8348 /* Sony Vaio Y cannot use SSC on LVDS */
8349 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
b690e96c
JB		 8350};
8351
8352static void intel_init_quirks(struct drm_device *dev)
8353{
8354 struct pci_dev *d = dev->pdev;
8355 int i;
8356
8357 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8358 struct intel_quirk *q = &intel_quirks[i];
8359
8360 if (d->device == q->device &&
8361 (d->subsystem_vendor == q->subsystem_vendor ||
8362 q->subsystem_vendor == PCI_ANY_ID) &&
8363 (d->subsystem_device == q->subsystem_device ||
8364 q->subsystem_device == PCI_ANY_ID))
8365 q->hook(dev);
8366 }
8367}
8368
9cce37f4
JB		 8369/* Disable the VGA plane that we never use */
8370static void i915_disable_vga(struct drm_device *dev)
8371{
8372 struct drm_i915_private *dev_priv = dev->dev_private;
8373 u8 sr1;
8374 u32 vga_reg;
8375
8376 if (HAS_PCH_SPLIT(dev))
8377 vga_reg = CPU_VGACNTRL;
8378 else
8379 vga_reg = VGACNTRL;
8380
8381 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8382 outb(1, VGA_SR_INDEX);
8383 sr1 = inb(VGA_SR_DATA);
8384 outb(sr1 | 1<<5, VGA_SR_DATA);
8385 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8386 udelay(300);
8387
8388 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8389 POSTING_READ(vga_reg);
8390}
8391
79e53945
JB		 8392void intel_modeset_init(struct drm_device *dev)
8393{
652c393a 8394 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 8395 int i;
8396
8397 drm_mode_config_init(dev);
8398
8399 dev->mode_config.min_width = 0;
8400 dev->mode_config.min_height = 0;
8401
8402 dev->mode_config.funcs = (void *)&intel_mode_funcs;
8403
b690e96c
JB		 8404 intel_init_quirks(dev);
8405
e70236a8
JB		 8406 intel_init_display(dev);
8407
a6c45cf0
CW		 8408 if (IS_GEN2(dev)) {
8409 dev->mode_config.max_width = 2048;
8410 dev->mode_config.max_height = 2048;
8411 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8412 dev->mode_config.max_width = 4096;
8413 dev->mode_config.max_height = 4096;
79e53945 8414 } else {
a6c45cf0
CW		 8415 dev->mode_config.max_width = 8192;
8416 dev->mode_config.max_height = 8192;
79e53945 8417 }
35c3047a 8418 dev->mode_config.fb_base = dev->agp->base;
79e53945 8419
28c97730 8420 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8421 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8422
a3524f1b 8423 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945
JB		 8424 intel_crtc_init(dev, i);
8425 }
8426
9cce37f4
JB		 8427 /* Just disable it once at startup */
8428 i915_disable_vga(dev);
79e53945 8429 intel_setup_outputs(dev);
652c393a 8430
645c62a5 8431 intel_init_clock_gating(dev);
9cce37f4 8432
7648fa99 8433 if (IS_IRONLAKE_M(dev)) {
f97108d1 8434 ironlake_enable_drps(dev);
7648fa99
JB		 8435 intel_init_emon(dev);
8436 }
f97108d1 8437
1c70c0ce 8438 if (IS_GEN6(dev) || IS_GEN7(dev)) {
3b8d8d91 8439 gen6_enable_rps(dev_priv);
23b2f8bb
JB		 8440 gen6_update_ring_freq(dev_priv);
8441 }
3b8d8d91 8442
652c393a
JB		 8443 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8444 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8445 (unsigned long)dev);
2c7111db
CW		 8446}
8447
8448void intel_modeset_gem_init(struct drm_device *dev)
8449{
8450 if (IS_IRONLAKE_M(dev))
8451 ironlake_enable_rc6(dev);
02e792fb
DV		 8452
8453 intel_setup_overlay(dev);
79e53945
JB		 8454}
8455
8456void intel_modeset_cleanup(struct drm_device *dev)
8457{
652c393a
JB		 8458 struct drm_i915_private *dev_priv = dev->dev_private;
8459 struct drm_crtc *crtc;
8460 struct intel_crtc *intel_crtc;
8461
f87ea761 8462 drm_kms_helper_poll_fini(dev);
652c393a
JB		 8463 mutex_lock(&dev->struct_mutex);
8464
723bfd70
JB		 8465 intel_unregister_dsm_handler();
8466
8467
652c393a
JB		 8468 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8469 /* Skip inactive CRTCs */
8470 if (!crtc->fb)
8471 continue;
8472
8473 intel_crtc = to_intel_crtc(crtc);
3dec0095 8474 intel_increase_pllclock(crtc);
652c393a
JB		 8475 }
8476
973d04f9 8477 intel_disable_fbc(dev);
e70236a8 8478
f97108d1
JB		 8479 if (IS_IRONLAKE_M(dev))
8480 ironlake_disable_drps(dev);
1c70c0ce 8481 if (IS_GEN6(dev) || IS_GEN7(dev))
3b8d8d91 8482 gen6_disable_rps(dev);
f97108d1 8483
d5bb081b
JB		 8484 if (IS_IRONLAKE_M(dev))
8485 ironlake_disable_rc6(dev);
0cdab21f 8486
69341a5e
KH		 8487 mutex_unlock(&dev->struct_mutex);
8488
6c0d9350
DV		 8489 /* Disable the irq before mode object teardown, for the irq might
8490 * enqueue unpin/hotplug work. */
8491 drm_irq_uninstall(dev);
8492 cancel_work_sync(&dev_priv->hotplug_work);
8493
1630fe75
CW		 8494 /* flush any delayed tasks or pending work */
8495 flush_scheduled_work();
8496
3dec0095
DV		 8497 /* Shut off idle work before the crtcs get freed. */
8498 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8499 intel_crtc = to_intel_crtc(crtc);
8500 del_timer_sync(&intel_crtc->idle_timer);
8501 }
8502 del_timer_sync(&dev_priv->idle_timer);
8503 cancel_work_sync(&dev_priv->idle_work);
8504
79e53945
JB		 8505 drm_mode_config_cleanup(dev);
8506}
8507
f1c79df3
ZW		 8508/*
8509 * Return which encoder is currently attached for connector.
8510 */
df0e9248 8511struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 8512{
df0e9248
CW		 8513 return &intel_attached_encoder(connector)->base;
8514}
f1c79df3 8515
df0e9248
CW		 8516void intel_connector_attach_encoder(struct intel_connector *connector,
8517 struct intel_encoder *encoder)
8518{
8519 connector->encoder = encoder;
8520 drm_mode_connector_attach_encoder(&connector->base,
8521 &encoder->base);
79e53945 8522}
28d52043
DA		 8523
8524/*
8525 * set vga decode state - true == enable VGA decode
8526 */
8527int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8528{
8529 struct drm_i915_private *dev_priv = dev->dev_private;
8530 u16 gmch_ctrl;
8531
8532 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8533 if (state)
8534 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8535 else
8536 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8537 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8538 return 0;
8539}
c4a1d9e4
CW		 8540
8541#ifdef CONFIG_DEBUG_FS
8542#include <linux/seq_file.h>
8543
8544struct intel_display_error_state {
8545 struct intel_cursor_error_state {
8546 u32 control;
8547 u32 position;
8548 u32 base;
8549 u32 size;
8550 } cursor[2];
8551
8552 struct intel_pipe_error_state {
8553 u32 conf;
8554 u32 source;
8555
8556 u32 htotal;
8557 u32 hblank;
8558 u32 hsync;
8559 u32 vtotal;
8560 u32 vblank;
8561 u32 vsync;
8562 } pipe[2];
8563
8564 struct intel_plane_error_state {
8565 u32 control;
8566 u32 stride;
8567 u32 size;
8568 u32 pos;
8569 u32 addr;
8570 u32 surface;
8571 u32 tile_offset;
8572 } plane[2];
8573};
8574
8575struct intel_display_error_state *
8576intel_display_capture_error_state(struct drm_device *dev)
8577{
8578 drm_i915_private_t *dev_priv = dev->dev_private;
8579 struct intel_display_error_state *error;
8580 int i;
8581
8582 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8583 if (error == NULL)
8584 return NULL;
8585
8586 for (i = 0; i < 2; i++) {
8587 error->cursor[i].control = I915_READ(CURCNTR(i));
8588 error->cursor[i].position = I915_READ(CURPOS(i));
8589 error->cursor[i].base = I915_READ(CURBASE(i));
8590
8591 error->plane[i].control = I915_READ(DSPCNTR(i));
8592 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8593 error->plane[i].size = I915_READ(DSPSIZE(i));
8594 error->plane[i].pos= I915_READ(DSPPOS(i));
8595 error->plane[i].addr = I915_READ(DSPADDR(i));
8596 if (INTEL_INFO(dev)->gen >= 4) {
8597 error->plane[i].surface = I915_READ(DSPSURF(i));
8598 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8599 }
8600
8601 error->pipe[i].conf = I915_READ(PIPECONF(i));
8602 error->pipe[i].source = I915_READ(PIPESRC(i));
8603 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8604 error->pipe[i].hblank = I915_READ(HBLANK(i));
8605 error->pipe[i].hsync = I915_READ(HSYNC(i));
8606 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8607 error->pipe[i].vblank = I915_READ(VBLANK(i));
8608 error->pipe[i].vsync = I915_READ(VSYNC(i));
8609 }
8610
8611 return error;
8612}
8613
8614void
8615intel_display_print_error_state(struct seq_file *m,
8616 struct drm_device *dev,
8617 struct intel_display_error_state *error)
8618{
8619 int i;
8620
8621 for (i = 0; i < 2; i++) {
8622 seq_printf(m, "Pipe [%d]:\n", i);
8623 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8624 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8625 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8626 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8627 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8628 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8629 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8630 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8631
8632 seq_printf(m, "Plane [%d]:\n", i);
8633 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8634 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8635 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8636 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8637 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8638 if (INTEL_INFO(dev)->gen >= 4) {
8639 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8640 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8641 }
8642
8643 seq_printf(m, "Cursor [%d]:\n", i);
8644 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8645 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8646 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8647 }
8648}
8649#endif
Linux kernel - Deliverables
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