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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
23b2f8bb | 27 | #include <linux/cpufreq.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
79e53945 JB |
35 | #include "drmP.h" |
36 | #include "intel_drv.h" | |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
e5510fac | 39 | #include "i915_trace.h" |
ab2c0672 | 40 | #include "drm_dp_helper.h" |
79e53945 JB |
41 | |
42 | #include "drm_crtc_helper.h" | |
43 | ||
32f9d658 ZW |
44 | #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
45 | ||
0206e353 | 46 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
7662c8bd | 47 | static void intel_update_watermarks(struct drm_device *dev); |
3dec0095 | 48 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 49 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 JB |
50 | |
51 | typedef struct { | |
0206e353 AJ |
52 | /* given values */ |
53 | int n; | |
54 | int m1, m2; | |
55 | int p1, p2; | |
56 | /* derived values */ | |
57 | int dot; | |
58 | int vco; | |
59 | int m; | |
60 | int p; | |
79e53945 JB |
61 | } intel_clock_t; |
62 | ||
63 | typedef struct { | |
0206e353 | 64 | int min, max; |
79e53945 JB |
65 | } intel_range_t; |
66 | ||
67 | typedef struct { | |
0206e353 AJ |
68 | int dot_limit; |
69 | int p2_slow, p2_fast; | |
79e53945 JB |
70 | } intel_p2_t; |
71 | ||
72 | #define INTEL_P2_NUM 2 | |
d4906093 ML |
73 | typedef struct intel_limit intel_limit_t; |
74 | struct intel_limit { | |
0206e353 AJ |
75 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
76 | intel_p2_t p2; | |
77 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, | |
78 | int, int, intel_clock_t *); | |
d4906093 | 79 | }; |
79e53945 | 80 | |
2377b741 JB |
81 | /* FDI */ |
82 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ | |
83 | ||
d4906093 ML |
84 | static bool |
85 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
86 | int target, int refclk, intel_clock_t *best_clock); | |
87 | static bool | |
88 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
89 | int target, int refclk, intel_clock_t *best_clock); | |
79e53945 | 90 | |
a4fc5ed6 KP |
91 | static bool |
92 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, | |
93 | int target, int refclk, intel_clock_t *best_clock); | |
5eb08b69 | 94 | static bool |
f2b115e6 AJ |
95 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
96 | int target, int refclk, intel_clock_t *best_clock); | |
a4fc5ed6 | 97 | |
021357ac CW |
98 | static inline u32 /* units of 100MHz */ |
99 | intel_fdi_link_freq(struct drm_device *dev) | |
100 | { | |
8b99e68c CW |
101 | if (IS_GEN5(dev)) { |
102 | struct drm_i915_private *dev_priv = dev->dev_private; | |
103 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
104 | } else | |
105 | return 27; | |
021357ac CW |
106 | } |
107 | ||
e4b36699 | 108 | static const intel_limit_t intel_limits_i8xx_dvo = { |
0206e353 AJ |
109 | .dot = { .min = 25000, .max = 350000 }, |
110 | .vco = { .min = 930000, .max = 1400000 }, | |
111 | .n = { .min = 3, .max = 16 }, | |
112 | .m = { .min = 96, .max = 140 }, | |
113 | .m1 = { .min = 18, .max = 26 }, | |
114 | .m2 = { .min = 6, .max = 16 }, | |
115 | .p = { .min = 4, .max = 128 }, | |
116 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
117 | .p2 = { .dot_limit = 165000, |
118 | .p2_slow = 4, .p2_fast = 2 }, | |
d4906093 | 119 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
120 | }; |
121 | ||
122 | static const intel_limit_t intel_limits_i8xx_lvds = { | |
0206e353 AJ |
123 | .dot = { .min = 25000, .max = 350000 }, |
124 | .vco = { .min = 930000, .max = 1400000 }, | |
125 | .n = { .min = 3, .max = 16 }, | |
126 | .m = { .min = 96, .max = 140 }, | |
127 | .m1 = { .min = 18, .max = 26 }, | |
128 | .m2 = { .min = 6, .max = 16 }, | |
129 | .p = { .min = 4, .max = 128 }, | |
130 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
131 | .p2 = { .dot_limit = 165000, |
132 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 133 | .find_pll = intel_find_best_PLL, |
e4b36699 | 134 | }; |
273e27ca | 135 | |
e4b36699 | 136 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
137 | .dot = { .min = 20000, .max = 400000 }, |
138 | .vco = { .min = 1400000, .max = 2800000 }, | |
139 | .n = { .min = 1, .max = 6 }, | |
140 | .m = { .min = 70, .max = 120 }, | |
141 | .m1 = { .min = 10, .max = 22 }, | |
142 | .m2 = { .min = 5, .max = 9 }, | |
143 | .p = { .min = 5, .max = 80 }, | |
144 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
145 | .p2 = { .dot_limit = 200000, |
146 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 147 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
148 | }; |
149 | ||
150 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
151 | .dot = { .min = 20000, .max = 400000 }, |
152 | .vco = { .min = 1400000, .max = 2800000 }, | |
153 | .n = { .min = 1, .max = 6 }, | |
154 | .m = { .min = 70, .max = 120 }, | |
155 | .m1 = { .min = 10, .max = 22 }, | |
156 | .m2 = { .min = 5, .max = 9 }, | |
157 | .p = { .min = 7, .max = 98 }, | |
158 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
159 | .p2 = { .dot_limit = 112000, |
160 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 161 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
162 | }; |
163 | ||
273e27ca | 164 | |
e4b36699 | 165 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
166 | .dot = { .min = 25000, .max = 270000 }, |
167 | .vco = { .min = 1750000, .max = 3500000}, | |
168 | .n = { .min = 1, .max = 4 }, | |
169 | .m = { .min = 104, .max = 138 }, | |
170 | .m1 = { .min = 17, .max = 23 }, | |
171 | .m2 = { .min = 5, .max = 11 }, | |
172 | .p = { .min = 10, .max = 30 }, | |
173 | .p1 = { .min = 1, .max = 3}, | |
174 | .p2 = { .dot_limit = 270000, | |
175 | .p2_slow = 10, | |
176 | .p2_fast = 10 | |
044c7c41 | 177 | }, |
d4906093 | 178 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
179 | }; |
180 | ||
181 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
182 | .dot = { .min = 22000, .max = 400000 }, |
183 | .vco = { .min = 1750000, .max = 3500000}, | |
184 | .n = { .min = 1, .max = 4 }, | |
185 | .m = { .min = 104, .max = 138 }, | |
186 | .m1 = { .min = 16, .max = 23 }, | |
187 | .m2 = { .min = 5, .max = 11 }, | |
188 | .p = { .min = 5, .max = 80 }, | |
189 | .p1 = { .min = 1, .max = 8}, | |
190 | .p2 = { .dot_limit = 165000, | |
191 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 192 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
193 | }; |
194 | ||
195 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
196 | .dot = { .min = 20000, .max = 115000 }, |
197 | .vco = { .min = 1750000, .max = 3500000 }, | |
198 | .n = { .min = 1, .max = 3 }, | |
199 | .m = { .min = 104, .max = 138 }, | |
200 | .m1 = { .min = 17, .max = 23 }, | |
201 | .m2 = { .min = 5, .max = 11 }, | |
202 | .p = { .min = 28, .max = 112 }, | |
203 | .p1 = { .min = 2, .max = 8 }, | |
204 | .p2 = { .dot_limit = 0, | |
205 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 206 | }, |
d4906093 | 207 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
208 | }; |
209 | ||
210 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
211 | .dot = { .min = 80000, .max = 224000 }, |
212 | .vco = { .min = 1750000, .max = 3500000 }, | |
213 | .n = { .min = 1, .max = 3 }, | |
214 | .m = { .min = 104, .max = 138 }, | |
215 | .m1 = { .min = 17, .max = 23 }, | |
216 | .m2 = { .min = 5, .max = 11 }, | |
217 | .p = { .min = 14, .max = 42 }, | |
218 | .p1 = { .min = 2, .max = 6 }, | |
219 | .p2 = { .dot_limit = 0, | |
220 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 221 | }, |
d4906093 | 222 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
223 | }; |
224 | ||
225 | static const intel_limit_t intel_limits_g4x_display_port = { | |
0206e353 AJ |
226 | .dot = { .min = 161670, .max = 227000 }, |
227 | .vco = { .min = 1750000, .max = 3500000}, | |
228 | .n = { .min = 1, .max = 2 }, | |
229 | .m = { .min = 97, .max = 108 }, | |
230 | .m1 = { .min = 0x10, .max = 0x12 }, | |
231 | .m2 = { .min = 0x05, .max = 0x06 }, | |
232 | .p = { .min = 10, .max = 20 }, | |
233 | .p1 = { .min = 1, .max = 2}, | |
234 | .p2 = { .dot_limit = 0, | |
273e27ca | 235 | .p2_slow = 10, .p2_fast = 10 }, |
0206e353 | 236 | .find_pll = intel_find_pll_g4x_dp, |
e4b36699 KP |
237 | }; |
238 | ||
f2b115e6 | 239 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
240 | .dot = { .min = 20000, .max = 400000}, |
241 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 242 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
243 | .n = { .min = 3, .max = 6 }, |
244 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 245 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
246 | .m1 = { .min = 0, .max = 0 }, |
247 | .m2 = { .min = 0, .max = 254 }, | |
248 | .p = { .min = 5, .max = 80 }, | |
249 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
250 | .p2 = { .dot_limit = 200000, |
251 | .p2_slow = 10, .p2_fast = 5 }, | |
6115707b | 252 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
253 | }; |
254 | ||
f2b115e6 | 255 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
256 | .dot = { .min = 20000, .max = 400000 }, |
257 | .vco = { .min = 1700000, .max = 3500000 }, | |
258 | .n = { .min = 3, .max = 6 }, | |
259 | .m = { .min = 2, .max = 256 }, | |
260 | .m1 = { .min = 0, .max = 0 }, | |
261 | .m2 = { .min = 0, .max = 254 }, | |
262 | .p = { .min = 7, .max = 112 }, | |
263 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
264 | .p2 = { .dot_limit = 112000, |
265 | .p2_slow = 14, .p2_fast = 14 }, | |
6115707b | 266 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
267 | }; |
268 | ||
273e27ca EA |
269 | /* Ironlake / Sandybridge |
270 | * | |
271 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
272 | * the range value for them is (actual_value - 2). | |
273 | */ | |
b91ad0ec | 274 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
275 | .dot = { .min = 25000, .max = 350000 }, |
276 | .vco = { .min = 1760000, .max = 3510000 }, | |
277 | .n = { .min = 1, .max = 5 }, | |
278 | .m = { .min = 79, .max = 127 }, | |
279 | .m1 = { .min = 12, .max = 22 }, | |
280 | .m2 = { .min = 5, .max = 9 }, | |
281 | .p = { .min = 5, .max = 80 }, | |
282 | .p1 = { .min = 1, .max = 8 }, | |
283 | .p2 = { .dot_limit = 225000, | |
284 | .p2_slow = 10, .p2_fast = 5 }, | |
4547668a | 285 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
286 | }; |
287 | ||
b91ad0ec | 288 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
289 | .dot = { .min = 25000, .max = 350000 }, |
290 | .vco = { .min = 1760000, .max = 3510000 }, | |
291 | .n = { .min = 1, .max = 3 }, | |
292 | .m = { .min = 79, .max = 118 }, | |
293 | .m1 = { .min = 12, .max = 22 }, | |
294 | .m2 = { .min = 5, .max = 9 }, | |
295 | .p = { .min = 28, .max = 112 }, | |
296 | .p1 = { .min = 2, .max = 8 }, | |
297 | .p2 = { .dot_limit = 225000, | |
298 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
299 | .find_pll = intel_g4x_find_best_PLL, |
300 | }; | |
301 | ||
302 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
303 | .dot = { .min = 25000, .max = 350000 }, |
304 | .vco = { .min = 1760000, .max = 3510000 }, | |
305 | .n = { .min = 1, .max = 3 }, | |
306 | .m = { .min = 79, .max = 127 }, | |
307 | .m1 = { .min = 12, .max = 22 }, | |
308 | .m2 = { .min = 5, .max = 9 }, | |
309 | .p = { .min = 14, .max = 56 }, | |
310 | .p1 = { .min = 2, .max = 8 }, | |
311 | .p2 = { .dot_limit = 225000, | |
312 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
313 | .find_pll = intel_g4x_find_best_PLL, |
314 | }; | |
315 | ||
273e27ca | 316 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 317 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
318 | .dot = { .min = 25000, .max = 350000 }, |
319 | .vco = { .min = 1760000, .max = 3510000 }, | |
320 | .n = { .min = 1, .max = 2 }, | |
321 | .m = { .min = 79, .max = 126 }, | |
322 | .m1 = { .min = 12, .max = 22 }, | |
323 | .m2 = { .min = 5, .max = 9 }, | |
324 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 325 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
326 | .p2 = { .dot_limit = 225000, |
327 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
328 | .find_pll = intel_g4x_find_best_PLL, |
329 | }; | |
330 | ||
331 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
332 | .dot = { .min = 25000, .max = 350000 }, |
333 | .vco = { .min = 1760000, .max = 3510000 }, | |
334 | .n = { .min = 1, .max = 3 }, | |
335 | .m = { .min = 79, .max = 126 }, | |
336 | .m1 = { .min = 12, .max = 22 }, | |
337 | .m2 = { .min = 5, .max = 9 }, | |
338 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 339 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
340 | .p2 = { .dot_limit = 225000, |
341 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
342 | .find_pll = intel_g4x_find_best_PLL, |
343 | }; | |
344 | ||
345 | static const intel_limit_t intel_limits_ironlake_display_port = { | |
0206e353 AJ |
346 | .dot = { .min = 25000, .max = 350000 }, |
347 | .vco = { .min = 1760000, .max = 3510000}, | |
348 | .n = { .min = 1, .max = 2 }, | |
349 | .m = { .min = 81, .max = 90 }, | |
350 | .m1 = { .min = 12, .max = 22 }, | |
351 | .m2 = { .min = 5, .max = 9 }, | |
352 | .p = { .min = 10, .max = 20 }, | |
353 | .p1 = { .min = 1, .max = 2}, | |
354 | .p2 = { .dot_limit = 0, | |
273e27ca | 355 | .p2_slow = 10, .p2_fast = 10 }, |
0206e353 | 356 | .find_pll = intel_find_pll_ironlake_dp, |
79e53945 JB |
357 | }; |
358 | ||
1b894b59 CW |
359 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
360 | int refclk) | |
2c07245f | 361 | { |
b91ad0ec ZW |
362 | struct drm_device *dev = crtc->dev; |
363 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2c07245f | 364 | const intel_limit_t *limit; |
b91ad0ec ZW |
365 | |
366 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
b91ad0ec ZW |
367 | if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == |
368 | LVDS_CLKB_POWER_UP) { | |
369 | /* LVDS dual channel */ | |
1b894b59 | 370 | if (refclk == 100000) |
b91ad0ec ZW |
371 | limit = &intel_limits_ironlake_dual_lvds_100m; |
372 | else | |
373 | limit = &intel_limits_ironlake_dual_lvds; | |
374 | } else { | |
1b894b59 | 375 | if (refclk == 100000) |
b91ad0ec ZW |
376 | limit = &intel_limits_ironlake_single_lvds_100m; |
377 | else | |
378 | limit = &intel_limits_ironlake_single_lvds; | |
379 | } | |
380 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || | |
4547668a ZY |
381 | HAS_eDP) |
382 | limit = &intel_limits_ironlake_display_port; | |
2c07245f | 383 | else |
b91ad0ec | 384 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
385 | |
386 | return limit; | |
387 | } | |
388 | ||
044c7c41 ML |
389 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
390 | { | |
391 | struct drm_device *dev = crtc->dev; | |
392 | struct drm_i915_private *dev_priv = dev->dev_private; | |
393 | const intel_limit_t *limit; | |
394 | ||
395 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
396 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
397 | LVDS_CLKB_POWER_UP) | |
398 | /* LVDS with dual channel */ | |
e4b36699 | 399 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 ML |
400 | else |
401 | /* LVDS with dual channel */ | |
e4b36699 | 402 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
403 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
404 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 405 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 406 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 407 | limit = &intel_limits_g4x_sdvo; |
0206e353 | 408 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
e4b36699 | 409 | limit = &intel_limits_g4x_display_port; |
044c7c41 | 410 | } else /* The option is for other outputs */ |
e4b36699 | 411 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
412 | |
413 | return limit; | |
414 | } | |
415 | ||
1b894b59 | 416 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
417 | { |
418 | struct drm_device *dev = crtc->dev; | |
419 | const intel_limit_t *limit; | |
420 | ||
bad720ff | 421 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 422 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 423 | else if (IS_G4X(dev)) { |
044c7c41 | 424 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 425 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 426 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 427 | limit = &intel_limits_pineview_lvds; |
2177832f | 428 | else |
f2b115e6 | 429 | limit = &intel_limits_pineview_sdvo; |
a6c45cf0 CW |
430 | } else if (!IS_GEN2(dev)) { |
431 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
432 | limit = &intel_limits_i9xx_lvds; | |
433 | else | |
434 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
435 | } else { |
436 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 437 | limit = &intel_limits_i8xx_lvds; |
79e53945 | 438 | else |
e4b36699 | 439 | limit = &intel_limits_i8xx_dvo; |
79e53945 JB |
440 | } |
441 | return limit; | |
442 | } | |
443 | ||
f2b115e6 AJ |
444 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
445 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 446 | { |
2177832f SL |
447 | clock->m = clock->m2 + 2; |
448 | clock->p = clock->p1 * clock->p2; | |
449 | clock->vco = refclk * clock->m / clock->n; | |
450 | clock->dot = clock->vco / clock->p; | |
451 | } | |
452 | ||
453 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) | |
454 | { | |
f2b115e6 AJ |
455 | if (IS_PINEVIEW(dev)) { |
456 | pineview_clock(refclk, clock); | |
2177832f SL |
457 | return; |
458 | } | |
79e53945 JB |
459 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
460 | clock->p = clock->p1 * clock->p2; | |
461 | clock->vco = refclk * clock->m / (clock->n + 2); | |
462 | clock->dot = clock->vco / clock->p; | |
463 | } | |
464 | ||
79e53945 JB |
465 | /** |
466 | * Returns whether any output on the specified pipe is of the specified type | |
467 | */ | |
4ef69c7a | 468 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
79e53945 | 469 | { |
4ef69c7a CW |
470 | struct drm_device *dev = crtc->dev; |
471 | struct drm_mode_config *mode_config = &dev->mode_config; | |
472 | struct intel_encoder *encoder; | |
473 | ||
474 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
475 | if (encoder->base.crtc == crtc && encoder->type == type) | |
476 | return true; | |
477 | ||
478 | return false; | |
79e53945 JB |
479 | } |
480 | ||
7c04d1d9 | 481 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
482 | /** |
483 | * Returns whether the given set of divisors are valid for a given refclk with | |
484 | * the given connectors. | |
485 | */ | |
486 | ||
1b894b59 CW |
487 | static bool intel_PLL_is_valid(struct drm_device *dev, |
488 | const intel_limit_t *limit, | |
489 | const intel_clock_t *clock) | |
79e53945 | 490 | { |
79e53945 | 491 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 492 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 493 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
0206e353 | 494 | INTELPllInvalid("p out of range\n"); |
79e53945 | 495 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 496 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 497 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 498 | INTELPllInvalid("m1 out of range\n"); |
f2b115e6 | 499 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
0206e353 | 500 | INTELPllInvalid("m1 <= m2\n"); |
79e53945 | 501 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
0206e353 | 502 | INTELPllInvalid("m out of range\n"); |
79e53945 | 503 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
0206e353 | 504 | INTELPllInvalid("n out of range\n"); |
79e53945 | 505 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 506 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
507 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
508 | * connector, etc., rather than just a single range. | |
509 | */ | |
510 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 511 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
512 | |
513 | return true; | |
514 | } | |
515 | ||
d4906093 ML |
516 | static bool |
517 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
518 | int target, int refclk, intel_clock_t *best_clock) | |
519 | ||
79e53945 JB |
520 | { |
521 | struct drm_device *dev = crtc->dev; | |
522 | struct drm_i915_private *dev_priv = dev->dev_private; | |
523 | intel_clock_t clock; | |
79e53945 JB |
524 | int err = target; |
525 | ||
bc5e5718 | 526 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
832cc28d | 527 | (I915_READ(LVDS)) != 0) { |
79e53945 JB |
528 | /* |
529 | * For LVDS, if the panel is on, just rely on its current | |
530 | * settings for dual-channel. We haven't figured out how to | |
531 | * reliably set up different single/dual channel state, if we | |
532 | * even can. | |
533 | */ | |
534 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
535 | LVDS_CLKB_POWER_UP) | |
536 | clock.p2 = limit->p2.p2_fast; | |
537 | else | |
538 | clock.p2 = limit->p2.p2_slow; | |
539 | } else { | |
540 | if (target < limit->p2.dot_limit) | |
541 | clock.p2 = limit->p2.p2_slow; | |
542 | else | |
543 | clock.p2 = limit->p2.p2_fast; | |
544 | } | |
545 | ||
0206e353 | 546 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 547 | |
42158660 ZY |
548 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
549 | clock.m1++) { | |
550 | for (clock.m2 = limit->m2.min; | |
551 | clock.m2 <= limit->m2.max; clock.m2++) { | |
f2b115e6 AJ |
552 | /* m1 is always 0 in Pineview */ |
553 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) | |
42158660 ZY |
554 | break; |
555 | for (clock.n = limit->n.min; | |
556 | clock.n <= limit->n.max; clock.n++) { | |
557 | for (clock.p1 = limit->p1.min; | |
558 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
559 | int this_err; |
560 | ||
2177832f | 561 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
562 | if (!intel_PLL_is_valid(dev, limit, |
563 | &clock)) | |
79e53945 JB |
564 | continue; |
565 | ||
566 | this_err = abs(clock.dot - target); | |
567 | if (this_err < err) { | |
568 | *best_clock = clock; | |
569 | err = this_err; | |
570 | } | |
571 | } | |
572 | } | |
573 | } | |
574 | } | |
575 | ||
576 | return (err != target); | |
577 | } | |
578 | ||
d4906093 ML |
579 | static bool |
580 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
581 | int target, int refclk, intel_clock_t *best_clock) | |
582 | { | |
583 | struct drm_device *dev = crtc->dev; | |
584 | struct drm_i915_private *dev_priv = dev->dev_private; | |
585 | intel_clock_t clock; | |
586 | int max_n; | |
587 | bool found; | |
6ba770dc AJ |
588 | /* approximately equals target * 0.00585 */ |
589 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
590 | found = false; |
591 | ||
592 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4547668a ZY |
593 | int lvds_reg; |
594 | ||
c619eed4 | 595 | if (HAS_PCH_SPLIT(dev)) |
4547668a ZY |
596 | lvds_reg = PCH_LVDS; |
597 | else | |
598 | lvds_reg = LVDS; | |
599 | if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) == | |
d4906093 ML |
600 | LVDS_CLKB_POWER_UP) |
601 | clock.p2 = limit->p2.p2_fast; | |
602 | else | |
603 | clock.p2 = limit->p2.p2_slow; | |
604 | } else { | |
605 | if (target < limit->p2.dot_limit) | |
606 | clock.p2 = limit->p2.p2_slow; | |
607 | else | |
608 | clock.p2 = limit->p2.p2_fast; | |
609 | } | |
610 | ||
611 | memset(best_clock, 0, sizeof(*best_clock)); | |
612 | max_n = limit->n.max; | |
f77f13e2 | 613 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 614 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 615 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
616 | for (clock.m1 = limit->m1.max; |
617 | clock.m1 >= limit->m1.min; clock.m1--) { | |
618 | for (clock.m2 = limit->m2.max; | |
619 | clock.m2 >= limit->m2.min; clock.m2--) { | |
620 | for (clock.p1 = limit->p1.max; | |
621 | clock.p1 >= limit->p1.min; clock.p1--) { | |
622 | int this_err; | |
623 | ||
2177832f | 624 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
625 | if (!intel_PLL_is_valid(dev, limit, |
626 | &clock)) | |
d4906093 | 627 | continue; |
1b894b59 CW |
628 | |
629 | this_err = abs(clock.dot - target); | |
d4906093 ML |
630 | if (this_err < err_most) { |
631 | *best_clock = clock; | |
632 | err_most = this_err; | |
633 | max_n = clock.n; | |
634 | found = true; | |
635 | } | |
636 | } | |
637 | } | |
638 | } | |
639 | } | |
2c07245f ZW |
640 | return found; |
641 | } | |
642 | ||
5eb08b69 | 643 | static bool |
f2b115e6 AJ |
644 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
645 | int target, int refclk, intel_clock_t *best_clock) | |
5eb08b69 ZW |
646 | { |
647 | struct drm_device *dev = crtc->dev; | |
648 | intel_clock_t clock; | |
4547668a | 649 | |
5eb08b69 ZW |
650 | if (target < 200000) { |
651 | clock.n = 1; | |
652 | clock.p1 = 2; | |
653 | clock.p2 = 10; | |
654 | clock.m1 = 12; | |
655 | clock.m2 = 9; | |
656 | } else { | |
657 | clock.n = 2; | |
658 | clock.p1 = 1; | |
659 | clock.p2 = 10; | |
660 | clock.m1 = 14; | |
661 | clock.m2 = 8; | |
662 | } | |
663 | intel_clock(dev, refclk, &clock); | |
664 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
665 | return true; | |
666 | } | |
667 | ||
a4fc5ed6 KP |
668 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
669 | static bool | |
670 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, | |
671 | int target, int refclk, intel_clock_t *best_clock) | |
672 | { | |
5eddb70b CW |
673 | intel_clock_t clock; |
674 | if (target < 200000) { | |
675 | clock.p1 = 2; | |
676 | clock.p2 = 10; | |
677 | clock.n = 2; | |
678 | clock.m1 = 23; | |
679 | clock.m2 = 8; | |
680 | } else { | |
681 | clock.p1 = 1; | |
682 | clock.p2 = 10; | |
683 | clock.n = 1; | |
684 | clock.m1 = 14; | |
685 | clock.m2 = 2; | |
686 | } | |
687 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); | |
688 | clock.p = (clock.p1 * clock.p2); | |
689 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; | |
690 | clock.vco = 0; | |
691 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
692 | return true; | |
a4fc5ed6 KP |
693 | } |
694 | ||
9d0498a2 JB |
695 | /** |
696 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
697 | * @dev: drm device | |
698 | * @pipe: pipe to wait for | |
699 | * | |
700 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
701 | * mode setting code. | |
702 | */ | |
703 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 704 | { |
9d0498a2 | 705 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 706 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 707 | |
300387c0 CW |
708 | /* Clear existing vblank status. Note this will clear any other |
709 | * sticky status fields as well. | |
710 | * | |
711 | * This races with i915_driver_irq_handler() with the result | |
712 | * that either function could miss a vblank event. Here it is not | |
713 | * fatal, as we will either wait upon the next vblank interrupt or | |
714 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
715 | * called during modeset at which time the GPU should be idle and | |
716 | * should *not* be performing page flips and thus not waiting on | |
717 | * vblanks... | |
718 | * Currently, the result of us stealing a vblank from the irq | |
719 | * handler is that a single frame will be skipped during swapbuffers. | |
720 | */ | |
721 | I915_WRITE(pipestat_reg, | |
722 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
723 | ||
9d0498a2 | 724 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
725 | if (wait_for(I915_READ(pipestat_reg) & |
726 | PIPE_VBLANK_INTERRUPT_STATUS, | |
727 | 50)) | |
9d0498a2 JB |
728 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
729 | } | |
730 | ||
ab7ad7f6 KP |
731 | /* |
732 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
733 | * @dev: drm device |
734 | * @pipe: pipe to wait for | |
735 | * | |
736 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
737 | * spinning on the vblank interrupt status bit, since we won't actually | |
738 | * see an interrupt when the pipe is disabled. | |
739 | * | |
ab7ad7f6 KP |
740 | * On Gen4 and above: |
741 | * wait for the pipe register state bit to turn off | |
742 | * | |
743 | * Otherwise: | |
744 | * wait for the display line value to settle (it usually | |
745 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 746 | * |
9d0498a2 | 747 | */ |
58e10eb9 | 748 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
749 | { |
750 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ab7ad7f6 KP |
751 | |
752 | if (INTEL_INFO(dev)->gen >= 4) { | |
58e10eb9 | 753 | int reg = PIPECONF(pipe); |
ab7ad7f6 KP |
754 | |
755 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
756 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
757 | 100)) | |
ab7ad7f6 KP |
758 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); |
759 | } else { | |
760 | u32 last_line; | |
58e10eb9 | 761 | int reg = PIPEDSL(pipe); |
ab7ad7f6 KP |
762 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
763 | ||
764 | /* Wait for the display line to settle */ | |
765 | do { | |
58e10eb9 | 766 | last_line = I915_READ(reg) & DSL_LINEMASK; |
ab7ad7f6 | 767 | mdelay(5); |
58e10eb9 | 768 | } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) && |
ab7ad7f6 KP |
769 | time_after(timeout, jiffies)); |
770 | if (time_after(jiffies, timeout)) | |
771 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); | |
772 | } | |
79e53945 JB |
773 | } |
774 | ||
b24e7179 JB |
775 | static const char *state_string(bool enabled) |
776 | { | |
777 | return enabled ? "on" : "off"; | |
778 | } | |
779 | ||
780 | /* Only for pre-ILK configs */ | |
781 | static void assert_pll(struct drm_i915_private *dev_priv, | |
782 | enum pipe pipe, bool state) | |
783 | { | |
784 | int reg; | |
785 | u32 val; | |
786 | bool cur_state; | |
787 | ||
788 | reg = DPLL(pipe); | |
789 | val = I915_READ(reg); | |
790 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
791 | WARN(cur_state != state, | |
792 | "PLL state assertion failure (expected %s, current %s)\n", | |
793 | state_string(state), state_string(cur_state)); | |
794 | } | |
795 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
796 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
797 | ||
040484af JB |
798 | /* For ILK+ */ |
799 | static void assert_pch_pll(struct drm_i915_private *dev_priv, | |
800 | enum pipe pipe, bool state) | |
801 | { | |
802 | int reg; | |
803 | u32 val; | |
804 | bool cur_state; | |
805 | ||
806 | reg = PCH_DPLL(pipe); | |
807 | val = I915_READ(reg); | |
808 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
809 | WARN(cur_state != state, | |
810 | "PCH PLL state assertion failure (expected %s, current %s)\n", | |
811 | state_string(state), state_string(cur_state)); | |
812 | } | |
813 | #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true) | |
814 | #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false) | |
815 | ||
816 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
817 | enum pipe pipe, bool state) | |
818 | { | |
819 | int reg; | |
820 | u32 val; | |
821 | bool cur_state; | |
822 | ||
823 | reg = FDI_TX_CTL(pipe); | |
824 | val = I915_READ(reg); | |
825 | cur_state = !!(val & FDI_TX_ENABLE); | |
826 | WARN(cur_state != state, | |
827 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
828 | state_string(state), state_string(cur_state)); | |
829 | } | |
830 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
831 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
832 | ||
833 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
834 | enum pipe pipe, bool state) | |
835 | { | |
836 | int reg; | |
837 | u32 val; | |
838 | bool cur_state; | |
839 | ||
840 | reg = FDI_RX_CTL(pipe); | |
841 | val = I915_READ(reg); | |
842 | cur_state = !!(val & FDI_RX_ENABLE); | |
843 | WARN(cur_state != state, | |
844 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
845 | state_string(state), state_string(cur_state)); | |
846 | } | |
847 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
848 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
849 | ||
850 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
851 | enum pipe pipe) | |
852 | { | |
853 | int reg; | |
854 | u32 val; | |
855 | ||
856 | /* ILK FDI PLL is always enabled */ | |
857 | if (dev_priv->info->gen == 5) | |
858 | return; | |
859 | ||
860 | reg = FDI_TX_CTL(pipe); | |
861 | val = I915_READ(reg); | |
862 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
863 | } | |
864 | ||
865 | static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv, | |
866 | enum pipe pipe) | |
867 | { | |
868 | int reg; | |
869 | u32 val; | |
870 | ||
871 | reg = FDI_RX_CTL(pipe); | |
872 | val = I915_READ(reg); | |
873 | WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n"); | |
874 | } | |
875 | ||
ea0760cf JB |
876 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
877 | enum pipe pipe) | |
878 | { | |
879 | int pp_reg, lvds_reg; | |
880 | u32 val; | |
881 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 882 | bool locked = true; |
ea0760cf JB |
883 | |
884 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
885 | pp_reg = PCH_PP_CONTROL; | |
886 | lvds_reg = PCH_LVDS; | |
887 | } else { | |
888 | pp_reg = PP_CONTROL; | |
889 | lvds_reg = LVDS; | |
890 | } | |
891 | ||
892 | val = I915_READ(pp_reg); | |
893 | if (!(val & PANEL_POWER_ON) || | |
894 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
895 | locked = false; | |
896 | ||
897 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
898 | panel_pipe = PIPE_B; | |
899 | ||
900 | WARN(panel_pipe == pipe && locked, | |
901 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 902 | pipe_name(pipe)); |
ea0760cf JB |
903 | } |
904 | ||
63d7bbe9 JB |
905 | static void assert_pipe(struct drm_i915_private *dev_priv, |
906 | enum pipe pipe, bool state) | |
b24e7179 JB |
907 | { |
908 | int reg; | |
909 | u32 val; | |
63d7bbe9 | 910 | bool cur_state; |
b24e7179 JB |
911 | |
912 | reg = PIPECONF(pipe); | |
913 | val = I915_READ(reg); | |
63d7bbe9 JB |
914 | cur_state = !!(val & PIPECONF_ENABLE); |
915 | WARN(cur_state != state, | |
916 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 917 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 | 918 | } |
63d7bbe9 JB |
919 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
920 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) | |
b24e7179 JB |
921 | |
922 | static void assert_plane_enabled(struct drm_i915_private *dev_priv, | |
923 | enum plane plane) | |
924 | { | |
925 | int reg; | |
926 | u32 val; | |
927 | ||
928 | reg = DSPCNTR(plane); | |
929 | val = I915_READ(reg); | |
930 | WARN(!(val & DISPLAY_PLANE_ENABLE), | |
931 | "plane %c assertion failure, should be active but is disabled\n", | |
9db4a9c7 | 932 | plane_name(plane)); |
b24e7179 JB |
933 | } |
934 | ||
935 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, | |
936 | enum pipe pipe) | |
937 | { | |
938 | int reg, i; | |
939 | u32 val; | |
940 | int cur_pipe; | |
941 | ||
19ec1358 JB |
942 | /* Planes are fixed to pipes on ILK+ */ |
943 | if (HAS_PCH_SPLIT(dev_priv->dev)) | |
944 | return; | |
945 | ||
b24e7179 JB |
946 | /* Need to check both planes against the pipe */ |
947 | for (i = 0; i < 2; i++) { | |
948 | reg = DSPCNTR(i); | |
949 | val = I915_READ(reg); | |
950 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
951 | DISPPLANE_SEL_PIPE_SHIFT; | |
952 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
953 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
954 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
955 | } |
956 | } | |
957 | ||
92f2584a JB |
958 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
959 | { | |
960 | u32 val; | |
961 | bool enabled; | |
962 | ||
963 | val = I915_READ(PCH_DREF_CONTROL); | |
964 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
965 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
966 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
967 | } | |
968 | ||
969 | static void assert_transcoder_disabled(struct drm_i915_private *dev_priv, | |
970 | enum pipe pipe) | |
971 | { | |
972 | int reg; | |
973 | u32 val; | |
974 | bool enabled; | |
975 | ||
976 | reg = TRANSCONF(pipe); | |
977 | val = I915_READ(reg); | |
978 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
979 | WARN(enabled, |
980 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
981 | pipe_name(pipe)); | |
92f2584a JB |
982 | } |
983 | ||
4e634389 KP |
984 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
985 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
986 | { |
987 | if ((val & DP_PORT_EN) == 0) | |
988 | return false; | |
989 | ||
990 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
991 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
992 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
993 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
994 | return false; | |
995 | } else { | |
996 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
997 | return false; | |
998 | } | |
999 | return true; | |
1000 | } | |
1001 | ||
1519b995 KP |
1002 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1003 | enum pipe pipe, u32 val) | |
1004 | { | |
1005 | if ((val & PORT_ENABLE) == 0) | |
1006 | return false; | |
1007 | ||
1008 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1009 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1010 | return false; | |
1011 | } else { | |
1012 | if ((val & TRANSCODER_MASK) != TRANSCODER(pipe)) | |
1013 | return false; | |
1014 | } | |
1015 | return true; | |
1016 | } | |
1017 | ||
1018 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1019 | enum pipe pipe, u32 val) | |
1020 | { | |
1021 | if ((val & LVDS_PORT_EN) == 0) | |
1022 | return false; | |
1023 | ||
1024 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1025 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1026 | return false; | |
1027 | } else { | |
1028 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1029 | return false; | |
1030 | } | |
1031 | return true; | |
1032 | } | |
1033 | ||
1034 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1035 | enum pipe pipe, u32 val) | |
1036 | { | |
1037 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1038 | return false; | |
1039 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1040 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1041 | return false; | |
1042 | } else { | |
1043 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1044 | return false; | |
1045 | } | |
1046 | return true; | |
1047 | } | |
1048 | ||
291906f1 | 1049 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1050 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1051 | { |
47a05eca | 1052 | u32 val = I915_READ(reg); |
4e634389 | 1053 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1054 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1055 | reg, pipe_name(pipe)); |
291906f1 JB |
1056 | } |
1057 | ||
1058 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1059 | enum pipe pipe, int reg) | |
1060 | { | |
47a05eca | 1061 | u32 val = I915_READ(reg); |
1519b995 | 1062 | WARN(hdmi_pipe_enabled(dev_priv, val, pipe), |
291906f1 | 1063 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1064 | reg, pipe_name(pipe)); |
291906f1 JB |
1065 | } |
1066 | ||
1067 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1068 | enum pipe pipe) | |
1069 | { | |
1070 | int reg; | |
1071 | u32 val; | |
291906f1 | 1072 | |
f0575e92 KP |
1073 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1074 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1075 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1076 | |
1077 | reg = PCH_ADPA; | |
1078 | val = I915_READ(reg); | |
1519b995 | 1079 | WARN(adpa_pipe_enabled(dev_priv, val, pipe), |
291906f1 | 1080 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1081 | pipe_name(pipe)); |
291906f1 JB |
1082 | |
1083 | reg = PCH_LVDS; | |
1084 | val = I915_READ(reg); | |
1519b995 | 1085 | WARN(lvds_pipe_enabled(dev_priv, val, pipe), |
291906f1 | 1086 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1087 | pipe_name(pipe)); |
291906f1 JB |
1088 | |
1089 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB); | |
1090 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC); | |
1091 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMID); | |
1092 | } | |
1093 | ||
63d7bbe9 JB |
1094 | /** |
1095 | * intel_enable_pll - enable a PLL | |
1096 | * @dev_priv: i915 private structure | |
1097 | * @pipe: pipe PLL to enable | |
1098 | * | |
1099 | * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to | |
1100 | * make sure the PLL reg is writable first though, since the panel write | |
1101 | * protect mechanism may be enabled. | |
1102 | * | |
1103 | * Note! This is for pre-ILK only. | |
1104 | */ | |
1105 | static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1106 | { | |
1107 | int reg; | |
1108 | u32 val; | |
1109 | ||
1110 | /* No really, not for ILK+ */ | |
1111 | BUG_ON(dev_priv->info->gen >= 5); | |
1112 | ||
1113 | /* PLL is protected by panel, make sure we can write it */ | |
1114 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
1115 | assert_panel_unlocked(dev_priv, pipe); | |
1116 | ||
1117 | reg = DPLL(pipe); | |
1118 | val = I915_READ(reg); | |
1119 | val |= DPLL_VCO_ENABLE; | |
1120 | ||
1121 | /* We do this three times for luck */ | |
1122 | I915_WRITE(reg, val); | |
1123 | POSTING_READ(reg); | |
1124 | udelay(150); /* wait for warmup */ | |
1125 | I915_WRITE(reg, val); | |
1126 | POSTING_READ(reg); | |
1127 | udelay(150); /* wait for warmup */ | |
1128 | I915_WRITE(reg, val); | |
1129 | POSTING_READ(reg); | |
1130 | udelay(150); /* wait for warmup */ | |
1131 | } | |
1132 | ||
1133 | /** | |
1134 | * intel_disable_pll - disable a PLL | |
1135 | * @dev_priv: i915 private structure | |
1136 | * @pipe: pipe PLL to disable | |
1137 | * | |
1138 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1139 | * | |
1140 | * Note! This is for pre-ILK only. | |
1141 | */ | |
1142 | static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1143 | { | |
1144 | int reg; | |
1145 | u32 val; | |
1146 | ||
1147 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1148 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1149 | return; | |
1150 | ||
1151 | /* Make sure the pipe isn't still relying on us */ | |
1152 | assert_pipe_disabled(dev_priv, pipe); | |
1153 | ||
1154 | reg = DPLL(pipe); | |
1155 | val = I915_READ(reg); | |
1156 | val &= ~DPLL_VCO_ENABLE; | |
1157 | I915_WRITE(reg, val); | |
1158 | POSTING_READ(reg); | |
1159 | } | |
1160 | ||
92f2584a JB |
1161 | /** |
1162 | * intel_enable_pch_pll - enable PCH PLL | |
1163 | * @dev_priv: i915 private structure | |
1164 | * @pipe: pipe PLL to enable | |
1165 | * | |
1166 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1167 | * drives the transcoder clock. | |
1168 | */ | |
1169 | static void intel_enable_pch_pll(struct drm_i915_private *dev_priv, | |
1170 | enum pipe pipe) | |
1171 | { | |
1172 | int reg; | |
1173 | u32 val; | |
1174 | ||
1175 | /* PCH only available on ILK+ */ | |
1176 | BUG_ON(dev_priv->info->gen < 5); | |
1177 | ||
1178 | /* PCH refclock must be enabled first */ | |
1179 | assert_pch_refclk_enabled(dev_priv); | |
1180 | ||
1181 | reg = PCH_DPLL(pipe); | |
1182 | val = I915_READ(reg); | |
1183 | val |= DPLL_VCO_ENABLE; | |
1184 | I915_WRITE(reg, val); | |
1185 | POSTING_READ(reg); | |
1186 | udelay(200); | |
1187 | } | |
1188 | ||
1189 | static void intel_disable_pch_pll(struct drm_i915_private *dev_priv, | |
1190 | enum pipe pipe) | |
1191 | { | |
1192 | int reg; | |
1193 | u32 val; | |
1194 | ||
1195 | /* PCH only available on ILK+ */ | |
1196 | BUG_ON(dev_priv->info->gen < 5); | |
1197 | ||
1198 | /* Make sure transcoder isn't still depending on us */ | |
1199 | assert_transcoder_disabled(dev_priv, pipe); | |
1200 | ||
1201 | reg = PCH_DPLL(pipe); | |
1202 | val = I915_READ(reg); | |
1203 | val &= ~DPLL_VCO_ENABLE; | |
1204 | I915_WRITE(reg, val); | |
1205 | POSTING_READ(reg); | |
1206 | udelay(200); | |
1207 | } | |
1208 | ||
040484af JB |
1209 | static void intel_enable_transcoder(struct drm_i915_private *dev_priv, |
1210 | enum pipe pipe) | |
1211 | { | |
1212 | int reg; | |
1213 | u32 val; | |
1214 | ||
1215 | /* PCH only available on ILK+ */ | |
1216 | BUG_ON(dev_priv->info->gen < 5); | |
1217 | ||
1218 | /* Make sure PCH DPLL is enabled */ | |
1219 | assert_pch_pll_enabled(dev_priv, pipe); | |
1220 | ||
1221 | /* FDI must be feeding us bits for PCH ports */ | |
1222 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1223 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1224 | ||
1225 | reg = TRANSCONF(pipe); | |
1226 | val = I915_READ(reg); | |
e9bcff5c JB |
1227 | |
1228 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1229 | /* | |
1230 | * make the BPC in transcoder be consistent with | |
1231 | * that in pipeconf reg. | |
1232 | */ | |
1233 | val &= ~PIPE_BPC_MASK; | |
1234 | val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK; | |
1235 | } | |
040484af JB |
1236 | I915_WRITE(reg, val | TRANS_ENABLE); |
1237 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
1238 | DRM_ERROR("failed to enable transcoder %d\n", pipe); | |
1239 | } | |
1240 | ||
1241 | static void intel_disable_transcoder(struct drm_i915_private *dev_priv, | |
1242 | enum pipe pipe) | |
1243 | { | |
1244 | int reg; | |
1245 | u32 val; | |
1246 | ||
1247 | /* FDI relies on the transcoder */ | |
1248 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1249 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1250 | ||
291906f1 JB |
1251 | /* Ports must be off as well */ |
1252 | assert_pch_ports_disabled(dev_priv, pipe); | |
1253 | ||
040484af JB |
1254 | reg = TRANSCONF(pipe); |
1255 | val = I915_READ(reg); | |
1256 | val &= ~TRANS_ENABLE; | |
1257 | I915_WRITE(reg, val); | |
1258 | /* wait for PCH transcoder off, transcoder state */ | |
1259 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
1260 | DRM_ERROR("failed to disable transcoder\n"); | |
1261 | } | |
1262 | ||
b24e7179 | 1263 | /** |
309cfea8 | 1264 | * intel_enable_pipe - enable a pipe, asserting requirements |
b24e7179 JB |
1265 | * @dev_priv: i915 private structure |
1266 | * @pipe: pipe to enable | |
040484af | 1267 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
b24e7179 JB |
1268 | * |
1269 | * Enable @pipe, making sure that various hardware specific requirements | |
1270 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. | |
1271 | * | |
1272 | * @pipe should be %PIPE_A or %PIPE_B. | |
1273 | * | |
1274 | * Will wait until the pipe is actually running (i.e. first vblank) before | |
1275 | * returning. | |
1276 | */ | |
040484af JB |
1277 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
1278 | bool pch_port) | |
b24e7179 JB |
1279 | { |
1280 | int reg; | |
1281 | u32 val; | |
1282 | ||
1283 | /* | |
1284 | * A pipe without a PLL won't actually be able to drive bits from | |
1285 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1286 | * need the check. | |
1287 | */ | |
1288 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
1289 | assert_pll_enabled(dev_priv, pipe); | |
040484af JB |
1290 | else { |
1291 | if (pch_port) { | |
1292 | /* if driving the PCH, we need FDI enabled */ | |
1293 | assert_fdi_rx_pll_enabled(dev_priv, pipe); | |
1294 | assert_fdi_tx_pll_enabled(dev_priv, pipe); | |
1295 | } | |
1296 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1297 | } | |
b24e7179 JB |
1298 | |
1299 | reg = PIPECONF(pipe); | |
1300 | val = I915_READ(reg); | |
00d70b15 CW |
1301 | if (val & PIPECONF_ENABLE) |
1302 | return; | |
1303 | ||
1304 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
b24e7179 JB |
1305 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1306 | } | |
1307 | ||
1308 | /** | |
309cfea8 | 1309 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1310 | * @dev_priv: i915 private structure |
1311 | * @pipe: pipe to disable | |
1312 | * | |
1313 | * Disable @pipe, making sure that various hardware specific requirements | |
1314 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1315 | * | |
1316 | * @pipe should be %PIPE_A or %PIPE_B. | |
1317 | * | |
1318 | * Will wait until the pipe has shut down before returning. | |
1319 | */ | |
1320 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1321 | enum pipe pipe) | |
1322 | { | |
1323 | int reg; | |
1324 | u32 val; | |
1325 | ||
1326 | /* | |
1327 | * Make sure planes won't keep trying to pump pixels to us, | |
1328 | * or we might hang the display. | |
1329 | */ | |
1330 | assert_planes_disabled(dev_priv, pipe); | |
1331 | ||
1332 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1333 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1334 | return; | |
1335 | ||
1336 | reg = PIPECONF(pipe); | |
1337 | val = I915_READ(reg); | |
00d70b15 CW |
1338 | if ((val & PIPECONF_ENABLE) == 0) |
1339 | return; | |
1340 | ||
1341 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
1342 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1343 | } | |
1344 | ||
d74362c9 KP |
1345 | /* |
1346 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1347 | * trigger in order to latch. The display address reg provides this. | |
1348 | */ | |
1349 | static void intel_flush_display_plane(struct drm_i915_private *dev_priv, | |
1350 | enum plane plane) | |
1351 | { | |
1352 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); | |
1353 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); | |
1354 | } | |
1355 | ||
b24e7179 JB |
1356 | /** |
1357 | * intel_enable_plane - enable a display plane on a given pipe | |
1358 | * @dev_priv: i915 private structure | |
1359 | * @plane: plane to enable | |
1360 | * @pipe: pipe being fed | |
1361 | * | |
1362 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1363 | */ | |
1364 | static void intel_enable_plane(struct drm_i915_private *dev_priv, | |
1365 | enum plane plane, enum pipe pipe) | |
1366 | { | |
1367 | int reg; | |
1368 | u32 val; | |
1369 | ||
1370 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1371 | assert_pipe_enabled(dev_priv, pipe); | |
1372 | ||
1373 | reg = DSPCNTR(plane); | |
1374 | val = I915_READ(reg); | |
00d70b15 CW |
1375 | if (val & DISPLAY_PLANE_ENABLE) |
1376 | return; | |
1377 | ||
1378 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
d74362c9 | 1379 | intel_flush_display_plane(dev_priv, plane); |
b24e7179 JB |
1380 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1381 | } | |
1382 | ||
b24e7179 JB |
1383 | /** |
1384 | * intel_disable_plane - disable a display plane | |
1385 | * @dev_priv: i915 private structure | |
1386 | * @plane: plane to disable | |
1387 | * @pipe: pipe consuming the data | |
1388 | * | |
1389 | * Disable @plane; should be an independent operation. | |
1390 | */ | |
1391 | static void intel_disable_plane(struct drm_i915_private *dev_priv, | |
1392 | enum plane plane, enum pipe pipe) | |
1393 | { | |
1394 | int reg; | |
1395 | u32 val; | |
1396 | ||
1397 | reg = DSPCNTR(plane); | |
1398 | val = I915_READ(reg); | |
00d70b15 CW |
1399 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1400 | return; | |
1401 | ||
1402 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
b24e7179 JB |
1403 | intel_flush_display_plane(dev_priv, plane); |
1404 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
1405 | } | |
1406 | ||
47a05eca | 1407 | static void disable_pch_dp(struct drm_i915_private *dev_priv, |
f0575e92 | 1408 | enum pipe pipe, int reg, u32 port_sel) |
47a05eca JB |
1409 | { |
1410 | u32 val = I915_READ(reg); | |
4e634389 | 1411 | if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) { |
f0575e92 | 1412 | DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe); |
47a05eca | 1413 | I915_WRITE(reg, val & ~DP_PORT_EN); |
f0575e92 | 1414 | } |
47a05eca JB |
1415 | } |
1416 | ||
1417 | static void disable_pch_hdmi(struct drm_i915_private *dev_priv, | |
1418 | enum pipe pipe, int reg) | |
1419 | { | |
1420 | u32 val = I915_READ(reg); | |
1519b995 | 1421 | if (hdmi_pipe_enabled(dev_priv, val, pipe)) { |
f0575e92 KP |
1422 | DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n", |
1423 | reg, pipe); | |
47a05eca | 1424 | I915_WRITE(reg, val & ~PORT_ENABLE); |
f0575e92 | 1425 | } |
47a05eca JB |
1426 | } |
1427 | ||
1428 | /* Disable any ports connected to this transcoder */ | |
1429 | static void intel_disable_pch_ports(struct drm_i915_private *dev_priv, | |
1430 | enum pipe pipe) | |
1431 | { | |
1432 | u32 reg, val; | |
1433 | ||
1434 | val = I915_READ(PCH_PP_CONTROL); | |
1435 | I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS); | |
1436 | ||
f0575e92 KP |
1437 | disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1438 | disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1439 | disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
47a05eca JB |
1440 | |
1441 | reg = PCH_ADPA; | |
1442 | val = I915_READ(reg); | |
1519b995 | 1443 | if (adpa_pipe_enabled(dev_priv, val, pipe)) |
47a05eca JB |
1444 | I915_WRITE(reg, val & ~ADPA_DAC_ENABLE); |
1445 | ||
1446 | reg = PCH_LVDS; | |
1447 | val = I915_READ(reg); | |
1519b995 KP |
1448 | if (lvds_pipe_enabled(dev_priv, val, pipe)) { |
1449 | DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val); | |
47a05eca JB |
1450 | I915_WRITE(reg, val & ~LVDS_PORT_EN); |
1451 | POSTING_READ(reg); | |
1452 | udelay(100); | |
1453 | } | |
1454 | ||
1455 | disable_pch_hdmi(dev_priv, pipe, HDMIB); | |
1456 | disable_pch_hdmi(dev_priv, pipe, HDMIC); | |
1457 | disable_pch_hdmi(dev_priv, pipe, HDMID); | |
1458 | } | |
1459 | ||
43a9539f CW |
1460 | static void i8xx_disable_fbc(struct drm_device *dev) |
1461 | { | |
1462 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1463 | u32 fbc_ctl; | |
1464 | ||
1465 | /* Disable compression */ | |
1466 | fbc_ctl = I915_READ(FBC_CONTROL); | |
1467 | if ((fbc_ctl & FBC_CTL_EN) == 0) | |
1468 | return; | |
1469 | ||
1470 | fbc_ctl &= ~FBC_CTL_EN; | |
1471 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
1472 | ||
1473 | /* Wait for compressing bit to clear */ | |
1474 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { | |
1475 | DRM_DEBUG_KMS("FBC idle timed out\n"); | |
1476 | return; | |
1477 | } | |
1478 | ||
1479 | DRM_DEBUG_KMS("disabled FBC\n"); | |
1480 | } | |
1481 | ||
80824003 JB |
1482 | static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1483 | { | |
1484 | struct drm_device *dev = crtc->dev; | |
1485 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1486 | struct drm_framebuffer *fb = crtc->fb; | |
1487 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1488 | struct drm_i915_gem_object *obj = intel_fb->obj; |
80824003 | 1489 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
016b9b61 | 1490 | int cfb_pitch; |
80824003 JB |
1491 | int plane, i; |
1492 | u32 fbc_ctl, fbc_ctl2; | |
1493 | ||
016b9b61 CW |
1494 | cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; |
1495 | if (fb->pitch < cfb_pitch) | |
1496 | cfb_pitch = fb->pitch; | |
80824003 JB |
1497 | |
1498 | /* FBC_CTL wants 64B units */ | |
016b9b61 CW |
1499 | cfb_pitch = (cfb_pitch / 64) - 1; |
1500 | plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; | |
80824003 JB |
1501 | |
1502 | /* Clear old tags */ | |
1503 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
1504 | I915_WRITE(FBC_TAG + (i * 4), 0); | |
1505 | ||
1506 | /* Set it up... */ | |
de568510 CW |
1507 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; |
1508 | fbc_ctl2 |= plane; | |
80824003 JB |
1509 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
1510 | I915_WRITE(FBC_FENCE_OFF, crtc->y); | |
1511 | ||
1512 | /* enable it... */ | |
1513 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; | |
ee25df2b | 1514 | if (IS_I945GM(dev)) |
49677901 | 1515 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
016b9b61 | 1516 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
80824003 | 1517 | fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; |
016b9b61 | 1518 | fbc_ctl |= obj->fence_reg; |
80824003 JB |
1519 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
1520 | ||
016b9b61 CW |
1521 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ", |
1522 | cfb_pitch, crtc->y, intel_crtc->plane); | |
80824003 JB |
1523 | } |
1524 | ||
ee5382ae | 1525 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
80824003 | 1526 | { |
80824003 JB |
1527 | struct drm_i915_private *dev_priv = dev->dev_private; |
1528 | ||
1529 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; | |
1530 | } | |
1531 | ||
74dff282 JB |
1532 | static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1533 | { | |
1534 | struct drm_device *dev = crtc->dev; | |
1535 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1536 | struct drm_framebuffer *fb = crtc->fb; | |
1537 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1538 | struct drm_i915_gem_object *obj = intel_fb->obj; |
74dff282 | 1539 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5eddb70b | 1540 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
74dff282 JB |
1541 | unsigned long stall_watermark = 200; |
1542 | u32 dpfc_ctl; | |
1543 | ||
74dff282 | 1544 | dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; |
016b9b61 | 1545 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; |
de568510 | 1546 | I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); |
74dff282 | 1547 | |
74dff282 JB |
1548 | I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
1549 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
1550 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
1551 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); | |
1552 | ||
1553 | /* enable it... */ | |
1554 | I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); | |
1555 | ||
28c97730 | 1556 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
74dff282 JB |
1557 | } |
1558 | ||
43a9539f | 1559 | static void g4x_disable_fbc(struct drm_device *dev) |
74dff282 JB |
1560 | { |
1561 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1562 | u32 dpfc_ctl; | |
1563 | ||
1564 | /* Disable compression */ | |
1565 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
bed4a673 CW |
1566 | if (dpfc_ctl & DPFC_CTL_EN) { |
1567 | dpfc_ctl &= ~DPFC_CTL_EN; | |
1568 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
74dff282 | 1569 | |
bed4a673 CW |
1570 | DRM_DEBUG_KMS("disabled FBC\n"); |
1571 | } | |
74dff282 JB |
1572 | } |
1573 | ||
ee5382ae | 1574 | static bool g4x_fbc_enabled(struct drm_device *dev) |
74dff282 | 1575 | { |
74dff282 JB |
1576 | struct drm_i915_private *dev_priv = dev->dev_private; |
1577 | ||
1578 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; | |
1579 | } | |
1580 | ||
4efe0708 JB |
1581 | static void sandybridge_blit_fbc_update(struct drm_device *dev) |
1582 | { | |
1583 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1584 | u32 blt_ecoskpd; | |
1585 | ||
1586 | /* Make sure blitter notifies FBC of writes */ | |
fcca7926 | 1587 | gen6_gt_force_wake_get(dev_priv); |
4efe0708 JB |
1588 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); |
1589 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << | |
1590 | GEN6_BLITTER_LOCK_SHIFT; | |
1591 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
1592 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; | |
1593 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
1594 | blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << | |
1595 | GEN6_BLITTER_LOCK_SHIFT); | |
1596 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
1597 | POSTING_READ(GEN6_BLITTER_ECOSKPD); | |
fcca7926 | 1598 | gen6_gt_force_wake_put(dev_priv); |
4efe0708 JB |
1599 | } |
1600 | ||
b52eb4dc ZY |
1601 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1602 | { | |
1603 | struct drm_device *dev = crtc->dev; | |
1604 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1605 | struct drm_framebuffer *fb = crtc->fb; | |
1606 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1607 | struct drm_i915_gem_object *obj = intel_fb->obj; |
b52eb4dc | 1608 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5eddb70b | 1609 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
b52eb4dc ZY |
1610 | unsigned long stall_watermark = 200; |
1611 | u32 dpfc_ctl; | |
1612 | ||
bed4a673 | 1613 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
b52eb4dc ZY |
1614 | dpfc_ctl &= DPFC_RESERVED; |
1615 | dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); | |
9ce9d069 CW |
1616 | /* Set persistent mode for front-buffer rendering, ala X. */ |
1617 | dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE; | |
016b9b61 | 1618 | dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg); |
de568510 | 1619 | I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); |
b52eb4dc | 1620 | |
b52eb4dc ZY |
1621 | I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
1622 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
1623 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
1624 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); | |
05394f39 | 1625 | I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); |
b52eb4dc | 1626 | /* enable it... */ |
bed4a673 | 1627 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
b52eb4dc | 1628 | |
9c04f015 YL |
1629 | if (IS_GEN6(dev)) { |
1630 | I915_WRITE(SNB_DPFC_CTL_SA, | |
016b9b61 | 1631 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
9c04f015 | 1632 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); |
4efe0708 | 1633 | sandybridge_blit_fbc_update(dev); |
9c04f015 YL |
1634 | } |
1635 | ||
b52eb4dc ZY |
1636 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
1637 | } | |
1638 | ||
43a9539f | 1639 | static void ironlake_disable_fbc(struct drm_device *dev) |
b52eb4dc ZY |
1640 | { |
1641 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1642 | u32 dpfc_ctl; | |
1643 | ||
1644 | /* Disable compression */ | |
1645 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
bed4a673 CW |
1646 | if (dpfc_ctl & DPFC_CTL_EN) { |
1647 | dpfc_ctl &= ~DPFC_CTL_EN; | |
1648 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
b52eb4dc | 1649 | |
bed4a673 CW |
1650 | DRM_DEBUG_KMS("disabled FBC\n"); |
1651 | } | |
b52eb4dc ZY |
1652 | } |
1653 | ||
1654 | static bool ironlake_fbc_enabled(struct drm_device *dev) | |
1655 | { | |
1656 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1657 | ||
1658 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; | |
1659 | } | |
1660 | ||
ee5382ae AJ |
1661 | bool intel_fbc_enabled(struct drm_device *dev) |
1662 | { | |
1663 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1664 | ||
1665 | if (!dev_priv->display.fbc_enabled) | |
1666 | return false; | |
1667 | ||
1668 | return dev_priv->display.fbc_enabled(dev); | |
1669 | } | |
1670 | ||
1630fe75 CW |
1671 | static void intel_fbc_work_fn(struct work_struct *__work) |
1672 | { | |
1673 | struct intel_fbc_work *work = | |
1674 | container_of(to_delayed_work(__work), | |
1675 | struct intel_fbc_work, work); | |
1676 | struct drm_device *dev = work->crtc->dev; | |
1677 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1678 | ||
1679 | mutex_lock(&dev->struct_mutex); | |
1680 | if (work == dev_priv->fbc_work) { | |
1681 | /* Double check that we haven't switched fb without cancelling | |
1682 | * the prior work. | |
1683 | */ | |
016b9b61 | 1684 | if (work->crtc->fb == work->fb) { |
1630fe75 CW |
1685 | dev_priv->display.enable_fbc(work->crtc, |
1686 | work->interval); | |
1687 | ||
016b9b61 CW |
1688 | dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane; |
1689 | dev_priv->cfb_fb = work->crtc->fb->base.id; | |
1690 | dev_priv->cfb_y = work->crtc->y; | |
1691 | } | |
1692 | ||
1630fe75 CW |
1693 | dev_priv->fbc_work = NULL; |
1694 | } | |
1695 | mutex_unlock(&dev->struct_mutex); | |
1696 | ||
1697 | kfree(work); | |
1698 | } | |
1699 | ||
1700 | static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) | |
1701 | { | |
1702 | if (dev_priv->fbc_work == NULL) | |
1703 | return; | |
1704 | ||
1705 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); | |
1706 | ||
1707 | /* Synchronisation is provided by struct_mutex and checking of | |
1708 | * dev_priv->fbc_work, so we can perform the cancellation | |
1709 | * entirely asynchronously. | |
1710 | */ | |
1711 | if (cancel_delayed_work(&dev_priv->fbc_work->work)) | |
1712 | /* tasklet was killed before being run, clean up */ | |
1713 | kfree(dev_priv->fbc_work); | |
1714 | ||
1715 | /* Mark the work as no longer wanted so that if it does | |
1716 | * wake-up (because the work was already running and waiting | |
1717 | * for our mutex), it will discover that is no longer | |
1718 | * necessary to run. | |
1719 | */ | |
1720 | dev_priv->fbc_work = NULL; | |
1721 | } | |
1722 | ||
43a9539f | 1723 | static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
ee5382ae | 1724 | { |
1630fe75 CW |
1725 | struct intel_fbc_work *work; |
1726 | struct drm_device *dev = crtc->dev; | |
1727 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee5382ae AJ |
1728 | |
1729 | if (!dev_priv->display.enable_fbc) | |
1730 | return; | |
1731 | ||
1630fe75 CW |
1732 | intel_cancel_fbc_work(dev_priv); |
1733 | ||
1734 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
1735 | if (work == NULL) { | |
1736 | dev_priv->display.enable_fbc(crtc, interval); | |
1737 | return; | |
1738 | } | |
1739 | ||
1740 | work->crtc = crtc; | |
1741 | work->fb = crtc->fb; | |
1742 | work->interval = interval; | |
1743 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); | |
1744 | ||
1745 | dev_priv->fbc_work = work; | |
1746 | ||
1747 | DRM_DEBUG_KMS("scheduling delayed FBC enable\n"); | |
1748 | ||
1749 | /* Delay the actual enabling to let pageflipping cease and the | |
016b9b61 CW |
1750 | * display to settle before starting the compression. Note that |
1751 | * this delay also serves a second purpose: it allows for a | |
1752 | * vblank to pass after disabling the FBC before we attempt | |
1753 | * to modify the control registers. | |
1630fe75 CW |
1754 | * |
1755 | * A more complicated solution would involve tracking vblanks | |
1756 | * following the termination of the page-flipping sequence | |
1757 | * and indeed performing the enable as a co-routine and not | |
1758 | * waiting synchronously upon the vblank. | |
1759 | */ | |
1760 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); | |
ee5382ae AJ |
1761 | } |
1762 | ||
1763 | void intel_disable_fbc(struct drm_device *dev) | |
1764 | { | |
1765 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1766 | ||
1630fe75 CW |
1767 | intel_cancel_fbc_work(dev_priv); |
1768 | ||
ee5382ae AJ |
1769 | if (!dev_priv->display.disable_fbc) |
1770 | return; | |
1771 | ||
1772 | dev_priv->display.disable_fbc(dev); | |
016b9b61 | 1773 | dev_priv->cfb_plane = -1; |
ee5382ae AJ |
1774 | } |
1775 | ||
80824003 JB |
1776 | /** |
1777 | * intel_update_fbc - enable/disable FBC as needed | |
bed4a673 | 1778 | * @dev: the drm_device |
80824003 JB |
1779 | * |
1780 | * Set up the framebuffer compression hardware at mode set time. We | |
1781 | * enable it if possible: | |
1782 | * - plane A only (on pre-965) | |
1783 | * - no pixel mulitply/line duplication | |
1784 | * - no alpha buffer discard | |
1785 | * - no dual wide | |
1786 | * - framebuffer <= 2048 in width, 1536 in height | |
1787 | * | |
1788 | * We can't assume that any compression will take place (worst case), | |
1789 | * so the compressed buffer has to be the same size as the uncompressed | |
1790 | * one. It also must reside (along with the line length buffer) in | |
1791 | * stolen memory. | |
1792 | * | |
1793 | * We need to enable/disable FBC on a global basis. | |
1794 | */ | |
bed4a673 | 1795 | static void intel_update_fbc(struct drm_device *dev) |
80824003 | 1796 | { |
80824003 | 1797 | struct drm_i915_private *dev_priv = dev->dev_private; |
bed4a673 CW |
1798 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
1799 | struct intel_crtc *intel_crtc; | |
1800 | struct drm_framebuffer *fb; | |
80824003 | 1801 | struct intel_framebuffer *intel_fb; |
05394f39 | 1802 | struct drm_i915_gem_object *obj; |
cd0de039 | 1803 | int enable_fbc; |
9c928d16 JB |
1804 | |
1805 | DRM_DEBUG_KMS("\n"); | |
80824003 JB |
1806 | |
1807 | if (!i915_powersave) | |
1808 | return; | |
1809 | ||
ee5382ae | 1810 | if (!I915_HAS_FBC(dev)) |
e70236a8 JB |
1811 | return; |
1812 | ||
80824003 JB |
1813 | /* |
1814 | * If FBC is already on, we just have to verify that we can | |
1815 | * keep it that way... | |
1816 | * Need to disable if: | |
9c928d16 | 1817 | * - more than one pipe is active |
80824003 JB |
1818 | * - changing FBC params (stride, fence, mode) |
1819 | * - new fb is too large to fit in compressed buffer | |
1820 | * - going to an unsupported config (interlace, pixel multiply, etc.) | |
1821 | */ | |
9c928d16 | 1822 | list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { |
d210246a | 1823 | if (tmp_crtc->enabled && tmp_crtc->fb) { |
bed4a673 CW |
1824 | if (crtc) { |
1825 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); | |
1826 | dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; | |
1827 | goto out_disable; | |
1828 | } | |
1829 | crtc = tmp_crtc; | |
1830 | } | |
9c928d16 | 1831 | } |
bed4a673 CW |
1832 | |
1833 | if (!crtc || crtc->fb == NULL) { | |
1834 | DRM_DEBUG_KMS("no output, disabling\n"); | |
1835 | dev_priv->no_fbc_reason = FBC_NO_OUTPUT; | |
9c928d16 JB |
1836 | goto out_disable; |
1837 | } | |
bed4a673 CW |
1838 | |
1839 | intel_crtc = to_intel_crtc(crtc); | |
1840 | fb = crtc->fb; | |
1841 | intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1842 | obj = intel_fb->obj; |
bed4a673 | 1843 | |
cd0de039 KP |
1844 | enable_fbc = i915_enable_fbc; |
1845 | if (enable_fbc < 0) { | |
1846 | DRM_DEBUG_KMS("fbc set to per-chip default\n"); | |
1847 | enable_fbc = 1; | |
1848 | if (INTEL_INFO(dev)->gen <= 5) | |
1849 | enable_fbc = 0; | |
1850 | } | |
1851 | if (!enable_fbc) { | |
1852 | DRM_DEBUG_KMS("fbc disabled per module param\n"); | |
c1a9f047 JB |
1853 | dev_priv->no_fbc_reason = FBC_MODULE_PARAM; |
1854 | goto out_disable; | |
1855 | } | |
05394f39 | 1856 | if (intel_fb->obj->base.size > dev_priv->cfb_size) { |
28c97730 | 1857 | DRM_DEBUG_KMS("framebuffer too large, disabling " |
5eddb70b | 1858 | "compression\n"); |
b5e50c3f | 1859 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
80824003 JB |
1860 | goto out_disable; |
1861 | } | |
bed4a673 CW |
1862 | if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || |
1863 | (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { | |
28c97730 | 1864 | DRM_DEBUG_KMS("mode incompatible with compression, " |
5eddb70b | 1865 | "disabling\n"); |
b5e50c3f | 1866 | dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; |
80824003 JB |
1867 | goto out_disable; |
1868 | } | |
bed4a673 CW |
1869 | if ((crtc->mode.hdisplay > 2048) || |
1870 | (crtc->mode.vdisplay > 1536)) { | |
28c97730 | 1871 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); |
b5e50c3f | 1872 | dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; |
80824003 JB |
1873 | goto out_disable; |
1874 | } | |
bed4a673 | 1875 | if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { |
28c97730 | 1876 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); |
b5e50c3f | 1877 | dev_priv->no_fbc_reason = FBC_BAD_PLANE; |
80824003 JB |
1878 | goto out_disable; |
1879 | } | |
de568510 CW |
1880 | |
1881 | /* The use of a CPU fence is mandatory in order to detect writes | |
1882 | * by the CPU to the scanout and trigger updates to the FBC. | |
1883 | */ | |
1884 | if (obj->tiling_mode != I915_TILING_X || | |
1885 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
1886 | DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); | |
b5e50c3f | 1887 | dev_priv->no_fbc_reason = FBC_NOT_TILED; |
80824003 JB |
1888 | goto out_disable; |
1889 | } | |
1890 | ||
c924b934 JW |
1891 | /* If the kernel debugger is active, always disable compression */ |
1892 | if (in_dbg_master()) | |
1893 | goto out_disable; | |
1894 | ||
016b9b61 CW |
1895 | /* If the scanout has not changed, don't modify the FBC settings. |
1896 | * Note that we make the fundamental assumption that the fb->obj | |
1897 | * cannot be unpinned (and have its GTT offset and fence revoked) | |
1898 | * without first being decoupled from the scanout and FBC disabled. | |
1899 | */ | |
1900 | if (dev_priv->cfb_plane == intel_crtc->plane && | |
1901 | dev_priv->cfb_fb == fb->base.id && | |
1902 | dev_priv->cfb_y == crtc->y) | |
1903 | return; | |
1904 | ||
1905 | if (intel_fbc_enabled(dev)) { | |
1906 | /* We update FBC along two paths, after changing fb/crtc | |
1907 | * configuration (modeswitching) and after page-flipping | |
1908 | * finishes. For the latter, we know that not only did | |
1909 | * we disable the FBC at the start of the page-flip | |
1910 | * sequence, but also more than one vblank has passed. | |
1911 | * | |
1912 | * For the former case of modeswitching, it is possible | |
1913 | * to switch between two FBC valid configurations | |
1914 | * instantaneously so we do need to disable the FBC | |
1915 | * before we can modify its control registers. We also | |
1916 | * have to wait for the next vblank for that to take | |
1917 | * effect. However, since we delay enabling FBC we can | |
1918 | * assume that a vblank has passed since disabling and | |
1919 | * that we can safely alter the registers in the deferred | |
1920 | * callback. | |
1921 | * | |
1922 | * In the scenario that we go from a valid to invalid | |
1923 | * and then back to valid FBC configuration we have | |
1924 | * no strict enforcement that a vblank occurred since | |
1925 | * disabling the FBC. However, along all current pipe | |
1926 | * disabling paths we do need to wait for a vblank at | |
1927 | * some point. And we wait before enabling FBC anyway. | |
1928 | */ | |
1929 | DRM_DEBUG_KMS("disabling active FBC for update\n"); | |
1930 | intel_disable_fbc(dev); | |
1931 | } | |
1932 | ||
bed4a673 | 1933 | intel_enable_fbc(crtc, 500); |
80824003 JB |
1934 | return; |
1935 | ||
1936 | out_disable: | |
80824003 | 1937 | /* Multiple disables should be harmless */ |
a939406f CW |
1938 | if (intel_fbc_enabled(dev)) { |
1939 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); | |
ee5382ae | 1940 | intel_disable_fbc(dev); |
a939406f | 1941 | } |
80824003 JB |
1942 | } |
1943 | ||
127bd2ac | 1944 | int |
48b956c5 | 1945 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 1946 | struct drm_i915_gem_object *obj, |
919926ae | 1947 | struct intel_ring_buffer *pipelined) |
6b95a207 | 1948 | { |
ce453d81 | 1949 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
1950 | u32 alignment; |
1951 | int ret; | |
1952 | ||
05394f39 | 1953 | switch (obj->tiling_mode) { |
6b95a207 | 1954 | case I915_TILING_NONE: |
534843da CW |
1955 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1956 | alignment = 128 * 1024; | |
a6c45cf0 | 1957 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
1958 | alignment = 4 * 1024; |
1959 | else | |
1960 | alignment = 64 * 1024; | |
6b95a207 KH |
1961 | break; |
1962 | case I915_TILING_X: | |
1963 | /* pin() will align the object as required by fence */ | |
1964 | alignment = 0; | |
1965 | break; | |
1966 | case I915_TILING_Y: | |
1967 | /* FIXME: Is this true? */ | |
1968 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); | |
1969 | return -EINVAL; | |
1970 | default: | |
1971 | BUG(); | |
1972 | } | |
1973 | ||
ce453d81 | 1974 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 1975 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 1976 | if (ret) |
ce453d81 | 1977 | goto err_interruptible; |
6b95a207 KH |
1978 | |
1979 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
1980 | * fence, whereas 965+ only requires a fence if using | |
1981 | * framebuffer compression. For simplicity, we always install | |
1982 | * a fence as the cost is not that onerous. | |
1983 | */ | |
05394f39 | 1984 | if (obj->tiling_mode != I915_TILING_NONE) { |
ce453d81 | 1985 | ret = i915_gem_object_get_fence(obj, pipelined); |
48b956c5 CW |
1986 | if (ret) |
1987 | goto err_unpin; | |
6b95a207 KH |
1988 | } |
1989 | ||
ce453d81 | 1990 | dev_priv->mm.interruptible = true; |
6b95a207 | 1991 | return 0; |
48b956c5 CW |
1992 | |
1993 | err_unpin: | |
1994 | i915_gem_object_unpin(obj); | |
ce453d81 CW |
1995 | err_interruptible: |
1996 | dev_priv->mm.interruptible = true; | |
48b956c5 | 1997 | return ret; |
6b95a207 KH |
1998 | } |
1999 | ||
17638cd6 JB |
2000 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2001 | int x, int y) | |
81255565 JB |
2002 | { |
2003 | struct drm_device *dev = crtc->dev; | |
2004 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2005 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2006 | struct intel_framebuffer *intel_fb; | |
05394f39 | 2007 | struct drm_i915_gem_object *obj; |
81255565 JB |
2008 | int plane = intel_crtc->plane; |
2009 | unsigned long Start, Offset; | |
81255565 | 2010 | u32 dspcntr; |
5eddb70b | 2011 | u32 reg; |
81255565 JB |
2012 | |
2013 | switch (plane) { | |
2014 | case 0: | |
2015 | case 1: | |
2016 | break; | |
2017 | default: | |
2018 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
2019 | return -EINVAL; | |
2020 | } | |
2021 | ||
2022 | intel_fb = to_intel_framebuffer(fb); | |
2023 | obj = intel_fb->obj; | |
81255565 | 2024 | |
5eddb70b CW |
2025 | reg = DSPCNTR(plane); |
2026 | dspcntr = I915_READ(reg); | |
81255565 JB |
2027 | /* Mask out pixel format bits in case we change it */ |
2028 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
2029 | switch (fb->bits_per_pixel) { | |
2030 | case 8: | |
2031 | dspcntr |= DISPPLANE_8BPP; | |
2032 | break; | |
2033 | case 16: | |
2034 | if (fb->depth == 15) | |
2035 | dspcntr |= DISPPLANE_15_16BPP; | |
2036 | else | |
2037 | dspcntr |= DISPPLANE_16BPP; | |
2038 | break; | |
2039 | case 24: | |
2040 | case 32: | |
2041 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
2042 | break; | |
2043 | default: | |
17638cd6 | 2044 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); |
81255565 JB |
2045 | return -EINVAL; |
2046 | } | |
a6c45cf0 | 2047 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2048 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2049 | dspcntr |= DISPPLANE_TILED; |
2050 | else | |
2051 | dspcntr &= ~DISPPLANE_TILED; | |
2052 | } | |
2053 | ||
5eddb70b | 2054 | I915_WRITE(reg, dspcntr); |
81255565 | 2055 | |
05394f39 | 2056 | Start = obj->gtt_offset; |
81255565 JB |
2057 | Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8); |
2058 | ||
4e6cfefc CW |
2059 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2060 | Start, Offset, x, y, fb->pitch); | |
5eddb70b | 2061 | I915_WRITE(DSPSTRIDE(plane), fb->pitch); |
a6c45cf0 | 2062 | if (INTEL_INFO(dev)->gen >= 4) { |
5eddb70b CW |
2063 | I915_WRITE(DSPSURF(plane), Start); |
2064 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2065 | I915_WRITE(DSPADDR(plane), Offset); | |
2066 | } else | |
2067 | I915_WRITE(DSPADDR(plane), Start + Offset); | |
2068 | POSTING_READ(reg); | |
81255565 | 2069 | |
17638cd6 JB |
2070 | return 0; |
2071 | } | |
2072 | ||
2073 | static int ironlake_update_plane(struct drm_crtc *crtc, | |
2074 | struct drm_framebuffer *fb, int x, int y) | |
2075 | { | |
2076 | struct drm_device *dev = crtc->dev; | |
2077 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2078 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2079 | struct intel_framebuffer *intel_fb; | |
2080 | struct drm_i915_gem_object *obj; | |
2081 | int plane = intel_crtc->plane; | |
2082 | unsigned long Start, Offset; | |
2083 | u32 dspcntr; | |
2084 | u32 reg; | |
2085 | ||
2086 | switch (plane) { | |
2087 | case 0: | |
2088 | case 1: | |
2089 | break; | |
2090 | default: | |
2091 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
2092 | return -EINVAL; | |
2093 | } | |
2094 | ||
2095 | intel_fb = to_intel_framebuffer(fb); | |
2096 | obj = intel_fb->obj; | |
2097 | ||
2098 | reg = DSPCNTR(plane); | |
2099 | dspcntr = I915_READ(reg); | |
2100 | /* Mask out pixel format bits in case we change it */ | |
2101 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
2102 | switch (fb->bits_per_pixel) { | |
2103 | case 8: | |
2104 | dspcntr |= DISPPLANE_8BPP; | |
2105 | break; | |
2106 | case 16: | |
2107 | if (fb->depth != 16) | |
2108 | return -EINVAL; | |
2109 | ||
2110 | dspcntr |= DISPPLANE_16BPP; | |
2111 | break; | |
2112 | case 24: | |
2113 | case 32: | |
2114 | if (fb->depth == 24) | |
2115 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
2116 | else if (fb->depth == 30) | |
2117 | dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA; | |
2118 | else | |
2119 | return -EINVAL; | |
2120 | break; | |
2121 | default: | |
2122 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); | |
2123 | return -EINVAL; | |
2124 | } | |
2125 | ||
2126 | if (obj->tiling_mode != I915_TILING_NONE) | |
2127 | dspcntr |= DISPPLANE_TILED; | |
2128 | else | |
2129 | dspcntr &= ~DISPPLANE_TILED; | |
2130 | ||
2131 | /* must disable */ | |
2132 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2133 | ||
2134 | I915_WRITE(reg, dspcntr); | |
2135 | ||
2136 | Start = obj->gtt_offset; | |
2137 | Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8); | |
2138 | ||
2139 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", | |
2140 | Start, Offset, x, y, fb->pitch); | |
2141 | I915_WRITE(DSPSTRIDE(plane), fb->pitch); | |
2142 | I915_WRITE(DSPSURF(plane), Start); | |
2143 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2144 | I915_WRITE(DSPADDR(plane), Offset); | |
2145 | POSTING_READ(reg); | |
2146 | ||
2147 | return 0; | |
2148 | } | |
2149 | ||
2150 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2151 | static int | |
2152 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2153 | int x, int y, enum mode_set_atomic state) | |
2154 | { | |
2155 | struct drm_device *dev = crtc->dev; | |
2156 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2157 | int ret; | |
2158 | ||
2159 | ret = dev_priv->display.update_plane(crtc, fb, x, y); | |
2160 | if (ret) | |
2161 | return ret; | |
2162 | ||
bed4a673 | 2163 | intel_update_fbc(dev); |
3dec0095 | 2164 | intel_increase_pllclock(crtc); |
81255565 JB |
2165 | |
2166 | return 0; | |
2167 | } | |
2168 | ||
5c3b82e2 | 2169 | static int |
3c4fdcfb KH |
2170 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
2171 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
2172 | { |
2173 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
2174 | struct drm_i915_master_private *master_priv; |
2175 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5c3b82e2 | 2176 | int ret; |
79e53945 JB |
2177 | |
2178 | /* no fb bound */ | |
2179 | if (!crtc->fb) { | |
a5071c2f | 2180 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2181 | return 0; |
2182 | } | |
2183 | ||
265db958 | 2184 | switch (intel_crtc->plane) { |
5c3b82e2 CW |
2185 | case 0: |
2186 | case 1: | |
2187 | break; | |
2188 | default: | |
a5071c2f | 2189 | DRM_ERROR("no plane for crtc\n"); |
5c3b82e2 | 2190 | return -EINVAL; |
79e53945 JB |
2191 | } |
2192 | ||
5c3b82e2 | 2193 | mutex_lock(&dev->struct_mutex); |
265db958 CW |
2194 | ret = intel_pin_and_fence_fb_obj(dev, |
2195 | to_intel_framebuffer(crtc->fb)->obj, | |
919926ae | 2196 | NULL); |
5c3b82e2 CW |
2197 | if (ret != 0) { |
2198 | mutex_unlock(&dev->struct_mutex); | |
a5071c2f | 2199 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2200 | return ret; |
2201 | } | |
79e53945 | 2202 | |
265db958 | 2203 | if (old_fb) { |
e6c3a2a6 | 2204 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 2205 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; |
265db958 | 2206 | |
e6c3a2a6 | 2207 | wait_event(dev_priv->pending_flip_queue, |
01eec727 | 2208 | atomic_read(&dev_priv->mm.wedged) || |
05394f39 | 2209 | atomic_read(&obj->pending_flip) == 0); |
85345517 CW |
2210 | |
2211 | /* Big Hammer, we also need to ensure that any pending | |
2212 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2213 | * current scanout is retired before unpinning the old | |
2214 | * framebuffer. | |
01eec727 CW |
2215 | * |
2216 | * This should only fail upon a hung GPU, in which case we | |
2217 | * can safely continue. | |
85345517 | 2218 | */ |
a8198eea | 2219 | ret = i915_gem_object_finish_gpu(obj); |
01eec727 | 2220 | (void) ret; |
265db958 CW |
2221 | } |
2222 | ||
21c74a8e JW |
2223 | ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y, |
2224 | LEAVE_ATOMIC_MODE_SET); | |
4e6cfefc | 2225 | if (ret) { |
265db958 | 2226 | i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj); |
5c3b82e2 | 2227 | mutex_unlock(&dev->struct_mutex); |
a5071c2f | 2228 | DRM_ERROR("failed to update base address\n"); |
4e6cfefc | 2229 | return ret; |
79e53945 | 2230 | } |
3c4fdcfb | 2231 | |
b7f1de28 CW |
2232 | if (old_fb) { |
2233 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
265db958 | 2234 | i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 2235 | } |
652c393a | 2236 | |
5c3b82e2 | 2237 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
2238 | |
2239 | if (!dev->primary->master) | |
5c3b82e2 | 2240 | return 0; |
79e53945 JB |
2241 | |
2242 | master_priv = dev->primary->master->driver_priv; | |
2243 | if (!master_priv->sarea_priv) | |
5c3b82e2 | 2244 | return 0; |
79e53945 | 2245 | |
265db958 | 2246 | if (intel_crtc->pipe) { |
79e53945 JB |
2247 | master_priv->sarea_priv->pipeB_x = x; |
2248 | master_priv->sarea_priv->pipeB_y = y; | |
5c3b82e2 CW |
2249 | } else { |
2250 | master_priv->sarea_priv->pipeA_x = x; | |
2251 | master_priv->sarea_priv->pipeA_y = y; | |
79e53945 | 2252 | } |
5c3b82e2 CW |
2253 | |
2254 | return 0; | |
79e53945 JB |
2255 | } |
2256 | ||
5eddb70b | 2257 | static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) |
32f9d658 ZW |
2258 | { |
2259 | struct drm_device *dev = crtc->dev; | |
2260 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2261 | u32 dpa_ctl; | |
2262 | ||
28c97730 | 2263 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
32f9d658 ZW |
2264 | dpa_ctl = I915_READ(DP_A); |
2265 | dpa_ctl &= ~DP_PLL_FREQ_MASK; | |
2266 | ||
2267 | if (clock < 200000) { | |
2268 | u32 temp; | |
2269 | dpa_ctl |= DP_PLL_FREQ_160MHZ; | |
2270 | /* workaround for 160Mhz: | |
2271 | 1) program 0x4600c bits 15:0 = 0x8124 | |
2272 | 2) program 0x46010 bit 0 = 1 | |
2273 | 3) program 0x46034 bit 24 = 1 | |
2274 | 4) program 0x64000 bit 14 = 1 | |
2275 | */ | |
2276 | temp = I915_READ(0x4600c); | |
2277 | temp &= 0xffff0000; | |
2278 | I915_WRITE(0x4600c, temp | 0x8124); | |
2279 | ||
2280 | temp = I915_READ(0x46010); | |
2281 | I915_WRITE(0x46010, temp | 1); | |
2282 | ||
2283 | temp = I915_READ(0x46034); | |
2284 | I915_WRITE(0x46034, temp | (1 << 24)); | |
2285 | } else { | |
2286 | dpa_ctl |= DP_PLL_FREQ_270MHZ; | |
2287 | } | |
2288 | I915_WRITE(DP_A, dpa_ctl); | |
2289 | ||
5eddb70b | 2290 | POSTING_READ(DP_A); |
32f9d658 ZW |
2291 | udelay(500); |
2292 | } | |
2293 | ||
5e84e1a4 ZW |
2294 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2295 | { | |
2296 | struct drm_device *dev = crtc->dev; | |
2297 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2298 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2299 | int pipe = intel_crtc->pipe; | |
2300 | u32 reg, temp; | |
2301 | ||
2302 | /* enable normal train */ | |
2303 | reg = FDI_TX_CTL(pipe); | |
2304 | temp = I915_READ(reg); | |
61e499bf | 2305 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2306 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2307 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2308 | } else { |
2309 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2310 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2311 | } |
5e84e1a4 ZW |
2312 | I915_WRITE(reg, temp); |
2313 | ||
2314 | reg = FDI_RX_CTL(pipe); | |
2315 | temp = I915_READ(reg); | |
2316 | if (HAS_PCH_CPT(dev)) { | |
2317 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2318 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2319 | } else { | |
2320 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2321 | temp |= FDI_LINK_TRAIN_NONE; | |
2322 | } | |
2323 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2324 | ||
2325 | /* wait one idle pattern time */ | |
2326 | POSTING_READ(reg); | |
2327 | udelay(1000); | |
357555c0 JB |
2328 | |
2329 | /* IVB wants error correction enabled */ | |
2330 | if (IS_IVYBRIDGE(dev)) | |
2331 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2332 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2333 | } |
2334 | ||
291427f5 JB |
2335 | static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe) |
2336 | { | |
2337 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2338 | u32 flags = I915_READ(SOUTH_CHICKEN1); | |
2339 | ||
2340 | flags |= FDI_PHASE_SYNC_OVR(pipe); | |
2341 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */ | |
2342 | flags |= FDI_PHASE_SYNC_EN(pipe); | |
2343 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */ | |
2344 | POSTING_READ(SOUTH_CHICKEN1); | |
2345 | } | |
2346 | ||
8db9d77b ZW |
2347 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2348 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2349 | { | |
2350 | struct drm_device *dev = crtc->dev; | |
2351 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2352 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2353 | int pipe = intel_crtc->pipe; | |
0fc932b8 | 2354 | int plane = intel_crtc->plane; |
5eddb70b | 2355 | u32 reg, temp, tries; |
8db9d77b | 2356 | |
0fc932b8 JB |
2357 | /* FDI needs bits from pipe & plane first */ |
2358 | assert_pipe_enabled(dev_priv, pipe); | |
2359 | assert_plane_enabled(dev_priv, plane); | |
2360 | ||
e1a44743 AJ |
2361 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2362 | for train result */ | |
5eddb70b CW |
2363 | reg = FDI_RX_IMR(pipe); |
2364 | temp = I915_READ(reg); | |
e1a44743 AJ |
2365 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2366 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2367 | I915_WRITE(reg, temp); |
2368 | I915_READ(reg); | |
e1a44743 AJ |
2369 | udelay(150); |
2370 | ||
8db9d77b | 2371 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2372 | reg = FDI_TX_CTL(pipe); |
2373 | temp = I915_READ(reg); | |
77ffb597 AJ |
2374 | temp &= ~(7 << 19); |
2375 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2376 | temp &= ~FDI_LINK_TRAIN_NONE; |
2377 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2378 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2379 | |
5eddb70b CW |
2380 | reg = FDI_RX_CTL(pipe); |
2381 | temp = I915_READ(reg); | |
8db9d77b ZW |
2382 | temp &= ~FDI_LINK_TRAIN_NONE; |
2383 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2384 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2385 | ||
2386 | POSTING_READ(reg); | |
8db9d77b ZW |
2387 | udelay(150); |
2388 | ||
5b2adf89 | 2389 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
6f06ce18 JB |
2390 | if (HAS_PCH_IBX(dev)) { |
2391 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
2392 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2393 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
2394 | } | |
5b2adf89 | 2395 | |
5eddb70b | 2396 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2397 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2398 | temp = I915_READ(reg); |
8db9d77b ZW |
2399 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2400 | ||
2401 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2402 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2403 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2404 | break; |
2405 | } | |
8db9d77b | 2406 | } |
e1a44743 | 2407 | if (tries == 5) |
5eddb70b | 2408 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2409 | |
2410 | /* Train 2 */ | |
5eddb70b CW |
2411 | reg = FDI_TX_CTL(pipe); |
2412 | temp = I915_READ(reg); | |
8db9d77b ZW |
2413 | temp &= ~FDI_LINK_TRAIN_NONE; |
2414 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2415 | I915_WRITE(reg, temp); |
8db9d77b | 2416 | |
5eddb70b CW |
2417 | reg = FDI_RX_CTL(pipe); |
2418 | temp = I915_READ(reg); | |
8db9d77b ZW |
2419 | temp &= ~FDI_LINK_TRAIN_NONE; |
2420 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2421 | I915_WRITE(reg, temp); |
8db9d77b | 2422 | |
5eddb70b CW |
2423 | POSTING_READ(reg); |
2424 | udelay(150); | |
8db9d77b | 2425 | |
5eddb70b | 2426 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2427 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2428 | temp = I915_READ(reg); |
8db9d77b ZW |
2429 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2430 | ||
2431 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2432 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2433 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2434 | break; | |
2435 | } | |
8db9d77b | 2436 | } |
e1a44743 | 2437 | if (tries == 5) |
5eddb70b | 2438 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2439 | |
2440 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2441 | |
8db9d77b ZW |
2442 | } |
2443 | ||
0206e353 | 2444 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2445 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2446 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2447 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2448 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2449 | }; | |
2450 | ||
2451 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2452 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2453 | { | |
2454 | struct drm_device *dev = crtc->dev; | |
2455 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2456 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2457 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2458 | u32 reg, temp, i; |
8db9d77b | 2459 | |
e1a44743 AJ |
2460 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2461 | for train result */ | |
5eddb70b CW |
2462 | reg = FDI_RX_IMR(pipe); |
2463 | temp = I915_READ(reg); | |
e1a44743 AJ |
2464 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2465 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2466 | I915_WRITE(reg, temp); |
2467 | ||
2468 | POSTING_READ(reg); | |
e1a44743 AJ |
2469 | udelay(150); |
2470 | ||
8db9d77b | 2471 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2472 | reg = FDI_TX_CTL(pipe); |
2473 | temp = I915_READ(reg); | |
77ffb597 AJ |
2474 | temp &= ~(7 << 19); |
2475 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2476 | temp &= ~FDI_LINK_TRAIN_NONE; |
2477 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2478 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2479 | /* SNB-B */ | |
2480 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2481 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2482 | |
5eddb70b CW |
2483 | reg = FDI_RX_CTL(pipe); |
2484 | temp = I915_READ(reg); | |
8db9d77b ZW |
2485 | if (HAS_PCH_CPT(dev)) { |
2486 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2487 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2488 | } else { | |
2489 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2490 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2491 | } | |
5eddb70b CW |
2492 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2493 | ||
2494 | POSTING_READ(reg); | |
8db9d77b ZW |
2495 | udelay(150); |
2496 | ||
291427f5 JB |
2497 | if (HAS_PCH_CPT(dev)) |
2498 | cpt_phase_pointer_enable(dev, pipe); | |
2499 | ||
0206e353 | 2500 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2501 | reg = FDI_TX_CTL(pipe); |
2502 | temp = I915_READ(reg); | |
8db9d77b ZW |
2503 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2504 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2505 | I915_WRITE(reg, temp); |
2506 | ||
2507 | POSTING_READ(reg); | |
8db9d77b ZW |
2508 | udelay(500); |
2509 | ||
5eddb70b CW |
2510 | reg = FDI_RX_IIR(pipe); |
2511 | temp = I915_READ(reg); | |
8db9d77b ZW |
2512 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2513 | ||
2514 | if (temp & FDI_RX_BIT_LOCK) { | |
5eddb70b | 2515 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2516 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
2517 | break; | |
2518 | } | |
2519 | } | |
2520 | if (i == 4) | |
5eddb70b | 2521 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2522 | |
2523 | /* Train 2 */ | |
5eddb70b CW |
2524 | reg = FDI_TX_CTL(pipe); |
2525 | temp = I915_READ(reg); | |
8db9d77b ZW |
2526 | temp &= ~FDI_LINK_TRAIN_NONE; |
2527 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2528 | if (IS_GEN6(dev)) { | |
2529 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2530 | /* SNB-B */ | |
2531 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2532 | } | |
5eddb70b | 2533 | I915_WRITE(reg, temp); |
8db9d77b | 2534 | |
5eddb70b CW |
2535 | reg = FDI_RX_CTL(pipe); |
2536 | temp = I915_READ(reg); | |
8db9d77b ZW |
2537 | if (HAS_PCH_CPT(dev)) { |
2538 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2539 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2540 | } else { | |
2541 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2542 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2543 | } | |
5eddb70b CW |
2544 | I915_WRITE(reg, temp); |
2545 | ||
2546 | POSTING_READ(reg); | |
8db9d77b ZW |
2547 | udelay(150); |
2548 | ||
0206e353 | 2549 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2550 | reg = FDI_TX_CTL(pipe); |
2551 | temp = I915_READ(reg); | |
8db9d77b ZW |
2552 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2553 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2554 | I915_WRITE(reg, temp); |
2555 | ||
2556 | POSTING_READ(reg); | |
8db9d77b ZW |
2557 | udelay(500); |
2558 | ||
5eddb70b CW |
2559 | reg = FDI_RX_IIR(pipe); |
2560 | temp = I915_READ(reg); | |
8db9d77b ZW |
2561 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2562 | ||
2563 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2564 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2565 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2566 | break; | |
2567 | } | |
2568 | } | |
2569 | if (i == 4) | |
5eddb70b | 2570 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2571 | |
2572 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2573 | } | |
2574 | ||
357555c0 JB |
2575 | /* Manual link training for Ivy Bridge A0 parts */ |
2576 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
2577 | { | |
2578 | struct drm_device *dev = crtc->dev; | |
2579 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2580 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2581 | int pipe = intel_crtc->pipe; | |
2582 | u32 reg, temp, i; | |
2583 | ||
2584 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
2585 | for train result */ | |
2586 | reg = FDI_RX_IMR(pipe); | |
2587 | temp = I915_READ(reg); | |
2588 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
2589 | temp &= ~FDI_RX_BIT_LOCK; | |
2590 | I915_WRITE(reg, temp); | |
2591 | ||
2592 | POSTING_READ(reg); | |
2593 | udelay(150); | |
2594 | ||
2595 | /* enable CPU FDI TX and PCH FDI RX */ | |
2596 | reg = FDI_TX_CTL(pipe); | |
2597 | temp = I915_READ(reg); | |
2598 | temp &= ~(7 << 19); | |
2599 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
2600 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
2601 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
2602 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2603 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2604 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
2605 | ||
2606 | reg = FDI_RX_CTL(pipe); | |
2607 | temp = I915_READ(reg); | |
2608 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
2609 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2610 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2611 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
2612 | ||
2613 | POSTING_READ(reg); | |
2614 | udelay(150); | |
2615 | ||
291427f5 JB |
2616 | if (HAS_PCH_CPT(dev)) |
2617 | cpt_phase_pointer_enable(dev, pipe); | |
2618 | ||
0206e353 | 2619 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2620 | reg = FDI_TX_CTL(pipe); |
2621 | temp = I915_READ(reg); | |
2622 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2623 | temp |= snb_b_fdi_train_param[i]; | |
2624 | I915_WRITE(reg, temp); | |
2625 | ||
2626 | POSTING_READ(reg); | |
2627 | udelay(500); | |
2628 | ||
2629 | reg = FDI_RX_IIR(pipe); | |
2630 | temp = I915_READ(reg); | |
2631 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2632 | ||
2633 | if (temp & FDI_RX_BIT_LOCK || | |
2634 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
2635 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2636 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2637 | break; | |
2638 | } | |
2639 | } | |
2640 | if (i == 4) | |
2641 | DRM_ERROR("FDI train 1 fail!\n"); | |
2642 | ||
2643 | /* Train 2 */ | |
2644 | reg = FDI_TX_CTL(pipe); | |
2645 | temp = I915_READ(reg); | |
2646 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; | |
2647 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
2648 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2649 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2650 | I915_WRITE(reg, temp); | |
2651 | ||
2652 | reg = FDI_RX_CTL(pipe); | |
2653 | temp = I915_READ(reg); | |
2654 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2655 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2656 | I915_WRITE(reg, temp); | |
2657 | ||
2658 | POSTING_READ(reg); | |
2659 | udelay(150); | |
2660 | ||
0206e353 | 2661 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2662 | reg = FDI_TX_CTL(pipe); |
2663 | temp = I915_READ(reg); | |
2664 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2665 | temp |= snb_b_fdi_train_param[i]; | |
2666 | I915_WRITE(reg, temp); | |
2667 | ||
2668 | POSTING_READ(reg); | |
2669 | udelay(500); | |
2670 | ||
2671 | reg = FDI_RX_IIR(pipe); | |
2672 | temp = I915_READ(reg); | |
2673 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2674 | ||
2675 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2676 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2677 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2678 | break; | |
2679 | } | |
2680 | } | |
2681 | if (i == 4) | |
2682 | DRM_ERROR("FDI train 2 fail!\n"); | |
2683 | ||
2684 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2685 | } | |
2686 | ||
2687 | static void ironlake_fdi_pll_enable(struct drm_crtc *crtc) | |
2c07245f ZW |
2688 | { |
2689 | struct drm_device *dev = crtc->dev; | |
2690 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2691 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2692 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2693 | u32 reg, temp; |
79e53945 | 2694 | |
c64e311e | 2695 | /* Write the TU size bits so error detection works */ |
5eddb70b CW |
2696 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
2697 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
c64e311e | 2698 | |
c98e9dcf | 2699 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2700 | reg = FDI_RX_CTL(pipe); |
2701 | temp = I915_READ(reg); | |
2702 | temp &= ~((0x7 << 19) | (0x7 << 16)); | |
c98e9dcf | 2703 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
5eddb70b CW |
2704 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
2705 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); | |
2706 | ||
2707 | POSTING_READ(reg); | |
c98e9dcf JB |
2708 | udelay(200); |
2709 | ||
2710 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2711 | temp = I915_READ(reg); |
2712 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2713 | ||
2714 | POSTING_READ(reg); | |
c98e9dcf JB |
2715 | udelay(200); |
2716 | ||
2717 | /* Enable CPU FDI TX PLL, always on for Ironlake */ | |
5eddb70b CW |
2718 | reg = FDI_TX_CTL(pipe); |
2719 | temp = I915_READ(reg); | |
c98e9dcf | 2720 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
5eddb70b CW |
2721 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
2722 | ||
2723 | POSTING_READ(reg); | |
c98e9dcf | 2724 | udelay(100); |
6be4a607 | 2725 | } |
0e23b99d JB |
2726 | } |
2727 | ||
291427f5 JB |
2728 | static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe) |
2729 | { | |
2730 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2731 | u32 flags = I915_READ(SOUTH_CHICKEN1); | |
2732 | ||
2733 | flags &= ~(FDI_PHASE_SYNC_EN(pipe)); | |
2734 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */ | |
2735 | flags &= ~(FDI_PHASE_SYNC_OVR(pipe)); | |
2736 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */ | |
2737 | POSTING_READ(SOUTH_CHICKEN1); | |
2738 | } | |
0fc932b8 JB |
2739 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2740 | { | |
2741 | struct drm_device *dev = crtc->dev; | |
2742 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2743 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2744 | int pipe = intel_crtc->pipe; | |
2745 | u32 reg, temp; | |
2746 | ||
2747 | /* disable CPU FDI tx and PCH FDI rx */ | |
2748 | reg = FDI_TX_CTL(pipe); | |
2749 | temp = I915_READ(reg); | |
2750 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2751 | POSTING_READ(reg); | |
2752 | ||
2753 | reg = FDI_RX_CTL(pipe); | |
2754 | temp = I915_READ(reg); | |
2755 | temp &= ~(0x7 << 16); | |
2756 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2757 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); | |
2758 | ||
2759 | POSTING_READ(reg); | |
2760 | udelay(100); | |
2761 | ||
2762 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
2763 | if (HAS_PCH_IBX(dev)) { |
2764 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
0fc932b8 JB |
2765 | I915_WRITE(FDI_RX_CHICKEN(pipe), |
2766 | I915_READ(FDI_RX_CHICKEN(pipe) & | |
6f06ce18 | 2767 | ~FDI_RX_PHASE_SYNC_POINTER_EN)); |
291427f5 JB |
2768 | } else if (HAS_PCH_CPT(dev)) { |
2769 | cpt_phase_pointer_disable(dev, pipe); | |
6f06ce18 | 2770 | } |
0fc932b8 JB |
2771 | |
2772 | /* still set train pattern 1 */ | |
2773 | reg = FDI_TX_CTL(pipe); | |
2774 | temp = I915_READ(reg); | |
2775 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2776 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2777 | I915_WRITE(reg, temp); | |
2778 | ||
2779 | reg = FDI_RX_CTL(pipe); | |
2780 | temp = I915_READ(reg); | |
2781 | if (HAS_PCH_CPT(dev)) { | |
2782 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2783 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2784 | } else { | |
2785 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2786 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2787 | } | |
2788 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
2789 | temp &= ~(0x07 << 16); | |
2790 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2791 | I915_WRITE(reg, temp); | |
2792 | ||
2793 | POSTING_READ(reg); | |
2794 | udelay(100); | |
2795 | } | |
2796 | ||
6b383a7f CW |
2797 | /* |
2798 | * When we disable a pipe, we need to clear any pending scanline wait events | |
2799 | * to avoid hanging the ring, which we assume we are waiting on. | |
2800 | */ | |
2801 | static void intel_clear_scanline_wait(struct drm_device *dev) | |
2802 | { | |
2803 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8168bd48 | 2804 | struct intel_ring_buffer *ring; |
6b383a7f CW |
2805 | u32 tmp; |
2806 | ||
2807 | if (IS_GEN2(dev)) | |
2808 | /* Can't break the hang on i8xx */ | |
2809 | return; | |
2810 | ||
1ec14ad3 | 2811 | ring = LP_RING(dev_priv); |
8168bd48 CW |
2812 | tmp = I915_READ_CTL(ring); |
2813 | if (tmp & RING_WAIT) | |
2814 | I915_WRITE_CTL(ring, tmp); | |
6b383a7f CW |
2815 | } |
2816 | ||
e6c3a2a6 CW |
2817 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2818 | { | |
05394f39 | 2819 | struct drm_i915_gem_object *obj; |
e6c3a2a6 CW |
2820 | struct drm_i915_private *dev_priv; |
2821 | ||
2822 | if (crtc->fb == NULL) | |
2823 | return; | |
2824 | ||
05394f39 | 2825 | obj = to_intel_framebuffer(crtc->fb)->obj; |
e6c3a2a6 CW |
2826 | dev_priv = crtc->dev->dev_private; |
2827 | wait_event(dev_priv->pending_flip_queue, | |
05394f39 | 2828 | atomic_read(&obj->pending_flip) == 0); |
e6c3a2a6 CW |
2829 | } |
2830 | ||
040484af JB |
2831 | static bool intel_crtc_driving_pch(struct drm_crtc *crtc) |
2832 | { | |
2833 | struct drm_device *dev = crtc->dev; | |
2834 | struct drm_mode_config *mode_config = &dev->mode_config; | |
2835 | struct intel_encoder *encoder; | |
2836 | ||
2837 | /* | |
2838 | * If there's a non-PCH eDP on this crtc, it must be DP_A, and that | |
2839 | * must be driven by its own crtc; no sharing is possible. | |
2840 | */ | |
2841 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
2842 | if (encoder->base.crtc != crtc) | |
2843 | continue; | |
2844 | ||
2845 | switch (encoder->type) { | |
2846 | case INTEL_OUTPUT_EDP: | |
2847 | if (!intel_encoder_is_pch_edp(&encoder->base)) | |
2848 | return false; | |
2849 | continue; | |
2850 | } | |
2851 | } | |
2852 | ||
2853 | return true; | |
2854 | } | |
2855 | ||
f67a559d JB |
2856 | /* |
2857 | * Enable PCH resources required for PCH ports: | |
2858 | * - PCH PLLs | |
2859 | * - FDI training & RX/TX | |
2860 | * - update transcoder timings | |
2861 | * - DP transcoding bits | |
2862 | * - transcoder | |
2863 | */ | |
2864 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
2865 | { |
2866 | struct drm_device *dev = crtc->dev; | |
2867 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2868 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2869 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2870 | u32 reg, temp; |
2c07245f | 2871 | |
c98e9dcf | 2872 | /* For PCH output, training FDI link */ |
674cf967 | 2873 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 2874 | |
92f2584a | 2875 | intel_enable_pch_pll(dev_priv, pipe); |
8db9d77b | 2876 | |
c98e9dcf JB |
2877 | if (HAS_PCH_CPT(dev)) { |
2878 | /* Be sure PCH DPLL SEL is set */ | |
2879 | temp = I915_READ(PCH_DPLL_SEL); | |
5eddb70b | 2880 | if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0) |
c98e9dcf | 2881 | temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); |
5eddb70b | 2882 | else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0) |
c98e9dcf JB |
2883 | temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
2884 | I915_WRITE(PCH_DPLL_SEL, temp); | |
c98e9dcf | 2885 | } |
5eddb70b | 2886 | |
d9b6cb56 JB |
2887 | /* set transcoder timing, panel must allow it */ |
2888 | assert_panel_unlocked(dev_priv, pipe); | |
5eddb70b CW |
2889 | I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); |
2890 | I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); | |
2891 | I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); | |
8db9d77b | 2892 | |
5eddb70b CW |
2893 | I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); |
2894 | I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); | |
2895 | I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); | |
8db9d77b | 2896 | |
5e84e1a4 ZW |
2897 | intel_fdi_normal_train(crtc); |
2898 | ||
c98e9dcf JB |
2899 | /* For PCH DP, enable TRANS_DP_CTL */ |
2900 | if (HAS_PCH_CPT(dev) && | |
2901 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
9325c9f0 | 2902 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5; |
5eddb70b CW |
2903 | reg = TRANS_DP_CTL(pipe); |
2904 | temp = I915_READ(reg); | |
2905 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
2906 | TRANS_DP_SYNC_MASK | |
2907 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
2908 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
2909 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 2910 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
2911 | |
2912 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 2913 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 2914 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 2915 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
2916 | |
2917 | switch (intel_trans_dp_port_sel(crtc)) { | |
2918 | case PCH_DP_B: | |
5eddb70b | 2919 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
2920 | break; |
2921 | case PCH_DP_C: | |
5eddb70b | 2922 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
2923 | break; |
2924 | case PCH_DP_D: | |
5eddb70b | 2925 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
2926 | break; |
2927 | default: | |
2928 | DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); | |
5eddb70b | 2929 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 2930 | break; |
32f9d658 | 2931 | } |
2c07245f | 2932 | |
5eddb70b | 2933 | I915_WRITE(reg, temp); |
6be4a607 | 2934 | } |
b52eb4dc | 2935 | |
040484af | 2936 | intel_enable_transcoder(dev_priv, pipe); |
f67a559d JB |
2937 | } |
2938 | ||
2939 | static void ironlake_crtc_enable(struct drm_crtc *crtc) | |
2940 | { | |
2941 | struct drm_device *dev = crtc->dev; | |
2942 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2943 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2944 | int pipe = intel_crtc->pipe; | |
2945 | int plane = intel_crtc->plane; | |
2946 | u32 temp; | |
2947 | bool is_pch_port; | |
2948 | ||
2949 | if (intel_crtc->active) | |
2950 | return; | |
2951 | ||
2952 | intel_crtc->active = true; | |
2953 | intel_update_watermarks(dev); | |
2954 | ||
2955 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
2956 | temp = I915_READ(PCH_LVDS); | |
2957 | if ((temp & LVDS_PORT_EN) == 0) | |
2958 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); | |
2959 | } | |
2960 | ||
2961 | is_pch_port = intel_crtc_driving_pch(crtc); | |
2962 | ||
2963 | if (is_pch_port) | |
357555c0 | 2964 | ironlake_fdi_pll_enable(crtc); |
f67a559d JB |
2965 | else |
2966 | ironlake_fdi_disable(crtc); | |
2967 | ||
2968 | /* Enable panel fitting for LVDS */ | |
2969 | if (dev_priv->pch_pf_size && | |
2970 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) { | |
2971 | /* Force use of hard-coded filter coefficients | |
2972 | * as some pre-programmed values are broken, | |
2973 | * e.g. x201. | |
2974 | */ | |
9db4a9c7 JB |
2975 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
2976 | I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); | |
2977 | I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); | |
f67a559d JB |
2978 | } |
2979 | ||
9c54c0dd JB |
2980 | /* |
2981 | * On ILK+ LUT must be loaded before the pipe is running but with | |
2982 | * clocks enabled | |
2983 | */ | |
2984 | intel_crtc_load_lut(crtc); | |
2985 | ||
f67a559d JB |
2986 | intel_enable_pipe(dev_priv, pipe, is_pch_port); |
2987 | intel_enable_plane(dev_priv, plane, pipe); | |
2988 | ||
2989 | if (is_pch_port) | |
2990 | ironlake_pch_enable(crtc); | |
c98e9dcf | 2991 | |
d1ebd816 | 2992 | mutex_lock(&dev->struct_mutex); |
bed4a673 | 2993 | intel_update_fbc(dev); |
d1ebd816 BW |
2994 | mutex_unlock(&dev->struct_mutex); |
2995 | ||
6b383a7f | 2996 | intel_crtc_update_cursor(crtc, true); |
6be4a607 JB |
2997 | } |
2998 | ||
2999 | static void ironlake_crtc_disable(struct drm_crtc *crtc) | |
3000 | { | |
3001 | struct drm_device *dev = crtc->dev; | |
3002 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3003 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3004 | int pipe = intel_crtc->pipe; | |
3005 | int plane = intel_crtc->plane; | |
5eddb70b | 3006 | u32 reg, temp; |
b52eb4dc | 3007 | |
f7abfe8b CW |
3008 | if (!intel_crtc->active) |
3009 | return; | |
3010 | ||
e6c3a2a6 | 3011 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 3012 | drm_vblank_off(dev, pipe); |
6b383a7f | 3013 | intel_crtc_update_cursor(crtc, false); |
5eddb70b | 3014 | |
b24e7179 | 3015 | intel_disable_plane(dev_priv, plane, pipe); |
913d8d11 | 3016 | |
973d04f9 CW |
3017 | if (dev_priv->cfb_plane == plane) |
3018 | intel_disable_fbc(dev); | |
2c07245f | 3019 | |
b24e7179 | 3020 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 3021 | |
6be4a607 | 3022 | /* Disable PF */ |
9db4a9c7 JB |
3023 | I915_WRITE(PF_CTL(pipe), 0); |
3024 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
2c07245f | 3025 | |
0fc932b8 | 3026 | ironlake_fdi_disable(crtc); |
2c07245f | 3027 | |
47a05eca JB |
3028 | /* This is a horrible layering violation; we should be doing this in |
3029 | * the connector/encoder ->prepare instead, but we don't always have | |
3030 | * enough information there about the config to know whether it will | |
3031 | * actually be necessary or just cause undesired flicker. | |
3032 | */ | |
3033 | intel_disable_pch_ports(dev_priv, pipe); | |
249c0e64 | 3034 | |
040484af | 3035 | intel_disable_transcoder(dev_priv, pipe); |
913d8d11 | 3036 | |
6be4a607 JB |
3037 | if (HAS_PCH_CPT(dev)) { |
3038 | /* disable TRANS_DP_CTL */ | |
5eddb70b CW |
3039 | reg = TRANS_DP_CTL(pipe); |
3040 | temp = I915_READ(reg); | |
3041 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); | |
cb3543c6 | 3042 | temp |= TRANS_DP_PORT_SEL_NONE; |
5eddb70b | 3043 | I915_WRITE(reg, temp); |
6be4a607 JB |
3044 | |
3045 | /* disable DPLL_SEL */ | |
3046 | temp = I915_READ(PCH_DPLL_SEL); | |
9db4a9c7 JB |
3047 | switch (pipe) { |
3048 | case 0: | |
3049 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); | |
3050 | break; | |
3051 | case 1: | |
6be4a607 | 3052 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
9db4a9c7 JB |
3053 | break; |
3054 | case 2: | |
3055 | /* FIXME: manage transcoder PLLs? */ | |
3056 | temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); | |
3057 | break; | |
3058 | default: | |
3059 | BUG(); /* wtf */ | |
3060 | } | |
6be4a607 | 3061 | I915_WRITE(PCH_DPLL_SEL, temp); |
6be4a607 | 3062 | } |
e3421a18 | 3063 | |
6be4a607 | 3064 | /* disable PCH DPLL */ |
92f2584a | 3065 | intel_disable_pch_pll(dev_priv, pipe); |
8db9d77b | 3066 | |
6be4a607 | 3067 | /* Switch from PCDclk to Rawclk */ |
5eddb70b CW |
3068 | reg = FDI_RX_CTL(pipe); |
3069 | temp = I915_READ(reg); | |
3070 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
8db9d77b | 3071 | |
6be4a607 | 3072 | /* Disable CPU FDI TX PLL */ |
5eddb70b CW |
3073 | reg = FDI_TX_CTL(pipe); |
3074 | temp = I915_READ(reg); | |
3075 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3076 | ||
3077 | POSTING_READ(reg); | |
6be4a607 | 3078 | udelay(100); |
8db9d77b | 3079 | |
5eddb70b CW |
3080 | reg = FDI_RX_CTL(pipe); |
3081 | temp = I915_READ(reg); | |
3082 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2c07245f | 3083 | |
6be4a607 | 3084 | /* Wait for the clocks to turn off. */ |
5eddb70b | 3085 | POSTING_READ(reg); |
6be4a607 | 3086 | udelay(100); |
6b383a7f | 3087 | |
f7abfe8b | 3088 | intel_crtc->active = false; |
6b383a7f | 3089 | intel_update_watermarks(dev); |
d1ebd816 BW |
3090 | |
3091 | mutex_lock(&dev->struct_mutex); | |
6b383a7f CW |
3092 | intel_update_fbc(dev); |
3093 | intel_clear_scanline_wait(dev); | |
d1ebd816 | 3094 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 3095 | } |
1b3c7a47 | 3096 | |
6be4a607 JB |
3097 | static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) |
3098 | { | |
3099 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3100 | int pipe = intel_crtc->pipe; | |
3101 | int plane = intel_crtc->plane; | |
8db9d77b | 3102 | |
6be4a607 JB |
3103 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
3104 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
3105 | */ | |
3106 | switch (mode) { | |
3107 | case DRM_MODE_DPMS_ON: | |
3108 | case DRM_MODE_DPMS_STANDBY: | |
3109 | case DRM_MODE_DPMS_SUSPEND: | |
3110 | DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane); | |
3111 | ironlake_crtc_enable(crtc); | |
3112 | break; | |
1b3c7a47 | 3113 | |
6be4a607 JB |
3114 | case DRM_MODE_DPMS_OFF: |
3115 | DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane); | |
3116 | ironlake_crtc_disable(crtc); | |
2c07245f ZW |
3117 | break; |
3118 | } | |
3119 | } | |
3120 | ||
02e792fb DV |
3121 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3122 | { | |
02e792fb | 3123 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 3124 | struct drm_device *dev = intel_crtc->base.dev; |
ce453d81 | 3125 | struct drm_i915_private *dev_priv = dev->dev_private; |
03f77ea5 | 3126 | |
23f09ce3 | 3127 | mutex_lock(&dev->struct_mutex); |
ce453d81 CW |
3128 | dev_priv->mm.interruptible = false; |
3129 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3130 | dev_priv->mm.interruptible = true; | |
23f09ce3 | 3131 | mutex_unlock(&dev->struct_mutex); |
02e792fb | 3132 | } |
02e792fb | 3133 | |
5dcdbcb0 CW |
3134 | /* Let userspace switch the overlay on again. In most cases userspace |
3135 | * has to recompute where to put it anyway. | |
3136 | */ | |
02e792fb DV |
3137 | } |
3138 | ||
0b8765c6 | 3139 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
3140 | { |
3141 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
3142 | struct drm_i915_private *dev_priv = dev->dev_private; |
3143 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3144 | int pipe = intel_crtc->pipe; | |
80824003 | 3145 | int plane = intel_crtc->plane; |
79e53945 | 3146 | |
f7abfe8b CW |
3147 | if (intel_crtc->active) |
3148 | return; | |
3149 | ||
3150 | intel_crtc->active = true; | |
6b383a7f CW |
3151 | intel_update_watermarks(dev); |
3152 | ||
63d7bbe9 | 3153 | intel_enable_pll(dev_priv, pipe); |
040484af | 3154 | intel_enable_pipe(dev_priv, pipe, false); |
b24e7179 | 3155 | intel_enable_plane(dev_priv, plane, pipe); |
79e53945 | 3156 | |
0b8765c6 | 3157 | intel_crtc_load_lut(crtc); |
bed4a673 | 3158 | intel_update_fbc(dev); |
79e53945 | 3159 | |
0b8765c6 JB |
3160 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
3161 | intel_crtc_dpms_overlay(intel_crtc, true); | |
6b383a7f | 3162 | intel_crtc_update_cursor(crtc, true); |
0b8765c6 | 3163 | } |
79e53945 | 3164 | |
0b8765c6 JB |
3165 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
3166 | { | |
3167 | struct drm_device *dev = crtc->dev; | |
3168 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3169 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3170 | int pipe = intel_crtc->pipe; | |
3171 | int plane = intel_crtc->plane; | |
b690e96c | 3172 | |
f7abfe8b CW |
3173 | if (!intel_crtc->active) |
3174 | return; | |
3175 | ||
0b8765c6 | 3176 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
3177 | intel_crtc_wait_for_pending_flips(crtc); |
3178 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 3179 | intel_crtc_dpms_overlay(intel_crtc, false); |
6b383a7f | 3180 | intel_crtc_update_cursor(crtc, false); |
0b8765c6 | 3181 | |
973d04f9 CW |
3182 | if (dev_priv->cfb_plane == plane) |
3183 | intel_disable_fbc(dev); | |
79e53945 | 3184 | |
b24e7179 | 3185 | intel_disable_plane(dev_priv, plane, pipe); |
b24e7179 | 3186 | intel_disable_pipe(dev_priv, pipe); |
63d7bbe9 | 3187 | intel_disable_pll(dev_priv, pipe); |
0b8765c6 | 3188 | |
f7abfe8b | 3189 | intel_crtc->active = false; |
6b383a7f CW |
3190 | intel_update_fbc(dev); |
3191 | intel_update_watermarks(dev); | |
3192 | intel_clear_scanline_wait(dev); | |
0b8765c6 JB |
3193 | } |
3194 | ||
3195 | static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) | |
3196 | { | |
3197 | /* XXX: When our outputs are all unaware of DPMS modes other than off | |
3198 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
3199 | */ | |
3200 | switch (mode) { | |
3201 | case DRM_MODE_DPMS_ON: | |
3202 | case DRM_MODE_DPMS_STANDBY: | |
3203 | case DRM_MODE_DPMS_SUSPEND: | |
3204 | i9xx_crtc_enable(crtc); | |
3205 | break; | |
3206 | case DRM_MODE_DPMS_OFF: | |
3207 | i9xx_crtc_disable(crtc); | |
79e53945 JB |
3208 | break; |
3209 | } | |
2c07245f ZW |
3210 | } |
3211 | ||
3212 | /** | |
3213 | * Sets the power management mode of the pipe and plane. | |
2c07245f ZW |
3214 | */ |
3215 | static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) | |
3216 | { | |
3217 | struct drm_device *dev = crtc->dev; | |
e70236a8 | 3218 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f ZW |
3219 | struct drm_i915_master_private *master_priv; |
3220 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3221 | int pipe = intel_crtc->pipe; | |
3222 | bool enabled; | |
3223 | ||
032d2a0d CW |
3224 | if (intel_crtc->dpms_mode == mode) |
3225 | return; | |
3226 | ||
65655d4a | 3227 | intel_crtc->dpms_mode = mode; |
debcaddc | 3228 | |
e70236a8 | 3229 | dev_priv->display.dpms(crtc, mode); |
79e53945 JB |
3230 | |
3231 | if (!dev->primary->master) | |
3232 | return; | |
3233 | ||
3234 | master_priv = dev->primary->master->driver_priv; | |
3235 | if (!master_priv->sarea_priv) | |
3236 | return; | |
3237 | ||
3238 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; | |
3239 | ||
3240 | switch (pipe) { | |
3241 | case 0: | |
3242 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
3243 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
3244 | break; | |
3245 | case 1: | |
3246 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
3247 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
3248 | break; | |
3249 | default: | |
9db4a9c7 | 3250 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
3251 | break; |
3252 | } | |
79e53945 JB |
3253 | } |
3254 | ||
cdd59983 CW |
3255 | static void intel_crtc_disable(struct drm_crtc *crtc) |
3256 | { | |
3257 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
3258 | struct drm_device *dev = crtc->dev; | |
3259 | ||
3260 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | |
3261 | ||
3262 | if (crtc->fb) { | |
3263 | mutex_lock(&dev->struct_mutex); | |
3264 | i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj); | |
3265 | mutex_unlock(&dev->struct_mutex); | |
3266 | } | |
3267 | } | |
3268 | ||
7e7d76c3 JB |
3269 | /* Prepare for a mode set. |
3270 | * | |
3271 | * Note we could be a lot smarter here. We need to figure out which outputs | |
3272 | * will be enabled, which disabled (in short, how the config will changes) | |
3273 | * and perform the minimum necessary steps to accomplish that, e.g. updating | |
3274 | * watermarks, FBC configuration, making sure PLLs are programmed correctly, | |
3275 | * panel fitting is in the proper state, etc. | |
3276 | */ | |
3277 | static void i9xx_crtc_prepare(struct drm_crtc *crtc) | |
79e53945 | 3278 | { |
7e7d76c3 | 3279 | i9xx_crtc_disable(crtc); |
79e53945 JB |
3280 | } |
3281 | ||
7e7d76c3 | 3282 | static void i9xx_crtc_commit(struct drm_crtc *crtc) |
79e53945 | 3283 | { |
7e7d76c3 | 3284 | i9xx_crtc_enable(crtc); |
7e7d76c3 JB |
3285 | } |
3286 | ||
3287 | static void ironlake_crtc_prepare(struct drm_crtc *crtc) | |
3288 | { | |
7e7d76c3 | 3289 | ironlake_crtc_disable(crtc); |
7e7d76c3 JB |
3290 | } |
3291 | ||
3292 | static void ironlake_crtc_commit(struct drm_crtc *crtc) | |
3293 | { | |
7e7d76c3 | 3294 | ironlake_crtc_enable(crtc); |
79e53945 JB |
3295 | } |
3296 | ||
0206e353 | 3297 | void intel_encoder_prepare(struct drm_encoder *encoder) |
79e53945 JB |
3298 | { |
3299 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
3300 | /* lvds has its own version of prepare see intel_lvds_prepare */ | |
3301 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); | |
3302 | } | |
3303 | ||
0206e353 | 3304 | void intel_encoder_commit(struct drm_encoder *encoder) |
79e53945 JB |
3305 | { |
3306 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
3307 | /* lvds has its own version of commit see intel_lvds_commit */ | |
3308 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
3309 | } | |
3310 | ||
ea5b213a CW |
3311 | void intel_encoder_destroy(struct drm_encoder *encoder) |
3312 | { | |
4ef69c7a | 3313 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 3314 | |
ea5b213a CW |
3315 | drm_encoder_cleanup(encoder); |
3316 | kfree(intel_encoder); | |
3317 | } | |
3318 | ||
79e53945 JB |
3319 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
3320 | struct drm_display_mode *mode, | |
3321 | struct drm_display_mode *adjusted_mode) | |
3322 | { | |
2c07245f | 3323 | struct drm_device *dev = crtc->dev; |
89749350 | 3324 | |
bad720ff | 3325 | if (HAS_PCH_SPLIT(dev)) { |
2c07245f | 3326 | /* FDI link clock is fixed at 2.7G */ |
2377b741 JB |
3327 | if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) |
3328 | return false; | |
2c07245f | 3329 | } |
89749350 CW |
3330 | |
3331 | /* XXX some encoders set the crtcinfo, others don't. | |
3332 | * Obviously we need some form of conflict resolution here... | |
3333 | */ | |
3334 | if (adjusted_mode->crtc_htotal == 0) | |
3335 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
3336 | ||
79e53945 JB |
3337 | return true; |
3338 | } | |
3339 | ||
e70236a8 JB |
3340 | static int i945_get_display_clock_speed(struct drm_device *dev) |
3341 | { | |
3342 | return 400000; | |
3343 | } | |
79e53945 | 3344 | |
e70236a8 | 3345 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 3346 | { |
e70236a8 JB |
3347 | return 333000; |
3348 | } | |
79e53945 | 3349 | |
e70236a8 JB |
3350 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
3351 | { | |
3352 | return 200000; | |
3353 | } | |
79e53945 | 3354 | |
e70236a8 JB |
3355 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
3356 | { | |
3357 | u16 gcfgc = 0; | |
79e53945 | 3358 | |
e70236a8 JB |
3359 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
3360 | ||
3361 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
3362 | return 133000; | |
3363 | else { | |
3364 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
3365 | case GC_DISPLAY_CLOCK_333_MHZ: | |
3366 | return 333000; | |
3367 | default: | |
3368 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
3369 | return 190000; | |
79e53945 | 3370 | } |
e70236a8 JB |
3371 | } |
3372 | } | |
3373 | ||
3374 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
3375 | { | |
3376 | return 266000; | |
3377 | } | |
3378 | ||
3379 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
3380 | { | |
3381 | u16 hpllcc = 0; | |
3382 | /* Assume that the hardware is in the high speed state. This | |
3383 | * should be the default. | |
3384 | */ | |
3385 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
3386 | case GC_CLOCK_133_200: | |
3387 | case GC_CLOCK_100_200: | |
3388 | return 200000; | |
3389 | case GC_CLOCK_166_250: | |
3390 | return 250000; | |
3391 | case GC_CLOCK_100_133: | |
79e53945 | 3392 | return 133000; |
e70236a8 | 3393 | } |
79e53945 | 3394 | |
e70236a8 JB |
3395 | /* Shouldn't happen */ |
3396 | return 0; | |
3397 | } | |
79e53945 | 3398 | |
e70236a8 JB |
3399 | static int i830_get_display_clock_speed(struct drm_device *dev) |
3400 | { | |
3401 | return 133000; | |
79e53945 JB |
3402 | } |
3403 | ||
2c07245f ZW |
3404 | struct fdi_m_n { |
3405 | u32 tu; | |
3406 | u32 gmch_m; | |
3407 | u32 gmch_n; | |
3408 | u32 link_m; | |
3409 | u32 link_n; | |
3410 | }; | |
3411 | ||
3412 | static void | |
3413 | fdi_reduce_ratio(u32 *num, u32 *den) | |
3414 | { | |
3415 | while (*num > 0xffffff || *den > 0xffffff) { | |
3416 | *num >>= 1; | |
3417 | *den >>= 1; | |
3418 | } | |
3419 | } | |
3420 | ||
2c07245f | 3421 | static void |
f2b115e6 AJ |
3422 | ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, |
3423 | int link_clock, struct fdi_m_n *m_n) | |
2c07245f | 3424 | { |
2c07245f ZW |
3425 | m_n->tu = 64; /* default size */ |
3426 | ||
22ed1113 CW |
3427 | /* BUG_ON(pixel_clock > INT_MAX / 36); */ |
3428 | m_n->gmch_m = bits_per_pixel * pixel_clock; | |
3429 | m_n->gmch_n = link_clock * nlanes * 8; | |
2c07245f ZW |
3430 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
3431 | ||
22ed1113 CW |
3432 | m_n->link_m = pixel_clock; |
3433 | m_n->link_n = link_clock; | |
2c07245f ZW |
3434 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); |
3435 | } | |
3436 | ||
3437 | ||
7662c8bd SL |
3438 | struct intel_watermark_params { |
3439 | unsigned long fifo_size; | |
3440 | unsigned long max_wm; | |
3441 | unsigned long default_wm; | |
3442 | unsigned long guard_size; | |
3443 | unsigned long cacheline_size; | |
3444 | }; | |
3445 | ||
f2b115e6 | 3446 | /* Pineview has different values for various configs */ |
d210246a | 3447 | static const struct intel_watermark_params pineview_display_wm = { |
f2b115e6 AJ |
3448 | PINEVIEW_DISPLAY_FIFO, |
3449 | PINEVIEW_MAX_WM, | |
3450 | PINEVIEW_DFT_WM, | |
3451 | PINEVIEW_GUARD_WM, | |
3452 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 3453 | }; |
d210246a | 3454 | static const struct intel_watermark_params pineview_display_hplloff_wm = { |
f2b115e6 AJ |
3455 | PINEVIEW_DISPLAY_FIFO, |
3456 | PINEVIEW_MAX_WM, | |
3457 | PINEVIEW_DFT_HPLLOFF_WM, | |
3458 | PINEVIEW_GUARD_WM, | |
3459 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 3460 | }; |
d210246a | 3461 | static const struct intel_watermark_params pineview_cursor_wm = { |
f2b115e6 AJ |
3462 | PINEVIEW_CURSOR_FIFO, |
3463 | PINEVIEW_CURSOR_MAX_WM, | |
3464 | PINEVIEW_CURSOR_DFT_WM, | |
3465 | PINEVIEW_CURSOR_GUARD_WM, | |
3466 | PINEVIEW_FIFO_LINE_SIZE, | |
7662c8bd | 3467 | }; |
d210246a | 3468 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { |
f2b115e6 AJ |
3469 | PINEVIEW_CURSOR_FIFO, |
3470 | PINEVIEW_CURSOR_MAX_WM, | |
3471 | PINEVIEW_CURSOR_DFT_WM, | |
3472 | PINEVIEW_CURSOR_GUARD_WM, | |
3473 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 3474 | }; |
d210246a | 3475 | static const struct intel_watermark_params g4x_wm_info = { |
0e442c60 JB |
3476 | G4X_FIFO_SIZE, |
3477 | G4X_MAX_WM, | |
3478 | G4X_MAX_WM, | |
3479 | 2, | |
3480 | G4X_FIFO_LINE_SIZE, | |
3481 | }; | |
d210246a | 3482 | static const struct intel_watermark_params g4x_cursor_wm_info = { |
4fe5e611 ZY |
3483 | I965_CURSOR_FIFO, |
3484 | I965_CURSOR_MAX_WM, | |
3485 | I965_CURSOR_DFT_WM, | |
3486 | 2, | |
3487 | G4X_FIFO_LINE_SIZE, | |
3488 | }; | |
d210246a | 3489 | static const struct intel_watermark_params i965_cursor_wm_info = { |
4fe5e611 ZY |
3490 | I965_CURSOR_FIFO, |
3491 | I965_CURSOR_MAX_WM, | |
3492 | I965_CURSOR_DFT_WM, | |
3493 | 2, | |
3494 | I915_FIFO_LINE_SIZE, | |
3495 | }; | |
d210246a | 3496 | static const struct intel_watermark_params i945_wm_info = { |
dff33cfc | 3497 | I945_FIFO_SIZE, |
7662c8bd SL |
3498 | I915_MAX_WM, |
3499 | 1, | |
dff33cfc JB |
3500 | 2, |
3501 | I915_FIFO_LINE_SIZE | |
7662c8bd | 3502 | }; |
d210246a | 3503 | static const struct intel_watermark_params i915_wm_info = { |
dff33cfc | 3504 | I915_FIFO_SIZE, |
7662c8bd SL |
3505 | I915_MAX_WM, |
3506 | 1, | |
dff33cfc | 3507 | 2, |
7662c8bd SL |
3508 | I915_FIFO_LINE_SIZE |
3509 | }; | |
d210246a | 3510 | static const struct intel_watermark_params i855_wm_info = { |
7662c8bd SL |
3511 | I855GM_FIFO_SIZE, |
3512 | I915_MAX_WM, | |
3513 | 1, | |
dff33cfc | 3514 | 2, |
7662c8bd SL |
3515 | I830_FIFO_LINE_SIZE |
3516 | }; | |
d210246a | 3517 | static const struct intel_watermark_params i830_wm_info = { |
7662c8bd SL |
3518 | I830_FIFO_SIZE, |
3519 | I915_MAX_WM, | |
3520 | 1, | |
dff33cfc | 3521 | 2, |
7662c8bd SL |
3522 | I830_FIFO_LINE_SIZE |
3523 | }; | |
3524 | ||
d210246a | 3525 | static const struct intel_watermark_params ironlake_display_wm_info = { |
7f8a8569 ZW |
3526 | ILK_DISPLAY_FIFO, |
3527 | ILK_DISPLAY_MAXWM, | |
3528 | ILK_DISPLAY_DFTWM, | |
3529 | 2, | |
3530 | ILK_FIFO_LINE_SIZE | |
3531 | }; | |
d210246a | 3532 | static const struct intel_watermark_params ironlake_cursor_wm_info = { |
c936f44d ZY |
3533 | ILK_CURSOR_FIFO, |
3534 | ILK_CURSOR_MAXWM, | |
3535 | ILK_CURSOR_DFTWM, | |
3536 | 2, | |
3537 | ILK_FIFO_LINE_SIZE | |
3538 | }; | |
d210246a | 3539 | static const struct intel_watermark_params ironlake_display_srwm_info = { |
7f8a8569 ZW |
3540 | ILK_DISPLAY_SR_FIFO, |
3541 | ILK_DISPLAY_MAX_SRWM, | |
3542 | ILK_DISPLAY_DFT_SRWM, | |
3543 | 2, | |
3544 | ILK_FIFO_LINE_SIZE | |
3545 | }; | |
d210246a | 3546 | static const struct intel_watermark_params ironlake_cursor_srwm_info = { |
7f8a8569 ZW |
3547 | ILK_CURSOR_SR_FIFO, |
3548 | ILK_CURSOR_MAX_SRWM, | |
3549 | ILK_CURSOR_DFT_SRWM, | |
3550 | 2, | |
3551 | ILK_FIFO_LINE_SIZE | |
3552 | }; | |
3553 | ||
d210246a | 3554 | static const struct intel_watermark_params sandybridge_display_wm_info = { |
1398261a YL |
3555 | SNB_DISPLAY_FIFO, |
3556 | SNB_DISPLAY_MAXWM, | |
3557 | SNB_DISPLAY_DFTWM, | |
3558 | 2, | |
3559 | SNB_FIFO_LINE_SIZE | |
3560 | }; | |
d210246a | 3561 | static const struct intel_watermark_params sandybridge_cursor_wm_info = { |
1398261a YL |
3562 | SNB_CURSOR_FIFO, |
3563 | SNB_CURSOR_MAXWM, | |
3564 | SNB_CURSOR_DFTWM, | |
3565 | 2, | |
3566 | SNB_FIFO_LINE_SIZE | |
3567 | }; | |
d210246a | 3568 | static const struct intel_watermark_params sandybridge_display_srwm_info = { |
1398261a YL |
3569 | SNB_DISPLAY_SR_FIFO, |
3570 | SNB_DISPLAY_MAX_SRWM, | |
3571 | SNB_DISPLAY_DFT_SRWM, | |
3572 | 2, | |
3573 | SNB_FIFO_LINE_SIZE | |
3574 | }; | |
d210246a | 3575 | static const struct intel_watermark_params sandybridge_cursor_srwm_info = { |
1398261a YL |
3576 | SNB_CURSOR_SR_FIFO, |
3577 | SNB_CURSOR_MAX_SRWM, | |
3578 | SNB_CURSOR_DFT_SRWM, | |
3579 | 2, | |
3580 | SNB_FIFO_LINE_SIZE | |
3581 | }; | |
3582 | ||
3583 | ||
dff33cfc JB |
3584 | /** |
3585 | * intel_calculate_wm - calculate watermark level | |
3586 | * @clock_in_khz: pixel clock | |
3587 | * @wm: chip FIFO params | |
3588 | * @pixel_size: display pixel size | |
3589 | * @latency_ns: memory latency for the platform | |
3590 | * | |
3591 | * Calculate the watermark level (the level at which the display plane will | |
3592 | * start fetching from memory again). Each chip has a different display | |
3593 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
3594 | * in the correct intel_watermark_params structure. | |
3595 | * | |
3596 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
3597 | * on the pixel size. When it reaches the watermark level, it'll start | |
3598 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
3599 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
3600 | * will occur, and a display engine hang could result. | |
3601 | */ | |
7662c8bd | 3602 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
d210246a CW |
3603 | const struct intel_watermark_params *wm, |
3604 | int fifo_size, | |
7662c8bd SL |
3605 | int pixel_size, |
3606 | unsigned long latency_ns) | |
3607 | { | |
390c4dd4 | 3608 | long entries_required, wm_size; |
dff33cfc | 3609 | |
d660467c JB |
3610 | /* |
3611 | * Note: we need to make sure we don't overflow for various clock & | |
3612 | * latency values. | |
3613 | * clocks go from a few thousand to several hundred thousand. | |
3614 | * latency is usually a few thousand | |
3615 | */ | |
3616 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / | |
3617 | 1000; | |
8de9b311 | 3618 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
7662c8bd | 3619 | |
bbb0aef5 | 3620 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); |
dff33cfc | 3621 | |
d210246a | 3622 | wm_size = fifo_size - (entries_required + wm->guard_size); |
dff33cfc | 3623 | |
bbb0aef5 | 3624 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); |
7662c8bd | 3625 | |
390c4dd4 JB |
3626 | /* Don't promote wm_size to unsigned... */ |
3627 | if (wm_size > (long)wm->max_wm) | |
7662c8bd | 3628 | wm_size = wm->max_wm; |
c3add4b6 | 3629 | if (wm_size <= 0) |
7662c8bd SL |
3630 | wm_size = wm->default_wm; |
3631 | return wm_size; | |
3632 | } | |
3633 | ||
3634 | struct cxsr_latency { | |
3635 | int is_desktop; | |
95534263 | 3636 | int is_ddr3; |
7662c8bd SL |
3637 | unsigned long fsb_freq; |
3638 | unsigned long mem_freq; | |
3639 | unsigned long display_sr; | |
3640 | unsigned long display_hpll_disable; | |
3641 | unsigned long cursor_sr; | |
3642 | unsigned long cursor_hpll_disable; | |
3643 | }; | |
3644 | ||
403c89ff | 3645 | static const struct cxsr_latency cxsr_latency_table[] = { |
95534263 LP |
3646 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
3647 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
3648 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
3649 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
3650 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
3651 | ||
3652 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
3653 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
3654 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
3655 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
3656 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
3657 | ||
3658 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
3659 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
3660 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
3661 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
3662 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
3663 | ||
3664 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
3665 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
3666 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
3667 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
3668 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
3669 | ||
3670 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
3671 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
3672 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
3673 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
3674 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
3675 | ||
3676 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
3677 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
3678 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
3679 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
3680 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
7662c8bd SL |
3681 | }; |
3682 | ||
403c89ff CW |
3683 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
3684 | int is_ddr3, | |
3685 | int fsb, | |
3686 | int mem) | |
7662c8bd | 3687 | { |
403c89ff | 3688 | const struct cxsr_latency *latency; |
7662c8bd | 3689 | int i; |
7662c8bd SL |
3690 | |
3691 | if (fsb == 0 || mem == 0) | |
3692 | return NULL; | |
3693 | ||
3694 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
3695 | latency = &cxsr_latency_table[i]; | |
3696 | if (is_desktop == latency->is_desktop && | |
95534263 | 3697 | is_ddr3 == latency->is_ddr3 && |
decbbcda JSR |
3698 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
3699 | return latency; | |
7662c8bd | 3700 | } |
decbbcda | 3701 | |
28c97730 | 3702 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
decbbcda JSR |
3703 | |
3704 | return NULL; | |
7662c8bd SL |
3705 | } |
3706 | ||
f2b115e6 | 3707 | static void pineview_disable_cxsr(struct drm_device *dev) |
7662c8bd SL |
3708 | { |
3709 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7662c8bd SL |
3710 | |
3711 | /* deactivate cxsr */ | |
3e33d94d | 3712 | I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); |
7662c8bd SL |
3713 | } |
3714 | ||
bcc24fb4 JB |
3715 | /* |
3716 | * Latency for FIFO fetches is dependent on several factors: | |
3717 | * - memory configuration (speed, channels) | |
3718 | * - chipset | |
3719 | * - current MCH state | |
3720 | * It can be fairly high in some situations, so here we assume a fairly | |
3721 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
3722 | * set this value too high, the FIFO will fetch frequently to stay full) | |
3723 | * and power consumption (set it too low to save power and we might see | |
3724 | * FIFO underruns and display "flicker"). | |
3725 | * | |
3726 | * A value of 5us seems to be a good balance; safe for very low end | |
3727 | * platforms but not overly aggressive on lower latency configs. | |
3728 | */ | |
69e302a9 | 3729 | static const int latency_ns = 5000; |
7662c8bd | 3730 | |
e70236a8 | 3731 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
dff33cfc JB |
3732 | { |
3733 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3734 | uint32_t dsparb = I915_READ(DSPARB); | |
3735 | int size; | |
3736 | ||
8de9b311 CW |
3737 | size = dsparb & 0x7f; |
3738 | if (plane) | |
3739 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
dff33cfc | 3740 | |
28c97730 | 3741 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3742 | plane ? "B" : "A", size); |
dff33cfc JB |
3743 | |
3744 | return size; | |
3745 | } | |
7662c8bd | 3746 | |
e70236a8 JB |
3747 | static int i85x_get_fifo_size(struct drm_device *dev, int plane) |
3748 | { | |
3749 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3750 | uint32_t dsparb = I915_READ(DSPARB); | |
3751 | int size; | |
3752 | ||
8de9b311 CW |
3753 | size = dsparb & 0x1ff; |
3754 | if (plane) | |
3755 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
e70236a8 | 3756 | size >>= 1; /* Convert to cachelines */ |
dff33cfc | 3757 | |
28c97730 | 3758 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3759 | plane ? "B" : "A", size); |
dff33cfc JB |
3760 | |
3761 | return size; | |
3762 | } | |
7662c8bd | 3763 | |
e70236a8 JB |
3764 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
3765 | { | |
3766 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3767 | uint32_t dsparb = I915_READ(DSPARB); | |
3768 | int size; | |
3769 | ||
3770 | size = dsparb & 0x7f; | |
3771 | size >>= 2; /* Convert to cachelines */ | |
3772 | ||
28c97730 | 3773 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b CW |
3774 | plane ? "B" : "A", |
3775 | size); | |
e70236a8 JB |
3776 | |
3777 | return size; | |
3778 | } | |
3779 | ||
3780 | static int i830_get_fifo_size(struct drm_device *dev, int plane) | |
3781 | { | |
3782 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3783 | uint32_t dsparb = I915_READ(DSPARB); | |
3784 | int size; | |
3785 | ||
3786 | size = dsparb & 0x7f; | |
3787 | size >>= 1; /* Convert to cachelines */ | |
3788 | ||
28c97730 | 3789 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3790 | plane ? "B" : "A", size); |
e70236a8 JB |
3791 | |
3792 | return size; | |
3793 | } | |
3794 | ||
d210246a CW |
3795 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) |
3796 | { | |
3797 | struct drm_crtc *crtc, *enabled = NULL; | |
3798 | ||
3799 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
3800 | if (crtc->enabled && crtc->fb) { | |
3801 | if (enabled) | |
3802 | return NULL; | |
3803 | enabled = crtc; | |
3804 | } | |
3805 | } | |
3806 | ||
3807 | return enabled; | |
3808 | } | |
3809 | ||
3810 | static void pineview_update_wm(struct drm_device *dev) | |
d4294342 ZY |
3811 | { |
3812 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a | 3813 | struct drm_crtc *crtc; |
403c89ff | 3814 | const struct cxsr_latency *latency; |
d4294342 ZY |
3815 | u32 reg; |
3816 | unsigned long wm; | |
d4294342 | 3817 | |
403c89ff | 3818 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
95534263 | 3819 | dev_priv->fsb_freq, dev_priv->mem_freq); |
d4294342 ZY |
3820 | if (!latency) { |
3821 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
3822 | pineview_disable_cxsr(dev); | |
3823 | return; | |
3824 | } | |
3825 | ||
d210246a CW |
3826 | crtc = single_enabled_crtc(dev); |
3827 | if (crtc) { | |
3828 | int clock = crtc->mode.clock; | |
3829 | int pixel_size = crtc->fb->bits_per_pixel / 8; | |
d4294342 ZY |
3830 | |
3831 | /* Display SR */ | |
d210246a CW |
3832 | wm = intel_calculate_wm(clock, &pineview_display_wm, |
3833 | pineview_display_wm.fifo_size, | |
d4294342 ZY |
3834 | pixel_size, latency->display_sr); |
3835 | reg = I915_READ(DSPFW1); | |
3836 | reg &= ~DSPFW_SR_MASK; | |
3837 | reg |= wm << DSPFW_SR_SHIFT; | |
3838 | I915_WRITE(DSPFW1, reg); | |
3839 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
3840 | ||
3841 | /* cursor SR */ | |
d210246a CW |
3842 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, |
3843 | pineview_display_wm.fifo_size, | |
d4294342 ZY |
3844 | pixel_size, latency->cursor_sr); |
3845 | reg = I915_READ(DSPFW3); | |
3846 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
3847 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; | |
3848 | I915_WRITE(DSPFW3, reg); | |
3849 | ||
3850 | /* Display HPLL off SR */ | |
d210246a CW |
3851 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, |
3852 | pineview_display_hplloff_wm.fifo_size, | |
d4294342 ZY |
3853 | pixel_size, latency->display_hpll_disable); |
3854 | reg = I915_READ(DSPFW3); | |
3855 | reg &= ~DSPFW_HPLL_SR_MASK; | |
3856 | reg |= wm & DSPFW_HPLL_SR_MASK; | |
3857 | I915_WRITE(DSPFW3, reg); | |
3858 | ||
3859 | /* cursor HPLL off SR */ | |
d210246a CW |
3860 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, |
3861 | pineview_display_hplloff_wm.fifo_size, | |
d4294342 ZY |
3862 | pixel_size, latency->cursor_hpll_disable); |
3863 | reg = I915_READ(DSPFW3); | |
3864 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
3865 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; | |
3866 | I915_WRITE(DSPFW3, reg); | |
3867 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
3868 | ||
3869 | /* activate cxsr */ | |
3e33d94d CW |
3870 | I915_WRITE(DSPFW3, |
3871 | I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); | |
d4294342 ZY |
3872 | DRM_DEBUG_KMS("Self-refresh is enabled\n"); |
3873 | } else { | |
3874 | pineview_disable_cxsr(dev); | |
3875 | DRM_DEBUG_KMS("Self-refresh is disabled\n"); | |
3876 | } | |
3877 | } | |
3878 | ||
417ae147 CW |
3879 | static bool g4x_compute_wm0(struct drm_device *dev, |
3880 | int plane, | |
3881 | const struct intel_watermark_params *display, | |
3882 | int display_latency_ns, | |
3883 | const struct intel_watermark_params *cursor, | |
3884 | int cursor_latency_ns, | |
3885 | int *plane_wm, | |
3886 | int *cursor_wm) | |
3887 | { | |
3888 | struct drm_crtc *crtc; | |
3889 | int htotal, hdisplay, clock, pixel_size; | |
3890 | int line_time_us, line_count; | |
3891 | int entries, tlb_miss; | |
3892 | ||
3893 | crtc = intel_get_crtc_for_plane(dev, plane); | |
5c72d064 CW |
3894 | if (crtc->fb == NULL || !crtc->enabled) { |
3895 | *cursor_wm = cursor->guard_size; | |
3896 | *plane_wm = display->guard_size; | |
417ae147 | 3897 | return false; |
5c72d064 | 3898 | } |
417ae147 CW |
3899 | |
3900 | htotal = crtc->mode.htotal; | |
3901 | hdisplay = crtc->mode.hdisplay; | |
3902 | clock = crtc->mode.clock; | |
3903 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
3904 | ||
3905 | /* Use the small buffer method to calculate plane watermark */ | |
3906 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; | |
3907 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; | |
3908 | if (tlb_miss > 0) | |
3909 | entries += tlb_miss; | |
3910 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | |
3911 | *plane_wm = entries + display->guard_size; | |
3912 | if (*plane_wm > (int)display->max_wm) | |
3913 | *plane_wm = display->max_wm; | |
3914 | ||
3915 | /* Use the large buffer method to calculate cursor watermark */ | |
3916 | line_time_us = ((htotal * 1000) / clock); | |
3917 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; | |
3918 | entries = line_count * 64 * pixel_size; | |
3919 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; | |
3920 | if (tlb_miss > 0) | |
3921 | entries += tlb_miss; | |
3922 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
3923 | *cursor_wm = entries + cursor->guard_size; | |
3924 | if (*cursor_wm > (int)cursor->max_wm) | |
3925 | *cursor_wm = (int)cursor->max_wm; | |
3926 | ||
3927 | return true; | |
3928 | } | |
3929 | ||
3930 | /* | |
3931 | * Check the wm result. | |
3932 | * | |
3933 | * If any calculated watermark values is larger than the maximum value that | |
3934 | * can be programmed into the associated watermark register, that watermark | |
3935 | * must be disabled. | |
3936 | */ | |
3937 | static bool g4x_check_srwm(struct drm_device *dev, | |
3938 | int display_wm, int cursor_wm, | |
3939 | const struct intel_watermark_params *display, | |
3940 | const struct intel_watermark_params *cursor) | |
652c393a | 3941 | { |
417ae147 CW |
3942 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", |
3943 | display_wm, cursor_wm); | |
652c393a | 3944 | |
417ae147 | 3945 | if (display_wm > display->max_wm) { |
bbb0aef5 | 3946 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", |
417ae147 CW |
3947 | display_wm, display->max_wm); |
3948 | return false; | |
3949 | } | |
0e442c60 | 3950 | |
417ae147 | 3951 | if (cursor_wm > cursor->max_wm) { |
bbb0aef5 | 3952 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", |
417ae147 CW |
3953 | cursor_wm, cursor->max_wm); |
3954 | return false; | |
3955 | } | |
0e442c60 | 3956 | |
417ae147 CW |
3957 | if (!(display_wm || cursor_wm)) { |
3958 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); | |
3959 | return false; | |
3960 | } | |
0e442c60 | 3961 | |
417ae147 CW |
3962 | return true; |
3963 | } | |
0e442c60 | 3964 | |
417ae147 | 3965 | static bool g4x_compute_srwm(struct drm_device *dev, |
d210246a CW |
3966 | int plane, |
3967 | int latency_ns, | |
417ae147 CW |
3968 | const struct intel_watermark_params *display, |
3969 | const struct intel_watermark_params *cursor, | |
3970 | int *display_wm, int *cursor_wm) | |
3971 | { | |
d210246a CW |
3972 | struct drm_crtc *crtc; |
3973 | int hdisplay, htotal, pixel_size, clock; | |
417ae147 CW |
3974 | unsigned long line_time_us; |
3975 | int line_count, line_size; | |
3976 | int small, large; | |
3977 | int entries; | |
0e442c60 | 3978 | |
417ae147 CW |
3979 | if (!latency_ns) { |
3980 | *display_wm = *cursor_wm = 0; | |
3981 | return false; | |
3982 | } | |
0e442c60 | 3983 | |
d210246a CW |
3984 | crtc = intel_get_crtc_for_plane(dev, plane); |
3985 | hdisplay = crtc->mode.hdisplay; | |
3986 | htotal = crtc->mode.htotal; | |
3987 | clock = crtc->mode.clock; | |
3988 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
3989 | ||
417ae147 CW |
3990 | line_time_us = (htotal * 1000) / clock; |
3991 | line_count = (latency_ns / line_time_us + 1000) / 1000; | |
3992 | line_size = hdisplay * pixel_size; | |
0e442c60 | 3993 | |
417ae147 CW |
3994 | /* Use the minimum of the small and large buffer method for primary */ |
3995 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
3996 | large = line_count * line_size; | |
0e442c60 | 3997 | |
417ae147 CW |
3998 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
3999 | *display_wm = entries + display->guard_size; | |
4fe5e611 | 4000 | |
417ae147 CW |
4001 | /* calculate the self-refresh watermark for display cursor */ |
4002 | entries = line_count * pixel_size * 64; | |
4003 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
4004 | *cursor_wm = entries + cursor->guard_size; | |
4fe5e611 | 4005 | |
417ae147 CW |
4006 | return g4x_check_srwm(dev, |
4007 | *display_wm, *cursor_wm, | |
4008 | display, cursor); | |
4009 | } | |
4fe5e611 | 4010 | |
7ccb4a53 | 4011 | #define single_plane_enabled(mask) is_power_of_2(mask) |
d210246a CW |
4012 | |
4013 | static void g4x_update_wm(struct drm_device *dev) | |
417ae147 CW |
4014 | { |
4015 | static const int sr_latency_ns = 12000; | |
4016 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4017 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
d210246a CW |
4018 | int plane_sr, cursor_sr; |
4019 | unsigned int enabled = 0; | |
417ae147 CW |
4020 | |
4021 | if (g4x_compute_wm0(dev, 0, | |
4022 | &g4x_wm_info, latency_ns, | |
4023 | &g4x_cursor_wm_info, latency_ns, | |
4024 | &planea_wm, &cursora_wm)) | |
d210246a | 4025 | enabled |= 1; |
417ae147 CW |
4026 | |
4027 | if (g4x_compute_wm0(dev, 1, | |
4028 | &g4x_wm_info, latency_ns, | |
4029 | &g4x_cursor_wm_info, latency_ns, | |
4030 | &planeb_wm, &cursorb_wm)) | |
d210246a | 4031 | enabled |= 2; |
417ae147 CW |
4032 | |
4033 | plane_sr = cursor_sr = 0; | |
d210246a CW |
4034 | if (single_plane_enabled(enabled) && |
4035 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
4036 | sr_latency_ns, | |
417ae147 CW |
4037 | &g4x_wm_info, |
4038 | &g4x_cursor_wm_info, | |
4039 | &plane_sr, &cursor_sr)) | |
0e442c60 | 4040 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
417ae147 CW |
4041 | else |
4042 | I915_WRITE(FW_BLC_SELF, | |
4043 | I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); | |
0e442c60 | 4044 | |
308977ac CW |
4045 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
4046 | planea_wm, cursora_wm, | |
4047 | planeb_wm, cursorb_wm, | |
4048 | plane_sr, cursor_sr); | |
0e442c60 | 4049 | |
417ae147 CW |
4050 | I915_WRITE(DSPFW1, |
4051 | (plane_sr << DSPFW_SR_SHIFT) | | |
0e442c60 | 4052 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
417ae147 CW |
4053 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
4054 | planea_wm); | |
4055 | I915_WRITE(DSPFW2, | |
4056 | (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | | |
0e442c60 JB |
4057 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
4058 | /* HPLL off in SR has some issues on G4x... disable it */ | |
417ae147 CW |
4059 | I915_WRITE(DSPFW3, |
4060 | (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) | | |
0e442c60 | 4061 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
652c393a JB |
4062 | } |
4063 | ||
d210246a | 4064 | static void i965_update_wm(struct drm_device *dev) |
7662c8bd SL |
4065 | { |
4066 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a CW |
4067 | struct drm_crtc *crtc; |
4068 | int srwm = 1; | |
4fe5e611 | 4069 | int cursor_sr = 16; |
1dc7546d JB |
4070 | |
4071 | /* Calc sr entries for one plane configs */ | |
d210246a CW |
4072 | crtc = single_enabled_crtc(dev); |
4073 | if (crtc) { | |
1dc7546d | 4074 | /* self-refresh has much higher latency */ |
69e302a9 | 4075 | static const int sr_latency_ns = 12000; |
d210246a CW |
4076 | int clock = crtc->mode.clock; |
4077 | int htotal = crtc->mode.htotal; | |
4078 | int hdisplay = crtc->mode.hdisplay; | |
4079 | int pixel_size = crtc->fb->bits_per_pixel / 8; | |
4080 | unsigned long line_time_us; | |
4081 | int entries; | |
1dc7546d | 4082 | |
d210246a | 4083 | line_time_us = ((htotal * 1000) / clock); |
1dc7546d JB |
4084 | |
4085 | /* Use ns/us then divide to preserve precision */ | |
d210246a CW |
4086 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
4087 | pixel_size * hdisplay; | |
4088 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); | |
d210246a | 4089 | srwm = I965_FIFO_SIZE - entries; |
1dc7546d JB |
4090 | if (srwm < 0) |
4091 | srwm = 1; | |
1b07e04e | 4092 | srwm &= 0x1ff; |
308977ac CW |
4093 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", |
4094 | entries, srwm); | |
4fe5e611 | 4095 | |
d210246a | 4096 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
5eddb70b | 4097 | pixel_size * 64; |
d210246a | 4098 | entries = DIV_ROUND_UP(entries, |
8de9b311 | 4099 | i965_cursor_wm_info.cacheline_size); |
4fe5e611 | 4100 | cursor_sr = i965_cursor_wm_info.fifo_size - |
d210246a | 4101 | (entries + i965_cursor_wm_info.guard_size); |
4fe5e611 ZY |
4102 | |
4103 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
4104 | cursor_sr = i965_cursor_wm_info.max_wm; | |
4105 | ||
4106 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
4107 | "cursor %d\n", srwm, cursor_sr); | |
4108 | ||
a6c45cf0 | 4109 | if (IS_CRESTLINE(dev)) |
adcdbc66 | 4110 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
33c5fd12 DJ |
4111 | } else { |
4112 | /* Turn off self refresh if both pipes are enabled */ | |
a6c45cf0 | 4113 | if (IS_CRESTLINE(dev)) |
adcdbc66 JB |
4114 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) |
4115 | & ~FW_BLC_SELF_EN); | |
1dc7546d | 4116 | } |
7662c8bd | 4117 | |
1dc7546d JB |
4118 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
4119 | srwm); | |
7662c8bd SL |
4120 | |
4121 | /* 965 has limitations... */ | |
417ae147 CW |
4122 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | |
4123 | (8 << 16) | (8 << 8) | (8 << 0)); | |
7662c8bd | 4124 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); |
4fe5e611 ZY |
4125 | /* update cursor SR watermark */ |
4126 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
7662c8bd SL |
4127 | } |
4128 | ||
d210246a | 4129 | static void i9xx_update_wm(struct drm_device *dev) |
7662c8bd SL |
4130 | { |
4131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a | 4132 | const struct intel_watermark_params *wm_info; |
dff33cfc JB |
4133 | uint32_t fwater_lo; |
4134 | uint32_t fwater_hi; | |
d210246a CW |
4135 | int cwm, srwm = 1; |
4136 | int fifo_size; | |
dff33cfc | 4137 | int planea_wm, planeb_wm; |
d210246a | 4138 | struct drm_crtc *crtc, *enabled = NULL; |
7662c8bd | 4139 | |
72557b4f | 4140 | if (IS_I945GM(dev)) |
d210246a | 4141 | wm_info = &i945_wm_info; |
a6c45cf0 | 4142 | else if (!IS_GEN2(dev)) |
d210246a | 4143 | wm_info = &i915_wm_info; |
7662c8bd | 4144 | else |
d210246a CW |
4145 | wm_info = &i855_wm_info; |
4146 | ||
4147 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); | |
4148 | crtc = intel_get_crtc_for_plane(dev, 0); | |
4149 | if (crtc->enabled && crtc->fb) { | |
4150 | planea_wm = intel_calculate_wm(crtc->mode.clock, | |
4151 | wm_info, fifo_size, | |
4152 | crtc->fb->bits_per_pixel / 8, | |
4153 | latency_ns); | |
4154 | enabled = crtc; | |
4155 | } else | |
4156 | planea_wm = fifo_size - wm_info->guard_size; | |
4157 | ||
4158 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); | |
4159 | crtc = intel_get_crtc_for_plane(dev, 1); | |
4160 | if (crtc->enabled && crtc->fb) { | |
4161 | planeb_wm = intel_calculate_wm(crtc->mode.clock, | |
4162 | wm_info, fifo_size, | |
4163 | crtc->fb->bits_per_pixel / 8, | |
4164 | latency_ns); | |
4165 | if (enabled == NULL) | |
4166 | enabled = crtc; | |
4167 | else | |
4168 | enabled = NULL; | |
4169 | } else | |
4170 | planeb_wm = fifo_size - wm_info->guard_size; | |
7662c8bd | 4171 | |
28c97730 | 4172 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
7662c8bd SL |
4173 | |
4174 | /* | |
4175 | * Overlay gets an aggressive default since video jitter is bad. | |
4176 | */ | |
4177 | cwm = 2; | |
4178 | ||
18b2190c AL |
4179 | /* Play safe and disable self-refresh before adjusting watermarks. */ |
4180 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
4181 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0); | |
4182 | else if (IS_I915GM(dev)) | |
4183 | I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); | |
4184 | ||
dff33cfc | 4185 | /* Calc sr entries for one plane configs */ |
d210246a | 4186 | if (HAS_FW_BLC(dev) && enabled) { |
dff33cfc | 4187 | /* self-refresh has much higher latency */ |
69e302a9 | 4188 | static const int sr_latency_ns = 6000; |
d210246a CW |
4189 | int clock = enabled->mode.clock; |
4190 | int htotal = enabled->mode.htotal; | |
4191 | int hdisplay = enabled->mode.hdisplay; | |
4192 | int pixel_size = enabled->fb->bits_per_pixel / 8; | |
4193 | unsigned long line_time_us; | |
4194 | int entries; | |
dff33cfc | 4195 | |
d210246a | 4196 | line_time_us = (htotal * 1000) / clock; |
dff33cfc JB |
4197 | |
4198 | /* Use ns/us then divide to preserve precision */ | |
d210246a CW |
4199 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
4200 | pixel_size * hdisplay; | |
4201 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); | |
4202 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); | |
4203 | srwm = wm_info->fifo_size - entries; | |
dff33cfc JB |
4204 | if (srwm < 0) |
4205 | srwm = 1; | |
ee980b80 LP |
4206 | |
4207 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
18b2190c AL |
4208 | I915_WRITE(FW_BLC_SELF, |
4209 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
4210 | else if (IS_I915GM(dev)) | |
ee980b80 | 4211 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); |
7662c8bd SL |
4212 | } |
4213 | ||
28c97730 | 4214 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
5eddb70b | 4215 | planea_wm, planeb_wm, cwm, srwm); |
7662c8bd | 4216 | |
dff33cfc JB |
4217 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
4218 | fwater_hi = (cwm & 0x1f); | |
4219 | ||
4220 | /* Set request length to 8 cachelines per fetch */ | |
4221 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
4222 | fwater_hi = fwater_hi | (1 << 8); | |
7662c8bd SL |
4223 | |
4224 | I915_WRITE(FW_BLC, fwater_lo); | |
4225 | I915_WRITE(FW_BLC2, fwater_hi); | |
18b2190c | 4226 | |
d210246a CW |
4227 | if (HAS_FW_BLC(dev)) { |
4228 | if (enabled) { | |
4229 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
4230 | I915_WRITE(FW_BLC_SELF, | |
4231 | FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); | |
4232 | else if (IS_I915GM(dev)) | |
4233 | I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); | |
4234 | DRM_DEBUG_KMS("memory self refresh enabled\n"); | |
4235 | } else | |
4236 | DRM_DEBUG_KMS("memory self refresh disabled\n"); | |
4237 | } | |
7662c8bd SL |
4238 | } |
4239 | ||
d210246a | 4240 | static void i830_update_wm(struct drm_device *dev) |
7662c8bd SL |
4241 | { |
4242 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a CW |
4243 | struct drm_crtc *crtc; |
4244 | uint32_t fwater_lo; | |
dff33cfc | 4245 | int planea_wm; |
7662c8bd | 4246 | |
d210246a CW |
4247 | crtc = single_enabled_crtc(dev); |
4248 | if (crtc == NULL) | |
4249 | return; | |
7662c8bd | 4250 | |
d210246a CW |
4251 | planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info, |
4252 | dev_priv->display.get_fifo_size(dev, 0), | |
4253 | crtc->fb->bits_per_pixel / 8, | |
4254 | latency_ns); | |
4255 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; | |
f3601326 JB |
4256 | fwater_lo |= (3<<8) | planea_wm; |
4257 | ||
28c97730 | 4258 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
7662c8bd SL |
4259 | |
4260 | I915_WRITE(FW_BLC, fwater_lo); | |
4261 | } | |
4262 | ||
7f8a8569 | 4263 | #define ILK_LP0_PLANE_LATENCY 700 |
c936f44d | 4264 | #define ILK_LP0_CURSOR_LATENCY 1300 |
7f8a8569 | 4265 | |
1398261a YL |
4266 | /* |
4267 | * Check the wm result. | |
4268 | * | |
4269 | * If any calculated watermark values is larger than the maximum value that | |
4270 | * can be programmed into the associated watermark register, that watermark | |
4271 | * must be disabled. | |
1398261a | 4272 | */ |
b79d4990 JB |
4273 | static bool ironlake_check_srwm(struct drm_device *dev, int level, |
4274 | int fbc_wm, int display_wm, int cursor_wm, | |
4275 | const struct intel_watermark_params *display, | |
4276 | const struct intel_watermark_params *cursor) | |
1398261a YL |
4277 | { |
4278 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4279 | ||
4280 | DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d," | |
4281 | " cursor %d\n", level, display_wm, fbc_wm, cursor_wm); | |
4282 | ||
4283 | if (fbc_wm > SNB_FBC_MAX_SRWM) { | |
4284 | DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n", | |
b79d4990 | 4285 | fbc_wm, SNB_FBC_MAX_SRWM, level); |
1398261a YL |
4286 | |
4287 | /* fbc has it's own way to disable FBC WM */ | |
4288 | I915_WRITE(DISP_ARB_CTL, | |
4289 | I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS); | |
4290 | return false; | |
4291 | } | |
4292 | ||
b79d4990 | 4293 | if (display_wm > display->max_wm) { |
1398261a | 4294 | DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n", |
b79d4990 | 4295 | display_wm, SNB_DISPLAY_MAX_SRWM, level); |
1398261a YL |
4296 | return false; |
4297 | } | |
4298 | ||
b79d4990 | 4299 | if (cursor_wm > cursor->max_wm) { |
1398261a | 4300 | DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n", |
b79d4990 | 4301 | cursor_wm, SNB_CURSOR_MAX_SRWM, level); |
1398261a YL |
4302 | return false; |
4303 | } | |
4304 | ||
4305 | if (!(fbc_wm || display_wm || cursor_wm)) { | |
4306 | DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level); | |
4307 | return false; | |
4308 | } | |
4309 | ||
4310 | return true; | |
4311 | } | |
4312 | ||
4313 | /* | |
4314 | * Compute watermark values of WM[1-3], | |
4315 | */ | |
d210246a CW |
4316 | static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane, |
4317 | int latency_ns, | |
b79d4990 JB |
4318 | const struct intel_watermark_params *display, |
4319 | const struct intel_watermark_params *cursor, | |
4320 | int *fbc_wm, int *display_wm, int *cursor_wm) | |
1398261a | 4321 | { |
d210246a | 4322 | struct drm_crtc *crtc; |
1398261a | 4323 | unsigned long line_time_us; |
d210246a | 4324 | int hdisplay, htotal, pixel_size, clock; |
b79d4990 | 4325 | int line_count, line_size; |
1398261a YL |
4326 | int small, large; |
4327 | int entries; | |
1398261a YL |
4328 | |
4329 | if (!latency_ns) { | |
4330 | *fbc_wm = *display_wm = *cursor_wm = 0; | |
4331 | return false; | |
4332 | } | |
4333 | ||
d210246a CW |
4334 | crtc = intel_get_crtc_for_plane(dev, plane); |
4335 | hdisplay = crtc->mode.hdisplay; | |
4336 | htotal = crtc->mode.htotal; | |
4337 | clock = crtc->mode.clock; | |
4338 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
4339 | ||
1398261a YL |
4340 | line_time_us = (htotal * 1000) / clock; |
4341 | line_count = (latency_ns / line_time_us + 1000) / 1000; | |
4342 | line_size = hdisplay * pixel_size; | |
4343 | ||
4344 | /* Use the minimum of the small and large buffer method for primary */ | |
4345 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
4346 | large = line_count * line_size; | |
4347 | ||
b79d4990 JB |
4348 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
4349 | *display_wm = entries + display->guard_size; | |
1398261a YL |
4350 | |
4351 | /* | |
b79d4990 | 4352 | * Spec says: |
1398261a YL |
4353 | * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2 |
4354 | */ | |
4355 | *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2; | |
4356 | ||
4357 | /* calculate the self-refresh watermark for display cursor */ | |
4358 | entries = line_count * pixel_size * 64; | |
b79d4990 JB |
4359 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
4360 | *cursor_wm = entries + cursor->guard_size; | |
1398261a | 4361 | |
b79d4990 JB |
4362 | return ironlake_check_srwm(dev, level, |
4363 | *fbc_wm, *display_wm, *cursor_wm, | |
4364 | display, cursor); | |
4365 | } | |
4366 | ||
d210246a | 4367 | static void ironlake_update_wm(struct drm_device *dev) |
b79d4990 JB |
4368 | { |
4369 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a CW |
4370 | int fbc_wm, plane_wm, cursor_wm; |
4371 | unsigned int enabled; | |
b79d4990 JB |
4372 | |
4373 | enabled = 0; | |
9f405100 CW |
4374 | if (g4x_compute_wm0(dev, 0, |
4375 | &ironlake_display_wm_info, | |
4376 | ILK_LP0_PLANE_LATENCY, | |
4377 | &ironlake_cursor_wm_info, | |
4378 | ILK_LP0_CURSOR_LATENCY, | |
4379 | &plane_wm, &cursor_wm)) { | |
b79d4990 JB |
4380 | I915_WRITE(WM0_PIPEA_ILK, |
4381 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
4382 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" | |
4383 | " plane %d, " "cursor: %d\n", | |
4384 | plane_wm, cursor_wm); | |
d210246a | 4385 | enabled |= 1; |
b79d4990 JB |
4386 | } |
4387 | ||
9f405100 CW |
4388 | if (g4x_compute_wm0(dev, 1, |
4389 | &ironlake_display_wm_info, | |
4390 | ILK_LP0_PLANE_LATENCY, | |
4391 | &ironlake_cursor_wm_info, | |
4392 | ILK_LP0_CURSOR_LATENCY, | |
4393 | &plane_wm, &cursor_wm)) { | |
b79d4990 JB |
4394 | I915_WRITE(WM0_PIPEB_ILK, |
4395 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
4396 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" | |
4397 | " plane %d, cursor: %d\n", | |
4398 | plane_wm, cursor_wm); | |
d210246a | 4399 | enabled |= 2; |
b79d4990 JB |
4400 | } |
4401 | ||
4402 | /* | |
4403 | * Calculate and update the self-refresh watermark only when one | |
4404 | * display plane is used. | |
4405 | */ | |
4406 | I915_WRITE(WM3_LP_ILK, 0); | |
4407 | I915_WRITE(WM2_LP_ILK, 0); | |
4408 | I915_WRITE(WM1_LP_ILK, 0); | |
4409 | ||
d210246a | 4410 | if (!single_plane_enabled(enabled)) |
b79d4990 | 4411 | return; |
d210246a | 4412 | enabled = ffs(enabled) - 1; |
b79d4990 JB |
4413 | |
4414 | /* WM1 */ | |
d210246a CW |
4415 | if (!ironlake_compute_srwm(dev, 1, enabled, |
4416 | ILK_READ_WM1_LATENCY() * 500, | |
b79d4990 JB |
4417 | &ironlake_display_srwm_info, |
4418 | &ironlake_cursor_srwm_info, | |
4419 | &fbc_wm, &plane_wm, &cursor_wm)) | |
4420 | return; | |
4421 | ||
4422 | I915_WRITE(WM1_LP_ILK, | |
4423 | WM1_LP_SR_EN | | |
4424 | (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4425 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4426 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4427 | cursor_wm); | |
4428 | ||
4429 | /* WM2 */ | |
d210246a CW |
4430 | if (!ironlake_compute_srwm(dev, 2, enabled, |
4431 | ILK_READ_WM2_LATENCY() * 500, | |
b79d4990 JB |
4432 | &ironlake_display_srwm_info, |
4433 | &ironlake_cursor_srwm_info, | |
4434 | &fbc_wm, &plane_wm, &cursor_wm)) | |
4435 | return; | |
4436 | ||
4437 | I915_WRITE(WM2_LP_ILK, | |
4438 | WM2_LP_EN | | |
4439 | (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4440 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4441 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4442 | cursor_wm); | |
4443 | ||
4444 | /* | |
4445 | * WM3 is unsupported on ILK, probably because we don't have latency | |
4446 | * data for that power state | |
4447 | */ | |
1398261a YL |
4448 | } |
4449 | ||
d210246a | 4450 | static void sandybridge_update_wm(struct drm_device *dev) |
1398261a YL |
4451 | { |
4452 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a0fa62d3 | 4453 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
d210246a CW |
4454 | int fbc_wm, plane_wm, cursor_wm; |
4455 | unsigned int enabled; | |
1398261a YL |
4456 | |
4457 | enabled = 0; | |
9f405100 CW |
4458 | if (g4x_compute_wm0(dev, 0, |
4459 | &sandybridge_display_wm_info, latency, | |
4460 | &sandybridge_cursor_wm_info, latency, | |
4461 | &plane_wm, &cursor_wm)) { | |
1398261a YL |
4462 | I915_WRITE(WM0_PIPEA_ILK, |
4463 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
4464 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" | |
4465 | " plane %d, " "cursor: %d\n", | |
4466 | plane_wm, cursor_wm); | |
d210246a | 4467 | enabled |= 1; |
1398261a YL |
4468 | } |
4469 | ||
9f405100 CW |
4470 | if (g4x_compute_wm0(dev, 1, |
4471 | &sandybridge_display_wm_info, latency, | |
4472 | &sandybridge_cursor_wm_info, latency, | |
4473 | &plane_wm, &cursor_wm)) { | |
1398261a YL |
4474 | I915_WRITE(WM0_PIPEB_ILK, |
4475 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
4476 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" | |
4477 | " plane %d, cursor: %d\n", | |
4478 | plane_wm, cursor_wm); | |
d210246a | 4479 | enabled |= 2; |
1398261a YL |
4480 | } |
4481 | ||
4482 | /* | |
4483 | * Calculate and update the self-refresh watermark only when one | |
4484 | * display plane is used. | |
4485 | * | |
4486 | * SNB support 3 levels of watermark. | |
4487 | * | |
4488 | * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, | |
4489 | * and disabled in the descending order | |
4490 | * | |
4491 | */ | |
4492 | I915_WRITE(WM3_LP_ILK, 0); | |
4493 | I915_WRITE(WM2_LP_ILK, 0); | |
4494 | I915_WRITE(WM1_LP_ILK, 0); | |
4495 | ||
d210246a | 4496 | if (!single_plane_enabled(enabled)) |
1398261a | 4497 | return; |
d210246a | 4498 | enabled = ffs(enabled) - 1; |
1398261a YL |
4499 | |
4500 | /* WM1 */ | |
d210246a CW |
4501 | if (!ironlake_compute_srwm(dev, 1, enabled, |
4502 | SNB_READ_WM1_LATENCY() * 500, | |
b79d4990 JB |
4503 | &sandybridge_display_srwm_info, |
4504 | &sandybridge_cursor_srwm_info, | |
4505 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
4506 | return; |
4507 | ||
4508 | I915_WRITE(WM1_LP_ILK, | |
4509 | WM1_LP_SR_EN | | |
4510 | (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4511 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4512 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4513 | cursor_wm); | |
4514 | ||
4515 | /* WM2 */ | |
d210246a CW |
4516 | if (!ironlake_compute_srwm(dev, 2, enabled, |
4517 | SNB_READ_WM2_LATENCY() * 500, | |
b79d4990 JB |
4518 | &sandybridge_display_srwm_info, |
4519 | &sandybridge_cursor_srwm_info, | |
4520 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
4521 | return; |
4522 | ||
4523 | I915_WRITE(WM2_LP_ILK, | |
4524 | WM2_LP_EN | | |
4525 | (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4526 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4527 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4528 | cursor_wm); | |
4529 | ||
4530 | /* WM3 */ | |
d210246a CW |
4531 | if (!ironlake_compute_srwm(dev, 3, enabled, |
4532 | SNB_READ_WM3_LATENCY() * 500, | |
b79d4990 JB |
4533 | &sandybridge_display_srwm_info, |
4534 | &sandybridge_cursor_srwm_info, | |
4535 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
4536 | return; |
4537 | ||
4538 | I915_WRITE(WM3_LP_ILK, | |
4539 | WM3_LP_EN | | |
4540 | (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4541 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4542 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4543 | cursor_wm); | |
4544 | } | |
4545 | ||
7662c8bd SL |
4546 | /** |
4547 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
4548 | * | |
4549 | * Calculate watermark values for the various WM regs based on current mode | |
4550 | * and plane configuration. | |
4551 | * | |
4552 | * There are several cases to deal with here: | |
4553 | * - normal (i.e. non-self-refresh) | |
4554 | * - self-refresh (SR) mode | |
4555 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
4556 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
4557 | * lines), so need to account for TLB latency | |
4558 | * | |
4559 | * The normal calculation is: | |
4560 | * watermark = dotclock * bytes per pixel * latency | |
4561 | * where latency is platform & configuration dependent (we assume pessimal | |
4562 | * values here). | |
4563 | * | |
4564 | * The SR calculation is: | |
4565 | * watermark = (trunc(latency/line time)+1) * surface width * | |
4566 | * bytes per pixel | |
4567 | * where | |
4568 | * line time = htotal / dotclock | |
fa143215 | 4569 | * surface width = hdisplay for normal plane and 64 for cursor |
7662c8bd SL |
4570 | * and latency is assumed to be high, as above. |
4571 | * | |
4572 | * The final value programmed to the register should always be rounded up, | |
4573 | * and include an extra 2 entries to account for clock crossings. | |
4574 | * | |
4575 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
4576 | * to set the non-SR watermarks to 8. | |
5eddb70b | 4577 | */ |
7662c8bd SL |
4578 | static void intel_update_watermarks(struct drm_device *dev) |
4579 | { | |
e70236a8 | 4580 | struct drm_i915_private *dev_priv = dev->dev_private; |
7662c8bd | 4581 | |
d210246a CW |
4582 | if (dev_priv->display.update_wm) |
4583 | dev_priv->display.update_wm(dev); | |
7662c8bd SL |
4584 | } |
4585 | ||
a7615030 CW |
4586 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
4587 | { | |
72bbe58c KP |
4588 | if (i915_panel_use_ssc >= 0) |
4589 | return i915_panel_use_ssc != 0; | |
4590 | return dev_priv->lvds_use_ssc | |
435793df | 4591 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
4592 | } |
4593 | ||
5a354204 JB |
4594 | /** |
4595 | * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send | |
4596 | * @crtc: CRTC structure | |
4597 | * | |
4598 | * A pipe may be connected to one or more outputs. Based on the depth of the | |
4599 | * attached framebuffer, choose a good color depth to use on the pipe. | |
4600 | * | |
4601 | * If possible, match the pipe depth to the fb depth. In some cases, this | |
4602 | * isn't ideal, because the connected output supports a lesser or restricted | |
4603 | * set of depths. Resolve that here: | |
4604 | * LVDS typically supports only 6bpc, so clamp down in that case | |
4605 | * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc | |
4606 | * Displays may support a restricted set as well, check EDID and clamp as | |
4607 | * appropriate. | |
4608 | * | |
4609 | * RETURNS: | |
4610 | * Dithering requirement (i.e. false if display bpc and pipe bpc match, | |
4611 | * true if they don't match). | |
4612 | */ | |
4613 | static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, | |
4614 | unsigned int *pipe_bpp) | |
4615 | { | |
4616 | struct drm_device *dev = crtc->dev; | |
4617 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4618 | struct drm_encoder *encoder; | |
4619 | struct drm_connector *connector; | |
4620 | unsigned int display_bpc = UINT_MAX, bpc; | |
4621 | ||
4622 | /* Walk the encoders & connectors on this crtc, get min bpc */ | |
4623 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
4624 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
4625 | ||
4626 | if (encoder->crtc != crtc) | |
4627 | continue; | |
4628 | ||
4629 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) { | |
4630 | unsigned int lvds_bpc; | |
4631 | ||
4632 | if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == | |
4633 | LVDS_A3_POWER_UP) | |
4634 | lvds_bpc = 8; | |
4635 | else | |
4636 | lvds_bpc = 6; | |
4637 | ||
4638 | if (lvds_bpc < display_bpc) { | |
4639 | DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc); | |
4640 | display_bpc = lvds_bpc; | |
4641 | } | |
4642 | continue; | |
4643 | } | |
4644 | ||
4645 | if (intel_encoder->type == INTEL_OUTPUT_EDP) { | |
4646 | /* Use VBT settings if we have an eDP panel */ | |
4647 | unsigned int edp_bpc = dev_priv->edp.bpp / 3; | |
4648 | ||
4649 | if (edp_bpc < display_bpc) { | |
4650 | DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc); | |
4651 | display_bpc = edp_bpc; | |
4652 | } | |
4653 | continue; | |
4654 | } | |
4655 | ||
4656 | /* Not one of the known troublemakers, check the EDID */ | |
4657 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
4658 | head) { | |
4659 | if (connector->encoder != encoder) | |
4660 | continue; | |
4661 | ||
62ac41a6 JB |
4662 | /* Don't use an invalid EDID bpc value */ |
4663 | if (connector->display_info.bpc && | |
4664 | connector->display_info.bpc < display_bpc) { | |
5a354204 JB |
4665 | DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc); |
4666 | display_bpc = connector->display_info.bpc; | |
4667 | } | |
4668 | } | |
4669 | ||
4670 | /* | |
4671 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
4672 | * through, clamp it down. (Note: >12bpc will be caught below.) | |
4673 | */ | |
4674 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { | |
4675 | if (display_bpc > 8 && display_bpc < 12) { | |
4676 | DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n"); | |
4677 | display_bpc = 12; | |
4678 | } else { | |
4679 | DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n"); | |
4680 | display_bpc = 8; | |
4681 | } | |
4682 | } | |
4683 | } | |
4684 | ||
4685 | /* | |
4686 | * We could just drive the pipe at the highest bpc all the time and | |
4687 | * enable dithering as needed, but that costs bandwidth. So choose | |
4688 | * the minimum value that expresses the full color range of the fb but | |
4689 | * also stays within the max display bpc discovered above. | |
4690 | */ | |
4691 | ||
4692 | switch (crtc->fb->depth) { | |
4693 | case 8: | |
4694 | bpc = 8; /* since we go through a colormap */ | |
4695 | break; | |
4696 | case 15: | |
4697 | case 16: | |
4698 | bpc = 6; /* min is 18bpp */ | |
4699 | break; | |
4700 | case 24: | |
578393cd | 4701 | bpc = 8; |
5a354204 JB |
4702 | break; |
4703 | case 30: | |
578393cd | 4704 | bpc = 10; |
5a354204 JB |
4705 | break; |
4706 | case 48: | |
578393cd | 4707 | bpc = 12; |
5a354204 JB |
4708 | break; |
4709 | default: | |
4710 | DRM_DEBUG("unsupported depth, assuming 24 bits\n"); | |
4711 | bpc = min((unsigned int)8, display_bpc); | |
4712 | break; | |
4713 | } | |
4714 | ||
578393cd KP |
4715 | display_bpc = min(display_bpc, bpc); |
4716 | ||
5a354204 JB |
4717 | DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n", |
4718 | bpc, display_bpc); | |
4719 | ||
578393cd | 4720 | *pipe_bpp = display_bpc * 3; |
5a354204 JB |
4721 | |
4722 | return display_bpc != bpc; | |
4723 | } | |
4724 | ||
f564048e EA |
4725 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
4726 | struct drm_display_mode *mode, | |
4727 | struct drm_display_mode *adjusted_mode, | |
4728 | int x, int y, | |
4729 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
4730 | { |
4731 | struct drm_device *dev = crtc->dev; | |
4732 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4733 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4734 | int pipe = intel_crtc->pipe; | |
80824003 | 4735 | int plane = intel_crtc->plane; |
c751ce4f | 4736 | int refclk, num_connectors = 0; |
652c393a | 4737 | intel_clock_t clock, reduced_clock; |
5eddb70b | 4738 | u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; |
652c393a | 4739 | bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; |
a4fc5ed6 | 4740 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
79e53945 | 4741 | struct drm_mode_config *mode_config = &dev->mode_config; |
5eddb70b | 4742 | struct intel_encoder *encoder; |
d4906093 | 4743 | const intel_limit_t *limit; |
5c3b82e2 | 4744 | int ret; |
fae14981 | 4745 | u32 temp; |
aa9b500d | 4746 | u32 lvds_sync = 0; |
79e53945 | 4747 | |
5eddb70b CW |
4748 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
4749 | if (encoder->base.crtc != crtc) | |
79e53945 JB |
4750 | continue; |
4751 | ||
5eddb70b | 4752 | switch (encoder->type) { |
79e53945 JB |
4753 | case INTEL_OUTPUT_LVDS: |
4754 | is_lvds = true; | |
4755 | break; | |
4756 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 4757 | case INTEL_OUTPUT_HDMI: |
79e53945 | 4758 | is_sdvo = true; |
5eddb70b | 4759 | if (encoder->needs_tv_clock) |
e2f0ba97 | 4760 | is_tv = true; |
79e53945 JB |
4761 | break; |
4762 | case INTEL_OUTPUT_DVO: | |
4763 | is_dvo = true; | |
4764 | break; | |
4765 | case INTEL_OUTPUT_TVOUT: | |
4766 | is_tv = true; | |
4767 | break; | |
4768 | case INTEL_OUTPUT_ANALOG: | |
4769 | is_crt = true; | |
4770 | break; | |
a4fc5ed6 KP |
4771 | case INTEL_OUTPUT_DISPLAYPORT: |
4772 | is_dp = true; | |
4773 | break; | |
79e53945 | 4774 | } |
43565a06 | 4775 | |
c751ce4f | 4776 | num_connectors++; |
79e53945 JB |
4777 | } |
4778 | ||
a7615030 | 4779 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
43565a06 | 4780 | refclk = dev_priv->lvds_ssc_freq * 1000; |
28c97730 | 4781 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
5eddb70b | 4782 | refclk / 1000); |
a6c45cf0 | 4783 | } else if (!IS_GEN2(dev)) { |
79e53945 JB |
4784 | refclk = 96000; |
4785 | } else { | |
4786 | refclk = 48000; | |
4787 | } | |
4788 | ||
d4906093 ML |
4789 | /* |
4790 | * Returns a set of divisors for the desired target clock with the given | |
4791 | * refclk, or FALSE. The returned values represent the clock equation: | |
4792 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
4793 | */ | |
1b894b59 | 4794 | limit = intel_limit(crtc, refclk); |
d4906093 | 4795 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock); |
79e53945 JB |
4796 | if (!ok) { |
4797 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5c3b82e2 | 4798 | return -EINVAL; |
79e53945 JB |
4799 | } |
4800 | ||
cda4b7d3 | 4801 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 4802 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 4803 | |
ddc9003c ZY |
4804 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
4805 | has_reduced_clock = limit->find_pll(limit, crtc, | |
5eddb70b CW |
4806 | dev_priv->lvds_downclock, |
4807 | refclk, | |
4808 | &reduced_clock); | |
18f9ed12 ZY |
4809 | if (has_reduced_clock && (clock.p != reduced_clock.p)) { |
4810 | /* | |
4811 | * If the different P is found, it means that we can't | |
4812 | * switch the display clock by using the FP0/FP1. | |
4813 | * In such case we will disable the LVDS downclock | |
4814 | * feature. | |
4815 | */ | |
4816 | DRM_DEBUG_KMS("Different P is found for " | |
5eddb70b | 4817 | "LVDS clock/downclock\n"); |
18f9ed12 ZY |
4818 | has_reduced_clock = 0; |
4819 | } | |
652c393a | 4820 | } |
7026d4ac ZW |
4821 | /* SDVO TV has fixed PLL values depend on its clock range, |
4822 | this mirrors vbios setting. */ | |
4823 | if (is_sdvo && is_tv) { | |
4824 | if (adjusted_mode->clock >= 100000 | |
5eddb70b | 4825 | && adjusted_mode->clock < 140500) { |
7026d4ac ZW |
4826 | clock.p1 = 2; |
4827 | clock.p2 = 10; | |
4828 | clock.n = 3; | |
4829 | clock.m1 = 16; | |
4830 | clock.m2 = 8; | |
4831 | } else if (adjusted_mode->clock >= 140500 | |
5eddb70b | 4832 | && adjusted_mode->clock <= 200000) { |
7026d4ac ZW |
4833 | clock.p1 = 1; |
4834 | clock.p2 = 10; | |
4835 | clock.n = 6; | |
4836 | clock.m1 = 12; | |
4837 | clock.m2 = 8; | |
4838 | } | |
4839 | } | |
4840 | ||
f2b115e6 | 4841 | if (IS_PINEVIEW(dev)) { |
2177832f | 4842 | fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; |
652c393a JB |
4843 | if (has_reduced_clock) |
4844 | fp2 = (1 << reduced_clock.n) << 16 | | |
4845 | reduced_clock.m1 << 8 | reduced_clock.m2; | |
4846 | } else { | |
2177832f | 4847 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
652c393a JB |
4848 | if (has_reduced_clock) |
4849 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | | |
4850 | reduced_clock.m2; | |
4851 | } | |
79e53945 | 4852 | |
929c77fb | 4853 | dpll = DPLL_VGA_MODE_DIS; |
2c07245f | 4854 | |
a6c45cf0 | 4855 | if (!IS_GEN2(dev)) { |
79e53945 JB |
4856 | if (is_lvds) |
4857 | dpll |= DPLLB_MODE_LVDS; | |
4858 | else | |
4859 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
4860 | if (is_sdvo) { | |
6c9547ff CW |
4861 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
4862 | if (pixel_multiplier > 1) { | |
4863 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
4864 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; | |
6c9547ff | 4865 | } |
79e53945 | 4866 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 | 4867 | } |
929c77fb | 4868 | if (is_dp) |
a4fc5ed6 | 4869 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 JB |
4870 | |
4871 | /* compute bitmask from p1 value */ | |
f2b115e6 AJ |
4872 | if (IS_PINEVIEW(dev)) |
4873 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
2c07245f | 4874 | else { |
2177832f | 4875 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
652c393a JB |
4876 | if (IS_G4X(dev) && has_reduced_clock) |
4877 | dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
2c07245f | 4878 | } |
79e53945 JB |
4879 | switch (clock.p2) { |
4880 | case 5: | |
4881 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
4882 | break; | |
4883 | case 7: | |
4884 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
4885 | break; | |
4886 | case 10: | |
4887 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
4888 | break; | |
4889 | case 14: | |
4890 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
4891 | break; | |
4892 | } | |
929c77fb | 4893 | if (INTEL_INFO(dev)->gen >= 4) |
79e53945 JB |
4894 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
4895 | } else { | |
4896 | if (is_lvds) { | |
4897 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4898 | } else { | |
4899 | if (clock.p1 == 2) | |
4900 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
4901 | else | |
4902 | dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4903 | if (clock.p2 == 4) | |
4904 | dpll |= PLL_P2_DIVIDE_BY_4; | |
4905 | } | |
4906 | } | |
4907 | ||
43565a06 KH |
4908 | if (is_sdvo && is_tv) |
4909 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
4910 | else if (is_tv) | |
79e53945 | 4911 | /* XXX: just matching BIOS for now */ |
43565a06 | 4912 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 4913 | dpll |= 3; |
a7615030 | 4914 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 4915 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
4916 | else |
4917 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4918 | ||
4919 | /* setup pipeconf */ | |
5eddb70b | 4920 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
4921 | |
4922 | /* Set up the display plane register */ | |
4923 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4924 | ||
f2b115e6 | 4925 | /* Ironlake's plane is forced to pipe, bit 24 is to |
2c07245f | 4926 | enable color space conversion */ |
929c77fb EA |
4927 | if (pipe == 0) |
4928 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
4929 | else | |
4930 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
79e53945 | 4931 | |
a6c45cf0 | 4932 | if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
79e53945 JB |
4933 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
4934 | * core speed. | |
4935 | * | |
4936 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
4937 | * pipe == 0 check? | |
4938 | */ | |
e70236a8 JB |
4939 | if (mode->clock > |
4940 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) | |
5eddb70b | 4941 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
79e53945 | 4942 | else |
5eddb70b | 4943 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; |
79e53945 JB |
4944 | } |
4945 | ||
929c77fb | 4946 | dpll |= DPLL_VCO_ENABLE; |
8d86dc6a | 4947 | |
28c97730 | 4948 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
79e53945 JB |
4949 | drm_mode_debug_printmodeline(mode); |
4950 | ||
fae14981 EA |
4951 | I915_WRITE(FP0(pipe), fp); |
4952 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
5eddb70b | 4953 | |
fae14981 | 4954 | POSTING_READ(DPLL(pipe)); |
c713bb08 | 4955 | udelay(150); |
8db9d77b | 4956 | |
79e53945 JB |
4957 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
4958 | * This is an exception to the general rule that mode_set doesn't turn | |
4959 | * things on. | |
4960 | */ | |
4961 | if (is_lvds) { | |
fae14981 | 4962 | temp = I915_READ(LVDS); |
5eddb70b | 4963 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
b3b095b3 | 4964 | if (pipe == 1) { |
929c77fb | 4965 | temp |= LVDS_PIPEB_SELECT; |
b3b095b3 | 4966 | } else { |
929c77fb | 4967 | temp &= ~LVDS_PIPEB_SELECT; |
b3b095b3 | 4968 | } |
a3e17eb8 | 4969 | /* set the corresponsding LVDS_BORDER bit */ |
5eddb70b | 4970 | temp |= dev_priv->lvds_border_bits; |
79e53945 JB |
4971 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
4972 | * set the DPLLs for dual-channel mode or not. | |
4973 | */ | |
4974 | if (clock.p2 == 7) | |
5eddb70b | 4975 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
79e53945 | 4976 | else |
5eddb70b | 4977 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
79e53945 JB |
4978 | |
4979 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
4980 | * appropriately here, but we need to look more thoroughly into how | |
4981 | * panels behave in the two modes. | |
4982 | */ | |
929c77fb EA |
4983 | /* set the dithering flag on LVDS as needed */ |
4984 | if (INTEL_INFO(dev)->gen >= 4) { | |
434ed097 | 4985 | if (dev_priv->lvds_dither) |
5eddb70b | 4986 | temp |= LVDS_ENABLE_DITHER; |
434ed097 | 4987 | else |
5eddb70b | 4988 | temp &= ~LVDS_ENABLE_DITHER; |
898822ce | 4989 | } |
aa9b500d BF |
4990 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
4991 | lvds_sync |= LVDS_HSYNC_POLARITY; | |
4992 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) | |
4993 | lvds_sync |= LVDS_VSYNC_POLARITY; | |
4994 | if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY)) | |
4995 | != lvds_sync) { | |
4996 | char flags[2] = "-+"; | |
4997 | DRM_INFO("Changing LVDS panel from " | |
4998 | "(%chsync, %cvsync) to (%chsync, %cvsync)\n", | |
4999 | flags[!(temp & LVDS_HSYNC_POLARITY)], | |
5000 | flags[!(temp & LVDS_VSYNC_POLARITY)], | |
5001 | flags[!(lvds_sync & LVDS_HSYNC_POLARITY)], | |
5002 | flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]); | |
5003 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
5004 | temp |= lvds_sync; | |
5005 | } | |
fae14981 | 5006 | I915_WRITE(LVDS, temp); |
79e53945 | 5007 | } |
434ed097 | 5008 | |
929c77fb | 5009 | if (is_dp) { |
a4fc5ed6 | 5010 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
434ed097 JB |
5011 | } |
5012 | ||
fae14981 | 5013 | I915_WRITE(DPLL(pipe), dpll); |
5eddb70b | 5014 | |
c713bb08 | 5015 | /* Wait for the clocks to stabilize. */ |
fae14981 | 5016 | POSTING_READ(DPLL(pipe)); |
c713bb08 | 5017 | udelay(150); |
32f9d658 | 5018 | |
c713bb08 EA |
5019 | if (INTEL_INFO(dev)->gen >= 4) { |
5020 | temp = 0; | |
5021 | if (is_sdvo) { | |
5022 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); | |
5023 | if (temp > 1) | |
5024 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
5025 | else | |
5026 | temp = 0; | |
32f9d658 | 5027 | } |
c713bb08 EA |
5028 | I915_WRITE(DPLL_MD(pipe), temp); |
5029 | } else { | |
5030 | /* The pixel multiplier can only be updated once the | |
5031 | * DPLL is enabled and the clocks are stable. | |
5032 | * | |
5033 | * So write it again. | |
5034 | */ | |
fae14981 | 5035 | I915_WRITE(DPLL(pipe), dpll); |
79e53945 | 5036 | } |
79e53945 | 5037 | |
5eddb70b | 5038 | intel_crtc->lowfreq_avail = false; |
652c393a | 5039 | if (is_lvds && has_reduced_clock && i915_powersave) { |
fae14981 | 5040 | I915_WRITE(FP1(pipe), fp2); |
652c393a JB |
5041 | intel_crtc->lowfreq_avail = true; |
5042 | if (HAS_PIPE_CXSR(dev)) { | |
28c97730 | 5043 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
652c393a JB |
5044 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
5045 | } | |
5046 | } else { | |
fae14981 | 5047 | I915_WRITE(FP1(pipe), fp); |
652c393a | 5048 | if (HAS_PIPE_CXSR(dev)) { |
28c97730 | 5049 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
652c393a JB |
5050 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
5051 | } | |
5052 | } | |
5053 | ||
734b4157 KH |
5054 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
5055 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
5056 | /* the chip adds 2 halflines automatically */ | |
5057 | adjusted_mode->crtc_vdisplay -= 1; | |
5058 | adjusted_mode->crtc_vtotal -= 1; | |
5059 | adjusted_mode->crtc_vblank_start -= 1; | |
5060 | adjusted_mode->crtc_vblank_end -= 1; | |
5061 | adjusted_mode->crtc_vsync_end -= 1; | |
5062 | adjusted_mode->crtc_vsync_start -= 1; | |
5063 | } else | |
5064 | pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */ | |
5065 | ||
5eddb70b CW |
5066 | I915_WRITE(HTOTAL(pipe), |
5067 | (adjusted_mode->crtc_hdisplay - 1) | | |
79e53945 | 5068 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5eddb70b CW |
5069 | I915_WRITE(HBLANK(pipe), |
5070 | (adjusted_mode->crtc_hblank_start - 1) | | |
79e53945 | 5071 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5eddb70b CW |
5072 | I915_WRITE(HSYNC(pipe), |
5073 | (adjusted_mode->crtc_hsync_start - 1) | | |
79e53945 | 5074 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5eddb70b CW |
5075 | |
5076 | I915_WRITE(VTOTAL(pipe), | |
5077 | (adjusted_mode->crtc_vdisplay - 1) | | |
79e53945 | 5078 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
5eddb70b CW |
5079 | I915_WRITE(VBLANK(pipe), |
5080 | (adjusted_mode->crtc_vblank_start - 1) | | |
79e53945 | 5081 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
5eddb70b CW |
5082 | I915_WRITE(VSYNC(pipe), |
5083 | (adjusted_mode->crtc_vsync_start - 1) | | |
79e53945 | 5084 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5eddb70b CW |
5085 | |
5086 | /* pipesrc and dspsize control the size that is scaled from, | |
5087 | * which should always be the user's requested size. | |
79e53945 | 5088 | */ |
929c77fb EA |
5089 | I915_WRITE(DSPSIZE(plane), |
5090 | ((mode->vdisplay - 1) << 16) | | |
5091 | (mode->hdisplay - 1)); | |
5092 | I915_WRITE(DSPPOS(plane), 0); | |
5eddb70b CW |
5093 | I915_WRITE(PIPESRC(pipe), |
5094 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
2c07245f | 5095 | |
f564048e EA |
5096 | I915_WRITE(PIPECONF(pipe), pipeconf); |
5097 | POSTING_READ(PIPECONF(pipe)); | |
929c77fb | 5098 | intel_enable_pipe(dev_priv, pipe, false); |
f564048e EA |
5099 | |
5100 | intel_wait_for_vblank(dev, pipe); | |
5101 | ||
f564048e EA |
5102 | I915_WRITE(DSPCNTR(plane), dspcntr); |
5103 | POSTING_READ(DSPCNTR(plane)); | |
284d9529 | 5104 | intel_enable_plane(dev_priv, plane, pipe); |
f564048e EA |
5105 | |
5106 | ret = intel_pipe_set_base(crtc, x, y, old_fb); | |
5107 | ||
5108 | intel_update_watermarks(dev); | |
5109 | ||
f564048e EA |
5110 | return ret; |
5111 | } | |
5112 | ||
9fb526db KP |
5113 | /* |
5114 | * Initialize reference clocks when the driver loads | |
5115 | */ | |
5116 | void ironlake_init_pch_refclk(struct drm_device *dev) | |
13d83a67 JB |
5117 | { |
5118 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5119 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 5120 | struct intel_encoder *encoder; |
13d83a67 JB |
5121 | u32 temp; |
5122 | bool has_lvds = false; | |
199e5d79 KP |
5123 | bool has_cpu_edp = false; |
5124 | bool has_pch_edp = false; | |
5125 | bool has_panel = false; | |
99eb6a01 KP |
5126 | bool has_ck505 = false; |
5127 | bool can_ssc = false; | |
13d83a67 JB |
5128 | |
5129 | /* We need to take the global config into account */ | |
199e5d79 KP |
5130 | list_for_each_entry(encoder, &mode_config->encoder_list, |
5131 | base.head) { | |
5132 | switch (encoder->type) { | |
5133 | case INTEL_OUTPUT_LVDS: | |
5134 | has_panel = true; | |
5135 | has_lvds = true; | |
5136 | break; | |
5137 | case INTEL_OUTPUT_EDP: | |
5138 | has_panel = true; | |
5139 | if (intel_encoder_is_pch_edp(&encoder->base)) | |
5140 | has_pch_edp = true; | |
5141 | else | |
5142 | has_cpu_edp = true; | |
5143 | break; | |
13d83a67 JB |
5144 | } |
5145 | } | |
5146 | ||
99eb6a01 KP |
5147 | if (HAS_PCH_IBX(dev)) { |
5148 | has_ck505 = dev_priv->display_clock_mode; | |
5149 | can_ssc = has_ck505; | |
5150 | } else { | |
5151 | has_ck505 = false; | |
5152 | can_ssc = true; | |
5153 | } | |
5154 | ||
5155 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n", | |
5156 | has_panel, has_lvds, has_pch_edp, has_cpu_edp, | |
5157 | has_ck505); | |
13d83a67 JB |
5158 | |
5159 | /* Ironlake: try to setup display ref clock before DPLL | |
5160 | * enabling. This is only under driver's control after | |
5161 | * PCH B stepping, previous chipset stepping should be | |
5162 | * ignoring this setting. | |
5163 | */ | |
5164 | temp = I915_READ(PCH_DREF_CONTROL); | |
5165 | /* Always enable nonspread source */ | |
5166 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; | |
13d83a67 | 5167 | |
99eb6a01 KP |
5168 | if (has_ck505) |
5169 | temp |= DREF_NONSPREAD_CK505_ENABLE; | |
5170 | else | |
5171 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; | |
13d83a67 | 5172 | |
199e5d79 KP |
5173 | if (has_panel) { |
5174 | temp &= ~DREF_SSC_SOURCE_MASK; | |
5175 | temp |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 5176 | |
199e5d79 | 5177 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 5178 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5179 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
13d83a67 | 5180 | temp |= DREF_SSC1_ENABLE; |
13d83a67 | 5181 | } |
199e5d79 KP |
5182 | |
5183 | /* Get SSC going before enabling the outputs */ | |
5184 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
5185 | POSTING_READ(PCH_DREF_CONTROL); | |
5186 | udelay(200); | |
5187 | ||
13d83a67 JB |
5188 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
5189 | ||
5190 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 5191 | if (has_cpu_edp) { |
99eb6a01 | 5192 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5193 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
13d83a67 | 5194 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
199e5d79 | 5195 | } |
13d83a67 JB |
5196 | else |
5197 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
199e5d79 KP |
5198 | } else |
5199 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5200 | ||
5201 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
5202 | POSTING_READ(PCH_DREF_CONTROL); | |
5203 | udelay(200); | |
5204 | } else { | |
5205 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
5206 | ||
5207 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
5208 | ||
5209 | /* Turn off CPU output */ | |
5210 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5211 | ||
5212 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
5213 | POSTING_READ(PCH_DREF_CONTROL); | |
5214 | udelay(200); | |
5215 | ||
5216 | /* Turn off the SSC source */ | |
5217 | temp &= ~DREF_SSC_SOURCE_MASK; | |
5218 | temp |= DREF_SSC_SOURCE_DISABLE; | |
5219 | ||
5220 | /* Turn off SSC1 */ | |
5221 | temp &= ~ DREF_SSC1_ENABLE; | |
5222 | ||
13d83a67 JB |
5223 | I915_WRITE(PCH_DREF_CONTROL, temp); |
5224 | POSTING_READ(PCH_DREF_CONTROL); | |
5225 | udelay(200); | |
5226 | } | |
5227 | } | |
5228 | ||
f564048e EA |
5229 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
5230 | struct drm_display_mode *mode, | |
5231 | struct drm_display_mode *adjusted_mode, | |
5232 | int x, int y, | |
5233 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
5234 | { |
5235 | struct drm_device *dev = crtc->dev; | |
5236 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5237 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5238 | int pipe = intel_crtc->pipe; | |
80824003 | 5239 | int plane = intel_crtc->plane; |
c751ce4f | 5240 | int refclk, num_connectors = 0; |
652c393a | 5241 | intel_clock_t clock, reduced_clock; |
5eddb70b | 5242 | u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; |
a07d6787 | 5243 | bool ok, has_reduced_clock = false, is_sdvo = false; |
a4fc5ed6 | 5244 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
8e647a27 | 5245 | struct intel_encoder *has_edp_encoder = NULL; |
79e53945 | 5246 | struct drm_mode_config *mode_config = &dev->mode_config; |
5eddb70b | 5247 | struct intel_encoder *encoder; |
d4906093 | 5248 | const intel_limit_t *limit; |
5c3b82e2 | 5249 | int ret; |
2c07245f | 5250 | struct fdi_m_n m_n = {0}; |
fae14981 | 5251 | u32 temp; |
aa9b500d | 5252 | u32 lvds_sync = 0; |
5a354204 JB |
5253 | int target_clock, pixel_multiplier, lane, link_bw, factor; |
5254 | unsigned int pipe_bpp; | |
5255 | bool dither; | |
79e53945 | 5256 | |
5eddb70b CW |
5257 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
5258 | if (encoder->base.crtc != crtc) | |
79e53945 JB |
5259 | continue; |
5260 | ||
5eddb70b | 5261 | switch (encoder->type) { |
79e53945 JB |
5262 | case INTEL_OUTPUT_LVDS: |
5263 | is_lvds = true; | |
5264 | break; | |
5265 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 5266 | case INTEL_OUTPUT_HDMI: |
79e53945 | 5267 | is_sdvo = true; |
5eddb70b | 5268 | if (encoder->needs_tv_clock) |
e2f0ba97 | 5269 | is_tv = true; |
79e53945 | 5270 | break; |
79e53945 JB |
5271 | case INTEL_OUTPUT_TVOUT: |
5272 | is_tv = true; | |
5273 | break; | |
5274 | case INTEL_OUTPUT_ANALOG: | |
5275 | is_crt = true; | |
5276 | break; | |
a4fc5ed6 KP |
5277 | case INTEL_OUTPUT_DISPLAYPORT: |
5278 | is_dp = true; | |
5279 | break; | |
32f9d658 | 5280 | case INTEL_OUTPUT_EDP: |
5eddb70b | 5281 | has_edp_encoder = encoder; |
32f9d658 | 5282 | break; |
79e53945 | 5283 | } |
43565a06 | 5284 | |
c751ce4f | 5285 | num_connectors++; |
79e53945 JB |
5286 | } |
5287 | ||
afffb9df KP |
5288 | /* |
5289 | * Every reference clock in a PCH system is 120MHz | |
5290 | */ | |
5291 | refclk = 120000; | |
79e53945 | 5292 | |
d4906093 ML |
5293 | /* |
5294 | * Returns a set of divisors for the desired target clock with the given | |
5295 | * refclk, or FALSE. The returned values represent the clock equation: | |
5296 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
5297 | */ | |
1b894b59 | 5298 | limit = intel_limit(crtc, refclk); |
d4906093 | 5299 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock); |
79e53945 JB |
5300 | if (!ok) { |
5301 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5c3b82e2 | 5302 | return -EINVAL; |
79e53945 JB |
5303 | } |
5304 | ||
cda4b7d3 | 5305 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 5306 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 5307 | |
ddc9003c ZY |
5308 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
5309 | has_reduced_clock = limit->find_pll(limit, crtc, | |
5eddb70b CW |
5310 | dev_priv->lvds_downclock, |
5311 | refclk, | |
5312 | &reduced_clock); | |
18f9ed12 ZY |
5313 | if (has_reduced_clock && (clock.p != reduced_clock.p)) { |
5314 | /* | |
5315 | * If the different P is found, it means that we can't | |
5316 | * switch the display clock by using the FP0/FP1. | |
5317 | * In such case we will disable the LVDS downclock | |
5318 | * feature. | |
5319 | */ | |
5320 | DRM_DEBUG_KMS("Different P is found for " | |
5eddb70b | 5321 | "LVDS clock/downclock\n"); |
18f9ed12 ZY |
5322 | has_reduced_clock = 0; |
5323 | } | |
652c393a | 5324 | } |
7026d4ac ZW |
5325 | /* SDVO TV has fixed PLL values depend on its clock range, |
5326 | this mirrors vbios setting. */ | |
5327 | if (is_sdvo && is_tv) { | |
5328 | if (adjusted_mode->clock >= 100000 | |
5eddb70b | 5329 | && adjusted_mode->clock < 140500) { |
7026d4ac ZW |
5330 | clock.p1 = 2; |
5331 | clock.p2 = 10; | |
5332 | clock.n = 3; | |
5333 | clock.m1 = 16; | |
5334 | clock.m2 = 8; | |
5335 | } else if (adjusted_mode->clock >= 140500 | |
5eddb70b | 5336 | && adjusted_mode->clock <= 200000) { |
7026d4ac ZW |
5337 | clock.p1 = 1; |
5338 | clock.p2 = 10; | |
5339 | clock.n = 6; | |
5340 | clock.m1 = 12; | |
5341 | clock.m2 = 8; | |
5342 | } | |
5343 | } | |
5344 | ||
2c07245f | 5345 | /* FDI link */ |
8febb297 EA |
5346 | pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
5347 | lane = 0; | |
5348 | /* CPU eDP doesn't require FDI link, so just set DP M/N | |
5349 | according to current link config */ | |
5350 | if (has_edp_encoder && | |
5351 | !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
5352 | target_clock = mode->clock; | |
5353 | intel_edp_link_config(has_edp_encoder, | |
5354 | &lane, &link_bw); | |
5355 | } else { | |
5356 | /* [e]DP over FDI requires target mode clock | |
5357 | instead of link clock */ | |
5358 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) | |
5eb08b69 | 5359 | target_clock = mode->clock; |
8febb297 EA |
5360 | else |
5361 | target_clock = adjusted_mode->clock; | |
5362 | ||
5363 | /* FDI is a binary signal running at ~2.7GHz, encoding | |
5364 | * each output octet as 10 bits. The actual frequency | |
5365 | * is stored as a divider into a 100MHz clock, and the | |
5366 | * mode pixel clock is stored in units of 1KHz. | |
5367 | * Hence the bw of each lane in terms of the mode signal | |
5368 | * is: | |
5369 | */ | |
5370 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5371 | } | |
58a27471 | 5372 | |
8febb297 EA |
5373 | /* determine panel color depth */ |
5374 | temp = I915_READ(PIPECONF(pipe)); | |
5375 | temp &= ~PIPE_BPC_MASK; | |
5a354204 JB |
5376 | dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp); |
5377 | switch (pipe_bpp) { | |
5378 | case 18: | |
5379 | temp |= PIPE_6BPC; | |
8febb297 | 5380 | break; |
5a354204 JB |
5381 | case 24: |
5382 | temp |= PIPE_8BPC; | |
8febb297 | 5383 | break; |
5a354204 JB |
5384 | case 30: |
5385 | temp |= PIPE_10BPC; | |
8febb297 | 5386 | break; |
5a354204 JB |
5387 | case 36: |
5388 | temp |= PIPE_12BPC; | |
8febb297 EA |
5389 | break; |
5390 | default: | |
62ac41a6 JB |
5391 | WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n", |
5392 | pipe_bpp); | |
5a354204 JB |
5393 | temp |= PIPE_8BPC; |
5394 | pipe_bpp = 24; | |
5395 | break; | |
8febb297 | 5396 | } |
77ffb597 | 5397 | |
5a354204 JB |
5398 | intel_crtc->bpp = pipe_bpp; |
5399 | I915_WRITE(PIPECONF(pipe), temp); | |
5400 | ||
8febb297 EA |
5401 | if (!lane) { |
5402 | /* | |
5403 | * Account for spread spectrum to avoid | |
5404 | * oversubscribing the link. Max center spread | |
5405 | * is 2.5%; use 5% for safety's sake. | |
5406 | */ | |
5a354204 | 5407 | u32 bps = target_clock * intel_crtc->bpp * 21 / 20; |
8febb297 | 5408 | lane = bps / (link_bw * 8) + 1; |
5eb08b69 | 5409 | } |
2c07245f | 5410 | |
8febb297 EA |
5411 | intel_crtc->fdi_lanes = lane; |
5412 | ||
5413 | if (pixel_multiplier > 1) | |
5414 | link_bw *= pixel_multiplier; | |
5a354204 JB |
5415 | ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, |
5416 | &m_n); | |
8febb297 | 5417 | |
a07d6787 EA |
5418 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
5419 | if (has_reduced_clock) | |
5420 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | | |
5421 | reduced_clock.m2; | |
79e53945 | 5422 | |
c1858123 | 5423 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
5424 | factor = 21; |
5425 | if (is_lvds) { | |
5426 | if ((intel_panel_use_ssc(dev_priv) && | |
5427 | dev_priv->lvds_ssc_freq == 100) || | |
5428 | (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) | |
5429 | factor = 25; | |
5430 | } else if (is_sdvo && is_tv) | |
5431 | factor = 20; | |
c1858123 | 5432 | |
cb0e0931 | 5433 | if (clock.m < factor * clock.n) |
8febb297 | 5434 | fp |= FP_CB_TUNE; |
2c07245f | 5435 | |
5eddb70b | 5436 | dpll = 0; |
2c07245f | 5437 | |
a07d6787 EA |
5438 | if (is_lvds) |
5439 | dpll |= DPLLB_MODE_LVDS; | |
5440 | else | |
5441 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
5442 | if (is_sdvo) { | |
5443 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); | |
5444 | if (pixel_multiplier > 1) { | |
5445 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
79e53945 | 5446 | } |
a07d6787 EA |
5447 | dpll |= DPLL_DVO_HIGH_SPEED; |
5448 | } | |
5449 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) | |
5450 | dpll |= DPLL_DVO_HIGH_SPEED; | |
79e53945 | 5451 | |
a07d6787 EA |
5452 | /* compute bitmask from p1 value */ |
5453 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5454 | /* also FPA1 */ | |
5455 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
5456 | ||
5457 | switch (clock.p2) { | |
5458 | case 5: | |
5459 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5460 | break; | |
5461 | case 7: | |
5462 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5463 | break; | |
5464 | case 10: | |
5465 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5466 | break; | |
5467 | case 14: | |
5468 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5469 | break; | |
79e53945 JB |
5470 | } |
5471 | ||
43565a06 KH |
5472 | if (is_sdvo && is_tv) |
5473 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
5474 | else if (is_tv) | |
79e53945 | 5475 | /* XXX: just matching BIOS for now */ |
43565a06 | 5476 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 5477 | dpll |= 3; |
a7615030 | 5478 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 5479 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
5480 | else |
5481 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5482 | ||
5483 | /* setup pipeconf */ | |
5eddb70b | 5484 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
5485 | |
5486 | /* Set up the display plane register */ | |
5487 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
5488 | ||
28c97730 | 5489 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
79e53945 JB |
5490 | drm_mode_debug_printmodeline(mode); |
5491 | ||
5c5313c8 JB |
5492 | /* PCH eDP needs FDI, but CPU eDP does not */ |
5493 | if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
fae14981 EA |
5494 | I915_WRITE(PCH_FP0(pipe), fp); |
5495 | I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
5eddb70b | 5496 | |
fae14981 | 5497 | POSTING_READ(PCH_DPLL(pipe)); |
79e53945 JB |
5498 | udelay(150); |
5499 | } | |
5500 | ||
8db9d77b ZW |
5501 | /* enable transcoder DPLL */ |
5502 | if (HAS_PCH_CPT(dev)) { | |
5503 | temp = I915_READ(PCH_DPLL_SEL); | |
9db4a9c7 JB |
5504 | switch (pipe) { |
5505 | case 0: | |
5eddb70b | 5506 | temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL; |
9db4a9c7 JB |
5507 | break; |
5508 | case 1: | |
5eddb70b | 5509 | temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL; |
9db4a9c7 JB |
5510 | break; |
5511 | case 2: | |
5512 | /* FIXME: manage transcoder PLLs? */ | |
5513 | temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL; | |
5514 | break; | |
5515 | default: | |
5516 | BUG(); | |
32f9d658 | 5517 | } |
8db9d77b | 5518 | I915_WRITE(PCH_DPLL_SEL, temp); |
5eddb70b CW |
5519 | |
5520 | POSTING_READ(PCH_DPLL_SEL); | |
8db9d77b ZW |
5521 | udelay(150); |
5522 | } | |
5523 | ||
79e53945 JB |
5524 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
5525 | * This is an exception to the general rule that mode_set doesn't turn | |
5526 | * things on. | |
5527 | */ | |
5528 | if (is_lvds) { | |
fae14981 | 5529 | temp = I915_READ(PCH_LVDS); |
5eddb70b | 5530 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
b3b095b3 ZW |
5531 | if (pipe == 1) { |
5532 | if (HAS_PCH_CPT(dev)) | |
5eddb70b | 5533 | temp |= PORT_TRANS_B_SEL_CPT; |
b3b095b3 | 5534 | else |
5eddb70b | 5535 | temp |= LVDS_PIPEB_SELECT; |
b3b095b3 ZW |
5536 | } else { |
5537 | if (HAS_PCH_CPT(dev)) | |
5eddb70b | 5538 | temp &= ~PORT_TRANS_SEL_MASK; |
b3b095b3 | 5539 | else |
5eddb70b | 5540 | temp &= ~LVDS_PIPEB_SELECT; |
b3b095b3 | 5541 | } |
a3e17eb8 | 5542 | /* set the corresponsding LVDS_BORDER bit */ |
5eddb70b | 5543 | temp |= dev_priv->lvds_border_bits; |
79e53945 JB |
5544 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
5545 | * set the DPLLs for dual-channel mode or not. | |
5546 | */ | |
5547 | if (clock.p2 == 7) | |
5eddb70b | 5548 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
79e53945 | 5549 | else |
5eddb70b | 5550 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
79e53945 JB |
5551 | |
5552 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
5553 | * appropriately here, but we need to look more thoroughly into how | |
5554 | * panels behave in the two modes. | |
5555 | */ | |
aa9b500d BF |
5556 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
5557 | lvds_sync |= LVDS_HSYNC_POLARITY; | |
5558 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) | |
5559 | lvds_sync |= LVDS_VSYNC_POLARITY; | |
5560 | if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY)) | |
5561 | != lvds_sync) { | |
5562 | char flags[2] = "-+"; | |
5563 | DRM_INFO("Changing LVDS panel from " | |
5564 | "(%chsync, %cvsync) to (%chsync, %cvsync)\n", | |
5565 | flags[!(temp & LVDS_HSYNC_POLARITY)], | |
5566 | flags[!(temp & LVDS_VSYNC_POLARITY)], | |
5567 | flags[!(lvds_sync & LVDS_HSYNC_POLARITY)], | |
5568 | flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]); | |
5569 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
5570 | temp |= lvds_sync; | |
5571 | } | |
fae14981 | 5572 | I915_WRITE(PCH_LVDS, temp); |
79e53945 | 5573 | } |
434ed097 | 5574 | |
8febb297 EA |
5575 | pipeconf &= ~PIPECONF_DITHER_EN; |
5576 | pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; | |
5a354204 | 5577 | if ((is_lvds && dev_priv->lvds_dither) || dither) { |
8febb297 EA |
5578 | pipeconf |= PIPECONF_DITHER_EN; |
5579 | pipeconf |= PIPECONF_DITHER_TYPE_ST1; | |
434ed097 | 5580 | } |
5c5313c8 | 5581 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
a4fc5ed6 | 5582 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
8febb297 | 5583 | } else { |
8db9d77b | 5584 | /* For non-DP output, clear any trans DP clock recovery setting.*/ |
9db4a9c7 JB |
5585 | I915_WRITE(TRANSDATA_M1(pipe), 0); |
5586 | I915_WRITE(TRANSDATA_N1(pipe), 0); | |
5587 | I915_WRITE(TRANSDPLINK_M1(pipe), 0); | |
5588 | I915_WRITE(TRANSDPLINK_N1(pipe), 0); | |
8db9d77b | 5589 | } |
79e53945 | 5590 | |
8febb297 EA |
5591 | if (!has_edp_encoder || |
5592 | intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
fae14981 | 5593 | I915_WRITE(PCH_DPLL(pipe), dpll); |
5eddb70b | 5594 | |
32f9d658 | 5595 | /* Wait for the clocks to stabilize. */ |
fae14981 | 5596 | POSTING_READ(PCH_DPLL(pipe)); |
32f9d658 ZW |
5597 | udelay(150); |
5598 | ||
8febb297 EA |
5599 | /* The pixel multiplier can only be updated once the |
5600 | * DPLL is enabled and the clocks are stable. | |
5601 | * | |
5602 | * So write it again. | |
5603 | */ | |
fae14981 | 5604 | I915_WRITE(PCH_DPLL(pipe), dpll); |
79e53945 | 5605 | } |
79e53945 | 5606 | |
5eddb70b | 5607 | intel_crtc->lowfreq_avail = false; |
652c393a | 5608 | if (is_lvds && has_reduced_clock && i915_powersave) { |
fae14981 | 5609 | I915_WRITE(PCH_FP1(pipe), fp2); |
652c393a JB |
5610 | intel_crtc->lowfreq_avail = true; |
5611 | if (HAS_PIPE_CXSR(dev)) { | |
28c97730 | 5612 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
652c393a JB |
5613 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
5614 | } | |
5615 | } else { | |
fae14981 | 5616 | I915_WRITE(PCH_FP1(pipe), fp); |
652c393a | 5617 | if (HAS_PIPE_CXSR(dev)) { |
28c97730 | 5618 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
652c393a JB |
5619 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
5620 | } | |
5621 | } | |
5622 | ||
734b4157 KH |
5623 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
5624 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
5625 | /* the chip adds 2 halflines automatically */ | |
5626 | adjusted_mode->crtc_vdisplay -= 1; | |
5627 | adjusted_mode->crtc_vtotal -= 1; | |
5628 | adjusted_mode->crtc_vblank_start -= 1; | |
5629 | adjusted_mode->crtc_vblank_end -= 1; | |
5630 | adjusted_mode->crtc_vsync_end -= 1; | |
5631 | adjusted_mode->crtc_vsync_start -= 1; | |
5632 | } else | |
5633 | pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */ | |
5634 | ||
5eddb70b CW |
5635 | I915_WRITE(HTOTAL(pipe), |
5636 | (adjusted_mode->crtc_hdisplay - 1) | | |
79e53945 | 5637 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5eddb70b CW |
5638 | I915_WRITE(HBLANK(pipe), |
5639 | (adjusted_mode->crtc_hblank_start - 1) | | |
79e53945 | 5640 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5eddb70b CW |
5641 | I915_WRITE(HSYNC(pipe), |
5642 | (adjusted_mode->crtc_hsync_start - 1) | | |
79e53945 | 5643 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5eddb70b CW |
5644 | |
5645 | I915_WRITE(VTOTAL(pipe), | |
5646 | (adjusted_mode->crtc_vdisplay - 1) | | |
79e53945 | 5647 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
5eddb70b CW |
5648 | I915_WRITE(VBLANK(pipe), |
5649 | (adjusted_mode->crtc_vblank_start - 1) | | |
79e53945 | 5650 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
5eddb70b CW |
5651 | I915_WRITE(VSYNC(pipe), |
5652 | (adjusted_mode->crtc_vsync_start - 1) | | |
79e53945 | 5653 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5eddb70b | 5654 | |
8febb297 EA |
5655 | /* pipesrc controls the size that is scaled from, which should |
5656 | * always be the user's requested size. | |
79e53945 | 5657 | */ |
5eddb70b CW |
5658 | I915_WRITE(PIPESRC(pipe), |
5659 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
2c07245f | 5660 | |
8febb297 EA |
5661 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
5662 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); | |
5663 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); | |
5664 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); | |
2c07245f | 5665 | |
8febb297 EA |
5666 | if (has_edp_encoder && |
5667 | !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
5668 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); | |
2c07245f ZW |
5669 | } |
5670 | ||
5eddb70b CW |
5671 | I915_WRITE(PIPECONF(pipe), pipeconf); |
5672 | POSTING_READ(PIPECONF(pipe)); | |
79e53945 | 5673 | |
9d0498a2 | 5674 | intel_wait_for_vblank(dev, pipe); |
79e53945 | 5675 | |
f00a3ddf | 5676 | if (IS_GEN5(dev)) { |
553bd149 ZW |
5677 | /* enable address swizzle for tiling buffer */ |
5678 | temp = I915_READ(DISP_ARB_CTL); | |
5679 | I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); | |
5680 | } | |
5681 | ||
5eddb70b | 5682 | I915_WRITE(DSPCNTR(plane), dspcntr); |
b24e7179 | 5683 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 5684 | |
5c3b82e2 | 5685 | ret = intel_pipe_set_base(crtc, x, y, old_fb); |
7662c8bd SL |
5686 | |
5687 | intel_update_watermarks(dev); | |
5688 | ||
1f803ee5 | 5689 | return ret; |
79e53945 JB |
5690 | } |
5691 | ||
f564048e EA |
5692 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
5693 | struct drm_display_mode *mode, | |
5694 | struct drm_display_mode *adjusted_mode, | |
5695 | int x, int y, | |
5696 | struct drm_framebuffer *old_fb) | |
5697 | { | |
5698 | struct drm_device *dev = crtc->dev; | |
5699 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b701d27 EA |
5700 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5701 | int pipe = intel_crtc->pipe; | |
f564048e EA |
5702 | int ret; |
5703 | ||
0b701d27 | 5704 | drm_vblank_pre_modeset(dev, pipe); |
7662c8bd | 5705 | |
f564048e EA |
5706 | ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode, |
5707 | x, y, old_fb); | |
7662c8bd | 5708 | |
79e53945 | 5709 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 5710 | |
120eced9 KP |
5711 | intel_crtc->dpms_mode = DRM_MODE_DPMS_ON; |
5712 | ||
1f803ee5 | 5713 | return ret; |
79e53945 JB |
5714 | } |
5715 | ||
e0dac65e WF |
5716 | static void g4x_write_eld(struct drm_connector *connector, |
5717 | struct drm_crtc *crtc) | |
5718 | { | |
5719 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
5720 | uint8_t *eld = connector->eld; | |
5721 | uint32_t eldv; | |
5722 | uint32_t len; | |
5723 | uint32_t i; | |
5724 | ||
5725 | i = I915_READ(G4X_AUD_VID_DID); | |
5726 | ||
5727 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
5728 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
5729 | else | |
5730 | eldv = G4X_ELDV_DEVCTG; | |
5731 | ||
5732 | i = I915_READ(G4X_AUD_CNTL_ST); | |
5733 | i &= ~(eldv | G4X_ELD_ADDR); | |
5734 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
5735 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
5736 | ||
5737 | if (!eld[0]) | |
5738 | return; | |
5739 | ||
5740 | len = min_t(uint8_t, eld[2], len); | |
5741 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
5742 | for (i = 0; i < len; i++) | |
5743 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
5744 | ||
5745 | i = I915_READ(G4X_AUD_CNTL_ST); | |
5746 | i |= eldv; | |
5747 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
5748 | } | |
5749 | ||
5750 | static void ironlake_write_eld(struct drm_connector *connector, | |
5751 | struct drm_crtc *crtc) | |
5752 | { | |
5753 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
5754 | uint8_t *eld = connector->eld; | |
5755 | uint32_t eldv; | |
5756 | uint32_t i; | |
5757 | int len; | |
5758 | int hdmiw_hdmiedid; | |
5759 | int aud_cntl_st; | |
5760 | int aud_cntrl_st2; | |
5761 | ||
5762 | if (IS_IVYBRIDGE(connector->dev)) { | |
5763 | hdmiw_hdmiedid = GEN7_HDMIW_HDMIEDID_A; | |
5764 | aud_cntl_st = GEN7_AUD_CNTRL_ST_A; | |
5765 | aud_cntrl_st2 = GEN7_AUD_CNTRL_ST2; | |
5766 | } else { | |
5767 | hdmiw_hdmiedid = GEN5_HDMIW_HDMIEDID_A; | |
5768 | aud_cntl_st = GEN5_AUD_CNTL_ST_A; | |
5769 | aud_cntrl_st2 = GEN5_AUD_CNTL_ST2; | |
5770 | } | |
5771 | ||
5772 | i = to_intel_crtc(crtc)->pipe; | |
5773 | hdmiw_hdmiedid += i * 0x100; | |
5774 | aud_cntl_st += i * 0x100; | |
5775 | ||
5776 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i)); | |
5777 | ||
5778 | i = I915_READ(aud_cntl_st); | |
5779 | i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */ | |
5780 | if (!i) { | |
5781 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
5782 | /* operate blindly on all ports */ | |
5783 | eldv = GEN5_ELD_VALIDB; | |
5784 | eldv |= GEN5_ELD_VALIDB << 4; | |
5785 | eldv |= GEN5_ELD_VALIDB << 8; | |
5786 | } else { | |
5787 | DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i); | |
5788 | eldv = GEN5_ELD_VALIDB << ((i - 1) * 4); | |
5789 | } | |
5790 | ||
5791 | i = I915_READ(aud_cntrl_st2); | |
5792 | i &= ~eldv; | |
5793 | I915_WRITE(aud_cntrl_st2, i); | |
5794 | ||
5795 | if (!eld[0]) | |
5796 | return; | |
5797 | ||
5798 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
5799 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
5800 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
5801 | } | |
5802 | ||
5803 | i = I915_READ(aud_cntl_st); | |
5804 | i &= ~GEN5_ELD_ADDRESS; | |
5805 | I915_WRITE(aud_cntl_st, i); | |
5806 | ||
5807 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
5808 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
5809 | for (i = 0; i < len; i++) | |
5810 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
5811 | ||
5812 | i = I915_READ(aud_cntrl_st2); | |
5813 | i |= eldv; | |
5814 | I915_WRITE(aud_cntrl_st2, i); | |
5815 | } | |
5816 | ||
5817 | void intel_write_eld(struct drm_encoder *encoder, | |
5818 | struct drm_display_mode *mode) | |
5819 | { | |
5820 | struct drm_crtc *crtc = encoder->crtc; | |
5821 | struct drm_connector *connector; | |
5822 | struct drm_device *dev = encoder->dev; | |
5823 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5824 | ||
5825 | connector = drm_select_eld(encoder, mode); | |
5826 | if (!connector) | |
5827 | return; | |
5828 | ||
5829 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
5830 | connector->base.id, | |
5831 | drm_get_connector_name(connector), | |
5832 | connector->encoder->base.id, | |
5833 | drm_get_encoder_name(connector->encoder)); | |
5834 | ||
5835 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
5836 | ||
5837 | if (dev_priv->display.write_eld) | |
5838 | dev_priv->display.write_eld(connector, crtc); | |
5839 | } | |
5840 | ||
79e53945 JB |
5841 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
5842 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
5843 | { | |
5844 | struct drm_device *dev = crtc->dev; | |
5845 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5846 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9db4a9c7 | 5847 | int palreg = PALETTE(intel_crtc->pipe); |
79e53945 JB |
5848 | int i; |
5849 | ||
5850 | /* The clocks have to be on to load the palette. */ | |
5851 | if (!crtc->enabled) | |
5852 | return; | |
5853 | ||
f2b115e6 | 5854 | /* use legacy palette for Ironlake */ |
bad720ff | 5855 | if (HAS_PCH_SPLIT(dev)) |
9db4a9c7 | 5856 | palreg = LGC_PALETTE(intel_crtc->pipe); |
2c07245f | 5857 | |
79e53945 JB |
5858 | for (i = 0; i < 256; i++) { |
5859 | I915_WRITE(palreg + 4 * i, | |
5860 | (intel_crtc->lut_r[i] << 16) | | |
5861 | (intel_crtc->lut_g[i] << 8) | | |
5862 | intel_crtc->lut_b[i]); | |
5863 | } | |
5864 | } | |
5865 | ||
560b85bb CW |
5866 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
5867 | { | |
5868 | struct drm_device *dev = crtc->dev; | |
5869 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5870 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5871 | bool visible = base != 0; | |
5872 | u32 cntl; | |
5873 | ||
5874 | if (intel_crtc->cursor_visible == visible) | |
5875 | return; | |
5876 | ||
9db4a9c7 | 5877 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
5878 | if (visible) { |
5879 | /* On these chipsets we can only modify the base whilst | |
5880 | * the cursor is disabled. | |
5881 | */ | |
9db4a9c7 | 5882 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
5883 | |
5884 | cntl &= ~(CURSOR_FORMAT_MASK); | |
5885 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
5886 | cntl |= CURSOR_ENABLE | | |
5887 | CURSOR_GAMMA_ENABLE | | |
5888 | CURSOR_FORMAT_ARGB; | |
5889 | } else | |
5890 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 5891 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
5892 | |
5893 | intel_crtc->cursor_visible = visible; | |
5894 | } | |
5895 | ||
5896 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
5897 | { | |
5898 | struct drm_device *dev = crtc->dev; | |
5899 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5900 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5901 | int pipe = intel_crtc->pipe; | |
5902 | bool visible = base != 0; | |
5903 | ||
5904 | if (intel_crtc->cursor_visible != visible) { | |
548f245b | 5905 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
5906 | if (base) { |
5907 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
5908 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
5909 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
5910 | } else { | |
5911 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
5912 | cntl |= CURSOR_MODE_DISABLE; | |
5913 | } | |
9db4a9c7 | 5914 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
5915 | |
5916 | intel_crtc->cursor_visible = visible; | |
5917 | } | |
5918 | /* and commit changes on next vblank */ | |
9db4a9c7 | 5919 | I915_WRITE(CURBASE(pipe), base); |
560b85bb CW |
5920 | } |
5921 | ||
cda4b7d3 | 5922 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
5923 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
5924 | bool on) | |
cda4b7d3 CW |
5925 | { |
5926 | struct drm_device *dev = crtc->dev; | |
5927 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5928 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5929 | int pipe = intel_crtc->pipe; | |
5930 | int x = intel_crtc->cursor_x; | |
5931 | int y = intel_crtc->cursor_y; | |
560b85bb | 5932 | u32 base, pos; |
cda4b7d3 CW |
5933 | bool visible; |
5934 | ||
5935 | pos = 0; | |
5936 | ||
6b383a7f | 5937 | if (on && crtc->enabled && crtc->fb) { |
cda4b7d3 CW |
5938 | base = intel_crtc->cursor_addr; |
5939 | if (x > (int) crtc->fb->width) | |
5940 | base = 0; | |
5941 | ||
5942 | if (y > (int) crtc->fb->height) | |
5943 | base = 0; | |
5944 | } else | |
5945 | base = 0; | |
5946 | ||
5947 | if (x < 0) { | |
5948 | if (x + intel_crtc->cursor_width < 0) | |
5949 | base = 0; | |
5950 | ||
5951 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
5952 | x = -x; | |
5953 | } | |
5954 | pos |= x << CURSOR_X_SHIFT; | |
5955 | ||
5956 | if (y < 0) { | |
5957 | if (y + intel_crtc->cursor_height < 0) | |
5958 | base = 0; | |
5959 | ||
5960 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
5961 | y = -y; | |
5962 | } | |
5963 | pos |= y << CURSOR_Y_SHIFT; | |
5964 | ||
5965 | visible = base != 0; | |
560b85bb | 5966 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
5967 | return; |
5968 | ||
9db4a9c7 | 5969 | I915_WRITE(CURPOS(pipe), pos); |
560b85bb CW |
5970 | if (IS_845G(dev) || IS_I865G(dev)) |
5971 | i845_update_cursor(crtc, base); | |
5972 | else | |
5973 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
5974 | |
5975 | if (visible) | |
5976 | intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj); | |
5977 | } | |
5978 | ||
79e53945 | 5979 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 5980 | struct drm_file *file, |
79e53945 JB |
5981 | uint32_t handle, |
5982 | uint32_t width, uint32_t height) | |
5983 | { | |
5984 | struct drm_device *dev = crtc->dev; | |
5985 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5986 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 5987 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 5988 | uint32_t addr; |
3f8bc370 | 5989 | int ret; |
79e53945 | 5990 | |
28c97730 | 5991 | DRM_DEBUG_KMS("\n"); |
79e53945 JB |
5992 | |
5993 | /* if we want to turn off the cursor ignore width and height */ | |
5994 | if (!handle) { | |
28c97730 | 5995 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 5996 | addr = 0; |
05394f39 | 5997 | obj = NULL; |
5004417d | 5998 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 5999 | goto finish; |
79e53945 JB |
6000 | } |
6001 | ||
6002 | /* Currently we only support 64x64 cursors */ | |
6003 | if (width != 64 || height != 64) { | |
6004 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
6005 | return -EINVAL; | |
6006 | } | |
6007 | ||
05394f39 | 6008 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 6009 | if (&obj->base == NULL) |
79e53945 JB |
6010 | return -ENOENT; |
6011 | ||
05394f39 | 6012 | if (obj->base.size < width * height * 4) { |
79e53945 | 6013 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
6014 | ret = -ENOMEM; |
6015 | goto fail; | |
79e53945 JB |
6016 | } |
6017 | ||
71acb5eb | 6018 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 6019 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 6020 | if (!dev_priv->info->cursor_needs_physical) { |
d9e86c0e CW |
6021 | if (obj->tiling_mode) { |
6022 | DRM_ERROR("cursor cannot be tiled\n"); | |
6023 | ret = -EINVAL; | |
6024 | goto fail_locked; | |
6025 | } | |
6026 | ||
2da3b9b9 | 6027 | ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL); |
e7b526bb CW |
6028 | if (ret) { |
6029 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
2da3b9b9 | 6030 | goto fail_locked; |
e7b526bb CW |
6031 | } |
6032 | ||
d9e86c0e CW |
6033 | ret = i915_gem_object_put_fence(obj); |
6034 | if (ret) { | |
2da3b9b9 | 6035 | DRM_ERROR("failed to release fence for cursor"); |
d9e86c0e CW |
6036 | goto fail_unpin; |
6037 | } | |
6038 | ||
05394f39 | 6039 | addr = obj->gtt_offset; |
71acb5eb | 6040 | } else { |
6eeefaf3 | 6041 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 6042 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
6043 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
6044 | align); | |
71acb5eb DA |
6045 | if (ret) { |
6046 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 6047 | goto fail_locked; |
71acb5eb | 6048 | } |
05394f39 | 6049 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
6050 | } |
6051 | ||
a6c45cf0 | 6052 | if (IS_GEN2(dev)) |
14b60391 JB |
6053 | I915_WRITE(CURSIZE, (height << 12) | width); |
6054 | ||
3f8bc370 | 6055 | finish: |
3f8bc370 | 6056 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 6057 | if (dev_priv->info->cursor_needs_physical) { |
05394f39 | 6058 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
6059 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
6060 | } else | |
6061 | i915_gem_object_unpin(intel_crtc->cursor_bo); | |
05394f39 | 6062 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 6063 | } |
80824003 | 6064 | |
7f9872e0 | 6065 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
6066 | |
6067 | intel_crtc->cursor_addr = addr; | |
05394f39 | 6068 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
6069 | intel_crtc->cursor_width = width; |
6070 | intel_crtc->cursor_height = height; | |
6071 | ||
6b383a7f | 6072 | intel_crtc_update_cursor(crtc, true); |
3f8bc370 | 6073 | |
79e53945 | 6074 | return 0; |
e7b526bb | 6075 | fail_unpin: |
05394f39 | 6076 | i915_gem_object_unpin(obj); |
7f9872e0 | 6077 | fail_locked: |
34b8686e | 6078 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 6079 | fail: |
05394f39 | 6080 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 6081 | return ret; |
79e53945 JB |
6082 | } |
6083 | ||
6084 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
6085 | { | |
79e53945 | 6086 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 6087 | |
cda4b7d3 CW |
6088 | intel_crtc->cursor_x = x; |
6089 | intel_crtc->cursor_y = y; | |
652c393a | 6090 | |
6b383a7f | 6091 | intel_crtc_update_cursor(crtc, true); |
79e53945 JB |
6092 | |
6093 | return 0; | |
6094 | } | |
6095 | ||
6096 | /** Sets the color ramps on behalf of RandR */ | |
6097 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
6098 | u16 blue, int regno) | |
6099 | { | |
6100 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6101 | ||
6102 | intel_crtc->lut_r[regno] = red >> 8; | |
6103 | intel_crtc->lut_g[regno] = green >> 8; | |
6104 | intel_crtc->lut_b[regno] = blue >> 8; | |
6105 | } | |
6106 | ||
b8c00ac5 DA |
6107 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
6108 | u16 *blue, int regno) | |
6109 | { | |
6110 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6111 | ||
6112 | *red = intel_crtc->lut_r[regno] << 8; | |
6113 | *green = intel_crtc->lut_g[regno] << 8; | |
6114 | *blue = intel_crtc->lut_b[regno] << 8; | |
6115 | } | |
6116 | ||
79e53945 | 6117 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 6118 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 6119 | { |
7203425a | 6120 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 6121 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 6122 | |
7203425a | 6123 | for (i = start; i < end; i++) { |
79e53945 JB |
6124 | intel_crtc->lut_r[i] = red[i] >> 8; |
6125 | intel_crtc->lut_g[i] = green[i] >> 8; | |
6126 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
6127 | } | |
6128 | ||
6129 | intel_crtc_load_lut(crtc); | |
6130 | } | |
6131 | ||
6132 | /** | |
6133 | * Get a pipe with a simple mode set on it for doing load-based monitor | |
6134 | * detection. | |
6135 | * | |
6136 | * It will be up to the load-detect code to adjust the pipe as appropriate for | |
c751ce4f | 6137 | * its requirements. The pipe will be connected to no other encoders. |
79e53945 | 6138 | * |
c751ce4f | 6139 | * Currently this code will only succeed if there is a pipe with no encoders |
79e53945 JB |
6140 | * configured for it. In the future, it could choose to temporarily disable |
6141 | * some outputs to free up a pipe for its use. | |
6142 | * | |
6143 | * \return crtc, or NULL if no pipes are available. | |
6144 | */ | |
6145 | ||
6146 | /* VESA 640x480x72Hz mode to set on the pipe */ | |
6147 | static struct drm_display_mode load_detect_mode = { | |
6148 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
6149 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
6150 | }; | |
6151 | ||
d2dff872 CW |
6152 | static struct drm_framebuffer * |
6153 | intel_framebuffer_create(struct drm_device *dev, | |
6154 | struct drm_mode_fb_cmd *mode_cmd, | |
6155 | struct drm_i915_gem_object *obj) | |
6156 | { | |
6157 | struct intel_framebuffer *intel_fb; | |
6158 | int ret; | |
6159 | ||
6160 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
6161 | if (!intel_fb) { | |
6162 | drm_gem_object_unreference_unlocked(&obj->base); | |
6163 | return ERR_PTR(-ENOMEM); | |
6164 | } | |
6165 | ||
6166 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
6167 | if (ret) { | |
6168 | drm_gem_object_unreference_unlocked(&obj->base); | |
6169 | kfree(intel_fb); | |
6170 | return ERR_PTR(ret); | |
6171 | } | |
6172 | ||
6173 | return &intel_fb->base; | |
6174 | } | |
6175 | ||
6176 | static u32 | |
6177 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
6178 | { | |
6179 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
6180 | return ALIGN(pitch, 64); | |
6181 | } | |
6182 | ||
6183 | static u32 | |
6184 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
6185 | { | |
6186 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
6187 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
6188 | } | |
6189 | ||
6190 | static struct drm_framebuffer * | |
6191 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
6192 | struct drm_display_mode *mode, | |
6193 | int depth, int bpp) | |
6194 | { | |
6195 | struct drm_i915_gem_object *obj; | |
6196 | struct drm_mode_fb_cmd mode_cmd; | |
6197 | ||
6198 | obj = i915_gem_alloc_object(dev, | |
6199 | intel_framebuffer_size_for_mode(mode, bpp)); | |
6200 | if (obj == NULL) | |
6201 | return ERR_PTR(-ENOMEM); | |
6202 | ||
6203 | mode_cmd.width = mode->hdisplay; | |
6204 | mode_cmd.height = mode->vdisplay; | |
6205 | mode_cmd.depth = depth; | |
6206 | mode_cmd.bpp = bpp; | |
6207 | mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp); | |
6208 | ||
6209 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
6210 | } | |
6211 | ||
6212 | static struct drm_framebuffer * | |
6213 | mode_fits_in_fbdev(struct drm_device *dev, | |
6214 | struct drm_display_mode *mode) | |
6215 | { | |
6216 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6217 | struct drm_i915_gem_object *obj; | |
6218 | struct drm_framebuffer *fb; | |
6219 | ||
6220 | if (dev_priv->fbdev == NULL) | |
6221 | return NULL; | |
6222 | ||
6223 | obj = dev_priv->fbdev->ifb.obj; | |
6224 | if (obj == NULL) | |
6225 | return NULL; | |
6226 | ||
6227 | fb = &dev_priv->fbdev->ifb.base; | |
6228 | if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay, | |
6229 | fb->bits_per_pixel)) | |
6230 | return NULL; | |
6231 | ||
6232 | if (obj->base.size < mode->vdisplay * fb->pitch) | |
6233 | return NULL; | |
6234 | ||
6235 | return fb; | |
6236 | } | |
6237 | ||
7173188d CW |
6238 | bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, |
6239 | struct drm_connector *connector, | |
6240 | struct drm_display_mode *mode, | |
8261b191 | 6241 | struct intel_load_detect_pipe *old) |
79e53945 JB |
6242 | { |
6243 | struct intel_crtc *intel_crtc; | |
6244 | struct drm_crtc *possible_crtc; | |
4ef69c7a | 6245 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
6246 | struct drm_crtc *crtc = NULL; |
6247 | struct drm_device *dev = encoder->dev; | |
d2dff872 | 6248 | struct drm_framebuffer *old_fb; |
79e53945 JB |
6249 | int i = -1; |
6250 | ||
d2dff872 CW |
6251 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
6252 | connector->base.id, drm_get_connector_name(connector), | |
6253 | encoder->base.id, drm_get_encoder_name(encoder)); | |
6254 | ||
79e53945 JB |
6255 | /* |
6256 | * Algorithm gets a little messy: | |
7a5e4805 | 6257 | * |
79e53945 JB |
6258 | * - if the connector already has an assigned crtc, use it (but make |
6259 | * sure it's on first) | |
7a5e4805 | 6260 | * |
79e53945 JB |
6261 | * - try to find the first unused crtc that can drive this connector, |
6262 | * and use that if we find one | |
79e53945 JB |
6263 | */ |
6264 | ||
6265 | /* See if we already have a CRTC for this connector */ | |
6266 | if (encoder->crtc) { | |
6267 | crtc = encoder->crtc; | |
8261b191 | 6268 | |
79e53945 | 6269 | intel_crtc = to_intel_crtc(crtc); |
8261b191 CW |
6270 | old->dpms_mode = intel_crtc->dpms_mode; |
6271 | old->load_detect_temp = false; | |
6272 | ||
6273 | /* Make sure the crtc and connector are running */ | |
79e53945 | 6274 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { |
6492711d CW |
6275 | struct drm_encoder_helper_funcs *encoder_funcs; |
6276 | struct drm_crtc_helper_funcs *crtc_funcs; | |
6277 | ||
79e53945 JB |
6278 | crtc_funcs = crtc->helper_private; |
6279 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
6492711d CW |
6280 | |
6281 | encoder_funcs = encoder->helper_private; | |
79e53945 JB |
6282 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); |
6283 | } | |
8261b191 | 6284 | |
7173188d | 6285 | return true; |
79e53945 JB |
6286 | } |
6287 | ||
6288 | /* Find an unused one (if possible) */ | |
6289 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
6290 | i++; | |
6291 | if (!(encoder->possible_crtcs & (1 << i))) | |
6292 | continue; | |
6293 | if (!possible_crtc->enabled) { | |
6294 | crtc = possible_crtc; | |
6295 | break; | |
6296 | } | |
79e53945 JB |
6297 | } |
6298 | ||
6299 | /* | |
6300 | * If we didn't find an unused CRTC, don't use any. | |
6301 | */ | |
6302 | if (!crtc) { | |
7173188d CW |
6303 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
6304 | return false; | |
79e53945 JB |
6305 | } |
6306 | ||
6307 | encoder->crtc = crtc; | |
c1c43977 | 6308 | connector->encoder = encoder; |
79e53945 JB |
6309 | |
6310 | intel_crtc = to_intel_crtc(crtc); | |
8261b191 CW |
6311 | old->dpms_mode = intel_crtc->dpms_mode; |
6312 | old->load_detect_temp = true; | |
d2dff872 | 6313 | old->release_fb = NULL; |
79e53945 | 6314 | |
6492711d CW |
6315 | if (!mode) |
6316 | mode = &load_detect_mode; | |
79e53945 | 6317 | |
d2dff872 CW |
6318 | old_fb = crtc->fb; |
6319 | ||
6320 | /* We need a framebuffer large enough to accommodate all accesses | |
6321 | * that the plane may generate whilst we perform load detection. | |
6322 | * We can not rely on the fbcon either being present (we get called | |
6323 | * during its initialisation to detect all boot displays, or it may | |
6324 | * not even exist) or that it is large enough to satisfy the | |
6325 | * requested mode. | |
6326 | */ | |
6327 | crtc->fb = mode_fits_in_fbdev(dev, mode); | |
6328 | if (crtc->fb == NULL) { | |
6329 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); | |
6330 | crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); | |
6331 | old->release_fb = crtc->fb; | |
6332 | } else | |
6333 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
6334 | if (IS_ERR(crtc->fb)) { | |
6335 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); | |
6336 | crtc->fb = old_fb; | |
6337 | return false; | |
79e53945 | 6338 | } |
79e53945 | 6339 | |
d2dff872 | 6340 | if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) { |
6492711d | 6341 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
6342 | if (old->release_fb) |
6343 | old->release_fb->funcs->destroy(old->release_fb); | |
6344 | crtc->fb = old_fb; | |
6492711d | 6345 | return false; |
79e53945 | 6346 | } |
7173188d | 6347 | |
79e53945 | 6348 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 6349 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
79e53945 | 6350 | |
7173188d | 6351 | return true; |
79e53945 JB |
6352 | } |
6353 | ||
c1c43977 | 6354 | void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, |
8261b191 CW |
6355 | struct drm_connector *connector, |
6356 | struct intel_load_detect_pipe *old) | |
79e53945 | 6357 | { |
4ef69c7a | 6358 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
6359 | struct drm_device *dev = encoder->dev; |
6360 | struct drm_crtc *crtc = encoder->crtc; | |
6361 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
6362 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
6363 | ||
d2dff872 CW |
6364 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
6365 | connector->base.id, drm_get_connector_name(connector), | |
6366 | encoder->base.id, drm_get_encoder_name(encoder)); | |
6367 | ||
8261b191 | 6368 | if (old->load_detect_temp) { |
c1c43977 | 6369 | connector->encoder = NULL; |
79e53945 | 6370 | drm_helper_disable_unused_functions(dev); |
d2dff872 CW |
6371 | |
6372 | if (old->release_fb) | |
6373 | old->release_fb->funcs->destroy(old->release_fb); | |
6374 | ||
0622a53c | 6375 | return; |
79e53945 JB |
6376 | } |
6377 | ||
c751ce4f | 6378 | /* Switch crtc and encoder back off if necessary */ |
0622a53c CW |
6379 | if (old->dpms_mode != DRM_MODE_DPMS_ON) { |
6380 | encoder_funcs->dpms(encoder, old->dpms_mode); | |
8261b191 | 6381 | crtc_funcs->dpms(crtc, old->dpms_mode); |
79e53945 JB |
6382 | } |
6383 | } | |
6384 | ||
6385 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
6386 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) | |
6387 | { | |
6388 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6389 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6390 | int pipe = intel_crtc->pipe; | |
548f245b | 6391 | u32 dpll = I915_READ(DPLL(pipe)); |
79e53945 JB |
6392 | u32 fp; |
6393 | intel_clock_t clock; | |
6394 | ||
6395 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
39adb7a5 | 6396 | fp = I915_READ(FP0(pipe)); |
79e53945 | 6397 | else |
39adb7a5 | 6398 | fp = I915_READ(FP1(pipe)); |
79e53945 JB |
6399 | |
6400 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
6401 | if (IS_PINEVIEW(dev)) { |
6402 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
6403 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
6404 | } else { |
6405 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
6406 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
6407 | } | |
6408 | ||
a6c45cf0 | 6409 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
6410 | if (IS_PINEVIEW(dev)) |
6411 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
6412 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
6413 | else |
6414 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
6415 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
6416 | ||
6417 | switch (dpll & DPLL_MODE_MASK) { | |
6418 | case DPLLB_MODE_DAC_SERIAL: | |
6419 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
6420 | 5 : 10; | |
6421 | break; | |
6422 | case DPLLB_MODE_LVDS: | |
6423 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
6424 | 7 : 14; | |
6425 | break; | |
6426 | default: | |
28c97730 | 6427 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 JB |
6428 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
6429 | return 0; | |
6430 | } | |
6431 | ||
6432 | /* XXX: Handle the 100Mhz refclk */ | |
2177832f | 6433 | intel_clock(dev, 96000, &clock); |
79e53945 JB |
6434 | } else { |
6435 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
6436 | ||
6437 | if (is_lvds) { | |
6438 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
6439 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
6440 | clock.p2 = 14; | |
6441 | ||
6442 | if ((dpll & PLL_REF_INPUT_MASK) == | |
6443 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
6444 | /* XXX: might not be 66MHz */ | |
2177832f | 6445 | intel_clock(dev, 66000, &clock); |
79e53945 | 6446 | } else |
2177832f | 6447 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
6448 | } else { |
6449 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
6450 | clock.p1 = 2; | |
6451 | else { | |
6452 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
6453 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
6454 | } | |
6455 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
6456 | clock.p2 = 4; | |
6457 | else | |
6458 | clock.p2 = 2; | |
6459 | ||
2177832f | 6460 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
6461 | } |
6462 | } | |
6463 | ||
6464 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
6465 | * i830PllIsValid() because it relies on the xf86_config connector | |
6466 | * configuration being accurate, which it isn't necessarily. | |
6467 | */ | |
6468 | ||
6469 | return clock.dot; | |
6470 | } | |
6471 | ||
6472 | /** Returns the currently programmed mode of the given pipe. */ | |
6473 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
6474 | struct drm_crtc *crtc) | |
6475 | { | |
548f245b | 6476 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
6477 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6478 | int pipe = intel_crtc->pipe; | |
6479 | struct drm_display_mode *mode; | |
548f245b JB |
6480 | int htot = I915_READ(HTOTAL(pipe)); |
6481 | int hsync = I915_READ(HSYNC(pipe)); | |
6482 | int vtot = I915_READ(VTOTAL(pipe)); | |
6483 | int vsync = I915_READ(VSYNC(pipe)); | |
79e53945 JB |
6484 | |
6485 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
6486 | if (!mode) | |
6487 | return NULL; | |
6488 | ||
6489 | mode->clock = intel_crtc_clock_get(dev, crtc); | |
6490 | mode->hdisplay = (htot & 0xffff) + 1; | |
6491 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
6492 | mode->hsync_start = (hsync & 0xffff) + 1; | |
6493 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
6494 | mode->vdisplay = (vtot & 0xffff) + 1; | |
6495 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
6496 | mode->vsync_start = (vsync & 0xffff) + 1; | |
6497 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
6498 | ||
6499 | drm_mode_set_name(mode); | |
6500 | drm_mode_set_crtcinfo(mode, 0); | |
6501 | ||
6502 | return mode; | |
6503 | } | |
6504 | ||
652c393a JB |
6505 | #define GPU_IDLE_TIMEOUT 500 /* ms */ |
6506 | ||
6507 | /* When this timer fires, we've been idle for awhile */ | |
6508 | static void intel_gpu_idle_timer(unsigned long arg) | |
6509 | { | |
6510 | struct drm_device *dev = (struct drm_device *)arg; | |
6511 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6512 | ||
ff7ea4c0 CW |
6513 | if (!list_empty(&dev_priv->mm.active_list)) { |
6514 | /* Still processing requests, so just re-arm the timer. */ | |
6515 | mod_timer(&dev_priv->idle_timer, jiffies + | |
6516 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
6517 | return; | |
6518 | } | |
652c393a | 6519 | |
ff7ea4c0 | 6520 | dev_priv->busy = false; |
01dfba93 | 6521 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
6522 | } |
6523 | ||
652c393a JB |
6524 | #define CRTC_IDLE_TIMEOUT 1000 /* ms */ |
6525 | ||
6526 | static void intel_crtc_idle_timer(unsigned long arg) | |
6527 | { | |
6528 | struct intel_crtc *intel_crtc = (struct intel_crtc *)arg; | |
6529 | struct drm_crtc *crtc = &intel_crtc->base; | |
6530 | drm_i915_private_t *dev_priv = crtc->dev->dev_private; | |
ff7ea4c0 | 6531 | struct intel_framebuffer *intel_fb; |
652c393a | 6532 | |
ff7ea4c0 CW |
6533 | intel_fb = to_intel_framebuffer(crtc->fb); |
6534 | if (intel_fb && intel_fb->obj->active) { | |
6535 | /* The framebuffer is still being accessed by the GPU. */ | |
6536 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
6537 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
6538 | return; | |
6539 | } | |
652c393a | 6540 | |
ff7ea4c0 | 6541 | intel_crtc->busy = false; |
01dfba93 | 6542 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
6543 | } |
6544 | ||
3dec0095 | 6545 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
6546 | { |
6547 | struct drm_device *dev = crtc->dev; | |
6548 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6549 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6550 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
6551 | int dpll_reg = DPLL(pipe); |
6552 | int dpll; | |
652c393a | 6553 | |
bad720ff | 6554 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
6555 | return; |
6556 | ||
6557 | if (!dev_priv->lvds_downclock_avail) | |
6558 | return; | |
6559 | ||
dbdc6479 | 6560 | dpll = I915_READ(dpll_reg); |
652c393a | 6561 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 6562 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a JB |
6563 | |
6564 | /* Unlock panel regs */ | |
dbdc6479 JB |
6565 | I915_WRITE(PP_CONTROL, |
6566 | I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); | |
652c393a JB |
6567 | |
6568 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
6569 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 6570 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 6571 | |
652c393a JB |
6572 | dpll = I915_READ(dpll_reg); |
6573 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 6574 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a JB |
6575 | |
6576 | /* ...and lock them again */ | |
6577 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); | |
6578 | } | |
6579 | ||
6580 | /* Schedule downclock */ | |
3dec0095 DV |
6581 | mod_timer(&intel_crtc->idle_timer, jiffies + |
6582 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
652c393a JB |
6583 | } |
6584 | ||
6585 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
6586 | { | |
6587 | struct drm_device *dev = crtc->dev; | |
6588 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6589 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6590 | int pipe = intel_crtc->pipe; | |
9db4a9c7 | 6591 | int dpll_reg = DPLL(pipe); |
652c393a JB |
6592 | int dpll = I915_READ(dpll_reg); |
6593 | ||
bad720ff | 6594 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
6595 | return; |
6596 | ||
6597 | if (!dev_priv->lvds_downclock_avail) | |
6598 | return; | |
6599 | ||
6600 | /* | |
6601 | * Since this is called by a timer, we should never get here in | |
6602 | * the manual case. | |
6603 | */ | |
6604 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
44d98a61 | 6605 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a JB |
6606 | |
6607 | /* Unlock panel regs */ | |
4a655f04 JB |
6608 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | |
6609 | PANEL_UNLOCK_REGS); | |
652c393a JB |
6610 | |
6611 | dpll |= DISPLAY_RATE_SELECT_FPA1; | |
6612 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 6613 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
6614 | dpll = I915_READ(dpll_reg); |
6615 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 6616 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
6617 | |
6618 | /* ...and lock them again */ | |
6619 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); | |
6620 | } | |
6621 | ||
6622 | } | |
6623 | ||
6624 | /** | |
6625 | * intel_idle_update - adjust clocks for idleness | |
6626 | * @work: work struct | |
6627 | * | |
6628 | * Either the GPU or display (or both) went idle. Check the busy status | |
6629 | * here and adjust the CRTC and GPU clocks as necessary. | |
6630 | */ | |
6631 | static void intel_idle_update(struct work_struct *work) | |
6632 | { | |
6633 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
6634 | idle_work); | |
6635 | struct drm_device *dev = dev_priv->dev; | |
6636 | struct drm_crtc *crtc; | |
6637 | struct intel_crtc *intel_crtc; | |
6638 | ||
6639 | if (!i915_powersave) | |
6640 | return; | |
6641 | ||
6642 | mutex_lock(&dev->struct_mutex); | |
6643 | ||
7648fa99 JB |
6644 | i915_update_gfx_val(dev_priv); |
6645 | ||
652c393a JB |
6646 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
6647 | /* Skip inactive CRTCs */ | |
6648 | if (!crtc->fb) | |
6649 | continue; | |
6650 | ||
6651 | intel_crtc = to_intel_crtc(crtc); | |
6652 | if (!intel_crtc->busy) | |
6653 | intel_decrease_pllclock(crtc); | |
6654 | } | |
6655 | ||
45ac22c8 | 6656 | |
652c393a JB |
6657 | mutex_unlock(&dev->struct_mutex); |
6658 | } | |
6659 | ||
6660 | /** | |
6661 | * intel_mark_busy - mark the GPU and possibly the display busy | |
6662 | * @dev: drm device | |
6663 | * @obj: object we're operating on | |
6664 | * | |
6665 | * Callers can use this function to indicate that the GPU is busy processing | |
6666 | * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout | |
6667 | * buffer), we'll also mark the display as busy, so we know to increase its | |
6668 | * clock frequency. | |
6669 | */ | |
05394f39 | 6670 | void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj) |
652c393a JB |
6671 | { |
6672 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6673 | struct drm_crtc *crtc = NULL; | |
6674 | struct intel_framebuffer *intel_fb; | |
6675 | struct intel_crtc *intel_crtc; | |
6676 | ||
5e17ee74 ZW |
6677 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6678 | return; | |
6679 | ||
18b2190c | 6680 | if (!dev_priv->busy) |
28cf798f | 6681 | dev_priv->busy = true; |
18b2190c | 6682 | else |
28cf798f CW |
6683 | mod_timer(&dev_priv->idle_timer, jiffies + |
6684 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
652c393a JB |
6685 | |
6686 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
6687 | if (!crtc->fb) | |
6688 | continue; | |
6689 | ||
6690 | intel_crtc = to_intel_crtc(crtc); | |
6691 | intel_fb = to_intel_framebuffer(crtc->fb); | |
6692 | if (intel_fb->obj == obj) { | |
6693 | if (!intel_crtc->busy) { | |
6694 | /* Non-busy -> busy, upclock */ | |
3dec0095 | 6695 | intel_increase_pllclock(crtc); |
652c393a JB |
6696 | intel_crtc->busy = true; |
6697 | } else { | |
6698 | /* Busy -> busy, put off timer */ | |
6699 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
6700 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
6701 | } | |
6702 | } | |
6703 | } | |
6704 | } | |
6705 | ||
79e53945 JB |
6706 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
6707 | { | |
6708 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
6709 | struct drm_device *dev = crtc->dev; |
6710 | struct intel_unpin_work *work; | |
6711 | unsigned long flags; | |
6712 | ||
6713 | spin_lock_irqsave(&dev->event_lock, flags); | |
6714 | work = intel_crtc->unpin_work; | |
6715 | intel_crtc->unpin_work = NULL; | |
6716 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6717 | ||
6718 | if (work) { | |
6719 | cancel_work_sync(&work->work); | |
6720 | kfree(work); | |
6721 | } | |
79e53945 JB |
6722 | |
6723 | drm_crtc_cleanup(crtc); | |
67e77c5a | 6724 | |
79e53945 JB |
6725 | kfree(intel_crtc); |
6726 | } | |
6727 | ||
6b95a207 KH |
6728 | static void intel_unpin_work_fn(struct work_struct *__work) |
6729 | { | |
6730 | struct intel_unpin_work *work = | |
6731 | container_of(__work, struct intel_unpin_work, work); | |
6732 | ||
6733 | mutex_lock(&work->dev->struct_mutex); | |
b1b87f6b | 6734 | i915_gem_object_unpin(work->old_fb_obj); |
05394f39 CW |
6735 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
6736 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 6737 | |
7782de3b | 6738 | intel_update_fbc(work->dev); |
6b95a207 KH |
6739 | mutex_unlock(&work->dev->struct_mutex); |
6740 | kfree(work); | |
6741 | } | |
6742 | ||
1afe3e9d | 6743 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 6744 | struct drm_crtc *crtc) |
6b95a207 KH |
6745 | { |
6746 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
6747 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6748 | struct intel_unpin_work *work; | |
05394f39 | 6749 | struct drm_i915_gem_object *obj; |
6b95a207 | 6750 | struct drm_pending_vblank_event *e; |
49b14a5c | 6751 | struct timeval tnow, tvbl; |
6b95a207 KH |
6752 | unsigned long flags; |
6753 | ||
6754 | /* Ignore early vblank irqs */ | |
6755 | if (intel_crtc == NULL) | |
6756 | return; | |
6757 | ||
49b14a5c MK |
6758 | do_gettimeofday(&tnow); |
6759 | ||
6b95a207 KH |
6760 | spin_lock_irqsave(&dev->event_lock, flags); |
6761 | work = intel_crtc->unpin_work; | |
6762 | if (work == NULL || !work->pending) { | |
6763 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6764 | return; | |
6765 | } | |
6766 | ||
6767 | intel_crtc->unpin_work = NULL; | |
6b95a207 KH |
6768 | |
6769 | if (work->event) { | |
6770 | e = work->event; | |
49b14a5c | 6771 | e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl); |
0af7e4df MK |
6772 | |
6773 | /* Called before vblank count and timestamps have | |
6774 | * been updated for the vblank interval of flip | |
6775 | * completion? Need to increment vblank count and | |
6776 | * add one videorefresh duration to returned timestamp | |
49b14a5c MK |
6777 | * to account for this. We assume this happened if we |
6778 | * get called over 0.9 frame durations after the last | |
6779 | * timestamped vblank. | |
6780 | * | |
6781 | * This calculation can not be used with vrefresh rates | |
6782 | * below 5Hz (10Hz to be on the safe side) without | |
6783 | * promoting to 64 integers. | |
0af7e4df | 6784 | */ |
49b14a5c MK |
6785 | if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) > |
6786 | 9 * crtc->framedur_ns) { | |
0af7e4df | 6787 | e->event.sequence++; |
49b14a5c MK |
6788 | tvbl = ns_to_timeval(timeval_to_ns(&tvbl) + |
6789 | crtc->framedur_ns); | |
0af7e4df MK |
6790 | } |
6791 | ||
49b14a5c MK |
6792 | e->event.tv_sec = tvbl.tv_sec; |
6793 | e->event.tv_usec = tvbl.tv_usec; | |
0af7e4df | 6794 | |
6b95a207 KH |
6795 | list_add_tail(&e->base.link, |
6796 | &e->base.file_priv->event_list); | |
6797 | wake_up_interruptible(&e->base.file_priv->event_wait); | |
6798 | } | |
6799 | ||
0af7e4df MK |
6800 | drm_vblank_put(dev, intel_crtc->pipe); |
6801 | ||
6b95a207 KH |
6802 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6803 | ||
05394f39 | 6804 | obj = work->old_fb_obj; |
d9e86c0e | 6805 | |
e59f2bac | 6806 | atomic_clear_mask(1 << intel_crtc->plane, |
05394f39 CW |
6807 | &obj->pending_flip.counter); |
6808 | if (atomic_read(&obj->pending_flip) == 0) | |
f787a5f5 | 6809 | wake_up(&dev_priv->pending_flip_queue); |
d9e86c0e | 6810 | |
6b95a207 | 6811 | schedule_work(&work->work); |
e5510fac JB |
6812 | |
6813 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
6814 | } |
6815 | ||
1afe3e9d JB |
6816 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
6817 | { | |
6818 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6819 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
6820 | ||
49b14a5c | 6821 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
6822 | } |
6823 | ||
6824 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
6825 | { | |
6826 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6827 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
6828 | ||
49b14a5c | 6829 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
6830 | } |
6831 | ||
6b95a207 KH |
6832 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
6833 | { | |
6834 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6835 | struct intel_crtc *intel_crtc = | |
6836 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
6837 | unsigned long flags; | |
6838 | ||
6839 | spin_lock_irqsave(&dev->event_lock, flags); | |
de3f440f | 6840 | if (intel_crtc->unpin_work) { |
4e5359cd SF |
6841 | if ((++intel_crtc->unpin_work->pending) > 1) |
6842 | DRM_ERROR("Prepared flip multiple times\n"); | |
de3f440f JB |
6843 | } else { |
6844 | DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); | |
6845 | } | |
6b95a207 KH |
6846 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6847 | } | |
6848 | ||
8c9f3aaf JB |
6849 | static int intel_gen2_queue_flip(struct drm_device *dev, |
6850 | struct drm_crtc *crtc, | |
6851 | struct drm_framebuffer *fb, | |
6852 | struct drm_i915_gem_object *obj) | |
6853 | { | |
6854 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6855 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6856 | unsigned long offset; | |
6857 | u32 flip_mask; | |
6858 | int ret; | |
6859 | ||
6860 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
6861 | if (ret) | |
6862 | goto out; | |
6863 | ||
6864 | /* Offset into the new buffer for cases of shared fbs between CRTCs */ | |
6865 | offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8; | |
6866 | ||
6867 | ret = BEGIN_LP_RING(6); | |
6868 | if (ret) | |
6869 | goto out; | |
6870 | ||
6871 | /* Can't queue multiple flips, so wait for the previous | |
6872 | * one to finish before executing the next. | |
6873 | */ | |
6874 | if (intel_crtc->plane) | |
6875 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
6876 | else | |
6877 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6878 | OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); | |
6879 | OUT_RING(MI_NOOP); | |
6880 | OUT_RING(MI_DISPLAY_FLIP | | |
6881 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
6882 | OUT_RING(fb->pitch); | |
6883 | OUT_RING(obj->gtt_offset + offset); | |
6884 | OUT_RING(MI_NOOP); | |
6885 | ADVANCE_LP_RING(); | |
6886 | out: | |
6887 | return ret; | |
6888 | } | |
6889 | ||
6890 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
6891 | struct drm_crtc *crtc, | |
6892 | struct drm_framebuffer *fb, | |
6893 | struct drm_i915_gem_object *obj) | |
6894 | { | |
6895 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6896 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6897 | unsigned long offset; | |
6898 | u32 flip_mask; | |
6899 | int ret; | |
6900 | ||
6901 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
6902 | if (ret) | |
6903 | goto out; | |
6904 | ||
6905 | /* Offset into the new buffer for cases of shared fbs between CRTCs */ | |
6906 | offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8; | |
6907 | ||
6908 | ret = BEGIN_LP_RING(6); | |
6909 | if (ret) | |
6910 | goto out; | |
6911 | ||
6912 | if (intel_crtc->plane) | |
6913 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
6914 | else | |
6915 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6916 | OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); | |
6917 | OUT_RING(MI_NOOP); | |
6918 | OUT_RING(MI_DISPLAY_FLIP_I915 | | |
6919 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
6920 | OUT_RING(fb->pitch); | |
6921 | OUT_RING(obj->gtt_offset + offset); | |
6922 | OUT_RING(MI_NOOP); | |
6923 | ||
6924 | ADVANCE_LP_RING(); | |
6925 | out: | |
6926 | return ret; | |
6927 | } | |
6928 | ||
6929 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
6930 | struct drm_crtc *crtc, | |
6931 | struct drm_framebuffer *fb, | |
6932 | struct drm_i915_gem_object *obj) | |
6933 | { | |
6934 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6935 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6936 | uint32_t pf, pipesrc; | |
6937 | int ret; | |
6938 | ||
6939 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
6940 | if (ret) | |
6941 | goto out; | |
6942 | ||
6943 | ret = BEGIN_LP_RING(4); | |
6944 | if (ret) | |
6945 | goto out; | |
6946 | ||
6947 | /* i965+ uses the linear or tiled offsets from the | |
6948 | * Display Registers (which do not change across a page-flip) | |
6949 | * so we need only reprogram the base address. | |
6950 | */ | |
6951 | OUT_RING(MI_DISPLAY_FLIP | | |
6952 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
6953 | OUT_RING(fb->pitch); | |
6954 | OUT_RING(obj->gtt_offset | obj->tiling_mode); | |
6955 | ||
6956 | /* XXX Enabling the panel-fitter across page-flip is so far | |
6957 | * untested on non-native modes, so ignore it for now. | |
6958 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
6959 | */ | |
6960 | pf = 0; | |
6961 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6962 | OUT_RING(pf | pipesrc); | |
6963 | ADVANCE_LP_RING(); | |
6964 | out: | |
6965 | return ret; | |
6966 | } | |
6967 | ||
6968 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
6969 | struct drm_crtc *crtc, | |
6970 | struct drm_framebuffer *fb, | |
6971 | struct drm_i915_gem_object *obj) | |
6972 | { | |
6973 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6974 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6975 | uint32_t pf, pipesrc; | |
6976 | int ret; | |
6977 | ||
6978 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
6979 | if (ret) | |
6980 | goto out; | |
6981 | ||
6982 | ret = BEGIN_LP_RING(4); | |
6983 | if (ret) | |
6984 | goto out; | |
6985 | ||
6986 | OUT_RING(MI_DISPLAY_FLIP | | |
6987 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
6988 | OUT_RING(fb->pitch | obj->tiling_mode); | |
6989 | OUT_RING(obj->gtt_offset); | |
6990 | ||
6991 | pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
6992 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6993 | OUT_RING(pf | pipesrc); | |
6994 | ADVANCE_LP_RING(); | |
6995 | out: | |
6996 | return ret; | |
6997 | } | |
6998 | ||
7c9017e5 JB |
6999 | /* |
7000 | * On gen7 we currently use the blit ring because (in early silicon at least) | |
7001 | * the render ring doesn't give us interrpts for page flip completion, which | |
7002 | * means clients will hang after the first flip is queued. Fortunately the | |
7003 | * blit ring generates interrupts properly, so use it instead. | |
7004 | */ | |
7005 | static int intel_gen7_queue_flip(struct drm_device *dev, | |
7006 | struct drm_crtc *crtc, | |
7007 | struct drm_framebuffer *fb, | |
7008 | struct drm_i915_gem_object *obj) | |
7009 | { | |
7010 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7011 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7012 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; | |
7013 | int ret; | |
7014 | ||
7015 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
7016 | if (ret) | |
7017 | goto out; | |
7018 | ||
7019 | ret = intel_ring_begin(ring, 4); | |
7020 | if (ret) | |
7021 | goto out; | |
7022 | ||
7023 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19)); | |
7024 | intel_ring_emit(ring, (fb->pitch | obj->tiling_mode)); | |
7025 | intel_ring_emit(ring, (obj->gtt_offset)); | |
7026 | intel_ring_emit(ring, (MI_NOOP)); | |
7027 | intel_ring_advance(ring); | |
7028 | out: | |
7029 | return ret; | |
7030 | } | |
7031 | ||
8c9f3aaf JB |
7032 | static int intel_default_queue_flip(struct drm_device *dev, |
7033 | struct drm_crtc *crtc, | |
7034 | struct drm_framebuffer *fb, | |
7035 | struct drm_i915_gem_object *obj) | |
7036 | { | |
7037 | return -ENODEV; | |
7038 | } | |
7039 | ||
6b95a207 KH |
7040 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
7041 | struct drm_framebuffer *fb, | |
7042 | struct drm_pending_vblank_event *event) | |
7043 | { | |
7044 | struct drm_device *dev = crtc->dev; | |
7045 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7046 | struct intel_framebuffer *intel_fb; | |
05394f39 | 7047 | struct drm_i915_gem_object *obj; |
6b95a207 KH |
7048 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7049 | struct intel_unpin_work *work; | |
8c9f3aaf | 7050 | unsigned long flags; |
52e68630 | 7051 | int ret; |
6b95a207 KH |
7052 | |
7053 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
7054 | if (work == NULL) | |
7055 | return -ENOMEM; | |
7056 | ||
6b95a207 KH |
7057 | work->event = event; |
7058 | work->dev = crtc->dev; | |
7059 | intel_fb = to_intel_framebuffer(crtc->fb); | |
b1b87f6b | 7060 | work->old_fb_obj = intel_fb->obj; |
6b95a207 KH |
7061 | INIT_WORK(&work->work, intel_unpin_work_fn); |
7062 | ||
7063 | /* We borrow the event spin lock for protecting unpin_work */ | |
7064 | spin_lock_irqsave(&dev->event_lock, flags); | |
7065 | if (intel_crtc->unpin_work) { | |
7066 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7067 | kfree(work); | |
468f0b44 CW |
7068 | |
7069 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
7070 | return -EBUSY; |
7071 | } | |
7072 | intel_crtc->unpin_work = work; | |
7073 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7074 | ||
7075 | intel_fb = to_intel_framebuffer(fb); | |
7076 | obj = intel_fb->obj; | |
7077 | ||
468f0b44 | 7078 | mutex_lock(&dev->struct_mutex); |
6b95a207 | 7079 | |
75dfca80 | 7080 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
7081 | drm_gem_object_reference(&work->old_fb_obj->base); |
7082 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
7083 | |
7084 | crtc->fb = fb; | |
96b099fd CW |
7085 | |
7086 | ret = drm_vblank_get(dev, intel_crtc->pipe); | |
7087 | if (ret) | |
7088 | goto cleanup_objs; | |
7089 | ||
e1f99ce6 | 7090 | work->pending_flip_obj = obj; |
e1f99ce6 | 7091 | |
4e5359cd SF |
7092 | work->enable_stall_check = true; |
7093 | ||
e1f99ce6 CW |
7094 | /* Block clients from rendering to the new back buffer until |
7095 | * the flip occurs and the object is no longer visible. | |
7096 | */ | |
05394f39 | 7097 | atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); |
e1f99ce6 | 7098 | |
8c9f3aaf JB |
7099 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); |
7100 | if (ret) | |
7101 | goto cleanup_pending; | |
6b95a207 | 7102 | |
7782de3b | 7103 | intel_disable_fbc(dev); |
6b95a207 KH |
7104 | mutex_unlock(&dev->struct_mutex); |
7105 | ||
e5510fac JB |
7106 | trace_i915_flip_request(intel_crtc->plane, obj); |
7107 | ||
6b95a207 | 7108 | return 0; |
96b099fd | 7109 | |
8c9f3aaf JB |
7110 | cleanup_pending: |
7111 | atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); | |
96b099fd | 7112 | cleanup_objs: |
05394f39 CW |
7113 | drm_gem_object_unreference(&work->old_fb_obj->base); |
7114 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
7115 | mutex_unlock(&dev->struct_mutex); |
7116 | ||
7117 | spin_lock_irqsave(&dev->event_lock, flags); | |
7118 | intel_crtc->unpin_work = NULL; | |
7119 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7120 | ||
7121 | kfree(work); | |
7122 | ||
7123 | return ret; | |
6b95a207 KH |
7124 | } |
7125 | ||
47f1c6c9 CW |
7126 | static void intel_sanitize_modesetting(struct drm_device *dev, |
7127 | int pipe, int plane) | |
7128 | { | |
7129 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7130 | u32 reg, val; | |
7131 | ||
7132 | if (HAS_PCH_SPLIT(dev)) | |
7133 | return; | |
7134 | ||
7135 | /* Who knows what state these registers were left in by the BIOS or | |
7136 | * grub? | |
7137 | * | |
7138 | * If we leave the registers in a conflicting state (e.g. with the | |
7139 | * display plane reading from the other pipe than the one we intend | |
7140 | * to use) then when we attempt to teardown the active mode, we will | |
7141 | * not disable the pipes and planes in the correct order -- leaving | |
7142 | * a plane reading from a disabled pipe and possibly leading to | |
7143 | * undefined behaviour. | |
7144 | */ | |
7145 | ||
7146 | reg = DSPCNTR(plane); | |
7147 | val = I915_READ(reg); | |
7148 | ||
7149 | if ((val & DISPLAY_PLANE_ENABLE) == 0) | |
7150 | return; | |
7151 | if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe) | |
7152 | return; | |
7153 | ||
7154 | /* This display plane is active and attached to the other CPU pipe. */ | |
7155 | pipe = !pipe; | |
7156 | ||
7157 | /* Disable the plane and wait for it to stop reading from the pipe. */ | |
b24e7179 JB |
7158 | intel_disable_plane(dev_priv, plane, pipe); |
7159 | intel_disable_pipe(dev_priv, pipe); | |
47f1c6c9 | 7160 | } |
79e53945 | 7161 | |
f6e5b160 CW |
7162 | static void intel_crtc_reset(struct drm_crtc *crtc) |
7163 | { | |
7164 | struct drm_device *dev = crtc->dev; | |
7165 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7166 | ||
7167 | /* Reset flags back to the 'unknown' status so that they | |
7168 | * will be correctly set on the initial modeset. | |
7169 | */ | |
7170 | intel_crtc->dpms_mode = -1; | |
7171 | ||
7172 | /* We need to fix up any BIOS configuration that conflicts with | |
7173 | * our expectations. | |
7174 | */ | |
7175 | intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane); | |
7176 | } | |
7177 | ||
7178 | static struct drm_crtc_helper_funcs intel_helper_funcs = { | |
7179 | .dpms = intel_crtc_dpms, | |
7180 | .mode_fixup = intel_crtc_mode_fixup, | |
7181 | .mode_set = intel_crtc_mode_set, | |
7182 | .mode_set_base = intel_pipe_set_base, | |
7183 | .mode_set_base_atomic = intel_pipe_set_base_atomic, | |
7184 | .load_lut = intel_crtc_load_lut, | |
7185 | .disable = intel_crtc_disable, | |
7186 | }; | |
7187 | ||
7188 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
7189 | .reset = intel_crtc_reset, | |
7190 | .cursor_set = intel_crtc_cursor_set, | |
7191 | .cursor_move = intel_crtc_cursor_move, | |
7192 | .gamma_set = intel_crtc_gamma_set, | |
7193 | .set_config = drm_crtc_helper_set_config, | |
7194 | .destroy = intel_crtc_destroy, | |
7195 | .page_flip = intel_crtc_page_flip, | |
7196 | }; | |
7197 | ||
b358d0a6 | 7198 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 7199 | { |
22fd0fab | 7200 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
7201 | struct intel_crtc *intel_crtc; |
7202 | int i; | |
7203 | ||
7204 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
7205 | if (intel_crtc == NULL) | |
7206 | return; | |
7207 | ||
7208 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
7209 | ||
7210 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
7211 | for (i = 0; i < 256; i++) { |
7212 | intel_crtc->lut_r[i] = i; | |
7213 | intel_crtc->lut_g[i] = i; | |
7214 | intel_crtc->lut_b[i] = i; | |
7215 | } | |
7216 | ||
80824003 JB |
7217 | /* Swap pipes & planes for FBC on pre-965 */ |
7218 | intel_crtc->pipe = pipe; | |
7219 | intel_crtc->plane = pipe; | |
e2e767ab | 7220 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
28c97730 | 7221 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 7222 | intel_crtc->plane = !pipe; |
80824003 JB |
7223 | } |
7224 | ||
22fd0fab JB |
7225 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
7226 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
7227 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
7228 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
7229 | ||
5d1d0cc8 | 7230 | intel_crtc_reset(&intel_crtc->base); |
04dbff52 | 7231 | intel_crtc->active = true; /* force the pipe off on setup_init_config */ |
5a354204 | 7232 | intel_crtc->bpp = 24; /* default for pre-Ironlake */ |
7e7d76c3 JB |
7233 | |
7234 | if (HAS_PCH_SPLIT(dev)) { | |
7235 | intel_helper_funcs.prepare = ironlake_crtc_prepare; | |
7236 | intel_helper_funcs.commit = ironlake_crtc_commit; | |
7237 | } else { | |
7238 | intel_helper_funcs.prepare = i9xx_crtc_prepare; | |
7239 | intel_helper_funcs.commit = i9xx_crtc_commit; | |
7240 | } | |
7241 | ||
79e53945 JB |
7242 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
7243 | ||
652c393a JB |
7244 | intel_crtc->busy = false; |
7245 | ||
7246 | setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer, | |
7247 | (unsigned long)intel_crtc); | |
79e53945 JB |
7248 | } |
7249 | ||
08d7b3d1 | 7250 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 7251 | struct drm_file *file) |
08d7b3d1 CW |
7252 | { |
7253 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7254 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; | |
c05422d5 DV |
7255 | struct drm_mode_object *drmmode_obj; |
7256 | struct intel_crtc *crtc; | |
08d7b3d1 CW |
7257 | |
7258 | if (!dev_priv) { | |
7259 | DRM_ERROR("called with no initialization\n"); | |
7260 | return -EINVAL; | |
7261 | } | |
7262 | ||
c05422d5 DV |
7263 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
7264 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 7265 | |
c05422d5 | 7266 | if (!drmmode_obj) { |
08d7b3d1 CW |
7267 | DRM_ERROR("no such CRTC id\n"); |
7268 | return -EINVAL; | |
7269 | } | |
7270 | ||
c05422d5 DV |
7271 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
7272 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 7273 | |
c05422d5 | 7274 | return 0; |
08d7b3d1 CW |
7275 | } |
7276 | ||
c5e4df33 | 7277 | static int intel_encoder_clones(struct drm_device *dev, int type_mask) |
79e53945 | 7278 | { |
4ef69c7a | 7279 | struct intel_encoder *encoder; |
79e53945 | 7280 | int index_mask = 0; |
79e53945 JB |
7281 | int entry = 0; |
7282 | ||
4ef69c7a CW |
7283 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
7284 | if (type_mask & encoder->clone_mask) | |
79e53945 JB |
7285 | index_mask |= (1 << entry); |
7286 | entry++; | |
7287 | } | |
4ef69c7a | 7288 | |
79e53945 JB |
7289 | return index_mask; |
7290 | } | |
7291 | ||
4d302442 CW |
7292 | static bool has_edp_a(struct drm_device *dev) |
7293 | { | |
7294 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7295 | ||
7296 | if (!IS_MOBILE(dev)) | |
7297 | return false; | |
7298 | ||
7299 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
7300 | return false; | |
7301 | ||
7302 | if (IS_GEN5(dev) && | |
7303 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) | |
7304 | return false; | |
7305 | ||
7306 | return true; | |
7307 | } | |
7308 | ||
79e53945 JB |
7309 | static void intel_setup_outputs(struct drm_device *dev) |
7310 | { | |
725e30ad | 7311 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 7312 | struct intel_encoder *encoder; |
cb0953d7 | 7313 | bool dpd_is_edp = false; |
c5d1b51d | 7314 | bool has_lvds = false; |
79e53945 | 7315 | |
541998a1 | 7316 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
c5d1b51d CW |
7317 | has_lvds = intel_lvds_init(dev); |
7318 | if (!has_lvds && !HAS_PCH_SPLIT(dev)) { | |
7319 | /* disable the panel fitter on everything but LVDS */ | |
7320 | I915_WRITE(PFIT_CONTROL, 0); | |
7321 | } | |
79e53945 | 7322 | |
bad720ff | 7323 | if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 7324 | dpd_is_edp = intel_dpd_is_edp(dev); |
30ad48b7 | 7325 | |
4d302442 | 7326 | if (has_edp_a(dev)) |
32f9d658 ZW |
7327 | intel_dp_init(dev, DP_A); |
7328 | ||
cb0953d7 AJ |
7329 | if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
7330 | intel_dp_init(dev, PCH_DP_D); | |
7331 | } | |
7332 | ||
7333 | intel_crt_init(dev); | |
7334 | ||
7335 | if (HAS_PCH_SPLIT(dev)) { | |
7336 | int found; | |
7337 | ||
30ad48b7 | 7338 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
461ed3ca ZY |
7339 | /* PCH SDVOB multiplex with HDMIB */ |
7340 | found = intel_sdvo_init(dev, PCH_SDVOB); | |
30ad48b7 ZW |
7341 | if (!found) |
7342 | intel_hdmi_init(dev, HDMIB); | |
5eb08b69 ZW |
7343 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
7344 | intel_dp_init(dev, PCH_DP_B); | |
30ad48b7 ZW |
7345 | } |
7346 | ||
7347 | if (I915_READ(HDMIC) & PORT_DETECTED) | |
7348 | intel_hdmi_init(dev, HDMIC); | |
7349 | ||
7350 | if (I915_READ(HDMID) & PORT_DETECTED) | |
7351 | intel_hdmi_init(dev, HDMID); | |
7352 | ||
5eb08b69 ZW |
7353 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
7354 | intel_dp_init(dev, PCH_DP_C); | |
7355 | ||
cb0953d7 | 7356 | if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
5eb08b69 ZW |
7357 | intel_dp_init(dev, PCH_DP_D); |
7358 | ||
103a196f | 7359 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 7360 | bool found = false; |
7d57382e | 7361 | |
725e30ad | 7362 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 7363 | DRM_DEBUG_KMS("probing SDVOB\n"); |
725e30ad | 7364 | found = intel_sdvo_init(dev, SDVOB); |
b01f2c3a JB |
7365 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
7366 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
725e30ad | 7367 | intel_hdmi_init(dev, SDVOB); |
b01f2c3a | 7368 | } |
27185ae1 | 7369 | |
b01f2c3a JB |
7370 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
7371 | DRM_DEBUG_KMS("probing DP_B\n"); | |
a4fc5ed6 | 7372 | intel_dp_init(dev, DP_B); |
b01f2c3a | 7373 | } |
725e30ad | 7374 | } |
13520b05 KH |
7375 | |
7376 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 7377 | |
b01f2c3a JB |
7378 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
7379 | DRM_DEBUG_KMS("probing SDVOC\n"); | |
725e30ad | 7380 | found = intel_sdvo_init(dev, SDVOC); |
b01f2c3a | 7381 | } |
27185ae1 ML |
7382 | |
7383 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { | |
7384 | ||
b01f2c3a JB |
7385 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
7386 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
725e30ad | 7387 | intel_hdmi_init(dev, SDVOC); |
b01f2c3a JB |
7388 | } |
7389 | if (SUPPORTS_INTEGRATED_DP(dev)) { | |
7390 | DRM_DEBUG_KMS("probing DP_C\n"); | |
a4fc5ed6 | 7391 | intel_dp_init(dev, DP_C); |
b01f2c3a | 7392 | } |
725e30ad | 7393 | } |
27185ae1 | 7394 | |
b01f2c3a JB |
7395 | if (SUPPORTS_INTEGRATED_DP(dev) && |
7396 | (I915_READ(DP_D) & DP_DETECTED)) { | |
7397 | DRM_DEBUG_KMS("probing DP_D\n"); | |
a4fc5ed6 | 7398 | intel_dp_init(dev, DP_D); |
b01f2c3a | 7399 | } |
bad720ff | 7400 | } else if (IS_GEN2(dev)) |
79e53945 JB |
7401 | intel_dvo_init(dev); |
7402 | ||
103a196f | 7403 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
7404 | intel_tv_init(dev); |
7405 | ||
4ef69c7a CW |
7406 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
7407 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
7408 | encoder->base.possible_clones = | |
7409 | intel_encoder_clones(dev, encoder->clone_mask); | |
79e53945 | 7410 | } |
47356eb6 | 7411 | |
2c7111db CW |
7412 | /* disable all the possible outputs/crtcs before entering KMS mode */ |
7413 | drm_helper_disable_unused_functions(dev); | |
9fb526db KP |
7414 | |
7415 | if (HAS_PCH_SPLIT(dev)) | |
7416 | ironlake_init_pch_refclk(dev); | |
79e53945 JB |
7417 | } |
7418 | ||
7419 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
7420 | { | |
7421 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 JB |
7422 | |
7423 | drm_framebuffer_cleanup(fb); | |
05394f39 | 7424 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); |
79e53945 JB |
7425 | |
7426 | kfree(intel_fb); | |
7427 | } | |
7428 | ||
7429 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 7430 | struct drm_file *file, |
79e53945 JB |
7431 | unsigned int *handle) |
7432 | { | |
7433 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 7434 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 7435 | |
05394f39 | 7436 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
7437 | } |
7438 | ||
7439 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
7440 | .destroy = intel_user_framebuffer_destroy, | |
7441 | .create_handle = intel_user_framebuffer_create_handle, | |
7442 | }; | |
7443 | ||
38651674 DA |
7444 | int intel_framebuffer_init(struct drm_device *dev, |
7445 | struct intel_framebuffer *intel_fb, | |
7446 | struct drm_mode_fb_cmd *mode_cmd, | |
05394f39 | 7447 | struct drm_i915_gem_object *obj) |
79e53945 | 7448 | { |
79e53945 JB |
7449 | int ret; |
7450 | ||
05394f39 | 7451 | if (obj->tiling_mode == I915_TILING_Y) |
57cd6508 CW |
7452 | return -EINVAL; |
7453 | ||
7454 | if (mode_cmd->pitch & 63) | |
7455 | return -EINVAL; | |
7456 | ||
7457 | switch (mode_cmd->bpp) { | |
7458 | case 8: | |
7459 | case 16: | |
b5626747 JB |
7460 | /* Only pre-ILK can handle 5:5:5 */ |
7461 | if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev)) | |
7462 | return -EINVAL; | |
7463 | break; | |
7464 | ||
57cd6508 CW |
7465 | case 24: |
7466 | case 32: | |
7467 | break; | |
7468 | default: | |
7469 | return -EINVAL; | |
7470 | } | |
7471 | ||
79e53945 JB |
7472 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
7473 | if (ret) { | |
7474 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
7475 | return ret; | |
7476 | } | |
7477 | ||
7478 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); | |
79e53945 | 7479 | intel_fb->obj = obj; |
79e53945 JB |
7480 | return 0; |
7481 | } | |
7482 | ||
79e53945 JB |
7483 | static struct drm_framebuffer * |
7484 | intel_user_framebuffer_create(struct drm_device *dev, | |
7485 | struct drm_file *filp, | |
7486 | struct drm_mode_fb_cmd *mode_cmd) | |
7487 | { | |
05394f39 | 7488 | struct drm_i915_gem_object *obj; |
79e53945 | 7489 | |
05394f39 | 7490 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle)); |
c8725226 | 7491 | if (&obj->base == NULL) |
cce13ff7 | 7492 | return ERR_PTR(-ENOENT); |
79e53945 | 7493 | |
d2dff872 | 7494 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
7495 | } |
7496 | ||
79e53945 | 7497 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 7498 | .fb_create = intel_user_framebuffer_create, |
eb1f8e4f | 7499 | .output_poll_changed = intel_fb_output_poll_changed, |
79e53945 JB |
7500 | }; |
7501 | ||
05394f39 | 7502 | static struct drm_i915_gem_object * |
aa40d6bb | 7503 | intel_alloc_context_page(struct drm_device *dev) |
9ea8d059 | 7504 | { |
05394f39 | 7505 | struct drm_i915_gem_object *ctx; |
9ea8d059 CW |
7506 | int ret; |
7507 | ||
2c34b850 BW |
7508 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
7509 | ||
aa40d6bb ZN |
7510 | ctx = i915_gem_alloc_object(dev, 4096); |
7511 | if (!ctx) { | |
9ea8d059 CW |
7512 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); |
7513 | return NULL; | |
7514 | } | |
7515 | ||
75e9e915 | 7516 | ret = i915_gem_object_pin(ctx, 4096, true); |
9ea8d059 CW |
7517 | if (ret) { |
7518 | DRM_ERROR("failed to pin power context: %d\n", ret); | |
7519 | goto err_unref; | |
7520 | } | |
7521 | ||
aa40d6bb | 7522 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); |
9ea8d059 CW |
7523 | if (ret) { |
7524 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); | |
7525 | goto err_unpin; | |
7526 | } | |
9ea8d059 | 7527 | |
aa40d6bb | 7528 | return ctx; |
9ea8d059 CW |
7529 | |
7530 | err_unpin: | |
aa40d6bb | 7531 | i915_gem_object_unpin(ctx); |
9ea8d059 | 7532 | err_unref: |
05394f39 | 7533 | drm_gem_object_unreference(&ctx->base); |
9ea8d059 CW |
7534 | mutex_unlock(&dev->struct_mutex); |
7535 | return NULL; | |
7536 | } | |
7537 | ||
7648fa99 JB |
7538 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
7539 | { | |
7540 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7541 | u16 rgvswctl; | |
7542 | ||
7543 | rgvswctl = I915_READ16(MEMSWCTL); | |
7544 | if (rgvswctl & MEMCTL_CMD_STS) { | |
7545 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
7546 | return false; /* still busy with another command */ | |
7547 | } | |
7548 | ||
7549 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
7550 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
7551 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
7552 | POSTING_READ16(MEMSWCTL); | |
7553 | ||
7554 | rgvswctl |= MEMCTL_CMD_STS; | |
7555 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
7556 | ||
7557 | return true; | |
7558 | } | |
7559 | ||
f97108d1 JB |
7560 | void ironlake_enable_drps(struct drm_device *dev) |
7561 | { | |
7562 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648fa99 | 7563 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
f97108d1 | 7564 | u8 fmax, fmin, fstart, vstart; |
f97108d1 | 7565 | |
ea056c14 JB |
7566 | /* Enable temp reporting */ |
7567 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
7568 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
7569 | ||
f97108d1 JB |
7570 | /* 100ms RC evaluation intervals */ |
7571 | I915_WRITE(RCUPEI, 100000); | |
7572 | I915_WRITE(RCDNEI, 100000); | |
7573 | ||
7574 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
7575 | I915_WRITE(RCBMAXAVG, 90000); | |
7576 | I915_WRITE(RCBMINAVG, 80000); | |
7577 | ||
7578 | I915_WRITE(MEMIHYST, 1); | |
7579 | ||
7580 | /* Set up min, max, and cur for interrupt handling */ | |
7581 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
7582 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
7583 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
7584 | MEMMODE_FSTART_SHIFT; | |
7648fa99 | 7585 | |
f97108d1 JB |
7586 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> |
7587 | PXVFREQ_PX_SHIFT; | |
7588 | ||
80dbf4b7 | 7589 | dev_priv->fmax = fmax; /* IPS callback will increase this */ |
7648fa99 JB |
7590 | dev_priv->fstart = fstart; |
7591 | ||
80dbf4b7 | 7592 | dev_priv->max_delay = fstart; |
f97108d1 JB |
7593 | dev_priv->min_delay = fmin; |
7594 | dev_priv->cur_delay = fstart; | |
7595 | ||
80dbf4b7 JB |
7596 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", |
7597 | fmax, fmin, fstart); | |
7648fa99 | 7598 | |
f97108d1 JB |
7599 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
7600 | ||
7601 | /* | |
7602 | * Interrupts will be enabled in ironlake_irq_postinstall | |
7603 | */ | |
7604 | ||
7605 | I915_WRITE(VIDSTART, vstart); | |
7606 | POSTING_READ(VIDSTART); | |
7607 | ||
7608 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
7609 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
7610 | ||
481b6af3 | 7611 | if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
913d8d11 | 7612 | DRM_ERROR("stuck trying to change perf mode\n"); |
f97108d1 JB |
7613 | msleep(1); |
7614 | ||
7648fa99 | 7615 | ironlake_set_drps(dev, fstart); |
f97108d1 | 7616 | |
7648fa99 JB |
7617 | dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
7618 | I915_READ(0x112e0); | |
7619 | dev_priv->last_time1 = jiffies_to_msecs(jiffies); | |
7620 | dev_priv->last_count2 = I915_READ(0x112f4); | |
7621 | getrawmonotonic(&dev_priv->last_time2); | |
f97108d1 JB |
7622 | } |
7623 | ||
7624 | void ironlake_disable_drps(struct drm_device *dev) | |
7625 | { | |
7626 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648fa99 | 7627 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
f97108d1 JB |
7628 | |
7629 | /* Ack interrupts, disable EFC interrupt */ | |
7630 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
7631 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
7632 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
7633 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
7634 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
7635 | ||
7636 | /* Go back to the starting frequency */ | |
7648fa99 | 7637 | ironlake_set_drps(dev, dev_priv->fstart); |
f97108d1 JB |
7638 | msleep(1); |
7639 | rgvswctl |= MEMCTL_CMD_STS; | |
7640 | I915_WRITE(MEMSWCTL, rgvswctl); | |
7641 | msleep(1); | |
7642 | ||
7643 | } | |
7644 | ||
3b8d8d91 JB |
7645 | void gen6_set_rps(struct drm_device *dev, u8 val) |
7646 | { | |
7647 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648 | u32 swreq; | |
7649 | ||
7650 | swreq = (val & 0x3ff) << 25; | |
7651 | I915_WRITE(GEN6_RPNSWREQ, swreq); | |
7652 | } | |
7653 | ||
7654 | void gen6_disable_rps(struct drm_device *dev) | |
7655 | { | |
7656 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7657 | ||
7658 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); | |
7659 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); | |
7660 | I915_WRITE(GEN6_PMIER, 0); | |
4912d041 BW |
7661 | |
7662 | spin_lock_irq(&dev_priv->rps_lock); | |
7663 | dev_priv->pm_iir = 0; | |
7664 | spin_unlock_irq(&dev_priv->rps_lock); | |
7665 | ||
3b8d8d91 JB |
7666 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); |
7667 | } | |
7668 | ||
7648fa99 JB |
7669 | static unsigned long intel_pxfreq(u32 vidfreq) |
7670 | { | |
7671 | unsigned long freq; | |
7672 | int div = (vidfreq & 0x3f0000) >> 16; | |
7673 | int post = (vidfreq & 0x3000) >> 12; | |
7674 | int pre = (vidfreq & 0x7); | |
7675 | ||
7676 | if (!pre) | |
7677 | return 0; | |
7678 | ||
7679 | freq = ((div * 133333) / ((1<<post) * pre)); | |
7680 | ||
7681 | return freq; | |
7682 | } | |
7683 | ||
7684 | void intel_init_emon(struct drm_device *dev) | |
7685 | { | |
7686 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7687 | u32 lcfuse; | |
7688 | u8 pxw[16]; | |
7689 | int i; | |
7690 | ||
7691 | /* Disable to program */ | |
7692 | I915_WRITE(ECR, 0); | |
7693 | POSTING_READ(ECR); | |
7694 | ||
7695 | /* Program energy weights for various events */ | |
7696 | I915_WRITE(SDEW, 0x15040d00); | |
7697 | I915_WRITE(CSIEW0, 0x007f0000); | |
7698 | I915_WRITE(CSIEW1, 0x1e220004); | |
7699 | I915_WRITE(CSIEW2, 0x04000004); | |
7700 | ||
7701 | for (i = 0; i < 5; i++) | |
7702 | I915_WRITE(PEW + (i * 4), 0); | |
7703 | for (i = 0; i < 3; i++) | |
7704 | I915_WRITE(DEW + (i * 4), 0); | |
7705 | ||
7706 | /* Program P-state weights to account for frequency power adjustment */ | |
7707 | for (i = 0; i < 16; i++) { | |
7708 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); | |
7709 | unsigned long freq = intel_pxfreq(pxvidfreq); | |
7710 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
7711 | PXVFREQ_PX_SHIFT; | |
7712 | unsigned long val; | |
7713 | ||
7714 | val = vid * vid; | |
7715 | val *= (freq / 1000); | |
7716 | val *= 255; | |
7717 | val /= (127*127*900); | |
7718 | if (val > 0xff) | |
7719 | DRM_ERROR("bad pxval: %ld\n", val); | |
7720 | pxw[i] = val; | |
7721 | } | |
7722 | /* Render standby states get 0 weight */ | |
7723 | pxw[14] = 0; | |
7724 | pxw[15] = 0; | |
7725 | ||
7726 | for (i = 0; i < 4; i++) { | |
7727 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
7728 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
7729 | I915_WRITE(PXW + (i * 4), val); | |
7730 | } | |
7731 | ||
7732 | /* Adjust magic regs to magic values (more experimental results) */ | |
7733 | I915_WRITE(OGW0, 0); | |
7734 | I915_WRITE(OGW1, 0); | |
7735 | I915_WRITE(EG0, 0x00007f00); | |
7736 | I915_WRITE(EG1, 0x0000000e); | |
7737 | I915_WRITE(EG2, 0x000e0000); | |
7738 | I915_WRITE(EG3, 0x68000300); | |
7739 | I915_WRITE(EG4, 0x42000000); | |
7740 | I915_WRITE(EG5, 0x00140031); | |
7741 | I915_WRITE(EG6, 0); | |
7742 | I915_WRITE(EG7, 0); | |
7743 | ||
7744 | for (i = 0; i < 8; i++) | |
7745 | I915_WRITE(PXWL + (i * 4), 0); | |
7746 | ||
7747 | /* Enable PMON + select events */ | |
7748 | I915_WRITE(ECR, 0x80000019); | |
7749 | ||
7750 | lcfuse = I915_READ(LCFUSE02); | |
7751 | ||
7752 | dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK); | |
7753 | } | |
7754 | ||
3b8d8d91 | 7755 | void gen6_enable_rps(struct drm_i915_private *dev_priv) |
8fd26859 | 7756 | { |
a6044e23 JB |
7757 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
7758 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
7df8721b | 7759 | u32 pcu_mbox, rc6_mask = 0; |
a6044e23 | 7760 | int cur_freq, min_freq, max_freq; |
8fd26859 CW |
7761 | int i; |
7762 | ||
7763 | /* Here begins a magic sequence of register writes to enable | |
7764 | * auto-downclocking. | |
7765 | * | |
7766 | * Perhaps there might be some value in exposing these to | |
7767 | * userspace... | |
7768 | */ | |
7769 | I915_WRITE(GEN6_RC_STATE, 0); | |
d1ebd816 | 7770 | mutex_lock(&dev_priv->dev->struct_mutex); |
fcca7926 | 7771 | gen6_gt_force_wake_get(dev_priv); |
8fd26859 | 7772 | |
3b8d8d91 | 7773 | /* disable the counters and set deterministic thresholds */ |
8fd26859 CW |
7774 | I915_WRITE(GEN6_RC_CONTROL, 0); |
7775 | ||
7776 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); | |
7777 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); | |
7778 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); | |
7779 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
7780 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
7781 | ||
7782 | for (i = 0; i < I915_NUM_RINGS; i++) | |
7783 | I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10); | |
7784 | ||
7785 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
7786 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); | |
7787 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); | |
7788 | I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); | |
7789 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ | |
7790 | ||
7df8721b JB |
7791 | if (i915_enable_rc6) |
7792 | rc6_mask = GEN6_RC_CTL_RC6p_ENABLE | | |
7793 | GEN6_RC_CTL_RC6_ENABLE; | |
7794 | ||
8fd26859 | 7795 | I915_WRITE(GEN6_RC_CONTROL, |
7df8721b | 7796 | rc6_mask | |
9c3d2f7f | 7797 | GEN6_RC_CTL_EI_MODE(1) | |
8fd26859 CW |
7798 | GEN6_RC_CTL_HW_ENABLE); |
7799 | ||
3b8d8d91 | 7800 | I915_WRITE(GEN6_RPNSWREQ, |
8fd26859 CW |
7801 | GEN6_FREQUENCY(10) | |
7802 | GEN6_OFFSET(0) | | |
7803 | GEN6_AGGRESSIVE_TURBO); | |
7804 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
7805 | GEN6_FREQUENCY(12)); | |
7806 | ||
7807 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); | |
7808 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
7809 | 18 << 24 | | |
7810 | 6 << 16); | |
ccab5c82 JB |
7811 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000); |
7812 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000); | |
8fd26859 | 7813 | I915_WRITE(GEN6_RP_UP_EI, 100000); |
ccab5c82 | 7814 | I915_WRITE(GEN6_RP_DOWN_EI, 5000000); |
8fd26859 CW |
7815 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
7816 | I915_WRITE(GEN6_RP_CONTROL, | |
7817 | GEN6_RP_MEDIA_TURBO | | |
7818 | GEN6_RP_USE_NORMAL_FREQ | | |
7819 | GEN6_RP_MEDIA_IS_GFX | | |
7820 | GEN6_RP_ENABLE | | |
ccab5c82 JB |
7821 | GEN6_RP_UP_BUSY_AVG | |
7822 | GEN6_RP_DOWN_IDLE_CONT); | |
8fd26859 CW |
7823 | |
7824 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
7825 | 500)) | |
7826 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); | |
7827 | ||
7828 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
7829 | I915_WRITE(GEN6_PCODE_MAILBOX, | |
7830 | GEN6_PCODE_READY | | |
7831 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE); | |
7832 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
7833 | 500)) | |
7834 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); | |
7835 | ||
a6044e23 JB |
7836 | min_freq = (rp_state_cap & 0xff0000) >> 16; |
7837 | max_freq = rp_state_cap & 0xff; | |
7838 | cur_freq = (gt_perf_status & 0xff00) >> 8; | |
7839 | ||
7840 | /* Check for overclock support */ | |
7841 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
7842 | 500)) | |
7843 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); | |
7844 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS); | |
7845 | pcu_mbox = I915_READ(GEN6_PCODE_DATA); | |
7846 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
7847 | 500)) | |
7848 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); | |
7849 | if (pcu_mbox & (1<<31)) { /* OC supported */ | |
7850 | max_freq = pcu_mbox & 0xff; | |
e281fcaa | 7851 | DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50); |
a6044e23 JB |
7852 | } |
7853 | ||
7854 | /* In units of 100MHz */ | |
7855 | dev_priv->max_delay = max_freq; | |
7856 | dev_priv->min_delay = min_freq; | |
7857 | dev_priv->cur_delay = cur_freq; | |
7858 | ||
8fd26859 CW |
7859 | /* requires MSI enabled */ |
7860 | I915_WRITE(GEN6_PMIER, | |
7861 | GEN6_PM_MBOX_EVENT | | |
7862 | GEN6_PM_THERMAL_EVENT | | |
7863 | GEN6_PM_RP_DOWN_TIMEOUT | | |
7864 | GEN6_PM_RP_UP_THRESHOLD | | |
7865 | GEN6_PM_RP_DOWN_THRESHOLD | | |
7866 | GEN6_PM_RP_UP_EI_EXPIRED | | |
7867 | GEN6_PM_RP_DOWN_EI_EXPIRED); | |
4912d041 BW |
7868 | spin_lock_irq(&dev_priv->rps_lock); |
7869 | WARN_ON(dev_priv->pm_iir != 0); | |
3b8d8d91 | 7870 | I915_WRITE(GEN6_PMIMR, 0); |
4912d041 | 7871 | spin_unlock_irq(&dev_priv->rps_lock); |
3b8d8d91 JB |
7872 | /* enable all PM interrupts */ |
7873 | I915_WRITE(GEN6_PMINTRMSK, 0); | |
8fd26859 | 7874 | |
fcca7926 | 7875 | gen6_gt_force_wake_put(dev_priv); |
d1ebd816 | 7876 | mutex_unlock(&dev_priv->dev->struct_mutex); |
8fd26859 CW |
7877 | } |
7878 | ||
23b2f8bb JB |
7879 | void gen6_update_ring_freq(struct drm_i915_private *dev_priv) |
7880 | { | |
7881 | int min_freq = 15; | |
7882 | int gpu_freq, ia_freq, max_ia_freq; | |
7883 | int scaling_factor = 180; | |
7884 | ||
7885 | max_ia_freq = cpufreq_quick_get_max(0); | |
7886 | /* | |
7887 | * Default to measured freq if none found, PCU will ensure we don't go | |
7888 | * over | |
7889 | */ | |
7890 | if (!max_ia_freq) | |
7891 | max_ia_freq = tsc_khz; | |
7892 | ||
7893 | /* Convert from kHz to MHz */ | |
7894 | max_ia_freq /= 1000; | |
7895 | ||
7896 | mutex_lock(&dev_priv->dev->struct_mutex); | |
7897 | ||
7898 | /* | |
7899 | * For each potential GPU frequency, load a ring frequency we'd like | |
7900 | * to use for memory access. We do this by specifying the IA frequency | |
7901 | * the PCU should use as a reference to determine the ring frequency. | |
7902 | */ | |
7903 | for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay; | |
7904 | gpu_freq--) { | |
7905 | int diff = dev_priv->max_delay - gpu_freq; | |
7906 | ||
7907 | /* | |
7908 | * For GPU frequencies less than 750MHz, just use the lowest | |
7909 | * ring freq. | |
7910 | */ | |
7911 | if (gpu_freq < min_freq) | |
7912 | ia_freq = 800; | |
7913 | else | |
7914 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); | |
7915 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); | |
7916 | ||
7917 | I915_WRITE(GEN6_PCODE_DATA, | |
7918 | (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) | | |
7919 | gpu_freq); | |
7920 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | | |
7921 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE); | |
7922 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & | |
7923 | GEN6_PCODE_READY) == 0, 10)) { | |
7924 | DRM_ERROR("pcode write of freq table timed out\n"); | |
7925 | continue; | |
7926 | } | |
7927 | } | |
7928 | ||
7929 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
7930 | } | |
7931 | ||
6067aaea JB |
7932 | static void ironlake_init_clock_gating(struct drm_device *dev) |
7933 | { | |
7934 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7935 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; | |
7936 | ||
7937 | /* Required for FBC */ | |
7938 | dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE | | |
7939 | DPFCRUNIT_CLOCK_GATE_DISABLE | | |
7940 | DPFDUNIT_CLOCK_GATE_DISABLE; | |
7941 | /* Required for CxSR */ | |
7942 | dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE; | |
7943 | ||
7944 | I915_WRITE(PCH_3DCGDIS0, | |
7945 | MARIUNIT_CLOCK_GATE_DISABLE | | |
7946 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
7947 | I915_WRITE(PCH_3DCGDIS1, | |
7948 | VFMUNIT_CLOCK_GATE_DISABLE); | |
7949 | ||
7950 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); | |
7951 | ||
6067aaea JB |
7952 | /* |
7953 | * According to the spec the following bits should be set in | |
7954 | * order to enable memory self-refresh | |
7955 | * The bit 22/21 of 0x42004 | |
7956 | * The bit 5 of 0x42020 | |
7957 | * The bit 15 of 0x45000 | |
7958 | */ | |
7959 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
7960 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
7961 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
7962 | I915_WRITE(ILK_DSPCLK_GATE, | |
7963 | (I915_READ(ILK_DSPCLK_GATE) | | |
7964 | ILK_DPARB_CLK_GATE)); | |
7965 | I915_WRITE(DISP_ARB_CTL, | |
7966 | (I915_READ(DISP_ARB_CTL) | | |
7967 | DISP_FBC_WM_DIS)); | |
7968 | I915_WRITE(WM3_LP_ILK, 0); | |
7969 | I915_WRITE(WM2_LP_ILK, 0); | |
7970 | I915_WRITE(WM1_LP_ILK, 0); | |
7971 | ||
7972 | /* | |
7973 | * Based on the document from hardware guys the following bits | |
7974 | * should be set unconditionally in order to enable FBC. | |
7975 | * The bit 22 of 0x42000 | |
7976 | * The bit 22 of 0x42004 | |
7977 | * The bit 7,8,9 of 0x42020. | |
7978 | */ | |
7979 | if (IS_IRONLAKE_M(dev)) { | |
7980 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
7981 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
7982 | ILK_FBCQ_DIS); | |
7983 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
7984 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
7985 | ILK_DPARB_GATE); | |
7986 | I915_WRITE(ILK_DSPCLK_GATE, | |
7987 | I915_READ(ILK_DSPCLK_GATE) | | |
7988 | ILK_DPFC_DIS1 | | |
7989 | ILK_DPFC_DIS2 | | |
7990 | ILK_CLK_FBC); | |
7991 | } | |
7992 | ||
7993 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
7994 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
7995 | ILK_ELPIN_409_SELECT); | |
7996 | I915_WRITE(_3D_CHICKEN2, | |
7997 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | | |
7998 | _3D_CHICKEN2_WM_READ_PIPELINED); | |
8fd26859 CW |
7999 | } |
8000 | ||
6067aaea | 8001 | static void gen6_init_clock_gating(struct drm_device *dev) |
652c393a JB |
8002 | { |
8003 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9db4a9c7 | 8004 | int pipe; |
6067aaea JB |
8005 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
8006 | ||
8007 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); | |
652c393a | 8008 | |
6067aaea JB |
8009 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
8010 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8011 | ILK_ELPIN_409_SELECT); | |
8956c8bb | 8012 | |
6067aaea JB |
8013 | I915_WRITE(WM3_LP_ILK, 0); |
8014 | I915_WRITE(WM2_LP_ILK, 0); | |
8015 | I915_WRITE(WM1_LP_ILK, 0); | |
652c393a JB |
8016 | |
8017 | /* | |
6067aaea JB |
8018 | * According to the spec the following bits should be |
8019 | * set in order to enable memory self-refresh and fbc: | |
8020 | * The bit21 and bit22 of 0x42000 | |
8021 | * The bit21 and bit22 of 0x42004 | |
8022 | * The bit5 and bit7 of 0x42020 | |
8023 | * The bit14 of 0x70180 | |
8024 | * The bit14 of 0x71180 | |
652c393a | 8025 | */ |
6067aaea JB |
8026 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
8027 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
8028 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); | |
8029 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
8030 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8031 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); | |
8032 | I915_WRITE(ILK_DSPCLK_GATE, | |
8033 | I915_READ(ILK_DSPCLK_GATE) | | |
8034 | ILK_DPARB_CLK_GATE | | |
8035 | ILK_DPFD_CLK_GATE); | |
8956c8bb | 8036 | |
d74362c9 | 8037 | for_each_pipe(pipe) { |
6067aaea JB |
8038 | I915_WRITE(DSPCNTR(pipe), |
8039 | I915_READ(DSPCNTR(pipe)) | | |
8040 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
d74362c9 KP |
8041 | intel_flush_display_plane(dev_priv, pipe); |
8042 | } | |
6067aaea | 8043 | } |
8956c8bb | 8044 | |
28963a3e JB |
8045 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
8046 | { | |
8047 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8048 | int pipe; | |
8049 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; | |
7f8a8569 | 8050 | |
28963a3e | 8051 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); |
382b0936 | 8052 | |
28963a3e JB |
8053 | I915_WRITE(WM3_LP_ILK, 0); |
8054 | I915_WRITE(WM2_LP_ILK, 0); | |
8055 | I915_WRITE(WM1_LP_ILK, 0); | |
de6e2eaf | 8056 | |
28963a3e | 8057 | I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE); |
67e92af0 | 8058 | |
d74362c9 | 8059 | for_each_pipe(pipe) { |
28963a3e JB |
8060 | I915_WRITE(DSPCNTR(pipe), |
8061 | I915_READ(DSPCNTR(pipe)) | | |
8062 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
d74362c9 KP |
8063 | intel_flush_display_plane(dev_priv, pipe); |
8064 | } | |
28963a3e JB |
8065 | } |
8066 | ||
6067aaea JB |
8067 | static void g4x_init_clock_gating(struct drm_device *dev) |
8068 | { | |
8069 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8070 | uint32_t dspclk_gate; | |
8fd26859 | 8071 | |
6067aaea JB |
8072 | I915_WRITE(RENCLK_GATE_D1, 0); |
8073 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
8074 | GS_UNIT_CLOCK_GATE_DISABLE | | |
8075 | CL_UNIT_CLOCK_GATE_DISABLE); | |
8076 | I915_WRITE(RAMCLK_GATE_D, 0); | |
8077 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
8078 | OVRUNIT_CLOCK_GATE_DISABLE | | |
8079 | OVCUNIT_CLOCK_GATE_DISABLE; | |
8080 | if (IS_GM45(dev)) | |
8081 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; | |
8082 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
8083 | } | |
1398261a | 8084 | |
6067aaea JB |
8085 | static void crestline_init_clock_gating(struct drm_device *dev) |
8086 | { | |
8087 | struct drm_i915_private *dev_priv = dev->dev_private; | |
652c393a | 8088 | |
6067aaea JB |
8089 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
8090 | I915_WRITE(RENCLK_GATE_D2, 0); | |
8091 | I915_WRITE(DSPCLK_GATE_D, 0); | |
8092 | I915_WRITE(RAMCLK_GATE_D, 0); | |
8093 | I915_WRITE16(DEUC, 0); | |
8094 | } | |
652c393a | 8095 | |
6067aaea JB |
8096 | static void broadwater_init_clock_gating(struct drm_device *dev) |
8097 | { | |
8098 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8099 | ||
8100 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | | |
8101 | I965_RCC_CLOCK_GATE_DISABLE | | |
8102 | I965_RCPB_CLOCK_GATE_DISABLE | | |
8103 | I965_ISC_CLOCK_GATE_DISABLE | | |
8104 | I965_FBC_CLOCK_GATE_DISABLE); | |
8105 | I915_WRITE(RENCLK_GATE_D2, 0); | |
8106 | } | |
8107 | ||
8108 | static void gen3_init_clock_gating(struct drm_device *dev) | |
8109 | { | |
8110 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8111 | u32 dstate = I915_READ(D_STATE); | |
8112 | ||
8113 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
8114 | DSTATE_DOT_CLOCK_GATING; | |
8115 | I915_WRITE(D_STATE, dstate); | |
8116 | } | |
8117 | ||
8118 | static void i85x_init_clock_gating(struct drm_device *dev) | |
8119 | { | |
8120 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8121 | ||
8122 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); | |
8123 | } | |
8124 | ||
8125 | static void i830_init_clock_gating(struct drm_device *dev) | |
8126 | { | |
8127 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8128 | ||
8129 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); | |
652c393a JB |
8130 | } |
8131 | ||
645c62a5 JB |
8132 | static void ibx_init_clock_gating(struct drm_device *dev) |
8133 | { | |
8134 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8135 | ||
8136 | /* | |
8137 | * On Ibex Peak and Cougar Point, we need to disable clock | |
8138 | * gating for the panel power sequencer or it will fail to | |
8139 | * start up when no ports are active. | |
8140 | */ | |
8141 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
8142 | } | |
8143 | ||
8144 | static void cpt_init_clock_gating(struct drm_device *dev) | |
8145 | { | |
8146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3bcf603f | 8147 | int pipe; |
645c62a5 JB |
8148 | |
8149 | /* | |
8150 | * On Ibex Peak and Cougar Point, we need to disable clock | |
8151 | * gating for the panel power sequencer or it will fail to | |
8152 | * start up when no ports are active. | |
8153 | */ | |
8154 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
8155 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | | |
8156 | DPLS_EDP_PPS_FIX_DIS); | |
3bcf603f JB |
8157 | /* Without this, mode sets may fail silently on FDI */ |
8158 | for_each_pipe(pipe) | |
8159 | I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS); | |
652c393a JB |
8160 | } |
8161 | ||
ac668088 | 8162 | static void ironlake_teardown_rc6(struct drm_device *dev) |
0cdab21f CW |
8163 | { |
8164 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8165 | ||
8166 | if (dev_priv->renderctx) { | |
ac668088 CW |
8167 | i915_gem_object_unpin(dev_priv->renderctx); |
8168 | drm_gem_object_unreference(&dev_priv->renderctx->base); | |
0cdab21f CW |
8169 | dev_priv->renderctx = NULL; |
8170 | } | |
8171 | ||
8172 | if (dev_priv->pwrctx) { | |
ac668088 CW |
8173 | i915_gem_object_unpin(dev_priv->pwrctx); |
8174 | drm_gem_object_unreference(&dev_priv->pwrctx->base); | |
8175 | dev_priv->pwrctx = NULL; | |
8176 | } | |
8177 | } | |
8178 | ||
8179 | static void ironlake_disable_rc6(struct drm_device *dev) | |
8180 | { | |
8181 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8182 | ||
8183 | if (I915_READ(PWRCTXA)) { | |
8184 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ | |
8185 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); | |
8186 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), | |
8187 | 50); | |
0cdab21f CW |
8188 | |
8189 | I915_WRITE(PWRCTXA, 0); | |
8190 | POSTING_READ(PWRCTXA); | |
8191 | ||
ac668088 CW |
8192 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
8193 | POSTING_READ(RSTDBYCTL); | |
0cdab21f | 8194 | } |
ac668088 | 8195 | |
99507307 | 8196 | ironlake_teardown_rc6(dev); |
0cdab21f CW |
8197 | } |
8198 | ||
ac668088 | 8199 | static int ironlake_setup_rc6(struct drm_device *dev) |
d5bb081b JB |
8200 | { |
8201 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8202 | ||
ac668088 CW |
8203 | if (dev_priv->renderctx == NULL) |
8204 | dev_priv->renderctx = intel_alloc_context_page(dev); | |
8205 | if (!dev_priv->renderctx) | |
8206 | return -ENOMEM; | |
8207 | ||
8208 | if (dev_priv->pwrctx == NULL) | |
8209 | dev_priv->pwrctx = intel_alloc_context_page(dev); | |
8210 | if (!dev_priv->pwrctx) { | |
8211 | ironlake_teardown_rc6(dev); | |
8212 | return -ENOMEM; | |
8213 | } | |
8214 | ||
8215 | return 0; | |
d5bb081b JB |
8216 | } |
8217 | ||
8218 | void ironlake_enable_rc6(struct drm_device *dev) | |
8219 | { | |
8220 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8221 | int ret; | |
8222 | ||
ac668088 CW |
8223 | /* rc6 disabled by default due to repeated reports of hanging during |
8224 | * boot and resume. | |
8225 | */ | |
8226 | if (!i915_enable_rc6) | |
8227 | return; | |
8228 | ||
2c34b850 | 8229 | mutex_lock(&dev->struct_mutex); |
ac668088 | 8230 | ret = ironlake_setup_rc6(dev); |
2c34b850 BW |
8231 | if (ret) { |
8232 | mutex_unlock(&dev->struct_mutex); | |
ac668088 | 8233 | return; |
2c34b850 | 8234 | } |
ac668088 | 8235 | |
d5bb081b JB |
8236 | /* |
8237 | * GPU can automatically power down the render unit if given a page | |
8238 | * to save state. | |
8239 | */ | |
8240 | ret = BEGIN_LP_RING(6); | |
8241 | if (ret) { | |
ac668088 | 8242 | ironlake_teardown_rc6(dev); |
2c34b850 | 8243 | mutex_unlock(&dev->struct_mutex); |
d5bb081b JB |
8244 | return; |
8245 | } | |
ac668088 | 8246 | |
d5bb081b JB |
8247 | OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
8248 | OUT_RING(MI_SET_CONTEXT); | |
8249 | OUT_RING(dev_priv->renderctx->gtt_offset | | |
8250 | MI_MM_SPACE_GTT | | |
8251 | MI_SAVE_EXT_STATE_EN | | |
8252 | MI_RESTORE_EXT_STATE_EN | | |
8253 | MI_RESTORE_INHIBIT); | |
8254 | OUT_RING(MI_SUSPEND_FLUSH); | |
8255 | OUT_RING(MI_NOOP); | |
8256 | OUT_RING(MI_FLUSH); | |
8257 | ADVANCE_LP_RING(); | |
8258 | ||
4a246cfc BW |
8259 | /* |
8260 | * Wait for the command parser to advance past MI_SET_CONTEXT. The HW | |
8261 | * does an implicit flush, combined with MI_FLUSH above, it should be | |
8262 | * safe to assume that renderctx is valid | |
8263 | */ | |
8264 | ret = intel_wait_ring_idle(LP_RING(dev_priv)); | |
8265 | if (ret) { | |
8266 | DRM_ERROR("failed to enable ironlake power power savings\n"); | |
8267 | ironlake_teardown_rc6(dev); | |
8268 | mutex_unlock(&dev->struct_mutex); | |
8269 | return; | |
8270 | } | |
8271 | ||
d5bb081b JB |
8272 | I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN); |
8273 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); | |
2c34b850 | 8274 | mutex_unlock(&dev->struct_mutex); |
d5bb081b JB |
8275 | } |
8276 | ||
645c62a5 JB |
8277 | void intel_init_clock_gating(struct drm_device *dev) |
8278 | { | |
8279 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8280 | ||
8281 | dev_priv->display.init_clock_gating(dev); | |
8282 | ||
8283 | if (dev_priv->display.init_pch_clock_gating) | |
8284 | dev_priv->display.init_pch_clock_gating(dev); | |
8285 | } | |
ac668088 | 8286 | |
e70236a8 JB |
8287 | /* Set up chip specific display functions */ |
8288 | static void intel_init_display(struct drm_device *dev) | |
8289 | { | |
8290 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8291 | ||
8292 | /* We always want a DPMS function */ | |
f564048e | 8293 | if (HAS_PCH_SPLIT(dev)) { |
f2b115e6 | 8294 | dev_priv->display.dpms = ironlake_crtc_dpms; |
f564048e | 8295 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
17638cd6 | 8296 | dev_priv->display.update_plane = ironlake_update_plane; |
f564048e | 8297 | } else { |
e70236a8 | 8298 | dev_priv->display.dpms = i9xx_crtc_dpms; |
f564048e | 8299 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
17638cd6 | 8300 | dev_priv->display.update_plane = i9xx_update_plane; |
f564048e | 8301 | } |
e70236a8 | 8302 | |
ee5382ae | 8303 | if (I915_HAS_FBC(dev)) { |
9c04f015 | 8304 | if (HAS_PCH_SPLIT(dev)) { |
b52eb4dc ZY |
8305 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; |
8306 | dev_priv->display.enable_fbc = ironlake_enable_fbc; | |
8307 | dev_priv->display.disable_fbc = ironlake_disable_fbc; | |
8308 | } else if (IS_GM45(dev)) { | |
74dff282 JB |
8309 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; |
8310 | dev_priv->display.enable_fbc = g4x_enable_fbc; | |
8311 | dev_priv->display.disable_fbc = g4x_disable_fbc; | |
a6c45cf0 | 8312 | } else if (IS_CRESTLINE(dev)) { |
e70236a8 JB |
8313 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
8314 | dev_priv->display.enable_fbc = i8xx_enable_fbc; | |
8315 | dev_priv->display.disable_fbc = i8xx_disable_fbc; | |
8316 | } | |
74dff282 | 8317 | /* 855GM needs testing */ |
e70236a8 JB |
8318 | } |
8319 | ||
8320 | /* Returns the core display clock speed */ | |
0206e353 | 8321 | if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) |
e70236a8 JB |
8322 | dev_priv->display.get_display_clock_speed = |
8323 | i945_get_display_clock_speed; | |
8324 | else if (IS_I915G(dev)) | |
8325 | dev_priv->display.get_display_clock_speed = | |
8326 | i915_get_display_clock_speed; | |
f2b115e6 | 8327 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
e70236a8 JB |
8328 | dev_priv->display.get_display_clock_speed = |
8329 | i9xx_misc_get_display_clock_speed; | |
8330 | else if (IS_I915GM(dev)) | |
8331 | dev_priv->display.get_display_clock_speed = | |
8332 | i915gm_get_display_clock_speed; | |
8333 | else if (IS_I865G(dev)) | |
8334 | dev_priv->display.get_display_clock_speed = | |
8335 | i865_get_display_clock_speed; | |
f0f8a9ce | 8336 | else if (IS_I85X(dev)) |
e70236a8 JB |
8337 | dev_priv->display.get_display_clock_speed = |
8338 | i855_get_display_clock_speed; | |
8339 | else /* 852, 830 */ | |
8340 | dev_priv->display.get_display_clock_speed = | |
8341 | i830_get_display_clock_speed; | |
8342 | ||
8343 | /* For FIFO watermark updates */ | |
7f8a8569 | 8344 | if (HAS_PCH_SPLIT(dev)) { |
645c62a5 JB |
8345 | if (HAS_PCH_IBX(dev)) |
8346 | dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating; | |
8347 | else if (HAS_PCH_CPT(dev)) | |
8348 | dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating; | |
8349 | ||
f00a3ddf | 8350 | if (IS_GEN5(dev)) { |
7f8a8569 ZW |
8351 | if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) |
8352 | dev_priv->display.update_wm = ironlake_update_wm; | |
8353 | else { | |
8354 | DRM_DEBUG_KMS("Failed to get proper latency. " | |
8355 | "Disable CxSR\n"); | |
8356 | dev_priv->display.update_wm = NULL; | |
1398261a | 8357 | } |
674cf967 | 8358 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
6067aaea | 8359 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
e0dac65e | 8360 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a YL |
8361 | } else if (IS_GEN6(dev)) { |
8362 | if (SNB_READ_WM0_LATENCY()) { | |
8363 | dev_priv->display.update_wm = sandybridge_update_wm; | |
8364 | } else { | |
8365 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
8366 | "Disable CxSR\n"); | |
8367 | dev_priv->display.update_wm = NULL; | |
7f8a8569 | 8368 | } |
674cf967 | 8369 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
6067aaea | 8370 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
e0dac65e | 8371 | dev_priv->display.write_eld = ironlake_write_eld; |
357555c0 JB |
8372 | } else if (IS_IVYBRIDGE(dev)) { |
8373 | /* FIXME: detect B0+ stepping and use auto training */ | |
8374 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
fe100d4d JB |
8375 | if (SNB_READ_WM0_LATENCY()) { |
8376 | dev_priv->display.update_wm = sandybridge_update_wm; | |
8377 | } else { | |
8378 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
8379 | "Disable CxSR\n"); | |
8380 | dev_priv->display.update_wm = NULL; | |
8381 | } | |
28963a3e | 8382 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
e0dac65e | 8383 | dev_priv->display.write_eld = ironlake_write_eld; |
7f8a8569 ZW |
8384 | } else |
8385 | dev_priv->display.update_wm = NULL; | |
8386 | } else if (IS_PINEVIEW(dev)) { | |
d4294342 | 8387 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
95534263 | 8388 | dev_priv->is_ddr3, |
d4294342 ZY |
8389 | dev_priv->fsb_freq, |
8390 | dev_priv->mem_freq)) { | |
8391 | DRM_INFO("failed to find known CxSR latency " | |
95534263 | 8392 | "(found ddr%s fsb freq %d, mem freq %d), " |
d4294342 | 8393 | "disabling CxSR\n", |
0206e353 | 8394 | (dev_priv->is_ddr3 == 1) ? "3" : "2", |
d4294342 ZY |
8395 | dev_priv->fsb_freq, dev_priv->mem_freq); |
8396 | /* Disable CxSR and never update its watermark again */ | |
8397 | pineview_disable_cxsr(dev); | |
8398 | dev_priv->display.update_wm = NULL; | |
8399 | } else | |
8400 | dev_priv->display.update_wm = pineview_update_wm; | |
95e0ee92 | 8401 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
6067aaea | 8402 | } else if (IS_G4X(dev)) { |
e0dac65e | 8403 | dev_priv->display.write_eld = g4x_write_eld; |
e70236a8 | 8404 | dev_priv->display.update_wm = g4x_update_wm; |
6067aaea JB |
8405 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; |
8406 | } else if (IS_GEN4(dev)) { | |
e70236a8 | 8407 | dev_priv->display.update_wm = i965_update_wm; |
6067aaea JB |
8408 | if (IS_CRESTLINE(dev)) |
8409 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; | |
8410 | else if (IS_BROADWATER(dev)) | |
8411 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; | |
8412 | } else if (IS_GEN3(dev)) { | |
e70236a8 JB |
8413 | dev_priv->display.update_wm = i9xx_update_wm; |
8414 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
6067aaea JB |
8415 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
8416 | } else if (IS_I865G(dev)) { | |
8417 | dev_priv->display.update_wm = i830_update_wm; | |
8418 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; | |
8419 | dev_priv->display.get_fifo_size = i830_get_fifo_size; | |
8f4695ed AJ |
8420 | } else if (IS_I85X(dev)) { |
8421 | dev_priv->display.update_wm = i9xx_update_wm; | |
8422 | dev_priv->display.get_fifo_size = i85x_get_fifo_size; | |
6067aaea | 8423 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; |
e70236a8 | 8424 | } else { |
8f4695ed | 8425 | dev_priv->display.update_wm = i830_update_wm; |
6067aaea | 8426 | dev_priv->display.init_clock_gating = i830_init_clock_gating; |
8f4695ed | 8427 | if (IS_845G(dev)) |
e70236a8 JB |
8428 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
8429 | else | |
8430 | dev_priv->display.get_fifo_size = i830_get_fifo_size; | |
e70236a8 | 8431 | } |
8c9f3aaf JB |
8432 | |
8433 | /* Default just returns -ENODEV to indicate unsupported */ | |
8434 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8435 | ||
8436 | switch (INTEL_INFO(dev)->gen) { | |
8437 | case 2: | |
8438 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
8439 | break; | |
8440 | ||
8441 | case 3: | |
8442 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
8443 | break; | |
8444 | ||
8445 | case 4: | |
8446 | case 5: | |
8447 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
8448 | break; | |
8449 | ||
8450 | case 6: | |
8451 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
8452 | break; | |
7c9017e5 JB |
8453 | case 7: |
8454 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
8455 | break; | |
8c9f3aaf | 8456 | } |
e70236a8 JB |
8457 | } |
8458 | ||
b690e96c JB |
8459 | /* |
8460 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
8461 | * resume, or other times. This quirk makes sure that's the case for | |
8462 | * affected systems. | |
8463 | */ | |
0206e353 | 8464 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
8465 | { |
8466 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8467 | ||
8468 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
8469 | DRM_DEBUG_DRIVER("applying pipe a force quirk\n"); | |
8470 | } | |
8471 | ||
435793df KP |
8472 | /* |
8473 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
8474 | */ | |
8475 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
8476 | { | |
8477 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8478 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
8479 | } | |
8480 | ||
b690e96c JB |
8481 | struct intel_quirk { |
8482 | int device; | |
8483 | int subsystem_vendor; | |
8484 | int subsystem_device; | |
8485 | void (*hook)(struct drm_device *dev); | |
8486 | }; | |
8487 | ||
8488 | struct intel_quirk intel_quirks[] = { | |
8489 | /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */ | |
8490 | { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force }, | |
8491 | /* HP Mini needs pipe A force quirk (LP: #322104) */ | |
0206e353 | 8492 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c JB |
8493 | |
8494 | /* Thinkpad R31 needs pipe A force quirk */ | |
8495 | { 0x3577, 0x1014, 0x0505, quirk_pipea_force }, | |
8496 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ | |
8497 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
8498 | ||
8499 | /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */ | |
8500 | { 0x3577, 0x1014, 0x0513, quirk_pipea_force }, | |
8501 | /* ThinkPad X40 needs pipe A force quirk */ | |
8502 | ||
8503 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ | |
8504 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
8505 | ||
8506 | /* 855 & before need to leave pipe A & dpll A up */ | |
8507 | { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
8508 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
435793df KP |
8509 | |
8510 | /* Lenovo U160 cannot use SSC on LVDS */ | |
8511 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
8512 | |
8513 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
8514 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
b690e96c JB |
8515 | }; |
8516 | ||
8517 | static void intel_init_quirks(struct drm_device *dev) | |
8518 | { | |
8519 | struct pci_dev *d = dev->pdev; | |
8520 | int i; | |
8521 | ||
8522 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
8523 | struct intel_quirk *q = &intel_quirks[i]; | |
8524 | ||
8525 | if (d->device == q->device && | |
8526 | (d->subsystem_vendor == q->subsystem_vendor || | |
8527 | q->subsystem_vendor == PCI_ANY_ID) && | |
8528 | (d->subsystem_device == q->subsystem_device || | |
8529 | q->subsystem_device == PCI_ANY_ID)) | |
8530 | q->hook(dev); | |
8531 | } | |
8532 | } | |
8533 | ||
9cce37f4 JB |
8534 | /* Disable the VGA plane that we never use */ |
8535 | static void i915_disable_vga(struct drm_device *dev) | |
8536 | { | |
8537 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8538 | u8 sr1; | |
8539 | u32 vga_reg; | |
8540 | ||
8541 | if (HAS_PCH_SPLIT(dev)) | |
8542 | vga_reg = CPU_VGACNTRL; | |
8543 | else | |
8544 | vga_reg = VGACNTRL; | |
8545 | ||
8546 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
8547 | outb(1, VGA_SR_INDEX); | |
8548 | sr1 = inb(VGA_SR_DATA); | |
8549 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
8550 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
8551 | udelay(300); | |
8552 | ||
8553 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
8554 | POSTING_READ(vga_reg); | |
8555 | } | |
8556 | ||
79e53945 JB |
8557 | void intel_modeset_init(struct drm_device *dev) |
8558 | { | |
652c393a | 8559 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
8560 | int i; |
8561 | ||
8562 | drm_mode_config_init(dev); | |
8563 | ||
8564 | dev->mode_config.min_width = 0; | |
8565 | dev->mode_config.min_height = 0; | |
8566 | ||
8567 | dev->mode_config.funcs = (void *)&intel_mode_funcs; | |
8568 | ||
b690e96c JB |
8569 | intel_init_quirks(dev); |
8570 | ||
e70236a8 JB |
8571 | intel_init_display(dev); |
8572 | ||
a6c45cf0 CW |
8573 | if (IS_GEN2(dev)) { |
8574 | dev->mode_config.max_width = 2048; | |
8575 | dev->mode_config.max_height = 2048; | |
8576 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
8577 | dev->mode_config.max_width = 4096; |
8578 | dev->mode_config.max_height = 4096; | |
79e53945 | 8579 | } else { |
a6c45cf0 CW |
8580 | dev->mode_config.max_width = 8192; |
8581 | dev->mode_config.max_height = 8192; | |
79e53945 | 8582 | } |
35c3047a | 8583 | dev->mode_config.fb_base = dev->agp->base; |
79e53945 | 8584 | |
28c97730 | 8585 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
a3524f1b | 8586 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
79e53945 | 8587 | |
a3524f1b | 8588 | for (i = 0; i < dev_priv->num_pipe; i++) { |
79e53945 JB |
8589 | intel_crtc_init(dev, i); |
8590 | } | |
8591 | ||
9cce37f4 JB |
8592 | /* Just disable it once at startup */ |
8593 | i915_disable_vga(dev); | |
79e53945 | 8594 | intel_setup_outputs(dev); |
652c393a | 8595 | |
645c62a5 | 8596 | intel_init_clock_gating(dev); |
9cce37f4 | 8597 | |
7648fa99 | 8598 | if (IS_IRONLAKE_M(dev)) { |
f97108d1 | 8599 | ironlake_enable_drps(dev); |
7648fa99 JB |
8600 | intel_init_emon(dev); |
8601 | } | |
f97108d1 | 8602 | |
1c70c0ce | 8603 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
3b8d8d91 | 8604 | gen6_enable_rps(dev_priv); |
23b2f8bb JB |
8605 | gen6_update_ring_freq(dev_priv); |
8606 | } | |
3b8d8d91 | 8607 | |
652c393a JB |
8608 | INIT_WORK(&dev_priv->idle_work, intel_idle_update); |
8609 | setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, | |
8610 | (unsigned long)dev); | |
2c7111db CW |
8611 | } |
8612 | ||
8613 | void intel_modeset_gem_init(struct drm_device *dev) | |
8614 | { | |
8615 | if (IS_IRONLAKE_M(dev)) | |
8616 | ironlake_enable_rc6(dev); | |
02e792fb DV |
8617 | |
8618 | intel_setup_overlay(dev); | |
79e53945 JB |
8619 | } |
8620 | ||
8621 | void intel_modeset_cleanup(struct drm_device *dev) | |
8622 | { | |
652c393a JB |
8623 | struct drm_i915_private *dev_priv = dev->dev_private; |
8624 | struct drm_crtc *crtc; | |
8625 | struct intel_crtc *intel_crtc; | |
8626 | ||
f87ea761 | 8627 | drm_kms_helper_poll_fini(dev); |
652c393a JB |
8628 | mutex_lock(&dev->struct_mutex); |
8629 | ||
723bfd70 JB |
8630 | intel_unregister_dsm_handler(); |
8631 | ||
8632 | ||
652c393a JB |
8633 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
8634 | /* Skip inactive CRTCs */ | |
8635 | if (!crtc->fb) | |
8636 | continue; | |
8637 | ||
8638 | intel_crtc = to_intel_crtc(crtc); | |
3dec0095 | 8639 | intel_increase_pllclock(crtc); |
652c393a JB |
8640 | } |
8641 | ||
973d04f9 | 8642 | intel_disable_fbc(dev); |
e70236a8 | 8643 | |
f97108d1 JB |
8644 | if (IS_IRONLAKE_M(dev)) |
8645 | ironlake_disable_drps(dev); | |
1c70c0ce | 8646 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
3b8d8d91 | 8647 | gen6_disable_rps(dev); |
f97108d1 | 8648 | |
d5bb081b JB |
8649 | if (IS_IRONLAKE_M(dev)) |
8650 | ironlake_disable_rc6(dev); | |
0cdab21f | 8651 | |
69341a5e KH |
8652 | mutex_unlock(&dev->struct_mutex); |
8653 | ||
6c0d9350 DV |
8654 | /* Disable the irq before mode object teardown, for the irq might |
8655 | * enqueue unpin/hotplug work. */ | |
8656 | drm_irq_uninstall(dev); | |
8657 | cancel_work_sync(&dev_priv->hotplug_work); | |
8658 | ||
1630fe75 CW |
8659 | /* flush any delayed tasks or pending work */ |
8660 | flush_scheduled_work(); | |
8661 | ||
3dec0095 DV |
8662 | /* Shut off idle work before the crtcs get freed. */ |
8663 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
8664 | intel_crtc = to_intel_crtc(crtc); | |
8665 | del_timer_sync(&intel_crtc->idle_timer); | |
8666 | } | |
8667 | del_timer_sync(&dev_priv->idle_timer); | |
8668 | cancel_work_sync(&dev_priv->idle_work); | |
8669 | ||
79e53945 JB |
8670 | drm_mode_config_cleanup(dev); |
8671 | } | |
8672 | ||
f1c79df3 ZW |
8673 | /* |
8674 | * Return which encoder is currently attached for connector. | |
8675 | */ | |
df0e9248 | 8676 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 8677 | { |
df0e9248 CW |
8678 | return &intel_attached_encoder(connector)->base; |
8679 | } | |
f1c79df3 | 8680 | |
df0e9248 CW |
8681 | void intel_connector_attach_encoder(struct intel_connector *connector, |
8682 | struct intel_encoder *encoder) | |
8683 | { | |
8684 | connector->encoder = encoder; | |
8685 | drm_mode_connector_attach_encoder(&connector->base, | |
8686 | &encoder->base); | |
79e53945 | 8687 | } |
28d52043 DA |
8688 | |
8689 | /* | |
8690 | * set vga decode state - true == enable VGA decode | |
8691 | */ | |
8692 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
8693 | { | |
8694 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8695 | u16 gmch_ctrl; | |
8696 | ||
8697 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
8698 | if (state) | |
8699 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
8700 | else | |
8701 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
8702 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
8703 | return 0; | |
8704 | } | |
c4a1d9e4 CW |
8705 | |
8706 | #ifdef CONFIG_DEBUG_FS | |
8707 | #include <linux/seq_file.h> | |
8708 | ||
8709 | struct intel_display_error_state { | |
8710 | struct intel_cursor_error_state { | |
8711 | u32 control; | |
8712 | u32 position; | |
8713 | u32 base; | |
8714 | u32 size; | |
8715 | } cursor[2]; | |
8716 | ||
8717 | struct intel_pipe_error_state { | |
8718 | u32 conf; | |
8719 | u32 source; | |
8720 | ||
8721 | u32 htotal; | |
8722 | u32 hblank; | |
8723 | u32 hsync; | |
8724 | u32 vtotal; | |
8725 | u32 vblank; | |
8726 | u32 vsync; | |
8727 | } pipe[2]; | |
8728 | ||
8729 | struct intel_plane_error_state { | |
8730 | u32 control; | |
8731 | u32 stride; | |
8732 | u32 size; | |
8733 | u32 pos; | |
8734 | u32 addr; | |
8735 | u32 surface; | |
8736 | u32 tile_offset; | |
8737 | } plane[2]; | |
8738 | }; | |
8739 | ||
8740 | struct intel_display_error_state * | |
8741 | intel_display_capture_error_state(struct drm_device *dev) | |
8742 | { | |
0206e353 | 8743 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
8744 | struct intel_display_error_state *error; |
8745 | int i; | |
8746 | ||
8747 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
8748 | if (error == NULL) | |
8749 | return NULL; | |
8750 | ||
8751 | for (i = 0; i < 2; i++) { | |
8752 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
8753 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
8754 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
8755 | ||
8756 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
8757 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
8758 | error->plane[i].size = I915_READ(DSPSIZE(i)); | |
0206e353 | 8759 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
c4a1d9e4 CW |
8760 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
8761 | if (INTEL_INFO(dev)->gen >= 4) { | |
8762 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
8763 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
8764 | } | |
8765 | ||
8766 | error->pipe[i].conf = I915_READ(PIPECONF(i)); | |
8767 | error->pipe[i].source = I915_READ(PIPESRC(i)); | |
8768 | error->pipe[i].htotal = I915_READ(HTOTAL(i)); | |
8769 | error->pipe[i].hblank = I915_READ(HBLANK(i)); | |
8770 | error->pipe[i].hsync = I915_READ(HSYNC(i)); | |
8771 | error->pipe[i].vtotal = I915_READ(VTOTAL(i)); | |
8772 | error->pipe[i].vblank = I915_READ(VBLANK(i)); | |
8773 | error->pipe[i].vsync = I915_READ(VSYNC(i)); | |
8774 | } | |
8775 | ||
8776 | return error; | |
8777 | } | |
8778 | ||
8779 | void | |
8780 | intel_display_print_error_state(struct seq_file *m, | |
8781 | struct drm_device *dev, | |
8782 | struct intel_display_error_state *error) | |
8783 | { | |
8784 | int i; | |
8785 | ||
8786 | for (i = 0; i < 2; i++) { | |
8787 | seq_printf(m, "Pipe [%d]:\n", i); | |
8788 | seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); | |
8789 | seq_printf(m, " SRC: %08x\n", error->pipe[i].source); | |
8790 | seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); | |
8791 | seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); | |
8792 | seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); | |
8793 | seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); | |
8794 | seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); | |
8795 | seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); | |
8796 | ||
8797 | seq_printf(m, "Plane [%d]:\n", i); | |
8798 | seq_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
8799 | seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
8800 | seq_printf(m, " SIZE: %08x\n", error->plane[i].size); | |
8801 | seq_printf(m, " POS: %08x\n", error->plane[i].pos); | |
8802 | seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); | |
8803 | if (INTEL_INFO(dev)->gen >= 4) { | |
8804 | seq_printf(m, " SURF: %08x\n", error->plane[i].surface); | |
8805 | seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
8806 | } | |
8807 | ||
8808 | seq_printf(m, "Cursor [%d]:\n", i); | |
8809 | seq_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
8810 | seq_printf(m, " POS: %08x\n", error->cursor[i].position); | |
8811 | seq_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
8812 | } | |
8813 | } | |
8814 | #endif |