Revert "drm/i915: Avoid using PIPE_CONTROL on Ironlake"
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
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1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
c1c7af60
JB
27#include <linux/module.h>
28#include <linux/input.h>
79e53945 29#include <linux/i2c.h>
7662c8bd 30#include <linux/kernel.h>
5a0e3ad6 31#include <linux/slab.h>
9cce37f4 32#include <linux/vgaarb.h>
79e53945
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33#include "drmP.h"
34#include "intel_drv.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
e5510fac 37#include "i915_trace.h"
ab2c0672 38#include "drm_dp_helper.h"
79e53945
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39
40#include "drm_crtc_helper.h"
41
32f9d658
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42#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
79e53945 44bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
7662c8bd 45static void intel_update_watermarks(struct drm_device *dev);
3dec0095 46static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 47static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
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48
49typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59} intel_clock_t;
60
61typedef struct {
62 int min, max;
63} intel_range_t;
64
65typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68} intel_p2_t;
69
70#define INTEL_P2_NUM 2
d4906093
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71typedef struct intel_limit intel_limit_t;
72struct intel_limit {
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73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
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75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77};
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78
79#define I8XX_DOT_MIN 25000
80#define I8XX_DOT_MAX 350000
81#define I8XX_VCO_MIN 930000
82#define I8XX_VCO_MAX 1400000
83#define I8XX_N_MIN 3
84#define I8XX_N_MAX 16
85#define I8XX_M_MIN 96
86#define I8XX_M_MAX 140
87#define I8XX_M1_MIN 18
88#define I8XX_M1_MAX 26
89#define I8XX_M2_MIN 6
90#define I8XX_M2_MAX 16
91#define I8XX_P_MIN 4
92#define I8XX_P_MAX 128
93#define I8XX_P1_MIN 2
94#define I8XX_P1_MAX 33
95#define I8XX_P1_LVDS_MIN 1
96#define I8XX_P1_LVDS_MAX 6
97#define I8XX_P2_SLOW 4
98#define I8XX_P2_FAST 2
99#define I8XX_P2_LVDS_SLOW 14
0c2e3952 100#define I8XX_P2_LVDS_FAST 7
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101#define I8XX_P2_SLOW_LIMIT 165000
102
103#define I9XX_DOT_MIN 20000
104#define I9XX_DOT_MAX 400000
105#define I9XX_VCO_MIN 1400000
106#define I9XX_VCO_MAX 2800000
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107#define PINEVIEW_VCO_MIN 1700000
108#define PINEVIEW_VCO_MAX 3500000
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109#define I9XX_N_MIN 1
110#define I9XX_N_MAX 6
f2b115e6
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111/* Pineview's Ncounter is a ring counter */
112#define PINEVIEW_N_MIN 3
113#define PINEVIEW_N_MAX 6
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114#define I9XX_M_MIN 70
115#define I9XX_M_MAX 120
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116#define PINEVIEW_M_MIN 2
117#define PINEVIEW_M_MAX 256
79e53945 118#define I9XX_M1_MIN 10
f3cade5c 119#define I9XX_M1_MAX 22
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120#define I9XX_M2_MIN 5
121#define I9XX_M2_MAX 9
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122/* Pineview M1 is reserved, and must be 0 */
123#define PINEVIEW_M1_MIN 0
124#define PINEVIEW_M1_MAX 0
125#define PINEVIEW_M2_MIN 0
126#define PINEVIEW_M2_MAX 254
79e53945
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127#define I9XX_P_SDVO_DAC_MIN 5
128#define I9XX_P_SDVO_DAC_MAX 80
129#define I9XX_P_LVDS_MIN 7
130#define I9XX_P_LVDS_MAX 98
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131#define PINEVIEW_P_LVDS_MIN 7
132#define PINEVIEW_P_LVDS_MAX 112
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133#define I9XX_P1_MIN 1
134#define I9XX_P1_MAX 8
135#define I9XX_P2_SDVO_DAC_SLOW 10
136#define I9XX_P2_SDVO_DAC_FAST 5
137#define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138#define I9XX_P2_LVDS_SLOW 14
139#define I9XX_P2_LVDS_FAST 7
140#define I9XX_P2_LVDS_SLOW_LIMIT 112000
141
044c7c41
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142/*The parameter is for SDVO on G4x platform*/
143#define G4X_DOT_SDVO_MIN 25000
144#define G4X_DOT_SDVO_MAX 270000
145#define G4X_VCO_MIN 1750000
146#define G4X_VCO_MAX 3500000
147#define G4X_N_SDVO_MIN 1
148#define G4X_N_SDVO_MAX 4
149#define G4X_M_SDVO_MIN 104
150#define G4X_M_SDVO_MAX 138
151#define G4X_M1_SDVO_MIN 17
152#define G4X_M1_SDVO_MAX 23
153#define G4X_M2_SDVO_MIN 5
154#define G4X_M2_SDVO_MAX 11
155#define G4X_P_SDVO_MIN 10
156#define G4X_P_SDVO_MAX 30
157#define G4X_P1_SDVO_MIN 1
158#define G4X_P1_SDVO_MAX 3
159#define G4X_P2_SDVO_SLOW 10
160#define G4X_P2_SDVO_FAST 10
161#define G4X_P2_SDVO_LIMIT 270000
162
163/*The parameter is for HDMI_DAC on G4x platform*/
164#define G4X_DOT_HDMI_DAC_MIN 22000
165#define G4X_DOT_HDMI_DAC_MAX 400000
166#define G4X_N_HDMI_DAC_MIN 1
167#define G4X_N_HDMI_DAC_MAX 4
168#define G4X_M_HDMI_DAC_MIN 104
169#define G4X_M_HDMI_DAC_MAX 138
170#define G4X_M1_HDMI_DAC_MIN 16
171#define G4X_M1_HDMI_DAC_MAX 23
172#define G4X_M2_HDMI_DAC_MIN 5
173#define G4X_M2_HDMI_DAC_MAX 11
174#define G4X_P_HDMI_DAC_MIN 5
175#define G4X_P_HDMI_DAC_MAX 80
176#define G4X_P1_HDMI_DAC_MIN 1
177#define G4X_P1_HDMI_DAC_MAX 8
178#define G4X_P2_HDMI_DAC_SLOW 10
179#define G4X_P2_HDMI_DAC_FAST 5
180#define G4X_P2_HDMI_DAC_LIMIT 165000
181
182/*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183#define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184#define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185#define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186#define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187#define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188#define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189#define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190#define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191#define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192#define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193#define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194#define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195#define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196#define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197#define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198#define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199#define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
200
201/*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202#define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203#define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204#define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205#define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206#define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207#define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208#define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209#define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210#define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211#define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212#define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213#define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214#define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215#define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216#define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217#define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218#define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
219
a4fc5ed6
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220/*The parameter is for DISPLAY PORT on G4x platform*/
221#define G4X_DOT_DISPLAY_PORT_MIN 161670
222#define G4X_DOT_DISPLAY_PORT_MAX 227000
223#define G4X_N_DISPLAY_PORT_MIN 1
224#define G4X_N_DISPLAY_PORT_MAX 2
225#define G4X_M_DISPLAY_PORT_MIN 97
226#define G4X_M_DISPLAY_PORT_MAX 108
227#define G4X_M1_DISPLAY_PORT_MIN 0x10
228#define G4X_M1_DISPLAY_PORT_MAX 0x12
229#define G4X_M2_DISPLAY_PORT_MIN 0x05
230#define G4X_M2_DISPLAY_PORT_MAX 0x06
231#define G4X_P_DISPLAY_PORT_MIN 10
232#define G4X_P_DISPLAY_PORT_MAX 20
233#define G4X_P1_DISPLAY_PORT_MIN 1
234#define G4X_P1_DISPLAY_PORT_MAX 2
235#define G4X_P2_DISPLAY_PORT_SLOW 10
236#define G4X_P2_DISPLAY_PORT_FAST 10
237#define G4X_P2_DISPLAY_PORT_LIMIT 0
238
bad720ff 239/* Ironlake / Sandybridge */
2c07245f
ZW
240/* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
242 */
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243#define IRONLAKE_DOT_MIN 25000
244#define IRONLAKE_DOT_MAX 350000
245#define IRONLAKE_VCO_MIN 1760000
246#define IRONLAKE_VCO_MAX 3510000
f2b115e6 247#define IRONLAKE_M1_MIN 12
a59e385e 248#define IRONLAKE_M1_MAX 22
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AJ
249#define IRONLAKE_M2_MIN 5
250#define IRONLAKE_M2_MAX 9
f2b115e6 251#define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
2c07245f 252
b91ad0ec
ZW
253/* We have parameter ranges for different type of outputs. */
254
255/* DAC & HDMI Refclk 120Mhz */
256#define IRONLAKE_DAC_N_MIN 1
257#define IRONLAKE_DAC_N_MAX 5
258#define IRONLAKE_DAC_M_MIN 79
259#define IRONLAKE_DAC_M_MAX 127
260#define IRONLAKE_DAC_P_MIN 5
261#define IRONLAKE_DAC_P_MAX 80
262#define IRONLAKE_DAC_P1_MIN 1
263#define IRONLAKE_DAC_P1_MAX 8
264#define IRONLAKE_DAC_P2_SLOW 10
265#define IRONLAKE_DAC_P2_FAST 5
266
267/* LVDS single-channel 120Mhz refclk */
268#define IRONLAKE_LVDS_S_N_MIN 1
269#define IRONLAKE_LVDS_S_N_MAX 3
270#define IRONLAKE_LVDS_S_M_MIN 79
271#define IRONLAKE_LVDS_S_M_MAX 118
272#define IRONLAKE_LVDS_S_P_MIN 28
273#define IRONLAKE_LVDS_S_P_MAX 112
274#define IRONLAKE_LVDS_S_P1_MIN 2
275#define IRONLAKE_LVDS_S_P1_MAX 8
276#define IRONLAKE_LVDS_S_P2_SLOW 14
277#define IRONLAKE_LVDS_S_P2_FAST 14
278
279/* LVDS dual-channel 120Mhz refclk */
280#define IRONLAKE_LVDS_D_N_MIN 1
281#define IRONLAKE_LVDS_D_N_MAX 3
282#define IRONLAKE_LVDS_D_M_MIN 79
283#define IRONLAKE_LVDS_D_M_MAX 127
284#define IRONLAKE_LVDS_D_P_MIN 14
285#define IRONLAKE_LVDS_D_P_MAX 56
286#define IRONLAKE_LVDS_D_P1_MIN 2
287#define IRONLAKE_LVDS_D_P1_MAX 8
288#define IRONLAKE_LVDS_D_P2_SLOW 7
289#define IRONLAKE_LVDS_D_P2_FAST 7
290
291/* LVDS single-channel 100Mhz refclk */
292#define IRONLAKE_LVDS_S_SSC_N_MIN 1
293#define IRONLAKE_LVDS_S_SSC_N_MAX 2
294#define IRONLAKE_LVDS_S_SSC_M_MIN 79
295#define IRONLAKE_LVDS_S_SSC_M_MAX 126
296#define IRONLAKE_LVDS_S_SSC_P_MIN 28
297#define IRONLAKE_LVDS_S_SSC_P_MAX 112
298#define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299#define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300#define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301#define IRONLAKE_LVDS_S_SSC_P2_FAST 14
302
303/* LVDS dual-channel 100Mhz refclk */
304#define IRONLAKE_LVDS_D_SSC_N_MIN 1
305#define IRONLAKE_LVDS_D_SSC_N_MAX 3
306#define IRONLAKE_LVDS_D_SSC_M_MIN 79
307#define IRONLAKE_LVDS_D_SSC_M_MAX 126
308#define IRONLAKE_LVDS_D_SSC_P_MIN 14
309#define IRONLAKE_LVDS_D_SSC_P_MAX 42
310#define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311#define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312#define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313#define IRONLAKE_LVDS_D_SSC_P2_FAST 7
314
315/* DisplayPort */
316#define IRONLAKE_DP_N_MIN 1
317#define IRONLAKE_DP_N_MAX 2
318#define IRONLAKE_DP_M_MIN 81
319#define IRONLAKE_DP_M_MAX 90
320#define IRONLAKE_DP_P_MIN 10
321#define IRONLAKE_DP_P_MAX 20
322#define IRONLAKE_DP_P2_FAST 10
323#define IRONLAKE_DP_P2_SLOW 10
324#define IRONLAKE_DP_P2_LIMIT 0
325#define IRONLAKE_DP_P1_MIN 1
326#define IRONLAKE_DP_P1_MAX 2
4547668a 327
2377b741
JB
328/* FDI */
329#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
330
d4906093
ML
331static bool
332intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
333 int target, int refclk, intel_clock_t *best_clock);
334static bool
335intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
336 int target, int refclk, intel_clock_t *best_clock);
79e53945 337
a4fc5ed6
KP
338static bool
339intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
340 int target, int refclk, intel_clock_t *best_clock);
5eb08b69 341static bool
f2b115e6
AJ
342intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
343 int target, int refclk, intel_clock_t *best_clock);
a4fc5ed6 344
021357ac
CW
345static inline u32 /* units of 100MHz */
346intel_fdi_link_freq(struct drm_device *dev)
347{
8b99e68c
CW
348 if (IS_GEN5(dev)) {
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
351 } else
352 return 27;
021357ac
CW
353}
354
e4b36699 355static const intel_limit_t intel_limits_i8xx_dvo = {
79e53945
JB
356 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
357 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
358 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
359 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
360 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
361 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
362 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
363 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
364 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
365 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
d4906093 366 .find_pll = intel_find_best_PLL,
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367};
368
369static const intel_limit_t intel_limits_i8xx_lvds = {
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370 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
371 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
372 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
373 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
374 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
375 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
376 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
377 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
378 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
379 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
d4906093 380 .find_pll = intel_find_best_PLL,
e4b36699
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381};
382
383static const intel_limit_t intel_limits_i9xx_sdvo = {
79e53945
JB
384 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
385 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
386 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
387 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
388 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
389 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
390 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
391 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
392 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
393 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
d4906093 394 .find_pll = intel_find_best_PLL,
e4b36699
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395};
396
397static const intel_limit_t intel_limits_i9xx_lvds = {
79e53945
JB
398 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
399 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
400 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
401 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
402 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
403 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
404 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
405 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
406 /* The single-channel range is 25-112Mhz, and dual-channel
407 * is 80-224Mhz. Prefer single channel as much as possible.
408 */
409 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
410 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
d4906093 411 .find_pll = intel_find_best_PLL,
e4b36699
KP
412};
413
044c7c41 414 /* below parameter and function is for G4X Chipset Family*/
e4b36699 415static const intel_limit_t intel_limits_g4x_sdvo = {
044c7c41
ML
416 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
417 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
418 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
419 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
420 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
421 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
422 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
423 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
424 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
425 .p2_slow = G4X_P2_SDVO_SLOW,
426 .p2_fast = G4X_P2_SDVO_FAST
427 },
d4906093 428 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP
429};
430
431static const intel_limit_t intel_limits_g4x_hdmi = {
044c7c41
ML
432 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
433 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
434 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
435 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
436 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
437 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
438 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
439 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
440 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
441 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
442 .p2_fast = G4X_P2_HDMI_DAC_FAST
443 },
d4906093 444 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP
445};
446
447static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
044c7c41
ML
448 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
449 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
450 .vco = { .min = G4X_VCO_MIN,
451 .max = G4X_VCO_MAX },
452 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
453 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
454 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
455 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
456 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
457 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
458 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
459 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
460 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
461 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
462 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
463 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
464 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
465 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
466 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
467 },
d4906093 468 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP
469};
470
471static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
044c7c41
ML
472 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
473 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
474 .vco = { .min = G4X_VCO_MIN,
475 .max = G4X_VCO_MAX },
476 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
477 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
478 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
479 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
480 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
481 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
482 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
483 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
484 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
485 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
486 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
487 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
488 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
489 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
490 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
491 },
d4906093 492 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP
493};
494
495static const intel_limit_t intel_limits_g4x_display_port = {
a4fc5ed6
KP
496 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
497 .max = G4X_DOT_DISPLAY_PORT_MAX },
498 .vco = { .min = G4X_VCO_MIN,
499 .max = G4X_VCO_MAX},
500 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
501 .max = G4X_N_DISPLAY_PORT_MAX },
502 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
503 .max = G4X_M_DISPLAY_PORT_MAX },
504 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
505 .max = G4X_M1_DISPLAY_PORT_MAX },
506 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
507 .max = G4X_M2_DISPLAY_PORT_MAX },
508 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
509 .max = G4X_P_DISPLAY_PORT_MAX },
510 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
511 .max = G4X_P1_DISPLAY_PORT_MAX},
512 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
513 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
514 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
515 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP
516};
517
f2b115e6 518static const intel_limit_t intel_limits_pineview_sdvo = {
2177832f 519 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
f2b115e6
AJ
520 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
521 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
522 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
523 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
524 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
2177832f
SL
525 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
526 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
527 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
528 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
6115707b 529 .find_pll = intel_find_best_PLL,
e4b36699
KP
530};
531
f2b115e6 532static const intel_limit_t intel_limits_pineview_lvds = {
2177832f 533 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
f2b115e6
AJ
534 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
535 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
536 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
537 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
538 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
539 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
2177832f 540 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
f2b115e6 541 /* Pineview only supports single-channel mode. */
2177832f
SL
542 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
543 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
6115707b 544 .find_pll = intel_find_best_PLL,
e4b36699
KP
545};
546
b91ad0ec 547static const intel_limit_t intel_limits_ironlake_dac = {
f2b115e6
AJ
548 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
549 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
b91ad0ec
ZW
550 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
551 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
f2b115e6
AJ
552 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
553 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
b91ad0ec
ZW
554 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
555 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
f2b115e6 556 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
b91ad0ec
ZW
557 .p2_slow = IRONLAKE_DAC_P2_SLOW,
558 .p2_fast = IRONLAKE_DAC_P2_FAST },
4547668a 559 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP
560};
561
b91ad0ec 562static const intel_limit_t intel_limits_ironlake_single_lvds = {
f2b115e6
AJ
563 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
564 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
b91ad0ec
ZW
565 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
566 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
f2b115e6
AJ
567 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
568 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
b91ad0ec
ZW
569 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
570 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
f2b115e6 571 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
b91ad0ec
ZW
572 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
573 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
574 .find_pll = intel_g4x_find_best_PLL,
575};
576
577static const intel_limit_t intel_limits_ironlake_dual_lvds = {
578 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
579 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
580 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
581 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
582 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
583 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
584 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
585 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
586 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
587 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
588 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
589 .find_pll = intel_g4x_find_best_PLL,
590};
591
592static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
593 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
594 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
595 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
596 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
597 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
598 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
599 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
600 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
601 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
602 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
603 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
604 .find_pll = intel_g4x_find_best_PLL,
605};
606
607static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
608 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
609 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
610 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
611 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
612 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
613 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
614 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
615 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
616 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
617 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
618 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
4547668a
ZY
619 .find_pll = intel_g4x_find_best_PLL,
620};
621
622static const intel_limit_t intel_limits_ironlake_display_port = {
623 .dot = { .min = IRONLAKE_DOT_MIN,
624 .max = IRONLAKE_DOT_MAX },
625 .vco = { .min = IRONLAKE_VCO_MIN,
626 .max = IRONLAKE_VCO_MAX},
b91ad0ec
ZW
627 .n = { .min = IRONLAKE_DP_N_MIN,
628 .max = IRONLAKE_DP_N_MAX },
629 .m = { .min = IRONLAKE_DP_M_MIN,
630 .max = IRONLAKE_DP_M_MAX },
4547668a
ZY
631 .m1 = { .min = IRONLAKE_M1_MIN,
632 .max = IRONLAKE_M1_MAX },
633 .m2 = { .min = IRONLAKE_M2_MIN,
634 .max = IRONLAKE_M2_MAX },
b91ad0ec
ZW
635 .p = { .min = IRONLAKE_DP_P_MIN,
636 .max = IRONLAKE_DP_P_MAX },
637 .p1 = { .min = IRONLAKE_DP_P1_MIN,
638 .max = IRONLAKE_DP_P1_MAX},
639 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
640 .p2_slow = IRONLAKE_DP_P2_SLOW,
641 .p2_fast = IRONLAKE_DP_P2_FAST },
4547668a 642 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB
643};
644
1b894b59
CW
645static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
646 int refclk)
2c07245f 647{
b91ad0ec
ZW
648 struct drm_device *dev = crtc->dev;
649 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 650 const intel_limit_t *limit;
b91ad0ec
ZW
651
652 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b91ad0ec
ZW
653 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
654 LVDS_CLKB_POWER_UP) {
655 /* LVDS dual channel */
1b894b59 656 if (refclk == 100000)
b91ad0ec
ZW
657 limit = &intel_limits_ironlake_dual_lvds_100m;
658 else
659 limit = &intel_limits_ironlake_dual_lvds;
660 } else {
1b894b59 661 if (refclk == 100000)
b91ad0ec
ZW
662 limit = &intel_limits_ironlake_single_lvds_100m;
663 else
664 limit = &intel_limits_ironlake_single_lvds;
665 }
666 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY
667 HAS_eDP)
668 limit = &intel_limits_ironlake_display_port;
2c07245f 669 else
b91ad0ec 670 limit = &intel_limits_ironlake_dac;
2c07245f
ZW
671
672 return limit;
673}
674
044c7c41
ML
675static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
676{
677 struct drm_device *dev = crtc->dev;
678 struct drm_i915_private *dev_priv = dev->dev_private;
679 const intel_limit_t *limit;
680
681 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
682 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
683 LVDS_CLKB_POWER_UP)
684 /* LVDS with dual channel */
e4b36699 685 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML
686 else
687 /* LVDS with dual channel */
e4b36699 688 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML
689 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
690 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 691 limit = &intel_limits_g4x_hdmi;
044c7c41 692 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 693 limit = &intel_limits_g4x_sdvo;
a4fc5ed6 694 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 695 limit = &intel_limits_g4x_display_port;
044c7c41 696 } else /* The option is for other outputs */
e4b36699 697 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML
698
699 return limit;
700}
701
1b894b59 702static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB
703{
704 struct drm_device *dev = crtc->dev;
705 const intel_limit_t *limit;
706
bad720ff 707 if (HAS_PCH_SPLIT(dev))
1b894b59 708 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 709 else if (IS_G4X(dev)) {
044c7c41 710 limit = intel_g4x_limit(crtc);
f2b115e6 711 } else if (IS_PINEVIEW(dev)) {
2177832f 712 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 713 limit = &intel_limits_pineview_lvds;
2177832f 714 else
f2b115e6 715 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW
716 } else if (!IS_GEN2(dev)) {
717 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
718 limit = &intel_limits_i9xx_lvds;
719 else
720 limit = &intel_limits_i9xx_sdvo;
79e53945
JB
721 } else {
722 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 723 limit = &intel_limits_i8xx_lvds;
79e53945 724 else
e4b36699 725 limit = &intel_limits_i8xx_dvo;
79e53945
JB
726 }
727 return limit;
728}
729
f2b115e6
AJ
730/* m1 is reserved as 0 in Pineview, n is a ring counter */
731static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 732{
2177832f
SL
733 clock->m = clock->m2 + 2;
734 clock->p = clock->p1 * clock->p2;
735 clock->vco = refclk * clock->m / clock->n;
736 clock->dot = clock->vco / clock->p;
737}
738
739static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
740{
f2b115e6
AJ
741 if (IS_PINEVIEW(dev)) {
742 pineview_clock(refclk, clock);
2177832f
SL
743 return;
744 }
79e53945
JB
745 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
746 clock->p = clock->p1 * clock->p2;
747 clock->vco = refclk * clock->m / (clock->n + 2);
748 clock->dot = clock->vco / clock->p;
749}
750
79e53945
JB
751/**
752 * Returns whether any output on the specified pipe is of the specified type
753 */
4ef69c7a 754bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 755{
4ef69c7a
CW
756 struct drm_device *dev = crtc->dev;
757 struct drm_mode_config *mode_config = &dev->mode_config;
758 struct intel_encoder *encoder;
759
760 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
761 if (encoder->base.crtc == crtc && encoder->type == type)
762 return true;
763
764 return false;
79e53945
JB
765}
766
7c04d1d9 767#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB
768/**
769 * Returns whether the given set of divisors are valid for a given refclk with
770 * the given connectors.
771 */
772
1b894b59
CW
773static bool intel_PLL_is_valid(struct drm_device *dev,
774 const intel_limit_t *limit,
775 const intel_clock_t *clock)
79e53945 776{
79e53945
JB
777 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
778 INTELPllInvalid ("p1 out of range\n");
779 if (clock->p < limit->p.min || limit->p.max < clock->p)
780 INTELPllInvalid ("p out of range\n");
781 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
782 INTELPllInvalid ("m2 out of range\n");
783 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
784 INTELPllInvalid ("m1 out of range\n");
f2b115e6 785 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
79e53945
JB
786 INTELPllInvalid ("m1 <= m2\n");
787 if (clock->m < limit->m.min || limit->m.max < clock->m)
788 INTELPllInvalid ("m out of range\n");
789 if (clock->n < limit->n.min || limit->n.max < clock->n)
790 INTELPllInvalid ("n out of range\n");
791 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
792 INTELPllInvalid ("vco out of range\n");
793 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
794 * connector, etc., rather than just a single range.
795 */
796 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
797 INTELPllInvalid ("dot out of range\n");
798
799 return true;
800}
801
d4906093
ML
802static bool
803intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
804 int target, int refclk, intel_clock_t *best_clock)
805
79e53945
JB
806{
807 struct drm_device *dev = crtc->dev;
808 struct drm_i915_private *dev_priv = dev->dev_private;
809 intel_clock_t clock;
79e53945
JB
810 int err = target;
811
bc5e5718 812 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 813 (I915_READ(LVDS)) != 0) {
79e53945
JB
814 /*
815 * For LVDS, if the panel is on, just rely on its current
816 * settings for dual-channel. We haven't figured out how to
817 * reliably set up different single/dual channel state, if we
818 * even can.
819 */
820 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
821 LVDS_CLKB_POWER_UP)
822 clock.p2 = limit->p2.p2_fast;
823 else
824 clock.p2 = limit->p2.p2_slow;
825 } else {
826 if (target < limit->p2.dot_limit)
827 clock.p2 = limit->p2.p2_slow;
828 else
829 clock.p2 = limit->p2.p2_fast;
830 }
831
832 memset (best_clock, 0, sizeof (*best_clock));
833
42158660
ZY
834 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
835 clock.m1++) {
836 for (clock.m2 = limit->m2.min;
837 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ
838 /* m1 is always 0 in Pineview */
839 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY
840 break;
841 for (clock.n = limit->n.min;
842 clock.n <= limit->n.max; clock.n++) {
843 for (clock.p1 = limit->p1.min;
844 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB
845 int this_err;
846
2177832f 847 intel_clock(dev, refclk, &clock);
1b894b59
CW
848 if (!intel_PLL_is_valid(dev, limit,
849 &clock))
79e53945
JB
850 continue;
851
852 this_err = abs(clock.dot - target);
853 if (this_err < err) {
854 *best_clock = clock;
855 err = this_err;
856 }
857 }
858 }
859 }
860 }
861
862 return (err != target);
863}
864
d4906093
ML
865static bool
866intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
867 int target, int refclk, intel_clock_t *best_clock)
868{
869 struct drm_device *dev = crtc->dev;
870 struct drm_i915_private *dev_priv = dev->dev_private;
871 intel_clock_t clock;
872 int max_n;
873 bool found;
6ba770dc
AJ
874 /* approximately equals target * 0.00585 */
875 int err_most = (target >> 8) + (target >> 9);
d4906093
ML
876 found = false;
877
878 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY
879 int lvds_reg;
880
c619eed4 881 if (HAS_PCH_SPLIT(dev))
4547668a
ZY
882 lvds_reg = PCH_LVDS;
883 else
884 lvds_reg = LVDS;
885 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML
886 LVDS_CLKB_POWER_UP)
887 clock.p2 = limit->p2.p2_fast;
888 else
889 clock.p2 = limit->p2.p2_slow;
890 } else {
891 if (target < limit->p2.dot_limit)
892 clock.p2 = limit->p2.p2_slow;
893 else
894 clock.p2 = limit->p2.p2_fast;
895 }
896
897 memset(best_clock, 0, sizeof(*best_clock));
898 max_n = limit->n.max;
f77f13e2 899 /* based on hardware requirement, prefer smaller n to precision */
d4906093 900 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 901 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML
902 for (clock.m1 = limit->m1.max;
903 clock.m1 >= limit->m1.min; clock.m1--) {
904 for (clock.m2 = limit->m2.max;
905 clock.m2 >= limit->m2.min; clock.m2--) {
906 for (clock.p1 = limit->p1.max;
907 clock.p1 >= limit->p1.min; clock.p1--) {
908 int this_err;
909
2177832f 910 intel_clock(dev, refclk, &clock);
1b894b59
CW
911 if (!intel_PLL_is_valid(dev, limit,
912 &clock))
d4906093 913 continue;
1b894b59
CW
914
915 this_err = abs(clock.dot - target);
d4906093
ML
916 if (this_err < err_most) {
917 *best_clock = clock;
918 err_most = this_err;
919 max_n = clock.n;
920 found = true;
921 }
922 }
923 }
924 }
925 }
2c07245f
ZW
926 return found;
927}
928
5eb08b69 929static bool
f2b115e6
AJ
930intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
931 int target, int refclk, intel_clock_t *best_clock)
5eb08b69
ZW
932{
933 struct drm_device *dev = crtc->dev;
934 intel_clock_t clock;
4547668a 935
5eb08b69
ZW
936 if (target < 200000) {
937 clock.n = 1;
938 clock.p1 = 2;
939 clock.p2 = 10;
940 clock.m1 = 12;
941 clock.m2 = 9;
942 } else {
943 clock.n = 2;
944 clock.p1 = 1;
945 clock.p2 = 10;
946 clock.m1 = 14;
947 clock.m2 = 8;
948 }
949 intel_clock(dev, refclk, &clock);
950 memcpy(best_clock, &clock, sizeof(intel_clock_t));
951 return true;
952}
953
a4fc5ed6
KP
954/* DisplayPort has only two frequencies, 162MHz and 270MHz */
955static bool
956intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
957 int target, int refclk, intel_clock_t *best_clock)
958{
5eddb70b
CW
959 intel_clock_t clock;
960 if (target < 200000) {
961 clock.p1 = 2;
962 clock.p2 = 10;
963 clock.n = 2;
964 clock.m1 = 23;
965 clock.m2 = 8;
966 } else {
967 clock.p1 = 1;
968 clock.p2 = 10;
969 clock.n = 1;
970 clock.m1 = 14;
971 clock.m2 = 2;
972 }
973 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
974 clock.p = (clock.p1 * clock.p2);
975 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
976 clock.vco = 0;
977 memcpy(best_clock, &clock, sizeof(intel_clock_t));
978 return true;
a4fc5ed6
KP
979}
980
9d0498a2
JB
981/**
982 * intel_wait_for_vblank - wait for vblank on a given pipe
983 * @dev: drm device
984 * @pipe: pipe to wait for
985 *
986 * Wait for vblank to occur on a given pipe. Needed for various bits of
987 * mode setting code.
988 */
989void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 990{
9d0498a2
JB
991 struct drm_i915_private *dev_priv = dev->dev_private;
992 int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
993
300387c0
CW
994 /* Clear existing vblank status. Note this will clear any other
995 * sticky status fields as well.
996 *
997 * This races with i915_driver_irq_handler() with the result
998 * that either function could miss a vblank event. Here it is not
999 * fatal, as we will either wait upon the next vblank interrupt or
1000 * timeout. Generally speaking intel_wait_for_vblank() is only
1001 * called during modeset at which time the GPU should be idle and
1002 * should *not* be performing page flips and thus not waiting on
1003 * vblanks...
1004 * Currently, the result of us stealing a vblank from the irq
1005 * handler is that a single frame will be skipped during swapbuffers.
1006 */
1007 I915_WRITE(pipestat_reg,
1008 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1009
9d0498a2 1010 /* Wait for vblank interrupt bit to set */
481b6af3
CW
1011 if (wait_for(I915_READ(pipestat_reg) &
1012 PIPE_VBLANK_INTERRUPT_STATUS,
1013 50))
9d0498a2
JB
1014 DRM_DEBUG_KMS("vblank wait timed out\n");
1015}
1016
ab7ad7f6
KP
1017/*
1018 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB
1019 * @dev: drm device
1020 * @pipe: pipe to wait for
1021 *
1022 * After disabling a pipe, we can't wait for vblank in the usual way,
1023 * spinning on the vblank interrupt status bit, since we won't actually
1024 * see an interrupt when the pipe is disabled.
1025 *
ab7ad7f6
KP
1026 * On Gen4 and above:
1027 * wait for the pipe register state bit to turn off
1028 *
1029 * Otherwise:
1030 * wait for the display line value to settle (it usually
1031 * ends up stopping at the start of the next frame).
58e10eb9 1032 *
9d0498a2 1033 */
58e10eb9 1034void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB
1035{
1036 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP
1037
1038 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 1039 int reg = PIPECONF(pipe);
ab7ad7f6
KP
1040
1041 /* Wait for the Pipe State to go off */
58e10eb9
CW
1042 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1043 100))
ab7ad7f6
KP
1044 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1045 } else {
1046 u32 last_line;
58e10eb9 1047 int reg = PIPEDSL(pipe);
ab7ad7f6
KP
1048 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1049
1050 /* Wait for the display line to settle */
1051 do {
58e10eb9 1052 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 1053 mdelay(5);
58e10eb9 1054 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP
1055 time_after(timeout, jiffies));
1056 if (time_after(jiffies, timeout))
1057 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1058 }
79e53945
JB
1059}
1060
80824003
JB
1061static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1062{
1063 struct drm_device *dev = crtc->dev;
1064 struct drm_i915_private *dev_priv = dev->dev_private;
1065 struct drm_framebuffer *fb = crtc->fb;
1066 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1067 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003
JB
1068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1069 int plane, i;
1070 u32 fbc_ctl, fbc_ctl2;
1071
bed4a673 1072 if (fb->pitch == dev_priv->cfb_pitch &&
05394f39 1073 obj->fence_reg == dev_priv->cfb_fence &&
bed4a673
CW
1074 intel_crtc->plane == dev_priv->cfb_plane &&
1075 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1076 return;
1077
1078 i8xx_disable_fbc(dev);
1079
80824003
JB
1080 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1081
1082 if (fb->pitch < dev_priv->cfb_pitch)
1083 dev_priv->cfb_pitch = fb->pitch;
1084
1085 /* FBC_CTL wants 64B units */
1086 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1087 dev_priv->cfb_fence = obj->fence_reg;
80824003
JB
1088 dev_priv->cfb_plane = intel_crtc->plane;
1089 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1090
1091 /* Clear old tags */
1092 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1093 I915_WRITE(FBC_TAG + (i * 4), 0);
1094
1095 /* Set it up... */
1096 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
05394f39 1097 if (obj->tiling_mode != I915_TILING_NONE)
80824003
JB
1098 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1099 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1100 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1101
1102 /* enable it... */
1103 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1104 if (IS_I945GM(dev))
49677901 1105 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
80824003
JB
1106 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1107 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
05394f39 1108 if (obj->tiling_mode != I915_TILING_NONE)
80824003
JB
1109 fbc_ctl |= dev_priv->cfb_fence;
1110 I915_WRITE(FBC_CONTROL, fbc_ctl);
1111
28c97730 1112 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
5eddb70b 1113 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
80824003
JB
1114}
1115
1116void i8xx_disable_fbc(struct drm_device *dev)
1117{
1118 struct drm_i915_private *dev_priv = dev->dev_private;
1119 u32 fbc_ctl;
1120
1121 /* Disable compression */
1122 fbc_ctl = I915_READ(FBC_CONTROL);
a5cad620
CW
1123 if ((fbc_ctl & FBC_CTL_EN) == 0)
1124 return;
1125
80824003
JB
1126 fbc_ctl &= ~FBC_CTL_EN;
1127 I915_WRITE(FBC_CONTROL, fbc_ctl);
1128
1129 /* Wait for compressing bit to clear */
481b6af3 1130 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
913d8d11
CW
1131 DRM_DEBUG_KMS("FBC idle timed out\n");
1132 return;
9517a92f 1133 }
80824003 1134
28c97730 1135 DRM_DEBUG_KMS("disabled FBC\n");
80824003
JB
1136}
1137
ee5382ae 1138static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1139{
80824003
JB
1140 struct drm_i915_private *dev_priv = dev->dev_private;
1141
1142 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1143}
1144
74dff282
JB
1145static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1146{
1147 struct drm_device *dev = crtc->dev;
1148 struct drm_i915_private *dev_priv = dev->dev_private;
1149 struct drm_framebuffer *fb = crtc->fb;
1150 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1151 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1153 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB
1154 unsigned long stall_watermark = 200;
1155 u32 dpfc_ctl;
1156
bed4a673
CW
1157 dpfc_ctl = I915_READ(DPFC_CONTROL);
1158 if (dpfc_ctl & DPFC_CTL_EN) {
1159 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
05394f39 1160 dev_priv->cfb_fence == obj->fence_reg &&
bed4a673
CW
1161 dev_priv->cfb_plane == intel_crtc->plane &&
1162 dev_priv->cfb_y == crtc->y)
1163 return;
1164
1165 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1166 POSTING_READ(DPFC_CONTROL);
1167 intel_wait_for_vblank(dev, intel_crtc->pipe);
1168 }
1169
74dff282 1170 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1171 dev_priv->cfb_fence = obj->fence_reg;
74dff282 1172 dev_priv->cfb_plane = intel_crtc->plane;
bed4a673 1173 dev_priv->cfb_y = crtc->y;
74dff282
JB
1174
1175 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
05394f39 1176 if (obj->tiling_mode != I915_TILING_NONE) {
74dff282
JB
1177 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1178 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1179 } else {
1180 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1181 }
1182
74dff282
JB
1183 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1184 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1185 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1186 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1187
1188 /* enable it... */
1189 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1190
28c97730 1191 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB
1192}
1193
1194void g4x_disable_fbc(struct drm_device *dev)
1195{
1196 struct drm_i915_private *dev_priv = dev->dev_private;
1197 u32 dpfc_ctl;
1198
1199 /* Disable compression */
1200 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW
1201 if (dpfc_ctl & DPFC_CTL_EN) {
1202 dpfc_ctl &= ~DPFC_CTL_EN;
1203 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1204
bed4a673
CW
1205 DRM_DEBUG_KMS("disabled FBC\n");
1206 }
74dff282
JB
1207}
1208
ee5382ae 1209static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1210{
74dff282
JB
1211 struct drm_i915_private *dev_priv = dev->dev_private;
1212
1213 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1214}
1215
b52eb4dc
ZY
1216static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1217{
1218 struct drm_device *dev = crtc->dev;
1219 struct drm_i915_private *dev_priv = dev->dev_private;
1220 struct drm_framebuffer *fb = crtc->fb;
1221 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1222 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1224 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY
1225 unsigned long stall_watermark = 200;
1226 u32 dpfc_ctl;
1227
bed4a673
CW
1228 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1229 if (dpfc_ctl & DPFC_CTL_EN) {
1230 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
05394f39 1231 dev_priv->cfb_fence == obj->fence_reg &&
bed4a673 1232 dev_priv->cfb_plane == intel_crtc->plane &&
05394f39 1233 dev_priv->cfb_offset == obj->gtt_offset &&
bed4a673
CW
1234 dev_priv->cfb_y == crtc->y)
1235 return;
1236
1237 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1238 POSTING_READ(ILK_DPFC_CONTROL);
1239 intel_wait_for_vblank(dev, intel_crtc->pipe);
1240 }
1241
b52eb4dc 1242 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1243 dev_priv->cfb_fence = obj->fence_reg;
b52eb4dc 1244 dev_priv->cfb_plane = intel_crtc->plane;
05394f39 1245 dev_priv->cfb_offset = obj->gtt_offset;
bed4a673 1246 dev_priv->cfb_y = crtc->y;
b52eb4dc 1247
b52eb4dc
ZY
1248 dpfc_ctl &= DPFC_RESERVED;
1249 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
05394f39 1250 if (obj->tiling_mode != I915_TILING_NONE) {
b52eb4dc
ZY
1251 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1252 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1253 } else {
1254 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1255 }
1256
b52eb4dc
ZY
1257 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1258 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1259 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1260 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1261 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1262 /* enable it... */
bed4a673 1263 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc
ZY
1264
1265 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1266}
1267
1268void ironlake_disable_fbc(struct drm_device *dev)
1269{
1270 struct drm_i915_private *dev_priv = dev->dev_private;
1271 u32 dpfc_ctl;
1272
1273 /* Disable compression */
1274 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW
1275 if (dpfc_ctl & DPFC_CTL_EN) {
1276 dpfc_ctl &= ~DPFC_CTL_EN;
1277 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1278
bed4a673
CW
1279 DRM_DEBUG_KMS("disabled FBC\n");
1280 }
b52eb4dc
ZY
1281}
1282
1283static bool ironlake_fbc_enabled(struct drm_device *dev)
1284{
1285 struct drm_i915_private *dev_priv = dev->dev_private;
1286
1287 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1288}
1289
ee5382ae
AJ
1290bool intel_fbc_enabled(struct drm_device *dev)
1291{
1292 struct drm_i915_private *dev_priv = dev->dev_private;
1293
1294 if (!dev_priv->display.fbc_enabled)
1295 return false;
1296
1297 return dev_priv->display.fbc_enabled(dev);
1298}
1299
1300void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1301{
1302 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1303
1304 if (!dev_priv->display.enable_fbc)
1305 return;
1306
1307 dev_priv->display.enable_fbc(crtc, interval);
1308}
1309
1310void intel_disable_fbc(struct drm_device *dev)
1311{
1312 struct drm_i915_private *dev_priv = dev->dev_private;
1313
1314 if (!dev_priv->display.disable_fbc)
1315 return;
1316
1317 dev_priv->display.disable_fbc(dev);
1318}
1319
80824003
JB
1320/**
1321 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1322 * @dev: the drm_device
80824003
JB
1323 *
1324 * Set up the framebuffer compression hardware at mode set time. We
1325 * enable it if possible:
1326 * - plane A only (on pre-965)
1327 * - no pixel mulitply/line duplication
1328 * - no alpha buffer discard
1329 * - no dual wide
1330 * - framebuffer <= 2048 in width, 1536 in height
1331 *
1332 * We can't assume that any compression will take place (worst case),
1333 * so the compressed buffer has to be the same size as the uncompressed
1334 * one. It also must reside (along with the line length buffer) in
1335 * stolen memory.
1336 *
1337 * We need to enable/disable FBC on a global basis.
1338 */
bed4a673 1339static void intel_update_fbc(struct drm_device *dev)
80824003 1340{
80824003 1341 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW
1342 struct drm_crtc *crtc = NULL, *tmp_crtc;
1343 struct intel_crtc *intel_crtc;
1344 struct drm_framebuffer *fb;
80824003 1345 struct intel_framebuffer *intel_fb;
05394f39 1346 struct drm_i915_gem_object *obj;
9c928d16
JB
1347
1348 DRM_DEBUG_KMS("\n");
80824003
JB
1349
1350 if (!i915_powersave)
1351 return;
1352
ee5382ae 1353 if (!I915_HAS_FBC(dev))
e70236a8
JB
1354 return;
1355
80824003
JB
1356 /*
1357 * If FBC is already on, we just have to verify that we can
1358 * keep it that way...
1359 * Need to disable if:
9c928d16 1360 * - more than one pipe is active
80824003
JB
1361 * - changing FBC params (stride, fence, mode)
1362 * - new fb is too large to fit in compressed buffer
1363 * - going to an unsupported config (interlace, pixel multiply, etc.)
1364 */
9c928d16 1365 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
bed4a673
CW
1366 if (tmp_crtc->enabled) {
1367 if (crtc) {
1368 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1369 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1370 goto out_disable;
1371 }
1372 crtc = tmp_crtc;
1373 }
9c928d16 1374 }
bed4a673
CW
1375
1376 if (!crtc || crtc->fb == NULL) {
1377 DRM_DEBUG_KMS("no output, disabling\n");
1378 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB
1379 goto out_disable;
1380 }
bed4a673
CW
1381
1382 intel_crtc = to_intel_crtc(crtc);
1383 fb = crtc->fb;
1384 intel_fb = to_intel_framebuffer(fb);
05394f39 1385 obj = intel_fb->obj;
bed4a673 1386
05394f39 1387 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 1388 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 1389 "compression\n");
b5e50c3f 1390 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB
1391 goto out_disable;
1392 }
bed4a673
CW
1393 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1394 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 1395 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 1396 "disabling\n");
b5e50c3f 1397 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB
1398 goto out_disable;
1399 }
bed4a673
CW
1400 if ((crtc->mode.hdisplay > 2048) ||
1401 (crtc->mode.vdisplay > 1536)) {
28c97730 1402 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 1403 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB
1404 goto out_disable;
1405 }
bed4a673 1406 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 1407 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 1408 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB
1409 goto out_disable;
1410 }
05394f39 1411 if (obj->tiling_mode != I915_TILING_X) {
28c97730 1412 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
b5e50c3f 1413 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB
1414 goto out_disable;
1415 }
1416
c924b934
JW
1417 /* If the kernel debugger is active, always disable compression */
1418 if (in_dbg_master())
1419 goto out_disable;
1420
bed4a673 1421 intel_enable_fbc(crtc, 500);
80824003
JB
1422 return;
1423
1424out_disable:
80824003 1425 /* Multiple disables should be harmless */
a939406f
CW
1426 if (intel_fbc_enabled(dev)) {
1427 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 1428 intel_disable_fbc(dev);
a939406f 1429 }
80824003
JB
1430}
1431
127bd2ac 1432int
48b956c5 1433intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1434 struct drm_i915_gem_object *obj,
919926ae 1435 struct intel_ring_buffer *pipelined)
6b95a207 1436{
6b95a207
KH
1437 u32 alignment;
1438 int ret;
1439
05394f39 1440 switch (obj->tiling_mode) {
6b95a207 1441 case I915_TILING_NONE:
534843da
CW
1442 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1443 alignment = 128 * 1024;
a6c45cf0 1444 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW
1445 alignment = 4 * 1024;
1446 else
1447 alignment = 64 * 1024;
6b95a207
KH
1448 break;
1449 case I915_TILING_X:
1450 /* pin() will align the object as required by fence */
1451 alignment = 0;
1452 break;
1453 case I915_TILING_Y:
1454 /* FIXME: Is this true? */
1455 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1456 return -EINVAL;
1457 default:
1458 BUG();
1459 }
1460
75e9e915 1461 ret = i915_gem_object_pin(obj, alignment, true);
48b956c5 1462 if (ret)
6b95a207
KH
1463 return ret;
1464
48b956c5
CW
1465 ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1466 if (ret)
1467 goto err_unpin;
7213342d 1468
6b95a207
KH
1469 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1470 * fence, whereas 965+ only requires a fence if using
1471 * framebuffer compression. For simplicity, we always install
1472 * a fence as the cost is not that onerous.
1473 */
05394f39 1474 if (obj->tiling_mode != I915_TILING_NONE) {
d9e86c0e 1475 ret = i915_gem_object_get_fence(obj, pipelined, false);
48b956c5
CW
1476 if (ret)
1477 goto err_unpin;
6b95a207
KH
1478 }
1479
1480 return 0;
48b956c5
CW
1481
1482err_unpin:
1483 i915_gem_object_unpin(obj);
1484 return ret;
6b95a207
KH
1485}
1486
81255565
JB
1487/* Assume fb object is pinned & idle & fenced and just update base pointers */
1488static int
1489intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
21c74a8e 1490 int x, int y, enum mode_set_atomic state)
81255565
JB
1491{
1492 struct drm_device *dev = crtc->dev;
1493 struct drm_i915_private *dev_priv = dev->dev_private;
1494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1495 struct intel_framebuffer *intel_fb;
05394f39 1496 struct drm_i915_gem_object *obj;
81255565
JB
1497 int plane = intel_crtc->plane;
1498 unsigned long Start, Offset;
81255565 1499 u32 dspcntr;
5eddb70b 1500 u32 reg;
81255565
JB
1501
1502 switch (plane) {
1503 case 0:
1504 case 1:
1505 break;
1506 default:
1507 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1508 return -EINVAL;
1509 }
1510
1511 intel_fb = to_intel_framebuffer(fb);
1512 obj = intel_fb->obj;
81255565 1513
5eddb70b
CW
1514 reg = DSPCNTR(plane);
1515 dspcntr = I915_READ(reg);
81255565
JB
1516 /* Mask out pixel format bits in case we change it */
1517 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1518 switch (fb->bits_per_pixel) {
1519 case 8:
1520 dspcntr |= DISPPLANE_8BPP;
1521 break;
1522 case 16:
1523 if (fb->depth == 15)
1524 dspcntr |= DISPPLANE_15_16BPP;
1525 else
1526 dspcntr |= DISPPLANE_16BPP;
1527 break;
1528 case 24:
1529 case 32:
1530 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1531 break;
1532 default:
1533 DRM_ERROR("Unknown color depth\n");
1534 return -EINVAL;
1535 }
a6c45cf0 1536 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1537 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB
1538 dspcntr |= DISPPLANE_TILED;
1539 else
1540 dspcntr &= ~DISPPLANE_TILED;
1541 }
1542
4e6cfefc 1543 if (HAS_PCH_SPLIT(dev))
81255565
JB
1544 /* must disable */
1545 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1546
5eddb70b 1547 I915_WRITE(reg, dspcntr);
81255565 1548
05394f39 1549 Start = obj->gtt_offset;
81255565
JB
1550 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1551
4e6cfefc
CW
1552 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1553 Start, Offset, x, y, fb->pitch);
5eddb70b 1554 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
a6c45cf0 1555 if (INTEL_INFO(dev)->gen >= 4) {
5eddb70b
CW
1556 I915_WRITE(DSPSURF(plane), Start);
1557 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1558 I915_WRITE(DSPADDR(plane), Offset);
1559 } else
1560 I915_WRITE(DSPADDR(plane), Start + Offset);
1561 POSTING_READ(reg);
81255565 1562
bed4a673 1563 intel_update_fbc(dev);
3dec0095 1564 intel_increase_pllclock(crtc);
81255565
JB
1565
1566 return 0;
1567}
1568
5c3b82e2 1569static int
3c4fdcfb
KH
1570intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1571 struct drm_framebuffer *old_fb)
79e53945
JB
1572{
1573 struct drm_device *dev = crtc->dev;
79e53945
JB
1574 struct drm_i915_master_private *master_priv;
1575 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 1576 int ret;
79e53945
JB
1577
1578 /* no fb bound */
1579 if (!crtc->fb) {
28c97730 1580 DRM_DEBUG_KMS("No FB bound\n");
5c3b82e2
CW
1581 return 0;
1582 }
1583
265db958 1584 switch (intel_crtc->plane) {
5c3b82e2
CW
1585 case 0:
1586 case 1:
1587 break;
1588 default:
5c3b82e2 1589 return -EINVAL;
79e53945
JB
1590 }
1591
5c3b82e2 1592 mutex_lock(&dev->struct_mutex);
265db958
CW
1593 ret = intel_pin_and_fence_fb_obj(dev,
1594 to_intel_framebuffer(crtc->fb)->obj,
919926ae 1595 NULL);
5c3b82e2
CW
1596 if (ret != 0) {
1597 mutex_unlock(&dev->struct_mutex);
1598 return ret;
1599 }
79e53945 1600
265db958 1601 if (old_fb) {
e6c3a2a6 1602 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1603 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
265db958 1604
e6c3a2a6 1605 wait_event(dev_priv->pending_flip_queue,
05394f39 1606 atomic_read(&obj->pending_flip) == 0);
85345517
CW
1607
1608 /* Big Hammer, we also need to ensure that any pending
1609 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1610 * current scanout is retired before unpinning the old
1611 * framebuffer.
1612 */
05394f39 1613 ret = i915_gem_object_flush_gpu(obj, false);
85345517
CW
1614 if (ret) {
1615 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1616 mutex_unlock(&dev->struct_mutex);
1617 return ret;
1618 }
265db958
CW
1619 }
1620
21c74a8e
JW
1621 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1622 LEAVE_ATOMIC_MODE_SET);
4e6cfefc 1623 if (ret) {
265db958 1624 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 1625 mutex_unlock(&dev->struct_mutex);
4e6cfefc 1626 return ret;
79e53945 1627 }
3c4fdcfb 1628
265db958
CW
1629 if (old_fb)
1630 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
652c393a 1631
5c3b82e2 1632 mutex_unlock(&dev->struct_mutex);
79e53945
JB
1633
1634 if (!dev->primary->master)
5c3b82e2 1635 return 0;
79e53945
JB
1636
1637 master_priv = dev->primary->master->driver_priv;
1638 if (!master_priv->sarea_priv)
5c3b82e2 1639 return 0;
79e53945 1640
265db958 1641 if (intel_crtc->pipe) {
79e53945
JB
1642 master_priv->sarea_priv->pipeB_x = x;
1643 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW
1644 } else {
1645 master_priv->sarea_priv->pipeA_x = x;
1646 master_priv->sarea_priv->pipeA_y = y;
79e53945 1647 }
5c3b82e2
CW
1648
1649 return 0;
79e53945
JB
1650}
1651
5eddb70b 1652static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW
1653{
1654 struct drm_device *dev = crtc->dev;
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 u32 dpa_ctl;
1657
28c97730 1658 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW
1659 dpa_ctl = I915_READ(DP_A);
1660 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1661
1662 if (clock < 200000) {
1663 u32 temp;
1664 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1665 /* workaround for 160Mhz:
1666 1) program 0x4600c bits 15:0 = 0x8124
1667 2) program 0x46010 bit 0 = 1
1668 3) program 0x46034 bit 24 = 1
1669 4) program 0x64000 bit 14 = 1
1670 */
1671 temp = I915_READ(0x4600c);
1672 temp &= 0xffff0000;
1673 I915_WRITE(0x4600c, temp | 0x8124);
1674
1675 temp = I915_READ(0x46010);
1676 I915_WRITE(0x46010, temp | 1);
1677
1678 temp = I915_READ(0x46034);
1679 I915_WRITE(0x46034, temp | (1 << 24));
1680 } else {
1681 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1682 }
1683 I915_WRITE(DP_A, dpa_ctl);
1684
5eddb70b 1685 POSTING_READ(DP_A);
32f9d658
ZW
1686 udelay(500);
1687}
1688
5e84e1a4
ZW
1689static void intel_fdi_normal_train(struct drm_crtc *crtc)
1690{
1691 struct drm_device *dev = crtc->dev;
1692 struct drm_i915_private *dev_priv = dev->dev_private;
1693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1694 int pipe = intel_crtc->pipe;
1695 u32 reg, temp;
1696
1697 /* enable normal train */
1698 reg = FDI_TX_CTL(pipe);
1699 temp = I915_READ(reg);
1700 temp &= ~FDI_LINK_TRAIN_NONE;
1701 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
1702 I915_WRITE(reg, temp);
1703
1704 reg = FDI_RX_CTL(pipe);
1705 temp = I915_READ(reg);
1706 if (HAS_PCH_CPT(dev)) {
1707 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1708 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1709 } else {
1710 temp &= ~FDI_LINK_TRAIN_NONE;
1711 temp |= FDI_LINK_TRAIN_NONE;
1712 }
1713 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1714
1715 /* wait one idle pattern time */
1716 POSTING_READ(reg);
1717 udelay(1000);
1718}
1719
8db9d77b
ZW
1720/* The FDI link training functions for ILK/Ibexpeak. */
1721static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1722{
1723 struct drm_device *dev = crtc->dev;
1724 struct drm_i915_private *dev_priv = dev->dev_private;
1725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1726 int pipe = intel_crtc->pipe;
5eddb70b 1727 u32 reg, temp, tries;
8db9d77b 1728
e1a44743
AJ
1729 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1730 for train result */
5eddb70b
CW
1731 reg = FDI_RX_IMR(pipe);
1732 temp = I915_READ(reg);
e1a44743
AJ
1733 temp &= ~FDI_RX_SYMBOL_LOCK;
1734 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW
1735 I915_WRITE(reg, temp);
1736 I915_READ(reg);
e1a44743
AJ
1737 udelay(150);
1738
8db9d77b 1739 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW
1740 reg = FDI_TX_CTL(pipe);
1741 temp = I915_READ(reg);
77ffb597
AJ
1742 temp &= ~(7 << 19);
1743 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW
1744 temp &= ~FDI_LINK_TRAIN_NONE;
1745 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 1746 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 1747
5eddb70b
CW
1748 reg = FDI_RX_CTL(pipe);
1749 temp = I915_READ(reg);
8db9d77b
ZW
1750 temp &= ~FDI_LINK_TRAIN_NONE;
1751 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW
1752 I915_WRITE(reg, temp | FDI_RX_ENABLE);
1753
1754 POSTING_READ(reg);
8db9d77b
ZW
1755 udelay(150);
1756
5b2adf89
JB
1757 /* Ironlake workaround, enable clock pointer after FDI enable*/
1758 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);
1759
5eddb70b 1760 reg = FDI_RX_IIR(pipe);
e1a44743 1761 for (tries = 0; tries < 5; tries++) {
5eddb70b 1762 temp = I915_READ(reg);
8db9d77b
ZW
1763 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1764
1765 if ((temp & FDI_RX_BIT_LOCK)) {
1766 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 1767 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW
1768 break;
1769 }
8db9d77b 1770 }
e1a44743 1771 if (tries == 5)
5eddb70b 1772 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW
1773
1774 /* Train 2 */
5eddb70b
CW
1775 reg = FDI_TX_CTL(pipe);
1776 temp = I915_READ(reg);
8db9d77b
ZW
1777 temp &= ~FDI_LINK_TRAIN_NONE;
1778 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 1779 I915_WRITE(reg, temp);
8db9d77b 1780
5eddb70b
CW
1781 reg = FDI_RX_CTL(pipe);
1782 temp = I915_READ(reg);
8db9d77b
ZW
1783 temp &= ~FDI_LINK_TRAIN_NONE;
1784 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 1785 I915_WRITE(reg, temp);
8db9d77b 1786
5eddb70b
CW
1787 POSTING_READ(reg);
1788 udelay(150);
8db9d77b 1789
5eddb70b 1790 reg = FDI_RX_IIR(pipe);
e1a44743 1791 for (tries = 0; tries < 5; tries++) {
5eddb70b 1792 temp = I915_READ(reg);
8db9d77b
ZW
1793 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1794
1795 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 1796 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW
1797 DRM_DEBUG_KMS("FDI train 2 done.\n");
1798 break;
1799 }
8db9d77b 1800 }
e1a44743 1801 if (tries == 5)
5eddb70b 1802 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW
1803
1804 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 1805
8db9d77b
ZW
1806}
1807
5eddb70b 1808static const int const snb_b_fdi_train_param [] = {
8db9d77b
ZW
1809 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1810 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1811 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1812 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1813};
1814
1815/* The FDI link training functions for SNB/Cougarpoint. */
1816static void gen6_fdi_link_train(struct drm_crtc *crtc)
1817{
1818 struct drm_device *dev = crtc->dev;
1819 struct drm_i915_private *dev_priv = dev->dev_private;
1820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1821 int pipe = intel_crtc->pipe;
5eddb70b 1822 u32 reg, temp, i;
8db9d77b 1823
e1a44743
AJ
1824 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1825 for train result */
5eddb70b
CW
1826 reg = FDI_RX_IMR(pipe);
1827 temp = I915_READ(reg);
e1a44743
AJ
1828 temp &= ~FDI_RX_SYMBOL_LOCK;
1829 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW
1830 I915_WRITE(reg, temp);
1831
1832 POSTING_READ(reg);
e1a44743
AJ
1833 udelay(150);
1834
8db9d77b 1835 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW
1836 reg = FDI_TX_CTL(pipe);
1837 temp = I915_READ(reg);
77ffb597
AJ
1838 temp &= ~(7 << 19);
1839 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW
1840 temp &= ~FDI_LINK_TRAIN_NONE;
1841 temp |= FDI_LINK_TRAIN_PATTERN_1;
1842 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1843 /* SNB-B */
1844 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 1845 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 1846
5eddb70b
CW
1847 reg = FDI_RX_CTL(pipe);
1848 temp = I915_READ(reg);
8db9d77b
ZW
1849 if (HAS_PCH_CPT(dev)) {
1850 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1851 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1852 } else {
1853 temp &= ~FDI_LINK_TRAIN_NONE;
1854 temp |= FDI_LINK_TRAIN_PATTERN_1;
1855 }
5eddb70b
CW
1856 I915_WRITE(reg, temp | FDI_RX_ENABLE);
1857
1858 POSTING_READ(reg);
8db9d77b
ZW
1859 udelay(150);
1860
8db9d77b 1861 for (i = 0; i < 4; i++ ) {
5eddb70b
CW
1862 reg = FDI_TX_CTL(pipe);
1863 temp = I915_READ(reg);
8db9d77b
ZW
1864 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1865 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW
1866 I915_WRITE(reg, temp);
1867
1868 POSTING_READ(reg);
8db9d77b
ZW
1869 udelay(500);
1870
5eddb70b
CW
1871 reg = FDI_RX_IIR(pipe);
1872 temp = I915_READ(reg);
8db9d77b
ZW
1873 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1874
1875 if (temp & FDI_RX_BIT_LOCK) {
5eddb70b 1876 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW
1877 DRM_DEBUG_KMS("FDI train 1 done.\n");
1878 break;
1879 }
1880 }
1881 if (i == 4)
5eddb70b 1882 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW
1883
1884 /* Train 2 */
5eddb70b
CW
1885 reg = FDI_TX_CTL(pipe);
1886 temp = I915_READ(reg);
8db9d77b
ZW
1887 temp &= ~FDI_LINK_TRAIN_NONE;
1888 temp |= FDI_LINK_TRAIN_PATTERN_2;
1889 if (IS_GEN6(dev)) {
1890 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1891 /* SNB-B */
1892 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1893 }
5eddb70b 1894 I915_WRITE(reg, temp);
8db9d77b 1895
5eddb70b
CW
1896 reg = FDI_RX_CTL(pipe);
1897 temp = I915_READ(reg);
8db9d77b
ZW
1898 if (HAS_PCH_CPT(dev)) {
1899 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1900 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1901 } else {
1902 temp &= ~FDI_LINK_TRAIN_NONE;
1903 temp |= FDI_LINK_TRAIN_PATTERN_2;
1904 }
5eddb70b
CW
1905 I915_WRITE(reg, temp);
1906
1907 POSTING_READ(reg);
8db9d77b
ZW
1908 udelay(150);
1909
1910 for (i = 0; i < 4; i++ ) {
5eddb70b
CW
1911 reg = FDI_TX_CTL(pipe);
1912 temp = I915_READ(reg);
8db9d77b
ZW
1913 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1914 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW
1915 I915_WRITE(reg, temp);
1916
1917 POSTING_READ(reg);
8db9d77b
ZW
1918 udelay(500);
1919
5eddb70b
CW
1920 reg = FDI_RX_IIR(pipe);
1921 temp = I915_READ(reg);
8db9d77b
ZW
1922 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1923
1924 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 1925 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW
1926 DRM_DEBUG_KMS("FDI train 2 done.\n");
1927 break;
1928 }
1929 }
1930 if (i == 4)
5eddb70b 1931 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW
1932
1933 DRM_DEBUG_KMS("FDI train done.\n");
1934}
1935
0e23b99d 1936static void ironlake_fdi_enable(struct drm_crtc *crtc)
2c07245f
ZW
1937{
1938 struct drm_device *dev = crtc->dev;
1939 struct drm_i915_private *dev_priv = dev->dev_private;
1940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1941 int pipe = intel_crtc->pipe;
5eddb70b 1942 u32 reg, temp;
79e53945 1943
c64e311e 1944 /* Write the TU size bits so error detection works */
5eddb70b
CW
1945 I915_WRITE(FDI_RX_TUSIZE1(pipe),
1946 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 1947
c98e9dcf 1948 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW
1949 reg = FDI_RX_CTL(pipe);
1950 temp = I915_READ(reg);
1951 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 1952 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW
1953 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
1954 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
1955
1956 POSTING_READ(reg);
c98e9dcf
JB
1957 udelay(200);
1958
1959 /* Switch from Rawclk to PCDclk */
5eddb70b
CW
1960 temp = I915_READ(reg);
1961 I915_WRITE(reg, temp | FDI_PCDCLK);
1962
1963 POSTING_READ(reg);
c98e9dcf
JB
1964 udelay(200);
1965
1966 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW
1967 reg = FDI_TX_CTL(pipe);
1968 temp = I915_READ(reg);
c98e9dcf 1969 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW
1970 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
1971
1972 POSTING_READ(reg);
c98e9dcf 1973 udelay(100);
6be4a607 1974 }
0e23b99d
JB
1975}
1976
5eddb70b
CW
1977static void intel_flush_display_plane(struct drm_device *dev,
1978 int plane)
1979{
1980 struct drm_i915_private *dev_priv = dev->dev_private;
1981 u32 reg = DSPADDR(plane);
1982 I915_WRITE(reg, I915_READ(reg));
1983}
1984
6b383a7f
CW
1985/*
1986 * When we disable a pipe, we need to clear any pending scanline wait events
1987 * to avoid hanging the ring, which we assume we are waiting on.
1988 */
1989static void intel_clear_scanline_wait(struct drm_device *dev)
1990{
1991 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 1992 struct intel_ring_buffer *ring;
6b383a7f
CW
1993 u32 tmp;
1994
1995 if (IS_GEN2(dev))
1996 /* Can't break the hang on i8xx */
1997 return;
1998
1ec14ad3 1999 ring = LP_RING(dev_priv);
8168bd48
CW
2000 tmp = I915_READ_CTL(ring);
2001 if (tmp & RING_WAIT)
2002 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW
2003}
2004
e6c3a2a6
CW
2005static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2006{
05394f39 2007 struct drm_i915_gem_object *obj;
e6c3a2a6
CW
2008 struct drm_i915_private *dev_priv;
2009
2010 if (crtc->fb == NULL)
2011 return;
2012
05394f39 2013 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW
2014 dev_priv = crtc->dev->dev_private;
2015 wait_event(dev_priv->pending_flip_queue,
05394f39 2016 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW
2017}
2018
0e23b99d
JB
2019static void ironlake_crtc_enable(struct drm_crtc *crtc)
2020{
2021 struct drm_device *dev = crtc->dev;
2022 struct drm_i915_private *dev_priv = dev->dev_private;
2023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2024 int pipe = intel_crtc->pipe;
2025 int plane = intel_crtc->plane;
5eddb70b 2026 u32 reg, temp;
0e23b99d 2027
f7abfe8b
CW
2028 if (intel_crtc->active)
2029 return;
2030
2031 intel_crtc->active = true;
6b383a7f
CW
2032 intel_update_watermarks(dev);
2033
0e23b99d
JB
2034 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2035 temp = I915_READ(PCH_LVDS);
5eddb70b 2036 if ((temp & LVDS_PORT_EN) == 0)
0e23b99d 2037 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
0e23b99d
JB
2038 }
2039
2040 ironlake_fdi_enable(crtc);
2c07245f 2041
6be4a607
JB
2042 /* Enable panel fitting for LVDS */
2043 if (dev_priv->pch_pf_size &&
1d850362 2044 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
6be4a607
JB
2045 /* Force use of hard-coded filter coefficients
2046 * as some pre-programmed values are broken,
2047 * e.g. x201.
2048 */
2049 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2050 PF_ENABLE | PF_FILTER_MED_3x3);
2051 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2052 dev_priv->pch_pf_pos);
2053 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2054 dev_priv->pch_pf_size);
2055 }
2c07245f 2056
6be4a607 2057 /* Enable CPU pipe */
5eddb70b
CW
2058 reg = PIPECONF(pipe);
2059 temp = I915_READ(reg);
2060 if ((temp & PIPECONF_ENABLE) == 0) {
2061 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2062 POSTING_READ(reg);
17f6766c 2063 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607 2064 }
2c07245f 2065
6be4a607 2066 /* configure and enable CPU plane */
5eddb70b
CW
2067 reg = DSPCNTR(plane);
2068 temp = I915_READ(reg);
6be4a607 2069 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
5eddb70b
CW
2070 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2071 intel_flush_display_plane(dev, plane);
6be4a607 2072 }
2c07245f 2073
c98e9dcf
JB
2074 /* For PCH output, training FDI link */
2075 if (IS_GEN6(dev))
2076 gen6_fdi_link_train(crtc);
2077 else
2078 ironlake_fdi_link_train(crtc);
2c07245f 2079
c98e9dcf 2080 /* enable PCH DPLL */
5eddb70b
CW
2081 reg = PCH_DPLL(pipe);
2082 temp = I915_READ(reg);
c98e9dcf 2083 if ((temp & DPLL_VCO_ENABLE) == 0) {
5eddb70b
CW
2084 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2085 POSTING_READ(reg);
8c4223be 2086 udelay(200);
c98e9dcf 2087 }
8db9d77b 2088
c98e9dcf
JB
2089 if (HAS_PCH_CPT(dev)) {
2090 /* Be sure PCH DPLL SEL is set */
2091 temp = I915_READ(PCH_DPLL_SEL);
5eddb70b 2092 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
c98e9dcf 2093 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
5eddb70b 2094 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
c98e9dcf
JB
2095 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2096 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2097 }
5eddb70b 2098
c98e9dcf 2099 /* set transcoder timing */
5eddb70b
CW
2100 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2101 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2102 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2103
5eddb70b
CW
2104 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2105 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2106 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
8db9d77b 2107
5e84e1a4
ZW
2108 intel_fdi_normal_train(crtc);
2109
c98e9dcf
JB
2110 /* For PCH DP, enable TRANS_DP_CTL */
2111 if (HAS_PCH_CPT(dev) &&
2112 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5eddb70b
CW
2113 reg = TRANS_DP_CTL(pipe);
2114 temp = I915_READ(reg);
2115 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA
2116 TRANS_DP_SYNC_MASK |
2117 TRANS_DP_BPC_MASK);
5eddb70b
CW
2118 temp |= (TRANS_DP_OUTPUT_ENABLE |
2119 TRANS_DP_ENH_FRAMING);
220cad3c 2120 temp |= TRANS_DP_8BPC;
c98e9dcf
JB
2121
2122 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2123 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2124 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2125 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB
2126
2127 switch (intel_trans_dp_port_sel(crtc)) {
2128 case PCH_DP_B:
5eddb70b 2129 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB
2130 break;
2131 case PCH_DP_C:
5eddb70b 2132 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB
2133 break;
2134 case PCH_DP_D:
5eddb70b 2135 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB
2136 break;
2137 default:
2138 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2139 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2140 break;
32f9d658 2141 }
2c07245f 2142
5eddb70b 2143 I915_WRITE(reg, temp);
6be4a607 2144 }
b52eb4dc 2145
c98e9dcf 2146 /* enable PCH transcoder */
5eddb70b
CW
2147 reg = TRANSCONF(pipe);
2148 temp = I915_READ(reg);
c98e9dcf
JB
2149 /*
2150 * make the BPC in transcoder be consistent with
2151 * that in pipeconf reg.
2152 */
2153 temp &= ~PIPE_BPC_MASK;
5eddb70b
CW
2154 temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2155 I915_WRITE(reg, temp | TRANS_ENABLE);
2156 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
17f6766c 2157 DRM_ERROR("failed to enable transcoder %d\n", pipe);
c98e9dcf 2158
6be4a607 2159 intel_crtc_load_lut(crtc);
bed4a673 2160 intel_update_fbc(dev);
6b383a7f 2161 intel_crtc_update_cursor(crtc, true);
6be4a607
JB
2162}
2163
2164static void ironlake_crtc_disable(struct drm_crtc *crtc)
2165{
2166 struct drm_device *dev = crtc->dev;
2167 struct drm_i915_private *dev_priv = dev->dev_private;
2168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2169 int pipe = intel_crtc->pipe;
2170 int plane = intel_crtc->plane;
5eddb70b 2171 u32 reg, temp;
b52eb4dc 2172
f7abfe8b
CW
2173 if (!intel_crtc->active)
2174 return;
2175
e6c3a2a6 2176 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 2177 drm_vblank_off(dev, pipe);
6b383a7f 2178 intel_crtc_update_cursor(crtc, false);
5eddb70b 2179
6be4a607 2180 /* Disable display plane */
5eddb70b
CW
2181 reg = DSPCNTR(plane);
2182 temp = I915_READ(reg);
2183 if (temp & DISPLAY_PLANE_ENABLE) {
2184 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2185 intel_flush_display_plane(dev, plane);
6be4a607 2186 }
913d8d11 2187
6be4a607
JB
2188 if (dev_priv->cfb_plane == plane &&
2189 dev_priv->display.disable_fbc)
2190 dev_priv->display.disable_fbc(dev);
2c07245f 2191
6be4a607 2192 /* disable cpu pipe, disable after all planes disabled */
5eddb70b
CW
2193 reg = PIPECONF(pipe);
2194 temp = I915_READ(reg);
2195 if (temp & PIPECONF_ENABLE) {
2196 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
17f6766c 2197 POSTING_READ(reg);
6be4a607 2198 /* wait for cpu pipe off, pipe state */
17f6766c 2199 intel_wait_for_pipe_off(dev, intel_crtc->pipe);
5eddb70b 2200 }
32f9d658 2201
6be4a607
JB
2202 /* Disable PF */
2203 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2204 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2c07245f 2205
6be4a607 2206 /* disable CPU FDI tx and PCH FDI rx */
5eddb70b
CW
2207 reg = FDI_TX_CTL(pipe);
2208 temp = I915_READ(reg);
2209 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2210 POSTING_READ(reg);
249c0e64 2211
5eddb70b
CW
2212 reg = FDI_RX_CTL(pipe);
2213 temp = I915_READ(reg);
2214 temp &= ~(0x7 << 16);
2215 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2216 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
6be4a607 2217
5eddb70b 2218 POSTING_READ(reg);
6be4a607
JB
2219 udelay(100);
2220
5b2adf89 2221 /* Ironlake workaround, disable clock pointer after downing FDI */
e07ac3a0
ZW
2222 if (HAS_PCH_IBX(dev))
2223 I915_WRITE(FDI_RX_CHICKEN(pipe),
2224 I915_READ(FDI_RX_CHICKEN(pipe) &
2225 ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
5b2adf89 2226
6be4a607 2227 /* still set train pattern 1 */
5eddb70b
CW
2228 reg = FDI_TX_CTL(pipe);
2229 temp = I915_READ(reg);
6be4a607
JB
2230 temp &= ~FDI_LINK_TRAIN_NONE;
2231 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2232 I915_WRITE(reg, temp);
6be4a607 2233
5eddb70b
CW
2234 reg = FDI_RX_CTL(pipe);
2235 temp = I915_READ(reg);
6be4a607
JB
2236 if (HAS_PCH_CPT(dev)) {
2237 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2238 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2239 } else {
2c07245f
ZW
2240 temp &= ~FDI_LINK_TRAIN_NONE;
2241 temp |= FDI_LINK_TRAIN_PATTERN_1;
6be4a607 2242 }
5eddb70b
CW
2243 /* BPC in FDI rx is consistent with that in PIPECONF */
2244 temp &= ~(0x07 << 16);
2245 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2246 I915_WRITE(reg, temp);
2c07245f 2247
5eddb70b 2248 POSTING_READ(reg);
6be4a607 2249 udelay(100);
2c07245f 2250
6be4a607
JB
2251 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2252 temp = I915_READ(PCH_LVDS);
5eddb70b
CW
2253 if (temp & LVDS_PORT_EN) {
2254 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2255 POSTING_READ(PCH_LVDS);
2256 udelay(100);
2257 }
6be4a607 2258 }
249c0e64 2259
6be4a607 2260 /* disable PCH transcoder */
5eddb70b
CW
2261 reg = TRANSCONF(plane);
2262 temp = I915_READ(reg);
2263 if (temp & TRANS_ENABLE) {
2264 I915_WRITE(reg, temp & ~TRANS_ENABLE);
6be4a607 2265 /* wait for PCH transcoder off, transcoder state */
5eddb70b 2266 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
6be4a607
JB
2267 DRM_ERROR("failed to disable transcoder\n");
2268 }
913d8d11 2269
6be4a607
JB
2270 if (HAS_PCH_CPT(dev)) {
2271 /* disable TRANS_DP_CTL */
5eddb70b
CW
2272 reg = TRANS_DP_CTL(pipe);
2273 temp = I915_READ(reg);
2274 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2275 I915_WRITE(reg, temp);
6be4a607
JB
2276
2277 /* disable DPLL_SEL */
2278 temp = I915_READ(PCH_DPLL_SEL);
5eddb70b 2279 if (pipe == 0)
6be4a607
JB
2280 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2281 else
2282 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2283 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 2284 }
e3421a18 2285
6be4a607 2286 /* disable PCH DPLL */
5eddb70b
CW
2287 reg = PCH_DPLL(pipe);
2288 temp = I915_READ(reg);
2289 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
8db9d77b 2290
6be4a607 2291 /* Switch from PCDclk to Rawclk */
5eddb70b
CW
2292 reg = FDI_RX_CTL(pipe);
2293 temp = I915_READ(reg);
2294 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 2295
6be4a607 2296 /* Disable CPU FDI TX PLL */
5eddb70b
CW
2297 reg = FDI_TX_CTL(pipe);
2298 temp = I915_READ(reg);
2299 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2300
2301 POSTING_READ(reg);
6be4a607 2302 udelay(100);
8db9d77b 2303
5eddb70b
CW
2304 reg = FDI_RX_CTL(pipe);
2305 temp = I915_READ(reg);
2306 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 2307
6be4a607 2308 /* Wait for the clocks to turn off. */
5eddb70b 2309 POSTING_READ(reg);
6be4a607 2310 udelay(100);
6b383a7f 2311
f7abfe8b 2312 intel_crtc->active = false;
6b383a7f
CW
2313 intel_update_watermarks(dev);
2314 intel_update_fbc(dev);
2315 intel_clear_scanline_wait(dev);
6be4a607 2316}
1b3c7a47 2317
6be4a607
JB
2318static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2319{
2320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2321 int pipe = intel_crtc->pipe;
2322 int plane = intel_crtc->plane;
8db9d77b 2323
6be4a607
JB
2324 /* XXX: When our outputs are all unaware of DPMS modes other than off
2325 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2326 */
2327 switch (mode) {
2328 case DRM_MODE_DPMS_ON:
2329 case DRM_MODE_DPMS_STANDBY:
2330 case DRM_MODE_DPMS_SUSPEND:
2331 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2332 ironlake_crtc_enable(crtc);
2333 break;
1b3c7a47 2334
6be4a607
JB
2335 case DRM_MODE_DPMS_OFF:
2336 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2337 ironlake_crtc_disable(crtc);
2c07245f
ZW
2338 break;
2339 }
2340}
2341
02e792fb
DV
2342static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2343{
02e792fb 2344 if (!enable && intel_crtc->overlay) {
23f09ce3 2345 struct drm_device *dev = intel_crtc->base.dev;
03f77ea5 2346
23f09ce3
CW
2347 mutex_lock(&dev->struct_mutex);
2348 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2349 mutex_unlock(&dev->struct_mutex);
02e792fb 2350 }
02e792fb 2351
5dcdbcb0
CW
2352 /* Let userspace switch the overlay on again. In most cases userspace
2353 * has to recompute where to put it anyway.
2354 */
02e792fb
DV
2355}
2356
0b8765c6 2357static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB
2358{
2359 struct drm_device *dev = crtc->dev;
79e53945
JB
2360 struct drm_i915_private *dev_priv = dev->dev_private;
2361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2362 int pipe = intel_crtc->pipe;
80824003 2363 int plane = intel_crtc->plane;
5eddb70b 2364 u32 reg, temp;
79e53945 2365
f7abfe8b
CW
2366 if (intel_crtc->active)
2367 return;
2368
2369 intel_crtc->active = true;
6b383a7f
CW
2370 intel_update_watermarks(dev);
2371
0b8765c6 2372 /* Enable the DPLL */
5eddb70b
CW
2373 reg = DPLL(pipe);
2374 temp = I915_READ(reg);
0b8765c6 2375 if ((temp & DPLL_VCO_ENABLE) == 0) {
5eddb70b
CW
2376 I915_WRITE(reg, temp);
2377
0b8765c6 2378 /* Wait for the clocks to stabilize. */
5eddb70b 2379 POSTING_READ(reg);
0b8765c6 2380 udelay(150);
5eddb70b
CW
2381
2382 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2383
0b8765c6 2384 /* Wait for the clocks to stabilize. */
5eddb70b 2385 POSTING_READ(reg);
0b8765c6 2386 udelay(150);
5eddb70b
CW
2387
2388 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2389
0b8765c6 2390 /* Wait for the clocks to stabilize. */
5eddb70b 2391 POSTING_READ(reg);
0b8765c6
JB
2392 udelay(150);
2393 }
79e53945 2394
0b8765c6 2395 /* Enable the pipe */
5eddb70b
CW
2396 reg = PIPECONF(pipe);
2397 temp = I915_READ(reg);
2398 if ((temp & PIPECONF_ENABLE) == 0)
2399 I915_WRITE(reg, temp | PIPECONF_ENABLE);
79e53945 2400
0b8765c6 2401 /* Enable the plane */
5eddb70b
CW
2402 reg = DSPCNTR(plane);
2403 temp = I915_READ(reg);
0b8765c6 2404 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
5eddb70b
CW
2405 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2406 intel_flush_display_plane(dev, plane);
0b8765c6 2407 }
79e53945 2408
0b8765c6 2409 intel_crtc_load_lut(crtc);
bed4a673 2410 intel_update_fbc(dev);
79e53945 2411
0b8765c6
JB
2412 /* Give the overlay scaler a chance to enable if it's on this pipe */
2413 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 2414 intel_crtc_update_cursor(crtc, true);
0b8765c6 2415}
79e53945 2416
0b8765c6
JB
2417static void i9xx_crtc_disable(struct drm_crtc *crtc)
2418{
2419 struct drm_device *dev = crtc->dev;
2420 struct drm_i915_private *dev_priv = dev->dev_private;
2421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2422 int pipe = intel_crtc->pipe;
2423 int plane = intel_crtc->plane;
5eddb70b 2424 u32 reg, temp;
b690e96c 2425
f7abfe8b
CW
2426 if (!intel_crtc->active)
2427 return;
2428
0b8765c6 2429 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW
2430 intel_crtc_wait_for_pending_flips(crtc);
2431 drm_vblank_off(dev, pipe);
0b8765c6 2432 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 2433 intel_crtc_update_cursor(crtc, false);
0b8765c6
JB
2434
2435 if (dev_priv->cfb_plane == plane &&
2436 dev_priv->display.disable_fbc)
2437 dev_priv->display.disable_fbc(dev);
79e53945 2438
0b8765c6 2439 /* Disable display plane */
5eddb70b
CW
2440 reg = DSPCNTR(plane);
2441 temp = I915_READ(reg);
2442 if (temp & DISPLAY_PLANE_ENABLE) {
2443 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
0b8765c6 2444 /* Flush the plane changes */
5eddb70b 2445 intel_flush_display_plane(dev, plane);
0b8765c6 2446
0b8765c6 2447 /* Wait for vblank for the disable to take effect */
a6c45cf0 2448 if (IS_GEN2(dev))
ab7ad7f6 2449 intel_wait_for_vblank(dev, pipe);
0b8765c6 2450 }
79e53945 2451
0b8765c6 2452 /* Don't disable pipe A or pipe A PLLs if needed */
5eddb70b 2453 if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
6b383a7f 2454 goto done;
0b8765c6
JB
2455
2456 /* Next, disable display pipes */
5eddb70b
CW
2457 reg = PIPECONF(pipe);
2458 temp = I915_READ(reg);
2459 if (temp & PIPECONF_ENABLE) {
2460 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2461
ab7ad7f6 2462 /* Wait for the pipe to turn off */
5eddb70b 2463 POSTING_READ(reg);
ab7ad7f6 2464 intel_wait_for_pipe_off(dev, pipe);
0b8765c6
JB
2465 }
2466
5eddb70b
CW
2467 reg = DPLL(pipe);
2468 temp = I915_READ(reg);
2469 if (temp & DPLL_VCO_ENABLE) {
2470 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
0b8765c6 2471
5eddb70b
CW
2472 /* Wait for the clocks to turn off. */
2473 POSTING_READ(reg);
2474 udelay(150);
0b8765c6 2475 }
6b383a7f
CW
2476
2477done:
f7abfe8b 2478 intel_crtc->active = false;
6b383a7f
CW
2479 intel_update_fbc(dev);
2480 intel_update_watermarks(dev);
2481 intel_clear_scanline_wait(dev);
0b8765c6
JB
2482}
2483
2484static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2485{
2486 /* XXX: When our outputs are all unaware of DPMS modes other than off
2487 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2488 */
2489 switch (mode) {
2490 case DRM_MODE_DPMS_ON:
2491 case DRM_MODE_DPMS_STANDBY:
2492 case DRM_MODE_DPMS_SUSPEND:
2493 i9xx_crtc_enable(crtc);
2494 break;
2495 case DRM_MODE_DPMS_OFF:
2496 i9xx_crtc_disable(crtc);
79e53945
JB
2497 break;
2498 }
2c07245f
ZW
2499}
2500
2501/**
2502 * Sets the power management mode of the pipe and plane.
2c07245f
ZW
2503 */
2504static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2505{
2506 struct drm_device *dev = crtc->dev;
e70236a8 2507 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW
2508 struct drm_i915_master_private *master_priv;
2509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2510 int pipe = intel_crtc->pipe;
2511 bool enabled;
2512
032d2a0d
CW
2513 if (intel_crtc->dpms_mode == mode)
2514 return;
2515
65655d4a 2516 intel_crtc->dpms_mode = mode;
debcaddc 2517
e70236a8 2518 dev_priv->display.dpms(crtc, mode);
79e53945
JB
2519
2520 if (!dev->primary->master)
2521 return;
2522
2523 master_priv = dev->primary->master->driver_priv;
2524 if (!master_priv->sarea_priv)
2525 return;
2526
2527 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2528
2529 switch (pipe) {
2530 case 0:
2531 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2532 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2533 break;
2534 case 1:
2535 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2536 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2537 break;
2538 default:
2539 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2540 break;
2541 }
79e53945
JB
2542}
2543
cdd59983
CW
2544static void intel_crtc_disable(struct drm_crtc *crtc)
2545{
2546 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2547 struct drm_device *dev = crtc->dev;
2548
2549 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2550
2551 if (crtc->fb) {
2552 mutex_lock(&dev->struct_mutex);
2553 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2554 mutex_unlock(&dev->struct_mutex);
2555 }
2556}
2557
7e7d76c3
JB
2558/* Prepare for a mode set.
2559 *
2560 * Note we could be a lot smarter here. We need to figure out which outputs
2561 * will be enabled, which disabled (in short, how the config will changes)
2562 * and perform the minimum necessary steps to accomplish that, e.g. updating
2563 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2564 * panel fitting is in the proper state, etc.
2565 */
2566static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 2567{
7e7d76c3 2568 i9xx_crtc_disable(crtc);
79e53945
JB
2569}
2570
7e7d76c3 2571static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 2572{
7e7d76c3 2573 i9xx_crtc_enable(crtc);
7e7d76c3
JB
2574}
2575
2576static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2577{
7e7d76c3 2578 ironlake_crtc_disable(crtc);
7e7d76c3
JB
2579}
2580
2581static void ironlake_crtc_commit(struct drm_crtc *crtc)
2582{
7e7d76c3 2583 ironlake_crtc_enable(crtc);
79e53945
JB
2584}
2585
2586void intel_encoder_prepare (struct drm_encoder *encoder)
2587{
2588 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2589 /* lvds has its own version of prepare see intel_lvds_prepare */
2590 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2591}
2592
2593void intel_encoder_commit (struct drm_encoder *encoder)
2594{
2595 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2596 /* lvds has its own version of commit see intel_lvds_commit */
2597 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2598}
2599
ea5b213a
CW
2600void intel_encoder_destroy(struct drm_encoder *encoder)
2601{
4ef69c7a 2602 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 2603
ea5b213a
CW
2604 drm_encoder_cleanup(encoder);
2605 kfree(intel_encoder);
2606}
2607
79e53945
JB
2608static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2609 struct drm_display_mode *mode,
2610 struct drm_display_mode *adjusted_mode)
2611{
2c07245f 2612 struct drm_device *dev = crtc->dev;
89749350 2613
bad720ff 2614 if (HAS_PCH_SPLIT(dev)) {
2c07245f 2615 /* FDI link clock is fixed at 2.7G */
2377b741
JB
2616 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2617 return false;
2c07245f 2618 }
89749350
CW
2619
2620 /* XXX some encoders set the crtcinfo, others don't.
2621 * Obviously we need some form of conflict resolution here...
2622 */
2623 if (adjusted_mode->crtc_htotal == 0)
2624 drm_mode_set_crtcinfo(adjusted_mode, 0);
2625
79e53945
JB
2626 return true;
2627}
2628
e70236a8
JB
2629static int i945_get_display_clock_speed(struct drm_device *dev)
2630{
2631 return 400000;
2632}
79e53945 2633
e70236a8 2634static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 2635{
e70236a8
JB
2636 return 333000;
2637}
79e53945 2638
e70236a8
JB
2639static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2640{
2641 return 200000;
2642}
79e53945 2643
e70236a8
JB
2644static int i915gm_get_display_clock_speed(struct drm_device *dev)
2645{
2646 u16 gcfgc = 0;
79e53945 2647
e70236a8
JB
2648 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2649
2650 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2651 return 133000;
2652 else {
2653 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2654 case GC_DISPLAY_CLOCK_333_MHZ:
2655 return 333000;
2656 default:
2657 case GC_DISPLAY_CLOCK_190_200_MHZ:
2658 return 190000;
79e53945 2659 }
e70236a8
JB
2660 }
2661}
2662
2663static int i865_get_display_clock_speed(struct drm_device *dev)
2664{
2665 return 266000;
2666}
2667
2668static int i855_get_display_clock_speed(struct drm_device *dev)
2669{
2670 u16 hpllcc = 0;
2671 /* Assume that the hardware is in the high speed state. This
2672 * should be the default.
2673 */
2674 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2675 case GC_CLOCK_133_200:
2676 case GC_CLOCK_100_200:
2677 return 200000;
2678 case GC_CLOCK_166_250:
2679 return 250000;
2680 case GC_CLOCK_100_133:
79e53945 2681 return 133000;
e70236a8 2682 }
79e53945 2683
e70236a8
JB
2684 /* Shouldn't happen */
2685 return 0;
2686}
79e53945 2687
e70236a8
JB
2688static int i830_get_display_clock_speed(struct drm_device *dev)
2689{
2690 return 133000;
79e53945
JB
2691}
2692
2c07245f
ZW
2693struct fdi_m_n {
2694 u32 tu;
2695 u32 gmch_m;
2696 u32 gmch_n;
2697 u32 link_m;
2698 u32 link_n;
2699};
2700
2701static void
2702fdi_reduce_ratio(u32 *num, u32 *den)
2703{
2704 while (*num > 0xffffff || *den > 0xffffff) {
2705 *num >>= 1;
2706 *den >>= 1;
2707 }
2708}
2709
2c07245f 2710static void
f2b115e6
AJ
2711ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2712 int link_clock, struct fdi_m_n *m_n)
2c07245f 2713{
2c07245f
ZW
2714 m_n->tu = 64; /* default size */
2715
22ed1113
CW
2716 /* BUG_ON(pixel_clock > INT_MAX / 36); */
2717 m_n->gmch_m = bits_per_pixel * pixel_clock;
2718 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW
2719 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2720
22ed1113
CW
2721 m_n->link_m = pixel_clock;
2722 m_n->link_n = link_clock;
2c07245f
ZW
2723 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2724}
2725
2726
7662c8bd
SL
2727struct intel_watermark_params {
2728 unsigned long fifo_size;
2729 unsigned long max_wm;
2730 unsigned long default_wm;
2731 unsigned long guard_size;
2732 unsigned long cacheline_size;
2733};
2734
f2b115e6
AJ
2735/* Pineview has different values for various configs */
2736static struct intel_watermark_params pineview_display_wm = {
2737 PINEVIEW_DISPLAY_FIFO,
2738 PINEVIEW_MAX_WM,
2739 PINEVIEW_DFT_WM,
2740 PINEVIEW_GUARD_WM,
2741 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 2742};
f2b115e6
AJ
2743static struct intel_watermark_params pineview_display_hplloff_wm = {
2744 PINEVIEW_DISPLAY_FIFO,
2745 PINEVIEW_MAX_WM,
2746 PINEVIEW_DFT_HPLLOFF_WM,
2747 PINEVIEW_GUARD_WM,
2748 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 2749};
f2b115e6
AJ
2750static struct intel_watermark_params pineview_cursor_wm = {
2751 PINEVIEW_CURSOR_FIFO,
2752 PINEVIEW_CURSOR_MAX_WM,
2753 PINEVIEW_CURSOR_DFT_WM,
2754 PINEVIEW_CURSOR_GUARD_WM,
2755 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 2756};
f2b115e6
AJ
2757static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2758 PINEVIEW_CURSOR_FIFO,
2759 PINEVIEW_CURSOR_MAX_WM,
2760 PINEVIEW_CURSOR_DFT_WM,
2761 PINEVIEW_CURSOR_GUARD_WM,
2762 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 2763};
0e442c60
JB
2764static struct intel_watermark_params g4x_wm_info = {
2765 G4X_FIFO_SIZE,
2766 G4X_MAX_WM,
2767 G4X_MAX_WM,
2768 2,
2769 G4X_FIFO_LINE_SIZE,
2770};
4fe5e611
ZY
2771static struct intel_watermark_params g4x_cursor_wm_info = {
2772 I965_CURSOR_FIFO,
2773 I965_CURSOR_MAX_WM,
2774 I965_CURSOR_DFT_WM,
2775 2,
2776 G4X_FIFO_LINE_SIZE,
2777};
2778static struct intel_watermark_params i965_cursor_wm_info = {
2779 I965_CURSOR_FIFO,
2780 I965_CURSOR_MAX_WM,
2781 I965_CURSOR_DFT_WM,
2782 2,
2783 I915_FIFO_LINE_SIZE,
2784};
7662c8bd 2785static struct intel_watermark_params i945_wm_info = {
dff33cfc 2786 I945_FIFO_SIZE,
7662c8bd
SL
2787 I915_MAX_WM,
2788 1,
dff33cfc
JB
2789 2,
2790 I915_FIFO_LINE_SIZE
7662c8bd
SL
2791};
2792static struct intel_watermark_params i915_wm_info = {
dff33cfc 2793 I915_FIFO_SIZE,
7662c8bd
SL
2794 I915_MAX_WM,
2795 1,
dff33cfc 2796 2,
7662c8bd
SL
2797 I915_FIFO_LINE_SIZE
2798};
2799static struct intel_watermark_params i855_wm_info = {
2800 I855GM_FIFO_SIZE,
2801 I915_MAX_WM,
2802 1,
dff33cfc 2803 2,
7662c8bd
SL
2804 I830_FIFO_LINE_SIZE
2805};
2806static struct intel_watermark_params i830_wm_info = {
2807 I830_FIFO_SIZE,
2808 I915_MAX_WM,
2809 1,
dff33cfc 2810 2,
7662c8bd
SL
2811 I830_FIFO_LINE_SIZE
2812};
2813
7f8a8569
ZW
2814static struct intel_watermark_params ironlake_display_wm_info = {
2815 ILK_DISPLAY_FIFO,
2816 ILK_DISPLAY_MAXWM,
2817 ILK_DISPLAY_DFTWM,
2818 2,
2819 ILK_FIFO_LINE_SIZE
2820};
2821
c936f44d
ZY
2822static struct intel_watermark_params ironlake_cursor_wm_info = {
2823 ILK_CURSOR_FIFO,
2824 ILK_CURSOR_MAXWM,
2825 ILK_CURSOR_DFTWM,
2826 2,
2827 ILK_FIFO_LINE_SIZE
2828};
2829
7f8a8569
ZW
2830static struct intel_watermark_params ironlake_display_srwm_info = {
2831 ILK_DISPLAY_SR_FIFO,
2832 ILK_DISPLAY_MAX_SRWM,
2833 ILK_DISPLAY_DFT_SRWM,
2834 2,
2835 ILK_FIFO_LINE_SIZE
2836};
2837
2838static struct intel_watermark_params ironlake_cursor_srwm_info = {
2839 ILK_CURSOR_SR_FIFO,
2840 ILK_CURSOR_MAX_SRWM,
2841 ILK_CURSOR_DFT_SRWM,
2842 2,
2843 ILK_FIFO_LINE_SIZE
2844};
2845
dff33cfc
JB
2846/**
2847 * intel_calculate_wm - calculate watermark level
2848 * @clock_in_khz: pixel clock
2849 * @wm: chip FIFO params
2850 * @pixel_size: display pixel size
2851 * @latency_ns: memory latency for the platform
2852 *
2853 * Calculate the watermark level (the level at which the display plane will
2854 * start fetching from memory again). Each chip has a different display
2855 * FIFO size and allocation, so the caller needs to figure that out and pass
2856 * in the correct intel_watermark_params structure.
2857 *
2858 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2859 * on the pixel size. When it reaches the watermark level, it'll start
2860 * fetching FIFO line sized based chunks from memory until the FIFO fills
2861 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2862 * will occur, and a display engine hang could result.
2863 */
7662c8bd
SL
2864static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2865 struct intel_watermark_params *wm,
2866 int pixel_size,
2867 unsigned long latency_ns)
2868{
390c4dd4 2869 long entries_required, wm_size;
dff33cfc 2870
d660467c
JB
2871 /*
2872 * Note: we need to make sure we don't overflow for various clock &
2873 * latency values.
2874 * clocks go from a few thousand to several hundred thousand.
2875 * latency is usually a few thousand
2876 */
2877 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2878 1000;
8de9b311 2879 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 2880
28c97730 2881 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
dff33cfc
JB
2882
2883 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2884
28c97730 2885 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
7662c8bd 2886
390c4dd4
JB
2887 /* Don't promote wm_size to unsigned... */
2888 if (wm_size > (long)wm->max_wm)
7662c8bd 2889 wm_size = wm->max_wm;
c3add4b6 2890 if (wm_size <= 0)
7662c8bd
SL
2891 wm_size = wm->default_wm;
2892 return wm_size;
2893}
2894
2895struct cxsr_latency {
2896 int is_desktop;
95534263 2897 int is_ddr3;
7662c8bd
SL
2898 unsigned long fsb_freq;
2899 unsigned long mem_freq;
2900 unsigned long display_sr;
2901 unsigned long display_hpll_disable;
2902 unsigned long cursor_sr;
2903 unsigned long cursor_hpll_disable;
2904};
2905
403c89ff 2906static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP
2907 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2908 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2909 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2910 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2911 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2912
2913 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2914 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2915 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2916 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2917 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2918
2919 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2920 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2921 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2922 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2923 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2924
2925 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2926 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2927 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2928 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2929 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2930
2931 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2932 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2933 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2934 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2935 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2936
2937 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2938 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2939 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2940 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2941 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL
2942};
2943
403c89ff
CW
2944static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2945 int is_ddr3,
2946 int fsb,
2947 int mem)
7662c8bd 2948{
403c89ff 2949 const struct cxsr_latency *latency;
7662c8bd 2950 int i;
7662c8bd
SL
2951
2952 if (fsb == 0 || mem == 0)
2953 return NULL;
2954
2955 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2956 latency = &cxsr_latency_table[i];
2957 if (is_desktop == latency->is_desktop &&
95534263 2958 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR
2959 fsb == latency->fsb_freq && mem == latency->mem_freq)
2960 return latency;
7662c8bd 2961 }
decbbcda 2962
28c97730 2963 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR
2964
2965 return NULL;
7662c8bd
SL
2966}
2967
f2b115e6 2968static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL
2969{
2970 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL
2971
2972 /* deactivate cxsr */
3e33d94d 2973 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL
2974}
2975
bcc24fb4
JB
2976/*
2977 * Latency for FIFO fetches is dependent on several factors:
2978 * - memory configuration (speed, channels)
2979 * - chipset
2980 * - current MCH state
2981 * It can be fairly high in some situations, so here we assume a fairly
2982 * pessimal value. It's a tradeoff between extra memory fetches (if we
2983 * set this value too high, the FIFO will fetch frequently to stay full)
2984 * and power consumption (set it too low to save power and we might see
2985 * FIFO underruns and display "flicker").
2986 *
2987 * A value of 5us seems to be a good balance; safe for very low end
2988 * platforms but not overly aggressive on lower latency configs.
2989 */
69e302a9 2990static const int latency_ns = 5000;
7662c8bd 2991
e70236a8 2992static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB
2993{
2994 struct drm_i915_private *dev_priv = dev->dev_private;
2995 uint32_t dsparb = I915_READ(DSPARB);
2996 int size;
2997
8de9b311
CW
2998 size = dsparb & 0x7f;
2999 if (plane)
3000 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 3001
28c97730 3002 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3003 plane ? "B" : "A", size);
dff33cfc
JB
3004
3005 return size;
3006}
7662c8bd 3007
e70236a8
JB
3008static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3009{
3010 struct drm_i915_private *dev_priv = dev->dev_private;
3011 uint32_t dsparb = I915_READ(DSPARB);
3012 int size;
3013
8de9b311
CW
3014 size = dsparb & 0x1ff;
3015 if (plane)
3016 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 3017 size >>= 1; /* Convert to cachelines */
dff33cfc 3018
28c97730 3019 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3020 plane ? "B" : "A", size);
dff33cfc
JB
3021
3022 return size;
3023}
7662c8bd 3024
e70236a8
JB
3025static int i845_get_fifo_size(struct drm_device *dev, int plane)
3026{
3027 struct drm_i915_private *dev_priv = dev->dev_private;
3028 uint32_t dsparb = I915_READ(DSPARB);
3029 int size;
3030
3031 size = dsparb & 0x7f;
3032 size >>= 2; /* Convert to cachelines */
3033
28c97730 3034 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW
3035 plane ? "B" : "A",
3036 size);
e70236a8
JB
3037
3038 return size;
3039}
3040
3041static int i830_get_fifo_size(struct drm_device *dev, int plane)
3042{
3043 struct drm_i915_private *dev_priv = dev->dev_private;
3044 uint32_t dsparb = I915_READ(DSPARB);
3045 int size;
3046
3047 size = dsparb & 0x7f;
3048 size >>= 1; /* Convert to cachelines */
3049
28c97730 3050 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3051 plane ? "B" : "A", size);
e70236a8
JB
3052
3053 return size;
3054}
3055
d4294342 3056static void pineview_update_wm(struct drm_device *dev, int planea_clock,
5eddb70b
CW
3057 int planeb_clock, int sr_hdisplay, int unused,
3058 int pixel_size)
d4294342
ZY
3059{
3060 struct drm_i915_private *dev_priv = dev->dev_private;
403c89ff 3061 const struct cxsr_latency *latency;
d4294342
ZY
3062 u32 reg;
3063 unsigned long wm;
d4294342
ZY
3064 int sr_clock;
3065
403c89ff 3066 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 3067 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY
3068 if (!latency) {
3069 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3070 pineview_disable_cxsr(dev);
3071 return;
3072 }
3073
3074 if (!planea_clock || !planeb_clock) {
3075 sr_clock = planea_clock ? planea_clock : planeb_clock;
3076
3077 /* Display SR */
3078 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3079 pixel_size, latency->display_sr);
3080 reg = I915_READ(DSPFW1);
3081 reg &= ~DSPFW_SR_MASK;
3082 reg |= wm << DSPFW_SR_SHIFT;
3083 I915_WRITE(DSPFW1, reg);
3084 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3085
3086 /* cursor SR */
3087 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3088 pixel_size, latency->cursor_sr);
3089 reg = I915_READ(DSPFW3);
3090 reg &= ~DSPFW_CURSOR_SR_MASK;
3091 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3092 I915_WRITE(DSPFW3, reg);
3093
3094 /* Display HPLL off SR */
3095 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3096 pixel_size, latency->display_hpll_disable);
3097 reg = I915_READ(DSPFW3);
3098 reg &= ~DSPFW_HPLL_SR_MASK;
3099 reg |= wm & DSPFW_HPLL_SR_MASK;
3100 I915_WRITE(DSPFW3, reg);
3101
3102 /* cursor HPLL off SR */
3103 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3104 pixel_size, latency->cursor_hpll_disable);
3105 reg = I915_READ(DSPFW3);
3106 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3107 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3108 I915_WRITE(DSPFW3, reg);
3109 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3110
3111 /* activate cxsr */
3e33d94d
CW
3112 I915_WRITE(DSPFW3,
3113 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY
3114 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3115 } else {
3116 pineview_disable_cxsr(dev);
3117 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3118 }
3119}
3120
0e442c60 3121static void g4x_update_wm(struct drm_device *dev, int planea_clock,
fa143215
ZY
3122 int planeb_clock, int sr_hdisplay, int sr_htotal,
3123 int pixel_size)
652c393a
JB
3124{
3125 struct drm_i915_private *dev_priv = dev->dev_private;
0e442c60
JB
3126 int total_size, cacheline_size;
3127 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3128 struct intel_watermark_params planea_params, planeb_params;
3129 unsigned long line_time_us;
3130 int sr_clock, sr_entries = 0, entries_required;
652c393a 3131
0e442c60
JB
3132 /* Create copies of the base settings for each pipe */
3133 planea_params = planeb_params = g4x_wm_info;
3134
3135 /* Grab a couple of global values before we overwrite them */
3136 total_size = planea_params.fifo_size;
3137 cacheline_size = planea_params.cacheline_size;
3138
3139 /*
3140 * Note: we need to make sure we don't overflow for various clock &
3141 * latency values.
3142 * clocks go from a few thousand to several hundred thousand.
3143 * latency is usually a few thousand
3144 */
3145 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3146 1000;
8de9b311 3147 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
0e442c60
JB
3148 planea_wm = entries_required + planea_params.guard_size;
3149
3150 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3151 1000;
8de9b311 3152 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
0e442c60
JB
3153 planeb_wm = entries_required + planeb_params.guard_size;
3154
3155 cursora_wm = cursorb_wm = 16;
3156 cursor_sr = 32;
3157
3158 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3159
3160 /* Calc sr entries for one plane configs */
3161 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3162 /* self-refresh has much higher latency */
69e302a9 3163 static const int sr_latency_ns = 12000;
0e442c60
JB
3164
3165 sr_clock = planea_clock ? planea_clock : planeb_clock;
fa143215 3166 line_time_us = ((sr_htotal * 1000) / sr_clock);
0e442c60
JB
3167
3168 /* Use ns/us then divide to preserve precision */
fa143215 3169 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 3170 pixel_size * sr_hdisplay;
8de9b311 3171 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
4fe5e611
ZY
3172
3173 entries_required = (((sr_latency_ns / line_time_us) +
3174 1000) / 1000) * pixel_size * 64;
8de9b311 3175 entries_required = DIV_ROUND_UP(entries_required,
5eddb70b 3176 g4x_cursor_wm_info.cacheline_size);
4fe5e611
ZY
3177 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3178
3179 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3180 cursor_sr = g4x_cursor_wm_info.max_wm;
3181 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3182 "cursor %d\n", sr_entries, cursor_sr);
3183
0e442c60 3184 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ
3185 } else {
3186 /* Turn off self refresh if both pipes are enabled */
3187 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
5eddb70b 3188 & ~FW_BLC_SELF_EN);
0e442c60
JB
3189 }
3190
3191 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3192 planea_wm, planeb_wm, sr_entries);
3193
3194 planea_wm &= 0x3f;
3195 planeb_wm &= 0x3f;
3196
3197 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3198 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3199 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3200 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3201 (cursora_wm << DSPFW_CURSORA_SHIFT));
3202 /* HPLL off in SR has some issues on G4x... disable it */
3203 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3204 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB
3205}
3206
1dc7546d 3207static void i965_update_wm(struct drm_device *dev, int planea_clock,
fa143215
ZY
3208 int planeb_clock, int sr_hdisplay, int sr_htotal,
3209 int pixel_size)
7662c8bd
SL
3210{
3211 struct drm_i915_private *dev_priv = dev->dev_private;
1dc7546d
JB
3212 unsigned long line_time_us;
3213 int sr_clock, sr_entries, srwm = 1;
4fe5e611 3214 int cursor_sr = 16;
1dc7546d
JB
3215
3216 /* Calc sr entries for one plane configs */
3217 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3218 /* self-refresh has much higher latency */
69e302a9 3219 static const int sr_latency_ns = 12000;
1dc7546d
JB
3220
3221 sr_clock = planea_clock ? planea_clock : planeb_clock;
fa143215 3222 line_time_us = ((sr_htotal * 1000) / sr_clock);
1dc7546d
JB
3223
3224 /* Use ns/us then divide to preserve precision */
fa143215 3225 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 3226 pixel_size * sr_hdisplay;
8de9b311 3227 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
1dc7546d 3228 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
1b07e04e 3229 srwm = I965_FIFO_SIZE - sr_entries;
1dc7546d
JB
3230 if (srwm < 0)
3231 srwm = 1;
1b07e04e 3232 srwm &= 0x1ff;
4fe5e611
ZY
3233
3234 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 3235 pixel_size * 64;
8de9b311
CW
3236 sr_entries = DIV_ROUND_UP(sr_entries,
3237 i965_cursor_wm_info.cacheline_size);
4fe5e611 3238 cursor_sr = i965_cursor_wm_info.fifo_size -
5eddb70b 3239 (sr_entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY
3240
3241 if (cursor_sr > i965_cursor_wm_info.max_wm)
3242 cursor_sr = i965_cursor_wm_info.max_wm;
3243
3244 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3245 "cursor %d\n", srwm, cursor_sr);
3246
a6c45cf0 3247 if (IS_CRESTLINE(dev))
adcdbc66 3248 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ
3249 } else {
3250 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 3251 if (IS_CRESTLINE(dev))
adcdbc66
JB
3252 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3253 & ~FW_BLC_SELF_EN);
1dc7546d 3254 }
7662c8bd 3255
1dc7546d
JB
3256 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3257 srwm);
7662c8bd
SL
3258
3259 /* 965 has limitations... */
1dc7546d
JB
3260 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3261 (8 << 0));
7662c8bd 3262 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY
3263 /* update cursor SR watermark */
3264 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL
3265}
3266
3267static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
fa143215
ZY
3268 int planeb_clock, int sr_hdisplay, int sr_htotal,
3269 int pixel_size)
7662c8bd
SL
3270{
3271 struct drm_i915_private *dev_priv = dev->dev_private;
dff33cfc
JB
3272 uint32_t fwater_lo;
3273 uint32_t fwater_hi;
3274 int total_size, cacheline_size, cwm, srwm = 1;
3275 int planea_wm, planeb_wm;
3276 struct intel_watermark_params planea_params, planeb_params;
7662c8bd
SL
3277 unsigned long line_time_us;
3278 int sr_clock, sr_entries = 0;
3279
dff33cfc 3280 /* Create copies of the base settings for each pipe */
a6c45cf0 3281 if (IS_CRESTLINE(dev) || IS_I945GM(dev))
dff33cfc 3282 planea_params = planeb_params = i945_wm_info;
a6c45cf0 3283 else if (!IS_GEN2(dev))
dff33cfc 3284 planea_params = planeb_params = i915_wm_info;
7662c8bd 3285 else
dff33cfc 3286 planea_params = planeb_params = i855_wm_info;
7662c8bd 3287
dff33cfc
JB
3288 /* Grab a couple of global values before we overwrite them */
3289 total_size = planea_params.fifo_size;
3290 cacheline_size = planea_params.cacheline_size;
7662c8bd 3291
dff33cfc 3292 /* Update per-plane FIFO sizes */
e70236a8
JB
3293 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3294 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
7662c8bd 3295
dff33cfc
JB
3296 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3297 pixel_size, latency_ns);
3298 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3299 pixel_size, latency_ns);
28c97730 3300 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL
3301
3302 /*
3303 * Overlay gets an aggressive default since video jitter is bad.
3304 */
3305 cwm = 2;
3306
dff33cfc 3307 /* Calc sr entries for one plane configs */
652c393a
JB
3308 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3309 (!planea_clock || !planeb_clock)) {
dff33cfc 3310 /* self-refresh has much higher latency */
69e302a9 3311 static const int sr_latency_ns = 6000;
dff33cfc 3312
7662c8bd 3313 sr_clock = planea_clock ? planea_clock : planeb_clock;
fa143215 3314 line_time_us = ((sr_htotal * 1000) / sr_clock);
dff33cfc
JB
3315
3316 /* Use ns/us then divide to preserve precision */
fa143215 3317 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 3318 pixel_size * sr_hdisplay;
8de9b311 3319 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
28c97730 3320 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
dff33cfc
JB
3321 srwm = total_size - sr_entries;
3322 if (srwm < 0)
3323 srwm = 1;
ee980b80
LP
3324
3325 if (IS_I945G(dev) || IS_I945GM(dev))
3326 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3327 else if (IS_I915GM(dev)) {
3328 /* 915M has a smaller SRWM field */
3329 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3330 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3331 }
33c5fd12
DJ
3332 } else {
3333 /* Turn off self refresh if both pipes are enabled */
ee980b80
LP
3334 if (IS_I945G(dev) || IS_I945GM(dev)) {
3335 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3336 & ~FW_BLC_SELF_EN);
3337 } else if (IS_I915GM(dev)) {
3338 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3339 }
7662c8bd
SL
3340 }
3341
28c97730 3342 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 3343 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 3344
dff33cfc
JB
3345 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3346 fwater_hi = (cwm & 0x1f);
3347
3348 /* Set request length to 8 cachelines per fetch */
3349 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3350 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL
3351
3352 I915_WRITE(FW_BLC, fwater_lo);
3353 I915_WRITE(FW_BLC2, fwater_hi);
7662c8bd
SL
3354}
3355
e70236a8 3356static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
fa143215 3357 int unused2, int unused3, int pixel_size)
7662c8bd
SL
3358{
3359 struct drm_i915_private *dev_priv = dev->dev_private;
f3601326 3360 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
dff33cfc 3361 int planea_wm;
7662c8bd 3362
e70236a8 3363 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
7662c8bd 3364
dff33cfc
JB
3365 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3366 pixel_size, latency_ns);
f3601326
JB
3367 fwater_lo |= (3<<8) | planea_wm;
3368
28c97730 3369 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL
3370
3371 I915_WRITE(FW_BLC, fwater_lo);
3372}
3373
7f8a8569 3374#define ILK_LP0_PLANE_LATENCY 700
c936f44d 3375#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 3376
4ed765f9
CW
3377static bool ironlake_compute_wm0(struct drm_device *dev,
3378 int pipe,
3379 int *plane_wm,
3380 int *cursor_wm)
7f8a8569 3381{
c936f44d 3382 struct drm_crtc *crtc;
4ed765f9
CW
3383 int htotal, hdisplay, clock, pixel_size = 0;
3384 int line_time_us, line_count, entries;
c936f44d 3385
4ed765f9
CW
3386 crtc = intel_get_crtc_for_pipe(dev, pipe);
3387 if (crtc->fb == NULL || !crtc->enabled)
3388 return false;
7f8a8569 3389
4ed765f9
CW
3390 htotal = crtc->mode.htotal;
3391 hdisplay = crtc->mode.hdisplay;
3392 clock = crtc->mode.clock;
3393 pixel_size = crtc->fb->bits_per_pixel / 8;
3394
3395 /* Use the small buffer method to calculate plane watermark */
3396 entries = ((clock * pixel_size / 1000) * ILK_LP0_PLANE_LATENCY) / 1000;
3397 entries = DIV_ROUND_UP(entries,
3398 ironlake_display_wm_info.cacheline_size);
3399 *plane_wm = entries + ironlake_display_wm_info.guard_size;
3400 if (*plane_wm > (int)ironlake_display_wm_info.max_wm)
3401 *plane_wm = ironlake_display_wm_info.max_wm;
3402
3403 /* Use the large buffer method to calculate cursor watermark */
3404 line_time_us = ((htotal * 1000) / clock);
3405 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3406 entries = line_count * 64 * pixel_size;
3407 entries = DIV_ROUND_UP(entries,
3408 ironlake_cursor_wm_info.cacheline_size);
3409 *cursor_wm = entries + ironlake_cursor_wm_info.guard_size;
3410 if (*cursor_wm > ironlake_cursor_wm_info.max_wm)
3411 *cursor_wm = ironlake_cursor_wm_info.max_wm;
7f8a8569 3412
4ed765f9
CW
3413 return true;
3414}
c936f44d 3415
4ed765f9
CW
3416static void ironlake_update_wm(struct drm_device *dev,
3417 int planea_clock, int planeb_clock,
3418 int sr_hdisplay, int sr_htotal,
3419 int pixel_size)
3420{
3421 struct drm_i915_private *dev_priv = dev->dev_private;
3422 int plane_wm, cursor_wm, enabled;
3423 int tmp;
c936f44d 3424
4ed765f9
CW
3425 enabled = 0;
3426 if (ironlake_compute_wm0(dev, 0, &plane_wm, &cursor_wm)) {
3427 I915_WRITE(WM0_PIPEA_ILK,
3428 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3429 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3430 " plane %d, " "cursor: %d\n",
3431 plane_wm, cursor_wm);
3432 enabled++;
3433 }
c936f44d 3434
4ed765f9
CW
3435 if (ironlake_compute_wm0(dev, 1, &plane_wm, &cursor_wm)) {
3436 I915_WRITE(WM0_PIPEB_ILK,
3437 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3438 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3439 " plane %d, cursor: %d\n",
3440 plane_wm, cursor_wm);
3441 enabled++;
7f8a8569
ZW
3442 }
3443
3444 /*
3445 * Calculate and update the self-refresh watermark only when one
3446 * display plane is used.
3447 */
4ed765f9 3448 tmp = 0;
f7746f0e 3449 if (enabled == 1) {
4ed765f9
CW
3450 unsigned long line_time_us;
3451 int small, large, plane_fbc;
3452 int sr_clock, entries;
3453 int line_count, line_size;
7f8a8569
ZW
3454 /* Read the self-refresh latency. The unit is 0.5us */
3455 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3456
3457 sr_clock = planea_clock ? planea_clock : planeb_clock;
4ed765f9 3458 line_time_us = (sr_htotal * 1000) / sr_clock;
7f8a8569
ZW
3459
3460 /* Use ns/us then divide to preserve precision */
3461 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
5eddb70b 3462 / 1000;
4ed765f9 3463 line_size = sr_hdisplay * pixel_size;
7f8a8569 3464
4ed765f9
CW
3465 /* Use the minimum of the small and large buffer method for primary */
3466 small = ((sr_clock * pixel_size / 1000) * (ilk_sr_latency * 500)) / 1000;
3467 large = line_count * line_size;
7f8a8569 3468
4ed765f9
CW
3469 entries = DIV_ROUND_UP(min(small, large),
3470 ironlake_display_srwm_info.cacheline_size);
7f8a8569 3471
4ed765f9
CW
3472 plane_fbc = entries * 64;
3473 plane_fbc = DIV_ROUND_UP(plane_fbc, line_size);
7f8a8569 3474
4ed765f9
CW
3475 plane_wm = entries + ironlake_display_srwm_info.guard_size;
3476 if (plane_wm > (int)ironlake_display_srwm_info.max_wm)
3477 plane_wm = ironlake_display_srwm_info.max_wm;
7f8a8569 3478
4ed765f9
CW
3479 /* calculate the self-refresh watermark for display cursor */
3480 entries = line_count * pixel_size * 64;
3481 entries = DIV_ROUND_UP(entries,
3482 ironlake_cursor_srwm_info.cacheline_size);
3483
3484 cursor_wm = entries + ironlake_cursor_srwm_info.guard_size;
3485 if (cursor_wm > (int)ironlake_cursor_srwm_info.max_wm)
3486 cursor_wm = ironlake_cursor_srwm_info.max_wm;
3487
3488 /* configure watermark and enable self-refresh */
3489 tmp = (WM1_LP_SR_EN |
3490 (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3491 (plane_fbc << WM1_LP_FBC_SHIFT) |
3492 (plane_wm << WM1_LP_SR_SHIFT) |
3493 cursor_wm);
3494 DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d,"
3495 " cursor %d\n", plane_wm, plane_fbc, cursor_wm);
7f8a8569 3496 }
4ed765f9
CW
3497 I915_WRITE(WM1_LP_ILK, tmp);
3498 /* XXX setup WM2 and WM3 */
7f8a8569 3499}
4ed765f9 3500
7662c8bd
SL
3501/**
3502 * intel_update_watermarks - update FIFO watermark values based on current modes
3503 *
3504 * Calculate watermark values for the various WM regs based on current mode
3505 * and plane configuration.
3506 *
3507 * There are several cases to deal with here:
3508 * - normal (i.e. non-self-refresh)
3509 * - self-refresh (SR) mode
3510 * - lines are large relative to FIFO size (buffer can hold up to 2)
3511 * - lines are small relative to FIFO size (buffer can hold more than 2
3512 * lines), so need to account for TLB latency
3513 *
3514 * The normal calculation is:
3515 * watermark = dotclock * bytes per pixel * latency
3516 * where latency is platform & configuration dependent (we assume pessimal
3517 * values here).
3518 *
3519 * The SR calculation is:
3520 * watermark = (trunc(latency/line time)+1) * surface width *
3521 * bytes per pixel
3522 * where
3523 * line time = htotal / dotclock
fa143215 3524 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL
3525 * and latency is assumed to be high, as above.
3526 *
3527 * The final value programmed to the register should always be rounded up,
3528 * and include an extra 2 entries to account for clock crossings.
3529 *
3530 * We don't use the sprite, so we can ignore that. And on Crestline we have
3531 * to set the non-SR watermarks to 8.
5eddb70b 3532 */
7662c8bd
SL
3533static void intel_update_watermarks(struct drm_device *dev)
3534{
e70236a8 3535 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 3536 struct drm_crtc *crtc;
7662c8bd
SL
3537 int sr_hdisplay = 0;
3538 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3539 int enabled = 0, pixel_size = 0;
fa143215 3540 int sr_htotal = 0;
7662c8bd 3541
c03342fa
ZW
3542 if (!dev_priv->display.update_wm)
3543 return;
3544
7662c8bd
SL
3545 /* Get the clock config from both planes */
3546 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
debcaddc 3547 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
f7abfe8b 3548 if (intel_crtc->active) {
7662c8bd
SL
3549 enabled++;
3550 if (intel_crtc->plane == 0) {
28c97730 3551 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
5eddb70b 3552 intel_crtc->pipe, crtc->mode.clock);
7662c8bd
SL
3553 planea_clock = crtc->mode.clock;
3554 } else {
28c97730 3555 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
5eddb70b 3556 intel_crtc->pipe, crtc->mode.clock);
7662c8bd
SL
3557 planeb_clock = crtc->mode.clock;
3558 }
3559 sr_hdisplay = crtc->mode.hdisplay;
3560 sr_clock = crtc->mode.clock;
fa143215 3561 sr_htotal = crtc->mode.htotal;
7662c8bd
SL
3562 if (crtc->fb)
3563 pixel_size = crtc->fb->bits_per_pixel / 8;
3564 else
3565 pixel_size = 4; /* by default */
3566 }
3567 }
3568
3569 if (enabled <= 0)
3570 return;
3571
e70236a8 3572 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
fa143215 3573 sr_hdisplay, sr_htotal, pixel_size);
7662c8bd
SL
3574}
3575
5c3b82e2
CW
3576static int intel_crtc_mode_set(struct drm_crtc *crtc,
3577 struct drm_display_mode *mode,
3578 struct drm_display_mode *adjusted_mode,
3579 int x, int y,
3580 struct drm_framebuffer *old_fb)
79e53945
JB
3581{
3582 struct drm_device *dev = crtc->dev;
3583 struct drm_i915_private *dev_priv = dev->dev_private;
3584 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3585 int pipe = intel_crtc->pipe;
80824003 3586 int plane = intel_crtc->plane;
5eddb70b 3587 u32 fp_reg, dpll_reg;
c751ce4f 3588 int refclk, num_connectors = 0;
652c393a 3589 intel_clock_t clock, reduced_clock;
5eddb70b 3590 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
652c393a 3591 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
a4fc5ed6 3592 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
8e647a27 3593 struct intel_encoder *has_edp_encoder = NULL;
79e53945 3594 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 3595 struct intel_encoder *encoder;
d4906093 3596 const intel_limit_t *limit;
5c3b82e2 3597 int ret;
2c07245f 3598 struct fdi_m_n m_n = {0};
5eddb70b 3599 u32 reg, temp;
5eb08b69 3600 int target_clock;
79e53945
JB
3601
3602 drm_vblank_pre_modeset(dev, pipe);
3603
5eddb70b
CW
3604 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3605 if (encoder->base.crtc != crtc)
79e53945
JB
3606 continue;
3607
5eddb70b 3608 switch (encoder->type) {
79e53945
JB
3609 case INTEL_OUTPUT_LVDS:
3610 is_lvds = true;
3611 break;
3612 case INTEL_OUTPUT_SDVO:
7d57382e 3613 case INTEL_OUTPUT_HDMI:
79e53945 3614 is_sdvo = true;
5eddb70b 3615 if (encoder->needs_tv_clock)
e2f0ba97 3616 is_tv = true;
79e53945
JB
3617 break;
3618 case INTEL_OUTPUT_DVO:
3619 is_dvo = true;
3620 break;
3621 case INTEL_OUTPUT_TVOUT:
3622 is_tv = true;
3623 break;
3624 case INTEL_OUTPUT_ANALOG:
3625 is_crt = true;
3626 break;
a4fc5ed6
KP
3627 case INTEL_OUTPUT_DISPLAYPORT:
3628 is_dp = true;
3629 break;
32f9d658 3630 case INTEL_OUTPUT_EDP:
5eddb70b 3631 has_edp_encoder = encoder;
32f9d658 3632 break;
79e53945 3633 }
43565a06 3634
c751ce4f 3635 num_connectors++;
79e53945
JB
3636 }
3637
c751ce4f 3638 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
43565a06 3639 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 3640 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 3641 refclk / 1000);
a6c45cf0 3642 } else if (!IS_GEN2(dev)) {
79e53945 3643 refclk = 96000;
1cb1b75e
JB
3644 if (HAS_PCH_SPLIT(dev) &&
3645 (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
2c07245f 3646 refclk = 120000; /* 120Mhz refclk */
79e53945
JB
3647 } else {
3648 refclk = 48000;
3649 }
3650
d4906093
ML
3651 /*
3652 * Returns a set of divisors for the desired target clock with the given
3653 * refclk, or FALSE. The returned values represent the clock equation:
3654 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3655 */
1b894b59 3656 limit = intel_limit(crtc, refclk);
d4906093 3657 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB
3658 if (!ok) {
3659 DRM_ERROR("Couldn't find PLL settings for mode!\n");
1f803ee5 3660 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 3661 return -EINVAL;
79e53945
JB
3662 }
3663
cda4b7d3 3664 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 3665 intel_crtc_update_cursor(crtc, true);
cda4b7d3 3666
ddc9003c
ZY
3667 if (is_lvds && dev_priv->lvds_downclock_avail) {
3668 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW
3669 dev_priv->lvds_downclock,
3670 refclk,
3671 &reduced_clock);
18f9ed12
ZY
3672 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3673 /*
3674 * If the different P is found, it means that we can't
3675 * switch the display clock by using the FP0/FP1.
3676 * In such case we will disable the LVDS downclock
3677 * feature.
3678 */
3679 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 3680 "LVDS clock/downclock\n");
18f9ed12
ZY
3681 has_reduced_clock = 0;
3682 }
652c393a 3683 }
7026d4ac
ZW
3684 /* SDVO TV has fixed PLL values depend on its clock range,
3685 this mirrors vbios setting. */
3686 if (is_sdvo && is_tv) {
3687 if (adjusted_mode->clock >= 100000
5eddb70b 3688 && adjusted_mode->clock < 140500) {
7026d4ac
ZW
3689 clock.p1 = 2;
3690 clock.p2 = 10;
3691 clock.n = 3;
3692 clock.m1 = 16;
3693 clock.m2 = 8;
3694 } else if (adjusted_mode->clock >= 140500
5eddb70b 3695 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW
3696 clock.p1 = 1;
3697 clock.p2 = 10;
3698 clock.n = 6;
3699 clock.m1 = 12;
3700 clock.m2 = 8;
3701 }
3702 }
3703
2c07245f 3704 /* FDI link */
bad720ff 3705 if (HAS_PCH_SPLIT(dev)) {
49078f7d 3706 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
77ffb597 3707 int lane = 0, link_bw, bpp;
5c5313c8 3708 /* CPU eDP doesn't require FDI link, so just set DP M/N
32f9d658 3709 according to current link config */
5c5313c8 3710 if (has_edp_encoder && !intel_encoder_is_pch_edp(&encoder->base)) {
5eb08b69 3711 target_clock = mode->clock;
8e647a27
CW
3712 intel_edp_link_config(has_edp_encoder,
3713 &lane, &link_bw);
32f9d658 3714 } else {
5c5313c8 3715 /* [e]DP over FDI requires target mode clock
32f9d658 3716 instead of link clock */
5c5313c8 3717 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
32f9d658
ZW
3718 target_clock = mode->clock;
3719 else
3720 target_clock = adjusted_mode->clock;
021357ac
CW
3721
3722 /* FDI is a binary signal running at ~2.7GHz, encoding
3723 * each output octet as 10 bits. The actual frequency
3724 * is stored as a divider into a 100MHz clock, and the
3725 * mode pixel clock is stored in units of 1KHz.
3726 * Hence the bw of each lane in terms of the mode signal
3727 * is:
3728 */
3729 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
32f9d658 3730 }
58a27471
ZW
3731
3732 /* determine panel color depth */
5eddb70b 3733 temp = I915_READ(PIPECONF(pipe));
e5a95eb7
ZY
3734 temp &= ~PIPE_BPC_MASK;
3735 if (is_lvds) {
e5a95eb7 3736 /* the BPC will be 6 if it is 18-bit LVDS panel */
5eddb70b 3737 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
e5a95eb7
ZY
3738 temp |= PIPE_8BPC;
3739 else
3740 temp |= PIPE_6BPC;
1d850362 3741 } else if (has_edp_encoder) {
5ceb0f9b 3742 switch (dev_priv->edp.bpp/3) {
885a5fb5
ZW
3743 case 8:
3744 temp |= PIPE_8BPC;
3745 break;
3746 case 10:
3747 temp |= PIPE_10BPC;
3748 break;
3749 case 6:
3750 temp |= PIPE_6BPC;
3751 break;
3752 case 12:
3753 temp |= PIPE_12BPC;
3754 break;
3755 }
e5a95eb7
ZY
3756 } else
3757 temp |= PIPE_8BPC;
5eddb70b 3758 I915_WRITE(PIPECONF(pipe), temp);
58a27471
ZW
3759
3760 switch (temp & PIPE_BPC_MASK) {
3761 case PIPE_8BPC:
3762 bpp = 24;
3763 break;
3764 case PIPE_10BPC:
3765 bpp = 30;
3766 break;
3767 case PIPE_6BPC:
3768 bpp = 18;
3769 break;
3770 case PIPE_12BPC:
3771 bpp = 36;
3772 break;
3773 default:
3774 DRM_ERROR("unknown pipe bpc value\n");
3775 bpp = 24;
3776 }
3777
77ffb597
AJ
3778 if (!lane) {
3779 /*
3780 * Account for spread spectrum to avoid
3781 * oversubscribing the link. Max center spread
3782 * is 2.5%; use 5% for safety's sake.
3783 */
3784 u32 bps = target_clock * bpp * 21 / 20;
3785 lane = bps / (link_bw * 8) + 1;
3786 }
3787
3788 intel_crtc->fdi_lanes = lane;
3789
49078f7d
CW
3790 if (pixel_multiplier > 1)
3791 link_bw *= pixel_multiplier;
f2b115e6 3792 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
5eb08b69 3793 }
2c07245f 3794
c038e51e
ZW
3795 /* Ironlake: try to setup display ref clock before DPLL
3796 * enabling. This is only under driver's control after
3797 * PCH B stepping, previous chipset stepping should be
3798 * ignoring this setting.
3799 */
bad720ff 3800 if (HAS_PCH_SPLIT(dev)) {
c038e51e
ZW
3801 temp = I915_READ(PCH_DREF_CONTROL);
3802 /* Always enable nonspread source */
3803 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3804 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
c038e51e
ZW
3805 temp &= ~DREF_SSC_SOURCE_MASK;
3806 temp |= DREF_SSC_SOURCE_ENABLE;
3807 I915_WRITE(PCH_DREF_CONTROL, temp);
c038e51e 3808
5eddb70b 3809 POSTING_READ(PCH_DREF_CONTROL);
c038e51e
ZW
3810 udelay(200);
3811
8e647a27 3812 if (has_edp_encoder) {
c038e51e
ZW
3813 if (dev_priv->lvds_use_ssc) {
3814 temp |= DREF_SSC1_ENABLE;
3815 I915_WRITE(PCH_DREF_CONTROL, temp);
c038e51e 3816
5eddb70b 3817 POSTING_READ(PCH_DREF_CONTROL);
c038e51e 3818 udelay(200);
7f823282
JB
3819 }
3820 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3821
3822 /* Enable CPU source on CPU attached eDP */
3823 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
3824 if (dev_priv->lvds_use_ssc)
3825 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3826 else
3827 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
c038e51e 3828 } else {
7f823282
JB
3829 /* Enable SSC on PCH eDP if needed */
3830 if (dev_priv->lvds_use_ssc) {
3831 DRM_ERROR("enabling SSC on PCH\n");
3832 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
3833 }
c038e51e 3834 }
5eddb70b 3835 I915_WRITE(PCH_DREF_CONTROL, temp);
7f823282
JB
3836 POSTING_READ(PCH_DREF_CONTROL);
3837 udelay(200);
c038e51e
ZW
3838 }
3839 }
3840
f2b115e6 3841 if (IS_PINEVIEW(dev)) {
2177832f 3842 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB
3843 if (has_reduced_clock)
3844 fp2 = (1 << reduced_clock.n) << 16 |
3845 reduced_clock.m1 << 8 | reduced_clock.m2;
3846 } else {
2177832f 3847 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB
3848 if (has_reduced_clock)
3849 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3850 reduced_clock.m2;
3851 }
79e53945 3852
c1858123
CW
3853 /* Enable autotuning of the PLL clock (if permissible) */
3854 if (HAS_PCH_SPLIT(dev)) {
3855 int factor = 21;
3856
3857 if (is_lvds) {
3858 if ((dev_priv->lvds_use_ssc &&
3859 dev_priv->lvds_ssc_freq == 100) ||
3860 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
3861 factor = 25;
3862 } else if (is_sdvo && is_tv)
3863 factor = 20;
3864
3865 if (clock.m1 < factor * clock.n)
3866 fp |= FP_CB_TUNE;
3867 }
3868
5eddb70b 3869 dpll = 0;
bad720ff 3870 if (!HAS_PCH_SPLIT(dev))
2c07245f
ZW
3871 dpll = DPLL_VGA_MODE_DIS;
3872
a6c45cf0 3873 if (!IS_GEN2(dev)) {
79e53945
JB
3874 if (is_lvds)
3875 dpll |= DPLLB_MODE_LVDS;
3876 else
3877 dpll |= DPLLB_MODE_DAC_SERIAL;
3878 if (is_sdvo) {
6c9547ff
CW
3879 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3880 if (pixel_multiplier > 1) {
3881 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3882 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3883 else if (HAS_PCH_SPLIT(dev))
3884 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3885 }
79e53945 3886 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 3887 }
83240120 3888 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
a4fc5ed6 3889 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945
JB
3890
3891 /* compute bitmask from p1 value */
f2b115e6
AJ
3892 if (IS_PINEVIEW(dev))
3893 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
2c07245f 3894 else {
2177832f 3895 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2c07245f 3896 /* also FPA1 */
bad720ff 3897 if (HAS_PCH_SPLIT(dev))
2c07245f 3898 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
652c393a
JB
3899 if (IS_G4X(dev) && has_reduced_clock)
3900 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2c07245f 3901 }
79e53945
JB
3902 switch (clock.p2) {
3903 case 5:
3904 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3905 break;
3906 case 7:
3907 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3908 break;
3909 case 10:
3910 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3911 break;
3912 case 14:
3913 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3914 break;
3915 }
a6c45cf0 3916 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
79e53945
JB
3917 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3918 } else {
3919 if (is_lvds) {
3920 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3921 } else {
3922 if (clock.p1 == 2)
3923 dpll |= PLL_P1_DIVIDE_BY_TWO;
3924 else
3925 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3926 if (clock.p2 == 4)
3927 dpll |= PLL_P2_DIVIDE_BY_4;
3928 }
3929 }
3930
43565a06
KH
3931 if (is_sdvo && is_tv)
3932 dpll |= PLL_REF_INPUT_TVCLKINBC;
3933 else if (is_tv)
79e53945 3934 /* XXX: just matching BIOS for now */
43565a06 3935 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 3936 dpll |= 3;
c751ce4f 3937 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
43565a06 3938 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB
3939 else
3940 dpll |= PLL_REF_INPUT_DREFCLK;
3941
3942 /* setup pipeconf */
5eddb70b 3943 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB
3944
3945 /* Set up the display plane register */
3946 dspcntr = DISPPLANE_GAMMA_ENABLE;
3947
f2b115e6 3948 /* Ironlake's plane is forced to pipe, bit 24 is to
2c07245f 3949 enable color space conversion */
bad720ff 3950 if (!HAS_PCH_SPLIT(dev)) {
2c07245f 3951 if (pipe == 0)
80824003 3952 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
2c07245f
ZW
3953 else
3954 dspcntr |= DISPPLANE_SEL_PIPE_B;
3955 }
79e53945 3956
a6c45cf0 3957 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB
3958 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3959 * core speed.
3960 *
3961 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3962 * pipe == 0 check?
3963 */
e70236a8
JB
3964 if (mode->clock >
3965 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 3966 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 3967 else
5eddb70b 3968 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB
3969 }
3970
8d86dc6a 3971 dspcntr |= DISPLAY_PLANE_ENABLE;
5eddb70b 3972 pipeconf |= PIPECONF_ENABLE;
8d86dc6a
LT
3973 dpll |= DPLL_VCO_ENABLE;
3974
28c97730 3975 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB
3976 drm_mode_debug_printmodeline(mode);
3977
f2b115e6 3978 /* assign to Ironlake registers */
bad720ff 3979 if (HAS_PCH_SPLIT(dev)) {
5eddb70b
CW
3980 fp_reg = PCH_FP0(pipe);
3981 dpll_reg = PCH_DPLL(pipe);
3982 } else {
3983 fp_reg = FP0(pipe);
3984 dpll_reg = DPLL(pipe);
2c07245f 3985 }
79e53945 3986
5c5313c8
JB
3987 /* PCH eDP needs FDI, but CPU eDP does not */
3988 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
79e53945
JB
3989 I915_WRITE(fp_reg, fp);
3990 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
5eddb70b
CW
3991
3992 POSTING_READ(dpll_reg);
79e53945
JB
3993 udelay(150);
3994 }
3995
8db9d77b
ZW
3996 /* enable transcoder DPLL */
3997 if (HAS_PCH_CPT(dev)) {
3998 temp = I915_READ(PCH_DPLL_SEL);
5eddb70b
CW
3999 if (pipe == 0)
4000 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
8db9d77b 4001 else
5eddb70b 4002 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
8db9d77b 4003 I915_WRITE(PCH_DPLL_SEL, temp);
5eddb70b
CW
4004
4005 POSTING_READ(PCH_DPLL_SEL);
8db9d77b
ZW
4006 udelay(150);
4007 }
4008
79e53945
JB
4009 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4010 * This is an exception to the general rule that mode_set doesn't turn
4011 * things on.
4012 */
4013 if (is_lvds) {
5eddb70b 4014 reg = LVDS;
bad720ff 4015 if (HAS_PCH_SPLIT(dev))
5eddb70b 4016 reg = PCH_LVDS;
541998a1 4017
5eddb70b
CW
4018 temp = I915_READ(reg);
4019 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3
ZW
4020 if (pipe == 1) {
4021 if (HAS_PCH_CPT(dev))
5eddb70b 4022 temp |= PORT_TRANS_B_SEL_CPT;
b3b095b3 4023 else
5eddb70b 4024 temp |= LVDS_PIPEB_SELECT;
b3b095b3
ZW
4025 } else {
4026 if (HAS_PCH_CPT(dev))
5eddb70b 4027 temp &= ~PORT_TRANS_SEL_MASK;
b3b095b3 4028 else
5eddb70b 4029 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 4030 }
a3e17eb8 4031 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4032 temp |= dev_priv->lvds_border_bits;
79e53945
JB
4033 /* Set the B0-B3 data pairs corresponding to whether we're going to
4034 * set the DPLLs for dual-channel mode or not.
4035 */
4036 if (clock.p2 == 7)
5eddb70b 4037 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4038 else
5eddb70b 4039 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB
4040
4041 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4042 * appropriately here, but we need to look more thoroughly into how
4043 * panels behave in the two modes.
4044 */
434ed097 4045 /* set the dithering flag on non-PCH LVDS as needed */
a6c45cf0 4046 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
434ed097 4047 if (dev_priv->lvds_dither)
5eddb70b 4048 temp |= LVDS_ENABLE_DITHER;
434ed097 4049 else
5eddb70b 4050 temp &= ~LVDS_ENABLE_DITHER;
898822ce 4051 }
5eddb70b 4052 I915_WRITE(reg, temp);
79e53945 4053 }
434ed097
JB
4054
4055 /* set the dithering flag and clear for anything other than a panel. */
4056 if (HAS_PCH_SPLIT(dev)) {
4057 pipeconf &= ~PIPECONF_DITHER_EN;
4058 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4059 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
4060 pipeconf |= PIPECONF_DITHER_EN;
4061 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
4062 }
4063 }
4064
5c5313c8 4065 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
a4fc5ed6 4066 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5c5313c8 4067 } else if (HAS_PCH_SPLIT(dev)) {
8db9d77b
ZW
4068 /* For non-DP output, clear any trans DP clock recovery setting.*/
4069 if (pipe == 0) {
4070 I915_WRITE(TRANSA_DATA_M1, 0);
4071 I915_WRITE(TRANSA_DATA_N1, 0);
4072 I915_WRITE(TRANSA_DP_LINK_M1, 0);
4073 I915_WRITE(TRANSA_DP_LINK_N1, 0);
4074 } else {
4075 I915_WRITE(TRANSB_DATA_M1, 0);
4076 I915_WRITE(TRANSB_DATA_N1, 0);
4077 I915_WRITE(TRANSB_DP_LINK_M1, 0);
4078 I915_WRITE(TRANSB_DP_LINK_N1, 0);
4079 }
4080 }
79e53945 4081
5c5313c8 4082 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
79e53945 4083 I915_WRITE(dpll_reg, dpll);
5eddb70b 4084
32f9d658 4085 /* Wait for the clocks to stabilize. */
5eddb70b 4086 POSTING_READ(dpll_reg);
32f9d658
ZW
4087 udelay(150);
4088
a6c45cf0 4089 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
5eddb70b 4090 temp = 0;
bb66c512 4091 if (is_sdvo) {
5eddb70b
CW
4092 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4093 if (temp > 1)
4094 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6c9547ff 4095 else
5eddb70b
CW
4096 temp = 0;
4097 }
4098 I915_WRITE(DPLL_MD(pipe), temp);
32f9d658 4099 } else {
a589b9f4
CW
4100 /* The pixel multiplier can only be updated once the
4101 * DPLL is enabled and the clocks are stable.
4102 *
4103 * So write it again.
4104 */
32f9d658
ZW
4105 I915_WRITE(dpll_reg, dpll);
4106 }
79e53945 4107 }
79e53945 4108
5eddb70b 4109 intel_crtc->lowfreq_avail = false;
652c393a
JB
4110 if (is_lvds && has_reduced_clock && i915_powersave) {
4111 I915_WRITE(fp_reg + 4, fp2);
4112 intel_crtc->lowfreq_avail = true;
4113 if (HAS_PIPE_CXSR(dev)) {
28c97730 4114 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB
4115 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4116 }
4117 } else {
4118 I915_WRITE(fp_reg + 4, fp);
652c393a 4119 if (HAS_PIPE_CXSR(dev)) {
28c97730 4120 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB
4121 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4122 }
4123 }
4124
734b4157
KH
4125 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4126 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4127 /* the chip adds 2 halflines automatically */
4128 adjusted_mode->crtc_vdisplay -= 1;
4129 adjusted_mode->crtc_vtotal -= 1;
4130 adjusted_mode->crtc_vblank_start -= 1;
4131 adjusted_mode->crtc_vblank_end -= 1;
4132 adjusted_mode->crtc_vsync_end -= 1;
4133 adjusted_mode->crtc_vsync_start -= 1;
4134 } else
4135 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4136
5eddb70b
CW
4137 I915_WRITE(HTOTAL(pipe),
4138 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4139 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW
4140 I915_WRITE(HBLANK(pipe),
4141 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4142 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW
4143 I915_WRITE(HSYNC(pipe),
4144 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4145 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW
4146
4147 I915_WRITE(VTOTAL(pipe),
4148 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4149 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW
4150 I915_WRITE(VBLANK(pipe),
4151 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4152 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW
4153 I915_WRITE(VSYNC(pipe),
4154 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4155 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW
4156
4157 /* pipesrc and dspsize control the size that is scaled from,
4158 * which should always be the user's requested size.
79e53945 4159 */
bad720ff 4160 if (!HAS_PCH_SPLIT(dev)) {
5eddb70b
CW
4161 I915_WRITE(DSPSIZE(plane),
4162 ((mode->vdisplay - 1) << 16) |
4163 (mode->hdisplay - 1));
4164 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4165 }
5eddb70b
CW
4166 I915_WRITE(PIPESRC(pipe),
4167 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4168
bad720ff 4169 if (HAS_PCH_SPLIT(dev)) {
5eddb70b
CW
4170 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4171 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4172 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4173 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 4174
5c5313c8 4175 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
f2b115e6 4176 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
32f9d658 4177 }
2c07245f
ZW
4178 }
4179
5eddb70b
CW
4180 I915_WRITE(PIPECONF(pipe), pipeconf);
4181 POSTING_READ(PIPECONF(pipe));
79e53945 4182
9d0498a2 4183 intel_wait_for_vblank(dev, pipe);
79e53945 4184
f00a3ddf 4185 if (IS_GEN5(dev)) {
553bd149
ZW
4186 /* enable address swizzle for tiling buffer */
4187 temp = I915_READ(DISP_ARB_CTL);
4188 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4189 }
4190
5eddb70b 4191 I915_WRITE(DSPCNTR(plane), dspcntr);
79e53945 4192
5c3b82e2 4193 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL
4194
4195 intel_update_watermarks(dev);
4196
79e53945 4197 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 4198
1f803ee5 4199 return ret;
79e53945
JB
4200}
4201
4202/** Loads the palette/gamma unit for the CRTC with the prepared values */
4203void intel_crtc_load_lut(struct drm_crtc *crtc)
4204{
4205 struct drm_device *dev = crtc->dev;
4206 struct drm_i915_private *dev_priv = dev->dev_private;
4207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4208 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4209 int i;
4210
4211 /* The clocks have to be on to load the palette. */
4212 if (!crtc->enabled)
4213 return;
4214
f2b115e6 4215 /* use legacy palette for Ironlake */
bad720ff 4216 if (HAS_PCH_SPLIT(dev))
2c07245f
ZW
4217 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4218 LGC_PALETTE_B;
4219
79e53945
JB
4220 for (i = 0; i < 256; i++) {
4221 I915_WRITE(palreg + 4 * i,
4222 (intel_crtc->lut_r[i] << 16) |
4223 (intel_crtc->lut_g[i] << 8) |
4224 intel_crtc->lut_b[i]);
4225 }
4226}
4227
560b85bb
CW
4228static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4229{
4230 struct drm_device *dev = crtc->dev;
4231 struct drm_i915_private *dev_priv = dev->dev_private;
4232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4233 bool visible = base != 0;
4234 u32 cntl;
4235
4236 if (intel_crtc->cursor_visible == visible)
4237 return;
4238
4239 cntl = I915_READ(CURACNTR);
4240 if (visible) {
4241 /* On these chipsets we can only modify the base whilst
4242 * the cursor is disabled.
4243 */
4244 I915_WRITE(CURABASE, base);
4245
4246 cntl &= ~(CURSOR_FORMAT_MASK);
4247 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4248 cntl |= CURSOR_ENABLE |
4249 CURSOR_GAMMA_ENABLE |
4250 CURSOR_FORMAT_ARGB;
4251 } else
4252 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4253 I915_WRITE(CURACNTR, cntl);
4254
4255 intel_crtc->cursor_visible = visible;
4256}
4257
4258static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4259{
4260 struct drm_device *dev = crtc->dev;
4261 struct drm_i915_private *dev_priv = dev->dev_private;
4262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4263 int pipe = intel_crtc->pipe;
4264 bool visible = base != 0;
4265
4266 if (intel_crtc->cursor_visible != visible) {
4267 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4268 if (base) {
4269 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4270 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4271 cntl |= pipe << 28; /* Connect to correct pipe */
4272 } else {
4273 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4274 cntl |= CURSOR_MODE_DISABLE;
4275 }
4276 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4277
4278 intel_crtc->cursor_visible = visible;
4279 }
4280 /* and commit changes on next vblank */
4281 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4282}
4283
cda4b7d3 4284/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW
4285static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4286 bool on)
cda4b7d3
CW
4287{
4288 struct drm_device *dev = crtc->dev;
4289 struct drm_i915_private *dev_priv = dev->dev_private;
4290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4291 int pipe = intel_crtc->pipe;
4292 int x = intel_crtc->cursor_x;
4293 int y = intel_crtc->cursor_y;
560b85bb 4294 u32 base, pos;
cda4b7d3
CW
4295 bool visible;
4296
4297 pos = 0;
4298
6b383a7f 4299 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW
4300 base = intel_crtc->cursor_addr;
4301 if (x > (int) crtc->fb->width)
4302 base = 0;
4303
4304 if (y > (int) crtc->fb->height)
4305 base = 0;
4306 } else
4307 base = 0;
4308
4309 if (x < 0) {
4310 if (x + intel_crtc->cursor_width < 0)
4311 base = 0;
4312
4313 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4314 x = -x;
4315 }
4316 pos |= x << CURSOR_X_SHIFT;
4317
4318 if (y < 0) {
4319 if (y + intel_crtc->cursor_height < 0)
4320 base = 0;
4321
4322 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4323 y = -y;
4324 }
4325 pos |= y << CURSOR_Y_SHIFT;
4326
4327 visible = base != 0;
560b85bb 4328 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW
4329 return;
4330
4331 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
560b85bb
CW
4332 if (IS_845G(dev) || IS_I865G(dev))
4333 i845_update_cursor(crtc, base);
4334 else
4335 i9xx_update_cursor(crtc, base);
cda4b7d3
CW
4336
4337 if (visible)
4338 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4339}
4340
79e53945 4341static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 4342 struct drm_file *file,
79e53945
JB
4343 uint32_t handle,
4344 uint32_t width, uint32_t height)
4345{
4346 struct drm_device *dev = crtc->dev;
4347 struct drm_i915_private *dev_priv = dev->dev_private;
4348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 4349 struct drm_i915_gem_object *obj;
cda4b7d3 4350 uint32_t addr;
3f8bc370 4351 int ret;
79e53945 4352
28c97730 4353 DRM_DEBUG_KMS("\n");
79e53945
JB
4354
4355 /* if we want to turn off the cursor ignore width and height */
4356 if (!handle) {
28c97730 4357 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 4358 addr = 0;
05394f39 4359 obj = NULL;
5004417d 4360 mutex_lock(&dev->struct_mutex);
3f8bc370 4361 goto finish;
79e53945
JB
4362 }
4363
4364 /* Currently we only support 64x64 cursors */
4365 if (width != 64 || height != 64) {
4366 DRM_ERROR("we currently only support 64x64 cursors\n");
4367 return -EINVAL;
4368 }
4369
05394f39
CW
4370 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
4371 if (!obj)
79e53945
JB
4372 return -ENOENT;
4373
05394f39 4374 if (obj->base.size < width * height * 4) {
79e53945 4375 DRM_ERROR("buffer is to small\n");
34b8686e
DA
4376 ret = -ENOMEM;
4377 goto fail;
79e53945
JB
4378 }
4379
71acb5eb 4380 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 4381 mutex_lock(&dev->struct_mutex);
b295d1b6 4382 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW
4383 if (obj->tiling_mode) {
4384 DRM_ERROR("cursor cannot be tiled\n");
4385 ret = -EINVAL;
4386 goto fail_locked;
4387 }
4388
05394f39 4389 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
71acb5eb
DA
4390 if (ret) {
4391 DRM_ERROR("failed to pin cursor bo\n");
7f9872e0 4392 goto fail_locked;
71acb5eb 4393 }
e7b526bb 4394
05394f39 4395 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
e7b526bb
CW
4396 if (ret) {
4397 DRM_ERROR("failed to move cursor bo into the GTT\n");
4398 goto fail_unpin;
4399 }
4400
d9e86c0e
CW
4401 ret = i915_gem_object_put_fence(obj);
4402 if (ret) {
4403 DRM_ERROR("failed to move cursor bo into the GTT\n");
4404 goto fail_unpin;
4405 }
4406
05394f39 4407 addr = obj->gtt_offset;
71acb5eb 4408 } else {
6eeefaf3 4409 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 4410 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW
4411 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4412 align);
71acb5eb
DA
4413 if (ret) {
4414 DRM_ERROR("failed to attach phys object\n");
7f9872e0 4415 goto fail_locked;
71acb5eb 4416 }
05394f39 4417 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH
4418 }
4419
a6c45cf0 4420 if (IS_GEN2(dev))
14b60391
JB
4421 I915_WRITE(CURSIZE, (height << 12) | width);
4422
3f8bc370 4423 finish:
3f8bc370 4424 if (intel_crtc->cursor_bo) {
b295d1b6 4425 if (dev_priv->info->cursor_needs_physical) {
05394f39 4426 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA
4427 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4428 } else
4429 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 4430 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 4431 }
80824003 4432
7f9872e0 4433 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH
4434
4435 intel_crtc->cursor_addr = addr;
05394f39 4436 intel_crtc->cursor_bo = obj;
cda4b7d3
CW
4437 intel_crtc->cursor_width = width;
4438 intel_crtc->cursor_height = height;
4439
6b383a7f 4440 intel_crtc_update_cursor(crtc, true);
3f8bc370 4441
79e53945 4442 return 0;
e7b526bb 4443fail_unpin:
05394f39 4444 i915_gem_object_unpin(obj);
7f9872e0 4445fail_locked:
34b8686e 4446 mutex_unlock(&dev->struct_mutex);
bc9025bd 4447fail:
05394f39 4448 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 4449 return ret;
79e53945
JB
4450}
4451
4452static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4453{
79e53945 4454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 4455
cda4b7d3
CW
4456 intel_crtc->cursor_x = x;
4457 intel_crtc->cursor_y = y;
652c393a 4458
6b383a7f 4459 intel_crtc_update_cursor(crtc, true);
79e53945
JB
4460
4461 return 0;
4462}
4463
4464/** Sets the color ramps on behalf of RandR */
4465void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4466 u16 blue, int regno)
4467{
4468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4469
4470 intel_crtc->lut_r[regno] = red >> 8;
4471 intel_crtc->lut_g[regno] = green >> 8;
4472 intel_crtc->lut_b[regno] = blue >> 8;
4473}
4474
b8c00ac5
DA
4475void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4476 u16 *blue, int regno)
4477{
4478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4479
4480 *red = intel_crtc->lut_r[regno] << 8;
4481 *green = intel_crtc->lut_g[regno] << 8;
4482 *blue = intel_crtc->lut_b[regno] << 8;
4483}
4484
79e53945 4485static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 4486 u16 *blue, uint32_t start, uint32_t size)
79e53945 4487{
7203425a 4488 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 4489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 4490
7203425a 4491 for (i = start; i < end; i++) {
79e53945
JB
4492 intel_crtc->lut_r[i] = red[i] >> 8;
4493 intel_crtc->lut_g[i] = green[i] >> 8;
4494 intel_crtc->lut_b[i] = blue[i] >> 8;
4495 }
4496
4497 intel_crtc_load_lut(crtc);
4498}
4499
4500/**
4501 * Get a pipe with a simple mode set on it for doing load-based monitor
4502 * detection.
4503 *
4504 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 4505 * its requirements. The pipe will be connected to no other encoders.
79e53945 4506 *
c751ce4f 4507 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB
4508 * configured for it. In the future, it could choose to temporarily disable
4509 * some outputs to free up a pipe for its use.
4510 *
4511 * \return crtc, or NULL if no pipes are available.
4512 */
4513
4514/* VESA 640x480x72Hz mode to set on the pipe */
4515static struct drm_display_mode load_detect_mode = {
4516 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4517 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4518};
4519
21d40d37 4520struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
c1c43977 4521 struct drm_connector *connector,
79e53945
JB
4522 struct drm_display_mode *mode,
4523 int *dpms_mode)
4524{
4525 struct intel_crtc *intel_crtc;
4526 struct drm_crtc *possible_crtc;
4527 struct drm_crtc *supported_crtc =NULL;
4ef69c7a 4528 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB
4529 struct drm_crtc *crtc = NULL;
4530 struct drm_device *dev = encoder->dev;
4531 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4532 struct drm_crtc_helper_funcs *crtc_funcs;
4533 int i = -1;
4534
4535 /*
4536 * Algorithm gets a little messy:
4537 * - if the connector already has an assigned crtc, use it (but make
4538 * sure it's on first)
4539 * - try to find the first unused crtc that can drive this connector,
4540 * and use that if we find one
4541 * - if there are no unused crtcs available, try to use the first
4542 * one we found that supports the connector
4543 */
4544
4545 /* See if we already have a CRTC for this connector */
4546 if (encoder->crtc) {
4547 crtc = encoder->crtc;
4548 /* Make sure the crtc and connector are running */
4549 intel_crtc = to_intel_crtc(crtc);
4550 *dpms_mode = intel_crtc->dpms_mode;
4551 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4552 crtc_funcs = crtc->helper_private;
4553 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4554 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4555 }
4556 return crtc;
4557 }
4558
4559 /* Find an unused one (if possible) */
4560 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4561 i++;
4562 if (!(encoder->possible_crtcs & (1 << i)))
4563 continue;
4564 if (!possible_crtc->enabled) {
4565 crtc = possible_crtc;
4566 break;
4567 }
4568 if (!supported_crtc)
4569 supported_crtc = possible_crtc;
4570 }
4571
4572 /*
4573 * If we didn't find an unused CRTC, don't use any.
4574 */
4575 if (!crtc) {
4576 return NULL;
4577 }
4578
4579 encoder->crtc = crtc;
c1c43977 4580 connector->encoder = encoder;
21d40d37 4581 intel_encoder->load_detect_temp = true;
79e53945
JB
4582
4583 intel_crtc = to_intel_crtc(crtc);
4584 *dpms_mode = intel_crtc->dpms_mode;
4585
4586 if (!crtc->enabled) {
4587 if (!mode)
4588 mode = &load_detect_mode;
3c4fdcfb 4589 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
79e53945
JB
4590 } else {
4591 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4592 crtc_funcs = crtc->helper_private;
4593 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4594 }
4595
4596 /* Add this connector to the crtc */
4597 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4598 encoder_funcs->commit(encoder);
4599 }
4600 /* let the connector get through one full cycle before testing */
9d0498a2 4601 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945
JB
4602
4603 return crtc;
4604}
4605
c1c43977
ZW
4606void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4607 struct drm_connector *connector, int dpms_mode)
79e53945 4608{
4ef69c7a 4609 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB
4610 struct drm_device *dev = encoder->dev;
4611 struct drm_crtc *crtc = encoder->crtc;
4612 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4613 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4614
21d40d37 4615 if (intel_encoder->load_detect_temp) {
79e53945 4616 encoder->crtc = NULL;
c1c43977 4617 connector->encoder = NULL;
21d40d37 4618 intel_encoder->load_detect_temp = false;
79e53945
JB
4619 crtc->enabled = drm_helper_crtc_in_use(crtc);
4620 drm_helper_disable_unused_functions(dev);
4621 }
4622
c751ce4f 4623 /* Switch crtc and encoder back off if necessary */
79e53945
JB
4624 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4625 if (encoder->crtc == crtc)
4626 encoder_funcs->dpms(encoder, dpms_mode);
4627 crtc_funcs->dpms(crtc, dpms_mode);
4628 }
4629}
4630
4631/* Returns the clock of the currently programmed mode of the given pipe. */
4632static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4633{
4634 struct drm_i915_private *dev_priv = dev->dev_private;
4635 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4636 int pipe = intel_crtc->pipe;
4637 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4638 u32 fp;
4639 intel_clock_t clock;
4640
4641 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4642 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4643 else
4644 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4645
4646 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ
4647 if (IS_PINEVIEW(dev)) {
4648 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4649 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL
4650 } else {
4651 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4652 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4653 }
4654
a6c45cf0 4655 if (!IS_GEN2(dev)) {
f2b115e6
AJ
4656 if (IS_PINEVIEW(dev))
4657 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4658 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL
4659 else
4660 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB
4661 DPLL_FPA01_P1_POST_DIV_SHIFT);
4662
4663 switch (dpll & DPLL_MODE_MASK) {
4664 case DPLLB_MODE_DAC_SERIAL:
4665 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4666 5 : 10;
4667 break;
4668 case DPLLB_MODE_LVDS:
4669 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4670 7 : 14;
4671 break;
4672 default:
28c97730 4673 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB
4674 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4675 return 0;
4676 }
4677
4678 /* XXX: Handle the 100Mhz refclk */
2177832f 4679 intel_clock(dev, 96000, &clock);
79e53945
JB
4680 } else {
4681 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4682
4683 if (is_lvds) {
4684 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4685 DPLL_FPA01_P1_POST_DIV_SHIFT);
4686 clock.p2 = 14;
4687
4688 if ((dpll & PLL_REF_INPUT_MASK) ==
4689 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4690 /* XXX: might not be 66MHz */
2177832f 4691 intel_clock(dev, 66000, &clock);
79e53945 4692 } else
2177832f 4693 intel_clock(dev, 48000, &clock);
79e53945
JB
4694 } else {
4695 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4696 clock.p1 = 2;
4697 else {
4698 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4699 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4700 }
4701 if (dpll & PLL_P2_DIVIDE_BY_4)
4702 clock.p2 = 4;
4703 else
4704 clock.p2 = 2;
4705
2177832f 4706 intel_clock(dev, 48000, &clock);
79e53945
JB
4707 }
4708 }
4709
4710 /* XXX: It would be nice to validate the clocks, but we can't reuse
4711 * i830PllIsValid() because it relies on the xf86_config connector
4712 * configuration being accurate, which it isn't necessarily.
4713 */
4714
4715 return clock.dot;
4716}
4717
4718/** Returns the currently programmed mode of the given pipe. */
4719struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4720 struct drm_crtc *crtc)
4721{
4722 struct drm_i915_private *dev_priv = dev->dev_private;
4723 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4724 int pipe = intel_crtc->pipe;
4725 struct drm_display_mode *mode;
4726 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4727 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4728 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4729 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4730
4731 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4732 if (!mode)
4733 return NULL;
4734
4735 mode->clock = intel_crtc_clock_get(dev, crtc);
4736 mode->hdisplay = (htot & 0xffff) + 1;
4737 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4738 mode->hsync_start = (hsync & 0xffff) + 1;
4739 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4740 mode->vdisplay = (vtot & 0xffff) + 1;
4741 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4742 mode->vsync_start = (vsync & 0xffff) + 1;
4743 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4744
4745 drm_mode_set_name(mode);
4746 drm_mode_set_crtcinfo(mode, 0);
4747
4748 return mode;
4749}
4750
652c393a
JB
4751#define GPU_IDLE_TIMEOUT 500 /* ms */
4752
4753/* When this timer fires, we've been idle for awhile */
4754static void intel_gpu_idle_timer(unsigned long arg)
4755{
4756 struct drm_device *dev = (struct drm_device *)arg;
4757 drm_i915_private_t *dev_priv = dev->dev_private;
4758
ff7ea4c0
CW
4759 if (!list_empty(&dev_priv->mm.active_list)) {
4760 /* Still processing requests, so just re-arm the timer. */
4761 mod_timer(&dev_priv->idle_timer, jiffies +
4762 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4763 return;
4764 }
652c393a 4765
ff7ea4c0 4766 dev_priv->busy = false;
01dfba93 4767 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB
4768}
4769
652c393a
JB
4770#define CRTC_IDLE_TIMEOUT 1000 /* ms */
4771
4772static void intel_crtc_idle_timer(unsigned long arg)
4773{
4774 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4775 struct drm_crtc *crtc = &intel_crtc->base;
4776 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 4777 struct intel_framebuffer *intel_fb;
652c393a 4778
ff7ea4c0
CW
4779 intel_fb = to_intel_framebuffer(crtc->fb);
4780 if (intel_fb && intel_fb->obj->active) {
4781 /* The framebuffer is still being accessed by the GPU. */
4782 mod_timer(&intel_crtc->idle_timer, jiffies +
4783 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4784 return;
4785 }
652c393a 4786
ff7ea4c0 4787 intel_crtc->busy = false;
01dfba93 4788 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB
4789}
4790
3dec0095 4791static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB
4792{
4793 struct drm_device *dev = crtc->dev;
4794 drm_i915_private_t *dev_priv = dev->dev_private;
4795 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4796 int pipe = intel_crtc->pipe;
4797 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4798 int dpll = I915_READ(dpll_reg);
4799
bad720ff 4800 if (HAS_PCH_SPLIT(dev))
652c393a
JB
4801 return;
4802
4803 if (!dev_priv->lvds_downclock_avail)
4804 return;
4805
4806 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 4807 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a
JB
4808
4809 /* Unlock panel regs */
4a655f04
JB
4810 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4811 PANEL_UNLOCK_REGS);
652c393a
JB
4812
4813 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4814 I915_WRITE(dpll_reg, dpll);
4815 dpll = I915_READ(dpll_reg);
9d0498a2 4816 intel_wait_for_vblank(dev, pipe);
652c393a
JB
4817 dpll = I915_READ(dpll_reg);
4818 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 4819 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB
4820
4821 /* ...and lock them again */
4822 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4823 }
4824
4825 /* Schedule downclock */
3dec0095
DV
4826 mod_timer(&intel_crtc->idle_timer, jiffies +
4827 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB
4828}
4829
4830static void intel_decrease_pllclock(struct drm_crtc *crtc)
4831{
4832 struct drm_device *dev = crtc->dev;
4833 drm_i915_private_t *dev_priv = dev->dev_private;
4834 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4835 int pipe = intel_crtc->pipe;
4836 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4837 int dpll = I915_READ(dpll_reg);
4838
bad720ff 4839 if (HAS_PCH_SPLIT(dev))
652c393a
JB
4840 return;
4841
4842 if (!dev_priv->lvds_downclock_avail)
4843 return;
4844
4845 /*
4846 * Since this is called by a timer, we should never get here in
4847 * the manual case.
4848 */
4849 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 4850 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a
JB
4851
4852 /* Unlock panel regs */
4a655f04
JB
4853 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4854 PANEL_UNLOCK_REGS);
652c393a
JB
4855
4856 dpll |= DISPLAY_RATE_SELECT_FPA1;
4857 I915_WRITE(dpll_reg, dpll);
4858 dpll = I915_READ(dpll_reg);
9d0498a2 4859 intel_wait_for_vblank(dev, pipe);
652c393a
JB
4860 dpll = I915_READ(dpll_reg);
4861 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 4862 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB
4863
4864 /* ...and lock them again */
4865 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4866 }
4867
4868}
4869
4870/**
4871 * intel_idle_update - adjust clocks for idleness
4872 * @work: work struct
4873 *
4874 * Either the GPU or display (or both) went idle. Check the busy status
4875 * here and adjust the CRTC and GPU clocks as necessary.
4876 */
4877static void intel_idle_update(struct work_struct *work)
4878{
4879 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4880 idle_work);
4881 struct drm_device *dev = dev_priv->dev;
4882 struct drm_crtc *crtc;
4883 struct intel_crtc *intel_crtc;
45ac22c8 4884 int enabled = 0;
652c393a
JB
4885
4886 if (!i915_powersave)
4887 return;
4888
4889 mutex_lock(&dev->struct_mutex);
4890
7648fa99
JB
4891 i915_update_gfx_val(dev_priv);
4892
652c393a
JB
4893 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4894 /* Skip inactive CRTCs */
4895 if (!crtc->fb)
4896 continue;
4897
45ac22c8 4898 enabled++;
652c393a
JB
4899 intel_crtc = to_intel_crtc(crtc);
4900 if (!intel_crtc->busy)
4901 intel_decrease_pllclock(crtc);
4902 }
4903
45ac22c8
LP
4904 if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4905 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4906 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4907 }
4908
652c393a
JB
4909 mutex_unlock(&dev->struct_mutex);
4910}
4911
4912/**
4913 * intel_mark_busy - mark the GPU and possibly the display busy
4914 * @dev: drm device
4915 * @obj: object we're operating on
4916 *
4917 * Callers can use this function to indicate that the GPU is busy processing
4918 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4919 * buffer), we'll also mark the display as busy, so we know to increase its
4920 * clock frequency.
4921 */
05394f39 4922void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB
4923{
4924 drm_i915_private_t *dev_priv = dev->dev_private;
4925 struct drm_crtc *crtc = NULL;
4926 struct intel_framebuffer *intel_fb;
4927 struct intel_crtc *intel_crtc;
4928
5e17ee74
ZW
4929 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4930 return;
4931
060e645a
LP
4932 if (!dev_priv->busy) {
4933 if (IS_I945G(dev) || IS_I945GM(dev)) {
4934 u32 fw_blc_self;
ee980b80 4935
060e645a
LP
4936 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4937 fw_blc_self = I915_READ(FW_BLC_SELF);
4938 fw_blc_self &= ~FW_BLC_SELF_EN;
4939 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4940 }
28cf798f 4941 dev_priv->busy = true;
060e645a 4942 } else
28cf798f
CW
4943 mod_timer(&dev_priv->idle_timer, jiffies +
4944 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB
4945
4946 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4947 if (!crtc->fb)
4948 continue;
4949
4950 intel_crtc = to_intel_crtc(crtc);
4951 intel_fb = to_intel_framebuffer(crtc->fb);
4952 if (intel_fb->obj == obj) {
4953 if (!intel_crtc->busy) {
060e645a
LP
4954 if (IS_I945G(dev) || IS_I945GM(dev)) {
4955 u32 fw_blc_self;
4956
4957 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4958 fw_blc_self = I915_READ(FW_BLC_SELF);
4959 fw_blc_self &= ~FW_BLC_SELF_EN;
4960 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4961 }
652c393a 4962 /* Non-busy -> busy, upclock */
3dec0095 4963 intel_increase_pllclock(crtc);
652c393a
JB
4964 intel_crtc->busy = true;
4965 } else {
4966 /* Busy -> busy, put off timer */
4967 mod_timer(&intel_crtc->idle_timer, jiffies +
4968 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4969 }
4970 }
4971 }
4972}
4973
79e53945
JB
4974static void intel_crtc_destroy(struct drm_crtc *crtc)
4975{
4976 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV
4977 struct drm_device *dev = crtc->dev;
4978 struct intel_unpin_work *work;
4979 unsigned long flags;
4980
4981 spin_lock_irqsave(&dev->event_lock, flags);
4982 work = intel_crtc->unpin_work;
4983 intel_crtc->unpin_work = NULL;
4984 spin_unlock_irqrestore(&dev->event_lock, flags);
4985
4986 if (work) {
4987 cancel_work_sync(&work->work);
4988 kfree(work);
4989 }
79e53945
JB
4990
4991 drm_crtc_cleanup(crtc);
67e77c5a 4992
79e53945
JB
4993 kfree(intel_crtc);
4994}
4995
6b95a207
KH
4996static void intel_unpin_work_fn(struct work_struct *__work)
4997{
4998 struct intel_unpin_work *work =
4999 container_of(__work, struct intel_unpin_work, work);
5000
5001 mutex_lock(&work->dev->struct_mutex);
b1b87f6b 5002 i915_gem_object_unpin(work->old_fb_obj);
05394f39
CW
5003 drm_gem_object_unreference(&work->pending_flip_obj->base);
5004 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 5005
6b95a207
KH
5006 mutex_unlock(&work->dev->struct_mutex);
5007 kfree(work);
5008}
5009
1afe3e9d
JB
5010static void do_intel_finish_page_flip(struct drm_device *dev,
5011 struct drm_crtc *crtc)
6b95a207
KH
5012{
5013 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH
5014 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5015 struct intel_unpin_work *work;
05394f39 5016 struct drm_i915_gem_object *obj;
6b95a207
KH
5017 struct drm_pending_vblank_event *e;
5018 struct timeval now;
5019 unsigned long flags;
5020
5021 /* Ignore early vblank irqs */
5022 if (intel_crtc == NULL)
5023 return;
5024
5025 spin_lock_irqsave(&dev->event_lock, flags);
5026 work = intel_crtc->unpin_work;
5027 if (work == NULL || !work->pending) {
5028 spin_unlock_irqrestore(&dev->event_lock, flags);
5029 return;
5030 }
5031
5032 intel_crtc->unpin_work = NULL;
5033 drm_vblank_put(dev, intel_crtc->pipe);
5034
5035 if (work->event) {
5036 e = work->event;
5037 do_gettimeofday(&now);
5038 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
5039 e->event.tv_sec = now.tv_sec;
5040 e->event.tv_usec = now.tv_usec;
5041 list_add_tail(&e->base.link,
5042 &e->base.file_priv->event_list);
5043 wake_up_interruptible(&e->base.file_priv->event_wait);
5044 }
5045
5046 spin_unlock_irqrestore(&dev->event_lock, flags);
5047
05394f39 5048 obj = work->old_fb_obj;
d9e86c0e 5049
e59f2bac 5050 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW
5051 &obj->pending_flip.counter);
5052 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 5053 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 5054
6b95a207 5055 schedule_work(&work->work);
e5510fac
JB
5056
5057 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH
5058}
5059
1afe3e9d
JB
5060void intel_finish_page_flip(struct drm_device *dev, int pipe)
5061{
5062 drm_i915_private_t *dev_priv = dev->dev_private;
5063 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5064
5065 do_intel_finish_page_flip(dev, crtc);
5066}
5067
5068void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5069{
5070 drm_i915_private_t *dev_priv = dev->dev_private;
5071 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5072
5073 do_intel_finish_page_flip(dev, crtc);
5074}
5075
6b95a207
KH
5076void intel_prepare_page_flip(struct drm_device *dev, int plane)
5077{
5078 drm_i915_private_t *dev_priv = dev->dev_private;
5079 struct intel_crtc *intel_crtc =
5080 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5081 unsigned long flags;
5082
5083 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 5084 if (intel_crtc->unpin_work) {
4e5359cd
SF
5085 if ((++intel_crtc->unpin_work->pending) > 1)
5086 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB
5087 } else {
5088 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5089 }
6b95a207
KH
5090 spin_unlock_irqrestore(&dev->event_lock, flags);
5091}
5092
5093static int intel_crtc_page_flip(struct drm_crtc *crtc,
5094 struct drm_framebuffer *fb,
5095 struct drm_pending_vblank_event *event)
5096{
5097 struct drm_device *dev = crtc->dev;
5098 struct drm_i915_private *dev_priv = dev->dev_private;
5099 struct intel_framebuffer *intel_fb;
05394f39 5100 struct drm_i915_gem_object *obj;
6b95a207
KH
5101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5102 struct intel_unpin_work *work;
be9a3dbf 5103 unsigned long flags, offset;
52e68630 5104 int pipe = intel_crtc->pipe;
20f0cd55 5105 u32 pf, pipesrc;
52e68630 5106 int ret;
6b95a207
KH
5107
5108 work = kzalloc(sizeof *work, GFP_KERNEL);
5109 if (work == NULL)
5110 return -ENOMEM;
5111
6b95a207
KH
5112 work->event = event;
5113 work->dev = crtc->dev;
5114 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 5115 work->old_fb_obj = intel_fb->obj;
6b95a207
KH
5116 INIT_WORK(&work->work, intel_unpin_work_fn);
5117
5118 /* We borrow the event spin lock for protecting unpin_work */
5119 spin_lock_irqsave(&dev->event_lock, flags);
5120 if (intel_crtc->unpin_work) {
5121 spin_unlock_irqrestore(&dev->event_lock, flags);
5122 kfree(work);
468f0b44
CW
5123
5124 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH
5125 return -EBUSY;
5126 }
5127 intel_crtc->unpin_work = work;
5128 spin_unlock_irqrestore(&dev->event_lock, flags);
5129
5130 intel_fb = to_intel_framebuffer(fb);
5131 obj = intel_fb->obj;
5132
468f0b44 5133 mutex_lock(&dev->struct_mutex);
1ec14ad3 5134 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
96b099fd
CW
5135 if (ret)
5136 goto cleanup_work;
6b95a207 5137
75dfca80 5138 /* Reference the objects for the scheduled work. */
05394f39
CW
5139 drm_gem_object_reference(&work->old_fb_obj->base);
5140 drm_gem_object_reference(&obj->base);
6b95a207
KH
5141
5142 crtc->fb = fb;
96b099fd
CW
5143
5144 ret = drm_vblank_get(dev, intel_crtc->pipe);
5145 if (ret)
5146 goto cleanup_objs;
5147
c7f9f9a8
CW
5148 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5149 u32 flip_mask;
48b956c5 5150
c7f9f9a8
CW
5151 /* Can't queue multiple flips, so wait for the previous
5152 * one to finish before executing the next.
5153 */
e1f99ce6
CW
5154 ret = BEGIN_LP_RING(2);
5155 if (ret)
5156 goto cleanup_objs;
5157
c7f9f9a8
CW
5158 if (intel_crtc->plane)
5159 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5160 else
5161 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5162 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5163 OUT_RING(MI_NOOP);
6146b3d6
DV
5164 ADVANCE_LP_RING();
5165 }
83f7fd05 5166
e1f99ce6 5167 work->pending_flip_obj = obj;
e1f99ce6 5168
4e5359cd
SF
5169 work->enable_stall_check = true;
5170
be9a3dbf 5171 /* Offset into the new buffer for cases of shared fbs between CRTCs */
52e68630 5172 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
be9a3dbf 5173
e1f99ce6
CW
5174 ret = BEGIN_LP_RING(4);
5175 if (ret)
5176 goto cleanup_objs;
5177
5178 /* Block clients from rendering to the new back buffer until
5179 * the flip occurs and the object is no longer visible.
5180 */
05394f39 5181 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6
CW
5182
5183 switch (INTEL_INFO(dev)->gen) {
52e68630 5184 case 2:
1afe3e9d
JB
5185 OUT_RING(MI_DISPLAY_FLIP |
5186 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5187 OUT_RING(fb->pitch);
05394f39 5188 OUT_RING(obj->gtt_offset + offset);
52e68630
CW
5189 OUT_RING(MI_NOOP);
5190 break;
5191
5192 case 3:
1afe3e9d
JB
5193 OUT_RING(MI_DISPLAY_FLIP_I915 |
5194 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5195 OUT_RING(fb->pitch);
05394f39 5196 OUT_RING(obj->gtt_offset + offset);
22fd0fab 5197 OUT_RING(MI_NOOP);
52e68630
CW
5198 break;
5199
5200 case 4:
5201 case 5:
5202 /* i965+ uses the linear or tiled offsets from the
5203 * Display Registers (which do not change across a page-flip)
5204 * so we need only reprogram the base address.
5205 */
69d0b96c
DV
5206 OUT_RING(MI_DISPLAY_FLIP |
5207 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5208 OUT_RING(fb->pitch);
05394f39 5209 OUT_RING(obj->gtt_offset | obj->tiling_mode);
52e68630
CW
5210
5211 /* XXX Enabling the panel-fitter across page-flip is so far
5212 * untested on non-native modes, so ignore it for now.
5213 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5214 */
5215 pf = 0;
5216 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5217 OUT_RING(pf | pipesrc);
5218 break;
5219
5220 case 6:
5221 OUT_RING(MI_DISPLAY_FLIP |
5222 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
05394f39
CW
5223 OUT_RING(fb->pitch | obj->tiling_mode);
5224 OUT_RING(obj->gtt_offset);
52e68630
CW
5225
5226 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5227 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5228 OUT_RING(pf | pipesrc);
5229 break;
22fd0fab 5230 }
6b95a207
KH
5231 ADVANCE_LP_RING();
5232
5233 mutex_unlock(&dev->struct_mutex);
5234
e5510fac
JB
5235 trace_i915_flip_request(intel_crtc->plane, obj);
5236
6b95a207 5237 return 0;
96b099fd
CW
5238
5239cleanup_objs:
05394f39
CW
5240 drm_gem_object_unreference(&work->old_fb_obj->base);
5241 drm_gem_object_unreference(&obj->base);
96b099fd
CW
5242cleanup_work:
5243 mutex_unlock(&dev->struct_mutex);
5244
5245 spin_lock_irqsave(&dev->event_lock, flags);
5246 intel_crtc->unpin_work = NULL;
5247 spin_unlock_irqrestore(&dev->event_lock, flags);
5248
5249 kfree(work);
5250
5251 return ret;
6b95a207
KH
5252}
5253
7e7d76c3 5254static struct drm_crtc_helper_funcs intel_helper_funcs = {
79e53945
JB
5255 .dpms = intel_crtc_dpms,
5256 .mode_fixup = intel_crtc_mode_fixup,
5257 .mode_set = intel_crtc_mode_set,
5258 .mode_set_base = intel_pipe_set_base,
81255565 5259 .mode_set_base_atomic = intel_pipe_set_base_atomic,
068143d3 5260 .load_lut = intel_crtc_load_lut,
cdd59983 5261 .disable = intel_crtc_disable,
79e53945
JB
5262};
5263
5264static const struct drm_crtc_funcs intel_crtc_funcs = {
5265 .cursor_set = intel_crtc_cursor_set,
5266 .cursor_move = intel_crtc_cursor_move,
5267 .gamma_set = intel_crtc_gamma_set,
5268 .set_config = drm_crtc_helper_set_config,
5269 .destroy = intel_crtc_destroy,
6b95a207 5270 .page_flip = intel_crtc_page_flip,
79e53945
JB
5271};
5272
47f1c6c9
CW
5273static void intel_sanitize_modesetting(struct drm_device *dev,
5274 int pipe, int plane)
5275{
5276 struct drm_i915_private *dev_priv = dev->dev_private;
5277 u32 reg, val;
5278
5279 if (HAS_PCH_SPLIT(dev))
5280 return;
5281
5282 /* Who knows what state these registers were left in by the BIOS or
5283 * grub?
5284 *
5285 * If we leave the registers in a conflicting state (e.g. with the
5286 * display plane reading from the other pipe than the one we intend
5287 * to use) then when we attempt to teardown the active mode, we will
5288 * not disable the pipes and planes in the correct order -- leaving
5289 * a plane reading from a disabled pipe and possibly leading to
5290 * undefined behaviour.
5291 */
5292
5293 reg = DSPCNTR(plane);
5294 val = I915_READ(reg);
5295
5296 if ((val & DISPLAY_PLANE_ENABLE) == 0)
5297 return;
5298 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
5299 return;
5300
5301 /* This display plane is active and attached to the other CPU pipe. */
5302 pipe = !pipe;
5303
5304 /* Disable the plane and wait for it to stop reading from the pipe. */
5305 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
5306 intel_flush_display_plane(dev, plane);
5307
5308 if (IS_GEN2(dev))
5309 intel_wait_for_vblank(dev, pipe);
5310
5311 if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
5312 return;
5313
5314 /* Switch off the pipe. */
5315 reg = PIPECONF(pipe);
5316 val = I915_READ(reg);
5317 if (val & PIPECONF_ENABLE) {
5318 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
5319 intel_wait_for_pipe_off(dev, pipe);
5320 }
5321}
79e53945 5322
b358d0a6 5323static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 5324{
22fd0fab 5325 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB
5326 struct intel_crtc *intel_crtc;
5327 int i;
5328
5329 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5330 if (intel_crtc == NULL)
5331 return;
5332
5333 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5334
5335 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB
5336 for (i = 0; i < 256; i++) {
5337 intel_crtc->lut_r[i] = i;
5338 intel_crtc->lut_g[i] = i;
5339 intel_crtc->lut_b[i] = i;
5340 }
5341
80824003
JB
5342 /* Swap pipes & planes for FBC on pre-965 */
5343 intel_crtc->pipe = pipe;
5344 intel_crtc->plane = pipe;
e2e767ab 5345 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 5346 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 5347 intel_crtc->plane = !pipe;
80824003
JB
5348 }
5349
22fd0fab
JB
5350 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5351 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5352 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5353 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5354
79e53945 5355 intel_crtc->cursor_addr = 0;
032d2a0d 5356 intel_crtc->dpms_mode = -1;
e65d9305 5357 intel_crtc->active = true; /* force the pipe off on setup_init_config */
7e7d76c3
JB
5358
5359 if (HAS_PCH_SPLIT(dev)) {
5360 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5361 intel_helper_funcs.commit = ironlake_crtc_commit;
5362 } else {
5363 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5364 intel_helper_funcs.commit = i9xx_crtc_commit;
5365 }
5366
79e53945
JB
5367 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5368
652c393a
JB
5369 intel_crtc->busy = false;
5370
5371 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5372 (unsigned long)intel_crtc);
47f1c6c9
CW
5373
5374 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
79e53945
JB
5375}
5376
08d7b3d1 5377int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 5378 struct drm_file *file)
08d7b3d1
CW
5379{
5380 drm_i915_private_t *dev_priv = dev->dev_private;
5381 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV
5382 struct drm_mode_object *drmmode_obj;
5383 struct intel_crtc *crtc;
08d7b3d1
CW
5384
5385 if (!dev_priv) {
5386 DRM_ERROR("called with no initialization\n");
5387 return -EINVAL;
5388 }
5389
c05422d5
DV
5390 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5391 DRM_MODE_OBJECT_CRTC);
08d7b3d1 5392
c05422d5 5393 if (!drmmode_obj) {
08d7b3d1
CW
5394 DRM_ERROR("no such CRTC id\n");
5395 return -EINVAL;
5396 }
5397
c05422d5
DV
5398 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5399 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 5400
c05422d5 5401 return 0;
08d7b3d1
CW
5402}
5403
c5e4df33 5404static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 5405{
4ef69c7a 5406 struct intel_encoder *encoder;
79e53945 5407 int index_mask = 0;
79e53945
JB
5408 int entry = 0;
5409
4ef69c7a
CW
5410 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5411 if (type_mask & encoder->clone_mask)
79e53945
JB
5412 index_mask |= (1 << entry);
5413 entry++;
5414 }
4ef69c7a 5415
79e53945
JB
5416 return index_mask;
5417}
5418
79e53945
JB
5419static void intel_setup_outputs(struct drm_device *dev)
5420{
725e30ad 5421 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 5422 struct intel_encoder *encoder;
cb0953d7 5423 bool dpd_is_edp = false;
c5d1b51d 5424 bool has_lvds = false;
79e53945 5425
541998a1 5426 if (IS_MOBILE(dev) && !IS_I830(dev))
c5d1b51d
CW
5427 has_lvds = intel_lvds_init(dev);
5428 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
5429 /* disable the panel fitter on everything but LVDS */
5430 I915_WRITE(PFIT_CONTROL, 0);
5431 }
79e53945 5432
bad720ff 5433 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 5434 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 5435
32f9d658
ZW
5436 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5437 intel_dp_init(dev, DP_A);
5438
cb0953d7
AJ
5439 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5440 intel_dp_init(dev, PCH_DP_D);
5441 }
5442
5443 intel_crt_init(dev);
5444
5445 if (HAS_PCH_SPLIT(dev)) {
5446 int found;
5447
30ad48b7 5448 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca
ZY
5449 /* PCH SDVOB multiplex with HDMIB */
5450 found = intel_sdvo_init(dev, PCH_SDVOB);
30ad48b7
ZW
5451 if (!found)
5452 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW
5453 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5454 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW
5455 }
5456
5457 if (I915_READ(HDMIC) & PORT_DETECTED)
5458 intel_hdmi_init(dev, HDMIC);
5459
5460 if (I915_READ(HDMID) & PORT_DETECTED)
5461 intel_hdmi_init(dev, HDMID);
5462
5eb08b69
ZW
5463 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5464 intel_dp_init(dev, PCH_DP_C);
5465
cb0953d7 5466 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW
5467 intel_dp_init(dev, PCH_DP_D);
5468
103a196f 5469 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 5470 bool found = false;
7d57382e 5471
725e30ad 5472 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 5473 DRM_DEBUG_KMS("probing SDVOB\n");
725e30ad 5474 found = intel_sdvo_init(dev, SDVOB);
b01f2c3a
JB
5475 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5476 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 5477 intel_hdmi_init(dev, SDVOB);
b01f2c3a 5478 }
27185ae1 5479
b01f2c3a
JB
5480 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5481 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 5482 intel_dp_init(dev, DP_B);
b01f2c3a 5483 }
725e30ad 5484 }
13520b05
KH
5485
5486 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 5487
b01f2c3a
JB
5488 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5489 DRM_DEBUG_KMS("probing SDVOC\n");
725e30ad 5490 found = intel_sdvo_init(dev, SDVOC);
b01f2c3a 5491 }
27185ae1
ML
5492
5493 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5494
b01f2c3a
JB
5495 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5496 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 5497 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB
5498 }
5499 if (SUPPORTS_INTEGRATED_DP(dev)) {
5500 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 5501 intel_dp_init(dev, DP_C);
b01f2c3a 5502 }
725e30ad 5503 }
27185ae1 5504
b01f2c3a
JB
5505 if (SUPPORTS_INTEGRATED_DP(dev) &&
5506 (I915_READ(DP_D) & DP_DETECTED)) {
5507 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 5508 intel_dp_init(dev, DP_D);
b01f2c3a 5509 }
bad720ff 5510 } else if (IS_GEN2(dev))
79e53945
JB
5511 intel_dvo_init(dev);
5512
103a196f 5513 if (SUPPORTS_TV(dev))
79e53945
JB
5514 intel_tv_init(dev);
5515
4ef69c7a
CW
5516 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5517 encoder->base.possible_crtcs = encoder->crtc_mask;
5518 encoder->base.possible_clones =
5519 intel_encoder_clones(dev, encoder->clone_mask);
79e53945
JB
5520 }
5521}
5522
5523static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5524{
5525 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB
5526
5527 drm_framebuffer_cleanup(fb);
05394f39 5528 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB
5529
5530 kfree(intel_fb);
5531}
5532
5533static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 5534 struct drm_file *file,
79e53945
JB
5535 unsigned int *handle)
5536{
5537 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 5538 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 5539
05394f39 5540 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB
5541}
5542
5543static const struct drm_framebuffer_funcs intel_fb_funcs = {
5544 .destroy = intel_user_framebuffer_destroy,
5545 .create_handle = intel_user_framebuffer_create_handle,
5546};
5547
38651674
DA
5548int intel_framebuffer_init(struct drm_device *dev,
5549 struct intel_framebuffer *intel_fb,
5550 struct drm_mode_fb_cmd *mode_cmd,
05394f39 5551 struct drm_i915_gem_object *obj)
79e53945 5552{
79e53945
JB
5553 int ret;
5554
05394f39 5555 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW
5556 return -EINVAL;
5557
5558 if (mode_cmd->pitch & 63)
5559 return -EINVAL;
5560
5561 switch (mode_cmd->bpp) {
5562 case 8:
5563 case 16:
5564 case 24:
5565 case 32:
5566 break;
5567 default:
5568 return -EINVAL;
5569 }
5570
79e53945
JB
5571 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5572 if (ret) {
5573 DRM_ERROR("framebuffer init failed %d\n", ret);
5574 return ret;
5575 }
5576
5577 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 5578 intel_fb->obj = obj;
79e53945
JB
5579 return 0;
5580}
5581
79e53945
JB
5582static struct drm_framebuffer *
5583intel_user_framebuffer_create(struct drm_device *dev,
5584 struct drm_file *filp,
5585 struct drm_mode_fb_cmd *mode_cmd)
5586{
05394f39 5587 struct drm_i915_gem_object *obj;
38651674 5588 struct intel_framebuffer *intel_fb;
79e53945
JB
5589 int ret;
5590
05394f39 5591 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
79e53945 5592 if (!obj)
cce13ff7 5593 return ERR_PTR(-ENOENT);
79e53945 5594
38651674
DA
5595 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5596 if (!intel_fb)
cce13ff7 5597 return ERR_PTR(-ENOMEM);
38651674 5598
05394f39 5599 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
79e53945 5600 if (ret) {
05394f39 5601 drm_gem_object_unreference_unlocked(&obj->base);
38651674 5602 kfree(intel_fb);
cce13ff7 5603 return ERR_PTR(ret);
79e53945
JB
5604 }
5605
38651674 5606 return &intel_fb->base;
79e53945
JB
5607}
5608
79e53945 5609static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 5610 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 5611 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB
5612};
5613
05394f39 5614static struct drm_i915_gem_object *
aa40d6bb 5615intel_alloc_context_page(struct drm_device *dev)
9ea8d059 5616{
05394f39 5617 struct drm_i915_gem_object *ctx;
9ea8d059
CW
5618 int ret;
5619
aa40d6bb
ZN
5620 ctx = i915_gem_alloc_object(dev, 4096);
5621 if (!ctx) {
9ea8d059
CW
5622 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5623 return NULL;
5624 }
5625
5626 mutex_lock(&dev->struct_mutex);
75e9e915 5627 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW
5628 if (ret) {
5629 DRM_ERROR("failed to pin power context: %d\n", ret);
5630 goto err_unref;
5631 }
5632
aa40d6bb 5633 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW
5634 if (ret) {
5635 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5636 goto err_unpin;
5637 }
5638 mutex_unlock(&dev->struct_mutex);
5639
aa40d6bb 5640 return ctx;
9ea8d059
CW
5641
5642err_unpin:
aa40d6bb 5643 i915_gem_object_unpin(ctx);
9ea8d059 5644err_unref:
05394f39 5645 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW
5646 mutex_unlock(&dev->struct_mutex);
5647 return NULL;
5648}
5649
7648fa99
JB
5650bool ironlake_set_drps(struct drm_device *dev, u8 val)
5651{
5652 struct drm_i915_private *dev_priv = dev->dev_private;
5653 u16 rgvswctl;
5654
5655 rgvswctl = I915_READ16(MEMSWCTL);
5656 if (rgvswctl & MEMCTL_CMD_STS) {
5657 DRM_DEBUG("gpu busy, RCS change rejected\n");
5658 return false; /* still busy with another command */
5659 }
5660
5661 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5662 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5663 I915_WRITE16(MEMSWCTL, rgvswctl);
5664 POSTING_READ16(MEMSWCTL);
5665
5666 rgvswctl |= MEMCTL_CMD_STS;
5667 I915_WRITE16(MEMSWCTL, rgvswctl);
5668
5669 return true;
5670}
5671
f97108d1
JB
5672void ironlake_enable_drps(struct drm_device *dev)
5673{
5674 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 5675 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 5676 u8 fmax, fmin, fstart, vstart;
f97108d1 5677
ea056c14
JB
5678 /* Enable temp reporting */
5679 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5680 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5681
f97108d1
JB
5682 /* 100ms RC evaluation intervals */
5683 I915_WRITE(RCUPEI, 100000);
5684 I915_WRITE(RCDNEI, 100000);
5685
5686 /* Set max/min thresholds to 90ms and 80ms respectively */
5687 I915_WRITE(RCBMAXAVG, 90000);
5688 I915_WRITE(RCBMINAVG, 80000);
5689
5690 I915_WRITE(MEMIHYST, 1);
5691
5692 /* Set up min, max, and cur for interrupt handling */
5693 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5694 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5695 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5696 MEMMODE_FSTART_SHIFT;
7648fa99 5697
f97108d1
JB
5698 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5699 PXVFREQ_PX_SHIFT;
5700
80dbf4b7 5701 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB
5702 dev_priv->fstart = fstart;
5703
80dbf4b7 5704 dev_priv->max_delay = fstart;
f97108d1
JB
5705 dev_priv->min_delay = fmin;
5706 dev_priv->cur_delay = fstart;
5707
80dbf4b7
JB
5708 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
5709 fmax, fmin, fstart);
7648fa99 5710
f97108d1
JB
5711 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5712
5713 /*
5714 * Interrupts will be enabled in ironlake_irq_postinstall
5715 */
5716
5717 I915_WRITE(VIDSTART, vstart);
5718 POSTING_READ(VIDSTART);
5719
5720 rgvmodectl |= MEMMODE_SWMODE_EN;
5721 I915_WRITE(MEMMODECTL, rgvmodectl);
5722
481b6af3 5723 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 5724 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB
5725 msleep(1);
5726
7648fa99 5727 ironlake_set_drps(dev, fstart);
f97108d1 5728
7648fa99
JB
5729 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5730 I915_READ(0x112e0);
5731 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5732 dev_priv->last_count2 = I915_READ(0x112f4);
5733 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB
5734}
5735
5736void ironlake_disable_drps(struct drm_device *dev)
5737{
5738 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 5739 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB
5740
5741 /* Ack interrupts, disable EFC interrupt */
5742 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5743 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5744 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5745 I915_WRITE(DEIIR, DE_PCU_EVENT);
5746 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5747
5748 /* Go back to the starting frequency */
7648fa99 5749 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB
5750 msleep(1);
5751 rgvswctl |= MEMCTL_CMD_STS;
5752 I915_WRITE(MEMSWCTL, rgvswctl);
5753 msleep(1);
5754
5755}
5756
7648fa99
JB
5757static unsigned long intel_pxfreq(u32 vidfreq)
5758{
5759 unsigned long freq;
5760 int div = (vidfreq & 0x3f0000) >> 16;
5761 int post = (vidfreq & 0x3000) >> 12;
5762 int pre = (vidfreq & 0x7);
5763
5764 if (!pre)
5765 return 0;
5766
5767 freq = ((div * 133333) / ((1<<post) * pre));
5768
5769 return freq;
5770}
5771
5772void intel_init_emon(struct drm_device *dev)
5773{
5774 struct drm_i915_private *dev_priv = dev->dev_private;
5775 u32 lcfuse;
5776 u8 pxw[16];
5777 int i;
5778
5779 /* Disable to program */
5780 I915_WRITE(ECR, 0);
5781 POSTING_READ(ECR);
5782
5783 /* Program energy weights for various events */
5784 I915_WRITE(SDEW, 0x15040d00);
5785 I915_WRITE(CSIEW0, 0x007f0000);
5786 I915_WRITE(CSIEW1, 0x1e220004);
5787 I915_WRITE(CSIEW2, 0x04000004);
5788
5789 for (i = 0; i < 5; i++)
5790 I915_WRITE(PEW + (i * 4), 0);
5791 for (i = 0; i < 3; i++)
5792 I915_WRITE(DEW + (i * 4), 0);
5793
5794 /* Program P-state weights to account for frequency power adjustment */
5795 for (i = 0; i < 16; i++) {
5796 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5797 unsigned long freq = intel_pxfreq(pxvidfreq);
5798 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5799 PXVFREQ_PX_SHIFT;
5800 unsigned long val;
5801
5802 val = vid * vid;
5803 val *= (freq / 1000);
5804 val *= 255;
5805 val /= (127*127*900);
5806 if (val > 0xff)
5807 DRM_ERROR("bad pxval: %ld\n", val);
5808 pxw[i] = val;
5809 }
5810 /* Render standby states get 0 weight */
5811 pxw[14] = 0;
5812 pxw[15] = 0;
5813
5814 for (i = 0; i < 4; i++) {
5815 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5816 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5817 I915_WRITE(PXW + (i * 4), val);
5818 }
5819
5820 /* Adjust magic regs to magic values (more experimental results) */
5821 I915_WRITE(OGW0, 0);
5822 I915_WRITE(OGW1, 0);
5823 I915_WRITE(EG0, 0x00007f00);
5824 I915_WRITE(EG1, 0x0000000e);
5825 I915_WRITE(EG2, 0x000e0000);
5826 I915_WRITE(EG3, 0x68000300);
5827 I915_WRITE(EG4, 0x42000000);
5828 I915_WRITE(EG5, 0x00140031);
5829 I915_WRITE(EG6, 0);
5830 I915_WRITE(EG7, 0);
5831
5832 for (i = 0; i < 8; i++)
5833 I915_WRITE(PXWL + (i * 4), 0);
5834
5835 /* Enable PMON + select events */
5836 I915_WRITE(ECR, 0x80000019);
5837
5838 lcfuse = I915_READ(LCFUSE02);
5839
5840 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5841}
5842
8fd26859
CW
5843static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
5844{
5845 int i;
5846
5847 /* Here begins a magic sequence of register writes to enable
5848 * auto-downclocking.
5849 *
5850 * Perhaps there might be some value in exposing these to
5851 * userspace...
5852 */
5853 I915_WRITE(GEN6_RC_STATE, 0);
5854 __gen6_force_wake_get(dev_priv);
5855
5856 /* disable the counters and set determistic thresholds */
5857 I915_WRITE(GEN6_RC_CONTROL, 0);
5858
5859 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5860 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5861 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5862 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5863 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5864
5865 for (i = 0; i < I915_NUM_RINGS; i++)
5866 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
5867
5868 I915_WRITE(GEN6_RC_SLEEP, 0);
5869 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5870 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5871 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
5872 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5873
5874 I915_WRITE(GEN6_RC_CONTROL,
5875 GEN6_RC_CTL_RC6p_ENABLE |
5876 GEN6_RC_CTL_RC6_ENABLE |
5877 GEN6_RC_CTL_HW_ENABLE);
5878
5879 I915_WRITE(GEN6_RC_NORMAL_FREQ,
5880 GEN6_FREQUENCY(10) |
5881 GEN6_OFFSET(0) |
5882 GEN6_AGGRESSIVE_TURBO);
5883 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5884 GEN6_FREQUENCY(12));
5885
5886 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5887 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5888 18 << 24 |
5889 6 << 16);
5890 I915_WRITE(GEN6_RP_UP_THRESHOLD, 90000);
5891 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 100000);
5892 I915_WRITE(GEN6_RP_UP_EI, 100000);
5893 I915_WRITE(GEN6_RP_DOWN_EI, 300000);
5894 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5895 I915_WRITE(GEN6_RP_CONTROL,
5896 GEN6_RP_MEDIA_TURBO |
5897 GEN6_RP_USE_NORMAL_FREQ |
5898 GEN6_RP_MEDIA_IS_GFX |
5899 GEN6_RP_ENABLE |
5900 GEN6_RP_UP_BUSY_MAX |
5901 GEN6_RP_DOWN_BUSY_MIN);
5902
5903 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5904 500))
5905 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
5906
5907 I915_WRITE(GEN6_PCODE_DATA, 0);
5908 I915_WRITE(GEN6_PCODE_MAILBOX,
5909 GEN6_PCODE_READY |
5910 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
5911 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5912 500))
5913 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
5914
5915 /* requires MSI enabled */
5916 I915_WRITE(GEN6_PMIER,
5917 GEN6_PM_MBOX_EVENT |
5918 GEN6_PM_THERMAL_EVENT |
5919 GEN6_PM_RP_DOWN_TIMEOUT |
5920 GEN6_PM_RP_UP_THRESHOLD |
5921 GEN6_PM_RP_DOWN_THRESHOLD |
5922 GEN6_PM_RP_UP_EI_EXPIRED |
5923 GEN6_PM_RP_DOWN_EI_EXPIRED);
5924
5925 __gen6_force_wake_put(dev_priv);
5926}
5927
0cdab21f 5928void intel_enable_clock_gating(struct drm_device *dev)
652c393a
JB
5929{
5930 struct drm_i915_private *dev_priv = dev->dev_private;
5931
5932 /*
5933 * Disable clock gating reported to work incorrectly according to the
5934 * specs, but enable as much else as we can.
5935 */
bad720ff 5936 if (HAS_PCH_SPLIT(dev)) {
8956c8bb
EA
5937 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5938
f00a3ddf 5939 if (IS_GEN5(dev)) {
8956c8bb
EA
5940 /* Required for FBC */
5941 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5942 /* Required for CxSR */
5943 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5944
5945 I915_WRITE(PCH_3DCGDIS0,
5946 MARIUNIT_CLOCK_GATE_DISABLE |
5947 SVSMUNIT_CLOCK_GATE_DISABLE);
5948 }
5949
5950 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7f8a8569 5951
382b0936
JB
5952 /*
5953 * On Ibex Peak and Cougar Point, we need to disable clock
5954 * gating for the panel power sequencer or it will fail to
5955 * start up when no ports are active.
5956 */
5957 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5958
7f8a8569
ZW
5959 /*
5960 * According to the spec the following bits should be set in
5961 * order to enable memory self-refresh
5962 * The bit 22/21 of 0x42004
5963 * The bit 5 of 0x42020
5964 * The bit 15 of 0x45000
5965 */
f00a3ddf 5966 if (IS_GEN5(dev)) {
7f8a8569
ZW
5967 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5968 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5969 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5970 I915_WRITE(ILK_DSPCLK_GATE,
5971 (I915_READ(ILK_DSPCLK_GATE) |
5972 ILK_DPARB_CLK_GATE));
5973 I915_WRITE(DISP_ARB_CTL,
5974 (I915_READ(DISP_ARB_CTL) |
5975 DISP_FBC_WM_DIS));
dd8849c8
JB
5976 I915_WRITE(WM3_LP_ILK, 0);
5977 I915_WRITE(WM2_LP_ILK, 0);
5978 I915_WRITE(WM1_LP_ILK, 0);
7f8a8569 5979 }
b52eb4dc
ZY
5980 /*
5981 * Based on the document from hardware guys the following bits
5982 * should be set unconditionally in order to enable FBC.
5983 * The bit 22 of 0x42000
5984 * The bit 22 of 0x42004
5985 * The bit 7,8,9 of 0x42020.
5986 */
5987 if (IS_IRONLAKE_M(dev)) {
5988 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5989 I915_READ(ILK_DISPLAY_CHICKEN1) |
5990 ILK_FBCQ_DIS);
5991 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5992 I915_READ(ILK_DISPLAY_CHICKEN2) |
5993 ILK_DPARB_GATE);
5994 I915_WRITE(ILK_DSPCLK_GATE,
5995 I915_READ(ILK_DSPCLK_GATE) |
5996 ILK_DPFC_DIS1 |
5997 ILK_DPFC_DIS2 |
5998 ILK_CLK_FBC);
5999 }
de6e2eaf 6000
67e92af0
EA
6001 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6002 I915_READ(ILK_DISPLAY_CHICKEN2) |
6003 ILK_ELPIN_409_SELECT);
6004
de6e2eaf
EA
6005 if (IS_GEN5(dev)) {
6006 I915_WRITE(_3D_CHICKEN2,
6007 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6008 _3D_CHICKEN2_WM_READ_PIPELINED);
6009 }
8fd26859 6010
c03342fa 6011 } else if (IS_G4X(dev)) {
652c393a
JB
6012 uint32_t dspclk_gate;
6013 I915_WRITE(RENCLK_GATE_D1, 0);
6014 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6015 GS_UNIT_CLOCK_GATE_DISABLE |
6016 CL_UNIT_CLOCK_GATE_DISABLE);
6017 I915_WRITE(RAMCLK_GATE_D, 0);
6018 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6019 OVRUNIT_CLOCK_GATE_DISABLE |
6020 OVCUNIT_CLOCK_GATE_DISABLE;
6021 if (IS_GM45(dev))
6022 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6023 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
a6c45cf0 6024 } else if (IS_CRESTLINE(dev)) {
652c393a
JB
6025 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6026 I915_WRITE(RENCLK_GATE_D2, 0);
6027 I915_WRITE(DSPCLK_GATE_D, 0);
6028 I915_WRITE(RAMCLK_GATE_D, 0);
6029 I915_WRITE16(DEUC, 0);
a6c45cf0 6030 } else if (IS_BROADWATER(dev)) {
652c393a
JB
6031 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6032 I965_RCC_CLOCK_GATE_DISABLE |
6033 I965_RCPB_CLOCK_GATE_DISABLE |
6034 I965_ISC_CLOCK_GATE_DISABLE |
6035 I965_FBC_CLOCK_GATE_DISABLE);
6036 I915_WRITE(RENCLK_GATE_D2, 0);
a6c45cf0 6037 } else if (IS_GEN3(dev)) {
652c393a
JB
6038 u32 dstate = I915_READ(D_STATE);
6039
6040 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6041 DSTATE_DOT_CLOCK_GATING;
6042 I915_WRITE(D_STATE, dstate);
f0f8a9ce 6043 } else if (IS_I85X(dev) || IS_I865G(dev)) {
652c393a
JB
6044 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6045 } else if (IS_I830(dev)) {
6046 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6047 }
97f5ab66
JB
6048
6049 /*
6050 * GPU can automatically power down the render unit if given a page
6051 * to save state.
6052 */
c5780270 6053 if (IS_IRONLAKE_M(dev) && 0) { /* XXX causes a failure during suspend */
aa40d6bb
ZN
6054 if (dev_priv->renderctx == NULL)
6055 dev_priv->renderctx = intel_alloc_context_page(dev);
6056 if (dev_priv->renderctx) {
05394f39
CW
6057 struct drm_i915_gem_object *obj = dev_priv->renderctx;
6058 if (BEGIN_LP_RING(4) == 0) {
6059 OUT_RING(MI_SET_CONTEXT);
6060 OUT_RING(obj->gtt_offset |
6061 MI_MM_SPACE_GTT |
6062 MI_SAVE_EXT_STATE_EN |
6063 MI_RESTORE_EXT_STATE_EN |
6064 MI_RESTORE_INHIBIT);
6065 OUT_RING(MI_NOOP);
6066 OUT_RING(MI_FLUSH);
6067 ADVANCE_LP_RING();
aa40d6bb 6068 }
bc41606a 6069 } else
aa40d6bb 6070 DRM_DEBUG_KMS("Failed to allocate render context."
bc41606a 6071 "Disable RC6\n");
aa40d6bb
ZN
6072 }
6073
3c8cdf9b 6074 if (IS_GEN4(dev) && IS_MOBILE(dev)) {
05394f39
CW
6075 if (dev_priv->pwrctx == NULL)
6076 dev_priv->pwrctx = intel_alloc_context_page(dev);
7e8b60fa 6077 if (dev_priv->pwrctx) {
05394f39
CW
6078 struct drm_i915_gem_object *obj = dev_priv->pwrctx;
6079 I915_WRITE(PWRCTXA, obj->gtt_offset | PWRCTX_EN);
9ea8d059
CW
6080 I915_WRITE(MCHBAR_RENDER_STANDBY,
6081 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
6082 }
97f5ab66 6083 }
8fd26859
CW
6084
6085 if (IS_GEN6(dev))
6086 gen6_enable_rc6(dev_priv);
652c393a
JB
6087}
6088
0cdab21f
CW
6089void intel_disable_clock_gating(struct drm_device *dev)
6090{
6091 struct drm_i915_private *dev_priv = dev->dev_private;
6092
6093 if (dev_priv->renderctx) {
6094 struct drm_i915_gem_object *obj = dev_priv->renderctx;
6095
6096 I915_WRITE(CCID, 0);
6097 POSTING_READ(CCID);
6098
6099 i915_gem_object_unpin(obj);
6100 drm_gem_object_unreference(&obj->base);
6101 dev_priv->renderctx = NULL;
6102 }
6103
6104 if (dev_priv->pwrctx) {
6105 struct drm_i915_gem_object *obj = dev_priv->pwrctx;
6106
6107 I915_WRITE(PWRCTXA, 0);
6108 POSTING_READ(PWRCTXA);
6109
6110 i915_gem_object_unpin(obj);
6111 drm_gem_object_unreference(&obj->base);
6112 dev_priv->pwrctx = NULL;
6113 }
6114}
6115
e70236a8
JB
6116/* Set up chip specific display functions */
6117static void intel_init_display(struct drm_device *dev)
6118{
6119 struct drm_i915_private *dev_priv = dev->dev_private;
6120
6121 /* We always want a DPMS function */
bad720ff 6122 if (HAS_PCH_SPLIT(dev))
f2b115e6 6123 dev_priv->display.dpms = ironlake_crtc_dpms;
e70236a8
JB
6124 else
6125 dev_priv->display.dpms = i9xx_crtc_dpms;
6126
ee5382ae 6127 if (I915_HAS_FBC(dev)) {
b52eb4dc
ZY
6128 if (IS_IRONLAKE_M(dev)) {
6129 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6130 dev_priv->display.enable_fbc = ironlake_enable_fbc;
6131 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6132 } else if (IS_GM45(dev)) {
74dff282
JB
6133 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6134 dev_priv->display.enable_fbc = g4x_enable_fbc;
6135 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 6136 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB
6137 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6138 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6139 dev_priv->display.disable_fbc = i8xx_disable_fbc;
6140 }
74dff282 6141 /* 855GM needs testing */
e70236a8
JB
6142 }
6143
6144 /* Returns the core display clock speed */
f2b115e6 6145 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
e70236a8
JB
6146 dev_priv->display.get_display_clock_speed =
6147 i945_get_display_clock_speed;
6148 else if (IS_I915G(dev))
6149 dev_priv->display.get_display_clock_speed =
6150 i915_get_display_clock_speed;
f2b115e6 6151 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB
6152 dev_priv->display.get_display_clock_speed =
6153 i9xx_misc_get_display_clock_speed;
6154 else if (IS_I915GM(dev))
6155 dev_priv->display.get_display_clock_speed =
6156 i915gm_get_display_clock_speed;
6157 else if (IS_I865G(dev))
6158 dev_priv->display.get_display_clock_speed =
6159 i865_get_display_clock_speed;
f0f8a9ce 6160 else if (IS_I85X(dev))
e70236a8
JB
6161 dev_priv->display.get_display_clock_speed =
6162 i855_get_display_clock_speed;
6163 else /* 852, 830 */
6164 dev_priv->display.get_display_clock_speed =
6165 i830_get_display_clock_speed;
6166
6167 /* For FIFO watermark updates */
7f8a8569 6168 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 6169 if (IS_GEN5(dev)) {
7f8a8569
ZW
6170 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
6171 dev_priv->display.update_wm = ironlake_update_wm;
6172 else {
6173 DRM_DEBUG_KMS("Failed to get proper latency. "
6174 "Disable CxSR\n");
6175 dev_priv->display.update_wm = NULL;
6176 }
6177 } else
6178 dev_priv->display.update_wm = NULL;
6179 } else if (IS_PINEVIEW(dev)) {
d4294342 6180 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 6181 dev_priv->is_ddr3,
d4294342
ZY
6182 dev_priv->fsb_freq,
6183 dev_priv->mem_freq)) {
6184 DRM_INFO("failed to find known CxSR latency "
95534263 6185 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 6186 "disabling CxSR\n",
95534263 6187 (dev_priv->is_ddr3 == 1) ? "3": "2",
d4294342
ZY
6188 dev_priv->fsb_freq, dev_priv->mem_freq);
6189 /* Disable CxSR and never update its watermark again */
6190 pineview_disable_cxsr(dev);
6191 dev_priv->display.update_wm = NULL;
6192 } else
6193 dev_priv->display.update_wm = pineview_update_wm;
6194 } else if (IS_G4X(dev))
e70236a8 6195 dev_priv->display.update_wm = g4x_update_wm;
a6c45cf0 6196 else if (IS_GEN4(dev))
e70236a8 6197 dev_priv->display.update_wm = i965_update_wm;
a6c45cf0 6198 else if (IS_GEN3(dev)) {
e70236a8
JB
6199 dev_priv->display.update_wm = i9xx_update_wm;
6200 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8f4695ed
AJ
6201 } else if (IS_I85X(dev)) {
6202 dev_priv->display.update_wm = i9xx_update_wm;
6203 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
e70236a8 6204 } else {
8f4695ed
AJ
6205 dev_priv->display.update_wm = i830_update_wm;
6206 if (IS_845G(dev))
e70236a8
JB
6207 dev_priv->display.get_fifo_size = i845_get_fifo_size;
6208 else
6209 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8
JB
6210 }
6211}
6212
b690e96c
JB
6213/*
6214 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6215 * resume, or other times. This quirk makes sure that's the case for
6216 * affected systems.
6217 */
6218static void quirk_pipea_force (struct drm_device *dev)
6219{
6220 struct drm_i915_private *dev_priv = dev->dev_private;
6221
6222 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6223 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
6224}
6225
6226struct intel_quirk {
6227 int device;
6228 int subsystem_vendor;
6229 int subsystem_device;
6230 void (*hook)(struct drm_device *dev);
6231};
6232
6233struct intel_quirk intel_quirks[] = {
6234 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
6235 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
6236 /* HP Mini needs pipe A force quirk (LP: #322104) */
6237 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
6238
6239 /* Thinkpad R31 needs pipe A force quirk */
6240 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6241 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6242 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6243
6244 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6245 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6246 /* ThinkPad X40 needs pipe A force quirk */
6247
6248 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6249 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6250
6251 /* 855 & before need to leave pipe A & dpll A up */
6252 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6253 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6254};
6255
6256static void intel_init_quirks(struct drm_device *dev)
6257{
6258 struct pci_dev *d = dev->pdev;
6259 int i;
6260
6261 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6262 struct intel_quirk *q = &intel_quirks[i];
6263
6264 if (d->device == q->device &&
6265 (d->subsystem_vendor == q->subsystem_vendor ||
6266 q->subsystem_vendor == PCI_ANY_ID) &&
6267 (d->subsystem_device == q->subsystem_device ||
6268 q->subsystem_device == PCI_ANY_ID))
6269 q->hook(dev);
6270 }
6271}
6272
9cce37f4
JB
6273/* Disable the VGA plane that we never use */
6274static void i915_disable_vga(struct drm_device *dev)
6275{
6276 struct drm_i915_private *dev_priv = dev->dev_private;
6277 u8 sr1;
6278 u32 vga_reg;
6279
6280 if (HAS_PCH_SPLIT(dev))
6281 vga_reg = CPU_VGACNTRL;
6282 else
6283 vga_reg = VGACNTRL;
6284
6285 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6286 outb(1, VGA_SR_INDEX);
6287 sr1 = inb(VGA_SR_DATA);
6288 outb(sr1 | 1<<5, VGA_SR_DATA);
6289 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6290 udelay(300);
6291
6292 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6293 POSTING_READ(vga_reg);
6294}
6295
79e53945
JB
6296void intel_modeset_init(struct drm_device *dev)
6297{
652c393a 6298 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB
6299 int i;
6300
6301 drm_mode_config_init(dev);
6302
6303 dev->mode_config.min_width = 0;
6304 dev->mode_config.min_height = 0;
6305
6306 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6307
b690e96c
JB
6308 intel_init_quirks(dev);
6309
e70236a8
JB
6310 intel_init_display(dev);
6311
a6c45cf0
CW
6312 if (IS_GEN2(dev)) {
6313 dev->mode_config.max_width = 2048;
6314 dev->mode_config.max_height = 2048;
6315 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP
6316 dev->mode_config.max_width = 4096;
6317 dev->mode_config.max_height = 4096;
79e53945 6318 } else {
a6c45cf0
CW
6319 dev->mode_config.max_width = 8192;
6320 dev->mode_config.max_height = 8192;
79e53945
JB
6321 }
6322
6323 /* set memory base */
a6c45cf0 6324 if (IS_GEN2(dev))
79e53945 6325 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
a6c45cf0
CW
6326 else
6327 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
79e53945 6328
a6c45cf0 6329 if (IS_MOBILE(dev) || !IS_GEN2(dev))
a3524f1b 6330 dev_priv->num_pipe = 2;
79e53945 6331 else
a3524f1b 6332 dev_priv->num_pipe = 1;
28c97730 6333 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 6334 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 6335
a3524f1b 6336 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945
JB
6337 intel_crtc_init(dev, i);
6338 }
6339
6340 intel_setup_outputs(dev);
652c393a 6341
0cdab21f 6342 intel_enable_clock_gating(dev);
652c393a 6343
9cce37f4
JB
6344 /* Just disable it once at startup */
6345 i915_disable_vga(dev);
6346
7648fa99 6347 if (IS_IRONLAKE_M(dev)) {
f97108d1 6348 ironlake_enable_drps(dev);
7648fa99
JB
6349 intel_init_emon(dev);
6350 }
f97108d1 6351
652c393a
JB
6352 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6353 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6354 (unsigned long)dev);
02e792fb
DV
6355
6356 intel_setup_overlay(dev);
79e53945
JB
6357}
6358
6359void intel_modeset_cleanup(struct drm_device *dev)
6360{
652c393a
JB
6361 struct drm_i915_private *dev_priv = dev->dev_private;
6362 struct drm_crtc *crtc;
6363 struct intel_crtc *intel_crtc;
6364
f87ea761 6365 drm_kms_helper_poll_fini(dev);
652c393a
JB
6366 mutex_lock(&dev->struct_mutex);
6367
723bfd70
JB
6368 intel_unregister_dsm_handler();
6369
6370
652c393a
JB
6371 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6372 /* Skip inactive CRTCs */
6373 if (!crtc->fb)
6374 continue;
6375
6376 intel_crtc = to_intel_crtc(crtc);
3dec0095 6377 intel_increase_pllclock(crtc);
652c393a
JB
6378 }
6379
e70236a8
JB
6380 if (dev_priv->display.disable_fbc)
6381 dev_priv->display.disable_fbc(dev);
6382
f97108d1
JB
6383 if (IS_IRONLAKE_M(dev))
6384 ironlake_disable_drps(dev);
6385
0cdab21f
CW
6386 intel_disable_clock_gating(dev);
6387
69341a5e
KH
6388 mutex_unlock(&dev->struct_mutex);
6389
6c0d9350
DV
6390 /* Disable the irq before mode object teardown, for the irq might
6391 * enqueue unpin/hotplug work. */
6392 drm_irq_uninstall(dev);
6393 cancel_work_sync(&dev_priv->hotplug_work);
6394
3dec0095
DV
6395 /* Shut off idle work before the crtcs get freed. */
6396 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6397 intel_crtc = to_intel_crtc(crtc);
6398 del_timer_sync(&intel_crtc->idle_timer);
6399 }
6400 del_timer_sync(&dev_priv->idle_timer);
6401 cancel_work_sync(&dev_priv->idle_work);
6402
79e53945
JB
6403 drm_mode_config_cleanup(dev);
6404}
6405
f1c79df3
ZW
6406/*
6407 * Return which encoder is currently attached for connector.
6408 */
df0e9248 6409struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 6410{
df0e9248
CW
6411 return &intel_attached_encoder(connector)->base;
6412}
f1c79df3 6413
df0e9248
CW
6414void intel_connector_attach_encoder(struct intel_connector *connector,
6415 struct intel_encoder *encoder)
6416{
6417 connector->encoder = encoder;
6418 drm_mode_connector_attach_encoder(&connector->base,
6419 &encoder->base);
79e53945 6420}
28d52043
DA
6421
6422/*
6423 * set vga decode state - true == enable VGA decode
6424 */
6425int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6426{
6427 struct drm_i915_private *dev_priv = dev->dev_private;
6428 u16 gmch_ctrl;
6429
6430 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6431 if (state)
6432 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6433 else
6434 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6435 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6436 return 0;
6437}
c4a1d9e4
CW
6438
6439#ifdef CONFIG_DEBUG_FS
6440#include <linux/seq_file.h>
6441
6442struct intel_display_error_state {
6443 struct intel_cursor_error_state {
6444 u32 control;
6445 u32 position;
6446 u32 base;
6447 u32 size;
6448 } cursor[2];
6449
6450 struct intel_pipe_error_state {
6451 u32 conf;
6452 u32 source;
6453
6454 u32 htotal;
6455 u32 hblank;
6456 u32 hsync;
6457 u32 vtotal;
6458 u32 vblank;
6459 u32 vsync;
6460 } pipe[2];
6461
6462 struct intel_plane_error_state {
6463 u32 control;
6464 u32 stride;
6465 u32 size;
6466 u32 pos;
6467 u32 addr;
6468 u32 surface;
6469 u32 tile_offset;
6470 } plane[2];
6471};
6472
6473struct intel_display_error_state *
6474intel_display_capture_error_state(struct drm_device *dev)
6475{
6476 drm_i915_private_t *dev_priv = dev->dev_private;
6477 struct intel_display_error_state *error;
6478 int i;
6479
6480 error = kmalloc(sizeof(*error), GFP_ATOMIC);
6481 if (error == NULL)
6482 return NULL;
6483
6484 for (i = 0; i < 2; i++) {
6485 error->cursor[i].control = I915_READ(CURCNTR(i));
6486 error->cursor[i].position = I915_READ(CURPOS(i));
6487 error->cursor[i].base = I915_READ(CURBASE(i));
6488
6489 error->plane[i].control = I915_READ(DSPCNTR(i));
6490 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
6491 error->plane[i].size = I915_READ(DSPSIZE(i));
6492 error->plane[i].pos= I915_READ(DSPPOS(i));
6493 error->plane[i].addr = I915_READ(DSPADDR(i));
6494 if (INTEL_INFO(dev)->gen >= 4) {
6495 error->plane[i].surface = I915_READ(DSPSURF(i));
6496 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
6497 }
6498
6499 error->pipe[i].conf = I915_READ(PIPECONF(i));
6500 error->pipe[i].source = I915_READ(PIPESRC(i));
6501 error->pipe[i].htotal = I915_READ(HTOTAL(i));
6502 error->pipe[i].hblank = I915_READ(HBLANK(i));
6503 error->pipe[i].hsync = I915_READ(HSYNC(i));
6504 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
6505 error->pipe[i].vblank = I915_READ(VBLANK(i));
6506 error->pipe[i].vsync = I915_READ(VSYNC(i));
6507 }
6508
6509 return error;
6510}
6511
6512void
6513intel_display_print_error_state(struct seq_file *m,
6514 struct drm_device *dev,
6515 struct intel_display_error_state *error)
6516{
6517 int i;
6518
6519 for (i = 0; i < 2; i++) {
6520 seq_printf(m, "Pipe [%d]:\n", i);
6521 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
6522 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
6523 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
6524 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
6525 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
6526 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
6527 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
6528 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
6529
6530 seq_printf(m, "Plane [%d]:\n", i);
6531 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
6532 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
6533 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
6534 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
6535 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
6536 if (INTEL_INFO(dev)->gen >= 4) {
6537 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
6538 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
6539 }
6540
6541 seq_printf(m, "Cursor [%d]:\n", i);
6542 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
6543 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
6544 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
6545 }
6546}
6547#endif
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