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drm/i915: Remove ctx->last_ring
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
ef9348c8
CML		 67/*
68 * CHV supports eDP 1.4 that have more link rates.
69 * Below only provides the fixed rate but exclude variable rate.
70 */
71static const struct dp_link_dpll chv_dpll[] = {
72 /*
73 * CHV requires to program fractional division for m2.
74 * m2 is stored in fixed point format using formula below
75 * (m2_int << 22) | m2_fraction
76 */
77 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
78 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
79 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
80 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
81 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
83};
84
cfcb0fc9
JB		 85/**
86 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
87 * @intel_dp: DP struct
88 *
89 * If a CPU or PCH DP output is attached to an eDP panel, this function
90 * will return true, and false otherwise.
91 */
92static bool is_edp(struct intel_dp *intel_dp)
93{
da63a9f2
PZ		 94 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
95
96 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 97}
98
68b4d824 99static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 100{
68b4d824
ID		 101 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
102
103 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 104}
105
df0e9248
CW		 106static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
107{
fa90ecef 108 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 109}
110
ea5b213a 111static void intel_dp_link_down(struct intel_dp *intel_dp);
adddaaf4 112static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 113static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 114
a4fc5ed6 115static int
ea5b213a 116intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 117{
7183dc29 118 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 119 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 120
121 switch (max_link_bw) {
122 case DP_LINK_BW_1_62:
123 case DP_LINK_BW_2_7:
124 break;
d4eead50 125 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 126 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
127 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 128 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
129 max_link_bw = DP_LINK_BW_5_4;
130 else
131 max_link_bw = DP_LINK_BW_2_7;
d4eead50 132 break;
a4fc5ed6 133 default:
d4eead50
ID		 134 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
135 max_link_bw);
a4fc5ed6
KP		 136 max_link_bw = DP_LINK_BW_1_62;
137 break;
138 }
139 return max_link_bw;
140}
141
eeb6324d
PZ		 142static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
143{
144 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
145 struct drm_device *dev = intel_dig_port->base.base.dev;
146 u8 source_max, sink_max;
147
148 source_max = 4;
149 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
150 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
151 source_max = 2;
152
153 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
154
155 return min(source_max, sink_max);
156}
157
cd9dde44
AJ		 158/*
159 * The units on the numbers in the next two are... bizarre. Examples will
160 * make it clearer; this one parallels an example in the eDP spec.
161 *
162 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
163 *
164 * 270000 * 1 * 8 / 10 == 216000
165 *
166 * The actual data capacity of that configuration is 2.16Gbit/s, so the
167 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
168 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
169 * 119000. At 18bpp that's 2142000 kilobits per second.
170 *
171 * Thus the strange-looking division by 10 in intel_dp_link_required, to
172 * get the result in decakilobits instead of kilobits.
173 */
174
a4fc5ed6 175static int
c898261c 176intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 177{
cd9dde44 178 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 179}
180
fe27d53e
DA		 181static int
182intel_dp_max_data_rate(int max_link_clock, int max_lanes)
183{
184 return (max_link_clock * max_lanes * 8) / 10;
185}
186
c19de8eb 187static enum drm_mode_status
a4fc5ed6
KP		 188intel_dp_mode_valid(struct drm_connector *connector,
189 struct drm_display_mode *mode)
190{
df0e9248 191 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 192 struct intel_connector *intel_connector = to_intel_connector(connector);
193 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 194 int target_clock = mode->clock;
195 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 196
dd06f90e
JN		 197 if (is_edp(intel_dp) && fixed_mode) {
198 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 199 return MODE_PANEL;
200
dd06f90e 201 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 202 return MODE_PANEL;
03afc4a2
DV		 203
204 target_clock = fixed_mode->clock;
7de56f43
ZY		 205 }
206
36008365 207 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 208 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 209
210 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
211 mode_rate = intel_dp_link_required(target_clock, 18);
212
213 if (mode_rate > max_rate)
c4867936 214 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 215
216 if (mode->clock < 10000)
217 return MODE_CLOCK_LOW;
218
0af78a2b
DV		 219 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
220 return MODE_H_ILLEGAL;
221
a4fc5ed6
KP		 222 return MODE_OK;
223}
224
225static uint32_t
226pack_aux(uint8_t *src, int src_bytes)
227{
228 int i;
229 uint32_t v = 0;
230
231 if (src_bytes > 4)
232 src_bytes = 4;
233 for (i = 0; i < src_bytes; i++)
234 v |= ((uint32_t) src[i]) << ((3-i) * 8);
235 return v;
236}
237
238static void
239unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
240{
241 int i;
242 if (dst_bytes > 4)
243 dst_bytes = 4;
244 for (i = 0; i < dst_bytes; i++)
245 dst[i] = src >> ((3-i) * 8);
246}
247
fb0f8fbf
KP		 248/* hrawclock is 1/4 the FSB frequency */
249static int
250intel_hrawclk(struct drm_device *dev)
251{
252 struct drm_i915_private *dev_priv = dev->dev_private;
253 uint32_t clkcfg;
254
9473c8f4
VP		 255 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
256 if (IS_VALLEYVIEW(dev))
257 return 200;
258
fb0f8fbf
KP		 259 clkcfg = I915_READ(CLKCFG);
260 switch (clkcfg & CLKCFG_FSB_MASK) {
261 case CLKCFG_FSB_400:
262 return 100;
263 case CLKCFG_FSB_533:
264 return 133;
265 case CLKCFG_FSB_667:
266 return 166;
267 case CLKCFG_FSB_800:
268 return 200;
269 case CLKCFG_FSB_1067:
270 return 266;
271 case CLKCFG_FSB_1333:
272 return 333;
273 /* these two are just a guess; one of them might be right */
274 case CLKCFG_FSB_1600:
275 case CLKCFG_FSB_1600_ALT:
276 return 400;
277 default:
278 return 133;
279 }
280}
281
bf13e81b
JN		 282static void
283intel_dp_init_panel_power_sequencer(struct drm_device *dev,
284 struct intel_dp *intel_dp,
285 struct edp_power_seq *out);
286static void
287intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
288 struct intel_dp *intel_dp,
289 struct edp_power_seq *out);
290
291static enum pipe
292vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
293{
294 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
295 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
296 struct drm_device *dev = intel_dig_port->base.base.dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 enum port port = intel_dig_port->port;
299 enum pipe pipe;
300
301 /* modeset should have pipe */
302 if (crtc)
303 return to_intel_crtc(crtc)->pipe;
304
305 /* init time, try to find a pipe with this port selected */
306 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
307 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
308 PANEL_PORT_SELECT_MASK;
309 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
310 return pipe;
311 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
312 return pipe;
313 }
314
315 /* shrug */
316 return PIPE_A;
317}
318
319static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
320{
321 struct drm_device *dev = intel_dp_to_dev(intel_dp);
322
323 if (HAS_PCH_SPLIT(dev))
324 return PCH_PP_CONTROL;
325 else
326 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
327}
328
329static u32 _pp_stat_reg(struct intel_dp *intel_dp)
330{
331 struct drm_device *dev = intel_dp_to_dev(intel_dp);
332
333 if (HAS_PCH_SPLIT(dev))
334 return PCH_PP_STATUS;
335 else
336 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
337}
338
4be73780 339static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 340{
30add22d 341 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 342 struct drm_i915_private *dev_priv = dev->dev_private;
343
bf13e81b 344 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 345}
346
4be73780 347static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 348{
30add22d 349 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 350 struct drm_i915_private *dev_priv = dev->dev_private;
bb4932c4
ID		 351 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
352 struct intel_encoder *intel_encoder = &intel_dig_port->base;
353 enum intel_display_power_domain power_domain;
ebf33b18 354
bb4932c4
ID		 355 power_domain = intel_display_port_power_domain(intel_encoder);
356 return intel_display_power_enabled(dev_priv, power_domain) &&
efbc20ab 357 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 358}
359
9b984dae
KP		 360static void
361intel_dp_check_edp(struct intel_dp *intel_dp)
362{
30add22d 363 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 364 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 365
9b984dae
KP		 366 if (!is_edp(intel_dp))
367 return;
453c5420 368
4be73780 369 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 370 WARN(1, "eDP powered off while attempting aux channel communication.\n");
371 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 372 I915_READ(_pp_stat_reg(intel_dp)),
373 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 374 }
375}
376
9ee32fea
DV		 377static uint32_t
378intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
379{
380 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
381 struct drm_device *dev = intel_dig_port->base.base.dev;
382 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 383 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 384 uint32_t status;
385 bool done;
386
ef04f00d 387#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 388 if (has_aux_irq)
b18ac466 389 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 390 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 391 else
392 done = wait_for_atomic(C, 10) == 0;
393 if (!done)
394 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
395 has_aux_irq);
396#undef C
397
398 return status;
399}
400
ec5b01dd 401static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 402{
174edf1f
PZ		 403 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
404 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 405
ec5b01dd
DL		 406 /*
407 * The clock divider is based off the hrawclk, and would like to run at
408 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 409 */
ec5b01dd
DL		 410 return index ? 0 : intel_hrawclk(dev) / 2;
411}
412
413static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
414{
415 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
416 struct drm_device *dev = intel_dig_port->base.base.dev;
417
418 if (index)
419 return 0;
420
421 if (intel_dig_port->port == PORT_A) {
422 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 423 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 424 else
b84a1cf8 425 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 426 } else {
427 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
428 }
429}
430
431static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
432{
433 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
434 struct drm_device *dev = intel_dig_port->base.base.dev;
435 struct drm_i915_private *dev_priv = dev->dev_private;
436
437 if (intel_dig_port->port == PORT_A) {
438 if (index)
439 return 0;
440 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 441 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
442 /* Workaround for non-ULT HSW */
bc86625a
CW		 443 switch (index) {
444 case 0: return 63;
445 case 1: return 72;
446 default: return 0;
447 }
ec5b01dd 448 } else {
bc86625a 449 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 450 }
b84a1cf8
RV		 451}
452
ec5b01dd
DL		 453static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
454{
455 return index ? 0 : 100;
456}
457
5ed12a19
DL		 458static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
459 bool has_aux_irq,
460 int send_bytes,
461 uint32_t aux_clock_divider)
462{
463 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
464 struct drm_device *dev = intel_dig_port->base.base.dev;
465 uint32_t precharge, timeout;
466
467 if (IS_GEN6(dev))
468 precharge = 3;
469 else
470 precharge = 5;
471
472 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
473 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
474 else
475 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
476
477 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 478 DP_AUX_CH_CTL_DONE |
5ed12a19 479 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 480 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 481 timeout |
788d4433 482 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 483 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
484 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 485 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 486}
487
b84a1cf8
RV		 488static int
489intel_dp_aux_ch(struct intel_dp *intel_dp,
490 uint8_t *send, int send_bytes,
491 uint8_t *recv, int recv_size)
492{
493 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
494 struct drm_device *dev = intel_dig_port->base.base.dev;
495 struct drm_i915_private *dev_priv = dev->dev_private;
496 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
497 uint32_t ch_data = ch_ctl + 4;
bc86625a 498 uint32_t aux_clock_divider;
b84a1cf8
RV		 499 int i, ret, recv_bytes;
500 uint32_t status;
5ed12a19 501 int try, clock = 0;
4e6b788c 502 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 503 bool vdd;
504
505 vdd = _edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 506
507 /* dp aux is extremely sensitive to irq latency, hence request the
508 * lowest possible wakeup latency and so prevent the cpu from going into
509 * deep sleep states.
510 */
511 pm_qos_update_request(&dev_priv->pm_qos, 0);
512
513 intel_dp_check_edp(intel_dp);
5eb08b69 514
c67a470b
PZ		 515 intel_aux_display_runtime_get(dev_priv);
516
11bee43e
JB		 517 /* Try to wait for any previous AUX channel activity */
518 for (try = 0; try < 3; try++) {
ef04f00d 519 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 520 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
521 break;
522 msleep(1);
523 }
524
525 if (try == 3) {
526 WARN(1, "dp_aux_ch not started status 0x%08x\n",
527 I915_READ(ch_ctl));
9ee32fea
DV		 528 ret = -EBUSY;
529 goto out;
4f7f7b7e
CW		 530 }
531
46a5ae9f
PZ		 532 /* Only 5 data registers! */
533 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
534 ret = -E2BIG;
535 goto out;
536 }
537
ec5b01dd 538 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 539 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
540 has_aux_irq,
541 send_bytes,
542 aux_clock_divider);
5ed12a19 543
bc86625a
CW		 544 /* Must try at least 3 times according to DP spec */
545 for (try = 0; try < 5; try++) {
546 /* Load the send data into the aux channel data registers */
547 for (i = 0; i < send_bytes; i += 4)
548 I915_WRITE(ch_data + i,
549 pack_aux(send + i, send_bytes - i));
550
551 /* Send the command and wait for it to complete */
5ed12a19 552 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 553
554 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
555
556 /* Clear done status and any errors */
557 I915_WRITE(ch_ctl,
558 status |
559 DP_AUX_CH_CTL_DONE |
560 DP_AUX_CH_CTL_TIME_OUT_ERROR |
561 DP_AUX_CH_CTL_RECEIVE_ERROR);
562
563 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
564 DP_AUX_CH_CTL_RECEIVE_ERROR))
565 continue;
566 if (status & DP_AUX_CH_CTL_DONE)
567 break;
568 }
4f7f7b7e 569 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 570 break;
571 }
572
a4fc5ed6 573 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 574 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 575 ret = -EBUSY;
576 goto out;
a4fc5ed6
KP		 577 }
578
579 /* Check for timeout or receive error.
580 * Timeouts occur when the sink is not connected
581 */
a5b3da54 582 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 583 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 584 ret = -EIO;
585 goto out;
a5b3da54 586 }
1ae8c0a5
KP		 587
588 /* Timeouts occur when the device isn't connected, so they're
589 * "normal" -- don't fill the kernel log with these */
a5b3da54 590 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 591 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 592 ret = -ETIMEDOUT;
593 goto out;
a4fc5ed6
KP		 594 }
595
596 /* Unload any bytes sent back from the other side */
597 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
598 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 599 if (recv_bytes > recv_size)
600 recv_bytes = recv_size;
0206e353 601
4f7f7b7e
CW		 602 for (i = 0; i < recv_bytes; i += 4)
603 unpack_aux(I915_READ(ch_data + i),
604 recv + i, recv_bytes - i);
a4fc5ed6 605
9ee32fea
DV		 606 ret = recv_bytes;
607out:
608 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 609 intel_aux_display_runtime_put(dev_priv);
9ee32fea 610
884f19e9
JN		 611 if (vdd)
612 edp_panel_vdd_off(intel_dp, false);
613
9ee32fea 614 return ret;
a4fc5ed6
KP		 615}
616
a6c8aff0
JN		 617#define BARE_ADDRESS_SIZE 3
618#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 619static ssize_t
620intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 621{
9d1a1031
JN		 622 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
623 uint8_t txbuf[20], rxbuf[20];
624 size_t txsize, rxsize;
a4fc5ed6 625 int ret;
a4fc5ed6 626
9d1a1031
JN		 627 txbuf[0] = msg->request << 4;
628 txbuf[1] = msg->address >> 8;
629 txbuf[2] = msg->address & 0xff;
630 txbuf[3] = msg->size - 1;
46a5ae9f 631
9d1a1031
JN		 632 switch (msg->request & ~DP_AUX_I2C_MOT) {
633 case DP_AUX_NATIVE_WRITE:
634 case DP_AUX_I2C_WRITE:
a6c8aff0 635 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 636 rxsize = 1;
f51a44b9 637
9d1a1031
JN		 638 if (WARN_ON(txsize > 20))
639 return -E2BIG;
a4fc5ed6 640
9d1a1031 641 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 642
9d1a1031
JN		 643 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
644 if (ret > 0) {
645 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 646
9d1a1031
JN		 647 /* Return payload size. */
648 ret = msg->size;
649 }
650 break;
46a5ae9f 651
9d1a1031
JN		 652 case DP_AUX_NATIVE_READ:
653 case DP_AUX_I2C_READ:
a6c8aff0 654 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 655 rxsize = msg->size + 1;
a4fc5ed6 656
9d1a1031
JN		 657 if (WARN_ON(rxsize > 20))
658 return -E2BIG;
a4fc5ed6 659
9d1a1031
JN		 660 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
661 if (ret > 0) {
662 msg->reply = rxbuf[0] >> 4;
663 /*
664 * Assume happy day, and copy the data. The caller is
665 * expected to check msg->reply before touching it.
666 *
667 * Return payload size.
668 */
669 ret--;
670 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 671 }
9d1a1031
JN		 672 break;
673
674 default:
675 ret = -EINVAL;
676 break;
a4fc5ed6 677 }
f51a44b9 678
9d1a1031 679 return ret;
a4fc5ed6
KP		 680}
681
9d1a1031
JN		 682static void
683intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
684{
685 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 686 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
687 enum port port = intel_dig_port->port;
0b99836f 688 const char *name = NULL;
ab2c0672
DA		 689 int ret;
690
33ad6626
JN		 691 switch (port) {
692 case PORT_A:
693 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 694 name = "DPDDC-A";
ab2c0672 695 break;
33ad6626
JN		 696 case PORT_B:
697 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 698 name = "DPDDC-B";
ab2c0672 699 break;
33ad6626
JN		 700 case PORT_C:
701 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 702 name = "DPDDC-C";
ab2c0672 703 break;
33ad6626
JN		 704 case PORT_D:
705 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 706 name = "DPDDC-D";
33ad6626
JN		 707 break;
708 default:
709 BUG();
ab2c0672
DA		 710 }
711
33ad6626
JN		 712 if (!HAS_DDI(dev))
713 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 714
0b99836f 715 intel_dp->aux.name = name;
9d1a1031
JN		 716 intel_dp->aux.dev = dev->dev;
717 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 718
0b99836f
JN		 719 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
720 connector->base.kdev->kobj.name);
8316f337 721
4f71d0cb 722 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 723 if (ret < 0) {
4f71d0cb 724 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 725 name, ret);
726 return;
ab2c0672 727 }
8a5e6aeb 728
0b99836f
JN		 729 ret = sysfs_create_link(&connector->base.kdev->kobj,
730 &intel_dp->aux.ddc.dev.kobj,
731 intel_dp->aux.ddc.dev.kobj.name);
732 if (ret < 0) {
733 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 734 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 735 }
a4fc5ed6
KP		 736}
737
80f65de3
ID		 738static void
739intel_dp_connector_unregister(struct intel_connector *intel_connector)
740{
741 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
742
743 sysfs_remove_link(&intel_connector->base.kdev->kobj,
0b99836f 744 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 745 intel_connector_unregister(intel_connector);
746}
747
c6bb3538
DV		 748static void
749intel_dp_set_clock(struct intel_encoder *encoder,
750 struct intel_crtc_config *pipe_config, int link_bw)
751{
752 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 753 const struct dp_link_dpll *divisor = NULL;
754 int i, count = 0;
c6bb3538
DV		 755
756 if (IS_G4X(dev)) {
9dd4ffdf
CML		 757 divisor = gen4_dpll;
758 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 759 } else if (IS_HASWELL(dev)) {
760 /* Haswell has special-purpose DP DDI clocks. */
761 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 762 divisor = pch_dpll;
763 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 764 } else if (IS_CHERRYVIEW(dev)) {
765 divisor = chv_dpll;
766 count = ARRAY_SIZE(chv_dpll);
c6bb3538 767 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 768 divisor = vlv_dpll;
769 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 770 }
9dd4ffdf
CML		 771
772 if (divisor && count) {
773 for (i = 0; i < count; i++) {
774 if (link_bw == divisor[i].link_bw) {
775 pipe_config->dpll = divisor[i].dpll;
776 pipe_config->clock_set = true;
777 break;
778 }
779 }
c6bb3538
DV		 780 }
781}
782
439d7ac0
PB		 783static void
784intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
785{
786 struct drm_device *dev = crtc->base.dev;
787 struct drm_i915_private *dev_priv = dev->dev_private;
788 enum transcoder transcoder = crtc->config.cpu_transcoder;
789
790 I915_WRITE(PIPE_DATA_M2(transcoder),
791 TU_SIZE(m_n->tu) | m_n->gmch_m);
792 I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
793 I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
794 I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
795}
796
00c09d70 797bool
5bfe2ac0
DV		 798intel_dp_compute_config(struct intel_encoder *encoder,
799 struct intel_crtc_config *pipe_config)
a4fc5ed6 800{
5bfe2ac0 801 struct drm_device *dev = encoder->base.dev;
36008365 802 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 803 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 804 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 805 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 806 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 807 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 808 int lane_count, clock;
56071a20 809 int min_lane_count = 1;
eeb6324d 810 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 811 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 812 int min_clock = 0;
06ea66b6 813 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 814 int bpp, mode_rate;
06ea66b6 815 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 816 int link_avail, link_clock;
a4fc5ed6 817
bc7d38a4 818 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 819 pipe_config->has_pch_encoder = true;
820
03afc4a2 821 pipe_config->has_dp_encoder = true;
9ed109a7 822 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 823
dd06f90e
JN		 824 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
825 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
826 adjusted_mode);
2dd24552
JB		 827 if (!HAS_PCH_SPLIT(dev))
828 intel_gmch_panel_fitting(intel_crtc, pipe_config,
829 intel_connector->panel.fitting_mode);
830 else
b074cec8
JB		 831 intel_pch_panel_fitting(intel_crtc, pipe_config,
832 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 833 }
834
cb1793ce 835 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 836 return false;
837
083f9560
DV		 838 DRM_DEBUG_KMS("DP link computation with max lane count %i "
839 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 840 max_lane_count, bws[max_clock],
841 adjusted_mode->crtc_clock);
083f9560 842
36008365
DV		 843 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
844 * bpc in between. */
3e7ca985 845 bpp = pipe_config->pipe_bpp;
56071a20
JN		 846 if (is_edp(intel_dp)) {
847 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
848 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
849 dev_priv->vbt.edp_bpp);
850 bpp = dev_priv->vbt.edp_bpp;
851 }
852
f4cdbc21
JN		 853 if (IS_BROADWELL(dev)) {
854 /* Yes, it's an ugly hack. */
855 min_lane_count = max_lane_count;
856 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
857 min_lane_count);
858 } else if (dev_priv->vbt.edp_lanes) {
56071a20
JN		 859 min_lane_count = min(dev_priv->vbt.edp_lanes,
860 max_lane_count);
861 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
862 min_lane_count);
863 }
864
865 if (dev_priv->vbt.edp_rate) {
866 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
867 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
868 bws[min_clock]);
869 }
7984211e 870 }
657445fe 871
36008365 872 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 873 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
874 bpp);
36008365 875
56071a20
JN		 876 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
877 for (clock = min_clock; clock <= max_clock; clock++) {
36008365
DV		 878 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
879 link_avail = intel_dp_max_data_rate(link_clock,
880 lane_count);
881
882 if (mode_rate <= link_avail) {
883 goto found;
884 }
885 }
886 }
887 }
c4867936 888
36008365 889 return false;
3685a8f3 890
36008365 891found:
55bc60db
VS		 892 if (intel_dp->color_range_auto) {
893 /*
894 * See:
895 * CEA-861-E - 5.1 Default Encoding Parameters
896 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
897 */
18316c8c 898 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 899 intel_dp->color_range = DP_COLOR_RANGE_16_235;
900 else
901 intel_dp->color_range = 0;
902 }
903
3685a8f3 904 if (intel_dp->color_range)
50f3b016 905 pipe_config->limited_color_range = true;
a4fc5ed6 906
36008365
DV		 907 intel_dp->link_bw = bws[clock];
908 intel_dp->lane_count = lane_count;
657445fe 909 pipe_config->pipe_bpp = bpp;
ff9a6750 910 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 911
36008365
DV		 912 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
913 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 914 pipe_config->port_clock, bpp);
36008365
DV		 915 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
916 mode_rate, link_avail);
a4fc5ed6 917
03afc4a2 918 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 919 adjusted_mode->crtc_clock,
920 pipe_config->port_clock,
03afc4a2 921 &pipe_config->dp_m_n);
9d1a455b 922
439d7ac0
PB		 923 if (intel_connector->panel.downclock_mode != NULL &&
924 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
925 intel_link_compute_m_n(bpp, lane_count,
926 intel_connector->panel.downclock_mode->clock,
927 pipe_config->port_clock,
928 &pipe_config->dp_m2_n2);
929 }
930
c6bb3538
DV		 931 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
932
03afc4a2 933 return true;
a4fc5ed6
KP		 934}
935
7c62a164 936static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 937{
7c62a164
DV		 938 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
939 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
940 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 941 struct drm_i915_private *dev_priv = dev->dev_private;
942 u32 dpa_ctl;
943
ff9a6750 944 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 945 dpa_ctl = I915_READ(DP_A);
946 dpa_ctl &= ~DP_PLL_FREQ_MASK;
947
ff9a6750 948 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 949 /* For a long time we've carried around a ILK-DevA w/a for the
950 * 160MHz clock. If we're really unlucky, it's still required.
951 */
952 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 953 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 954 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 955 } else {
956 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 957 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 958 }
1ce17038 959
ea9b6006
DV		 960 I915_WRITE(DP_A, dpa_ctl);
961
962 POSTING_READ(DP_A);
963 udelay(500);
964}
965
8ac33ed3 966static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 967{
b934223d 968 struct drm_device *dev = encoder->base.dev;
417e822d 969 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 970 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 971 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 972 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
973 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 974
417e822d 975 /*
1a2eb460 976 * There are four kinds of DP registers:
417e822d
KP		 977 *
978 * IBX PCH
1a2eb460
KP		 979 * SNB CPU
980 * IVB CPU
417e822d
KP		 981 * CPT PCH
982 *
983 * IBX PCH and CPU are the same for almost everything,
984 * except that the CPU DP PLL is configured in this
985 * register
986 *
987 * CPT PCH is quite different, having many bits moved
988 * to the TRANS_DP_CTL register instead. That
989 * configuration happens (oddly) in ironlake_pch_enable
990 */
9c9e7927 991
417e822d
KP		 992 /* Preserve the BIOS-computed detected bit. This is
993 * supposed to be read-only.
994 */
995 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 996
417e822d 997 /* Handle DP bits in common between all three register formats */
417e822d 998 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 999 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1000
9ed109a7 1001 if (crtc->config.has_audio) {
e0dac65e 1002 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1003 pipe_name(crtc->pipe));
ea5b213a 1004 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1005 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1006 }
247d89f6 1007
417e822d 1008 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1009
bc7d38a4 1010 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1011 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1012 intel_dp->DP |= DP_SYNC_HS_HIGH;
1013 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1014 intel_dp->DP |= DP_SYNC_VS_HIGH;
1015 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1016
6aba5b6c 1017 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1018 intel_dp->DP |= DP_ENHANCED_FRAMING;
1019
7c62a164 1020 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1021 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1022 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1023 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1024
1025 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1026 intel_dp->DP |= DP_SYNC_HS_HIGH;
1027 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1028 intel_dp->DP |= DP_SYNC_VS_HIGH;
1029 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1030
6aba5b6c 1031 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1032 intel_dp->DP |= DP_ENHANCED_FRAMING;
1033
44f37d1f
CML		 1034 if (!IS_CHERRYVIEW(dev)) {
1035 if (crtc->pipe == 1)
1036 intel_dp->DP |= DP_PIPEB_SELECT;
1037 } else {
1038 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1039 }
417e822d
KP		 1040 } else {
1041 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1042 }
a4fc5ed6
KP		 1043}
1044
ffd6749d
PZ		 1045#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1046#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1047
1a5ef5b7
PZ		 1048#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1049#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1050
ffd6749d
PZ		 1051#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1052#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1053
4be73780 1054static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1055 u32 mask,
1056 u32 value)
bd943159 1057{
30add22d 1058 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1059 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1060 u32 pp_stat_reg, pp_ctrl_reg;
1061
bf13e81b
JN		 1062 pp_stat_reg = _pp_stat_reg(intel_dp);
1063 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1064
99ea7127 1065 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1066 mask, value,
1067 I915_READ(pp_stat_reg),
1068 I915_READ(pp_ctrl_reg));
32ce697c 1069
453c5420 1070 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1071 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1072 I915_READ(pp_stat_reg),
1073 I915_READ(pp_ctrl_reg));
32ce697c 1074 }
54c136d4
CW		 1075
1076 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1077}
32ce697c 1078
4be73780 1079static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1080{
1081 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1082 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1083}
1084
4be73780 1085static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1086{
1087 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1088 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1089}
1090
4be73780 1091static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1092{
1093 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1094
1095 /* When we disable the VDD override bit last we have to do the manual
1096 * wait. */
1097 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1098 intel_dp->panel_power_cycle_delay);
1099
4be73780 1100 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1101}
1102
4be73780 1103static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1104{
1105 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1106 intel_dp->backlight_on_delay);
1107}
1108
4be73780 1109static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1110{
1111 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1112 intel_dp->backlight_off_delay);
1113}
99ea7127 1114
832dd3c1
KP		 1115/* Read the current pp_control value, unlocking the register if it
1116 * is locked
1117 */
1118
453c5420 1119static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1120{
453c5420
JB		 1121 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1122 struct drm_i915_private *dev_priv = dev->dev_private;
1123 u32 control;
832dd3c1 1124
bf13e81b 1125 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1126 control &= ~PANEL_UNLOCK_MASK;
1127 control |= PANEL_UNLOCK_REGS;
1128 return control;
bd943159
KP		 1129}
1130
adddaaf4 1131static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1132{
30add22d 1133 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1134 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1135 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1136 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1137 enum intel_display_power_domain power_domain;
5d613501 1138 u32 pp;
453c5420 1139 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1140 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1141
97af61f5 1142 if (!is_edp(intel_dp))
adddaaf4 1143 return false;
bd943159
KP		 1144
1145 intel_dp->want_panel_vdd = true;
99ea7127 1146
4be73780 1147 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1148 return need_to_disable;
b0665d57 1149
4e6e1a54
ID		 1150 power_domain = intel_display_port_power_domain(intel_encoder);
1151 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1152
b0665d57 1153 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1154
4be73780
DV		 1155 if (!edp_have_panel_power(intel_dp))
1156 wait_panel_power_cycle(intel_dp);
99ea7127 1157
453c5420 1158 pp = ironlake_get_pp_control(intel_dp);
5d613501 1159 pp |= EDP_FORCE_VDD;
ebf33b18 1160
bf13e81b
JN		 1161 pp_stat_reg = _pp_stat_reg(intel_dp);
1162 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1163
1164 I915_WRITE(pp_ctrl_reg, pp);
1165 POSTING_READ(pp_ctrl_reg);
1166 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1167 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1168 /*
1169 * If the panel wasn't on, delay before accessing aux channel
1170 */
4be73780 1171 if (!edp_have_panel_power(intel_dp)) {
bd943159 1172 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1173 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1174 }
adddaaf4
JN		 1175
1176 return need_to_disable;
1177}
1178
b80d6c78 1179void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4
JN		 1180{
1181 if (is_edp(intel_dp)) {
1182 bool vdd = _edp_panel_vdd_on(intel_dp);
1183
1184 WARN(!vdd, "eDP VDD already requested on\n");
1185 }
5d613501
JB		 1186}
1187
4be73780 1188static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1189{
30add22d 1190 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1191 struct drm_i915_private *dev_priv = dev->dev_private;
1192 u32 pp;
453c5420 1193 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1194
51fd371b 1195 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
a0e99e68 1196
4be73780 1197 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
4e6e1a54
ID		 1198 struct intel_digital_port *intel_dig_port =
1199 dp_to_dig_port(intel_dp);
1200 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1201 enum intel_display_power_domain power_domain;
1202
b0665d57
PZ		 1203 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1204
453c5420 1205 pp = ironlake_get_pp_control(intel_dp);
bd943159 1206 pp &= ~EDP_FORCE_VDD;
bd943159 1207
9f08ef59
PZ		 1208 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1209 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1210
1211 I915_WRITE(pp_ctrl_reg, pp);
1212 POSTING_READ(pp_ctrl_reg);
99ea7127 1213
453c5420
JB		 1214 /* Make sure sequencer is idle before allowing subsequent activity */
1215 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1216 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1217
1218 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1219 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1220
4e6e1a54
ID		 1221 power_domain = intel_display_port_power_domain(intel_encoder);
1222 intel_display_power_put(dev_priv, power_domain);
bd943159
KP		 1223 }
1224}
5d613501 1225
4be73780 1226static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1227{
1228 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1229 struct intel_dp, panel_vdd_work);
30add22d 1230 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1231
51fd371b 1232 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 1233 edp_panel_vdd_off_sync(intel_dp);
51fd371b 1234 drm_modeset_unlock(&dev->mode_config.connection_mutex);
bd943159
KP		 1235}
1236
4be73780 1237static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1238{
97af61f5
KP		 1239 if (!is_edp(intel_dp))
1240 return;
5d613501 1241
bd943159 1242 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1243
bd943159
KP		 1244 intel_dp->want_panel_vdd = false;
1245
1246 if (sync) {
4be73780 1247 edp_panel_vdd_off_sync(intel_dp);
bd943159
KP		 1248 } else {
1249 /*
1250 * Queue the timer to fire a long
1251 * time from now (relative to the power down delay)
1252 * to keep the panel power up across a sequence of operations
1253 */
1254 schedule_delayed_work(&intel_dp->panel_vdd_work,
1255 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1256 }
5d613501
JB		 1257}
1258
4be73780 1259void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1260{
30add22d 1261 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1262 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1263 u32 pp;
453c5420 1264 u32 pp_ctrl_reg;
9934c132 1265
97af61f5 1266 if (!is_edp(intel_dp))
bd943159 1267 return;
99ea7127
KP		 1268
1269 DRM_DEBUG_KMS("Turn eDP power on\n");
1270
4be73780 1271 if (edp_have_panel_power(intel_dp)) {
99ea7127 1272 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1273 return;
99ea7127 1274 }
9934c132 1275
4be73780 1276 wait_panel_power_cycle(intel_dp);
37c6c9b0 1277
bf13e81b 1278 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1279 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1280 if (IS_GEN5(dev)) {
1281 /* ILK workaround: disable reset around power sequence */
1282 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1283 I915_WRITE(pp_ctrl_reg, pp);
1284 POSTING_READ(pp_ctrl_reg);
05ce1a49 1285 }
37c6c9b0 1286
1c0ae80a 1287 pp |= POWER_TARGET_ON;
99ea7127
KP		 1288 if (!IS_GEN5(dev))
1289 pp |= PANEL_POWER_RESET;
1290
453c5420
JB		 1291 I915_WRITE(pp_ctrl_reg, pp);
1292 POSTING_READ(pp_ctrl_reg);
9934c132 1293
4be73780 1294 wait_panel_on(intel_dp);
dce56b3c 1295 intel_dp->last_power_on = jiffies;
9934c132 1296
05ce1a49
KP		 1297 if (IS_GEN5(dev)) {
1298 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1299 I915_WRITE(pp_ctrl_reg, pp);
1300 POSTING_READ(pp_ctrl_reg);
05ce1a49 1301 }
9934c132
JB		 1302}
1303
4be73780 1304void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1305{
4e6e1a54
ID		 1306 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1307 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1308 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1309 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1310 enum intel_display_power_domain power_domain;
99ea7127 1311 u32 pp;
453c5420 1312 u32 pp_ctrl_reg;
9934c132 1313
97af61f5
KP		 1314 if (!is_edp(intel_dp))
1315 return;
37c6c9b0 1316
99ea7127 1317 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1318
4be73780 1319 edp_wait_backlight_off(intel_dp);
dce56b3c 1320
24f3e092
JN		 1321 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1322
453c5420 1323 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1324 /* We need to switch off panel power _and_ force vdd, for otherwise some
1325 * panels get very unhappy and cease to work. */
b3064154
PJ		 1326 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1327 EDP_BLC_ENABLE);
453c5420 1328
bf13e81b 1329 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1330
849e39f5
PZ		 1331 intel_dp->want_panel_vdd = false;
1332
453c5420
JB		 1333 I915_WRITE(pp_ctrl_reg, pp);
1334 POSTING_READ(pp_ctrl_reg);
9934c132 1335
dce56b3c 1336 intel_dp->last_power_cycle = jiffies;
4be73780 1337 wait_panel_off(intel_dp);
849e39f5
PZ		 1338
1339 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1340 power_domain = intel_display_port_power_domain(intel_encoder);
1341 intel_display_power_put(dev_priv, power_domain);
9934c132
JB		 1342}
1343
4be73780 1344void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1345{
da63a9f2
PZ		 1346 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1347 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1348 struct drm_i915_private *dev_priv = dev->dev_private;
1349 u32 pp;
453c5420 1350 u32 pp_ctrl_reg;
32f9d658 1351
f01eca2e
KP		 1352 if (!is_edp(intel_dp))
1353 return;
1354
28c97730 1355 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1356 /*
1357 * If we enable the backlight right away following a panel power
1358 * on, we may see slight flicker as the panel syncs with the eDP
1359 * link. So delay a bit to make sure the image is solid before
1360 * allowing it to appear.
1361 */
4be73780 1362 wait_backlight_on(intel_dp);
453c5420 1363 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1364 pp |= EDP_BLC_ENABLE;
453c5420 1365
bf13e81b 1366 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1367
1368 I915_WRITE(pp_ctrl_reg, pp);
1369 POSTING_READ(pp_ctrl_reg);
035aa3de 1370
752aa88a 1371 intel_panel_enable_backlight(intel_dp->attached_connector);
32f9d658
ZW		 1372}
1373
4be73780 1374void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1375{
30add22d 1376 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1377 struct drm_i915_private *dev_priv = dev->dev_private;
1378 u32 pp;
453c5420 1379 u32 pp_ctrl_reg;
32f9d658 1380
f01eca2e
KP		 1381 if (!is_edp(intel_dp))
1382 return;
1383
752aa88a 1384 intel_panel_disable_backlight(intel_dp->attached_connector);
035aa3de 1385
28c97730 1386 DRM_DEBUG_KMS("\n");
453c5420 1387 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1388 pp &= ~EDP_BLC_ENABLE;
453c5420 1389
bf13e81b 1390 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1391
1392 I915_WRITE(pp_ctrl_reg, pp);
1393 POSTING_READ(pp_ctrl_reg);
dce56b3c 1394 intel_dp->last_backlight_off = jiffies;
32f9d658 1395}
a4fc5ed6 1396
2bd2ad64 1397static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1398{
da63a9f2
PZ		 1399 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1400 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1401 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1402 struct drm_i915_private *dev_priv = dev->dev_private;
1403 u32 dpa_ctl;
1404
2bd2ad64
DV		 1405 assert_pipe_disabled(dev_priv,
1406 to_intel_crtc(crtc)->pipe);
1407
d240f20f
JB		 1408 DRM_DEBUG_KMS("\n");
1409 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1410 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1411 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1412
1413 /* We don't adjust intel_dp->DP while tearing down the link, to
1414 * facilitate link retraining (e.g. after hotplug). Hence clear all
1415 * enable bits here to ensure that we don't enable too much. */
1416 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1417 intel_dp->DP |= DP_PLL_ENABLE;
1418 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1419 POSTING_READ(DP_A);
1420 udelay(200);
d240f20f
JB		 1421}
1422
2bd2ad64 1423static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1424{
da63a9f2
PZ		 1425 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1426 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1427 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1428 struct drm_i915_private *dev_priv = dev->dev_private;
1429 u32 dpa_ctl;
1430
2bd2ad64
DV		 1431 assert_pipe_disabled(dev_priv,
1432 to_intel_crtc(crtc)->pipe);
1433
d240f20f 1434 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1435 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1436 "dp pll off, should be on\n");
1437 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1438
1439 /* We can't rely on the value tracked for the DP register in
1440 * intel_dp->DP because link_down must not change that (otherwise link
1441 * re-training will fail. */
298b0b39 1442 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1443 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1444 POSTING_READ(DP_A);
d240f20f
JB		 1445 udelay(200);
1446}
1447
c7ad3810 1448/* If the sink supports it, try to set the power state appropriately */
c19b0669 1449void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1450{
1451 int ret, i;
1452
1453 /* Should have a valid DPCD by this point */
1454 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1455 return;
1456
1457 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1458 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1459 DP_SET_POWER_D3);
c7ad3810
JB		 1460 if (ret != 1)
1461 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1462 } else {
1463 /*
1464 * When turning on, we need to retry for 1ms to give the sink
1465 * time to wake up.
1466 */
1467 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1468 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1469 DP_SET_POWER_D0);
c7ad3810
JB		 1470 if (ret == 1)
1471 break;
1472 msleep(1);
1473 }
1474 }
1475}
1476
19d8fe15
DV		 1477static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1478 enum pipe *pipe)
d240f20f 1479{
19d8fe15 1480 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1481 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1482 struct drm_device *dev = encoder->base.dev;
1483 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1484 enum intel_display_power_domain power_domain;
1485 u32 tmp;
1486
1487 power_domain = intel_display_port_power_domain(encoder);
1488 if (!intel_display_power_enabled(dev_priv, power_domain))
1489 return false;
1490
1491 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1492
1493 if (!(tmp & DP_PORT_EN))
1494 return false;
1495
bc7d38a4 1496 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1497 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1498 } else if (IS_CHERRYVIEW(dev)) {
1499 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1500 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1501 *pipe = PORT_TO_PIPE(tmp);
1502 } else {
1503 u32 trans_sel;
1504 u32 trans_dp;
1505 int i;
1506
1507 switch (intel_dp->output_reg) {
1508 case PCH_DP_B:
1509 trans_sel = TRANS_DP_PORT_SEL_B;
1510 break;
1511 case PCH_DP_C:
1512 trans_sel = TRANS_DP_PORT_SEL_C;
1513 break;
1514 case PCH_DP_D:
1515 trans_sel = TRANS_DP_PORT_SEL_D;
1516 break;
1517 default:
1518 return true;
1519 }
1520
1521 for_each_pipe(i) {
1522 trans_dp = I915_READ(TRANS_DP_CTL(i));
1523 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1524 *pipe = i;
1525 return true;
1526 }
1527 }
19d8fe15 1528
4a0833ec
DV		 1529 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1530 intel_dp->output_reg);
1531 }
d240f20f 1532
19d8fe15
DV		 1533 return true;
1534}
d240f20f 1535
045ac3b5
JB		 1536static void intel_dp_get_config(struct intel_encoder *encoder,
1537 struct intel_crtc_config *pipe_config)
1538{
1539 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1540 u32 tmp, flags = 0;
63000ef6
XZ		 1541 struct drm_device *dev = encoder->base.dev;
1542 struct drm_i915_private *dev_priv = dev->dev_private;
1543 enum port port = dp_to_dig_port(intel_dp)->port;
1544 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1545 int dotclock;
045ac3b5 1546
9ed109a7
DV		 1547 tmp = I915_READ(intel_dp->output_reg);
1548 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1549 pipe_config->has_audio = true;
1550
63000ef6 1551 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1552 if (tmp & DP_SYNC_HS_HIGH)
1553 flags |= DRM_MODE_FLAG_PHSYNC;
1554 else
1555 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1556
63000ef6
XZ		 1557 if (tmp & DP_SYNC_VS_HIGH)
1558 flags |= DRM_MODE_FLAG_PVSYNC;
1559 else
1560 flags |= DRM_MODE_FLAG_NVSYNC;
1561 } else {
1562 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1563 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1564 flags |= DRM_MODE_FLAG_PHSYNC;
1565 else
1566 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1567
63000ef6
XZ		 1568 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1569 flags |= DRM_MODE_FLAG_PVSYNC;
1570 else
1571 flags |= DRM_MODE_FLAG_NVSYNC;
1572 }
045ac3b5
JB		 1573
1574 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1575
eb14cb74
VS		 1576 pipe_config->has_dp_encoder = true;
1577
1578 intel_dp_get_m_n(crtc, pipe_config);
1579
18442d08 1580 if (port == PORT_A) {
f1f644dc
JB		 1581 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1582 pipe_config->port_clock = 162000;
1583 else
1584 pipe_config->port_clock = 270000;
1585 }
18442d08
VS		 1586
1587 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1588 &pipe_config->dp_m_n);
1589
1590 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1591 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1592
241bfc38 1593 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1594
c6cd2ee2
JN		 1595 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1596 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1597 /*
1598 * This is a big fat ugly hack.
1599 *
1600 * Some machines in UEFI boot mode provide us a VBT that has 18
1601 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1602 * unknown we fail to light up. Yet the same BIOS boots up with
1603 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1604 * max, not what it tells us to use.
1605 *
1606 * Note: This will still be broken if the eDP panel is not lit
1607 * up by the BIOS, and thus we can't get the mode at module
1608 * load.
1609 */
1610 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1611 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1612 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1613 }
045ac3b5
JB		 1614}
1615
34eb7579 1616static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1617{
34eb7579 1618 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1619}
1620
2b28bb1b
RV		 1621static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1622{
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1624
18b5992c 1625 if (!HAS_PSR(dev))
2b28bb1b
RV		 1626 return false;
1627
18b5992c 1628 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1629}
1630
1631static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1632 struct edp_vsc_psr *vsc_psr)
1633{
1634 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1635 struct drm_device *dev = dig_port->base.base.dev;
1636 struct drm_i915_private *dev_priv = dev->dev_private;
1637 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1638 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1639 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1640 uint32_t *data = (uint32_t *) vsc_psr;
1641 unsigned int i;
1642
1643 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1644 the video DIP being updated before program video DIP data buffer
1645 registers for DIP being updated. */
1646 I915_WRITE(ctl_reg, 0);
1647 POSTING_READ(ctl_reg);
1648
1649 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1650 if (i < sizeof(struct edp_vsc_psr))
1651 I915_WRITE(data_reg + i, *data++);
1652 else
1653 I915_WRITE(data_reg + i, 0);
1654 }
1655
1656 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1657 POSTING_READ(ctl_reg);
1658}
1659
1660static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1661{
1662 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1663 struct drm_i915_private *dev_priv = dev->dev_private;
1664 struct edp_vsc_psr psr_vsc;
1665
6118efe5 1666 if (dev_priv->psr.setup_done)
2b28bb1b
RV		 1667 return;
1668
1669 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1670 memset(&psr_vsc, 0, sizeof(psr_vsc));
1671 psr_vsc.sdp_header.HB0 = 0;
1672 psr_vsc.sdp_header.HB1 = 0x7;
1673 psr_vsc.sdp_header.HB2 = 0x2;
1674 psr_vsc.sdp_header.HB3 = 0x8;
1675 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1676
1677 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1678 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1679 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b 1680
6118efe5 1681 dev_priv->psr.setup_done = true;
2b28bb1b
RV		 1682}
1683
1684static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1685{
0e0ae652
RV		 1686 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1687 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 1688 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1689 uint32_t aux_clock_divider;
2b28bb1b
RV		 1690 int precharge = 0x3;
1691 int msg_size = 5; /* Header(4) + Message(1) */
0e0ae652 1692 bool only_standby = false;
2b28bb1b 1693
ec5b01dd
DL		 1694 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1695
0e0ae652
RV		 1696 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1697 only_standby = true;
1698
2b28bb1b 1699 /* Enable PSR in sink */
0e0ae652 1700 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 1701 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1702 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1703 else
9d1a1031
JN		 1704 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1705 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1706
1707 /* Setup AUX registers */
18b5992c
BW		 1708 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1709 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1710 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1711 DP_AUX_CH_CTL_TIME_OUT_400us |
1712 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1713 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1714 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1715}
1716
1717static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1718{
0e0ae652
RV		 1719 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1720 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 1721 struct drm_i915_private *dev_priv = dev->dev_private;
1722 uint32_t max_sleep_time = 0x1f;
1723 uint32_t idle_frames = 1;
1724 uint32_t val = 0x0;
ed8546ac 1725 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 1726 bool only_standby = false;
1727
1728 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1729 only_standby = true;
2b28bb1b 1730
0e0ae652 1731 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 1732 val |= EDP_PSR_LINK_STANDBY;
1733 val |= EDP_PSR_TP2_TP3_TIME_0us;
1734 val |= EDP_PSR_TP1_TIME_0us;
1735 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 1736 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 1737 } else
1738 val |= EDP_PSR_LINK_DISABLE;
1739
18b5992c 1740 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1741 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1742 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1743 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1744 EDP_PSR_ENABLE);
1745}
1746
3f51e471
RV		 1747static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1748{
1749 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1750 struct drm_device *dev = dig_port->base.base.dev;
1751 struct drm_i915_private *dev_priv = dev->dev_private;
1752 struct drm_crtc *crtc = dig_port->base.base.crtc;
1753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
f4510a27 1754 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
3f51e471
RV		 1755 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1756
a031d709
RV		 1757 dev_priv->psr.source_ok = false;
1758
0e0ae652
RV		 1759 if (!HAS_PSR(dev)) {
1760 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1761 return false;
1762 }
1763
1764 if (IS_HASWELL(dev) && (intel_encoder->type != INTEL_OUTPUT_EDP ||
1765 dig_port->port != PORT_A)) {
3f51e471 1766 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1767 return false;
1768 }
1769
d330a953 1770 if (!i915.enable_psr) {
105b7c11 1771 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1772 return false;
1773 }
1774
cd234b0b
CW		 1775 crtc = dig_port->base.base.crtc;
1776 if (crtc == NULL) {
1777 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1778 return false;
1779 }
1780
1781 intel_crtc = to_intel_crtc(crtc);
20ddf665 1782 if (!intel_crtc_active(crtc)) {
3f51e471 1783 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1784 return false;
1785 }
1786
f4510a27 1787 obj = to_intel_framebuffer(crtc->primary->fb)->obj;
3f51e471
RV		 1788 if (obj->tiling_mode != I915_TILING_X ||
1789 obj->fence_reg == I915_FENCE_REG_NONE) {
1790 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1791 return false;
1792 }
1793
4c8c7000
RV		 1794 /* Below limitations aren't valid for Broadwell */
1795 if (IS_BROADWELL(dev))
1796 goto out;
1797
3f51e471
RV		 1798 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1799 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1800 return false;
1801 }
1802
1803 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1804 S3D_ENABLE) {
1805 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1806 return false;
1807 }
1808
ca73b4f0 1809 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1810 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1811 return false;
1812 }
1813
4c8c7000 1814 out:
a031d709 1815 dev_priv->psr.source_ok = true;
3f51e471
RV		 1816 return true;
1817}
1818
3d739d92 1819static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 1820{
7c8f8a70
RV		 1821 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1822 struct drm_device *dev = intel_dig_port->base.base.dev;
1823 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 1824
7c8f8a70 1825 if (intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1826 return;
1827
2b28bb1b
RV		 1828 /* Enable PSR on the panel */
1829 intel_edp_psr_enable_sink(intel_dp);
1830
1831 /* Enable PSR on the host */
1832 intel_edp_psr_enable_source(intel_dp);
7c8f8a70
RV		 1833
1834 dev_priv->psr.enabled = true;
1835 dev_priv->psr.active = true;
2b28bb1b
RV		 1836}
1837
3d739d92
RV		 1838void intel_edp_psr_enable(struct intel_dp *intel_dp)
1839{
1840 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1841
4704c573
RV		 1842 if (!HAS_PSR(dev)) {
1843 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1844 return;
1845 }
1846
34eb7579
RV		 1847 if (!is_edp_psr(intel_dp)) {
1848 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1849 return;
1850 }
1851
16487254
RV		 1852 /* Setup PSR once */
1853 intel_edp_psr_setup(intel_dp);
1854
7c8f8a70 1855 if (intel_edp_psr_match_conditions(intel_dp))
3d739d92
RV		 1856 intel_edp_psr_do_enable(intel_dp);
1857}
1858
2b28bb1b
RV		 1859void intel_edp_psr_disable(struct intel_dp *intel_dp)
1860{
1861 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1862 struct drm_i915_private *dev_priv = dev->dev_private;
1863
7c8f8a70 1864 if (!dev_priv->psr.enabled)
2b28bb1b
RV		 1865 return;
1866
18b5992c
BW		 1867 I915_WRITE(EDP_PSR_CTL(dev),
1868 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1869
1870 /* Wait till PSR is idle */
18b5992c 1871 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1872 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1873 DRM_ERROR("Timed out waiting for PSR Idle State\n");
7c8f8a70
RV		 1874
1875 dev_priv->psr.enabled = false;
2b28bb1b
RV		 1876}
1877
3d739d92
RV		 1878void intel_edp_psr_update(struct drm_device *dev)
1879{
16487254 1880 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 1881
4704c573
RV		 1882 if (!HAS_PSR(dev))
1883 return;
1884
16487254
RV		 1885 if (!dev_priv->psr.setup_done)
1886 return;
1887
7c8f8a70
RV		 1888 intel_edp_psr_exit(dev, true);
1889}
1890
f02a326e 1891static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 1892{
1893 struct drm_i915_private *dev_priv =
1894 container_of(work, typeof(*dev_priv), psr.work.work);
1895 struct drm_device *dev = dev_priv->dev;
1896 struct intel_encoder *encoder;
1897 struct intel_dp *intel_dp = NULL;
1898
3d739d92
RV		 1899 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1900 if (encoder->type == INTEL_OUTPUT_EDP) {
1901 intel_dp = enc_to_intel_dp(&encoder->base);
1902
3d739d92
RV		 1903 if (!intel_edp_psr_match_conditions(intel_dp))
1904 intel_edp_psr_disable(intel_dp);
1905 else
7c8f8a70 1906 intel_edp_psr_do_enable(intel_dp);
3d739d92
RV		 1907 }
1908}
1909
f02a326e 1910static void intel_edp_psr_inactivate(struct drm_device *dev)
7c8f8a70
RV		 1911{
1912 struct drm_i915_private *dev_priv = dev->dev_private;
1913 struct intel_connector *connector;
1914 struct intel_encoder *encoder;
1915 struct intel_crtc *intel_crtc;
1916 struct intel_dp *intel_dp = NULL;
1917
1918 list_for_each_entry(connector, &dev->mode_config.connector_list,
1919 base.head) {
1920
1921 if (connector->base.dpms != DRM_MODE_DPMS_ON)
1922 continue;
1923
1924 encoder = to_intel_encoder(connector->base.encoder);
1925 if (encoder->type == INTEL_OUTPUT_EDP) {
1926
1927 intel_dp = enc_to_intel_dp(&encoder->base);
1928 intel_crtc = to_intel_crtc(encoder->base.crtc);
1929
1930 dev_priv->psr.active = false;
1931
1932 I915_WRITE(EDP_PSR_CTL(dev), I915_READ(EDP_PSR_CTL(dev))
1933 & ~EDP_PSR_ENABLE);
1934 }
1935 }
1936}
1937
1938void intel_edp_psr_exit(struct drm_device *dev, bool schedule_back)
1939{
1940 struct drm_i915_private *dev_priv = dev->dev_private;
1941
1942 if (!HAS_PSR(dev))
1943 return;
1944
1945 if (!dev_priv->psr.setup_done)
1946 return;
1947
1948 cancel_delayed_work_sync(&dev_priv->psr.work);
1949
1950 if (dev_priv->psr.active)
1951 intel_edp_psr_inactivate(dev);
1952
1953 if (schedule_back)
1954 schedule_delayed_work(&dev_priv->psr.work,
1955 msecs_to_jiffies(100));
1956}
1957
1958void intel_edp_psr_init(struct drm_device *dev)
1959{
1960 struct drm_i915_private *dev_priv = dev->dev_private;
1961
1962 if (!HAS_PSR(dev))
1963 return;
1964
1965 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
1966}
1967
e8cb4558 1968static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1969{
e8cb4558 1970 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1971 enum port port = dp_to_dig_port(intel_dp)->port;
1972 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1973
1974 /* Make sure the panel is off before trying to change the mode. But also
1975 * ensure that we have vdd while we switch off the panel. */
24f3e092 1976 intel_edp_panel_vdd_on(intel_dp);
4be73780 1977 intel_edp_backlight_off(intel_dp);
fdbc3b1f 1978 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 1979 intel_edp_panel_off(intel_dp);
3739850b
DV		 1980
1981 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1982 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1983 intel_dp_link_down(intel_dp);
d240f20f
JB		 1984}
1985
49277c31 1986static void g4x_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1987{
2bd2ad64 1988 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1989 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 1990
49277c31
VS		 1991 if (port != PORT_A)
1992 return;
1993
1994 intel_dp_link_down(intel_dp);
1995 ironlake_edp_pll_off(intel_dp);
1996}
1997
1998static void vlv_post_disable_dp(struct intel_encoder *encoder)
1999{
2000 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2001
2002 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2003}
2004
580d3811
VS		 2005static void chv_post_disable_dp(struct intel_encoder *encoder)
2006{
2007 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2008 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2009 struct drm_device *dev = encoder->base.dev;
2010 struct drm_i915_private *dev_priv = dev->dev_private;
2011 struct intel_crtc *intel_crtc =
2012 to_intel_crtc(encoder->base.crtc);
2013 enum dpio_channel ch = vlv_dport_to_channel(dport);
2014 enum pipe pipe = intel_crtc->pipe;
2015 u32 val;
2016
2017 intel_dp_link_down(intel_dp);
2018
2019 mutex_lock(&dev_priv->dpio_lock);
2020
2021 /* Propagate soft reset to data lane reset */
97fd4d5c 2022 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2023 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2024 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2025
97fd4d5c
VS		 2026 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2027 val |= CHV_PCS_REQ_SOFTRESET_EN;
2028 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2029
2030 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2031 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2032 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2033
2034 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2035 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2036 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2037
2038 mutex_unlock(&dev_priv->dpio_lock);
2039}
2040
e8cb4558 2041static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2042{
e8cb4558
DV		 2043 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2044 struct drm_device *dev = encoder->base.dev;
2045 struct drm_i915_private *dev_priv = dev->dev_private;
2046 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2047
0c33d8d7
DV		 2048 if (WARN_ON(dp_reg & DP_PORT_EN))
2049 return;
5d613501 2050
24f3e092 2051 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 2052 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2053 intel_dp_start_link_train(intel_dp);
4be73780
DV		 2054 intel_edp_panel_on(intel_dp);
2055 edp_panel_vdd_off(intel_dp, true);
33a34e4e 2056 intel_dp_complete_link_train(intel_dp);
3ab9c637 2057 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2058}
89b667f8 2059
ecff4f3b
JN		 2060static void g4x_enable_dp(struct intel_encoder *encoder)
2061{
828f5c6e
JN		 2062 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2063
ecff4f3b 2064 intel_enable_dp(encoder);
4be73780 2065 intel_edp_backlight_on(intel_dp);
ab1f90f9 2066}
89b667f8 2067
ab1f90f9
JN		 2068static void vlv_enable_dp(struct intel_encoder *encoder)
2069{
828f5c6e
JN		 2070 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2071
4be73780 2072 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2073}
2074
ecff4f3b 2075static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2076{
2077 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2078 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2079
8ac33ed3
DV		 2080 intel_dp_prepare(encoder);
2081
d41f1efb
DV		 2082 /* Only ilk+ has port A */
2083 if (dport->port == PORT_A) {
2084 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2085 ironlake_edp_pll_on(intel_dp);
d41f1efb 2086 }
ab1f90f9
JN		 2087}
2088
2089static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2090{
2bd2ad64 2091 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2092 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2093 struct drm_device *dev = encoder->base.dev;
89b667f8 2094 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2095 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2096 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 2097 int pipe = intel_crtc->pipe;
bf13e81b 2098 struct edp_power_seq power_seq;
ab1f90f9 2099 u32 val;
a4fc5ed6 2100
ab1f90f9 2101 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2102
ab3c759a 2103 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2104 val = 0;
2105 if (pipe)
2106 val |= (1<<21);
2107 else
2108 val &= ~(1<<21);
2109 val |= 0x001000c4;
ab3c759a
CML		 2110 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2111 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2112 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2113
ab1f90f9
JN		 2114 mutex_unlock(&dev_priv->dpio_lock);
2115
2cac613b
ID		 2116 if (is_edp(intel_dp)) {
2117 /* init power sequencer on this pipe and port */
2118 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2119 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2120 &power_seq);
2121 }
bf13e81b 2122
ab1f90f9
JN		 2123 intel_enable_dp(encoder);
2124
e4607fcf 2125 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2126}
2127
ecff4f3b 2128static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2129{
2130 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2131 struct drm_device *dev = encoder->base.dev;
2132 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2133 struct intel_crtc *intel_crtc =
2134 to_intel_crtc(encoder->base.crtc);
e4607fcf 2135 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2136 int pipe = intel_crtc->pipe;
89b667f8 2137
8ac33ed3
DV		 2138 intel_dp_prepare(encoder);
2139
89b667f8 2140 /* Program Tx lane resets to default */
0980a60f 2141 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2142 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2143 DPIO_PCS_TX_LANE2_RESET |
2144 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2145 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2146 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2147 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2148 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2149 DPIO_PCS_CLK_SOFT_RESET);
2150
2151 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2152 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2153 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2154 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2155 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2156}
2157
e4a1d846
CML		 2158static void chv_pre_enable_dp(struct intel_encoder *encoder)
2159{
2160 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2161 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2162 struct drm_device *dev = encoder->base.dev;
2163 struct drm_i915_private *dev_priv = dev->dev_private;
2164 struct edp_power_seq power_seq;
2165 struct intel_crtc *intel_crtc =
2166 to_intel_crtc(encoder->base.crtc);
2167 enum dpio_channel ch = vlv_dport_to_channel(dport);
2168 int pipe = intel_crtc->pipe;
2169 int data, i;
949c1d43 2170 u32 val;
e4a1d846 2171
e4a1d846 2172 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2173
2174 /* Deassert soft data lane reset*/
97fd4d5c 2175 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2176 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2177 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2178
2179 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2180 val |= CHV_PCS_REQ_SOFTRESET_EN;
2181 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2182
2183 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2184 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2185 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2186
97fd4d5c 2187 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2188 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2189 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2190
2191 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2192 for (i = 0; i < 4; i++) {
2193 /* Set the latency optimal bit */
2194 data = (i == 1) ? 0x0 : 0x6;
2195 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2196 data << DPIO_FRC_LATENCY_SHFIT);
2197
2198 /* Set the upar bit */
2199 data = (i == 1) ? 0x0 : 0x1;
2200 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2201 data << DPIO_UPAR_SHIFT);
2202 }
2203
2204 /* Data lane stagger programming */
2205 /* FIXME: Fix up value only after power analysis */
2206
2207 mutex_unlock(&dev_priv->dpio_lock);
2208
2209 if (is_edp(intel_dp)) {
2210 /* init power sequencer on this pipe and port */
2211 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2212 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2213 &power_seq);
2214 }
2215
2216 intel_enable_dp(encoder);
2217
2218 vlv_wait_port_ready(dev_priv, dport);
2219}
2220
9197c88b
VS		 2221static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2222{
2223 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2224 struct drm_device *dev = encoder->base.dev;
2225 struct drm_i915_private *dev_priv = dev->dev_private;
2226 struct intel_crtc *intel_crtc =
2227 to_intel_crtc(encoder->base.crtc);
2228 enum dpio_channel ch = vlv_dport_to_channel(dport);
2229 enum pipe pipe = intel_crtc->pipe;
2230 u32 val;
2231
2232 mutex_lock(&dev_priv->dpio_lock);
2233
b9e5ac3c
VS		 2234 /* program left/right clock distribution */
2235 if (pipe != PIPE_B) {
2236 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2237 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2238 if (ch == DPIO_CH0)
2239 val |= CHV_BUFLEFTENA1_FORCE;
2240 if (ch == DPIO_CH1)
2241 val |= CHV_BUFRIGHTENA1_FORCE;
2242 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2243 } else {
2244 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2245 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2246 if (ch == DPIO_CH0)
2247 val |= CHV_BUFLEFTENA2_FORCE;
2248 if (ch == DPIO_CH1)
2249 val |= CHV_BUFRIGHTENA2_FORCE;
2250 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2251 }
2252
9197c88b
VS		 2253 /* program clock channel usage */
2254 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2255 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2256 if (pipe != PIPE_B)
2257 val &= ~CHV_PCS_USEDCLKCHANNEL;
2258 else
2259 val |= CHV_PCS_USEDCLKCHANNEL;
2260 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2261
2262 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2263 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2264 if (pipe != PIPE_B)
2265 val &= ~CHV_PCS_USEDCLKCHANNEL;
2266 else
2267 val |= CHV_PCS_USEDCLKCHANNEL;
2268 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2269
2270 /*
2271 * This a a bit weird since generally CL
2272 * matches the pipe, but here we need to
2273 * pick the CL based on the port.
2274 */
2275 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2276 if (pipe != PIPE_B)
2277 val &= ~CHV_CMN_USEDCLKCHANNEL;
2278 else
2279 val |= CHV_CMN_USEDCLKCHANNEL;
2280 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2281
2282 mutex_unlock(&dev_priv->dpio_lock);
2283}
2284
a4fc5ed6 2285/*
df0c237d
JB		 2286 * Native read with retry for link status and receiver capability reads for
2287 * cases where the sink may still be asleep.
9d1a1031
JN		 2288 *
2289 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2290 * supposed to retry 3 times per the spec.
a4fc5ed6 2291 */
9d1a1031
JN		 2292static ssize_t
2293intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2294 void *buffer, size_t size)
a4fc5ed6 2295{
9d1a1031
JN		 2296 ssize_t ret;
2297 int i;
61da5fab 2298
61da5fab 2299 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2300 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2301 if (ret == size)
2302 return ret;
61da5fab
JB		 2303 msleep(1);
2304 }
a4fc5ed6 2305
9d1a1031 2306 return ret;
a4fc5ed6
KP		 2307}
2308
2309/*
2310 * Fetch AUX CH registers 0x202 - 0x207 which contain
2311 * link status information
2312 */
2313static bool
93f62dad 2314intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2315{
9d1a1031
JN		 2316 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2317 DP_LANE0_1_STATUS,
2318 link_status,
2319 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2320}
2321
1100244e 2322/* These are source-specific values. */
a4fc5ed6 2323static uint8_t
1a2eb460 2324intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2325{
30add22d 2326 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2327 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2328
9576c27f 2329 if (IS_VALLEYVIEW(dev))
e2fa6fba 2330 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 2331 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 2332 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 2333 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 2334 return DP_TRAIN_VOLTAGE_SWING_1200;
2335 else
2336 return DP_TRAIN_VOLTAGE_SWING_800;
2337}
2338
2339static uint8_t
2340intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2341{
30add22d 2342 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2343 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2344
9576c27f 2345 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722
PZ		 2346 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2347 case DP_TRAIN_VOLTAGE_SWING_400:
2348 return DP_TRAIN_PRE_EMPHASIS_9_5;
2349 case DP_TRAIN_VOLTAGE_SWING_600:
2350 return DP_TRAIN_PRE_EMPHASIS_6;
2351 case DP_TRAIN_VOLTAGE_SWING_800:
2352 return DP_TRAIN_PRE_EMPHASIS_3_5;
2353 case DP_TRAIN_VOLTAGE_SWING_1200:
2354 default:
2355 return DP_TRAIN_PRE_EMPHASIS_0;
2356 }
e2fa6fba
P		 2357 } else if (IS_VALLEYVIEW(dev)) {
2358 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2359 case DP_TRAIN_VOLTAGE_SWING_400:
2360 return DP_TRAIN_PRE_EMPHASIS_9_5;
2361 case DP_TRAIN_VOLTAGE_SWING_600:
2362 return DP_TRAIN_PRE_EMPHASIS_6;
2363 case DP_TRAIN_VOLTAGE_SWING_800:
2364 return DP_TRAIN_PRE_EMPHASIS_3_5;
2365 case DP_TRAIN_VOLTAGE_SWING_1200:
2366 default:
2367 return DP_TRAIN_PRE_EMPHASIS_0;
2368 }
bc7d38a4 2369 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2370 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2371 case DP_TRAIN_VOLTAGE_SWING_400:
2372 return DP_TRAIN_PRE_EMPHASIS_6;
2373 case DP_TRAIN_VOLTAGE_SWING_600:
2374 case DP_TRAIN_VOLTAGE_SWING_800:
2375 return DP_TRAIN_PRE_EMPHASIS_3_5;
2376 default:
2377 return DP_TRAIN_PRE_EMPHASIS_0;
2378 }
2379 } else {
2380 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2381 case DP_TRAIN_VOLTAGE_SWING_400:
2382 return DP_TRAIN_PRE_EMPHASIS_6;
2383 case DP_TRAIN_VOLTAGE_SWING_600:
2384 return DP_TRAIN_PRE_EMPHASIS_6;
2385 case DP_TRAIN_VOLTAGE_SWING_800:
2386 return DP_TRAIN_PRE_EMPHASIS_3_5;
2387 case DP_TRAIN_VOLTAGE_SWING_1200:
2388 default:
2389 return DP_TRAIN_PRE_EMPHASIS_0;
2390 }
a4fc5ed6
KP		 2391 }
2392}
2393
e2fa6fba
P		 2394static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2395{
2396 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2397 struct drm_i915_private *dev_priv = dev->dev_private;
2398 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2399 struct intel_crtc *intel_crtc =
2400 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2401 unsigned long demph_reg_value, preemph_reg_value,
2402 uniqtranscale_reg_value;
2403 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2404 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2405 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2406
2407 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2408 case DP_TRAIN_PRE_EMPHASIS_0:
2409 preemph_reg_value = 0x0004000;
2410 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2411 case DP_TRAIN_VOLTAGE_SWING_400:
2412 demph_reg_value = 0x2B405555;
2413 uniqtranscale_reg_value = 0x552AB83A;
2414 break;
2415 case DP_TRAIN_VOLTAGE_SWING_600:
2416 demph_reg_value = 0x2B404040;
2417 uniqtranscale_reg_value = 0x5548B83A;
2418 break;
2419 case DP_TRAIN_VOLTAGE_SWING_800:
2420 demph_reg_value = 0x2B245555;
2421 uniqtranscale_reg_value = 0x5560B83A;
2422 break;
2423 case DP_TRAIN_VOLTAGE_SWING_1200:
2424 demph_reg_value = 0x2B405555;
2425 uniqtranscale_reg_value = 0x5598DA3A;
2426 break;
2427 default:
2428 return 0;
2429 }
2430 break;
2431 case DP_TRAIN_PRE_EMPHASIS_3_5:
2432 preemph_reg_value = 0x0002000;
2433 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2434 case DP_TRAIN_VOLTAGE_SWING_400:
2435 demph_reg_value = 0x2B404040;
2436 uniqtranscale_reg_value = 0x5552B83A;
2437 break;
2438 case DP_TRAIN_VOLTAGE_SWING_600:
2439 demph_reg_value = 0x2B404848;
2440 uniqtranscale_reg_value = 0x5580B83A;
2441 break;
2442 case DP_TRAIN_VOLTAGE_SWING_800:
2443 demph_reg_value = 0x2B404040;
2444 uniqtranscale_reg_value = 0x55ADDA3A;
2445 break;
2446 default:
2447 return 0;
2448 }
2449 break;
2450 case DP_TRAIN_PRE_EMPHASIS_6:
2451 preemph_reg_value = 0x0000000;
2452 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2453 case DP_TRAIN_VOLTAGE_SWING_400:
2454 demph_reg_value = 0x2B305555;
2455 uniqtranscale_reg_value = 0x5570B83A;
2456 break;
2457 case DP_TRAIN_VOLTAGE_SWING_600:
2458 demph_reg_value = 0x2B2B4040;
2459 uniqtranscale_reg_value = 0x55ADDA3A;
2460 break;
2461 default:
2462 return 0;
2463 }
2464 break;
2465 case DP_TRAIN_PRE_EMPHASIS_9_5:
2466 preemph_reg_value = 0x0006000;
2467 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2468 case DP_TRAIN_VOLTAGE_SWING_400:
2469 demph_reg_value = 0x1B405555;
2470 uniqtranscale_reg_value = 0x55ADDA3A;
2471 break;
2472 default:
2473 return 0;
2474 }
2475 break;
2476 default:
2477 return 0;
2478 }
2479
0980a60f 2480 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2481 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2482 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2483 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2484 uniqtranscale_reg_value);
ab3c759a
CML		 2485 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2486 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2487 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2488 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2489 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2490
2491 return 0;
2492}
2493
e4a1d846
CML		 2494static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2495{
2496 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2497 struct drm_i915_private *dev_priv = dev->dev_private;
2498 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2499 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 2500 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 2501 uint8_t train_set = intel_dp->train_set[0];
2502 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 2503 enum pipe pipe = intel_crtc->pipe;
2504 int i;
e4a1d846
CML		 2505
2506 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2507 case DP_TRAIN_PRE_EMPHASIS_0:
2508 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2509 case DP_TRAIN_VOLTAGE_SWING_400:
2510 deemph_reg_value = 128;
2511 margin_reg_value = 52;
2512 break;
2513 case DP_TRAIN_VOLTAGE_SWING_600:
2514 deemph_reg_value = 128;
2515 margin_reg_value = 77;
2516 break;
2517 case DP_TRAIN_VOLTAGE_SWING_800:
2518 deemph_reg_value = 128;
2519 margin_reg_value = 102;
2520 break;
2521 case DP_TRAIN_VOLTAGE_SWING_1200:
2522 deemph_reg_value = 128;
2523 margin_reg_value = 154;
2524 /* FIXME extra to set for 1200 */
2525 break;
2526 default:
2527 return 0;
2528 }
2529 break;
2530 case DP_TRAIN_PRE_EMPHASIS_3_5:
2531 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2532 case DP_TRAIN_VOLTAGE_SWING_400:
2533 deemph_reg_value = 85;
2534 margin_reg_value = 78;
2535 break;
2536 case DP_TRAIN_VOLTAGE_SWING_600:
2537 deemph_reg_value = 85;
2538 margin_reg_value = 116;
2539 break;
2540 case DP_TRAIN_VOLTAGE_SWING_800:
2541 deemph_reg_value = 85;
2542 margin_reg_value = 154;
2543 break;
2544 default:
2545 return 0;
2546 }
2547 break;
2548 case DP_TRAIN_PRE_EMPHASIS_6:
2549 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2550 case DP_TRAIN_VOLTAGE_SWING_400:
2551 deemph_reg_value = 64;
2552 margin_reg_value = 104;
2553 break;
2554 case DP_TRAIN_VOLTAGE_SWING_600:
2555 deemph_reg_value = 64;
2556 margin_reg_value = 154;
2557 break;
2558 default:
2559 return 0;
2560 }
2561 break;
2562 case DP_TRAIN_PRE_EMPHASIS_9_5:
2563 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2564 case DP_TRAIN_VOLTAGE_SWING_400:
2565 deemph_reg_value = 43;
2566 margin_reg_value = 154;
2567 break;
2568 default:
2569 return 0;
2570 }
2571 break;
2572 default:
2573 return 0;
2574 }
2575
2576 mutex_lock(&dev_priv->dpio_lock);
2577
2578 /* Clear calc init */
1966e59e
VS		 2579 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2580 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2581 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2582
2583 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2584 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2585 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2586
2587 /* Program swing deemph */
f72df8db
VS		 2588 for (i = 0; i < 4; i++) {
2589 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2590 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2591 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2592 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2593 }
e4a1d846
CML		 2594
2595 /* Program swing margin */
f72df8db
VS		 2596 for (i = 0; i < 4; i++) {
2597 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2598 val &= ~DPIO_SWING_MARGIN_MASK;
2599 val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
2600 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2601 }
e4a1d846
CML		 2602
2603 /* Disable unique transition scale */
f72df8db
VS		 2604 for (i = 0; i < 4; i++) {
2605 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2606 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2607 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2608 }
e4a1d846
CML		 2609
2610 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2611 == DP_TRAIN_PRE_EMPHASIS_0) &&
2612 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2613 == DP_TRAIN_VOLTAGE_SWING_1200)) {
2614
2615 /*
2616 * The document said it needs to set bit 27 for ch0 and bit 26
2617 * for ch1. Might be a typo in the doc.
2618 * For now, for this unique transition scale selection, set bit
2619 * 27 for ch0 and ch1.
2620 */
f72df8db
VS		 2621 for (i = 0; i < 4; i++) {
2622 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2623 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2624 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2625 }
e4a1d846 2626
f72df8db
VS		 2627 for (i = 0; i < 4; i++) {
2628 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2629 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2630 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2631 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2632 }
e4a1d846
CML		 2633 }
2634
2635 /* Start swing calculation */
1966e59e
VS		 2636 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2637 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2638 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2639
2640 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2641 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2642 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2643
2644 /* LRC Bypass */
2645 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2646 val |= DPIO_LRC_BYPASS;
2647 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2648
2649 mutex_unlock(&dev_priv->dpio_lock);
2650
2651 return 0;
2652}
2653
a4fc5ed6 2654static void
0301b3ac
JN		 2655intel_get_adjust_train(struct intel_dp *intel_dp,
2656 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2657{
2658 uint8_t v = 0;
2659 uint8_t p = 0;
2660 int lane;
1a2eb460
KP		 2661 uint8_t voltage_max;
2662 uint8_t preemph_max;
a4fc5ed6 2663
33a34e4e 2664 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2665 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2666 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2667
2668 if (this_v > v)
2669 v = this_v;
2670 if (this_p > p)
2671 p = this_p;
2672 }
2673
1a2eb460 2674 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2675 if (v >= voltage_max)
2676 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2677
1a2eb460
KP		 2678 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2679 if (p >= preemph_max)
2680 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2681
2682 for (lane = 0; lane < 4; lane++)
33a34e4e 2683 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2684}
2685
2686static uint32_t
f0a3424e 2687intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2688{
3cf2efb1 2689 uint32_t signal_levels = 0;
a4fc5ed6 2690
3cf2efb1 2691 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2692 case DP_TRAIN_VOLTAGE_SWING_400:
2693 default:
2694 signal_levels |= DP_VOLTAGE_0_4;
2695 break;
2696 case DP_TRAIN_VOLTAGE_SWING_600:
2697 signal_levels |= DP_VOLTAGE_0_6;
2698 break;
2699 case DP_TRAIN_VOLTAGE_SWING_800:
2700 signal_levels |= DP_VOLTAGE_0_8;
2701 break;
2702 case DP_TRAIN_VOLTAGE_SWING_1200:
2703 signal_levels |= DP_VOLTAGE_1_2;
2704 break;
2705 }
3cf2efb1 2706 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2707 case DP_TRAIN_PRE_EMPHASIS_0:
2708 default:
2709 signal_levels |= DP_PRE_EMPHASIS_0;
2710 break;
2711 case DP_TRAIN_PRE_EMPHASIS_3_5:
2712 signal_levels |= DP_PRE_EMPHASIS_3_5;
2713 break;
2714 case DP_TRAIN_PRE_EMPHASIS_6:
2715 signal_levels |= DP_PRE_EMPHASIS_6;
2716 break;
2717 case DP_TRAIN_PRE_EMPHASIS_9_5:
2718 signal_levels |= DP_PRE_EMPHASIS_9_5;
2719 break;
2720 }
2721 return signal_levels;
2722}
2723
e3421a18
ZW		 2724/* Gen6's DP voltage swing and pre-emphasis control */
2725static uint32_t
2726intel_gen6_edp_signal_levels(uint8_t train_set)
2727{
3c5a62b5
YL		 2728 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2729 DP_TRAIN_PRE_EMPHASIS_MASK);
2730 switch (signal_levels) {
e3421a18 2731 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2732 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2733 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2734 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2735 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2736 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2737 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2738 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2739 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2740 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2741 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2742 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2743 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2744 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2745 default:
3c5a62b5
YL		 2746 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2747 "0x%x\n", signal_levels);
2748 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2749 }
2750}
2751
1a2eb460
KP		 2752/* Gen7's DP voltage swing and pre-emphasis control */
2753static uint32_t
2754intel_gen7_edp_signal_levels(uint8_t train_set)
2755{
2756 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2757 DP_TRAIN_PRE_EMPHASIS_MASK);
2758 switch (signal_levels) {
2759 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2760 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2761 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2762 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2763 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2764 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2765
2766 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2767 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2768 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2769 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2770
2771 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2772 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2773 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2774 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2775
2776 default:
2777 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2778 "0x%x\n", signal_levels);
2779 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2780 }
2781}
2782
d6c0d722
PZ		 2783/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2784static uint32_t
f0a3424e 2785intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2786{
d6c0d722
PZ		 2787 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2788 DP_TRAIN_PRE_EMPHASIS_MASK);
2789 switch (signal_levels) {
2790 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2791 return DDI_BUF_EMP_400MV_0DB_HSW;
2792 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2793 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2794 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2795 return DDI_BUF_EMP_400MV_6DB_HSW;
2796 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2797 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2798
d6c0d722
PZ		 2799 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2800 return DDI_BUF_EMP_600MV_0DB_HSW;
2801 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2802 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2803 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2804 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2805
d6c0d722
PZ		 2806 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2807 return DDI_BUF_EMP_800MV_0DB_HSW;
2808 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2809 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2810 default:
2811 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2812 "0x%x\n", signal_levels);
2813 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2814 }
a4fc5ed6
KP		 2815}
2816
f0a3424e
PZ		 2817/* Properly updates "DP" with the correct signal levels. */
2818static void
2819intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2820{
2821 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2822 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2823 struct drm_device *dev = intel_dig_port->base.base.dev;
2824 uint32_t signal_levels, mask;
2825 uint8_t train_set = intel_dp->train_set[0];
2826
9576c27f 2827 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
f0a3424e
PZ		 2828 signal_levels = intel_hsw_signal_levels(train_set);
2829 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 2830 } else if (IS_CHERRYVIEW(dev)) {
2831 signal_levels = intel_chv_signal_levels(intel_dp);
2832 mask = 0;
e2fa6fba
P		 2833 } else if (IS_VALLEYVIEW(dev)) {
2834 signal_levels = intel_vlv_signal_levels(intel_dp);
2835 mask = 0;
bc7d38a4 2836 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2837 signal_levels = intel_gen7_edp_signal_levels(train_set);
2838 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2839 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2840 signal_levels = intel_gen6_edp_signal_levels(train_set);
2841 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2842 } else {
2843 signal_levels = intel_gen4_signal_levels(train_set);
2844 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2845 }
2846
2847 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2848
2849 *DP = (*DP & ~mask) | signal_levels;
2850}
2851
a4fc5ed6 2852static bool
ea5b213a 2853intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2854 uint32_t *DP,
58e10eb9 2855 uint8_t dp_train_pat)
a4fc5ed6 2856{
174edf1f
PZ		 2857 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2858 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2859 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2860 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2861 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2862 int ret, len;
a4fc5ed6 2863
22b8bf17 2864 if (HAS_DDI(dev)) {
3ab9c637 2865 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2866
2867 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2868 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2869 else
2870 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2871
2872 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2873 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2874 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2875 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2876
2877 break;
2878 case DP_TRAINING_PATTERN_1:
2879 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2880 break;
2881 case DP_TRAINING_PATTERN_2:
2882 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2883 break;
2884 case DP_TRAINING_PATTERN_3:
2885 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2886 break;
2887 }
174edf1f 2888 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2889
bc7d38a4 2890 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2891 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2892
2893 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2894 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2895 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2896 break;
2897 case DP_TRAINING_PATTERN_1:
70aff66c 2898 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2899 break;
2900 case DP_TRAINING_PATTERN_2:
70aff66c 2901 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2902 break;
2903 case DP_TRAINING_PATTERN_3:
2904 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2905 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2906 break;
2907 }
2908
2909 } else {
70aff66c 2910 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2911
2912 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2913 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2914 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2915 break;
2916 case DP_TRAINING_PATTERN_1:
70aff66c 2917 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2918 break;
2919 case DP_TRAINING_PATTERN_2:
70aff66c 2920 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2921 break;
2922 case DP_TRAINING_PATTERN_3:
2923 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2924 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2925 break;
2926 }
2927 }
2928
70aff66c 2929 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2930 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2931
2cdfe6c8
JN		 2932 buf[0] = dp_train_pat;
2933 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2934 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2935 /* don't write DP_TRAINING_LANEx_SET on disable */
2936 len = 1;
2937 } else {
2938 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2939 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2940 len = intel_dp->lane_count + 1;
47ea7542 2941 }
a4fc5ed6 2942
9d1a1031
JN		 2943 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2944 buf, len);
2cdfe6c8
JN		 2945
2946 return ret == len;
a4fc5ed6
KP		 2947}
2948
70aff66c
JN		 2949static bool
2950intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2951 uint8_t dp_train_pat)
2952{
953d22e8 2953 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2954 intel_dp_set_signal_levels(intel_dp, DP);
2955 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2956}
2957
2958static bool
2959intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2960 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2961{
2962 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2963 struct drm_device *dev = intel_dig_port->base.base.dev;
2964 struct drm_i915_private *dev_priv = dev->dev_private;
2965 int ret;
2966
2967 intel_get_adjust_train(intel_dp, link_status);
2968 intel_dp_set_signal_levels(intel_dp, DP);
2969
2970 I915_WRITE(intel_dp->output_reg, *DP);
2971 POSTING_READ(intel_dp->output_reg);
2972
9d1a1031
JN		 2973 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2974 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 2975
2976 return ret == intel_dp->lane_count;
2977}
2978
3ab9c637
ID		 2979static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2980{
2981 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2982 struct drm_device *dev = intel_dig_port->base.base.dev;
2983 struct drm_i915_private *dev_priv = dev->dev_private;
2984 enum port port = intel_dig_port->port;
2985 uint32_t val;
2986
2987 if (!HAS_DDI(dev))
2988 return;
2989
2990 val = I915_READ(DP_TP_CTL(port));
2991 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2992 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2993 I915_WRITE(DP_TP_CTL(port), val);
2994
2995 /*
2996 * On PORT_A we can have only eDP in SST mode. There the only reason
2997 * we need to set idle transmission mode is to work around a HW issue
2998 * where we enable the pipe while not in idle link-training mode.
2999 * In this case there is requirement to wait for a minimum number of
3000 * idle patterns to be sent.
3001 */
3002 if (port == PORT_A)
3003 return;
3004
3005 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3006 1))
3007 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3008}
3009
33a34e4e 3010/* Enable corresponding port and start training pattern 1 */
c19b0669 3011void
33a34e4e 3012intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3013{
da63a9f2 3014 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3015 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3016 int i;
3017 uint8_t voltage;
cdb0e95b 3018 int voltage_tries, loop_tries;
ea5b213a 3019 uint32_t DP = intel_dp->DP;
6aba5b6c 3020 uint8_t link_config[2];
a4fc5ed6 3021
affa9354 3022 if (HAS_DDI(dev))
c19b0669
PZ		 3023 intel_ddi_prepare_link_retrain(encoder);
3024
3cf2efb1 3025 /* Write the link configuration data */
6aba5b6c
JN		 3026 link_config[0] = intel_dp->link_bw;
3027 link_config[1] = intel_dp->lane_count;
3028 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3029 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3030 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3031
3032 link_config[0] = 0;
3033 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3034 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3035
3036 DP |= DP_PORT_EN;
1a2eb460 3037
70aff66c
JN		 3038 /* clock recovery */
3039 if (!intel_dp_reset_link_train(intel_dp, &DP,
3040 DP_TRAINING_PATTERN_1 |
3041 DP_LINK_SCRAMBLING_DISABLE)) {
3042 DRM_ERROR("failed to enable link training\n");
3043 return;
3044 }
3045
a4fc5ed6 3046 voltage = 0xff;
cdb0e95b
KP		 3047 voltage_tries = 0;
3048 loop_tries = 0;
a4fc5ed6 3049 for (;;) {
70aff66c 3050 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3051
a7c9655f 3052 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3053 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3054 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3055 break;
93f62dad 3056 }
a4fc5ed6 3057
01916270 3058 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3059 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3060 break;
3061 }
3062
3063 /* Check to see if we've tried the max voltage */
3064 for (i = 0; i < intel_dp->lane_count; i++)
3065 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3066 break;
3b4f819d 3067 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3068 ++loop_tries;
3069 if (loop_tries == 5) {
3def84b3 3070 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3071 break;
3072 }
70aff66c
JN		 3073 intel_dp_reset_link_train(intel_dp, &DP,
3074 DP_TRAINING_PATTERN_1 |
3075 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3076 voltage_tries = 0;
3077 continue;
3078 }
a4fc5ed6 3079
3cf2efb1 3080 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3081 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3082 ++voltage_tries;
b06fbda3 3083 if (voltage_tries == 5) {
3def84b3 3084 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3085 break;
3086 }
3087 } else
3088 voltage_tries = 0;
3089 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3090
70aff66c
JN		 3091 /* Update training set as requested by target */
3092 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3093 DRM_ERROR("failed to update link training\n");
3094 break;
3095 }
a4fc5ed6
KP		 3096 }
3097
33a34e4e
JB		 3098 intel_dp->DP = DP;
3099}
3100
c19b0669 3101void
33a34e4e
JB		 3102intel_dp_complete_link_train(struct intel_dp *intel_dp)
3103{
33a34e4e 3104 bool channel_eq = false;
37f80975 3105 int tries, cr_tries;
33a34e4e 3106 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3107 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3108
3109 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3110 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3111 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3112
a4fc5ed6 3113 /* channel equalization */
70aff66c 3114 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3115 training_pattern |
70aff66c
JN		 3116 DP_LINK_SCRAMBLING_DISABLE)) {
3117 DRM_ERROR("failed to start channel equalization\n");
3118 return;
3119 }
3120
a4fc5ed6 3121 tries = 0;
37f80975 3122 cr_tries = 0;
a4fc5ed6
KP		 3123 channel_eq = false;
3124 for (;;) {
70aff66c 3125 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3126
37f80975
JB		 3127 if (cr_tries > 5) {
3128 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3129 break;
3130 }
3131
a7c9655f 3132 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3133 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3134 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3135 break;
70aff66c 3136 }
a4fc5ed6 3137
37f80975 3138 /* Make sure clock is still ok */
01916270 3139 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3140 intel_dp_start_link_train(intel_dp);
70aff66c 3141 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3142 training_pattern |
70aff66c 3143 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3144 cr_tries++;
3145 continue;
3146 }
3147
1ffdff13 3148 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3149 channel_eq = true;
3150 break;
3151 }
a4fc5ed6 3152
37f80975
JB		 3153 /* Try 5 times, then try clock recovery if that fails */
3154 if (tries > 5) {
3155 intel_dp_link_down(intel_dp);
3156 intel_dp_start_link_train(intel_dp);
70aff66c 3157 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3158 training_pattern |
70aff66c 3159 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3160 tries = 0;
3161 cr_tries++;
3162 continue;
3163 }
a4fc5ed6 3164
70aff66c
JN		 3165 /* Update training set as requested by target */
3166 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3167 DRM_ERROR("failed to update link training\n");
3168 break;
3169 }
3cf2efb1 3170 ++tries;
869184a6 3171 }
3cf2efb1 3172
3ab9c637
ID		 3173 intel_dp_set_idle_link_train(intel_dp);
3174
3175 intel_dp->DP = DP;
3176
d6c0d722 3177 if (channel_eq)
07f42258 3178 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3179
3ab9c637
ID		 3180}
3181
3182void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3183{
70aff66c 3184 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3185 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3186}
3187
3188static void
ea5b213a 3189intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3190{
da63a9f2 3191 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3192 enum port port = intel_dig_port->port;
da63a9f2 3193 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3194 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3195 struct intel_crtc *intel_crtc =
3196 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3197 uint32_t DP = intel_dp->DP;
a4fc5ed6 3198
bc76e320 3199 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3200 return;
3201
0c33d8d7 3202 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3203 return;
3204
28c97730 3205 DRM_DEBUG_KMS("\n");
32f9d658 3206
bc7d38a4 3207 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3208 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3209 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 3210 } else {
3211 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3212 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3213 }
fe255d00 3214 POSTING_READ(intel_dp->output_reg);
5eb08b69 3215
493a7081 3216 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3217 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3218 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3219
5bddd17f
EA		 3220 /* Hardware workaround: leaving our transcoder select
3221 * set to transcoder B while it's off will prevent the
3222 * corresponding HDMI output on transcoder A.
3223 *
3224 * Combine this with another hardware workaround:
3225 * transcoder select bit can only be cleared while the
3226 * port is enabled.
3227 */
3228 DP &= ~DP_PIPEB_SELECT;
3229 I915_WRITE(intel_dp->output_reg, DP);
3230
3231 /* Changes to enable or select take place the vblank
3232 * after being written.
3233 */
ff50afe9
DV		 3234 if (WARN_ON(crtc == NULL)) {
3235 /* We should never try to disable a port without a crtc
3236 * attached. For paranoia keep the code around for a
3237 * bit. */
31acbcc4
CW		 3238 POSTING_READ(intel_dp->output_reg);
3239 msleep(50);
3240 } else
ab527efc 3241 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3242 }
3243
832afda6 3244 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3245 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3246 POSTING_READ(intel_dp->output_reg);
f01eca2e 3247 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3248}
3249
26d61aad
KP		 3250static bool
3251intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3252{
a031d709
RV		 3253 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3254 struct drm_device *dev = dig_port->base.base.dev;
3255 struct drm_i915_private *dev_priv = dev->dev_private;
3256
577c7a50
DL		 3257 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3258
9d1a1031
JN		 3259 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3260 sizeof(intel_dp->dpcd)) < 0)
edb39244 3261 return false; /* aux transfer failed */
92fd8fd1 3262
577c7a50
DL		 3263 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3264 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3265 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3266
edb39244
AJ		 3267 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3268 return false; /* DPCD not present */
3269
2293bb5c
SK		 3270 /* Check if the panel supports PSR */
3271 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3272 if (is_edp(intel_dp)) {
9d1a1031
JN		 3273 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3274 intel_dp->psr_dpcd,
3275 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3276 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3277 dev_priv->psr.sink_support = true;
50003939 3278 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3279 }
50003939
JN		 3280 }
3281
06ea66b6
TP		 3282 /* Training Pattern 3 support */
3283 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3284 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3285 intel_dp->use_tps3 = true;
3286 DRM_DEBUG_KMS("Displayport TPS3 supported");
3287 } else
3288 intel_dp->use_tps3 = false;
3289
edb39244
AJ		 3290 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3291 DP_DWN_STRM_PORT_PRESENT))
3292 return true; /* native DP sink */
3293
3294 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3295 return true; /* no per-port downstream info */
3296
9d1a1031
JN		 3297 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3298 intel_dp->downstream_ports,
3299 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3300 return false; /* downstream port status fetch failed */
3301
3302 return true;
92fd8fd1
KP		 3303}
3304
0d198328
AJ		 3305static void
3306intel_dp_probe_oui(struct intel_dp *intel_dp)
3307{
3308 u8 buf[3];
3309
3310 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3311 return;
3312
24f3e092 3313 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3314
9d1a1031 3315 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3316 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3317 buf[0], buf[1], buf[2]);
3318
9d1a1031 3319 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3320 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3321 buf[0], buf[1], buf[2]);
351cfc34 3322
4be73780 3323 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3324}
3325
d2e216d0
RV		 3326int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3327{
3328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3329 struct drm_device *dev = intel_dig_port->base.base.dev;
3330 struct intel_crtc *intel_crtc =
3331 to_intel_crtc(intel_dig_port->base.base.crtc);
3332 u8 buf[1];
3333
9d1a1031 3334 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 3335 return -EAGAIN;
3336
3337 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3338 return -ENOTTY;
3339
9d1a1031
JN		 3340 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3341 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 3342 return -EAGAIN;
3343
3344 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3345 intel_wait_for_vblank(dev, intel_crtc->pipe);
3346 intel_wait_for_vblank(dev, intel_crtc->pipe);
3347
9d1a1031 3348 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 3349 return -EAGAIN;
3350
9d1a1031 3351 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3352 return 0;
3353}
3354
a60f0e38
JB		 3355static bool
3356intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3357{
9d1a1031
JN		 3358 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3359 DP_DEVICE_SERVICE_IRQ_VECTOR,
3360 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3361}
3362
3363static void
3364intel_dp_handle_test_request(struct intel_dp *intel_dp)
3365{
3366 /* NAK by default */
9d1a1031 3367 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3368}
3369
a4fc5ed6
KP		 3370/*
3371 * According to DP spec
3372 * 5.1.2:
3373 * 1. Read DPCD
3374 * 2. Configure link according to Receiver Capabilities
3375 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3376 * 4. Check link status on receipt of hot-plug interrupt
3377 */
3378
00c09d70 3379void
ea5b213a 3380intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3381{
da63a9f2 3382 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3383 u8 sink_irq_vector;
93f62dad 3384 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3385
6e9f798d 3386 /* FIXME: This access isn't protected by any locks. */
da63a9f2 3387 if (!intel_encoder->connectors_active)
d2b996ac 3388 return;
59cd09e1 3389
da63a9f2 3390 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3391 return;
3392
92fd8fd1 3393 /* Try to read receiver status if the link appears to be up */
93f62dad 3394 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3395 return;
3396 }
3397
92fd8fd1 3398 /* Now read the DPCD to see if it's actually running */
26d61aad 3399 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3400 return;
3401 }
3402
a60f0e38
JB		 3403 /* Try to read the source of the interrupt */
3404 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3405 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3406 /* Clear interrupt source */
9d1a1031
JN		 3407 drm_dp_dpcd_writeb(&intel_dp->aux,
3408 DP_DEVICE_SERVICE_IRQ_VECTOR,
3409 sink_irq_vector);
a60f0e38
JB		 3410
3411 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3412 intel_dp_handle_test_request(intel_dp);
3413 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3414 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3415 }
3416
1ffdff13 3417 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3418 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3419 intel_encoder->base.name);
33a34e4e
JB		 3420 intel_dp_start_link_train(intel_dp);
3421 intel_dp_complete_link_train(intel_dp);
3ab9c637 3422 intel_dp_stop_link_train(intel_dp);
33a34e4e 3423 }
a4fc5ed6 3424}
a4fc5ed6 3425
caf9ab24 3426/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3427static enum drm_connector_status
26d61aad 3428intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3429{
caf9ab24 3430 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3431 uint8_t type;
3432
3433 if (!intel_dp_get_dpcd(intel_dp))
3434 return connector_status_disconnected;
3435
3436 /* if there's no downstream port, we're done */
3437 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3438 return connector_status_connected;
caf9ab24
AJ		 3439
3440 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3441 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3442 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3443 uint8_t reg;
9d1a1031
JN		 3444
3445 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3446 &reg, 1) < 0)
caf9ab24 3447 return connector_status_unknown;
9d1a1031 3448
23235177
AJ		 3449 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3450 : connector_status_disconnected;
caf9ab24
AJ		 3451 }
3452
3453 /* If no HPD, poke DDC gently */
0b99836f 3454 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3455 return connector_status_connected;
caf9ab24
AJ		 3456
3457 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3458 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3459 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3460 if (type == DP_DS_PORT_TYPE_VGA ||
3461 type == DP_DS_PORT_TYPE_NON_EDID)
3462 return connector_status_unknown;
3463 } else {
3464 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3465 DP_DWN_STRM_PORT_TYPE_MASK;
3466 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3467 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3468 return connector_status_unknown;
3469 }
caf9ab24
AJ		 3470
3471 /* Anything else is out of spec, warn and ignore */
3472 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3473 return connector_status_disconnected;
71ba9000
AJ		 3474}
3475
5eb08b69 3476static enum drm_connector_status
a9756bb5 3477ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3478{
30add22d 3479 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3480 struct drm_i915_private *dev_priv = dev->dev_private;
3481 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3482 enum drm_connector_status status;
3483
fe16d949
CW		 3484 /* Can't disconnect eDP, but you can close the lid... */
3485 if (is_edp(intel_dp)) {
30add22d 3486 status = intel_panel_detect(dev);
fe16d949
CW		 3487 if (status == connector_status_unknown)
3488 status = connector_status_connected;
3489 return status;
3490 }
01cb9ea6 3491
1b469639
DL		 3492 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3493 return connector_status_disconnected;
3494
26d61aad 3495 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3496}
3497
a4fc5ed6 3498static enum drm_connector_status
a9756bb5 3499g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3500{
30add22d 3501 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3502 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3503 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3504 uint32_t bit;
5eb08b69 3505
35aad75f
JB		 3506 /* Can't disconnect eDP, but you can close the lid... */
3507 if (is_edp(intel_dp)) {
3508 enum drm_connector_status status;
3509
3510 status = intel_panel_detect(dev);
3511 if (status == connector_status_unknown)
3512 status = connector_status_connected;
3513 return status;
3514 }
3515
232a6ee9
TP		 3516 if (IS_VALLEYVIEW(dev)) {
3517 switch (intel_dig_port->port) {
3518 case PORT_B:
3519 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3520 break;
3521 case PORT_C:
3522 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3523 break;
3524 case PORT_D:
3525 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3526 break;
3527 default:
3528 return connector_status_unknown;
3529 }
3530 } else {
3531 switch (intel_dig_port->port) {
3532 case PORT_B:
3533 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3534 break;
3535 case PORT_C:
3536 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3537 break;
3538 case PORT_D:
3539 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3540 break;
3541 default:
3542 return connector_status_unknown;
3543 }
a4fc5ed6
KP		 3544 }
3545
10f76a38 3546 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3547 return connector_status_disconnected;
3548
26d61aad 3549 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3550}
3551
8c241fef
KP		 3552static struct edid *
3553intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3554{
9cd300e0 3555 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3556
9cd300e0
JN		 3557 /* use cached edid if we have one */
3558 if (intel_connector->edid) {
9cd300e0
JN		 3559 /* invalid edid */
3560 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3561 return NULL;
3562
55e9edeb 3563 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3564 }
8c241fef 3565
9cd300e0 3566 return drm_get_edid(connector, adapter);
8c241fef
KP		 3567}
3568
3569static int
3570intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3571{
9cd300e0 3572 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3573
9cd300e0
JN		 3574 /* use cached edid if we have one */
3575 if (intel_connector->edid) {
3576 /* invalid edid */
3577 if (IS_ERR(intel_connector->edid))
3578 return 0;
3579
3580 return intel_connector_update_modes(connector,
3581 intel_connector->edid);
d6f24d0f
JB		 3582 }
3583
9cd300e0 3584 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3585}
3586
a9756bb5
ZW		 3587static enum drm_connector_status
3588intel_dp_detect(struct drm_connector *connector, bool force)
3589{
3590 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3591 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3592 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3593 struct drm_device *dev = connector->dev;
c8c8fb33 3594 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3595 enum drm_connector_status status;
671dedd2 3596 enum intel_display_power_domain power_domain;
a9756bb5
ZW		 3597 struct edid *edid = NULL;
3598
c8c8fb33
PZ		 3599 intel_runtime_pm_get(dev_priv);
3600
671dedd2
ID		 3601 power_domain = intel_display_port_power_domain(intel_encoder);
3602 intel_display_power_get(dev_priv, power_domain);
3603
164c8598 3604 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 3605 connector->base.id, connector->name);
164c8598 3606
a9756bb5
ZW		 3607 intel_dp->has_audio = false;
3608
3609 if (HAS_PCH_SPLIT(dev))
3610 status = ironlake_dp_detect(intel_dp);
3611 else
3612 status = g4x_dp_detect(intel_dp);
1b9be9d0 3613
a9756bb5 3614 if (status != connector_status_connected)
c8c8fb33 3615 goto out;
a9756bb5 3616
0d198328
AJ		 3617 intel_dp_probe_oui(intel_dp);
3618
c3e5f67b
DV		 3619 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3620 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3621 } else {
0b99836f 3622 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
f684960e
CW		 3623 if (edid) {
3624 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3625 kfree(edid);
3626 }
a9756bb5
ZW		 3627 }
3628
d63885da
PZ		 3629 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3630 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3631 status = connector_status_connected;
3632
3633out:
671dedd2
ID		 3634 intel_display_power_put(dev_priv, power_domain);
3635
c8c8fb33 3636 intel_runtime_pm_put(dev_priv);
671dedd2 3637
c8c8fb33 3638 return status;
a4fc5ed6
KP		 3639}
3640
3641static int intel_dp_get_modes(struct drm_connector *connector)
3642{
df0e9248 3643 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3644 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3645 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3646 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3647 struct drm_device *dev = connector->dev;
671dedd2
ID		 3648 struct drm_i915_private *dev_priv = dev->dev_private;
3649 enum intel_display_power_domain power_domain;
32f9d658 3650 int ret;
a4fc5ed6
KP		 3651
3652 /* We should parse the EDID data and find out if it has an audio sink
3653 */
3654
671dedd2
ID		 3655 power_domain = intel_display_port_power_domain(intel_encoder);
3656 intel_display_power_get(dev_priv, power_domain);
3657
0b99836f 3658 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
671dedd2 3659 intel_display_power_put(dev_priv, power_domain);
f8779fda 3660 if (ret)
32f9d658
ZW		 3661 return ret;
3662
f8779fda 3663 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3664 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3665 struct drm_display_mode *mode;
dd06f90e
JN		 3666 mode = drm_mode_duplicate(dev,
3667 intel_connector->panel.fixed_mode);
f8779fda 3668 if (mode) {
32f9d658
ZW		 3669 drm_mode_probed_add(connector, mode);
3670 return 1;
3671 }
3672 }
3673 return 0;
a4fc5ed6
KP		 3674}
3675
1aad7ac0
CW		 3676static bool
3677intel_dp_detect_audio(struct drm_connector *connector)
3678{
3679 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3680 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3681 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3682 struct drm_device *dev = connector->dev;
3683 struct drm_i915_private *dev_priv = dev->dev_private;
3684 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3685 struct edid *edid;
3686 bool has_audio = false;
3687
671dedd2
ID		 3688 power_domain = intel_display_port_power_domain(intel_encoder);
3689 intel_display_power_get(dev_priv, power_domain);
3690
0b99836f 3691 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
1aad7ac0
CW		 3692 if (edid) {
3693 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3694 kfree(edid);
3695 }
3696
671dedd2
ID		 3697 intel_display_power_put(dev_priv, power_domain);
3698
1aad7ac0
CW		 3699 return has_audio;
3700}
3701
f684960e
CW		 3702static int
3703intel_dp_set_property(struct drm_connector *connector,
3704 struct drm_property *property,
3705 uint64_t val)
3706{
e953fd7b 3707 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3708 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3709 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3710 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3711 int ret;
3712
662595df 3713 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3714 if (ret)
3715 return ret;
3716
3f43c48d 3717 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3718 int i = val;
3719 bool has_audio;
3720
3721 if (i == intel_dp->force_audio)
f684960e
CW		 3722 return 0;
3723
1aad7ac0 3724 intel_dp->force_audio = i;
f684960e 3725
c3e5f67b 3726 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3727 has_audio = intel_dp_detect_audio(connector);
3728 else
c3e5f67b 3729 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3730
3731 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3732 return 0;
3733
1aad7ac0 3734 intel_dp->has_audio = has_audio;
f684960e
CW		 3735 goto done;
3736 }
3737
e953fd7b 3738 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3739 bool old_auto = intel_dp->color_range_auto;
3740 uint32_t old_range = intel_dp->color_range;
3741
55bc60db
VS		 3742 switch (val) {
3743 case INTEL_BROADCAST_RGB_AUTO:
3744 intel_dp->color_range_auto = true;
3745 break;
3746 case INTEL_BROADCAST_RGB_FULL:
3747 intel_dp->color_range_auto = false;
3748 intel_dp->color_range = 0;
3749 break;
3750 case INTEL_BROADCAST_RGB_LIMITED:
3751 intel_dp->color_range_auto = false;
3752 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3753 break;
3754 default:
3755 return -EINVAL;
3756 }
ae4edb80
DV		 3757
3758 if (old_auto == intel_dp->color_range_auto &&
3759 old_range == intel_dp->color_range)
3760 return 0;
3761
e953fd7b
CW		 3762 goto done;
3763 }
3764
53b41837
YN		 3765 if (is_edp(intel_dp) &&
3766 property == connector->dev->mode_config.scaling_mode_property) {
3767 if (val == DRM_MODE_SCALE_NONE) {
3768 DRM_DEBUG_KMS("no scaling not supported\n");
3769 return -EINVAL;
3770 }
3771
3772 if (intel_connector->panel.fitting_mode == val) {
3773 /* the eDP scaling property is not changed */
3774 return 0;
3775 }
3776 intel_connector->panel.fitting_mode = val;
3777
3778 goto done;
3779 }
3780
f684960e
CW		 3781 return -EINVAL;
3782
3783done:
c0c36b94
CW		 3784 if (intel_encoder->base.crtc)
3785 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3786
3787 return 0;
3788}
3789
a4fc5ed6 3790static void
73845adf 3791intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3792{
1d508706 3793 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3794
9cd300e0
JN		 3795 if (!IS_ERR_OR_NULL(intel_connector->edid))
3796 kfree(intel_connector->edid);
3797
acd8db10
PZ		 3798 /* Can't call is_edp() since the encoder may have been destroyed
3799 * already. */
3800 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3801 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3802
a4fc5ed6 3803 drm_connector_cleanup(connector);
55f78c43 3804 kfree(connector);
a4fc5ed6
KP		 3805}
3806
00c09d70 3807void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3808{
da63a9f2
PZ		 3809 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3810 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3811 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927 3812
4f71d0cb 3813 drm_dp_aux_unregister(&intel_dp->aux);
24d05927 3814 drm_encoder_cleanup(encoder);
bd943159
KP		 3815 if (is_edp(intel_dp)) {
3816 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 3817 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 3818 edp_panel_vdd_off_sync(intel_dp);
51fd371b 3819 drm_modeset_unlock(&dev->mode_config.connection_mutex);
bd943159 3820 }
da63a9f2 3821 kfree(intel_dig_port);
24d05927
DV		 3822}
3823
a4fc5ed6 3824static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3825 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3826 .detect = intel_dp_detect,
3827 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3828 .set_property = intel_dp_set_property,
73845adf 3829 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3830};
3831
3832static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3833 .get_modes = intel_dp_get_modes,
3834 .mode_valid = intel_dp_mode_valid,
df0e9248 3835 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3836};
3837
a4fc5ed6 3838static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3839 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3840};
3841
995b6762 3842static void
21d40d37 3843intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3844{
fa90ecef 3845 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3846
885a5014 3847 intel_dp_check_link_status(intel_dp);
c8110e52 3848}
6207937d 3849
e3421a18
ZW		 3850/* Return which DP Port should be selected for Transcoder DP control */
3851int
0206e353 3852intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3853{
3854 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3855 struct intel_encoder *intel_encoder;
3856 struct intel_dp *intel_dp;
e3421a18 3857
fa90ecef
PZ		 3858 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3859 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3860
fa90ecef
PZ		 3861 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3862 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3863 return intel_dp->output_reg;
e3421a18 3864 }
ea5b213a 3865
e3421a18
ZW		 3866 return -1;
3867}
3868
36e83a18 3869/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3870bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3871{
3872 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3873 union child_device_config *p_child;
36e83a18 3874 int i;
5d8a7752
VS		 3875 static const short port_mapping[] = {
3876 [PORT_B] = PORT_IDPB,
3877 [PORT_C] = PORT_IDPC,
3878 [PORT_D] = PORT_IDPD,
3879 };
36e83a18 3880
3b32a35b
VS		 3881 if (port == PORT_A)
3882 return true;
3883
41aa3448 3884 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3885 return false;
3886
41aa3448
RV		 3887 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3888 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3889
5d8a7752 3890 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3891 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3892 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3893 return true;
3894 }
3895 return false;
3896}
3897
f684960e
CW		 3898static void
3899intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3900{
53b41837
YN		 3901 struct intel_connector *intel_connector = to_intel_connector(connector);
3902
3f43c48d 3903 intel_attach_force_audio_property(connector);
e953fd7b 3904 intel_attach_broadcast_rgb_property(connector);
55bc60db 3905 intel_dp->color_range_auto = true;
53b41837
YN		 3906
3907 if (is_edp(intel_dp)) {
3908 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3909 drm_object_attach_property(
3910 &connector->base,
53b41837 3911 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3912 DRM_MODE_SCALE_ASPECT);
3913 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3914 }
f684960e
CW		 3915}
3916
dada1a9f
ID		 3917static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3918{
3919 intel_dp->last_power_cycle = jiffies;
3920 intel_dp->last_power_on = jiffies;
3921 intel_dp->last_backlight_off = jiffies;
3922}
3923
67a54566
DV		 3924static void
3925intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3926 struct intel_dp *intel_dp,
3927 struct edp_power_seq *out)
67a54566
DV		 3928{
3929 struct drm_i915_private *dev_priv = dev->dev_private;
3930 struct edp_power_seq cur, vbt, spec, final;
3931 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3932 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3933
3934 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3935 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3936 pp_on_reg = PCH_PP_ON_DELAYS;
3937 pp_off_reg = PCH_PP_OFF_DELAYS;
3938 pp_div_reg = PCH_PP_DIVISOR;
3939 } else {
bf13e81b
JN		 3940 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3941
3942 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3943 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3944 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3945 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3946 }
67a54566
DV		 3947
3948 /* Workaround: Need to write PP_CONTROL with the unlock key as
3949 * the very first thing. */
453c5420 3950 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3951 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3952
453c5420
JB		 3953 pp_on = I915_READ(pp_on_reg);
3954 pp_off = I915_READ(pp_off_reg);
3955 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3956
3957 /* Pull timing values out of registers */
3958 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3959 PANEL_POWER_UP_DELAY_SHIFT;
3960
3961 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3962 PANEL_LIGHT_ON_DELAY_SHIFT;
3963
3964 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3965 PANEL_LIGHT_OFF_DELAY_SHIFT;
3966
3967 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3968 PANEL_POWER_DOWN_DELAY_SHIFT;
3969
3970 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3971 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3972
3973 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3974 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3975
41aa3448 3976 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3977
3978 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3979 * our hw here, which are all in 100usec. */
3980 spec.t1_t3 = 210 * 10;
3981 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3982 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3983 spec.t10 = 500 * 10;
3984 /* This one is special and actually in units of 100ms, but zero
3985 * based in the hw (so we need to add 100 ms). But the sw vbt
3986 * table multiplies it with 1000 to make it in units of 100usec,
3987 * too. */
3988 spec.t11_t12 = (510 + 100) * 10;
3989
3990 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3991 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3992
3993 /* Use the max of the register settings and vbt. If both are
3994 * unset, fall back to the spec limits. */
3995#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3996 spec.field : \
3997 max(cur.field, vbt.field))
3998 assign_final(t1_t3);
3999 assign_final(t8);
4000 assign_final(t9);
4001 assign_final(t10);
4002 assign_final(t11_t12);
4003#undef assign_final
4004
4005#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4006 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4007 intel_dp->backlight_on_delay = get_delay(t8);
4008 intel_dp->backlight_off_delay = get_delay(t9);
4009 intel_dp->panel_power_down_delay = get_delay(t10);
4010 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4011#undef get_delay
4012
f30d26e4
JN		 4013 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4014 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4015 intel_dp->panel_power_cycle_delay);
4016
4017 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4018 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4019
4020 if (out)
4021 *out = final;
4022}
4023
4024static void
4025intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4026 struct intel_dp *intel_dp,
4027 struct edp_power_seq *seq)
4028{
4029 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4030 u32 pp_on, pp_off, pp_div, port_sel = 0;
4031 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4032 int pp_on_reg, pp_off_reg, pp_div_reg;
4033
4034 if (HAS_PCH_SPLIT(dev)) {
4035 pp_on_reg = PCH_PP_ON_DELAYS;
4036 pp_off_reg = PCH_PP_OFF_DELAYS;
4037 pp_div_reg = PCH_PP_DIVISOR;
4038 } else {
bf13e81b
JN		 4039 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4040
4041 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4042 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4043 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4044 }
4045
b2f19d1a
PZ		 4046 /*
4047 * And finally store the new values in the power sequencer. The
4048 * backlight delays are set to 1 because we do manual waits on them. For
4049 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4050 * we'll end up waiting for the backlight off delay twice: once when we
4051 * do the manual sleep, and once when we disable the panel and wait for
4052 * the PP_STATUS bit to become zero.
4053 */
f30d26e4 4054 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4055 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4056 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4057 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4058 /* Compute the divisor for the pp clock, simply match the Bspec
4059 * formula. */
453c5420 4060 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4061 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4062 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4063
4064 /* Haswell doesn't have any port selection bits for the panel
4065 * power sequencer any more. */
bc7d38a4 4066 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 4067 if (dp_to_dig_port(intel_dp)->port == PORT_B)
4068 port_sel = PANEL_PORT_SELECT_DPB_VLV;
4069 else
4070 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 4071 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4072 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 4073 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4074 else
a24c144c 4075 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4076 }
4077
453c5420
JB		 4078 pp_on |= port_sel;
4079
4080 I915_WRITE(pp_on_reg, pp_on);
4081 I915_WRITE(pp_off_reg, pp_off);
4082 I915_WRITE(pp_div_reg, pp_div);
67a54566 4083
67a54566 4084 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4085 I915_READ(pp_on_reg),
4086 I915_READ(pp_off_reg),
4087 I915_READ(pp_div_reg));
f684960e
CW		 4088}
4089
439d7ac0
PB		 4090void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4091{
4092 struct drm_i915_private *dev_priv = dev->dev_private;
4093 struct intel_encoder *encoder;
4094 struct intel_dp *intel_dp = NULL;
4095 struct intel_crtc_config *config = NULL;
4096 struct intel_crtc *intel_crtc = NULL;
4097 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4098 u32 reg, val;
4099 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4100
4101 if (refresh_rate <= 0) {
4102 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4103 return;
4104 }
4105
4106 if (intel_connector == NULL) {
4107 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4108 return;
4109 }
4110
4111 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4112 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4113 return;
4114 }
4115
4116 encoder = intel_attached_encoder(&intel_connector->base);
4117 intel_dp = enc_to_intel_dp(&encoder->base);
4118 intel_crtc = encoder->new_crtc;
4119
4120 if (!intel_crtc) {
4121 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4122 return;
4123 }
4124
4125 config = &intel_crtc->config;
4126
4127 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4128 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4129 return;
4130 }
4131
4132 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4133 index = DRRS_LOW_RR;
4134
4135 if (index == intel_dp->drrs_state.refresh_rate_type) {
4136 DRM_DEBUG_KMS(
4137 "DRRS requested for previously set RR...ignoring\n");
4138 return;
4139 }
4140
4141 if (!intel_crtc->active) {
4142 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4143 return;
4144 }
4145
4146 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4147 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4148 val = I915_READ(reg);
4149 if (index > DRRS_HIGH_RR) {
4150 val |= PIPECONF_EDP_RR_MODE_SWITCH;
4151 intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
4152 } else {
4153 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4154 }
4155 I915_WRITE(reg, val);
4156 }
4157
4158 /*
4159 * mutex taken to ensure that there is no race between differnt
4160 * drrs calls trying to update refresh rate. This scenario may occur
4161 * in future when idleness detection based DRRS in kernel and
4162 * possible calls from user space to set differnt RR are made.
4163 */
4164
4165 mutex_lock(&intel_dp->drrs_state.mutex);
4166
4167 intel_dp->drrs_state.refresh_rate_type = index;
4168
4169 mutex_unlock(&intel_dp->drrs_state.mutex);
4170
4171 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4172}
4173
4f9db5b5
PB		 4174static struct drm_display_mode *
4175intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4176 struct intel_connector *intel_connector,
4177 struct drm_display_mode *fixed_mode)
4178{
4179 struct drm_connector *connector = &intel_connector->base;
4180 struct intel_dp *intel_dp = &intel_dig_port->dp;
4181 struct drm_device *dev = intel_dig_port->base.base.dev;
4182 struct drm_i915_private *dev_priv = dev->dev_private;
4183 struct drm_display_mode *downclock_mode = NULL;
4184
4185 if (INTEL_INFO(dev)->gen <= 6) {
4186 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4187 return NULL;
4188 }
4189
4190 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4191 DRM_INFO("VBT doesn't support DRRS\n");
4192 return NULL;
4193 }
4194
4195 downclock_mode = intel_find_panel_downclock
4196 (dev, fixed_mode, connector);
4197
4198 if (!downclock_mode) {
4199 DRM_INFO("DRRS not supported\n");
4200 return NULL;
4201 }
4202
439d7ac0
PB		 4203 dev_priv->drrs.connector = intel_connector;
4204
4205 mutex_init(&intel_dp->drrs_state.mutex);
4206
4f9db5b5
PB		 4207 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4208
4209 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4210 DRM_INFO("seamless DRRS supported for eDP panel.\n");
4211 return downclock_mode;
4212}
4213
ed92f0b2 4214static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4215 struct intel_connector *intel_connector,
4216 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4217{
4218 struct drm_connector *connector = &intel_connector->base;
4219 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4220 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4221 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4222 struct drm_i915_private *dev_priv = dev->dev_private;
4223 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4224 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4225 bool has_dpcd;
4226 struct drm_display_mode *scan;
4227 struct edid *edid;
4228
4f9db5b5
PB		 4229 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4230
ed92f0b2
PZ		 4231 if (!is_edp(intel_dp))
4232 return true;
4233
63635217
PZ		 4234 /* The VDD bit needs a power domain reference, so if the bit is already
4235 * enabled when we boot, grab this reference. */
4236 if (edp_have_panel_vdd(intel_dp)) {
4237 enum intel_display_power_domain power_domain;
4238 power_domain = intel_display_port_power_domain(intel_encoder);
4239 intel_display_power_get(dev_priv, power_domain);
4240 }
4241
ed92f0b2 4242 /* Cache DPCD and EDID for edp. */
24f3e092 4243 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 4244 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 4245 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 4246
4247 if (has_dpcd) {
4248 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4249 dev_priv->no_aux_handshake =
4250 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4251 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4252 } else {
4253 /* if this fails, presume the device is a ghost */
4254 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4255 return false;
4256 }
4257
4258 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 4259 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 4260
060c8778 4261 mutex_lock(&dev->mode_config.mutex);
0b99836f 4262 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4263 if (edid) {
4264 if (drm_add_edid_modes(connector, edid)) {
4265 drm_mode_connector_update_edid_property(connector,
4266 edid);
4267 drm_edid_to_eld(connector, edid);
4268 } else {
4269 kfree(edid);
4270 edid = ERR_PTR(-EINVAL);
4271 }
4272 } else {
4273 edid = ERR_PTR(-ENOENT);
4274 }
4275 intel_connector->edid = edid;
4276
4277 /* prefer fixed mode from EDID if available */
4278 list_for_each_entry(scan, &connector->probed_modes, head) {
4279 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4280 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 4281 downclock_mode = intel_dp_drrs_init(
4282 intel_dig_port,
4283 intel_connector, fixed_mode);
ed92f0b2
PZ		 4284 break;
4285 }
4286 }
4287
4288 /* fallback to VBT if available for eDP */
4289 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4290 fixed_mode = drm_mode_duplicate(dev,
4291 dev_priv->vbt.lfp_lvds_vbt_mode);
4292 if (fixed_mode)
4293 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4294 }
060c8778 4295 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 4296
4f9db5b5 4297 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
ed92f0b2
PZ		 4298 intel_panel_setup_backlight(connector);
4299
4300 return true;
4301}
4302
16c25533 4303bool
f0fec3f2
PZ		 4304intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4305 struct intel_connector *intel_connector)
a4fc5ed6 4306{
f0fec3f2
PZ		 4307 struct drm_connector *connector = &intel_connector->base;
4308 struct intel_dp *intel_dp = &intel_dig_port->dp;
4309 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4310 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 4311 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 4312 enum port port = intel_dig_port->port;
0095e6dc 4313 struct edp_power_seq power_seq = { 0 };
0b99836f 4314 int type;
a4fc5ed6 4315
ec5b01dd
DL		 4316 /* intel_dp vfuncs */
4317 if (IS_VALLEYVIEW(dev))
4318 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4319 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4320 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4321 else if (HAS_PCH_SPLIT(dev))
4322 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4323 else
4324 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4325
153b1100
DL		 4326 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4327
0767935e
DV		 4328 /* Preserve the current hw state. */
4329 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 4330 intel_dp->attached_connector = intel_connector;
3d3dc149 4331
3b32a35b 4332 if (intel_dp_is_edp(dev, port))
b329530c 4333 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 4334 else
4335 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 4336
f7d24902
ID		 4337 /*
4338 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4339 * for DP the encoder type can be set by the caller to
4340 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4341 */
4342 if (type == DRM_MODE_CONNECTOR_eDP)
4343 intel_encoder->type = INTEL_OUTPUT_EDP;
4344
e7281eab
ID		 4345 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4346 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4347 port_name(port));
4348
b329530c 4349 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 4350 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4351
a4fc5ed6
KP		 4352 connector->interlace_allowed = true;
4353 connector->doublescan_allowed = 0;
4354
f0fec3f2 4355 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 4356 edp_panel_vdd_work);
a4fc5ed6 4357
df0e9248 4358 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 4359 drm_sysfs_connector_add(connector);
4360
affa9354 4361 if (HAS_DDI(dev))
bcbc889b
PZ		 4362 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4363 else
4364 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 4365 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 4366
0b99836f 4367 /* Set up the hotplug pin. */
ab9d7c30
PZ		 4368 switch (port) {
4369 case PORT_A:
1d843f9d 4370 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 4371 break;
4372 case PORT_B:
1d843f9d 4373 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 4374 break;
4375 case PORT_C:
1d843f9d 4376 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 4377 break;
4378 case PORT_D:
1d843f9d 4379 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 4380 break;
4381 default:
ad1c0b19 4382 BUG();
5eb08b69
ZW		 4383 }
4384
dada1a9f
ID		 4385 if (is_edp(intel_dp)) {
4386 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 4387 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 4388 }
0095e6dc 4389
9d1a1031 4390 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 4391
0095e6dc 4392 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 4393 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 4394 if (is_edp(intel_dp)) {
4395 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 4396 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 4397 edp_panel_vdd_off_sync(intel_dp);
51fd371b 4398 drm_modeset_unlock(&dev->mode_config.connection_mutex);
15b1d171 4399 }
b2f246a8
PZ		 4400 drm_sysfs_connector_remove(connector);
4401 drm_connector_cleanup(connector);
16c25533 4402 return false;
b2f246a8 4403 }
32f9d658 4404
f684960e
CW		 4405 intel_dp_add_properties(intel_dp, connector);
4406
a4fc5ed6
KP		 4407 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4408 * 0xd. Failure to do so will result in spurious interrupts being
4409 * generated on the port when a cable is not attached.
4410 */
4411 if (IS_G4X(dev) && !IS_GM45(dev)) {
4412 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4413 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4414 }
16c25533
PZ		 4415
4416 return true;
a4fc5ed6 4417}
f0fec3f2
PZ		 4418
4419void
4420intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4421{
4422 struct intel_digital_port *intel_dig_port;
4423 struct intel_encoder *intel_encoder;
4424 struct drm_encoder *encoder;
4425 struct intel_connector *intel_connector;
4426
b14c5679 4427 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 4428 if (!intel_dig_port)
4429 return;
4430
b14c5679 4431 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 4432 if (!intel_connector) {
4433 kfree(intel_dig_port);
4434 return;
4435 }
4436
4437 intel_encoder = &intel_dig_port->base;
4438 encoder = &intel_encoder->base;
4439
4440 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4441 DRM_MODE_ENCODER_TMDS);
4442
5bfe2ac0 4443 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 4444 intel_encoder->disable = intel_disable_dp;
00c09d70 4445 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 4446 intel_encoder->get_config = intel_dp_get_config;
e4a1d846 4447 if (IS_CHERRYVIEW(dev)) {
9197c88b 4448 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 4449 intel_encoder->pre_enable = chv_pre_enable_dp;
4450 intel_encoder->enable = vlv_enable_dp;
580d3811 4451 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 4452 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 4453 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 4454 intel_encoder->pre_enable = vlv_pre_enable_dp;
4455 intel_encoder->enable = vlv_enable_dp;
49277c31 4456 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 4457 } else {
ecff4f3b
JN		 4458 intel_encoder->pre_enable = g4x_pre_enable_dp;
4459 intel_encoder->enable = g4x_enable_dp;
49277c31 4460 intel_encoder->post_disable = g4x_post_disable_dp;
ab1f90f9 4461 }
f0fec3f2 4462
174edf1f 4463 intel_dig_port->port = port;
f0fec3f2
PZ		 4464 intel_dig_port->dp.output_reg = output_reg;
4465
00c09d70 4466 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 4467 if (IS_CHERRYVIEW(dev)) {
4468 if (port == PORT_D)
4469 intel_encoder->crtc_mask = 1 << 2;
4470 else
4471 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4472 } else {
4473 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4474 }
bc079e8b 4475 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 4476 intel_encoder->hot_plug = intel_dp_hot_plug;
4477
15b1d171
PZ		 4478 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4479 drm_encoder_cleanup(encoder);
4480 kfree(intel_dig_port);
b2f246a8 4481 kfree(intel_connector);
15b1d171 4482 }
f0fec3f2 4483}
Linux kernel - Deliverables
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