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drm/i915: Convert overlay double wide check over to pipe config
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 5, .m2 = 3 } },
63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
cfcb0fc9
JB		 67/**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74static bool is_edp(struct intel_dp *intel_dp)
75{
da63a9f2
PZ		 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 79}
80
68b4d824 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 82{
68b4d824
ID		 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 86}
87
df0e9248
CW		 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89{
fa90ecef 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 91}
92
ea5b213a 93static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 94
a4fc5ed6 95static int
ea5b213a 96intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 97{
7183dc29 98 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 99
100 switch (max_link_bw) {
101 case DP_LINK_BW_1_62:
102 case DP_LINK_BW_2_7:
103 break;
d4eead50
ID		 104 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
105 max_link_bw = DP_LINK_BW_2_7;
106 break;
a4fc5ed6 107 default:
d4eead50
ID		 108 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
109 max_link_bw);
a4fc5ed6
KP		 110 max_link_bw = DP_LINK_BW_1_62;
111 break;
112 }
113 return max_link_bw;
114}
115
cd9dde44
AJ		 116/*
117 * The units on the numbers in the next two are... bizarre. Examples will
118 * make it clearer; this one parallels an example in the eDP spec.
119 *
120 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
121 *
122 * 270000 * 1 * 8 / 10 == 216000
123 *
124 * The actual data capacity of that configuration is 2.16Gbit/s, so the
125 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
126 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
127 * 119000. At 18bpp that's 2142000 kilobits per second.
128 *
129 * Thus the strange-looking division by 10 in intel_dp_link_required, to
130 * get the result in decakilobits instead of kilobits.
131 */
132
a4fc5ed6 133static int
c898261c 134intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 135{
cd9dde44 136 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 137}
138
fe27d53e
DA		 139static int
140intel_dp_max_data_rate(int max_link_clock, int max_lanes)
141{
142 return (max_link_clock * max_lanes * 8) / 10;
143}
144
a4fc5ed6
KP		 145static int
146intel_dp_mode_valid(struct drm_connector *connector,
147 struct drm_display_mode *mode)
148{
df0e9248 149 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 150 struct intel_connector *intel_connector = to_intel_connector(connector);
151 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 152 int target_clock = mode->clock;
153 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 154
dd06f90e
JN		 155 if (is_edp(intel_dp) && fixed_mode) {
156 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 157 return MODE_PANEL;
158
dd06f90e 159 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 160 return MODE_PANEL;
03afc4a2
DV		 161
162 target_clock = fixed_mode->clock;
7de56f43
ZY		 163 }
164
36008365
DV		 165 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
166 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
167
168 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
169 mode_rate = intel_dp_link_required(target_clock, 18);
170
171 if (mode_rate > max_rate)
c4867936 172 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 173
174 if (mode->clock < 10000)
175 return MODE_CLOCK_LOW;
176
0af78a2b
DV		 177 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
178 return MODE_H_ILLEGAL;
179
a4fc5ed6
KP		 180 return MODE_OK;
181}
182
183static uint32_t
184pack_aux(uint8_t *src, int src_bytes)
185{
186 int i;
187 uint32_t v = 0;
188
189 if (src_bytes > 4)
190 src_bytes = 4;
191 for (i = 0; i < src_bytes; i++)
192 v |= ((uint32_t) src[i]) << ((3-i) * 8);
193 return v;
194}
195
196static void
197unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
198{
199 int i;
200 if (dst_bytes > 4)
201 dst_bytes = 4;
202 for (i = 0; i < dst_bytes; i++)
203 dst[i] = src >> ((3-i) * 8);
204}
205
fb0f8fbf
KP		 206/* hrawclock is 1/4 the FSB frequency */
207static int
208intel_hrawclk(struct drm_device *dev)
209{
210 struct drm_i915_private *dev_priv = dev->dev_private;
211 uint32_t clkcfg;
212
9473c8f4
VP		 213 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
214 if (IS_VALLEYVIEW(dev))
215 return 200;
216
fb0f8fbf
KP		 217 clkcfg = I915_READ(CLKCFG);
218 switch (clkcfg & CLKCFG_FSB_MASK) {
219 case CLKCFG_FSB_400:
220 return 100;
221 case CLKCFG_FSB_533:
222 return 133;
223 case CLKCFG_FSB_667:
224 return 166;
225 case CLKCFG_FSB_800:
226 return 200;
227 case CLKCFG_FSB_1067:
228 return 266;
229 case CLKCFG_FSB_1333:
230 return 333;
231 /* these two are just a guess; one of them might be right */
232 case CLKCFG_FSB_1600:
233 case CLKCFG_FSB_1600_ALT:
234 return 400;
235 default:
236 return 133;
237 }
238}
239
bf13e81b
JN		 240static void
241intel_dp_init_panel_power_sequencer(struct drm_device *dev,
242 struct intel_dp *intel_dp,
243 struct edp_power_seq *out);
244static void
245intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
246 struct intel_dp *intel_dp,
247 struct edp_power_seq *out);
248
249static enum pipe
250vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
251{
252 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
253 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
254 struct drm_device *dev = intel_dig_port->base.base.dev;
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 enum port port = intel_dig_port->port;
257 enum pipe pipe;
258
259 /* modeset should have pipe */
260 if (crtc)
261 return to_intel_crtc(crtc)->pipe;
262
263 /* init time, try to find a pipe with this port selected */
264 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
265 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
266 PANEL_PORT_SELECT_MASK;
267 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
268 return pipe;
269 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
270 return pipe;
271 }
272
273 /* shrug */
274 return PIPE_A;
275}
276
277static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
278{
279 struct drm_device *dev = intel_dp_to_dev(intel_dp);
280
281 if (HAS_PCH_SPLIT(dev))
282 return PCH_PP_CONTROL;
283 else
284 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
285}
286
287static u32 _pp_stat_reg(struct intel_dp *intel_dp)
288{
289 struct drm_device *dev = intel_dp_to_dev(intel_dp);
290
291 if (HAS_PCH_SPLIT(dev))
292 return PCH_PP_STATUS;
293 else
294 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
295}
296
ebf33b18
KP		 297static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
298{
30add22d 299 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 300 struct drm_i915_private *dev_priv = dev->dev_private;
301
bf13e81b 302 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 303}
304
305static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
306{
30add22d 307 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 308 struct drm_i915_private *dev_priv = dev->dev_private;
309
bf13e81b 310 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 311}
312
9b984dae
KP		 313static void
314intel_dp_check_edp(struct intel_dp *intel_dp)
315{
30add22d 316 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 317 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 318
9b984dae
KP		 319 if (!is_edp(intel_dp))
320 return;
453c5420 321
ebf33b18 322 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 323 WARN(1, "eDP powered off while attempting aux channel communication.\n");
324 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 325 I915_READ(_pp_stat_reg(intel_dp)),
326 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 327 }
328}
329
9ee32fea
DV		 330static uint32_t
331intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
332{
333 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
334 struct drm_device *dev = intel_dig_port->base.base.dev;
335 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 336 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 337 uint32_t status;
338 bool done;
339
ef04f00d 340#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 341 if (has_aux_irq)
b18ac466 342 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 343 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 344 else
345 done = wait_for_atomic(C, 10) == 0;
346 if (!done)
347 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
348 has_aux_irq);
349#undef C
350
351 return status;
352}
353
bc86625a
CW		 354static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
355 int index)
a4fc5ed6 356{
174edf1f
PZ		 357 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
358 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 359 struct drm_i915_private *dev_priv = dev->dev_private;
9ee32fea 360
a4fc5ed6 361 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 362 * and would like to run at 2MHz. So, take the
363 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 364 *
365 * Note that PCH attached eDP panels should use a 125MHz input
366 * clock divider.
a4fc5ed6 367 */
a62d0834 368 if (IS_VALLEYVIEW(dev)) {
bc86625a 369 return index ? 0 : 100;
a62d0834 370 } else if (intel_dig_port->port == PORT_A) {
bc86625a
CW		 371 if (index)
372 return 0;
affa9354 373 if (HAS_DDI(dev))
bc86625a 374 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
9473c8f4 375 else if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 376 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 377 else
b84a1cf8 378 return 225; /* eDP input clock at 450Mhz */
2c55c336
JN		 379 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
380 /* Workaround for non-ULT HSW */
bc86625a
CW		 381 switch (index) {
382 case 0: return 63;
383 case 1: return 72;
384 default: return 0;
385 }
2c55c336 386 } else if (HAS_PCH_SPLIT(dev)) {
bc86625a 387 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 388 } else {
bc86625a 389 return index ? 0 :intel_hrawclk(dev) / 2;
2c55c336 390 }
b84a1cf8
RV		 391}
392
393static int
394intel_dp_aux_ch(struct intel_dp *intel_dp,
395 uint8_t *send, int send_bytes,
396 uint8_t *recv, int recv_size)
397{
398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
399 struct drm_device *dev = intel_dig_port->base.base.dev;
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
402 uint32_t ch_data = ch_ctl + 4;
bc86625a 403 uint32_t aux_clock_divider;
b84a1cf8
RV		 404 int i, ret, recv_bytes;
405 uint32_t status;
bc86625a 406 int try, precharge, clock = 0;
b84a1cf8
RV		 407 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
408
409 /* dp aux is extremely sensitive to irq latency, hence request the
410 * lowest possible wakeup latency and so prevent the cpu from going into
411 * deep sleep states.
412 */
413 pm_qos_update_request(&dev_priv->pm_qos, 0);
414
415 intel_dp_check_edp(intel_dp);
5eb08b69 416
6b4e0a93
DV		 417 if (IS_GEN6(dev))
418 precharge = 3;
419 else
420 precharge = 5;
421
c67a470b
PZ		 422 intel_aux_display_runtime_get(dev_priv);
423
11bee43e
JB		 424 /* Try to wait for any previous AUX channel activity */
425 for (try = 0; try < 3; try++) {
ef04f00d 426 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 427 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
428 break;
429 msleep(1);
430 }
431
432 if (try == 3) {
433 WARN(1, "dp_aux_ch not started status 0x%08x\n",
434 I915_READ(ch_ctl));
9ee32fea
DV		 435 ret = -EBUSY;
436 goto out;
4f7f7b7e
CW		 437 }
438
bc86625a
CW		 439 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
440 /* Must try at least 3 times according to DP spec */
441 for (try = 0; try < 5; try++) {
442 /* Load the send data into the aux channel data registers */
443 for (i = 0; i < send_bytes; i += 4)
444 I915_WRITE(ch_data + i,
445 pack_aux(send + i, send_bytes - i));
446
447 /* Send the command and wait for it to complete */
448 I915_WRITE(ch_ctl,
449 DP_AUX_CH_CTL_SEND_BUSY |
450 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
451 DP_AUX_CH_CTL_TIME_OUT_400us |
452 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
453 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
454 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
455 DP_AUX_CH_CTL_DONE |
456 DP_AUX_CH_CTL_TIME_OUT_ERROR |
457 DP_AUX_CH_CTL_RECEIVE_ERROR);
458
459 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
460
461 /* Clear done status and any errors */
462 I915_WRITE(ch_ctl,
463 status |
464 DP_AUX_CH_CTL_DONE |
465 DP_AUX_CH_CTL_TIME_OUT_ERROR |
466 DP_AUX_CH_CTL_RECEIVE_ERROR);
467
468 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
469 DP_AUX_CH_CTL_RECEIVE_ERROR))
470 continue;
471 if (status & DP_AUX_CH_CTL_DONE)
472 break;
473 }
4f7f7b7e 474 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 475 break;
476 }
477
a4fc5ed6 478 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 479 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 480 ret = -EBUSY;
481 goto out;
a4fc5ed6
KP		 482 }
483
484 /* Check for timeout or receive error.
485 * Timeouts occur when the sink is not connected
486 */
a5b3da54 487 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 488 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 489 ret = -EIO;
490 goto out;
a5b3da54 491 }
1ae8c0a5
KP		 492
493 /* Timeouts occur when the device isn't connected, so they're
494 * "normal" -- don't fill the kernel log with these */
a5b3da54 495 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 496 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 497 ret = -ETIMEDOUT;
498 goto out;
a4fc5ed6
KP		 499 }
500
501 /* Unload any bytes sent back from the other side */
502 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
503 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 504 if (recv_bytes > recv_size)
505 recv_bytes = recv_size;
0206e353 506
4f7f7b7e
CW		 507 for (i = 0; i < recv_bytes; i += 4)
508 unpack_aux(I915_READ(ch_data + i),
509 recv + i, recv_bytes - i);
a4fc5ed6 510
9ee32fea
DV		 511 ret = recv_bytes;
512out:
513 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 514 intel_aux_display_runtime_put(dev_priv);
9ee32fea
DV		 515
516 return ret;
a4fc5ed6
KP		 517}
518
519/* Write data to the aux channel in native mode */
520static int
ea5b213a 521intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 522 uint16_t address, uint8_t *send, int send_bytes)
523{
524 int ret;
525 uint8_t msg[20];
526 int msg_bytes;
527 uint8_t ack;
528
9b984dae 529 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 530 if (send_bytes > 16)
531 return -1;
532 msg[0] = AUX_NATIVE_WRITE << 4;
533 msg[1] = address >> 8;
eebc863e 534 msg[2] = address & 0xff;
a4fc5ed6
KP		 535 msg[3] = send_bytes - 1;
536 memcpy(&msg[4], send, send_bytes);
537 msg_bytes = send_bytes + 4;
538 for (;;) {
ea5b213a 539 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 540 if (ret < 0)
541 return ret;
542 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
543 break;
544 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
545 udelay(100);
546 else
a5b3da54 547 return -EIO;
a4fc5ed6
KP		 548 }
549 return send_bytes;
550}
551
552/* Write a single byte to the aux channel in native mode */
553static int
ea5b213a 554intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 555 uint16_t address, uint8_t byte)
556{
ea5b213a 557 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 558}
559
560/* read bytes from a native aux channel */
561static int
ea5b213a 562intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 563 uint16_t address, uint8_t *recv, int recv_bytes)
564{
565 uint8_t msg[4];
566 int msg_bytes;
567 uint8_t reply[20];
568 int reply_bytes;
569 uint8_t ack;
570 int ret;
571
9b984dae 572 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 573 msg[0] = AUX_NATIVE_READ << 4;
574 msg[1] = address >> 8;
575 msg[2] = address & 0xff;
576 msg[3] = recv_bytes - 1;
577
578 msg_bytes = 4;
579 reply_bytes = recv_bytes + 1;
580
581 for (;;) {
ea5b213a 582 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 583 reply, reply_bytes);
a5b3da54
KP		 584 if (ret == 0)
585 return -EPROTO;
586 if (ret < 0)
a4fc5ed6
KP		 587 return ret;
588 ack = reply[0];
589 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
590 memcpy(recv, reply + 1, ret - 1);
591 return ret - 1;
592 }
593 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
594 udelay(100);
595 else
a5b3da54 596 return -EIO;
a4fc5ed6
KP		 597 }
598}
599
600static int
ab2c0672
DA		 601intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
602 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 603{
ab2c0672 604 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 605 struct intel_dp *intel_dp = container_of(adapter,
606 struct intel_dp,
607 adapter);
ab2c0672
DA		 608 uint16_t address = algo_data->address;
609 uint8_t msg[5];
610 uint8_t reply[2];
8316f337 611 unsigned retry;
ab2c0672
DA		 612 int msg_bytes;
613 int reply_bytes;
614 int ret;
615
9b984dae 616 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 617 /* Set up the command byte */
618 if (mode & MODE_I2C_READ)
619 msg[0] = AUX_I2C_READ << 4;
620 else
621 msg[0] = AUX_I2C_WRITE << 4;
622
623 if (!(mode & MODE_I2C_STOP))
624 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 625
ab2c0672
DA		 626 msg[1] = address >> 8;
627 msg[2] = address;
628
629 switch (mode) {
630 case MODE_I2C_WRITE:
631 msg[3] = 0;
632 msg[4] = write_byte;
633 msg_bytes = 5;
634 reply_bytes = 1;
635 break;
636 case MODE_I2C_READ:
637 msg[3] = 0;
638 msg_bytes = 4;
639 reply_bytes = 2;
640 break;
641 default:
642 msg_bytes = 3;
643 reply_bytes = 1;
644 break;
645 }
646
8316f337
DF		 647 for (retry = 0; retry < 5; retry++) {
648 ret = intel_dp_aux_ch(intel_dp,
649 msg, msg_bytes,
650 reply, reply_bytes);
ab2c0672 651 if (ret < 0) {
3ff99164 652 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 653 return ret;
654 }
8316f337
DF		 655
656 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
657 case AUX_NATIVE_REPLY_ACK:
658 /* I2C-over-AUX Reply field is only valid
659 * when paired with AUX ACK.
660 */
661 break;
662 case AUX_NATIVE_REPLY_NACK:
663 DRM_DEBUG_KMS("aux_ch native nack\n");
664 return -EREMOTEIO;
665 case AUX_NATIVE_REPLY_DEFER:
666 udelay(100);
667 continue;
668 default:
669 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
670 reply[0]);
671 return -EREMOTEIO;
672 }
673
ab2c0672
DA		 674 switch (reply[0] & AUX_I2C_REPLY_MASK) {
675 case AUX_I2C_REPLY_ACK:
676 if (mode == MODE_I2C_READ) {
677 *read_byte = reply[1];
678 }
679 return reply_bytes - 1;
680 case AUX_I2C_REPLY_NACK:
8316f337 681 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 682 return -EREMOTEIO;
683 case AUX_I2C_REPLY_DEFER:
8316f337 684 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 685 udelay(100);
686 break;
687 default:
8316f337 688 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 689 return -EREMOTEIO;
690 }
691 }
8316f337
DF		 692
693 DRM_ERROR("too many retries, giving up\n");
694 return -EREMOTEIO;
a4fc5ed6
KP		 695}
696
697static int
ea5b213a 698intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 699 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 700{
0b5c541b
KP		 701 int ret;
702
d54e9d28 703 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 704 intel_dp->algo.running = false;
705 intel_dp->algo.address = 0;
706 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
707
0206e353 708 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 709 intel_dp->adapter.owner = THIS_MODULE;
710 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 711 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 712 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
713 intel_dp->adapter.algo_data = &intel_dp->algo;
714 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
715
0b5c541b
KP		 716 ironlake_edp_panel_vdd_on(intel_dp);
717 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 718 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 719 return ret;
a4fc5ed6
KP		 720}
721
c6bb3538
DV		 722static void
723intel_dp_set_clock(struct intel_encoder *encoder,
724 struct intel_crtc_config *pipe_config, int link_bw)
725{
726 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 727 const struct dp_link_dpll *divisor = NULL;
728 int i, count = 0;
c6bb3538
DV		 729
730 if (IS_G4X(dev)) {
9dd4ffdf
CML		 731 divisor = gen4_dpll;
732 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 733 } else if (IS_HASWELL(dev)) {
734 /* Haswell has special-purpose DP DDI clocks. */
735 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 736 divisor = pch_dpll;
737 count = ARRAY_SIZE(pch_dpll);
c6bb3538 738 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 739 divisor = vlv_dpll;
740 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 741 }
9dd4ffdf
CML		 742
743 if (divisor && count) {
744 for (i = 0; i < count; i++) {
745 if (link_bw == divisor[i].link_bw) {
746 pipe_config->dpll = divisor[i].dpll;
747 pipe_config->clock_set = true;
748 break;
749 }
750 }
751 }
c6bb3538
DV		 752}
753
00c09d70 754bool
5bfe2ac0
DV		 755intel_dp_compute_config(struct intel_encoder *encoder,
756 struct intel_crtc_config *pipe_config)
a4fc5ed6 757{
5bfe2ac0 758 struct drm_device *dev = encoder->base.dev;
36008365 759 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 760 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 761 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 762 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 763 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 764 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 765 int lane_count, clock;
397fe157 766 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 767 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 768 int bpp, mode_rate;
a4fc5ed6 769 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
ff9a6750 770 int link_avail, link_clock;
a4fc5ed6 771
bc7d38a4 772 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 773 pipe_config->has_pch_encoder = true;
774
03afc4a2 775 pipe_config->has_dp_encoder = true;
a4fc5ed6 776
dd06f90e
JN		 777 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
778 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
779 adjusted_mode);
2dd24552
JB		 780 if (!HAS_PCH_SPLIT(dev))
781 intel_gmch_panel_fitting(intel_crtc, pipe_config,
782 intel_connector->panel.fitting_mode);
783 else
b074cec8
JB		 784 intel_pch_panel_fitting(intel_crtc, pipe_config,
785 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 786 }
787
cb1793ce 788 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 789 return false;
790
083f9560
DV		 791 DRM_DEBUG_KMS("DP link computation with max lane count %i "
792 "max bw %02x pixel clock %iKHz\n",
71244653 793 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 794
36008365
DV		 795 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
796 * bpc in between. */
3e7ca985 797 bpp = pipe_config->pipe_bpp;
7984211e
ID		 798 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) {
799 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
800 dev_priv->vbt.edp_bpp);
e1b73cba 801 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
7984211e 802 }
657445fe 803
36008365 804 for (; bpp >= 6*3; bpp -= 2*3) {
ff9a6750 805 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
36008365
DV		 806
807 for (clock = 0; clock <= max_clock; clock++) {
808 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
809 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
810 link_avail = intel_dp_max_data_rate(link_clock,
811 lane_count);
812
813 if (mode_rate <= link_avail) {
814 goto found;
815 }
816 }
817 }
818 }
c4867936 819
36008365 820 return false;
3685a8f3 821
36008365 822found:
55bc60db
VS		 823 if (intel_dp->color_range_auto) {
824 /*
825 * See:
826 * CEA-861-E - 5.1 Default Encoding Parameters
827 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
828 */
18316c8c 829 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 830 intel_dp->color_range = DP_COLOR_RANGE_16_235;
831 else
832 intel_dp->color_range = 0;
833 }
834
3685a8f3 835 if (intel_dp->color_range)
50f3b016 836 pipe_config->limited_color_range = true;
a4fc5ed6 837
36008365
DV		 838 intel_dp->link_bw = bws[clock];
839 intel_dp->lane_count = lane_count;
657445fe 840 pipe_config->pipe_bpp = bpp;
ff9a6750 841 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 842
36008365
DV		 843 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
844 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 845 pipe_config->port_clock, bpp);
36008365
DV		 846 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
847 mode_rate, link_avail);
a4fc5ed6 848
03afc4a2 849 intel_link_compute_m_n(bpp, lane_count,
ff9a6750 850 adjusted_mode->clock, pipe_config->port_clock,
03afc4a2 851 &pipe_config->dp_m_n);
9d1a455b 852
c6bb3538
DV		 853 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
854
03afc4a2 855 return true;
a4fc5ed6
KP		 856}
857
247d89f6
PZ		 858void intel_dp_init_link_config(struct intel_dp *intel_dp)
859{
860 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
861 intel_dp->link_configuration[0] = intel_dp->link_bw;
862 intel_dp->link_configuration[1] = intel_dp->lane_count;
863 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
864 /*
865 * Check for DPCD version > 1.1 and enhanced framing support
866 */
867 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
868 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
869 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
870 }
871}
872
7c62a164 873static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 874{
7c62a164
DV		 875 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
876 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
877 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 878 struct drm_i915_private *dev_priv = dev->dev_private;
879 u32 dpa_ctl;
880
ff9a6750 881 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 882 dpa_ctl = I915_READ(DP_A);
883 dpa_ctl &= ~DP_PLL_FREQ_MASK;
884
ff9a6750 885 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 886 /* For a long time we've carried around a ILK-DevA w/a for the
887 * 160MHz clock. If we're really unlucky, it's still required.
888 */
889 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 890 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 891 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 892 } else {
893 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 894 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 895 }
1ce17038 896
ea9b6006
DV		 897 I915_WRITE(DP_A, dpa_ctl);
898
899 POSTING_READ(DP_A);
900 udelay(500);
901}
902
b934223d 903static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 904{
b934223d 905 struct drm_device *dev = encoder->base.dev;
417e822d 906 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 907 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 908 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 909 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
910 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 911
417e822d 912 /*
1a2eb460 913 * There are four kinds of DP registers:
417e822d
KP		 914 *
915 * IBX PCH
1a2eb460
KP		 916 * SNB CPU
917 * IVB CPU
417e822d
KP		 918 * CPT PCH
919 *
920 * IBX PCH and CPU are the same for almost everything,
921 * except that the CPU DP PLL is configured in this
922 * register
923 *
924 * CPT PCH is quite different, having many bits moved
925 * to the TRANS_DP_CTL register instead. That
926 * configuration happens (oddly) in ironlake_pch_enable
927 */
9c9e7927 928
417e822d
KP		 929 /* Preserve the BIOS-computed detected bit. This is
930 * supposed to be read-only.
931 */
932 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 933
417e822d 934 /* Handle DP bits in common between all three register formats */
417e822d 935 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 936 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 937
e0dac65e
WF		 938 if (intel_dp->has_audio) {
939 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 940 pipe_name(crtc->pipe));
ea5b213a 941 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 942 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 943 }
247d89f6
PZ		 944
945 intel_dp_init_link_config(intel_dp);
a4fc5ed6 946
417e822d 947 /* Split out the IBX/CPU vs CPT settings */
32f9d658 948
bc7d38a4 949 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 950 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
951 intel_dp->DP |= DP_SYNC_HS_HIGH;
952 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
953 intel_dp->DP |= DP_SYNC_VS_HIGH;
954 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
955
956 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
957 intel_dp->DP |= DP_ENHANCED_FRAMING;
958
7c62a164 959 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 960 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 961 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 962 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 963
964 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
965 intel_dp->DP |= DP_SYNC_HS_HIGH;
966 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
967 intel_dp->DP |= DP_SYNC_VS_HIGH;
968 intel_dp->DP |= DP_LINK_TRAIN_OFF;
969
970 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
971 intel_dp->DP |= DP_ENHANCED_FRAMING;
972
7c62a164 973 if (crtc->pipe == 1)
417e822d 974 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 975 } else {
976 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 977 }
ea9b6006 978
bc7d38a4 979 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 980 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 981}
982
99ea7127
KP		 983#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
984#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
985
986#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
987#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
988
989#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
990#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
991
992static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
993 u32 mask,
994 u32 value)
bd943159 995{
30add22d 996 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 997 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 998 u32 pp_stat_reg, pp_ctrl_reg;
999
bf13e81b
JN		 1000 pp_stat_reg = _pp_stat_reg(intel_dp);
1001 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1002
99ea7127 1003 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1004 mask, value,
1005 I915_READ(pp_stat_reg),
1006 I915_READ(pp_ctrl_reg));
32ce697c 1007
453c5420 1008 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1009 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1010 I915_READ(pp_stat_reg),
1011 I915_READ(pp_ctrl_reg));
32ce697c 1012 }
99ea7127 1013}
32ce697c 1014
99ea7127
KP		 1015static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1016{
1017 DRM_DEBUG_KMS("Wait for panel power on\n");
1018 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1019}
1020
99ea7127
KP		 1021static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1022{
1023 DRM_DEBUG_KMS("Wait for panel power off time\n");
1024 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1025}
1026
1027static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1028{
1029 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1030 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1031}
1032
1033
832dd3c1
KP		 1034/* Read the current pp_control value, unlocking the register if it
1035 * is locked
1036 */
1037
453c5420 1038static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1039{
453c5420
JB		 1040 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1041 struct drm_i915_private *dev_priv = dev->dev_private;
1042 u32 control;
832dd3c1 1043
bf13e81b 1044 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1045 control &= ~PANEL_UNLOCK_MASK;
1046 control |= PANEL_UNLOCK_REGS;
1047 return control;
bd943159
KP		 1048}
1049
82a4d9c0 1050void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1051{
30add22d 1052 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1053 struct drm_i915_private *dev_priv = dev->dev_private;
1054 u32 pp;
453c5420 1055 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1056
97af61f5
KP		 1057 if (!is_edp(intel_dp))
1058 return;
f01eca2e 1059 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1060
bd943159
KP		 1061 WARN(intel_dp->want_panel_vdd,
1062 "eDP VDD already requested on\n");
1063
1064 intel_dp->want_panel_vdd = true;
99ea7127 1065
bd943159
KP		 1066 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1067 DRM_DEBUG_KMS("eDP VDD already on\n");
1068 return;
1069 }
1070
99ea7127
KP		 1071 if (!ironlake_edp_have_panel_power(intel_dp))
1072 ironlake_wait_panel_power_cycle(intel_dp);
1073
453c5420 1074 pp = ironlake_get_pp_control(intel_dp);
5d613501 1075 pp |= EDP_FORCE_VDD;
ebf33b18 1076
bf13e81b
JN		 1077 pp_stat_reg = _pp_stat_reg(intel_dp);
1078 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1079
1080 I915_WRITE(pp_ctrl_reg, pp);
1081 POSTING_READ(pp_ctrl_reg);
1082 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1083 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1084 /*
1085 * If the panel wasn't on, delay before accessing aux channel
1086 */
1087 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1088 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1089 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1090 }
5d613501
JB		 1091}
1092
bd943159 1093static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1094{
30add22d 1095 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1096 struct drm_i915_private *dev_priv = dev->dev_private;
1097 u32 pp;
453c5420 1098 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1099
a0e99e68
DV		 1100 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1101
bd943159 1102 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
453c5420 1103 pp = ironlake_get_pp_control(intel_dp);
bd943159 1104 pp &= ~EDP_FORCE_VDD;
bd943159 1105
bf13e81b
JN		 1106 pp_stat_reg = _pp_ctrl_reg(intel_dp);
1107 pp_ctrl_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1108
1109 I915_WRITE(pp_ctrl_reg, pp);
1110 POSTING_READ(pp_ctrl_reg);
99ea7127 1111
453c5420
JB		 1112 /* Make sure sequencer is idle before allowing subsequent activity */
1113 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1114 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
99ea7127 1115 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1116 }
1117}
5d613501 1118
bd943159
KP		 1119static void ironlake_panel_vdd_work(struct work_struct *__work)
1120{
1121 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1122 struct intel_dp, panel_vdd_work);
30add22d 1123 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1124
627f7675 1125 mutex_lock(&dev->mode_config.mutex);
bd943159 1126 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1127 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1128}
1129
82a4d9c0 1130void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1131{
97af61f5
KP		 1132 if (!is_edp(intel_dp))
1133 return;
5d613501 1134
bd943159
KP		 1135 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1136 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1137
bd943159
KP		 1138 intel_dp->want_panel_vdd = false;
1139
1140 if (sync) {
1141 ironlake_panel_vdd_off_sync(intel_dp);
1142 } else {
1143 /*
1144 * Queue the timer to fire a long
1145 * time from now (relative to the power down delay)
1146 * to keep the panel power up across a sequence of operations
1147 */
1148 schedule_delayed_work(&intel_dp->panel_vdd_work,
1149 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1150 }
5d613501
JB		 1151}
1152
82a4d9c0 1153void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1154{
30add22d 1155 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1156 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1157 u32 pp;
453c5420 1158 u32 pp_ctrl_reg;
9934c132 1159
97af61f5 1160 if (!is_edp(intel_dp))
bd943159 1161 return;
99ea7127
KP		 1162
1163 DRM_DEBUG_KMS("Turn eDP power on\n");
1164
1165 if (ironlake_edp_have_panel_power(intel_dp)) {
1166 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1167 return;
99ea7127 1168 }
9934c132 1169
99ea7127 1170 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1171
bf13e81b 1172 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1173 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1174 if (IS_GEN5(dev)) {
1175 /* ILK workaround: disable reset around power sequence */
1176 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1177 I915_WRITE(pp_ctrl_reg, pp);
1178 POSTING_READ(pp_ctrl_reg);
05ce1a49 1179 }
37c6c9b0 1180
1c0ae80a 1181 pp |= POWER_TARGET_ON;
99ea7127
KP		 1182 if (!IS_GEN5(dev))
1183 pp |= PANEL_POWER_RESET;
1184
453c5420
JB		 1185 I915_WRITE(pp_ctrl_reg, pp);
1186 POSTING_READ(pp_ctrl_reg);
9934c132 1187
99ea7127 1188 ironlake_wait_panel_on(intel_dp);
9934c132 1189
05ce1a49
KP		 1190 if (IS_GEN5(dev)) {
1191 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1192 I915_WRITE(pp_ctrl_reg, pp);
1193 POSTING_READ(pp_ctrl_reg);
05ce1a49 1194 }
9934c132
JB		 1195}
1196
82a4d9c0 1197void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1198{
30add22d 1199 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1200 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1201 u32 pp;
453c5420 1202 u32 pp_ctrl_reg;
9934c132 1203
97af61f5
KP		 1204 if (!is_edp(intel_dp))
1205 return;
37c6c9b0 1206
99ea7127 1207 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1208
6cb49835 1209 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1210
453c5420 1211 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1212 /* We need to switch off panel power _and_ force vdd, for otherwise some
1213 * panels get very unhappy and cease to work. */
1214 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
453c5420 1215
bf13e81b 1216 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1217
1218 I915_WRITE(pp_ctrl_reg, pp);
1219 POSTING_READ(pp_ctrl_reg);
9934c132 1220
35a38556
DV		 1221 intel_dp->want_panel_vdd = false;
1222
99ea7127 1223 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1224}
1225
d6c50ff8 1226void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1227{
da63a9f2
PZ		 1228 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1229 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1230 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1231 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658 1232 u32 pp;
453c5420 1233 u32 pp_ctrl_reg;
32f9d658 1234
f01eca2e
KP		 1235 if (!is_edp(intel_dp))
1236 return;
1237
28c97730 1238 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1239 /*
1240 * If we enable the backlight right away following a panel power
1241 * on, we may see slight flicker as the panel syncs with the eDP
1242 * link. So delay a bit to make sure the image is solid before
1243 * allowing it to appear.
1244 */
f01eca2e 1245 msleep(intel_dp->backlight_on_delay);
453c5420 1246 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1247 pp |= EDP_BLC_ENABLE;
453c5420 1248
bf13e81b 1249 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1250
1251 I915_WRITE(pp_ctrl_reg, pp);
1252 POSTING_READ(pp_ctrl_reg);
035aa3de
DV		 1253
1254 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1255}
1256
d6c50ff8 1257void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1258{
30add22d 1259 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1260 struct drm_i915_private *dev_priv = dev->dev_private;
1261 u32 pp;
453c5420 1262 u32 pp_ctrl_reg;
32f9d658 1263
f01eca2e
KP		 1264 if (!is_edp(intel_dp))
1265 return;
1266
035aa3de
DV		 1267 intel_panel_disable_backlight(dev);
1268
28c97730 1269 DRM_DEBUG_KMS("\n");
453c5420 1270 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1271 pp &= ~EDP_BLC_ENABLE;
453c5420 1272
bf13e81b 1273 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1274
1275 I915_WRITE(pp_ctrl_reg, pp);
1276 POSTING_READ(pp_ctrl_reg);
f01eca2e 1277 msleep(intel_dp->backlight_off_delay);
32f9d658 1278}
a4fc5ed6 1279
2bd2ad64 1280static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1281{
da63a9f2
PZ		 1282 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1283 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1284 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1285 struct drm_i915_private *dev_priv = dev->dev_private;
1286 u32 dpa_ctl;
1287
2bd2ad64
DV		 1288 assert_pipe_disabled(dev_priv,
1289 to_intel_crtc(crtc)->pipe);
1290
d240f20f
JB		 1291 DRM_DEBUG_KMS("\n");
1292 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1293 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1294 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1295
1296 /* We don't adjust intel_dp->DP while tearing down the link, to
1297 * facilitate link retraining (e.g. after hotplug). Hence clear all
1298 * enable bits here to ensure that we don't enable too much. */
1299 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1300 intel_dp->DP |= DP_PLL_ENABLE;
1301 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1302 POSTING_READ(DP_A);
1303 udelay(200);
d240f20f
JB		 1304}
1305
2bd2ad64 1306static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1307{
da63a9f2
PZ		 1308 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1309 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1310 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1311 struct drm_i915_private *dev_priv = dev->dev_private;
1312 u32 dpa_ctl;
1313
2bd2ad64
DV		 1314 assert_pipe_disabled(dev_priv,
1315 to_intel_crtc(crtc)->pipe);
1316
d240f20f 1317 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1318 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1319 "dp pll off, should be on\n");
1320 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1321
1322 /* We can't rely on the value tracked for the DP register in
1323 * intel_dp->DP because link_down must not change that (otherwise link
1324 * re-training will fail. */
298b0b39 1325 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1326 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1327 POSTING_READ(DP_A);
d240f20f
JB		 1328 udelay(200);
1329}
1330
c7ad3810 1331/* If the sink supports it, try to set the power state appropriately */
c19b0669 1332void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1333{
1334 int ret, i;
1335
1336 /* Should have a valid DPCD by this point */
1337 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1338 return;
1339
1340 if (mode != DRM_MODE_DPMS_ON) {
1341 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1342 DP_SET_POWER_D3);
1343 if (ret != 1)
1344 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1345 } else {
1346 /*
1347 * When turning on, we need to retry for 1ms to give the sink
1348 * time to wake up.
1349 */
1350 for (i = 0; i < 3; i++) {
1351 ret = intel_dp_aux_native_write_1(intel_dp,
1352 DP_SET_POWER,
1353 DP_SET_POWER_D0);
1354 if (ret == 1)
1355 break;
1356 msleep(1);
1357 }
1358 }
1359}
1360
19d8fe15
DV		 1361static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1362 enum pipe *pipe)
d240f20f 1363{
19d8fe15 1364 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1365 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1366 struct drm_device *dev = encoder->base.dev;
1367 struct drm_i915_private *dev_priv = dev->dev_private;
1368 u32 tmp = I915_READ(intel_dp->output_reg);
1369
1370 if (!(tmp & DP_PORT_EN))
1371 return false;
1372
bc7d38a4 1373 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1374 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1375 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1376 *pipe = PORT_TO_PIPE(tmp);
1377 } else {
1378 u32 trans_sel;
1379 u32 trans_dp;
1380 int i;
1381
1382 switch (intel_dp->output_reg) {
1383 case PCH_DP_B:
1384 trans_sel = TRANS_DP_PORT_SEL_B;
1385 break;
1386 case PCH_DP_C:
1387 trans_sel = TRANS_DP_PORT_SEL_C;
1388 break;
1389 case PCH_DP_D:
1390 trans_sel = TRANS_DP_PORT_SEL_D;
1391 break;
1392 default:
1393 return true;
1394 }
1395
1396 for_each_pipe(i) {
1397 trans_dp = I915_READ(TRANS_DP_CTL(i));
1398 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1399 *pipe = i;
1400 return true;
1401 }
1402 }
19d8fe15 1403
4a0833ec
DV		 1404 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1405 intel_dp->output_reg);
1406 }
d240f20f 1407
19d8fe15
DV		 1408 return true;
1409}
d240f20f 1410
045ac3b5
JB		 1411static void intel_dp_get_config(struct intel_encoder *encoder,
1412 struct intel_crtc_config *pipe_config)
1413{
1414 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1415 u32 tmp, flags = 0;
63000ef6
XZ		 1416 struct drm_device *dev = encoder->base.dev;
1417 struct drm_i915_private *dev_priv = dev->dev_private;
1418 enum port port = dp_to_dig_port(intel_dp)->port;
1419 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1420 int dotclock;
045ac3b5 1421
63000ef6
XZ		 1422 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1423 tmp = I915_READ(intel_dp->output_reg);
1424 if (tmp & DP_SYNC_HS_HIGH)
1425 flags |= DRM_MODE_FLAG_PHSYNC;
1426 else
1427 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1428
63000ef6
XZ		 1429 if (tmp & DP_SYNC_VS_HIGH)
1430 flags |= DRM_MODE_FLAG_PVSYNC;
1431 else
1432 flags |= DRM_MODE_FLAG_NVSYNC;
1433 } else {
1434 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1435 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1436 flags |= DRM_MODE_FLAG_PHSYNC;
1437 else
1438 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1439
63000ef6
XZ		 1440 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1441 flags |= DRM_MODE_FLAG_PVSYNC;
1442 else
1443 flags |= DRM_MODE_FLAG_NVSYNC;
1444 }
045ac3b5
JB		 1445
1446 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1447
eb14cb74
VS		 1448 pipe_config->has_dp_encoder = true;
1449
1450 intel_dp_get_m_n(crtc, pipe_config);
1451
18442d08 1452 if (port == PORT_A) {
f1f644dc
JB		 1453 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1454 pipe_config->port_clock = 162000;
1455 else
1456 pipe_config->port_clock = 270000;
1457 }
18442d08
VS		 1458
1459 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1460 &pipe_config->dp_m_n);
1461
1462 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1463 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1464
1465 pipe_config->adjusted_mode.clock = dotclock;
045ac3b5
JB		 1466}
1467
2293bb5c
SK		 1468static bool is_edp_psr(struct intel_dp *intel_dp)
1469{
1470 return is_edp(intel_dp) &&
1471 intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1472}
1473
2b28bb1b
RV		 1474static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1475{
1476 struct drm_i915_private *dev_priv = dev->dev_private;
1477
1478 if (!IS_HASWELL(dev))
1479 return false;
1480
1481 return I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
1482}
1483
1484static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1485 struct edp_vsc_psr *vsc_psr)
1486{
1487 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1488 struct drm_device *dev = dig_port->base.base.dev;
1489 struct drm_i915_private *dev_priv = dev->dev_private;
1490 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1491 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1492 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1493 uint32_t *data = (uint32_t *) vsc_psr;
1494 unsigned int i;
1495
1496 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1497 the video DIP being updated before program video DIP data buffer
1498 registers for DIP being updated. */
1499 I915_WRITE(ctl_reg, 0);
1500 POSTING_READ(ctl_reg);
1501
1502 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1503 if (i < sizeof(struct edp_vsc_psr))
1504 I915_WRITE(data_reg + i, *data++);
1505 else
1506 I915_WRITE(data_reg + i, 0);
1507 }
1508
1509 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1510 POSTING_READ(ctl_reg);
1511}
1512
1513static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1514{
1515 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1516 struct drm_i915_private *dev_priv = dev->dev_private;
1517 struct edp_vsc_psr psr_vsc;
1518
1519 if (intel_dp->psr_setup_done)
1520 return;
1521
1522 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1523 memset(&psr_vsc, 0, sizeof(psr_vsc));
1524 psr_vsc.sdp_header.HB0 = 0;
1525 psr_vsc.sdp_header.HB1 = 0x7;
1526 psr_vsc.sdp_header.HB2 = 0x2;
1527 psr_vsc.sdp_header.HB3 = 0x8;
1528 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1529
1530 /* Avoid continuous PSR exit by masking memup and hpd */
1531 I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
1532 EDP_PSR_DEBUG_MASK_HPD);
1533
1534 intel_dp->psr_setup_done = true;
1535}
1536
1537static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1538{
1539 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1540 struct drm_i915_private *dev_priv = dev->dev_private;
bc86625a 1541 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
2b28bb1b
RV		 1542 int precharge = 0x3;
1543 int msg_size = 5; /* Header(4) + Message(1) */
1544
1545 /* Enable PSR in sink */
1546 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1547 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1548 DP_PSR_ENABLE &
1549 ~DP_PSR_MAIN_LINK_ACTIVE);
1550 else
1551 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1552 DP_PSR_ENABLE |
1553 DP_PSR_MAIN_LINK_ACTIVE);
1554
1555 /* Setup AUX registers */
1556 I915_WRITE(EDP_PSR_AUX_DATA1, EDP_PSR_DPCD_COMMAND);
1557 I915_WRITE(EDP_PSR_AUX_DATA2, EDP_PSR_DPCD_NORMAL_OPERATION);
1558 I915_WRITE(EDP_PSR_AUX_CTL,
1559 DP_AUX_CH_CTL_TIME_OUT_400us |
1560 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1561 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1562 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1563}
1564
1565static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1566{
1567 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1568 struct drm_i915_private *dev_priv = dev->dev_private;
1569 uint32_t max_sleep_time = 0x1f;
1570 uint32_t idle_frames = 1;
1571 uint32_t val = 0x0;
1572
1573 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1574 val |= EDP_PSR_LINK_STANDBY;
1575 val |= EDP_PSR_TP2_TP3_TIME_0us;
1576 val |= EDP_PSR_TP1_TIME_0us;
1577 val |= EDP_PSR_SKIP_AUX_EXIT;
1578 } else
1579 val |= EDP_PSR_LINK_DISABLE;
1580
1581 I915_WRITE(EDP_PSR_CTL, val |
1582 EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
1583 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1584 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1585 EDP_PSR_ENABLE);
1586}
1587
3f51e471
RV		 1588static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1589{
1590 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1591 struct drm_device *dev = dig_port->base.base.dev;
1592 struct drm_i915_private *dev_priv = dev->dev_private;
1593 struct drm_crtc *crtc = dig_port->base.base.crtc;
1594 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1595 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1596 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1597
1598 if (!IS_HASWELL(dev)) {
1599 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1600 dev_priv->no_psr_reason = PSR_NO_SOURCE;
1601 return false;
1602 }
1603
1604 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1605 (dig_port->port != PORT_A)) {
1606 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1607 dev_priv->no_psr_reason = PSR_HSW_NOT_DDIA;
1608 return false;
1609 }
1610
1611 if (!is_edp_psr(intel_dp)) {
1612 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1613 dev_priv->no_psr_reason = PSR_NO_SINK;
1614 return false;
1615 }
1616
105b7c11
RV		 1617 if (!i915_enable_psr) {
1618 DRM_DEBUG_KMS("PSR disable by flag\n");
1619 dev_priv->no_psr_reason = PSR_MODULE_PARAM;
1620 return false;
1621 }
1622
cd234b0b
CW		 1623 crtc = dig_port->base.base.crtc;
1624 if (crtc == NULL) {
1625 DRM_DEBUG_KMS("crtc not active for PSR\n");
1626 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1627 return false;
1628 }
1629
1630 intel_crtc = to_intel_crtc(crtc);
20ddf665 1631 if (!intel_crtc_active(crtc)) {
3f51e471
RV		 1632 DRM_DEBUG_KMS("crtc not active for PSR\n");
1633 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1634 return false;
1635 }
1636
cd234b0b 1637 obj = to_intel_framebuffer(crtc->fb)->obj;
3f51e471
RV		 1638 if (obj->tiling_mode != I915_TILING_X ||
1639 obj->fence_reg == I915_FENCE_REG_NONE) {
1640 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1641 dev_priv->no_psr_reason = PSR_NOT_TILED;
1642 return false;
1643 }
1644
1645 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1646 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1647 dev_priv->no_psr_reason = PSR_SPRITE_ENABLED;
1648 return false;
1649 }
1650
1651 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1652 S3D_ENABLE) {
1653 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1654 dev_priv->no_psr_reason = PSR_S3D_ENABLED;
1655 return false;
1656 }
1657
ca73b4f0 1658 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471
RV		 1659 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1660 dev_priv->no_psr_reason = PSR_INTERLACED_ENABLED;
1661 return false;
1662 }
1663
1664 return true;
1665}
1666
3d739d92 1667static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1668{
1669 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1670
3f51e471
RV		 1671 if (!intel_edp_psr_match_conditions(intel_dp) ||
1672 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1673 return;
1674
1675 /* Setup PSR once */
1676 intel_edp_psr_setup(intel_dp);
1677
1678 /* Enable PSR on the panel */
1679 intel_edp_psr_enable_sink(intel_dp);
1680
1681 /* Enable PSR on the host */
1682 intel_edp_psr_enable_source(intel_dp);
1683}
1684
3d739d92
RV		 1685void intel_edp_psr_enable(struct intel_dp *intel_dp)
1686{
1687 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1688
1689 if (intel_edp_psr_match_conditions(intel_dp) &&
1690 !intel_edp_is_psr_enabled(dev))
1691 intel_edp_psr_do_enable(intel_dp);
1692}
1693
2b28bb1b
RV		 1694void intel_edp_psr_disable(struct intel_dp *intel_dp)
1695{
1696 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1697 struct drm_i915_private *dev_priv = dev->dev_private;
1698
1699 if (!intel_edp_is_psr_enabled(dev))
1700 return;
1701
1702 I915_WRITE(EDP_PSR_CTL, I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
1703
1704 /* Wait till PSR is idle */
1705 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
1706 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1707 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1708}
1709
3d739d92
RV		 1710void intel_edp_psr_update(struct drm_device *dev)
1711{
1712 struct intel_encoder *encoder;
1713 struct intel_dp *intel_dp = NULL;
1714
1715 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1716 if (encoder->type == INTEL_OUTPUT_EDP) {
1717 intel_dp = enc_to_intel_dp(&encoder->base);
1718
1719 if (!is_edp_psr(intel_dp))
1720 return;
1721
1722 if (!intel_edp_psr_match_conditions(intel_dp))
1723 intel_edp_psr_disable(intel_dp);
1724 else
1725 if (!intel_edp_is_psr_enabled(dev))
1726 intel_edp_psr_do_enable(intel_dp);
1727 }
1728}
1729
e8cb4558 1730static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1731{
e8cb4558 1732 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1733 enum port port = dp_to_dig_port(intel_dp)->port;
1734 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1735
1736 /* Make sure the panel is off before trying to change the mode. But also
1737 * ensure that we have vdd while we switch off the panel. */
1738 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1739 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1740 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1741 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1742
1743 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1744 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1745 intel_dp_link_down(intel_dp);
d240f20f
JB		 1746}
1747
2bd2ad64 1748static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1749{
2bd2ad64 1750 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1751 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1752 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1753
982a3866 1754 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1755 intel_dp_link_down(intel_dp);
b2634017
JB		 1756 if (!IS_VALLEYVIEW(dev))
1757 ironlake_edp_pll_off(intel_dp);
3739850b 1758 }
2bd2ad64
DV		 1759}
1760
e8cb4558 1761static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1762{
e8cb4558
DV		 1763 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1764 struct drm_device *dev = encoder->base.dev;
1765 struct drm_i915_private *dev_priv = dev->dev_private;
1766 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1767
0c33d8d7
DV		 1768 if (WARN_ON(dp_reg & DP_PORT_EN))
1769 return;
5d613501 1770
97af61f5 1771 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1772 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1773 intel_dp_start_link_train(intel_dp);
97af61f5 1774 ironlake_edp_panel_on(intel_dp);
bd943159 1775 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1776 intel_dp_complete_link_train(intel_dp);
3ab9c637 1777 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1778}
89b667f8 1779
ecff4f3b
JN		 1780static void g4x_enable_dp(struct intel_encoder *encoder)
1781{
828f5c6e
JN		 1782 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1783
ecff4f3b 1784 intel_enable_dp(encoder);
828f5c6e 1785 ironlake_edp_backlight_on(intel_dp);
ecff4f3b
JN		 1786}
1787
ab1f90f9
JN		 1788static void vlv_enable_dp(struct intel_encoder *encoder)
1789{
828f5c6e
JN		 1790 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1791
1792 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1793}
1794
ecff4f3b 1795static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1796{
1797 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1798 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1799
1800 if (dport->port == PORT_A)
1801 ironlake_edp_pll_on(intel_dp);
1802}
1803
1804static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1805{
2bd2ad64 1806 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1807 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1808 struct drm_device *dev = encoder->base.dev;
89b667f8 1809 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9
JN		 1810 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1811 int port = vlv_dport_to_channel(dport);
1812 int pipe = intel_crtc->pipe;
bf13e81b 1813 struct edp_power_seq power_seq;
ab1f90f9 1814 u32 val;
a4fc5ed6 1815
ab1f90f9 1816 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1817
5e69f97f 1818 val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port));
ab1f90f9
JN		 1819 val = 0;
1820 if (pipe)
1821 val |= (1<<21);
1822 else
1823 val &= ~(1<<21);
1824 val |= 0x001000c4;
5e69f97f
CML		 1825 vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val);
1826 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
1827 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
89b667f8 1828
ab1f90f9
JN		 1829 mutex_unlock(&dev_priv->dpio_lock);
1830
bf13e81b
JN		 1831 /* init power sequencer on this pipe and port */
1832 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1833 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1834 &power_seq);
1835
ab1f90f9
JN		 1836 intel_enable_dp(encoder);
1837
1838 vlv_wait_port_ready(dev_priv, port);
89b667f8
JB		 1839}
1840
ecff4f3b 1841static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1842{
1843 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1844 struct drm_device *dev = encoder->base.dev;
1845 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1846 struct intel_crtc *intel_crtc =
1847 to_intel_crtc(encoder->base.crtc);
89b667f8 1848 int port = vlv_dport_to_channel(dport);
5e69f97f 1849 int pipe = intel_crtc->pipe;
89b667f8 1850
89b667f8 1851 /* Program Tx lane resets to default */
0980a60f 1852 mutex_lock(&dev_priv->dpio_lock);
5e69f97f 1853 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port),
89b667f8
JB		 1854 DPIO_PCS_TX_LANE2_RESET |
1855 DPIO_PCS_TX_LANE1_RESET);
5e69f97f 1856 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port),
89b667f8
JB		 1857 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1858 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1859 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1860 DPIO_PCS_CLK_SOFT_RESET);
1861
1862 /* Fix up inter-pair skew failure */
5e69f97f
CML		 1863 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00);
1864 vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500);
1865 vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000);
0980a60f 1866 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 1867}
1868
1869/*
df0c237d
JB		 1870 * Native read with retry for link status and receiver capability reads for
1871 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1872 */
1873static bool
df0c237d
JB		 1874intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1875 uint8_t *recv, int recv_bytes)
a4fc5ed6 1876{
61da5fab
JB		 1877 int ret, i;
1878
df0c237d
JB		 1879 /*
1880 * Sinks are *supposed* to come up within 1ms from an off state,
1881 * but we're also supposed to retry 3 times per the spec.
1882 */
61da5fab 1883 for (i = 0; i < 3; i++) {
df0c237d
JB		 1884 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1885 recv_bytes);
1886 if (ret == recv_bytes)
61da5fab
JB		 1887 return true;
1888 msleep(1);
1889 }
a4fc5ed6 1890
61da5fab 1891 return false;
a4fc5ed6
KP		 1892}
1893
1894/*
1895 * Fetch AUX CH registers 0x202 - 0x207 which contain
1896 * link status information
1897 */
1898static bool
93f62dad 1899intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1900{
df0c237d
JB		 1901 return intel_dp_aux_native_read_retry(intel_dp,
1902 DP_LANE0_1_STATUS,
93f62dad 1903 link_status,
df0c237d 1904 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1905}
1906
a4fc5ed6
KP		 1907#if 0
1908static char *voltage_names[] = {
1909 "0.4V", "0.6V", "0.8V", "1.2V"
1910};
1911static char *pre_emph_names[] = {
1912 "0dB", "3.5dB", "6dB", "9.5dB"
1913};
1914static char *link_train_names[] = {
1915 "pattern 1", "pattern 2", "idle", "off"
1916};
1917#endif
1918
1919/*
1920 * These are source-specific values; current Intel hardware supports
1921 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1922 */
a4fc5ed6
KP		 1923
1924static uint8_t
1a2eb460 1925intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1926{
30add22d 1927 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1928 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1929
e2fa6fba
P		 1930 if (IS_VALLEYVIEW(dev))
1931 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 1932 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 1933 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 1934 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 1935 return DP_TRAIN_VOLTAGE_SWING_1200;
1936 else
1937 return DP_TRAIN_VOLTAGE_SWING_800;
1938}
1939
1940static uint8_t
1941intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1942{
30add22d 1943 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1944 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1945
22b8bf17 1946 if (HAS_DDI(dev)) {
d6c0d722
PZ		 1947 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1948 case DP_TRAIN_VOLTAGE_SWING_400:
1949 return DP_TRAIN_PRE_EMPHASIS_9_5;
1950 case DP_TRAIN_VOLTAGE_SWING_600:
1951 return DP_TRAIN_PRE_EMPHASIS_6;
1952 case DP_TRAIN_VOLTAGE_SWING_800:
1953 return DP_TRAIN_PRE_EMPHASIS_3_5;
1954 case DP_TRAIN_VOLTAGE_SWING_1200:
1955 default:
1956 return DP_TRAIN_PRE_EMPHASIS_0;
1957 }
e2fa6fba
P		 1958 } else if (IS_VALLEYVIEW(dev)) {
1959 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1960 case DP_TRAIN_VOLTAGE_SWING_400:
1961 return DP_TRAIN_PRE_EMPHASIS_9_5;
1962 case DP_TRAIN_VOLTAGE_SWING_600:
1963 return DP_TRAIN_PRE_EMPHASIS_6;
1964 case DP_TRAIN_VOLTAGE_SWING_800:
1965 return DP_TRAIN_PRE_EMPHASIS_3_5;
1966 case DP_TRAIN_VOLTAGE_SWING_1200:
1967 default:
1968 return DP_TRAIN_PRE_EMPHASIS_0;
1969 }
bc7d38a4 1970 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1971 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1972 case DP_TRAIN_VOLTAGE_SWING_400:
1973 return DP_TRAIN_PRE_EMPHASIS_6;
1974 case DP_TRAIN_VOLTAGE_SWING_600:
1975 case DP_TRAIN_VOLTAGE_SWING_800:
1976 return DP_TRAIN_PRE_EMPHASIS_3_5;
1977 default:
1978 return DP_TRAIN_PRE_EMPHASIS_0;
1979 }
1980 } else {
1981 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1982 case DP_TRAIN_VOLTAGE_SWING_400:
1983 return DP_TRAIN_PRE_EMPHASIS_6;
1984 case DP_TRAIN_VOLTAGE_SWING_600:
1985 return DP_TRAIN_PRE_EMPHASIS_6;
1986 case DP_TRAIN_VOLTAGE_SWING_800:
1987 return DP_TRAIN_PRE_EMPHASIS_3_5;
1988 case DP_TRAIN_VOLTAGE_SWING_1200:
1989 default:
1990 return DP_TRAIN_PRE_EMPHASIS_0;
1991 }
a4fc5ed6
KP		 1992 }
1993}
1994
e2fa6fba
P		 1995static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1996{
1997 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1998 struct drm_i915_private *dev_priv = dev->dev_private;
1999 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2000 struct intel_crtc *intel_crtc =
2001 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2002 unsigned long demph_reg_value, preemph_reg_value,
2003 uniqtranscale_reg_value;
2004 uint8_t train_set = intel_dp->train_set[0];
cece5d58 2005 int port = vlv_dport_to_channel(dport);
5e69f97f 2006 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2007
2008 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2009 case DP_TRAIN_PRE_EMPHASIS_0:
2010 preemph_reg_value = 0x0004000;
2011 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2012 case DP_TRAIN_VOLTAGE_SWING_400:
2013 demph_reg_value = 0x2B405555;
2014 uniqtranscale_reg_value = 0x552AB83A;
2015 break;
2016 case DP_TRAIN_VOLTAGE_SWING_600:
2017 demph_reg_value = 0x2B404040;
2018 uniqtranscale_reg_value = 0x5548B83A;
2019 break;
2020 case DP_TRAIN_VOLTAGE_SWING_800:
2021 demph_reg_value = 0x2B245555;
2022 uniqtranscale_reg_value = 0x5560B83A;
2023 break;
2024 case DP_TRAIN_VOLTAGE_SWING_1200:
2025 demph_reg_value = 0x2B405555;
2026 uniqtranscale_reg_value = 0x5598DA3A;
2027 break;
2028 default:
2029 return 0;
2030 }
2031 break;
2032 case DP_TRAIN_PRE_EMPHASIS_3_5:
2033 preemph_reg_value = 0x0002000;
2034 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2035 case DP_TRAIN_VOLTAGE_SWING_400:
2036 demph_reg_value = 0x2B404040;
2037 uniqtranscale_reg_value = 0x5552B83A;
2038 break;
2039 case DP_TRAIN_VOLTAGE_SWING_600:
2040 demph_reg_value = 0x2B404848;
2041 uniqtranscale_reg_value = 0x5580B83A;
2042 break;
2043 case DP_TRAIN_VOLTAGE_SWING_800:
2044 demph_reg_value = 0x2B404040;
2045 uniqtranscale_reg_value = 0x55ADDA3A;
2046 break;
2047 default:
2048 return 0;
2049 }
2050 break;
2051 case DP_TRAIN_PRE_EMPHASIS_6:
2052 preemph_reg_value = 0x0000000;
2053 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2054 case DP_TRAIN_VOLTAGE_SWING_400:
2055 demph_reg_value = 0x2B305555;
2056 uniqtranscale_reg_value = 0x5570B83A;
2057 break;
2058 case DP_TRAIN_VOLTAGE_SWING_600:
2059 demph_reg_value = 0x2B2B4040;
2060 uniqtranscale_reg_value = 0x55ADDA3A;
2061 break;
2062 default:
2063 return 0;
2064 }
2065 break;
2066 case DP_TRAIN_PRE_EMPHASIS_9_5:
2067 preemph_reg_value = 0x0006000;
2068 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2069 case DP_TRAIN_VOLTAGE_SWING_400:
2070 demph_reg_value = 0x1B405555;
2071 uniqtranscale_reg_value = 0x55ADDA3A;
2072 break;
2073 default:
2074 return 0;
2075 }
2076 break;
2077 default:
2078 return 0;
2079 }
2080
0980a60f 2081 mutex_lock(&dev_priv->dpio_lock);
5e69f97f
CML		 2082 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x00000000);
2083 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port), demph_reg_value);
2084 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port),
e2fa6fba 2085 uniqtranscale_reg_value);
5e69f97f
CML		 2086 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port), 0x0C782040);
2087 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000);
2088 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
2089 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x80000000);
0980a60f 2090 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2091
2092 return 0;
2093}
2094
a4fc5ed6 2095static void
93f62dad 2096intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2097{
2098 uint8_t v = 0;
2099 uint8_t p = 0;
2100 int lane;
1a2eb460
KP		 2101 uint8_t voltage_max;
2102 uint8_t preemph_max;
a4fc5ed6 2103
33a34e4e 2104 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2105 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2106 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2107
2108 if (this_v > v)
2109 v = this_v;
2110 if (this_p > p)
2111 p = this_p;
2112 }
2113
1a2eb460 2114 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2115 if (v >= voltage_max)
2116 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2117
1a2eb460
KP		 2118 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2119 if (p >= preemph_max)
2120 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2121
2122 for (lane = 0; lane < 4; lane++)
33a34e4e 2123 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2124}
2125
2126static uint32_t
f0a3424e 2127intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2128{
3cf2efb1 2129 uint32_t signal_levels = 0;
a4fc5ed6 2130
3cf2efb1 2131 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2132 case DP_TRAIN_VOLTAGE_SWING_400:
2133 default:
2134 signal_levels |= DP_VOLTAGE_0_4;
2135 break;
2136 case DP_TRAIN_VOLTAGE_SWING_600:
2137 signal_levels |= DP_VOLTAGE_0_6;
2138 break;
2139 case DP_TRAIN_VOLTAGE_SWING_800:
2140 signal_levels |= DP_VOLTAGE_0_8;
2141 break;
2142 case DP_TRAIN_VOLTAGE_SWING_1200:
2143 signal_levels |= DP_VOLTAGE_1_2;
2144 break;
2145 }
3cf2efb1 2146 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2147 case DP_TRAIN_PRE_EMPHASIS_0:
2148 default:
2149 signal_levels |= DP_PRE_EMPHASIS_0;
2150 break;
2151 case DP_TRAIN_PRE_EMPHASIS_3_5:
2152 signal_levels |= DP_PRE_EMPHASIS_3_5;
2153 break;
2154 case DP_TRAIN_PRE_EMPHASIS_6:
2155 signal_levels |= DP_PRE_EMPHASIS_6;
2156 break;
2157 case DP_TRAIN_PRE_EMPHASIS_9_5:
2158 signal_levels |= DP_PRE_EMPHASIS_9_5;
2159 break;
2160 }
2161 return signal_levels;
2162}
2163
e3421a18
ZW		 2164/* Gen6's DP voltage swing and pre-emphasis control */
2165static uint32_t
2166intel_gen6_edp_signal_levels(uint8_t train_set)
2167{
3c5a62b5
YL		 2168 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2169 DP_TRAIN_PRE_EMPHASIS_MASK);
2170 switch (signal_levels) {
e3421a18 2171 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2172 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2173 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2174 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2175 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2176 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2177 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2178 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2179 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2180 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2181 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2182 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2183 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2184 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2185 default:
3c5a62b5
YL		 2186 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2187 "0x%x\n", signal_levels);
2188 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2189 }
2190}
2191
1a2eb460
KP		 2192/* Gen7's DP voltage swing and pre-emphasis control */
2193static uint32_t
2194intel_gen7_edp_signal_levels(uint8_t train_set)
2195{
2196 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2197 DP_TRAIN_PRE_EMPHASIS_MASK);
2198 switch (signal_levels) {
2199 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2200 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2201 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2202 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2203 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2204 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2205
2206 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2207 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2208 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2209 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2210
2211 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2212 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2213 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2214 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2215
2216 default:
2217 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2218 "0x%x\n", signal_levels);
2219 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2220 }
2221}
2222
d6c0d722
PZ		 2223/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2224static uint32_t
f0a3424e 2225intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2226{
d6c0d722
PZ		 2227 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2228 DP_TRAIN_PRE_EMPHASIS_MASK);
2229 switch (signal_levels) {
2230 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2231 return DDI_BUF_EMP_400MV_0DB_HSW;
2232 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2233 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2234 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2235 return DDI_BUF_EMP_400MV_6DB_HSW;
2236 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2237 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2238
d6c0d722
PZ		 2239 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2240 return DDI_BUF_EMP_600MV_0DB_HSW;
2241 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2242 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2243 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2244 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2245
d6c0d722
PZ		 2246 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2247 return DDI_BUF_EMP_800MV_0DB_HSW;
2248 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2249 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2250 default:
2251 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2252 "0x%x\n", signal_levels);
2253 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2254 }
a4fc5ed6
KP		 2255}
2256
f0a3424e
PZ		 2257/* Properly updates "DP" with the correct signal levels. */
2258static void
2259intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2260{
2261 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2262 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2263 struct drm_device *dev = intel_dig_port->base.base.dev;
2264 uint32_t signal_levels, mask;
2265 uint8_t train_set = intel_dp->train_set[0];
2266
22b8bf17 2267 if (HAS_DDI(dev)) {
f0a3424e
PZ		 2268 signal_levels = intel_hsw_signal_levels(train_set);
2269 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2270 } else if (IS_VALLEYVIEW(dev)) {
2271 signal_levels = intel_vlv_signal_levels(intel_dp);
2272 mask = 0;
bc7d38a4 2273 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2274 signal_levels = intel_gen7_edp_signal_levels(train_set);
2275 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2276 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2277 signal_levels = intel_gen6_edp_signal_levels(train_set);
2278 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2279 } else {
2280 signal_levels = intel_gen4_signal_levels(train_set);
2281 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2282 }
2283
2284 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2285
2286 *DP = (*DP & ~mask) | signal_levels;
2287}
2288
a4fc5ed6 2289static bool
ea5b213a 2290intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 2291 uint32_t dp_reg_value,
58e10eb9 2292 uint8_t dp_train_pat)
a4fc5ed6 2293{
174edf1f
PZ		 2294 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2295 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2296 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2297 enum port port = intel_dig_port->port;
a4fc5ed6
KP		 2298 int ret;
2299
22b8bf17 2300 if (HAS_DDI(dev)) {
3ab9c637 2301 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2302
2303 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2304 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2305 else
2306 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2307
2308 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2309 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2310 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2311 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2312
2313 break;
2314 case DP_TRAINING_PATTERN_1:
2315 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2316 break;
2317 case DP_TRAINING_PATTERN_2:
2318 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2319 break;
2320 case DP_TRAINING_PATTERN_3:
2321 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2322 break;
2323 }
174edf1f 2324 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2325
bc7d38a4 2326 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
47ea7542
PZ		 2327 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
2328
2329 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2330 case DP_TRAINING_PATTERN_DISABLE:
2331 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
2332 break;
2333 case DP_TRAINING_PATTERN_1:
2334 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
2335 break;
2336 case DP_TRAINING_PATTERN_2:
2337 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2338 break;
2339 case DP_TRAINING_PATTERN_3:
2340 DRM_ERROR("DP training pattern 3 not supported\n");
2341 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2342 break;
2343 }
2344
2345 } else {
2346 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
2347
2348 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2349 case DP_TRAINING_PATTERN_DISABLE:
2350 dp_reg_value |= DP_LINK_TRAIN_OFF;
2351 break;
2352 case DP_TRAINING_PATTERN_1:
2353 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
2354 break;
2355 case DP_TRAINING_PATTERN_2:
2356 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2357 break;
2358 case DP_TRAINING_PATTERN_3:
2359 DRM_ERROR("DP training pattern 3 not supported\n");
2360 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2361 break;
2362 }
2363 }
2364
ea5b213a
CW		 2365 I915_WRITE(intel_dp->output_reg, dp_reg_value);
2366 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2367
ea5b213a 2368 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 2369 DP_TRAINING_PATTERN_SET,
2370 dp_train_pat);
2371
47ea7542
PZ		 2372 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
2373 DP_TRAINING_PATTERN_DISABLE) {
2374 ret = intel_dp_aux_native_write(intel_dp,
2375 DP_TRAINING_LANE0_SET,
2376 intel_dp->train_set,
2377 intel_dp->lane_count);
2378 if (ret != intel_dp->lane_count)
2379 return false;
2380 }
a4fc5ed6
KP		 2381
2382 return true;
2383}
2384
3ab9c637
ID		 2385static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2386{
2387 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2388 struct drm_device *dev = intel_dig_port->base.base.dev;
2389 struct drm_i915_private *dev_priv = dev->dev_private;
2390 enum port port = intel_dig_port->port;
2391 uint32_t val;
2392
2393 if (!HAS_DDI(dev))
2394 return;
2395
2396 val = I915_READ(DP_TP_CTL(port));
2397 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2398 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2399 I915_WRITE(DP_TP_CTL(port), val);
2400
2401 /*
2402 * On PORT_A we can have only eDP in SST mode. There the only reason
2403 * we need to set idle transmission mode is to work around a HW issue
2404 * where we enable the pipe while not in idle link-training mode.
2405 * In this case there is requirement to wait for a minimum number of
2406 * idle patterns to be sent.
2407 */
2408 if (port == PORT_A)
2409 return;
2410
2411 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2412 1))
2413 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2414}
2415
33a34e4e 2416/* Enable corresponding port and start training pattern 1 */
c19b0669 2417void
33a34e4e 2418intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2419{
da63a9f2 2420 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2421 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2422 int i;
2423 uint8_t voltage;
cdb0e95b 2424 int voltage_tries, loop_tries;
ea5b213a 2425 uint32_t DP = intel_dp->DP;
a4fc5ed6 2426
affa9354 2427 if (HAS_DDI(dev))
c19b0669
PZ		 2428 intel_ddi_prepare_link_retrain(encoder);
2429
3cf2efb1
CW		 2430 /* Write the link configuration data */
2431 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2432 intel_dp->link_configuration,
2433 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 2434
2435 DP |= DP_PORT_EN;
1a2eb460 2436
33a34e4e 2437 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 2438 voltage = 0xff;
cdb0e95b
KP		 2439 voltage_tries = 0;
2440 loop_tries = 0;
a4fc5ed6 2441 for (;;) {
33a34e4e 2442 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 2443 uint8_t link_status[DP_LINK_STATUS_SIZE];
f0a3424e
PZ		 2444
2445 intel_dp_set_signal_levels(intel_dp, &DP);
a4fc5ed6 2446
a7c9655f 2447 /* Set training pattern 1 */
47ea7542 2448 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2449 DP_TRAINING_PATTERN_1 |
2450 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 2451 break;
a4fc5ed6 2452
a7c9655f 2453 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2454 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2455 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2456 break;
93f62dad 2457 }
a4fc5ed6 2458
01916270 2459 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2460 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2461 break;
2462 }
2463
2464 /* Check to see if we've tried the max voltage */
2465 for (i = 0; i < intel_dp->lane_count; i++)
2466 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2467 break;
3b4f819d 2468 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2469 ++loop_tries;
2470 if (loop_tries == 5) {
cdb0e95b
KP		 2471 DRM_DEBUG_KMS("too many full retries, give up\n");
2472 break;
2473 }
2474 memset(intel_dp->train_set, 0, 4);
2475 voltage_tries = 0;
2476 continue;
2477 }
a4fc5ed6 2478
3cf2efb1 2479 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2480 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2481 ++voltage_tries;
b06fbda3
DV		 2482 if (voltage_tries == 5) {
2483 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2484 break;
2485 }
2486 } else
2487 voltage_tries = 0;
2488 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2489
3cf2efb1 2490 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2491 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 2492 }
2493
33a34e4e
JB		 2494 intel_dp->DP = DP;
2495}
2496
c19b0669 2497void
33a34e4e
JB		 2498intel_dp_complete_link_train(struct intel_dp *intel_dp)
2499{
33a34e4e 2500 bool channel_eq = false;
37f80975 2501 int tries, cr_tries;
33a34e4e
JB		 2502 uint32_t DP = intel_dp->DP;
2503
a4fc5ed6
KP		 2504 /* channel equalization */
2505 tries = 0;
37f80975 2506 cr_tries = 0;
a4fc5ed6
KP		 2507 channel_eq = false;
2508 for (;;) {
93f62dad 2509 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2510
37f80975
JB		 2511 if (cr_tries > 5) {
2512 DRM_ERROR("failed to train DP, aborting\n");
2513 intel_dp_link_down(intel_dp);
2514 break;
2515 }
2516
f0a3424e 2517 intel_dp_set_signal_levels(intel_dp, &DP);
e3421a18 2518
a4fc5ed6 2519 /* channel eq pattern */
47ea7542 2520 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2521 DP_TRAINING_PATTERN_2 |
2522 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 2523 break;
2524
a7c9655f 2525 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 2526 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 2527 break;
a4fc5ed6 2528
37f80975 2529 /* Make sure clock is still ok */
01916270 2530 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 2531 intel_dp_start_link_train(intel_dp);
2532 cr_tries++;
2533 continue;
2534 }
2535
1ffdff13 2536 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2537 channel_eq = true;
2538 break;
2539 }
a4fc5ed6 2540
37f80975
JB		 2541 /* Try 5 times, then try clock recovery if that fails */
2542 if (tries > 5) {
2543 intel_dp_link_down(intel_dp);
2544 intel_dp_start_link_train(intel_dp);
2545 tries = 0;
2546 cr_tries++;
2547 continue;
2548 }
a4fc5ed6 2549
3cf2efb1 2550 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2551 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 2552 ++tries;
869184a6 2553 }
3cf2efb1 2554
3ab9c637
ID		 2555 intel_dp_set_idle_link_train(intel_dp);
2556
2557 intel_dp->DP = DP;
2558
d6c0d722 2559 if (channel_eq)
07f42258 2560 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2561
3ab9c637
ID		 2562}
2563
2564void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2565{
2566 intel_dp_set_link_train(intel_dp, intel_dp->DP,
2567 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2568}
2569
2570static void
ea5b213a 2571intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2572{
da63a9f2 2573 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2574 enum port port = intel_dig_port->port;
da63a9f2 2575 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2576 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2577 struct intel_crtc *intel_crtc =
2578 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2579 uint32_t DP = intel_dp->DP;
a4fc5ed6 2580
c19b0669
PZ		 2581 /*
2582 * DDI code has a strict mode set sequence and we should try to respect
2583 * it, otherwise we might hang the machine in many different ways. So we
2584 * really should be disabling the port only on a complete crtc_disable
2585 * sequence. This function is just called under two conditions on DDI
2586 * code:
2587 * - Link train failed while doing crtc_enable, and on this case we
2588 * really should respect the mode set sequence and wait for a
2589 * crtc_disable.
2590 * - Someone turned the monitor off and intel_dp_check_link_status
2591 * called us. We don't need to disable the whole port on this case, so
2592 * when someone turns the monitor on again,
2593 * intel_ddi_prepare_link_retrain will take care of redoing the link
2594 * train.
2595 */
affa9354 2596 if (HAS_DDI(dev))
c19b0669
PZ		 2597 return;
2598
0c33d8d7 2599 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2600 return;
2601
28c97730 2602 DRM_DEBUG_KMS("\n");
32f9d658 2603
bc7d38a4 2604 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2605 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2606 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2607 } else {
2608 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2609 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2610 }
fe255d00 2611 POSTING_READ(intel_dp->output_reg);
5eb08b69 2612
ab527efc
DV		 2613 /* We don't really know why we're doing this */
2614 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2615
493a7081 2616 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2617 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2618 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2619
5bddd17f
EA		 2620 /* Hardware workaround: leaving our transcoder select
2621 * set to transcoder B while it's off will prevent the
2622 * corresponding HDMI output on transcoder A.
2623 *
2624 * Combine this with another hardware workaround:
2625 * transcoder select bit can only be cleared while the
2626 * port is enabled.
2627 */
2628 DP &= ~DP_PIPEB_SELECT;
2629 I915_WRITE(intel_dp->output_reg, DP);
2630
2631 /* Changes to enable or select take place the vblank
2632 * after being written.
2633 */
ff50afe9
DV		 2634 if (WARN_ON(crtc == NULL)) {
2635 /* We should never try to disable a port without a crtc
2636 * attached. For paranoia keep the code around for a
2637 * bit. */
31acbcc4
CW		 2638 POSTING_READ(intel_dp->output_reg);
2639 msleep(50);
2640 } else
ab527efc 2641 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2642 }
2643
832afda6 2644 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2645 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2646 POSTING_READ(intel_dp->output_reg);
f01eca2e 2647 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2648}
2649
26d61aad
KP		 2650static bool
2651intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2652{
577c7a50
DL		 2653 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2654
92fd8fd1 2655 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2656 sizeof(intel_dp->dpcd)) == 0)
2657 return false; /* aux transfer failed */
92fd8fd1 2658
577c7a50
DL		 2659 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2660 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2661 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2662
edb39244
AJ		 2663 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2664 return false; /* DPCD not present */
2665
2293bb5c
SK		 2666 /* Check if the panel supports PSR */
2667 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2668 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2669 intel_dp->psr_dpcd,
2670 sizeof(intel_dp->psr_dpcd));
2671 if (is_edp_psr(intel_dp))
2672 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
edb39244
AJ		 2673 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2674 DP_DWN_STRM_PORT_PRESENT))
2675 return true; /* native DP sink */
2676
2677 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2678 return true; /* no per-port downstream info */
2679
2680 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2681 intel_dp->downstream_ports,
2682 DP_MAX_DOWNSTREAM_PORTS) == 0)
2683 return false; /* downstream port status fetch failed */
2684
2685 return true;
92fd8fd1
KP		 2686}
2687
0d198328
AJ		 2688static void
2689intel_dp_probe_oui(struct intel_dp *intel_dp)
2690{
2691 u8 buf[3];
2692
2693 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2694 return;
2695
351cfc34
DV		 2696 ironlake_edp_panel_vdd_on(intel_dp);
2697
0d198328
AJ		 2698 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2699 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2700 buf[0], buf[1], buf[2]);
2701
2702 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2703 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2704 buf[0], buf[1], buf[2]);
351cfc34
DV		 2705
2706 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2707}
2708
a60f0e38
JB		 2709static bool
2710intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2711{
2712 int ret;
2713
2714 ret = intel_dp_aux_native_read_retry(intel_dp,
2715 DP_DEVICE_SERVICE_IRQ_VECTOR,
2716 sink_irq_vector, 1);
2717 if (!ret)
2718 return false;
2719
2720 return true;
2721}
2722
2723static void
2724intel_dp_handle_test_request(struct intel_dp *intel_dp)
2725{
2726 /* NAK by default */
9324cf7f 2727 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2728}
2729
a4fc5ed6
KP		 2730/*
2731 * According to DP spec
2732 * 5.1.2:
2733 * 1. Read DPCD
2734 * 2. Configure link according to Receiver Capabilities
2735 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2736 * 4. Check link status on receipt of hot-plug interrupt
2737 */
2738
00c09d70 2739void
ea5b213a 2740intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2741{
da63a9f2 2742 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2743 u8 sink_irq_vector;
93f62dad 2744 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2745
da63a9f2 2746 if (!intel_encoder->connectors_active)
d2b996ac 2747 return;
59cd09e1 2748
da63a9f2 2749 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2750 return;
2751
92fd8fd1 2752 /* Try to read receiver status if the link appears to be up */
93f62dad 2753 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2754 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2755 return;
2756 }
2757
92fd8fd1 2758 /* Now read the DPCD to see if it's actually running */
26d61aad 2759 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2760 intel_dp_link_down(intel_dp);
2761 return;
2762 }
2763
a60f0e38
JB		 2764 /* Try to read the source of the interrupt */
2765 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2766 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2767 /* Clear interrupt source */
2768 intel_dp_aux_native_write_1(intel_dp,
2769 DP_DEVICE_SERVICE_IRQ_VECTOR,
2770 sink_irq_vector);
2771
2772 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2773 intel_dp_handle_test_request(intel_dp);
2774 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2775 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2776 }
2777
1ffdff13 2778 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2779 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2780 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2781 intel_dp_start_link_train(intel_dp);
2782 intel_dp_complete_link_train(intel_dp);
3ab9c637 2783 intel_dp_stop_link_train(intel_dp);
33a34e4e 2784 }
a4fc5ed6 2785}
a4fc5ed6 2786
caf9ab24 2787/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2788static enum drm_connector_status
26d61aad 2789intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2790{
caf9ab24
AJ		 2791 uint8_t *dpcd = intel_dp->dpcd;
2792 bool hpd;
2793 uint8_t type;
2794
2795 if (!intel_dp_get_dpcd(intel_dp))
2796 return connector_status_disconnected;
2797
2798 /* if there's no downstream port, we're done */
2799 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2800 return connector_status_connected;
caf9ab24
AJ		 2801
2802 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2803 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2804 if (hpd) {
23235177 2805 uint8_t reg;
caf9ab24 2806 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2807 &reg, 1))
caf9ab24 2808 return connector_status_unknown;
23235177
AJ		 2809 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2810 : connector_status_disconnected;
caf9ab24
AJ		 2811 }
2812
2813 /* If no HPD, poke DDC gently */
2814 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2815 return connector_status_connected;
caf9ab24
AJ		 2816
2817 /* Well we tried, say unknown for unreliable port types */
2818 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2819 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2820 return connector_status_unknown;
2821
2822 /* Anything else is out of spec, warn and ignore */
2823 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2824 return connector_status_disconnected;
71ba9000
AJ		 2825}
2826
5eb08b69 2827static enum drm_connector_status
a9756bb5 2828ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2829{
30add22d 2830 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2831 struct drm_i915_private *dev_priv = dev->dev_private;
2832 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2833 enum drm_connector_status status;
2834
fe16d949
CW		 2835 /* Can't disconnect eDP, but you can close the lid... */
2836 if (is_edp(intel_dp)) {
30add22d 2837 status = intel_panel_detect(dev);
fe16d949
CW		 2838 if (status == connector_status_unknown)
2839 status = connector_status_connected;
2840 return status;
2841 }
01cb9ea6 2842
1b469639
DL		 2843 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2844 return connector_status_disconnected;
2845
26d61aad 2846 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2847}
2848
a4fc5ed6 2849static enum drm_connector_status
a9756bb5 2850g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2851{
30add22d 2852 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2853 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 2854 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 2855 uint32_t bit;
5eb08b69 2856
35aad75f
JB		 2857 /* Can't disconnect eDP, but you can close the lid... */
2858 if (is_edp(intel_dp)) {
2859 enum drm_connector_status status;
2860
2861 status = intel_panel_detect(dev);
2862 if (status == connector_status_unknown)
2863 status = connector_status_connected;
2864 return status;
2865 }
2866
34f2be46
VS		 2867 switch (intel_dig_port->port) {
2868 case PORT_B:
26739f12 2869 bit = PORTB_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2870 break;
34f2be46 2871 case PORT_C:
26739f12 2872 bit = PORTC_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2873 break;
34f2be46 2874 case PORT_D:
26739f12 2875 bit = PORTD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2876 break;
2877 default:
2878 return connector_status_unknown;
2879 }
2880
10f76a38 2881 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2882 return connector_status_disconnected;
2883
26d61aad 2884 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2885}
2886
8c241fef
KP		 2887static struct edid *
2888intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2889{
9cd300e0 2890 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2891
9cd300e0
JN		 2892 /* use cached edid if we have one */
2893 if (intel_connector->edid) {
2894 struct edid *edid;
2895 int size;
2896
2897 /* invalid edid */
2898 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2899 return NULL;
2900
9cd300e0 2901 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
edbe1581 2902 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
d6f24d0f
JB		 2903 if (!edid)
2904 return NULL;
2905
d6f24d0f
JB		 2906 return edid;
2907 }
8c241fef 2908
9cd300e0 2909 return drm_get_edid(connector, adapter);
8c241fef
KP		 2910}
2911
2912static int
2913intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2914{
9cd300e0 2915 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2916
9cd300e0
JN		 2917 /* use cached edid if we have one */
2918 if (intel_connector->edid) {
2919 /* invalid edid */
2920 if (IS_ERR(intel_connector->edid))
2921 return 0;
2922
2923 return intel_connector_update_modes(connector,
2924 intel_connector->edid);
d6f24d0f
JB		 2925 }
2926
9cd300e0 2927 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2928}
2929
a9756bb5
ZW		 2930static enum drm_connector_status
2931intel_dp_detect(struct drm_connector *connector, bool force)
2932{
2933 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2934 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2935 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2936 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 2937 enum drm_connector_status status;
2938 struct edid *edid = NULL;
2939
164c8598
CW		 2940 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2941 connector->base.id, drm_get_connector_name(connector));
2942
a9756bb5
ZW		 2943 intel_dp->has_audio = false;
2944
2945 if (HAS_PCH_SPLIT(dev))
2946 status = ironlake_dp_detect(intel_dp);
2947 else
2948 status = g4x_dp_detect(intel_dp);
1b9be9d0 2949
a9756bb5
ZW		 2950 if (status != connector_status_connected)
2951 return status;
2952
0d198328
AJ		 2953 intel_dp_probe_oui(intel_dp);
2954
c3e5f67b
DV		 2955 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2956 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2957 } else {
8c241fef 2958 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2959 if (edid) {
2960 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2961 kfree(edid);
2962 }
a9756bb5
ZW		 2963 }
2964
d63885da
PZ		 2965 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2966 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2967 return connector_status_connected;
a4fc5ed6
KP		 2968}
2969
2970static int intel_dp_get_modes(struct drm_connector *connector)
2971{
df0e9248 2972 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2973 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2974 struct drm_device *dev = connector->dev;
32f9d658 2975 int ret;
a4fc5ed6
KP		 2976
2977 /* We should parse the EDID data and find out if it has an audio sink
2978 */
2979
8c241fef 2980 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2981 if (ret)
32f9d658
ZW		 2982 return ret;
2983
f8779fda 2984 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2985 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2986 struct drm_display_mode *mode;
dd06f90e
JN		 2987 mode = drm_mode_duplicate(dev,
2988 intel_connector->panel.fixed_mode);
f8779fda 2989 if (mode) {
32f9d658
ZW		 2990 drm_mode_probed_add(connector, mode);
2991 return 1;
2992 }
2993 }
2994 return 0;
a4fc5ed6
KP		 2995}
2996
1aad7ac0
CW		 2997static bool
2998intel_dp_detect_audio(struct drm_connector *connector)
2999{
3000 struct intel_dp *intel_dp = intel_attached_dp(connector);
3001 struct edid *edid;
3002 bool has_audio = false;
3003
8c241fef 3004 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 3005 if (edid) {
3006 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3007 kfree(edid);
3008 }
3009
3010 return has_audio;
3011}
3012
f684960e
CW		 3013static int
3014intel_dp_set_property(struct drm_connector *connector,
3015 struct drm_property *property,
3016 uint64_t val)
3017{
e953fd7b 3018 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3019 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3020 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3021 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3022 int ret;
3023
662595df 3024 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3025 if (ret)
3026 return ret;
3027
3f43c48d 3028 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3029 int i = val;
3030 bool has_audio;
3031
3032 if (i == intel_dp->force_audio)
f684960e
CW		 3033 return 0;
3034
1aad7ac0 3035 intel_dp->force_audio = i;
f684960e 3036
c3e5f67b 3037 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3038 has_audio = intel_dp_detect_audio(connector);
3039 else
c3e5f67b 3040 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3041
3042 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3043 return 0;
3044
1aad7ac0 3045 intel_dp->has_audio = has_audio;
f684960e
CW		 3046 goto done;
3047 }
3048
e953fd7b 3049 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3050 bool old_auto = intel_dp->color_range_auto;
3051 uint32_t old_range = intel_dp->color_range;
3052
55bc60db
VS		 3053 switch (val) {
3054 case INTEL_BROADCAST_RGB_AUTO:
3055 intel_dp->color_range_auto = true;
3056 break;
3057 case INTEL_BROADCAST_RGB_FULL:
3058 intel_dp->color_range_auto = false;
3059 intel_dp->color_range = 0;
3060 break;
3061 case INTEL_BROADCAST_RGB_LIMITED:
3062 intel_dp->color_range_auto = false;
3063 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3064 break;
3065 default:
3066 return -EINVAL;
3067 }
ae4edb80
DV		 3068
3069 if (old_auto == intel_dp->color_range_auto &&
3070 old_range == intel_dp->color_range)
3071 return 0;
3072
e953fd7b
CW		 3073 goto done;
3074 }
3075
53b41837
YN		 3076 if (is_edp(intel_dp) &&
3077 property == connector->dev->mode_config.scaling_mode_property) {
3078 if (val == DRM_MODE_SCALE_NONE) {
3079 DRM_DEBUG_KMS("no scaling not supported\n");
3080 return -EINVAL;
3081 }
3082
3083 if (intel_connector->panel.fitting_mode == val) {
3084 /* the eDP scaling property is not changed */
3085 return 0;
3086 }
3087 intel_connector->panel.fitting_mode = val;
3088
3089 goto done;
3090 }
3091
f684960e
CW		 3092 return -EINVAL;
3093
3094done:
c0c36b94
CW		 3095 if (intel_encoder->base.crtc)
3096 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3097
3098 return 0;
3099}
3100
a4fc5ed6 3101static void
73845adf 3102intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3103{
1d508706 3104 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3105
9cd300e0
JN		 3106 if (!IS_ERR_OR_NULL(intel_connector->edid))
3107 kfree(intel_connector->edid);
3108
acd8db10
PZ		 3109 /* Can't call is_edp() since the encoder may have been destroyed
3110 * already. */
3111 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3112 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3113
a4fc5ed6
KP		 3114 drm_sysfs_connector_remove(connector);
3115 drm_connector_cleanup(connector);
55f78c43 3116 kfree(connector);
a4fc5ed6
KP		 3117}
3118
00c09d70 3119void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3120{
da63a9f2
PZ		 3121 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3122 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3123 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927
DV		 3124
3125 i2c_del_adapter(&intel_dp->adapter);
3126 drm_encoder_cleanup(encoder);
bd943159
KP		 3127 if (is_edp(intel_dp)) {
3128 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3129 mutex_lock(&dev->mode_config.mutex);
bd943159 3130 ironlake_panel_vdd_off_sync(intel_dp);
bd173813 3131 mutex_unlock(&dev->mode_config.mutex);
bd943159 3132 }
da63a9f2 3133 kfree(intel_dig_port);
24d05927
DV		 3134}
3135
a4fc5ed6 3136static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3137 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3138 .detect = intel_dp_detect,
3139 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3140 .set_property = intel_dp_set_property,
73845adf 3141 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3142};
3143
3144static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3145 .get_modes = intel_dp_get_modes,
3146 .mode_valid = intel_dp_mode_valid,
df0e9248 3147 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3148};
3149
a4fc5ed6 3150static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3151 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3152};
3153
995b6762 3154static void
21d40d37 3155intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3156{
fa90ecef 3157 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3158
885a5014 3159 intel_dp_check_link_status(intel_dp);
c8110e52 3160}
6207937d 3161
e3421a18
ZW		 3162/* Return which DP Port should be selected for Transcoder DP control */
3163int
0206e353 3164intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3165{
3166 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3167 struct intel_encoder *intel_encoder;
3168 struct intel_dp *intel_dp;
e3421a18 3169
fa90ecef
PZ		 3170 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3171 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3172
fa90ecef
PZ		 3173 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3174 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3175 return intel_dp->output_reg;
e3421a18 3176 }
ea5b213a 3177
e3421a18
ZW		 3178 return -1;
3179}
3180
36e83a18 3181/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 3182bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 3183{
3184 struct drm_i915_private *dev_priv = dev->dev_private;
3185 struct child_device_config *p_child;
3186 int i;
3187
41aa3448 3188 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3189 return false;
3190
41aa3448
RV		 3191 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3192 p_child = dev_priv->vbt.child_dev + i;
36e83a18
ZY		 3193
3194 if (p_child->dvo_port == PORT_IDPD &&
3195 p_child->device_type == DEVICE_TYPE_eDP)
3196 return true;
3197 }
3198 return false;
3199}
3200
f684960e
CW		 3201static void
3202intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3203{
53b41837
YN		 3204 struct intel_connector *intel_connector = to_intel_connector(connector);
3205
3f43c48d 3206 intel_attach_force_audio_property(connector);
e953fd7b 3207 intel_attach_broadcast_rgb_property(connector);
55bc60db 3208 intel_dp->color_range_auto = true;
53b41837
YN		 3209
3210 if (is_edp(intel_dp)) {
3211 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3212 drm_object_attach_property(
3213 &connector->base,
53b41837 3214 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3215 DRM_MODE_SCALE_ASPECT);
3216 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3217 }
f684960e
CW		 3218}
3219
67a54566
DV		 3220static void
3221intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3222 struct intel_dp *intel_dp,
3223 struct edp_power_seq *out)
67a54566
DV		 3224{
3225 struct drm_i915_private *dev_priv = dev->dev_private;
3226 struct edp_power_seq cur, vbt, spec, final;
3227 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3228 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3229
3230 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3231 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3232 pp_on_reg = PCH_PP_ON_DELAYS;
3233 pp_off_reg = PCH_PP_OFF_DELAYS;
3234 pp_div_reg = PCH_PP_DIVISOR;
3235 } else {
bf13e81b
JN		 3236 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3237
3238 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3239 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3240 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3241 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3242 }
67a54566
DV		 3243
3244 /* Workaround: Need to write PP_CONTROL with the unlock key as
3245 * the very first thing. */
453c5420 3246 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3247 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3248
453c5420
JB		 3249 pp_on = I915_READ(pp_on_reg);
3250 pp_off = I915_READ(pp_off_reg);
3251 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3252
3253 /* Pull timing values out of registers */
3254 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3255 PANEL_POWER_UP_DELAY_SHIFT;
3256
3257 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3258 PANEL_LIGHT_ON_DELAY_SHIFT;
3259
3260 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3261 PANEL_LIGHT_OFF_DELAY_SHIFT;
3262
3263 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3264 PANEL_POWER_DOWN_DELAY_SHIFT;
3265
3266 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3267 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3268
3269 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3270 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3271
41aa3448 3272 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3273
3274 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3275 * our hw here, which are all in 100usec. */
3276 spec.t1_t3 = 210 * 10;
3277 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3278 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3279 spec.t10 = 500 * 10;
3280 /* This one is special and actually in units of 100ms, but zero
3281 * based in the hw (so we need to add 100 ms). But the sw vbt
3282 * table multiplies it with 1000 to make it in units of 100usec,
3283 * too. */
3284 spec.t11_t12 = (510 + 100) * 10;
3285
3286 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3287 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3288
3289 /* Use the max of the register settings and vbt. If both are
3290 * unset, fall back to the spec limits. */
3291#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3292 spec.field : \
3293 max(cur.field, vbt.field))
3294 assign_final(t1_t3);
3295 assign_final(t8);
3296 assign_final(t9);
3297 assign_final(t10);
3298 assign_final(t11_t12);
3299#undef assign_final
3300
3301#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3302 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3303 intel_dp->backlight_on_delay = get_delay(t8);
3304 intel_dp->backlight_off_delay = get_delay(t9);
3305 intel_dp->panel_power_down_delay = get_delay(t10);
3306 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3307#undef get_delay
3308
f30d26e4
JN		 3309 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3310 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3311 intel_dp->panel_power_cycle_delay);
3312
3313 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3314 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3315
3316 if (out)
3317 *out = final;
3318}
3319
3320static void
3321intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3322 struct intel_dp *intel_dp,
3323 struct edp_power_seq *seq)
3324{
3325 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3326 u32 pp_on, pp_off, pp_div, port_sel = 0;
3327 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3328 int pp_on_reg, pp_off_reg, pp_div_reg;
3329
3330 if (HAS_PCH_SPLIT(dev)) {
3331 pp_on_reg = PCH_PP_ON_DELAYS;
3332 pp_off_reg = PCH_PP_OFF_DELAYS;
3333 pp_div_reg = PCH_PP_DIVISOR;
3334 } else {
bf13e81b
JN		 3335 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3336
3337 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3338 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3339 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3340 }
3341
67a54566 3342 /* And finally store the new values in the power sequencer. */
f30d26e4
JN		 3343 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3344 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3345 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3346 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3347 /* Compute the divisor for the pp clock, simply match the Bspec
3348 * formula. */
453c5420 3349 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3350 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3351 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3352
3353 /* Haswell doesn't have any port selection bits for the panel
3354 * power sequencer any more. */
bc7d38a4 3355 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3356 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3357 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3358 else
3359 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3360 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3361 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3362 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3363 else
a24c144c 3364 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3365 }
3366
453c5420
JB		 3367 pp_on |= port_sel;
3368
3369 I915_WRITE(pp_on_reg, pp_on);
3370 I915_WRITE(pp_off_reg, pp_off);
3371 I915_WRITE(pp_div_reg, pp_div);
67a54566 3372
67a54566 3373 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3374 I915_READ(pp_on_reg),
3375 I915_READ(pp_off_reg),
3376 I915_READ(pp_div_reg));
f684960e
CW		 3377}
3378
ed92f0b2
PZ		 3379static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3380 struct intel_connector *intel_connector)
3381{
3382 struct drm_connector *connector = &intel_connector->base;
3383 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3384 struct drm_device *dev = intel_dig_port->base.base.dev;
3385 struct drm_i915_private *dev_priv = dev->dev_private;
3386 struct drm_display_mode *fixed_mode = NULL;
3387 struct edp_power_seq power_seq = { 0 };
3388 bool has_dpcd;
3389 struct drm_display_mode *scan;
3390 struct edid *edid;
3391
3392 if (!is_edp(intel_dp))
3393 return true;
3394
3395 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3396
3397 /* Cache DPCD and EDID for edp. */
3398 ironlake_edp_panel_vdd_on(intel_dp);
3399 has_dpcd = intel_dp_get_dpcd(intel_dp);
3400 ironlake_edp_panel_vdd_off(intel_dp, false);
3401
3402 if (has_dpcd) {
3403 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3404 dev_priv->no_aux_handshake =
3405 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3406 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3407 } else {
3408 /* if this fails, presume the device is a ghost */
3409 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3410 return false;
3411 }
3412
3413 /* We now know it's not a ghost, init power sequence regs. */
3414 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3415 &power_seq);
3416
3417 ironlake_edp_panel_vdd_on(intel_dp);
3418 edid = drm_get_edid(connector, &intel_dp->adapter);
3419 if (edid) {
3420 if (drm_add_edid_modes(connector, edid)) {
3421 drm_mode_connector_update_edid_property(connector,
3422 edid);
3423 drm_edid_to_eld(connector, edid);
3424 } else {
3425 kfree(edid);
3426 edid = ERR_PTR(-EINVAL);
3427 }
3428 } else {
3429 edid = ERR_PTR(-ENOENT);
3430 }
3431 intel_connector->edid = edid;
3432
3433 /* prefer fixed mode from EDID if available */
3434 list_for_each_entry(scan, &connector->probed_modes, head) {
3435 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3436 fixed_mode = drm_mode_duplicate(dev, scan);
3437 break;
3438 }
3439 }
3440
3441 /* fallback to VBT if available for eDP */
3442 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3443 fixed_mode = drm_mode_duplicate(dev,
3444 dev_priv->vbt.lfp_lvds_vbt_mode);
3445 if (fixed_mode)
3446 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3447 }
3448
3449 ironlake_edp_panel_vdd_off(intel_dp, false);
3450
3451 intel_panel_init(&intel_connector->panel, fixed_mode);
3452 intel_panel_setup_backlight(connector);
3453
3454 return true;
3455}
3456
16c25533 3457bool
f0fec3f2
PZ		 3458intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3459 struct intel_connector *intel_connector)
a4fc5ed6 3460{
f0fec3f2
PZ		 3461 struct drm_connector *connector = &intel_connector->base;
3462 struct intel_dp *intel_dp = &intel_dig_port->dp;
3463 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3464 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3465 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3466 enum port port = intel_dig_port->port;
5eb08b69 3467 const char *name = NULL;
b2a14755 3468 int type, error;
a4fc5ed6 3469
0767935e
DV		 3470 /* Preserve the current hw state. */
3471 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3472 intel_dp->attached_connector = intel_connector;
3d3dc149 3473
f7d24902 3474 type = DRM_MODE_CONNECTOR_DisplayPort;
19c03924
GB		 3475 /*
3476 * FIXME : We need to initialize built-in panels before external panels.
3477 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3478 */
f7d24902
ID		 3479 switch (port) {
3480 case PORT_A:
b329530c 3481 type = DRM_MODE_CONNECTOR_eDP;
f7d24902
ID		 3482 break;
3483 case PORT_C:
3484 if (IS_VALLEYVIEW(dev))
3485 type = DRM_MODE_CONNECTOR_eDP;
3486 break;
3487 case PORT_D:
3488 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3489 type = DRM_MODE_CONNECTOR_eDP;
3490 break;
3491 default: /* silence GCC warning */
3492 break;
b329530c
AJ		 3493 }
3494
f7d24902
ID		 3495 /*
3496 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3497 * for DP the encoder type can be set by the caller to
3498 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3499 */
3500 if (type == DRM_MODE_CONNECTOR_eDP)
3501 intel_encoder->type = INTEL_OUTPUT_EDP;
3502
e7281eab
ID		 3503 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3504 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3505 port_name(port));
3506
b329530c 3507 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3508 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3509
a4fc5ed6
KP		 3510 connector->interlace_allowed = true;
3511 connector->doublescan_allowed = 0;
3512
f0fec3f2
PZ		 3513 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3514 ironlake_panel_vdd_work);
a4fc5ed6 3515
df0e9248 3516 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3517 drm_sysfs_connector_add(connector);
3518
affa9354 3519 if (HAS_DDI(dev))
bcbc889b
PZ		 3520 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3521 else
3522 intel_connector->get_hw_state = intel_connector_get_hw_state;
3523
9ed35ab1
PZ		 3524 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3525 if (HAS_DDI(dev)) {
3526 switch (intel_dig_port->port) {
3527 case PORT_A:
3528 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3529 break;
3530 case PORT_B:
3531 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3532 break;
3533 case PORT_C:
3534 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3535 break;
3536 case PORT_D:
3537 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3538 break;
3539 default:
3540 BUG();
3541 }
3542 }
e8cb4558 3543
a4fc5ed6 3544 /* Set up the DDC bus. */
ab9d7c30
PZ		 3545 switch (port) {
3546 case PORT_A:
1d843f9d 3547 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3548 name = "DPDDC-A";
3549 break;
3550 case PORT_B:
1d843f9d 3551 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3552 name = "DPDDC-B";
3553 break;
3554 case PORT_C:
1d843f9d 3555 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3556 name = "DPDDC-C";
3557 break;
3558 case PORT_D:
1d843f9d 3559 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3560 name = "DPDDC-D";
3561 break;
3562 default:
ad1c0b19 3563 BUG();
5eb08b69
ZW		 3564 }
3565
b2a14755
PZ		 3566 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3567 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3568 error, port_name(port));
c1f05264 3569
2b28bb1b
RV		 3570 intel_dp->psr_setup_done = false;
3571
b2f246a8 3572 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
15b1d171
PZ		 3573 i2c_del_adapter(&intel_dp->adapter);
3574 if (is_edp(intel_dp)) {
3575 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3576 mutex_lock(&dev->mode_config.mutex);
3577 ironlake_panel_vdd_off_sync(intel_dp);
3578 mutex_unlock(&dev->mode_config.mutex);
3579 }
b2f246a8
PZ		 3580 drm_sysfs_connector_remove(connector);
3581 drm_connector_cleanup(connector);
16c25533 3582 return false;
b2f246a8 3583 }
32f9d658 3584
f684960e
CW		 3585 intel_dp_add_properties(intel_dp, connector);
3586
a4fc5ed6
KP		 3587 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3588 * 0xd. Failure to do so will result in spurious interrupts being
3589 * generated on the port when a cable is not attached.
3590 */
3591 if (IS_G4X(dev) && !IS_GM45(dev)) {
3592 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3593 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3594 }
16c25533
PZ		 3595
3596 return true;
a4fc5ed6 3597}
f0fec3f2
PZ		 3598
3599void
3600intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3601{
3602 struct intel_digital_port *intel_dig_port;
3603 struct intel_encoder *intel_encoder;
3604 struct drm_encoder *encoder;
3605 struct intel_connector *intel_connector;
3606
3607 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3608 if (!intel_dig_port)
3609 return;
3610
3611 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3612 if (!intel_connector) {
3613 kfree(intel_dig_port);
3614 return;
3615 }
3616
3617 intel_encoder = &intel_dig_port->base;
3618 encoder = &intel_encoder->base;
3619
3620 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3621 DRM_MODE_ENCODER_TMDS);
3622
5bfe2ac0 3623 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 3624 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70
PZ		 3625 intel_encoder->disable = intel_disable_dp;
3626 intel_encoder->post_disable = intel_post_disable_dp;
3627 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3628 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 3629 if (IS_VALLEYVIEW(dev)) {
ecff4f3b 3630 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 3631 intel_encoder->pre_enable = vlv_pre_enable_dp;
3632 intel_encoder->enable = vlv_enable_dp;
3633 } else {
ecff4f3b
JN		 3634 intel_encoder->pre_enable = g4x_pre_enable_dp;
3635 intel_encoder->enable = g4x_enable_dp;
ab1f90f9 3636 }
f0fec3f2 3637
174edf1f 3638 intel_dig_port->port = port;
f0fec3f2
PZ		 3639 intel_dig_port->dp.output_reg = output_reg;
3640
00c09d70 3641 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 3642 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3643 intel_encoder->cloneable = false;
3644 intel_encoder->hot_plug = intel_dp_hot_plug;
3645
15b1d171
PZ		 3646 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3647 drm_encoder_cleanup(encoder);
3648 kfree(intel_dig_port);
b2f246a8 3649 kfree(intel_connector);
15b1d171 3650 }
f0fec3f2 3651}
Linux kernel - Deliverables
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