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drm/i915: Only restore backlight combination mode reg for ums
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
cfcb0fc9
JB		 67/**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74static bool is_edp(struct intel_dp *intel_dp)
75{
da63a9f2
PZ		 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 79}
80
68b4d824 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 82{
68b4d824
ID		 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 86}
87
df0e9248
CW		 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89{
fa90ecef 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 91}
92
ea5b213a 93static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 94
a4fc5ed6 95static int
ea5b213a 96intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 97{
7183dc29 98 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 99
100 switch (max_link_bw) {
101 case DP_LINK_BW_1_62:
102 case DP_LINK_BW_2_7:
103 break;
d4eead50
ID		 104 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
105 max_link_bw = DP_LINK_BW_2_7;
106 break;
a4fc5ed6 107 default:
d4eead50
ID		 108 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
109 max_link_bw);
a4fc5ed6
KP		 110 max_link_bw = DP_LINK_BW_1_62;
111 break;
112 }
113 return max_link_bw;
114}
115
cd9dde44
AJ		 116/*
117 * The units on the numbers in the next two are... bizarre. Examples will
118 * make it clearer; this one parallels an example in the eDP spec.
119 *
120 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
121 *
122 * 270000 * 1 * 8 / 10 == 216000
123 *
124 * The actual data capacity of that configuration is 2.16Gbit/s, so the
125 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
126 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
127 * 119000. At 18bpp that's 2142000 kilobits per second.
128 *
129 * Thus the strange-looking division by 10 in intel_dp_link_required, to
130 * get the result in decakilobits instead of kilobits.
131 */
132
a4fc5ed6 133static int
c898261c 134intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 135{
cd9dde44 136 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 137}
138
fe27d53e
DA		 139static int
140intel_dp_max_data_rate(int max_link_clock, int max_lanes)
141{
142 return (max_link_clock * max_lanes * 8) / 10;
143}
144
c19de8eb 145static enum drm_mode_status
a4fc5ed6
KP		 146intel_dp_mode_valid(struct drm_connector *connector,
147 struct drm_display_mode *mode)
148{
df0e9248 149 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 150 struct intel_connector *intel_connector = to_intel_connector(connector);
151 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 152 int target_clock = mode->clock;
153 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 154
dd06f90e
JN		 155 if (is_edp(intel_dp) && fixed_mode) {
156 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 157 return MODE_PANEL;
158
dd06f90e 159 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 160 return MODE_PANEL;
03afc4a2
DV		 161
162 target_clock = fixed_mode->clock;
7de56f43
ZY		 163 }
164
36008365
DV		 165 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
166 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
167
168 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
169 mode_rate = intel_dp_link_required(target_clock, 18);
170
171 if (mode_rate > max_rate)
c4867936 172 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 173
174 if (mode->clock < 10000)
175 return MODE_CLOCK_LOW;
176
0af78a2b
DV		 177 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
178 return MODE_H_ILLEGAL;
179
a4fc5ed6
KP		 180 return MODE_OK;
181}
182
183static uint32_t
184pack_aux(uint8_t *src, int src_bytes)
185{
186 int i;
187 uint32_t v = 0;
188
189 if (src_bytes > 4)
190 src_bytes = 4;
191 for (i = 0; i < src_bytes; i++)
192 v |= ((uint32_t) src[i]) << ((3-i) * 8);
193 return v;
194}
195
196static void
197unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
198{
199 int i;
200 if (dst_bytes > 4)
201 dst_bytes = 4;
202 for (i = 0; i < dst_bytes; i++)
203 dst[i] = src >> ((3-i) * 8);
204}
205
fb0f8fbf
KP		 206/* hrawclock is 1/4 the FSB frequency */
207static int
208intel_hrawclk(struct drm_device *dev)
209{
210 struct drm_i915_private *dev_priv = dev->dev_private;
211 uint32_t clkcfg;
212
9473c8f4
VP		 213 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
214 if (IS_VALLEYVIEW(dev))
215 return 200;
216
fb0f8fbf
KP		 217 clkcfg = I915_READ(CLKCFG);
218 switch (clkcfg & CLKCFG_FSB_MASK) {
219 case CLKCFG_FSB_400:
220 return 100;
221 case CLKCFG_FSB_533:
222 return 133;
223 case CLKCFG_FSB_667:
224 return 166;
225 case CLKCFG_FSB_800:
226 return 200;
227 case CLKCFG_FSB_1067:
228 return 266;
229 case CLKCFG_FSB_1333:
230 return 333;
231 /* these two are just a guess; one of them might be right */
232 case CLKCFG_FSB_1600:
233 case CLKCFG_FSB_1600_ALT:
234 return 400;
235 default:
236 return 133;
237 }
238}
239
bf13e81b
JN		 240static void
241intel_dp_init_panel_power_sequencer(struct drm_device *dev,
242 struct intel_dp *intel_dp,
243 struct edp_power_seq *out);
244static void
245intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
246 struct intel_dp *intel_dp,
247 struct edp_power_seq *out);
248
249static enum pipe
250vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
251{
252 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
253 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
254 struct drm_device *dev = intel_dig_port->base.base.dev;
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 enum port port = intel_dig_port->port;
257 enum pipe pipe;
258
259 /* modeset should have pipe */
260 if (crtc)
261 return to_intel_crtc(crtc)->pipe;
262
263 /* init time, try to find a pipe with this port selected */
264 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
265 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
266 PANEL_PORT_SELECT_MASK;
267 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
268 return pipe;
269 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
270 return pipe;
271 }
272
273 /* shrug */
274 return PIPE_A;
275}
276
277static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
278{
279 struct drm_device *dev = intel_dp_to_dev(intel_dp);
280
281 if (HAS_PCH_SPLIT(dev))
282 return PCH_PP_CONTROL;
283 else
284 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
285}
286
287static u32 _pp_stat_reg(struct intel_dp *intel_dp)
288{
289 struct drm_device *dev = intel_dp_to_dev(intel_dp);
290
291 if (HAS_PCH_SPLIT(dev))
292 return PCH_PP_STATUS;
293 else
294 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
295}
296
ebf33b18
KP		 297static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
298{
30add22d 299 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 300 struct drm_i915_private *dev_priv = dev->dev_private;
301
bf13e81b 302 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 303}
304
305static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
306{
30add22d 307 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 308 struct drm_i915_private *dev_priv = dev->dev_private;
309
bf13e81b 310 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 311}
312
9b984dae
KP		 313static void
314intel_dp_check_edp(struct intel_dp *intel_dp)
315{
30add22d 316 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 317 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 318
9b984dae
KP		 319 if (!is_edp(intel_dp))
320 return;
453c5420 321
ebf33b18 322 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 323 WARN(1, "eDP powered off while attempting aux channel communication.\n");
324 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 325 I915_READ(_pp_stat_reg(intel_dp)),
326 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 327 }
328}
329
9ee32fea
DV		 330static uint32_t
331intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
332{
333 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
334 struct drm_device *dev = intel_dig_port->base.base.dev;
335 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 336 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 337 uint32_t status;
338 bool done;
339
ef04f00d 340#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 341 if (has_aux_irq)
b18ac466 342 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 343 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 344 else
345 done = wait_for_atomic(C, 10) == 0;
346 if (!done)
347 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
348 has_aux_irq);
349#undef C
350
351 return status;
352}
353
bc86625a
CW		 354static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
355 int index)
a4fc5ed6 356{
174edf1f
PZ		 357 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
358 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 359 struct drm_i915_private *dev_priv = dev->dev_private;
9ee32fea 360
a4fc5ed6 361 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 362 * and would like to run at 2MHz. So, take the
363 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 364 *
365 * Note that PCH attached eDP panels should use a 125MHz input
366 * clock divider.
a4fc5ed6 367 */
a62d0834 368 if (IS_VALLEYVIEW(dev)) {
bc86625a 369 return index ? 0 : 100;
a62d0834 370 } else if (intel_dig_port->port == PORT_A) {
bc86625a
CW		 371 if (index)
372 return 0;
affa9354 373 if (HAS_DDI(dev))
bc86625a 374 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
9473c8f4 375 else if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 376 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 377 else
b84a1cf8 378 return 225; /* eDP input clock at 450Mhz */
2c55c336
JN		 379 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
380 /* Workaround for non-ULT HSW */
bc86625a
CW		 381 switch (index) {
382 case 0: return 63;
383 case 1: return 72;
384 default: return 0;
385 }
2c55c336 386 } else if (HAS_PCH_SPLIT(dev)) {
bc86625a 387 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 388 } else {
bc86625a 389 return index ? 0 :intel_hrawclk(dev) / 2;
2c55c336 390 }
b84a1cf8
RV		 391}
392
393static int
394intel_dp_aux_ch(struct intel_dp *intel_dp,
395 uint8_t *send, int send_bytes,
396 uint8_t *recv, int recv_size)
397{
398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
399 struct drm_device *dev = intel_dig_port->base.base.dev;
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
402 uint32_t ch_data = ch_ctl + 4;
bc86625a 403 uint32_t aux_clock_divider;
b84a1cf8
RV		 404 int i, ret, recv_bytes;
405 uint32_t status;
bc86625a 406 int try, precharge, clock = 0;
4aeebd74 407 bool has_aux_irq = true;
a81a507d 408 uint32_t timeout;
b84a1cf8
RV		 409
410 /* dp aux is extremely sensitive to irq latency, hence request the
411 * lowest possible wakeup latency and so prevent the cpu from going into
412 * deep sleep states.
413 */
414 pm_qos_update_request(&dev_priv->pm_qos, 0);
415
416 intel_dp_check_edp(intel_dp);
5eb08b69 417
6b4e0a93
DV		 418 if (IS_GEN6(dev))
419 precharge = 3;
420 else
421 precharge = 5;
422
a81a507d
BW		 423 if (IS_BROADWELL(dev) && ch_ctl == DPA_AUX_CH_CTL)
424 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
425 else
426 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
427
c67a470b
PZ		 428 intel_aux_display_runtime_get(dev_priv);
429
11bee43e
JB		 430 /* Try to wait for any previous AUX channel activity */
431 for (try = 0; try < 3; try++) {
ef04f00d 432 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 433 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
434 break;
435 msleep(1);
436 }
437
438 if (try == 3) {
439 WARN(1, "dp_aux_ch not started status 0x%08x\n",
440 I915_READ(ch_ctl));
9ee32fea
DV		 441 ret = -EBUSY;
442 goto out;
4f7f7b7e
CW		 443 }
444
46a5ae9f
PZ		 445 /* Only 5 data registers! */
446 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
447 ret = -E2BIG;
448 goto out;
449 }
450
bc86625a
CW		 451 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
452 /* Must try at least 3 times according to DP spec */
453 for (try = 0; try < 5; try++) {
454 /* Load the send data into the aux channel data registers */
455 for (i = 0; i < send_bytes; i += 4)
456 I915_WRITE(ch_data + i,
457 pack_aux(send + i, send_bytes - i));
458
459 /* Send the command and wait for it to complete */
460 I915_WRITE(ch_ctl,
461 DP_AUX_CH_CTL_SEND_BUSY |
462 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
a81a507d 463 timeout |
bc86625a
CW		 464 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
465 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
466 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
467 DP_AUX_CH_CTL_DONE |
468 DP_AUX_CH_CTL_TIME_OUT_ERROR |
469 DP_AUX_CH_CTL_RECEIVE_ERROR);
470
471 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
472
473 /* Clear done status and any errors */
474 I915_WRITE(ch_ctl,
475 status |
476 DP_AUX_CH_CTL_DONE |
477 DP_AUX_CH_CTL_TIME_OUT_ERROR |
478 DP_AUX_CH_CTL_RECEIVE_ERROR);
479
480 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
481 DP_AUX_CH_CTL_RECEIVE_ERROR))
482 continue;
483 if (status & DP_AUX_CH_CTL_DONE)
484 break;
485 }
4f7f7b7e 486 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 487 break;
488 }
489
a4fc5ed6 490 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 491 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 492 ret = -EBUSY;
493 goto out;
a4fc5ed6
KP		 494 }
495
496 /* Check for timeout or receive error.
497 * Timeouts occur when the sink is not connected
498 */
a5b3da54 499 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 500 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 501 ret = -EIO;
502 goto out;
a5b3da54 503 }
1ae8c0a5
KP		 504
505 /* Timeouts occur when the device isn't connected, so they're
506 * "normal" -- don't fill the kernel log with these */
a5b3da54 507 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 508 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 509 ret = -ETIMEDOUT;
510 goto out;
a4fc5ed6
KP		 511 }
512
513 /* Unload any bytes sent back from the other side */
514 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
515 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 516 if (recv_bytes > recv_size)
517 recv_bytes = recv_size;
0206e353 518
4f7f7b7e
CW		 519 for (i = 0; i < recv_bytes; i += 4)
520 unpack_aux(I915_READ(ch_data + i),
521 recv + i, recv_bytes - i);
a4fc5ed6 522
9ee32fea
DV		 523 ret = recv_bytes;
524out:
525 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 526 intel_aux_display_runtime_put(dev_priv);
9ee32fea
DV		 527
528 return ret;
a4fc5ed6
KP		 529}
530
531/* Write data to the aux channel in native mode */
532static int
ea5b213a 533intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 534 uint16_t address, uint8_t *send, int send_bytes)
535{
536 int ret;
537 uint8_t msg[20];
538 int msg_bytes;
539 uint8_t ack;
540
46a5ae9f
PZ		 541 if (WARN_ON(send_bytes > 16))
542 return -E2BIG;
543
9b984dae 544 intel_dp_check_edp(intel_dp);
6b27f7f0 545 msg[0] = DP_AUX_NATIVE_WRITE << 4;
a4fc5ed6 546 msg[1] = address >> 8;
eebc863e 547 msg[2] = address & 0xff;
a4fc5ed6
KP		 548 msg[3] = send_bytes - 1;
549 memcpy(&msg[4], send, send_bytes);
550 msg_bytes = send_bytes + 4;
551 for (;;) {
ea5b213a 552 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 553 if (ret < 0)
554 return ret;
6b27f7f0
TR		 555 ack >>= 4;
556 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
a4fc5ed6 557 break;
6b27f7f0 558 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
a4fc5ed6
KP		 559 udelay(100);
560 else
a5b3da54 561 return -EIO;
a4fc5ed6
KP		 562 }
563 return send_bytes;
564}
565
566/* Write a single byte to the aux channel in native mode */
567static int
ea5b213a 568intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 569 uint16_t address, uint8_t byte)
570{
ea5b213a 571 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 572}
573
574/* read bytes from a native aux channel */
575static int
ea5b213a 576intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 577 uint16_t address, uint8_t *recv, int recv_bytes)
578{
579 uint8_t msg[4];
580 int msg_bytes;
581 uint8_t reply[20];
582 int reply_bytes;
583 uint8_t ack;
584 int ret;
585
46a5ae9f
PZ		 586 if (WARN_ON(recv_bytes > 19))
587 return -E2BIG;
588
9b984dae 589 intel_dp_check_edp(intel_dp);
6b27f7f0 590 msg[0] = DP_AUX_NATIVE_READ << 4;
a4fc5ed6
KP		 591 msg[1] = address >> 8;
592 msg[2] = address & 0xff;
593 msg[3] = recv_bytes - 1;
594
595 msg_bytes = 4;
596 reply_bytes = recv_bytes + 1;
597
598 for (;;) {
ea5b213a 599 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 600 reply, reply_bytes);
a5b3da54
KP		 601 if (ret == 0)
602 return -EPROTO;
603 if (ret < 0)
a4fc5ed6 604 return ret;
6b27f7f0
TR		 605 ack = reply[0] >> 4;
606 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) {
a4fc5ed6
KP		 607 memcpy(recv, reply + 1, ret - 1);
608 return ret - 1;
609 }
6b27f7f0 610 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
a4fc5ed6
KP		 611 udelay(100);
612 else
a5b3da54 613 return -EIO;
a4fc5ed6
KP		 614 }
615}
616
617static int
ab2c0672
DA		 618intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
619 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 620{
ab2c0672 621 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 622 struct intel_dp *intel_dp = container_of(adapter,
623 struct intel_dp,
624 adapter);
ab2c0672
DA		 625 uint16_t address = algo_data->address;
626 uint8_t msg[5];
627 uint8_t reply[2];
8316f337 628 unsigned retry;
ab2c0672
DA		 629 int msg_bytes;
630 int reply_bytes;
631 int ret;
632
8a5e6aeb 633 ironlake_edp_panel_vdd_on(intel_dp);
9b984dae 634 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 635 /* Set up the command byte */
636 if (mode & MODE_I2C_READ)
6b27f7f0 637 msg[0] = DP_AUX_I2C_READ << 4;
ab2c0672 638 else
6b27f7f0 639 msg[0] = DP_AUX_I2C_WRITE << 4;
ab2c0672
DA		 640
641 if (!(mode & MODE_I2C_STOP))
6b27f7f0 642 msg[0] |= DP_AUX_I2C_MOT << 4;
a4fc5ed6 643
ab2c0672
DA		 644 msg[1] = address >> 8;
645 msg[2] = address;
646
647 switch (mode) {
648 case MODE_I2C_WRITE:
649 msg[3] = 0;
650 msg[4] = write_byte;
651 msg_bytes = 5;
652 reply_bytes = 1;
653 break;
654 case MODE_I2C_READ:
655 msg[3] = 0;
656 msg_bytes = 4;
657 reply_bytes = 2;
658 break;
659 default:
660 msg_bytes = 3;
661 reply_bytes = 1;
662 break;
663 }
664
58c67ce9
JN		 665 /*
666 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
667 * required to retry at least seven times upon receiving AUX_DEFER
668 * before giving up the AUX transaction.
669 */
670 for (retry = 0; retry < 7; retry++) {
8316f337
DF		 671 ret = intel_dp_aux_ch(intel_dp,
672 msg, msg_bytes,
673 reply, reply_bytes);
ab2c0672 674 if (ret < 0) {
3ff99164 675 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
8a5e6aeb 676 goto out;
ab2c0672 677 }
8316f337 678
6b27f7f0
TR		 679 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
680 case DP_AUX_NATIVE_REPLY_ACK:
8316f337
DF		 681 /* I2C-over-AUX Reply field is only valid
682 * when paired with AUX ACK.
683 */
684 break;
6b27f7f0 685 case DP_AUX_NATIVE_REPLY_NACK:
8316f337 686 DRM_DEBUG_KMS("aux_ch native nack\n");
8a5e6aeb
PZ		 687 ret = -EREMOTEIO;
688 goto out;
6b27f7f0 689 case DP_AUX_NATIVE_REPLY_DEFER:
8d16f258
JN		 690 /*
691 * For now, just give more slack to branch devices. We
692 * could check the DPCD for I2C bit rate capabilities,
693 * and if available, adjust the interval. We could also
694 * be more careful with DP-to-Legacy adapters where a
695 * long legacy cable may force very low I2C bit rates.
696 */
697 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
698 DP_DWN_STRM_PORT_PRESENT)
699 usleep_range(500, 600);
700 else
701 usleep_range(300, 400);
8316f337
DF		 702 continue;
703 default:
704 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
705 reply[0]);
8a5e6aeb
PZ		 706 ret = -EREMOTEIO;
707 goto out;
8316f337
DF		 708 }
709
6b27f7f0
TR		 710 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
711 case DP_AUX_I2C_REPLY_ACK:
ab2c0672
DA		 712 if (mode == MODE_I2C_READ) {
713 *read_byte = reply[1];
714 }
8a5e6aeb
PZ		 715 ret = reply_bytes - 1;
716 goto out;
6b27f7f0 717 case DP_AUX_I2C_REPLY_NACK:
8316f337 718 DRM_DEBUG_KMS("aux_i2c nack\n");
8a5e6aeb
PZ		 719 ret = -EREMOTEIO;
720 goto out;
6b27f7f0 721 case DP_AUX_I2C_REPLY_DEFER:
8316f337 722 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 723 udelay(100);
724 break;
725 default:
8316f337 726 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
8a5e6aeb
PZ		 727 ret = -EREMOTEIO;
728 goto out;
ab2c0672
DA		 729 }
730 }
8316f337
DF		 731
732 DRM_ERROR("too many retries, giving up\n");
8a5e6aeb
PZ		 733 ret = -EREMOTEIO;
734
735out:
736 ironlake_edp_panel_vdd_off(intel_dp, false);
737 return ret;
a4fc5ed6
KP		 738}
739
740static int
ea5b213a 741intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 742 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 743{
0b5c541b
KP		 744 int ret;
745
d54e9d28 746 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 747 intel_dp->algo.running = false;
748 intel_dp->algo.address = 0;
749 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
750
0206e353 751 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 752 intel_dp->adapter.owner = THIS_MODULE;
753 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 754 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 755 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
756 intel_dp->adapter.algo_data = &intel_dp->algo;
5bdebb18 757 intel_dp->adapter.dev.parent = intel_connector->base.kdev;
ea5b213a 758
0b5c541b 759 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
0b5c541b 760 return ret;
a4fc5ed6
KP		 761}
762
c6bb3538
DV		 763static void
764intel_dp_set_clock(struct intel_encoder *encoder,
765 struct intel_crtc_config *pipe_config, int link_bw)
766{
767 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 768 const struct dp_link_dpll *divisor = NULL;
769 int i, count = 0;
c6bb3538
DV		 770
771 if (IS_G4X(dev)) {
9dd4ffdf
CML		 772 divisor = gen4_dpll;
773 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 774 } else if (IS_HASWELL(dev)) {
775 /* Haswell has special-purpose DP DDI clocks. */
776 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 777 divisor = pch_dpll;
778 count = ARRAY_SIZE(pch_dpll);
c6bb3538 779 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 780 divisor = vlv_dpll;
781 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 782 }
9dd4ffdf
CML		 783
784 if (divisor && count) {
785 for (i = 0; i < count; i++) {
786 if (link_bw == divisor[i].link_bw) {
787 pipe_config->dpll = divisor[i].dpll;
788 pipe_config->clock_set = true;
789 break;
790 }
791 }
c6bb3538
DV		 792 }
793}
794
00c09d70 795bool
5bfe2ac0
DV		 796intel_dp_compute_config(struct intel_encoder *encoder,
797 struct intel_crtc_config *pipe_config)
a4fc5ed6 798{
5bfe2ac0 799 struct drm_device *dev = encoder->base.dev;
36008365 800 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 801 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 802 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 803 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 804 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 805 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 806 int lane_count, clock;
397fe157 807 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 808 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 809 int bpp, mode_rate;
a4fc5ed6 810 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
ff9a6750 811 int link_avail, link_clock;
a4fc5ed6 812
bc7d38a4 813 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 814 pipe_config->has_pch_encoder = true;
815
03afc4a2 816 pipe_config->has_dp_encoder = true;
a4fc5ed6 817
dd06f90e
JN		 818 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
819 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
820 adjusted_mode);
2dd24552
JB		 821 if (!HAS_PCH_SPLIT(dev))
822 intel_gmch_panel_fitting(intel_crtc, pipe_config,
823 intel_connector->panel.fitting_mode);
824 else
b074cec8
JB		 825 intel_pch_panel_fitting(intel_crtc, pipe_config,
826 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 827 }
828
cb1793ce 829 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 830 return false;
831
083f9560
DV		 832 DRM_DEBUG_KMS("DP link computation with max lane count %i "
833 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 834 max_lane_count, bws[max_clock],
835 adjusted_mode->crtc_clock);
083f9560 836
36008365
DV		 837 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
838 * bpc in between. */
3e7ca985 839 bpp = pipe_config->pipe_bpp;
6da7f10d
JN		 840 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
841 dev_priv->vbt.edp_bpp < bpp) {
7984211e
ID		 842 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
843 dev_priv->vbt.edp_bpp);
6da7f10d 844 bpp = dev_priv->vbt.edp_bpp;
7984211e 845 }
657445fe 846
36008365 847 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 848 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
849 bpp);
36008365
DV		 850
851 for (clock = 0; clock <= max_clock; clock++) {
852 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
853 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
854 link_avail = intel_dp_max_data_rate(link_clock,
855 lane_count);
856
857 if (mode_rate <= link_avail) {
858 goto found;
859 }
860 }
861 }
862 }
c4867936 863
36008365 864 return false;
3685a8f3 865
36008365 866found:
55bc60db
VS		 867 if (intel_dp->color_range_auto) {
868 /*
869 * See:
870 * CEA-861-E - 5.1 Default Encoding Parameters
871 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
872 */
18316c8c 873 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 874 intel_dp->color_range = DP_COLOR_RANGE_16_235;
875 else
876 intel_dp->color_range = 0;
877 }
878
3685a8f3 879 if (intel_dp->color_range)
50f3b016 880 pipe_config->limited_color_range = true;
a4fc5ed6 881
36008365
DV		 882 intel_dp->link_bw = bws[clock];
883 intel_dp->lane_count = lane_count;
657445fe 884 pipe_config->pipe_bpp = bpp;
ff9a6750 885 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 886
36008365
DV		 887 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
888 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 889 pipe_config->port_clock, bpp);
36008365
DV		 890 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
891 mode_rate, link_avail);
a4fc5ed6 892
03afc4a2 893 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 894 adjusted_mode->crtc_clock,
895 pipe_config->port_clock,
03afc4a2 896 &pipe_config->dp_m_n);
9d1a455b 897
c6bb3538
DV		 898 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
899
03afc4a2 900 return true;
a4fc5ed6
KP		 901}
902
7c62a164 903static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 904{
7c62a164
DV		 905 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
906 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
907 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 908 struct drm_i915_private *dev_priv = dev->dev_private;
909 u32 dpa_ctl;
910
ff9a6750 911 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 912 dpa_ctl = I915_READ(DP_A);
913 dpa_ctl &= ~DP_PLL_FREQ_MASK;
914
ff9a6750 915 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 916 /* For a long time we've carried around a ILK-DevA w/a for the
917 * 160MHz clock. If we're really unlucky, it's still required.
918 */
919 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 920 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 921 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 922 } else {
923 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 924 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 925 }
1ce17038 926
ea9b6006
DV		 927 I915_WRITE(DP_A, dpa_ctl);
928
929 POSTING_READ(DP_A);
930 udelay(500);
931}
932
b934223d 933static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 934{
b934223d 935 struct drm_device *dev = encoder->base.dev;
417e822d 936 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 937 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 938 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 939 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
940 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 941
417e822d 942 /*
1a2eb460 943 * There are four kinds of DP registers:
417e822d
KP		 944 *
945 * IBX PCH
1a2eb460
KP		 946 * SNB CPU
947 * IVB CPU
417e822d
KP		 948 * CPT PCH
949 *
950 * IBX PCH and CPU are the same for almost everything,
951 * except that the CPU DP PLL is configured in this
952 * register
953 *
954 * CPT PCH is quite different, having many bits moved
955 * to the TRANS_DP_CTL register instead. That
956 * configuration happens (oddly) in ironlake_pch_enable
957 */
9c9e7927 958
417e822d
KP		 959 /* Preserve the BIOS-computed detected bit. This is
960 * supposed to be read-only.
961 */
962 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 963
417e822d 964 /* Handle DP bits in common between all three register formats */
417e822d 965 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 966 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 967
e0dac65e
WF		 968 if (intel_dp->has_audio) {
969 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 970 pipe_name(crtc->pipe));
ea5b213a 971 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 972 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 973 }
247d89f6 974
417e822d 975 /* Split out the IBX/CPU vs CPT settings */
32f9d658 976
bc7d38a4 977 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 978 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
979 intel_dp->DP |= DP_SYNC_HS_HIGH;
980 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
981 intel_dp->DP |= DP_SYNC_VS_HIGH;
982 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
983
6aba5b6c 984 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 985 intel_dp->DP |= DP_ENHANCED_FRAMING;
986
7c62a164 987 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 988 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 989 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 990 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 991
992 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
993 intel_dp->DP |= DP_SYNC_HS_HIGH;
994 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
995 intel_dp->DP |= DP_SYNC_VS_HIGH;
996 intel_dp->DP |= DP_LINK_TRAIN_OFF;
997
6aba5b6c 998 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 999 intel_dp->DP |= DP_ENHANCED_FRAMING;
1000
7c62a164 1001 if (crtc->pipe == 1)
417e822d 1002 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 1003 } else {
1004 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1005 }
ea9b6006 1006
bc7d38a4 1007 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 1008 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 1009}
1010
99ea7127
KP		 1011#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1012#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1013
1014#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1015#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1016
1017#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1018#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1019
1020static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1021 u32 mask,
1022 u32 value)
bd943159 1023{
30add22d 1024 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1025 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1026 u32 pp_stat_reg, pp_ctrl_reg;
1027
bf13e81b
JN		 1028 pp_stat_reg = _pp_stat_reg(intel_dp);
1029 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1030
99ea7127 1031 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1032 mask, value,
1033 I915_READ(pp_stat_reg),
1034 I915_READ(pp_ctrl_reg));
32ce697c 1035
453c5420 1036 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1037 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1038 I915_READ(pp_stat_reg),
1039 I915_READ(pp_ctrl_reg));
32ce697c 1040 }
54c136d4
CW		 1041
1042 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1043}
32ce697c 1044
99ea7127
KP		 1045static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1046{
1047 DRM_DEBUG_KMS("Wait for panel power on\n");
1048 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1049}
1050
99ea7127
KP		 1051static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1052{
1053 DRM_DEBUG_KMS("Wait for panel power off time\n");
1054 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1055}
1056
1057static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1058{
1059 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1060 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1061}
1062
1063
832dd3c1
KP		 1064/* Read the current pp_control value, unlocking the register if it
1065 * is locked
1066 */
1067
453c5420 1068static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1069{
453c5420
JB		 1070 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1071 struct drm_i915_private *dev_priv = dev->dev_private;
1072 u32 control;
832dd3c1 1073
bf13e81b 1074 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1075 control &= ~PANEL_UNLOCK_MASK;
1076 control |= PANEL_UNLOCK_REGS;
1077 return control;
bd943159
KP		 1078}
1079
82a4d9c0 1080void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1081{
30add22d 1082 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1083 struct drm_i915_private *dev_priv = dev->dev_private;
1084 u32 pp;
453c5420 1085 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1086
97af61f5
KP		 1087 if (!is_edp(intel_dp))
1088 return;
5d613501 1089
bd943159
KP		 1090 WARN(intel_dp->want_panel_vdd,
1091 "eDP VDD already requested on\n");
1092
1093 intel_dp->want_panel_vdd = true;
99ea7127 1094
b0665d57 1095 if (ironlake_edp_have_panel_vdd(intel_dp))
bd943159 1096 return;
b0665d57 1097
e9cb81a2
PZ		 1098 intel_runtime_pm_get(dev_priv);
1099
b0665d57 1100 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1101
99ea7127
KP		 1102 if (!ironlake_edp_have_panel_power(intel_dp))
1103 ironlake_wait_panel_power_cycle(intel_dp);
1104
453c5420 1105 pp = ironlake_get_pp_control(intel_dp);
5d613501 1106 pp |= EDP_FORCE_VDD;
ebf33b18 1107
bf13e81b
JN		 1108 pp_stat_reg = _pp_stat_reg(intel_dp);
1109 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1110
1111 I915_WRITE(pp_ctrl_reg, pp);
1112 POSTING_READ(pp_ctrl_reg);
1113 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1114 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1115 /*
1116 * If the panel wasn't on, delay before accessing aux channel
1117 */
1118 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1119 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1120 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1121 }
5d613501
JB		 1122}
1123
bd943159 1124static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1125{
30add22d 1126 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1127 struct drm_i915_private *dev_priv = dev->dev_private;
1128 u32 pp;
453c5420 1129 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1130
a0e99e68
DV		 1131 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1132
bd943159 1133 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
b0665d57
PZ		 1134 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1135
453c5420 1136 pp = ironlake_get_pp_control(intel_dp);
bd943159 1137 pp &= ~EDP_FORCE_VDD;
bd943159 1138
9f08ef59
PZ		 1139 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1140 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1141
1142 I915_WRITE(pp_ctrl_reg, pp);
1143 POSTING_READ(pp_ctrl_reg);
99ea7127 1144
453c5420
JB		 1145 /* Make sure sequencer is idle before allowing subsequent activity */
1146 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1147 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1148
1149 if ((pp & POWER_TARGET_ON) == 0)
1150 msleep(intel_dp->panel_power_cycle_delay);
e9cb81a2
PZ		 1151
1152 intel_runtime_pm_put(dev_priv);
bd943159
KP		 1153 }
1154}
5d613501 1155
bd943159
KP		 1156static void ironlake_panel_vdd_work(struct work_struct *__work)
1157{
1158 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1159 struct intel_dp, panel_vdd_work);
30add22d 1160 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1161
627f7675 1162 mutex_lock(&dev->mode_config.mutex);
bd943159 1163 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1164 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1165}
1166
82a4d9c0 1167void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1168{
97af61f5
KP		 1169 if (!is_edp(intel_dp))
1170 return;
5d613501 1171
bd943159 1172 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1173
bd943159
KP		 1174 intel_dp->want_panel_vdd = false;
1175
1176 if (sync) {
1177 ironlake_panel_vdd_off_sync(intel_dp);
1178 } else {
1179 /*
1180 * Queue the timer to fire a long
1181 * time from now (relative to the power down delay)
1182 * to keep the panel power up across a sequence of operations
1183 */
1184 schedule_delayed_work(&intel_dp->panel_vdd_work,
1185 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1186 }
5d613501
JB		 1187}
1188
82a4d9c0 1189void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1190{
30add22d 1191 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1192 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1193 u32 pp;
453c5420 1194 u32 pp_ctrl_reg;
9934c132 1195
97af61f5 1196 if (!is_edp(intel_dp))
bd943159 1197 return;
99ea7127
KP		 1198
1199 DRM_DEBUG_KMS("Turn eDP power on\n");
1200
1201 if (ironlake_edp_have_panel_power(intel_dp)) {
1202 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1203 return;
99ea7127 1204 }
9934c132 1205
99ea7127 1206 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1207
bf13e81b 1208 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1209 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1210 if (IS_GEN5(dev)) {
1211 /* ILK workaround: disable reset around power sequence */
1212 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1213 I915_WRITE(pp_ctrl_reg, pp);
1214 POSTING_READ(pp_ctrl_reg);
05ce1a49 1215 }
37c6c9b0 1216
1c0ae80a 1217 pp |= POWER_TARGET_ON;
99ea7127
KP		 1218 if (!IS_GEN5(dev))
1219 pp |= PANEL_POWER_RESET;
1220
453c5420
JB		 1221 I915_WRITE(pp_ctrl_reg, pp);
1222 POSTING_READ(pp_ctrl_reg);
9934c132 1223
99ea7127 1224 ironlake_wait_panel_on(intel_dp);
9934c132 1225
05ce1a49
KP		 1226 if (IS_GEN5(dev)) {
1227 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1228 I915_WRITE(pp_ctrl_reg, pp);
1229 POSTING_READ(pp_ctrl_reg);
05ce1a49 1230 }
9934c132
JB		 1231}
1232
82a4d9c0 1233void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1234{
30add22d 1235 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1236 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1237 u32 pp;
453c5420 1238 u32 pp_ctrl_reg;
9934c132 1239
97af61f5
KP		 1240 if (!is_edp(intel_dp))
1241 return;
37c6c9b0 1242
99ea7127 1243 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1244
453c5420 1245 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1246 /* We need to switch off panel power _and_ force vdd, for otherwise some
1247 * panels get very unhappy and cease to work. */
dff392db 1248 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE);
453c5420 1249
bf13e81b 1250 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1251
1252 I915_WRITE(pp_ctrl_reg, pp);
1253 POSTING_READ(pp_ctrl_reg);
9934c132 1254
99ea7127 1255 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1256}
1257
d6c50ff8 1258void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1259{
da63a9f2
PZ		 1260 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1261 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1262 struct drm_i915_private *dev_priv = dev->dev_private;
1263 u32 pp;
453c5420 1264 u32 pp_ctrl_reg;
32f9d658 1265
f01eca2e
KP		 1266 if (!is_edp(intel_dp))
1267 return;
1268
28c97730 1269 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1270 /*
1271 * If we enable the backlight right away following a panel power
1272 * on, we may see slight flicker as the panel syncs with the eDP
1273 * link. So delay a bit to make sure the image is solid before
1274 * allowing it to appear.
1275 */
f01eca2e 1276 msleep(intel_dp->backlight_on_delay);
453c5420 1277 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1278 pp |= EDP_BLC_ENABLE;
453c5420 1279
bf13e81b 1280 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1281
1282 I915_WRITE(pp_ctrl_reg, pp);
1283 POSTING_READ(pp_ctrl_reg);
035aa3de 1284
752aa88a 1285 intel_panel_enable_backlight(intel_dp->attached_connector);
32f9d658
ZW		 1286}
1287
d6c50ff8 1288void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1289{
30add22d 1290 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1291 struct drm_i915_private *dev_priv = dev->dev_private;
1292 u32 pp;
453c5420 1293 u32 pp_ctrl_reg;
32f9d658 1294
f01eca2e
KP		 1295 if (!is_edp(intel_dp))
1296 return;
1297
752aa88a 1298 intel_panel_disable_backlight(intel_dp->attached_connector);
035aa3de 1299
28c97730 1300 DRM_DEBUG_KMS("\n");
453c5420 1301 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1302 pp &= ~EDP_BLC_ENABLE;
453c5420 1303
bf13e81b 1304 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1305
1306 I915_WRITE(pp_ctrl_reg, pp);
1307 POSTING_READ(pp_ctrl_reg);
f01eca2e 1308 msleep(intel_dp->backlight_off_delay);
32f9d658 1309}
a4fc5ed6 1310
2bd2ad64 1311static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1312{
da63a9f2
PZ		 1313 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1314 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1315 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1316 struct drm_i915_private *dev_priv = dev->dev_private;
1317 u32 dpa_ctl;
1318
2bd2ad64
DV		 1319 assert_pipe_disabled(dev_priv,
1320 to_intel_crtc(crtc)->pipe);
1321
d240f20f
JB		 1322 DRM_DEBUG_KMS("\n");
1323 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1324 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1325 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1326
1327 /* We don't adjust intel_dp->DP while tearing down the link, to
1328 * facilitate link retraining (e.g. after hotplug). Hence clear all
1329 * enable bits here to ensure that we don't enable too much. */
1330 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1331 intel_dp->DP |= DP_PLL_ENABLE;
1332 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1333 POSTING_READ(DP_A);
1334 udelay(200);
d240f20f
JB		 1335}
1336
2bd2ad64 1337static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1338{
da63a9f2
PZ		 1339 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1340 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1341 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1342 struct drm_i915_private *dev_priv = dev->dev_private;
1343 u32 dpa_ctl;
1344
2bd2ad64
DV		 1345 assert_pipe_disabled(dev_priv,
1346 to_intel_crtc(crtc)->pipe);
1347
d240f20f 1348 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1349 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1350 "dp pll off, should be on\n");
1351 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1352
1353 /* We can't rely on the value tracked for the DP register in
1354 * intel_dp->DP because link_down must not change that (otherwise link
1355 * re-training will fail. */
298b0b39 1356 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1357 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1358 POSTING_READ(DP_A);
d240f20f
JB		 1359 udelay(200);
1360}
1361
c7ad3810 1362/* If the sink supports it, try to set the power state appropriately */
c19b0669 1363void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1364{
1365 int ret, i;
1366
1367 /* Should have a valid DPCD by this point */
1368 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1369 return;
1370
1371 if (mode != DRM_MODE_DPMS_ON) {
1372 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1373 DP_SET_POWER_D3);
1374 if (ret != 1)
1375 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1376 } else {
1377 /*
1378 * When turning on, we need to retry for 1ms to give the sink
1379 * time to wake up.
1380 */
1381 for (i = 0; i < 3; i++) {
1382 ret = intel_dp_aux_native_write_1(intel_dp,
1383 DP_SET_POWER,
1384 DP_SET_POWER_D0);
1385 if (ret == 1)
1386 break;
1387 msleep(1);
1388 }
1389 }
1390}
1391
19d8fe15
DV		 1392static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1393 enum pipe *pipe)
d240f20f 1394{
19d8fe15 1395 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1396 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1397 struct drm_device *dev = encoder->base.dev;
1398 struct drm_i915_private *dev_priv = dev->dev_private;
1399 u32 tmp = I915_READ(intel_dp->output_reg);
1400
1401 if (!(tmp & DP_PORT_EN))
1402 return false;
1403
bc7d38a4 1404 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1405 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1406 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1407 *pipe = PORT_TO_PIPE(tmp);
1408 } else {
1409 u32 trans_sel;
1410 u32 trans_dp;
1411 int i;
1412
1413 switch (intel_dp->output_reg) {
1414 case PCH_DP_B:
1415 trans_sel = TRANS_DP_PORT_SEL_B;
1416 break;
1417 case PCH_DP_C:
1418 trans_sel = TRANS_DP_PORT_SEL_C;
1419 break;
1420 case PCH_DP_D:
1421 trans_sel = TRANS_DP_PORT_SEL_D;
1422 break;
1423 default:
1424 return true;
1425 }
1426
1427 for_each_pipe(i) {
1428 trans_dp = I915_READ(TRANS_DP_CTL(i));
1429 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1430 *pipe = i;
1431 return true;
1432 }
1433 }
19d8fe15 1434
4a0833ec
DV		 1435 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1436 intel_dp->output_reg);
1437 }
d240f20f 1438
19d8fe15
DV		 1439 return true;
1440}
d240f20f 1441
045ac3b5
JB		 1442static void intel_dp_get_config(struct intel_encoder *encoder,
1443 struct intel_crtc_config *pipe_config)
1444{
1445 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1446 u32 tmp, flags = 0;
63000ef6
XZ		 1447 struct drm_device *dev = encoder->base.dev;
1448 struct drm_i915_private *dev_priv = dev->dev_private;
1449 enum port port = dp_to_dig_port(intel_dp)->port;
1450 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1451 int dotclock;
045ac3b5 1452
63000ef6
XZ		 1453 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1454 tmp = I915_READ(intel_dp->output_reg);
1455 if (tmp & DP_SYNC_HS_HIGH)
1456 flags |= DRM_MODE_FLAG_PHSYNC;
1457 else
1458 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1459
63000ef6
XZ		 1460 if (tmp & DP_SYNC_VS_HIGH)
1461 flags |= DRM_MODE_FLAG_PVSYNC;
1462 else
1463 flags |= DRM_MODE_FLAG_NVSYNC;
1464 } else {
1465 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1466 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1467 flags |= DRM_MODE_FLAG_PHSYNC;
1468 else
1469 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1470
63000ef6
XZ		 1471 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1472 flags |= DRM_MODE_FLAG_PVSYNC;
1473 else
1474 flags |= DRM_MODE_FLAG_NVSYNC;
1475 }
045ac3b5
JB		 1476
1477 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1478
eb14cb74
VS		 1479 pipe_config->has_dp_encoder = true;
1480
1481 intel_dp_get_m_n(crtc, pipe_config);
1482
18442d08 1483 if (port == PORT_A) {
f1f644dc
JB		 1484 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1485 pipe_config->port_clock = 162000;
1486 else
1487 pipe_config->port_clock = 270000;
1488 }
18442d08
VS		 1489
1490 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1491 &pipe_config->dp_m_n);
1492
1493 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1494 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1495
241bfc38 1496 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1497
c6cd2ee2
JN		 1498 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1499 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1500 /*
1501 * This is a big fat ugly hack.
1502 *
1503 * Some machines in UEFI boot mode provide us a VBT that has 18
1504 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1505 * unknown we fail to light up. Yet the same BIOS boots up with
1506 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1507 * max, not what it tells us to use.
1508 *
1509 * Note: This will still be broken if the eDP panel is not lit
1510 * up by the BIOS, and thus we can't get the mode at module
1511 * load.
1512 */
1513 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1514 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1515 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1516 }
045ac3b5
JB		 1517}
1518
a031d709 1519static bool is_edp_psr(struct drm_device *dev)
2293bb5c 1520{
a031d709
RV		 1521 struct drm_i915_private *dev_priv = dev->dev_private;
1522
1523 return dev_priv->psr.sink_support;
2293bb5c
SK		 1524}
1525
2b28bb1b
RV		 1526static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1527{
1528 struct drm_i915_private *dev_priv = dev->dev_private;
1529
18b5992c 1530 if (!HAS_PSR(dev))
2b28bb1b
RV		 1531 return false;
1532
18b5992c 1533 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1534}
1535
1536static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1537 struct edp_vsc_psr *vsc_psr)
1538{
1539 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1540 struct drm_device *dev = dig_port->base.base.dev;
1541 struct drm_i915_private *dev_priv = dev->dev_private;
1542 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1543 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1544 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1545 uint32_t *data = (uint32_t *) vsc_psr;
1546 unsigned int i;
1547
1548 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1549 the video DIP being updated before program video DIP data buffer
1550 registers for DIP being updated. */
1551 I915_WRITE(ctl_reg, 0);
1552 POSTING_READ(ctl_reg);
1553
1554 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1555 if (i < sizeof(struct edp_vsc_psr))
1556 I915_WRITE(data_reg + i, *data++);
1557 else
1558 I915_WRITE(data_reg + i, 0);
1559 }
1560
1561 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1562 POSTING_READ(ctl_reg);
1563}
1564
1565static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1566{
1567 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1568 struct drm_i915_private *dev_priv = dev->dev_private;
1569 struct edp_vsc_psr psr_vsc;
1570
1571 if (intel_dp->psr_setup_done)
1572 return;
1573
1574 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1575 memset(&psr_vsc, 0, sizeof(psr_vsc));
1576 psr_vsc.sdp_header.HB0 = 0;
1577 psr_vsc.sdp_header.HB1 = 0x7;
1578 psr_vsc.sdp_header.HB2 = 0x2;
1579 psr_vsc.sdp_header.HB3 = 0x8;
1580 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1581
1582 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1583 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1584 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1585
1586 intel_dp->psr_setup_done = true;
1587}
1588
1589static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1590{
1591 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1592 struct drm_i915_private *dev_priv = dev->dev_private;
bc86625a 1593 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
2b28bb1b
RV		 1594 int precharge = 0x3;
1595 int msg_size = 5; /* Header(4) + Message(1) */
1596
1597 /* Enable PSR in sink */
1598 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1599 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1600 DP_PSR_ENABLE &
1601 ~DP_PSR_MAIN_LINK_ACTIVE);
1602 else
1603 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1604 DP_PSR_ENABLE |
1605 DP_PSR_MAIN_LINK_ACTIVE);
1606
1607 /* Setup AUX registers */
18b5992c
BW		 1608 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1609 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1610 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1611 DP_AUX_CH_CTL_TIME_OUT_400us |
1612 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1613 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1614 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1615}
1616
1617static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1618{
1619 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1620 struct drm_i915_private *dev_priv = dev->dev_private;
1621 uint32_t max_sleep_time = 0x1f;
1622 uint32_t idle_frames = 1;
1623 uint32_t val = 0x0;
ed8546ac 1624 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2b28bb1b
RV		 1625
1626 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1627 val |= EDP_PSR_LINK_STANDBY;
1628 val |= EDP_PSR_TP2_TP3_TIME_0us;
1629 val |= EDP_PSR_TP1_TIME_0us;
1630 val |= EDP_PSR_SKIP_AUX_EXIT;
1631 } else
1632 val |= EDP_PSR_LINK_DISABLE;
1633
18b5992c 1634 I915_WRITE(EDP_PSR_CTL(dev), val |
ed8546ac 1635 IS_BROADWELL(dev) ? 0 : link_entry_time |
2b28bb1b
RV		 1636 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1637 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1638 EDP_PSR_ENABLE);
1639}
1640
3f51e471
RV		 1641static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1642{
1643 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1644 struct drm_device *dev = dig_port->base.base.dev;
1645 struct drm_i915_private *dev_priv = dev->dev_private;
1646 struct drm_crtc *crtc = dig_port->base.base.crtc;
1647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1648 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1649 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1650
a031d709
RV		 1651 dev_priv->psr.source_ok = false;
1652
18b5992c 1653 if (!HAS_PSR(dev)) {
3f51e471 1654 DRM_DEBUG_KMS("PSR not supported on this platform\n");
3f51e471
RV		 1655 return false;
1656 }
1657
1658 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1659 (dig_port->port != PORT_A)) {
1660 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1661 return false;
1662 }
1663
105b7c11
RV		 1664 if (!i915_enable_psr) {
1665 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1666 return false;
1667 }
1668
cd234b0b
CW		 1669 crtc = dig_port->base.base.crtc;
1670 if (crtc == NULL) {
1671 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1672 return false;
1673 }
1674
1675 intel_crtc = to_intel_crtc(crtc);
20ddf665 1676 if (!intel_crtc_active(crtc)) {
3f51e471 1677 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1678 return false;
1679 }
1680
cd234b0b 1681 obj = to_intel_framebuffer(crtc->fb)->obj;
3f51e471
RV		 1682 if (obj->tiling_mode != I915_TILING_X ||
1683 obj->fence_reg == I915_FENCE_REG_NONE) {
1684 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1685 return false;
1686 }
1687
1688 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1689 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1690 return false;
1691 }
1692
1693 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1694 S3D_ENABLE) {
1695 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1696 return false;
1697 }
1698
ca73b4f0 1699 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1700 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1701 return false;
1702 }
1703
a031d709 1704 dev_priv->psr.source_ok = true;
3f51e471
RV		 1705 return true;
1706}
1707
3d739d92 1708static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1709{
1710 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1711
3f51e471
RV		 1712 if (!intel_edp_psr_match_conditions(intel_dp) ||
1713 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1714 return;
1715
1716 /* Setup PSR once */
1717 intel_edp_psr_setup(intel_dp);
1718
1719 /* Enable PSR on the panel */
1720 intel_edp_psr_enable_sink(intel_dp);
1721
1722 /* Enable PSR on the host */
1723 intel_edp_psr_enable_source(intel_dp);
1724}
1725
3d739d92
RV		 1726void intel_edp_psr_enable(struct intel_dp *intel_dp)
1727{
1728 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1729
1730 if (intel_edp_psr_match_conditions(intel_dp) &&
1731 !intel_edp_is_psr_enabled(dev))
1732 intel_edp_psr_do_enable(intel_dp);
1733}
1734
2b28bb1b
RV		 1735void intel_edp_psr_disable(struct intel_dp *intel_dp)
1736{
1737 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1738 struct drm_i915_private *dev_priv = dev->dev_private;
1739
1740 if (!intel_edp_is_psr_enabled(dev))
1741 return;
1742
18b5992c
BW		 1743 I915_WRITE(EDP_PSR_CTL(dev),
1744 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1745
1746 /* Wait till PSR is idle */
18b5992c 1747 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1748 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1749 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1750}
1751
3d739d92
RV		 1752void intel_edp_psr_update(struct drm_device *dev)
1753{
1754 struct intel_encoder *encoder;
1755 struct intel_dp *intel_dp = NULL;
1756
1757 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1758 if (encoder->type == INTEL_OUTPUT_EDP) {
1759 intel_dp = enc_to_intel_dp(&encoder->base);
1760
a031d709 1761 if (!is_edp_psr(dev))
3d739d92
RV		 1762 return;
1763
1764 if (!intel_edp_psr_match_conditions(intel_dp))
1765 intel_edp_psr_disable(intel_dp);
1766 else
1767 if (!intel_edp_is_psr_enabled(dev))
1768 intel_edp_psr_do_enable(intel_dp);
1769 }
1770}
1771
e8cb4558 1772static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1773{
e8cb4558 1774 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1775 enum port port = dp_to_dig_port(intel_dp)->port;
1776 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1777
1778 /* Make sure the panel is off before trying to change the mode. But also
1779 * ensure that we have vdd while we switch off the panel. */
21264c63 1780 ironlake_edp_backlight_off(intel_dp);
fdbc3b1f 1781 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
35a38556 1782 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1783
1784 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1785 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1786 intel_dp_link_down(intel_dp);
d240f20f
JB		 1787}
1788
2bd2ad64 1789static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1790{
2bd2ad64 1791 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1792 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1793 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1794
982a3866 1795 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1796 intel_dp_link_down(intel_dp);
b2634017
JB		 1797 if (!IS_VALLEYVIEW(dev))
1798 ironlake_edp_pll_off(intel_dp);
3739850b 1799 }
2bd2ad64
DV		 1800}
1801
e8cb4558 1802static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1803{
e8cb4558
DV		 1804 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1805 struct drm_device *dev = encoder->base.dev;
1806 struct drm_i915_private *dev_priv = dev->dev_private;
1807 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1808
0c33d8d7
DV		 1809 if (WARN_ON(dp_reg & DP_PORT_EN))
1810 return;
5d613501 1811
97af61f5 1812 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1813 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1814 intel_dp_start_link_train(intel_dp);
97af61f5 1815 ironlake_edp_panel_on(intel_dp);
bd943159 1816 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1817 intel_dp_complete_link_train(intel_dp);
3ab9c637 1818 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1819}
89b667f8 1820
ecff4f3b
JN		 1821static void g4x_enable_dp(struct intel_encoder *encoder)
1822{
828f5c6e
JN		 1823 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1824
ecff4f3b 1825 intel_enable_dp(encoder);
f01eca2e 1826 ironlake_edp_backlight_on(intel_dp);
ab1f90f9 1827}
89b667f8 1828
ab1f90f9
JN		 1829static void vlv_enable_dp(struct intel_encoder *encoder)
1830{
828f5c6e
JN		 1831 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1832
1833 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1834}
1835
ecff4f3b 1836static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1837{
1838 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1839 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1840
1841 if (dport->port == PORT_A)
1842 ironlake_edp_pll_on(intel_dp);
1843}
1844
1845static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1846{
2bd2ad64 1847 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1848 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1849 struct drm_device *dev = encoder->base.dev;
89b667f8 1850 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 1851 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 1852 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 1853 int pipe = intel_crtc->pipe;
bf13e81b 1854 struct edp_power_seq power_seq;
ab1f90f9 1855 u32 val;
a4fc5ed6 1856
ab1f90f9 1857 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1858
ab3c759a 1859 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 1860 val = 0;
1861 if (pipe)
1862 val |= (1<<21);
1863 else
1864 val &= ~(1<<21);
1865 val |= 0x001000c4;
ab3c759a
CML		 1866 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1867 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1868 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 1869
ab1f90f9
JN		 1870 mutex_unlock(&dev_priv->dpio_lock);
1871
bf13e81b
JN		 1872 /* init power sequencer on this pipe and port */
1873 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1874 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1875 &power_seq);
1876
ab1f90f9
JN		 1877 intel_enable_dp(encoder);
1878
e4607fcf 1879 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 1880}
1881
ecff4f3b 1882static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1883{
1884 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1885 struct drm_device *dev = encoder->base.dev;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1887 struct intel_crtc *intel_crtc =
1888 to_intel_crtc(encoder->base.crtc);
e4607fcf 1889 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 1890 int pipe = intel_crtc->pipe;
89b667f8 1891
89b667f8 1892 /* Program Tx lane resets to default */
0980a60f 1893 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 1894 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 1895 DPIO_PCS_TX_LANE2_RESET |
1896 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 1897 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 1898 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1899 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1900 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1901 DPIO_PCS_CLK_SOFT_RESET);
1902
1903 /* Fix up inter-pair skew failure */
ab3c759a
CML		 1904 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1905 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1906 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 1907 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 1908}
1909
1910/*
df0c237d
JB		 1911 * Native read with retry for link status and receiver capability reads for
1912 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1913 */
1914static bool
df0c237d
JB		 1915intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1916 uint8_t *recv, int recv_bytes)
a4fc5ed6 1917{
61da5fab
JB		 1918 int ret, i;
1919
df0c237d
JB		 1920 /*
1921 * Sinks are *supposed* to come up within 1ms from an off state,
1922 * but we're also supposed to retry 3 times per the spec.
1923 */
61da5fab 1924 for (i = 0; i < 3; i++) {
df0c237d
JB		 1925 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1926 recv_bytes);
1927 if (ret == recv_bytes)
61da5fab
JB		 1928 return true;
1929 msleep(1);
1930 }
a4fc5ed6 1931
61da5fab 1932 return false;
a4fc5ed6
KP		 1933}
1934
1935/*
1936 * Fetch AUX CH registers 0x202 - 0x207 which contain
1937 * link status information
1938 */
1939static bool
93f62dad 1940intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1941{
df0c237d
JB		 1942 return intel_dp_aux_native_read_retry(intel_dp,
1943 DP_LANE0_1_STATUS,
93f62dad 1944 link_status,
df0c237d 1945 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1946}
1947
a4fc5ed6
KP		 1948/*
1949 * These are source-specific values; current Intel hardware supports
1950 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1951 */
a4fc5ed6
KP		 1952
1953static uint8_t
1a2eb460 1954intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1955{
30add22d 1956 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1957 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1958
8f93f4f1 1959 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
e2fa6fba 1960 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 1961 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 1962 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 1963 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 1964 return DP_TRAIN_VOLTAGE_SWING_1200;
1965 else
1966 return DP_TRAIN_VOLTAGE_SWING_800;
1967}
1968
1969static uint8_t
1970intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1971{
30add22d 1972 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1973 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1974
8f93f4f1
PZ		 1975 if (IS_BROADWELL(dev)) {
1976 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1977 case DP_TRAIN_VOLTAGE_SWING_400:
1978 case DP_TRAIN_VOLTAGE_SWING_600:
1979 return DP_TRAIN_PRE_EMPHASIS_6;
1980 case DP_TRAIN_VOLTAGE_SWING_800:
1981 return DP_TRAIN_PRE_EMPHASIS_3_5;
1982 case DP_TRAIN_VOLTAGE_SWING_1200:
1983 default:
1984 return DP_TRAIN_PRE_EMPHASIS_0;
1985 }
1986 } else if (IS_HASWELL(dev)) {
d6c0d722
PZ		 1987 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1988 case DP_TRAIN_VOLTAGE_SWING_400:
1989 return DP_TRAIN_PRE_EMPHASIS_9_5;
1990 case DP_TRAIN_VOLTAGE_SWING_600:
1991 return DP_TRAIN_PRE_EMPHASIS_6;
1992 case DP_TRAIN_VOLTAGE_SWING_800:
1993 return DP_TRAIN_PRE_EMPHASIS_3_5;
1994 case DP_TRAIN_VOLTAGE_SWING_1200:
1995 default:
1996 return DP_TRAIN_PRE_EMPHASIS_0;
1997 }
e2fa6fba
P		 1998 } else if (IS_VALLEYVIEW(dev)) {
1999 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2000 case DP_TRAIN_VOLTAGE_SWING_400:
2001 return DP_TRAIN_PRE_EMPHASIS_9_5;
2002 case DP_TRAIN_VOLTAGE_SWING_600:
2003 return DP_TRAIN_PRE_EMPHASIS_6;
2004 case DP_TRAIN_VOLTAGE_SWING_800:
2005 return DP_TRAIN_PRE_EMPHASIS_3_5;
2006 case DP_TRAIN_VOLTAGE_SWING_1200:
2007 default:
2008 return DP_TRAIN_PRE_EMPHASIS_0;
2009 }
bc7d38a4 2010 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2011 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2012 case DP_TRAIN_VOLTAGE_SWING_400:
2013 return DP_TRAIN_PRE_EMPHASIS_6;
2014 case DP_TRAIN_VOLTAGE_SWING_600:
2015 case DP_TRAIN_VOLTAGE_SWING_800:
2016 return DP_TRAIN_PRE_EMPHASIS_3_5;
2017 default:
2018 return DP_TRAIN_PRE_EMPHASIS_0;
2019 }
2020 } else {
2021 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2022 case DP_TRAIN_VOLTAGE_SWING_400:
2023 return DP_TRAIN_PRE_EMPHASIS_6;
2024 case DP_TRAIN_VOLTAGE_SWING_600:
2025 return DP_TRAIN_PRE_EMPHASIS_6;
2026 case DP_TRAIN_VOLTAGE_SWING_800:
2027 return DP_TRAIN_PRE_EMPHASIS_3_5;
2028 case DP_TRAIN_VOLTAGE_SWING_1200:
2029 default:
2030 return DP_TRAIN_PRE_EMPHASIS_0;
2031 }
a4fc5ed6
KP		 2032 }
2033}
2034
e2fa6fba
P		 2035static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2036{
2037 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2038 struct drm_i915_private *dev_priv = dev->dev_private;
2039 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2040 struct intel_crtc *intel_crtc =
2041 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2042 unsigned long demph_reg_value, preemph_reg_value,
2043 uniqtranscale_reg_value;
2044 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2045 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2046 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2047
2048 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2049 case DP_TRAIN_PRE_EMPHASIS_0:
2050 preemph_reg_value = 0x0004000;
2051 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2052 case DP_TRAIN_VOLTAGE_SWING_400:
2053 demph_reg_value = 0x2B405555;
2054 uniqtranscale_reg_value = 0x552AB83A;
2055 break;
2056 case DP_TRAIN_VOLTAGE_SWING_600:
2057 demph_reg_value = 0x2B404040;
2058 uniqtranscale_reg_value = 0x5548B83A;
2059 break;
2060 case DP_TRAIN_VOLTAGE_SWING_800:
2061 demph_reg_value = 0x2B245555;
2062 uniqtranscale_reg_value = 0x5560B83A;
2063 break;
2064 case DP_TRAIN_VOLTAGE_SWING_1200:
2065 demph_reg_value = 0x2B405555;
2066 uniqtranscale_reg_value = 0x5598DA3A;
2067 break;
2068 default:
2069 return 0;
2070 }
2071 break;
2072 case DP_TRAIN_PRE_EMPHASIS_3_5:
2073 preemph_reg_value = 0x0002000;
2074 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2075 case DP_TRAIN_VOLTAGE_SWING_400:
2076 demph_reg_value = 0x2B404040;
2077 uniqtranscale_reg_value = 0x5552B83A;
2078 break;
2079 case DP_TRAIN_VOLTAGE_SWING_600:
2080 demph_reg_value = 0x2B404848;
2081 uniqtranscale_reg_value = 0x5580B83A;
2082 break;
2083 case DP_TRAIN_VOLTAGE_SWING_800:
2084 demph_reg_value = 0x2B404040;
2085 uniqtranscale_reg_value = 0x55ADDA3A;
2086 break;
2087 default:
2088 return 0;
2089 }
2090 break;
2091 case DP_TRAIN_PRE_EMPHASIS_6:
2092 preemph_reg_value = 0x0000000;
2093 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2094 case DP_TRAIN_VOLTAGE_SWING_400:
2095 demph_reg_value = 0x2B305555;
2096 uniqtranscale_reg_value = 0x5570B83A;
2097 break;
2098 case DP_TRAIN_VOLTAGE_SWING_600:
2099 demph_reg_value = 0x2B2B4040;
2100 uniqtranscale_reg_value = 0x55ADDA3A;
2101 break;
2102 default:
2103 return 0;
2104 }
2105 break;
2106 case DP_TRAIN_PRE_EMPHASIS_9_5:
2107 preemph_reg_value = 0x0006000;
2108 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2109 case DP_TRAIN_VOLTAGE_SWING_400:
2110 demph_reg_value = 0x1B405555;
2111 uniqtranscale_reg_value = 0x55ADDA3A;
2112 break;
2113 default:
2114 return 0;
2115 }
2116 break;
2117 default:
2118 return 0;
2119 }
2120
0980a60f 2121 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2122 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2123 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2124 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2125 uniqtranscale_reg_value);
ab3c759a
CML		 2126 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2127 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2128 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2129 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2130 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2131
2132 return 0;
2133}
2134
a4fc5ed6 2135static void
0301b3ac
JN		 2136intel_get_adjust_train(struct intel_dp *intel_dp,
2137 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2138{
2139 uint8_t v = 0;
2140 uint8_t p = 0;
2141 int lane;
1a2eb460
KP		 2142 uint8_t voltage_max;
2143 uint8_t preemph_max;
a4fc5ed6 2144
33a34e4e 2145 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2146 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2147 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2148
2149 if (this_v > v)
2150 v = this_v;
2151 if (this_p > p)
2152 p = this_p;
2153 }
2154
1a2eb460 2155 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2156 if (v >= voltage_max)
2157 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2158
1a2eb460
KP		 2159 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2160 if (p >= preemph_max)
2161 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2162
2163 for (lane = 0; lane < 4; lane++)
33a34e4e 2164 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2165}
2166
2167static uint32_t
f0a3424e 2168intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2169{
3cf2efb1 2170 uint32_t signal_levels = 0;
a4fc5ed6 2171
3cf2efb1 2172 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2173 case DP_TRAIN_VOLTAGE_SWING_400:
2174 default:
2175 signal_levels |= DP_VOLTAGE_0_4;
2176 break;
2177 case DP_TRAIN_VOLTAGE_SWING_600:
2178 signal_levels |= DP_VOLTAGE_0_6;
2179 break;
2180 case DP_TRAIN_VOLTAGE_SWING_800:
2181 signal_levels |= DP_VOLTAGE_0_8;
2182 break;
2183 case DP_TRAIN_VOLTAGE_SWING_1200:
2184 signal_levels |= DP_VOLTAGE_1_2;
2185 break;
2186 }
3cf2efb1 2187 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2188 case DP_TRAIN_PRE_EMPHASIS_0:
2189 default:
2190 signal_levels |= DP_PRE_EMPHASIS_0;
2191 break;
2192 case DP_TRAIN_PRE_EMPHASIS_3_5:
2193 signal_levels |= DP_PRE_EMPHASIS_3_5;
2194 break;
2195 case DP_TRAIN_PRE_EMPHASIS_6:
2196 signal_levels |= DP_PRE_EMPHASIS_6;
2197 break;
2198 case DP_TRAIN_PRE_EMPHASIS_9_5:
2199 signal_levels |= DP_PRE_EMPHASIS_9_5;
2200 break;
2201 }
2202 return signal_levels;
2203}
2204
e3421a18
ZW		 2205/* Gen6's DP voltage swing and pre-emphasis control */
2206static uint32_t
2207intel_gen6_edp_signal_levels(uint8_t train_set)
2208{
3c5a62b5
YL		 2209 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2210 DP_TRAIN_PRE_EMPHASIS_MASK);
2211 switch (signal_levels) {
e3421a18 2212 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2213 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2214 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2215 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2216 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2217 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2218 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2219 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2220 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2221 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2222 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2223 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2224 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2225 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2226 default:
3c5a62b5
YL		 2227 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2228 "0x%x\n", signal_levels);
2229 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2230 }
2231}
2232
1a2eb460
KP		 2233/* Gen7's DP voltage swing and pre-emphasis control */
2234static uint32_t
2235intel_gen7_edp_signal_levels(uint8_t train_set)
2236{
2237 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2238 DP_TRAIN_PRE_EMPHASIS_MASK);
2239 switch (signal_levels) {
2240 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2241 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2242 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2243 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2244 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2245 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2246
2247 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2248 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2249 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2250 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2251
2252 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2253 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2254 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2255 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2256
2257 default:
2258 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2259 "0x%x\n", signal_levels);
2260 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2261 }
2262}
2263
d6c0d722
PZ		 2264/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2265static uint32_t
f0a3424e 2266intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2267{
d6c0d722
PZ		 2268 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2269 DP_TRAIN_PRE_EMPHASIS_MASK);
2270 switch (signal_levels) {
2271 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2272 return DDI_BUF_EMP_400MV_0DB_HSW;
2273 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2274 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2275 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2276 return DDI_BUF_EMP_400MV_6DB_HSW;
2277 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2278 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2279
d6c0d722
PZ		 2280 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2281 return DDI_BUF_EMP_600MV_0DB_HSW;
2282 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2283 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2284 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2285 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2286
d6c0d722
PZ		 2287 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2288 return DDI_BUF_EMP_800MV_0DB_HSW;
2289 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2290 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2291 default:
2292 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2293 "0x%x\n", signal_levels);
2294 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2295 }
a4fc5ed6
KP		 2296}
2297
8f93f4f1
PZ		 2298static uint32_t
2299intel_bdw_signal_levels(uint8_t train_set)
2300{
2301 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2302 DP_TRAIN_PRE_EMPHASIS_MASK);
2303 switch (signal_levels) {
2304 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2305 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2306 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2307 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2308 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2309 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2310
2311 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2312 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2313 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2314 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2315 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2316 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2317
2318 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2319 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2320 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2321 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2322
2323 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2324 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2325
2326 default:
2327 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2328 "0x%x\n", signal_levels);
2329 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2330 }
2331}
2332
f0a3424e
PZ		 2333/* Properly updates "DP" with the correct signal levels. */
2334static void
2335intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2336{
2337 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2338 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2339 struct drm_device *dev = intel_dig_port->base.base.dev;
2340 uint32_t signal_levels, mask;
2341 uint8_t train_set = intel_dp->train_set[0];
2342
8f93f4f1
PZ		 2343 if (IS_BROADWELL(dev)) {
2344 signal_levels = intel_bdw_signal_levels(train_set);
2345 mask = DDI_BUF_EMP_MASK;
2346 } else if (IS_HASWELL(dev)) {
f0a3424e
PZ		 2347 signal_levels = intel_hsw_signal_levels(train_set);
2348 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2349 } else if (IS_VALLEYVIEW(dev)) {
2350 signal_levels = intel_vlv_signal_levels(intel_dp);
2351 mask = 0;
bc7d38a4 2352 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2353 signal_levels = intel_gen7_edp_signal_levels(train_set);
2354 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2355 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2356 signal_levels = intel_gen6_edp_signal_levels(train_set);
2357 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2358 } else {
2359 signal_levels = intel_gen4_signal_levels(train_set);
2360 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2361 }
2362
2363 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2364
2365 *DP = (*DP & ~mask) | signal_levels;
2366}
2367
a4fc5ed6 2368static bool
ea5b213a 2369intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2370 uint32_t *DP,
58e10eb9 2371 uint8_t dp_train_pat)
a4fc5ed6 2372{
174edf1f
PZ		 2373 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2374 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2375 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2376 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2377 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2378 int ret, len;
a4fc5ed6 2379
22b8bf17 2380 if (HAS_DDI(dev)) {
3ab9c637 2381 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2382
2383 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2384 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2385 else
2386 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2387
2388 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2389 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2390 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2391 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2392
2393 break;
2394 case DP_TRAINING_PATTERN_1:
2395 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2396 break;
2397 case DP_TRAINING_PATTERN_2:
2398 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2399 break;
2400 case DP_TRAINING_PATTERN_3:
2401 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2402 break;
2403 }
174edf1f 2404 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2405
bc7d38a4 2406 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2407 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2408
2409 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2410 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2411 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2412 break;
2413 case DP_TRAINING_PATTERN_1:
70aff66c 2414 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2415 break;
2416 case DP_TRAINING_PATTERN_2:
70aff66c 2417 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2418 break;
2419 case DP_TRAINING_PATTERN_3:
2420 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2421 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2422 break;
2423 }
2424
2425 } else {
70aff66c 2426 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2427
2428 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2429 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2430 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2431 break;
2432 case DP_TRAINING_PATTERN_1:
70aff66c 2433 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2434 break;
2435 case DP_TRAINING_PATTERN_2:
70aff66c 2436 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2437 break;
2438 case DP_TRAINING_PATTERN_3:
2439 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2440 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2441 break;
2442 }
2443 }
2444
70aff66c 2445 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2446 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2447
2cdfe6c8
JN		 2448 buf[0] = dp_train_pat;
2449 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2450 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2451 /* don't write DP_TRAINING_LANEx_SET on disable */
2452 len = 1;
2453 } else {
2454 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2455 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2456 len = intel_dp->lane_count + 1;
47ea7542 2457 }
a4fc5ed6 2458
2cdfe6c8
JN		 2459 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
2460 buf, len);
2461
2462 return ret == len;
a4fc5ed6
KP		 2463}
2464
70aff66c
JN		 2465static bool
2466intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2467 uint8_t dp_train_pat)
2468{
953d22e8 2469 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2470 intel_dp_set_signal_levels(intel_dp, DP);
2471 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2472}
2473
2474static bool
2475intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2476 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2477{
2478 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2479 struct drm_device *dev = intel_dig_port->base.base.dev;
2480 struct drm_i915_private *dev_priv = dev->dev_private;
2481 int ret;
2482
2483 intel_get_adjust_train(intel_dp, link_status);
2484 intel_dp_set_signal_levels(intel_dp, DP);
2485
2486 I915_WRITE(intel_dp->output_reg, *DP);
2487 POSTING_READ(intel_dp->output_reg);
2488
2489 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
2490 intel_dp->train_set,
2491 intel_dp->lane_count);
2492
2493 return ret == intel_dp->lane_count;
2494}
2495
3ab9c637
ID		 2496static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2497{
2498 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2499 struct drm_device *dev = intel_dig_port->base.base.dev;
2500 struct drm_i915_private *dev_priv = dev->dev_private;
2501 enum port port = intel_dig_port->port;
2502 uint32_t val;
2503
2504 if (!HAS_DDI(dev))
2505 return;
2506
2507 val = I915_READ(DP_TP_CTL(port));
2508 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2509 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2510 I915_WRITE(DP_TP_CTL(port), val);
2511
2512 /*
2513 * On PORT_A we can have only eDP in SST mode. There the only reason
2514 * we need to set idle transmission mode is to work around a HW issue
2515 * where we enable the pipe while not in idle link-training mode.
2516 * In this case there is requirement to wait for a minimum number of
2517 * idle patterns to be sent.
2518 */
2519 if (port == PORT_A)
2520 return;
2521
2522 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2523 1))
2524 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2525}
2526
33a34e4e 2527/* Enable corresponding port and start training pattern 1 */
c19b0669 2528void
33a34e4e 2529intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2530{
da63a9f2 2531 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2532 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2533 int i;
2534 uint8_t voltage;
cdb0e95b 2535 int voltage_tries, loop_tries;
ea5b213a 2536 uint32_t DP = intel_dp->DP;
6aba5b6c 2537 uint8_t link_config[2];
a4fc5ed6 2538
affa9354 2539 if (HAS_DDI(dev))
c19b0669
PZ		 2540 intel_ddi_prepare_link_retrain(encoder);
2541
3cf2efb1 2542 /* Write the link configuration data */
6aba5b6c
JN		 2543 link_config[0] = intel_dp->link_bw;
2544 link_config[1] = intel_dp->lane_count;
2545 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2546 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2547 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
2548
2549 link_config[0] = 0;
2550 link_config[1] = DP_SET_ANSI_8B10B;
2551 intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 2552
2553 DP |= DP_PORT_EN;
1a2eb460 2554
70aff66c
JN		 2555 /* clock recovery */
2556 if (!intel_dp_reset_link_train(intel_dp, &DP,
2557 DP_TRAINING_PATTERN_1 |
2558 DP_LINK_SCRAMBLING_DISABLE)) {
2559 DRM_ERROR("failed to enable link training\n");
2560 return;
2561 }
2562
a4fc5ed6 2563 voltage = 0xff;
cdb0e95b
KP		 2564 voltage_tries = 0;
2565 loop_tries = 0;
a4fc5ed6 2566 for (;;) {
70aff66c 2567 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 2568
a7c9655f 2569 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2570 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2571 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2572 break;
93f62dad 2573 }
a4fc5ed6 2574
01916270 2575 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2576 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2577 break;
2578 }
2579
2580 /* Check to see if we've tried the max voltage */
2581 for (i = 0; i < intel_dp->lane_count; i++)
2582 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2583 break;
3b4f819d 2584 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2585 ++loop_tries;
2586 if (loop_tries == 5) {
3def84b3 2587 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 2588 break;
2589 }
70aff66c
JN		 2590 intel_dp_reset_link_train(intel_dp, &DP,
2591 DP_TRAINING_PATTERN_1 |
2592 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 2593 voltage_tries = 0;
2594 continue;
2595 }
a4fc5ed6 2596
3cf2efb1 2597 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2598 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2599 ++voltage_tries;
b06fbda3 2600 if (voltage_tries == 5) {
3def84b3 2601 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 2602 break;
2603 }
2604 } else
2605 voltage_tries = 0;
2606 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2607
70aff66c
JN		 2608 /* Update training set as requested by target */
2609 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2610 DRM_ERROR("failed to update link training\n");
2611 break;
2612 }
a4fc5ed6
KP		 2613 }
2614
33a34e4e
JB		 2615 intel_dp->DP = DP;
2616}
2617
c19b0669 2618void
33a34e4e
JB		 2619intel_dp_complete_link_train(struct intel_dp *intel_dp)
2620{
33a34e4e 2621 bool channel_eq = false;
37f80975 2622 int tries, cr_tries;
33a34e4e
JB		 2623 uint32_t DP = intel_dp->DP;
2624
a4fc5ed6 2625 /* channel equalization */
70aff66c
JN		 2626 if (!intel_dp_set_link_train(intel_dp, &DP,
2627 DP_TRAINING_PATTERN_2 |
2628 DP_LINK_SCRAMBLING_DISABLE)) {
2629 DRM_ERROR("failed to start channel equalization\n");
2630 return;
2631 }
2632
a4fc5ed6 2633 tries = 0;
37f80975 2634 cr_tries = 0;
a4fc5ed6
KP		 2635 channel_eq = false;
2636 for (;;) {
70aff66c 2637 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2638
37f80975
JB		 2639 if (cr_tries > 5) {
2640 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 2641 break;
2642 }
2643
a7c9655f 2644 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 2645 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2646 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2647 break;
70aff66c 2648 }
a4fc5ed6 2649
37f80975 2650 /* Make sure clock is still ok */
01916270 2651 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 2652 intel_dp_start_link_train(intel_dp);
70aff66c
JN		 2653 intel_dp_set_link_train(intel_dp, &DP,
2654 DP_TRAINING_PATTERN_2 |
2655 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2656 cr_tries++;
2657 continue;
2658 }
2659
1ffdff13 2660 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2661 channel_eq = true;
2662 break;
2663 }
a4fc5ed6 2664
37f80975
JB		 2665 /* Try 5 times, then try clock recovery if that fails */
2666 if (tries > 5) {
2667 intel_dp_link_down(intel_dp);
2668 intel_dp_start_link_train(intel_dp);
70aff66c
JN		 2669 intel_dp_set_link_train(intel_dp, &DP,
2670 DP_TRAINING_PATTERN_2 |
2671 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2672 tries = 0;
2673 cr_tries++;
2674 continue;
2675 }
a4fc5ed6 2676
70aff66c
JN		 2677 /* Update training set as requested by target */
2678 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2679 DRM_ERROR("failed to update link training\n");
2680 break;
2681 }
3cf2efb1 2682 ++tries;
869184a6 2683 }
3cf2efb1 2684
3ab9c637
ID		 2685 intel_dp_set_idle_link_train(intel_dp);
2686
2687 intel_dp->DP = DP;
2688
d6c0d722 2689 if (channel_eq)
07f42258 2690 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2691
3ab9c637
ID		 2692}
2693
2694void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2695{
70aff66c 2696 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 2697 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2698}
2699
2700static void
ea5b213a 2701intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2702{
da63a9f2 2703 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2704 enum port port = intel_dig_port->port;
da63a9f2 2705 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2706 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2707 struct intel_crtc *intel_crtc =
2708 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2709 uint32_t DP = intel_dp->DP;
a4fc5ed6 2710
c19b0669
PZ		 2711 /*
2712 * DDI code has a strict mode set sequence and we should try to respect
2713 * it, otherwise we might hang the machine in many different ways. So we
2714 * really should be disabling the port only on a complete crtc_disable
2715 * sequence. This function is just called under two conditions on DDI
2716 * code:
2717 * - Link train failed while doing crtc_enable, and on this case we
2718 * really should respect the mode set sequence and wait for a
2719 * crtc_disable.
2720 * - Someone turned the monitor off and intel_dp_check_link_status
2721 * called us. We don't need to disable the whole port on this case, so
2722 * when someone turns the monitor on again,
2723 * intel_ddi_prepare_link_retrain will take care of redoing the link
2724 * train.
2725 */
affa9354 2726 if (HAS_DDI(dev))
c19b0669
PZ		 2727 return;
2728
0c33d8d7 2729 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2730 return;
2731
28c97730 2732 DRM_DEBUG_KMS("\n");
32f9d658 2733
bc7d38a4 2734 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2735 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2736 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2737 } else {
2738 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2739 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2740 }
fe255d00 2741 POSTING_READ(intel_dp->output_reg);
5eb08b69 2742
ab527efc
DV		 2743 /* We don't really know why we're doing this */
2744 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2745
493a7081 2746 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2747 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2748 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2749
5bddd17f
EA		 2750 /* Hardware workaround: leaving our transcoder select
2751 * set to transcoder B while it's off will prevent the
2752 * corresponding HDMI output on transcoder A.
2753 *
2754 * Combine this with another hardware workaround:
2755 * transcoder select bit can only be cleared while the
2756 * port is enabled.
2757 */
2758 DP &= ~DP_PIPEB_SELECT;
2759 I915_WRITE(intel_dp->output_reg, DP);
2760
2761 /* Changes to enable or select take place the vblank
2762 * after being written.
2763 */
ff50afe9
DV		 2764 if (WARN_ON(crtc == NULL)) {
2765 /* We should never try to disable a port without a crtc
2766 * attached. For paranoia keep the code around for a
2767 * bit. */
31acbcc4
CW		 2768 POSTING_READ(intel_dp->output_reg);
2769 msleep(50);
2770 } else
ab527efc 2771 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2772 }
2773
832afda6 2774 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2775 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2776 POSTING_READ(intel_dp->output_reg);
f01eca2e 2777 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2778}
2779
26d61aad
KP		 2780static bool
2781intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2782{
a031d709
RV		 2783 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2784 struct drm_device *dev = dig_port->base.base.dev;
2785 struct drm_i915_private *dev_priv = dev->dev_private;
2786
577c7a50
DL		 2787 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2788
92fd8fd1 2789 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2790 sizeof(intel_dp->dpcd)) == 0)
2791 return false; /* aux transfer failed */
92fd8fd1 2792
577c7a50
DL		 2793 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2794 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2795 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2796
edb39244
AJ		 2797 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2798 return false; /* DPCD not present */
2799
2293bb5c
SK		 2800 /* Check if the panel supports PSR */
2801 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939
JN		 2802 if (is_edp(intel_dp)) {
2803 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2804 intel_dp->psr_dpcd,
2805 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 2806 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2807 dev_priv->psr.sink_support = true;
50003939 2808 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 2809 }
50003939
JN		 2810 }
2811
edb39244
AJ		 2812 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2813 DP_DWN_STRM_PORT_PRESENT))
2814 return true; /* native DP sink */
2815
2816 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2817 return true; /* no per-port downstream info */
2818
2819 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2820 intel_dp->downstream_ports,
2821 DP_MAX_DOWNSTREAM_PORTS) == 0)
2822 return false; /* downstream port status fetch failed */
2823
2824 return true;
92fd8fd1
KP		 2825}
2826
0d198328
AJ		 2827static void
2828intel_dp_probe_oui(struct intel_dp *intel_dp)
2829{
2830 u8 buf[3];
2831
2832 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2833 return;
2834
351cfc34
DV		 2835 ironlake_edp_panel_vdd_on(intel_dp);
2836
0d198328
AJ		 2837 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2838 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2839 buf[0], buf[1], buf[2]);
2840
2841 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2842 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2843 buf[0], buf[1], buf[2]);
351cfc34
DV		 2844
2845 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2846}
2847
a60f0e38
JB		 2848static bool
2849intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2850{
2851 int ret;
2852
2853 ret = intel_dp_aux_native_read_retry(intel_dp,
2854 DP_DEVICE_SERVICE_IRQ_VECTOR,
2855 sink_irq_vector, 1);
2856 if (!ret)
2857 return false;
2858
2859 return true;
2860}
2861
2862static void
2863intel_dp_handle_test_request(struct intel_dp *intel_dp)
2864{
2865 /* NAK by default */
9324cf7f 2866 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2867}
2868
a4fc5ed6
KP		 2869/*
2870 * According to DP spec
2871 * 5.1.2:
2872 * 1. Read DPCD
2873 * 2. Configure link according to Receiver Capabilities
2874 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2875 * 4. Check link status on receipt of hot-plug interrupt
2876 */
2877
00c09d70 2878void
ea5b213a 2879intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2880{
da63a9f2 2881 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2882 u8 sink_irq_vector;
93f62dad 2883 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2884
da63a9f2 2885 if (!intel_encoder->connectors_active)
d2b996ac 2886 return;
59cd09e1 2887
da63a9f2 2888 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2889 return;
2890
92fd8fd1 2891 /* Try to read receiver status if the link appears to be up */
93f62dad 2892 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 2893 return;
2894 }
2895
92fd8fd1 2896 /* Now read the DPCD to see if it's actually running */
26d61aad 2897 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2898 return;
2899 }
2900
a60f0e38
JB		 2901 /* Try to read the source of the interrupt */
2902 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2903 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2904 /* Clear interrupt source */
2905 intel_dp_aux_native_write_1(intel_dp,
2906 DP_DEVICE_SERVICE_IRQ_VECTOR,
2907 sink_irq_vector);
2908
2909 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2910 intel_dp_handle_test_request(intel_dp);
2911 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2912 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2913 }
2914
1ffdff13 2915 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2916 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2917 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2918 intel_dp_start_link_train(intel_dp);
2919 intel_dp_complete_link_train(intel_dp);
3ab9c637 2920 intel_dp_stop_link_train(intel_dp);
33a34e4e 2921 }
a4fc5ed6 2922}
a4fc5ed6 2923
caf9ab24 2924/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2925static enum drm_connector_status
26d61aad 2926intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2927{
caf9ab24 2928 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 2929 uint8_t type;
2930
2931 if (!intel_dp_get_dpcd(intel_dp))
2932 return connector_status_disconnected;
2933
2934 /* if there's no downstream port, we're done */
2935 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2936 return connector_status_connected;
caf9ab24
AJ		 2937
2938 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 2939 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2940 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 2941 uint8_t reg;
caf9ab24 2942 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2943 &reg, 1))
caf9ab24 2944 return connector_status_unknown;
23235177
AJ		 2945 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2946 : connector_status_disconnected;
caf9ab24
AJ		 2947 }
2948
2949 /* If no HPD, poke DDC gently */
2950 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2951 return connector_status_connected;
caf9ab24
AJ		 2952
2953 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 2954 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
2955 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2956 if (type == DP_DS_PORT_TYPE_VGA ||
2957 type == DP_DS_PORT_TYPE_NON_EDID)
2958 return connector_status_unknown;
2959 } else {
2960 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2961 DP_DWN_STRM_PORT_TYPE_MASK;
2962 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
2963 type == DP_DWN_STRM_PORT_TYPE_OTHER)
2964 return connector_status_unknown;
2965 }
caf9ab24
AJ		 2966
2967 /* Anything else is out of spec, warn and ignore */
2968 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2969 return connector_status_disconnected;
71ba9000
AJ		 2970}
2971
5eb08b69 2972static enum drm_connector_status
a9756bb5 2973ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2974{
30add22d 2975 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2976 struct drm_i915_private *dev_priv = dev->dev_private;
2977 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2978 enum drm_connector_status status;
2979
fe16d949
CW		 2980 /* Can't disconnect eDP, but you can close the lid... */
2981 if (is_edp(intel_dp)) {
30add22d 2982 status = intel_panel_detect(dev);
fe16d949
CW		 2983 if (status == connector_status_unknown)
2984 status = connector_status_connected;
2985 return status;
2986 }
01cb9ea6 2987
1b469639
DL		 2988 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2989 return connector_status_disconnected;
2990
26d61aad 2991 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2992}
2993
a4fc5ed6 2994static enum drm_connector_status
a9756bb5 2995g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2996{
30add22d 2997 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2998 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 2999 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3000 uint32_t bit;
5eb08b69 3001
35aad75f
JB		 3002 /* Can't disconnect eDP, but you can close the lid... */
3003 if (is_edp(intel_dp)) {
3004 enum drm_connector_status status;
3005
3006 status = intel_panel_detect(dev);
3007 if (status == connector_status_unknown)
3008 status = connector_status_connected;
3009 return status;
3010 }
3011
232a6ee9
TP		 3012 if (IS_VALLEYVIEW(dev)) {
3013 switch (intel_dig_port->port) {
3014 case PORT_B:
3015 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3016 break;
3017 case PORT_C:
3018 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3019 break;
3020 case PORT_D:
3021 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3022 break;
3023 default:
3024 return connector_status_unknown;
3025 }
3026 } else {
3027 switch (intel_dig_port->port) {
3028 case PORT_B:
3029 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3030 break;
3031 case PORT_C:
3032 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3033 break;
3034 case PORT_D:
3035 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3036 break;
3037 default:
3038 return connector_status_unknown;
3039 }
a4fc5ed6
KP		 3040 }
3041
10f76a38 3042 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3043 return connector_status_disconnected;
3044
26d61aad 3045 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3046}
3047
8c241fef
KP		 3048static struct edid *
3049intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3050{
9cd300e0 3051 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3052
9cd300e0
JN		 3053 /* use cached edid if we have one */
3054 if (intel_connector->edid) {
9cd300e0
JN		 3055 /* invalid edid */
3056 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3057 return NULL;
3058
55e9edeb 3059 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3060 }
8c241fef 3061
9cd300e0 3062 return drm_get_edid(connector, adapter);
8c241fef
KP		 3063}
3064
3065static int
3066intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3067{
9cd300e0 3068 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3069
9cd300e0
JN		 3070 /* use cached edid if we have one */
3071 if (intel_connector->edid) {
3072 /* invalid edid */
3073 if (IS_ERR(intel_connector->edid))
3074 return 0;
3075
3076 return intel_connector_update_modes(connector,
3077 intel_connector->edid);
d6f24d0f
JB		 3078 }
3079
9cd300e0 3080 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3081}
3082
a9756bb5
ZW		 3083static enum drm_connector_status
3084intel_dp_detect(struct drm_connector *connector, bool force)
3085{
3086 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3087 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3088 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3089 struct drm_device *dev = connector->dev;
c8c8fb33 3090 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5
ZW		 3091 enum drm_connector_status status;
3092 struct edid *edid = NULL;
3093
c8c8fb33
PZ		 3094 intel_runtime_pm_get(dev_priv);
3095
164c8598
CW		 3096 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3097 connector->base.id, drm_get_connector_name(connector));
3098
a9756bb5
ZW		 3099 intel_dp->has_audio = false;
3100
3101 if (HAS_PCH_SPLIT(dev))
3102 status = ironlake_dp_detect(intel_dp);
3103 else
3104 status = g4x_dp_detect(intel_dp);
1b9be9d0 3105
a9756bb5 3106 if (status != connector_status_connected)
c8c8fb33 3107 goto out;
a9756bb5 3108
0d198328
AJ		 3109 intel_dp_probe_oui(intel_dp);
3110
c3e5f67b
DV		 3111 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3112 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3113 } else {
8c241fef 3114 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 3115 if (edid) {
3116 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3117 kfree(edid);
3118 }
a9756bb5
ZW		 3119 }
3120
d63885da
PZ		 3121 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3122 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3123 status = connector_status_connected;
3124
3125out:
3126 intel_runtime_pm_put(dev_priv);
3127 return status;
a4fc5ed6
KP		 3128}
3129
3130static int intel_dp_get_modes(struct drm_connector *connector)
3131{
df0e9248 3132 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 3133 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3134 struct drm_device *dev = connector->dev;
32f9d658 3135 int ret;
a4fc5ed6
KP		 3136
3137 /* We should parse the EDID data and find out if it has an audio sink
3138 */
3139
8c241fef 3140 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 3141 if (ret)
32f9d658
ZW		 3142 return ret;
3143
f8779fda 3144 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3145 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3146 struct drm_display_mode *mode;
dd06f90e
JN		 3147 mode = drm_mode_duplicate(dev,
3148 intel_connector->panel.fixed_mode);
f8779fda 3149 if (mode) {
32f9d658
ZW		 3150 drm_mode_probed_add(connector, mode);
3151 return 1;
3152 }
3153 }
3154 return 0;
a4fc5ed6
KP		 3155}
3156
1aad7ac0
CW		 3157static bool
3158intel_dp_detect_audio(struct drm_connector *connector)
3159{
3160 struct intel_dp *intel_dp = intel_attached_dp(connector);
3161 struct edid *edid;
3162 bool has_audio = false;
3163
8c241fef 3164 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 3165 if (edid) {
3166 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3167 kfree(edid);
3168 }
3169
3170 return has_audio;
3171}
3172
f684960e
CW		 3173static int
3174intel_dp_set_property(struct drm_connector *connector,
3175 struct drm_property *property,
3176 uint64_t val)
3177{
e953fd7b 3178 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3179 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3180 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3181 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3182 int ret;
3183
662595df 3184 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3185 if (ret)
3186 return ret;
3187
3f43c48d 3188 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3189 int i = val;
3190 bool has_audio;
3191
3192 if (i == intel_dp->force_audio)
f684960e
CW		 3193 return 0;
3194
1aad7ac0 3195 intel_dp->force_audio = i;
f684960e 3196
c3e5f67b 3197 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3198 has_audio = intel_dp_detect_audio(connector);
3199 else
c3e5f67b 3200 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3201
3202 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3203 return 0;
3204
1aad7ac0 3205 intel_dp->has_audio = has_audio;
f684960e
CW		 3206 goto done;
3207 }
3208
e953fd7b 3209 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3210 bool old_auto = intel_dp->color_range_auto;
3211 uint32_t old_range = intel_dp->color_range;
3212
55bc60db
VS		 3213 switch (val) {
3214 case INTEL_BROADCAST_RGB_AUTO:
3215 intel_dp->color_range_auto = true;
3216 break;
3217 case INTEL_BROADCAST_RGB_FULL:
3218 intel_dp->color_range_auto = false;
3219 intel_dp->color_range = 0;
3220 break;
3221 case INTEL_BROADCAST_RGB_LIMITED:
3222 intel_dp->color_range_auto = false;
3223 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3224 break;
3225 default:
3226 return -EINVAL;
3227 }
ae4edb80
DV		 3228
3229 if (old_auto == intel_dp->color_range_auto &&
3230 old_range == intel_dp->color_range)
3231 return 0;
3232
e953fd7b
CW		 3233 goto done;
3234 }
3235
53b41837
YN		 3236 if (is_edp(intel_dp) &&
3237 property == connector->dev->mode_config.scaling_mode_property) {
3238 if (val == DRM_MODE_SCALE_NONE) {
3239 DRM_DEBUG_KMS("no scaling not supported\n");
3240 return -EINVAL;
3241 }
3242
3243 if (intel_connector->panel.fitting_mode == val) {
3244 /* the eDP scaling property is not changed */
3245 return 0;
3246 }
3247 intel_connector->panel.fitting_mode = val;
3248
3249 goto done;
3250 }
3251
f684960e
CW		 3252 return -EINVAL;
3253
3254done:
c0c36b94
CW		 3255 if (intel_encoder->base.crtc)
3256 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3257
3258 return 0;
3259}
3260
a4fc5ed6 3261static void
73845adf 3262intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3263{
1d508706 3264 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3265
9cd300e0
JN		 3266 if (!IS_ERR_OR_NULL(intel_connector->edid))
3267 kfree(intel_connector->edid);
3268
acd8db10
PZ		 3269 /* Can't call is_edp() since the encoder may have been destroyed
3270 * already. */
3271 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3272 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3273
a4fc5ed6 3274 drm_connector_cleanup(connector);
55f78c43 3275 kfree(connector);
a4fc5ed6
KP		 3276}
3277
00c09d70 3278void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3279{
da63a9f2
PZ		 3280 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3281 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3282 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927
DV		 3283
3284 i2c_del_adapter(&intel_dp->adapter);
3285 drm_encoder_cleanup(encoder);
bd943159
KP		 3286 if (is_edp(intel_dp)) {
3287 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3288 mutex_lock(&dev->mode_config.mutex);
bd943159 3289 ironlake_panel_vdd_off_sync(intel_dp);
bd173813 3290 mutex_unlock(&dev->mode_config.mutex);
bd943159 3291 }
da63a9f2 3292 kfree(intel_dig_port);
24d05927
DV		 3293}
3294
a4fc5ed6 3295static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3296 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3297 .detect = intel_dp_detect,
3298 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3299 .set_property = intel_dp_set_property,
73845adf 3300 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3301};
3302
3303static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3304 .get_modes = intel_dp_get_modes,
3305 .mode_valid = intel_dp_mode_valid,
df0e9248 3306 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3307};
3308
a4fc5ed6 3309static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3310 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3311};
3312
995b6762 3313static void
21d40d37 3314intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3315{
fa90ecef 3316 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3317
885a5014 3318 intel_dp_check_link_status(intel_dp);
c8110e52 3319}
6207937d 3320
e3421a18
ZW		 3321/* Return which DP Port should be selected for Transcoder DP control */
3322int
0206e353 3323intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3324{
3325 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3326 struct intel_encoder *intel_encoder;
3327 struct intel_dp *intel_dp;
e3421a18 3328
fa90ecef
PZ		 3329 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3330 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3331
fa90ecef
PZ		 3332 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3333 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3334 return intel_dp->output_reg;
e3421a18 3335 }
ea5b213a 3336
e3421a18
ZW		 3337 return -1;
3338}
3339
36e83a18 3340/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3341bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3342{
3343 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3344 union child_device_config *p_child;
36e83a18 3345 int i;
5d8a7752
VS		 3346 static const short port_mapping[] = {
3347 [PORT_B] = PORT_IDPB,
3348 [PORT_C] = PORT_IDPC,
3349 [PORT_D] = PORT_IDPD,
3350 };
36e83a18 3351
3b32a35b
VS		 3352 if (port == PORT_A)
3353 return true;
3354
41aa3448 3355 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3356 return false;
3357
41aa3448
RV		 3358 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3359 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3360
5d8a7752 3361 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3362 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3363 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3364 return true;
3365 }
3366 return false;
3367}
3368
f684960e
CW		 3369static void
3370intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3371{
53b41837
YN		 3372 struct intel_connector *intel_connector = to_intel_connector(connector);
3373
3f43c48d 3374 intel_attach_force_audio_property(connector);
e953fd7b 3375 intel_attach_broadcast_rgb_property(connector);
55bc60db 3376 intel_dp->color_range_auto = true;
53b41837
YN		 3377
3378 if (is_edp(intel_dp)) {
3379 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3380 drm_object_attach_property(
3381 &connector->base,
53b41837 3382 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3383 DRM_MODE_SCALE_ASPECT);
3384 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3385 }
f684960e
CW		 3386}
3387
67a54566
DV		 3388static void
3389intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3390 struct intel_dp *intel_dp,
3391 struct edp_power_seq *out)
67a54566
DV		 3392{
3393 struct drm_i915_private *dev_priv = dev->dev_private;
3394 struct edp_power_seq cur, vbt, spec, final;
3395 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3396 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3397
3398 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3399 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3400 pp_on_reg = PCH_PP_ON_DELAYS;
3401 pp_off_reg = PCH_PP_OFF_DELAYS;
3402 pp_div_reg = PCH_PP_DIVISOR;
3403 } else {
bf13e81b
JN		 3404 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3405
3406 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3407 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3408 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3409 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3410 }
67a54566
DV		 3411
3412 /* Workaround: Need to write PP_CONTROL with the unlock key as
3413 * the very first thing. */
453c5420 3414 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3415 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3416
453c5420
JB		 3417 pp_on = I915_READ(pp_on_reg);
3418 pp_off = I915_READ(pp_off_reg);
3419 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3420
3421 /* Pull timing values out of registers */
3422 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3423 PANEL_POWER_UP_DELAY_SHIFT;
3424
3425 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3426 PANEL_LIGHT_ON_DELAY_SHIFT;
3427
3428 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3429 PANEL_LIGHT_OFF_DELAY_SHIFT;
3430
3431 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3432 PANEL_POWER_DOWN_DELAY_SHIFT;
3433
3434 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3435 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3436
3437 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3438 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3439
41aa3448 3440 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3441
3442 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3443 * our hw here, which are all in 100usec. */
3444 spec.t1_t3 = 210 * 10;
3445 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3446 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3447 spec.t10 = 500 * 10;
3448 /* This one is special and actually in units of 100ms, but zero
3449 * based in the hw (so we need to add 100 ms). But the sw vbt
3450 * table multiplies it with 1000 to make it in units of 100usec,
3451 * too. */
3452 spec.t11_t12 = (510 + 100) * 10;
3453
3454 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3455 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3456
3457 /* Use the max of the register settings and vbt. If both are
3458 * unset, fall back to the spec limits. */
3459#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3460 spec.field : \
3461 max(cur.field, vbt.field))
3462 assign_final(t1_t3);
3463 assign_final(t8);
3464 assign_final(t9);
3465 assign_final(t10);
3466 assign_final(t11_t12);
3467#undef assign_final
3468
3469#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3470 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3471 intel_dp->backlight_on_delay = get_delay(t8);
3472 intel_dp->backlight_off_delay = get_delay(t9);
3473 intel_dp->panel_power_down_delay = get_delay(t10);
3474 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3475#undef get_delay
3476
f30d26e4
JN		 3477 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3478 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3479 intel_dp->panel_power_cycle_delay);
3480
3481 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3482 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3483
3484 if (out)
3485 *out = final;
3486}
3487
3488static void
3489intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3490 struct intel_dp *intel_dp,
3491 struct edp_power_seq *seq)
3492{
3493 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3494 u32 pp_on, pp_off, pp_div, port_sel = 0;
3495 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3496 int pp_on_reg, pp_off_reg, pp_div_reg;
3497
3498 if (HAS_PCH_SPLIT(dev)) {
3499 pp_on_reg = PCH_PP_ON_DELAYS;
3500 pp_off_reg = PCH_PP_OFF_DELAYS;
3501 pp_div_reg = PCH_PP_DIVISOR;
3502 } else {
bf13e81b
JN		 3503 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3504
3505 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3506 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3507 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3508 }
3509
67a54566 3510 /* And finally store the new values in the power sequencer. */
f30d26e4
JN		 3511 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3512 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3513 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3514 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3515 /* Compute the divisor for the pp clock, simply match the Bspec
3516 * formula. */
453c5420 3517 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3518 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3519 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3520
3521 /* Haswell doesn't have any port selection bits for the panel
3522 * power sequencer any more. */
bc7d38a4 3523 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3524 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3525 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3526 else
3527 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3528 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3529 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3530 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3531 else
a24c144c 3532 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3533 }
3534
453c5420
JB		 3535 pp_on |= port_sel;
3536
3537 I915_WRITE(pp_on_reg, pp_on);
3538 I915_WRITE(pp_off_reg, pp_off);
3539 I915_WRITE(pp_div_reg, pp_div);
67a54566 3540
67a54566 3541 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3542 I915_READ(pp_on_reg),
3543 I915_READ(pp_off_reg),
3544 I915_READ(pp_div_reg));
f684960e
CW		 3545}
3546
ed92f0b2
PZ		 3547static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3548 struct intel_connector *intel_connector)
3549{
3550 struct drm_connector *connector = &intel_connector->base;
3551 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3552 struct drm_device *dev = intel_dig_port->base.base.dev;
3553 struct drm_i915_private *dev_priv = dev->dev_private;
3554 struct drm_display_mode *fixed_mode = NULL;
3555 struct edp_power_seq power_seq = { 0 };
3556 bool has_dpcd;
3557 struct drm_display_mode *scan;
3558 struct edid *edid;
3559
3560 if (!is_edp(intel_dp))
3561 return true;
3562
3563 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3564
3565 /* Cache DPCD and EDID for edp. */
3566 ironlake_edp_panel_vdd_on(intel_dp);
3567 has_dpcd = intel_dp_get_dpcd(intel_dp);
3568 ironlake_edp_panel_vdd_off(intel_dp, false);
3569
3570 if (has_dpcd) {
3571 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3572 dev_priv->no_aux_handshake =
3573 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3574 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3575 } else {
3576 /* if this fails, presume the device is a ghost */
3577 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3578 return false;
3579 }
3580
3581 /* We now know it's not a ghost, init power sequence regs. */
3582 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3583 &power_seq);
3584
ed92f0b2
PZ		 3585 edid = drm_get_edid(connector, &intel_dp->adapter);
3586 if (edid) {
3587 if (drm_add_edid_modes(connector, edid)) {
3588 drm_mode_connector_update_edid_property(connector,
3589 edid);
3590 drm_edid_to_eld(connector, edid);
3591 } else {
3592 kfree(edid);
3593 edid = ERR_PTR(-EINVAL);
3594 }
3595 } else {
3596 edid = ERR_PTR(-ENOENT);
3597 }
3598 intel_connector->edid = edid;
3599
3600 /* prefer fixed mode from EDID if available */
3601 list_for_each_entry(scan, &connector->probed_modes, head) {
3602 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3603 fixed_mode = drm_mode_duplicate(dev, scan);
3604 break;
3605 }
3606 }
3607
3608 /* fallback to VBT if available for eDP */
3609 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3610 fixed_mode = drm_mode_duplicate(dev,
3611 dev_priv->vbt.lfp_lvds_vbt_mode);
3612 if (fixed_mode)
3613 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3614 }
3615
ed92f0b2
PZ		 3616 intel_panel_init(&intel_connector->panel, fixed_mode);
3617 intel_panel_setup_backlight(connector);
3618
3619 return true;
3620}
3621
16c25533 3622bool
f0fec3f2
PZ		 3623intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3624 struct intel_connector *intel_connector)
a4fc5ed6 3625{
f0fec3f2
PZ		 3626 struct drm_connector *connector = &intel_connector->base;
3627 struct intel_dp *intel_dp = &intel_dig_port->dp;
3628 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3629 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3630 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3631 enum port port = intel_dig_port->port;
5eb08b69 3632 const char *name = NULL;
b2a14755 3633 int type, error;
a4fc5ed6 3634
0767935e
DV		 3635 /* Preserve the current hw state. */
3636 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3637 intel_dp->attached_connector = intel_connector;
3d3dc149 3638
3b32a35b 3639 if (intel_dp_is_edp(dev, port))
b329530c 3640 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 3641 else
3642 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 3643
f7d24902
ID		 3644 /*
3645 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3646 * for DP the encoder type can be set by the caller to
3647 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3648 */
3649 if (type == DRM_MODE_CONNECTOR_eDP)
3650 intel_encoder->type = INTEL_OUTPUT_EDP;
3651
e7281eab
ID		 3652 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3653 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3654 port_name(port));
3655
b329530c 3656 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3657 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3658
a4fc5ed6
KP		 3659 connector->interlace_allowed = true;
3660 connector->doublescan_allowed = 0;
3661
f0fec3f2
PZ		 3662 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3663 ironlake_panel_vdd_work);
a4fc5ed6 3664
df0e9248 3665 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3666 drm_sysfs_connector_add(connector);
3667
affa9354 3668 if (HAS_DDI(dev))
bcbc889b
PZ		 3669 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3670 else
3671 intel_connector->get_hw_state = intel_connector_get_hw_state;
3672
9ed35ab1
PZ		 3673 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3674 if (HAS_DDI(dev)) {
3675 switch (intel_dig_port->port) {
3676 case PORT_A:
3677 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3678 break;
3679 case PORT_B:
3680 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3681 break;
3682 case PORT_C:
3683 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3684 break;
3685 case PORT_D:
3686 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3687 break;
3688 default:
3689 BUG();
3690 }
3691 }
e8cb4558 3692
a4fc5ed6 3693 /* Set up the DDC bus. */
ab9d7c30
PZ		 3694 switch (port) {
3695 case PORT_A:
1d843f9d 3696 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3697 name = "DPDDC-A";
3698 break;
3699 case PORT_B:
1d843f9d 3700 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3701 name = "DPDDC-B";
3702 break;
3703 case PORT_C:
1d843f9d 3704 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3705 name = "DPDDC-C";
3706 break;
3707 case PORT_D:
1d843f9d 3708 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3709 name = "DPDDC-D";
3710 break;
3711 default:
ad1c0b19 3712 BUG();
5eb08b69
ZW		 3713 }
3714
b2a14755
PZ		 3715 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3716 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3717 error, port_name(port));
c1f05264 3718
2b28bb1b
RV		 3719 intel_dp->psr_setup_done = false;
3720
b2f246a8 3721 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
15b1d171
PZ		 3722 i2c_del_adapter(&intel_dp->adapter);
3723 if (is_edp(intel_dp)) {
3724 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3725 mutex_lock(&dev->mode_config.mutex);
3726 ironlake_panel_vdd_off_sync(intel_dp);
3727 mutex_unlock(&dev->mode_config.mutex);
3728 }
b2f246a8
PZ		 3729 drm_sysfs_connector_remove(connector);
3730 drm_connector_cleanup(connector);
16c25533 3731 return false;
b2f246a8 3732 }
32f9d658 3733
f684960e
CW		 3734 intel_dp_add_properties(intel_dp, connector);
3735
a4fc5ed6
KP		 3736 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3737 * 0xd. Failure to do so will result in spurious interrupts being
3738 * generated on the port when a cable is not attached.
3739 */
3740 if (IS_G4X(dev) && !IS_GM45(dev)) {
3741 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3742 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3743 }
16c25533
PZ		 3744
3745 return true;
a4fc5ed6 3746}
f0fec3f2
PZ		 3747
3748void
3749intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3750{
3751 struct intel_digital_port *intel_dig_port;
3752 struct intel_encoder *intel_encoder;
3753 struct drm_encoder *encoder;
3754 struct intel_connector *intel_connector;
3755
b14c5679 3756 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 3757 if (!intel_dig_port)
3758 return;
3759
b14c5679 3760 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 3761 if (!intel_connector) {
3762 kfree(intel_dig_port);
3763 return;
3764 }
3765
3766 intel_encoder = &intel_dig_port->base;
3767 encoder = &intel_encoder->base;
3768
3769 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3770 DRM_MODE_ENCODER_TMDS);
3771
5bfe2ac0 3772 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 3773 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70
PZ		 3774 intel_encoder->disable = intel_disable_dp;
3775 intel_encoder->post_disable = intel_post_disable_dp;
3776 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3777 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 3778 if (IS_VALLEYVIEW(dev)) {
ecff4f3b 3779 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 3780 intel_encoder->pre_enable = vlv_pre_enable_dp;
3781 intel_encoder->enable = vlv_enable_dp;
3782 } else {
ecff4f3b
JN		 3783 intel_encoder->pre_enable = g4x_pre_enable_dp;
3784 intel_encoder->enable = g4x_enable_dp;
ab1f90f9 3785 }
f0fec3f2 3786
174edf1f 3787 intel_dig_port->port = port;
f0fec3f2
PZ		 3788 intel_dig_port->dp.output_reg = output_reg;
3789
00c09d70 3790 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 3791 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3792 intel_encoder->cloneable = false;
3793 intel_encoder->hot_plug = intel_dp_hot_plug;
3794
15b1d171
PZ		 3795 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3796 drm_encoder_cleanup(encoder);
3797 kfree(intel_dig_port);
b2f246a8 3798 kfree(intel_connector);
15b1d171 3799 }
f0fec3f2 3800}
Linux kernel - Deliverables
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