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drm/i915: Move the conditional seqno query into the tracepoint
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 5, .m2 = 3 } },
63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
cfcb0fc9
JB		 67/**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74static bool is_edp(struct intel_dp *intel_dp)
75{
da63a9f2
PZ		 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 79}
80
68b4d824 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 82{
68b4d824
ID		 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 86}
87
df0e9248
CW		 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89{
fa90ecef 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 91}
92
ea5b213a 93static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 94
a4fc5ed6 95static int
ea5b213a 96intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 97{
7183dc29 98 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 99
100 switch (max_link_bw) {
101 case DP_LINK_BW_1_62:
102 case DP_LINK_BW_2_7:
103 break;
d4eead50
ID		 104 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
105 max_link_bw = DP_LINK_BW_2_7;
106 break;
a4fc5ed6 107 default:
d4eead50
ID		 108 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
109 max_link_bw);
a4fc5ed6
KP		 110 max_link_bw = DP_LINK_BW_1_62;
111 break;
112 }
113 return max_link_bw;
114}
115
cd9dde44
AJ		 116/*
117 * The units on the numbers in the next two are... bizarre. Examples will
118 * make it clearer; this one parallels an example in the eDP spec.
119 *
120 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
121 *
122 * 270000 * 1 * 8 / 10 == 216000
123 *
124 * The actual data capacity of that configuration is 2.16Gbit/s, so the
125 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
126 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
127 * 119000. At 18bpp that's 2142000 kilobits per second.
128 *
129 * Thus the strange-looking division by 10 in intel_dp_link_required, to
130 * get the result in decakilobits instead of kilobits.
131 */
132
a4fc5ed6 133static int
c898261c 134intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 135{
cd9dde44 136 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 137}
138
fe27d53e
DA		 139static int
140intel_dp_max_data_rate(int max_link_clock, int max_lanes)
141{
142 return (max_link_clock * max_lanes * 8) / 10;
143}
144
a4fc5ed6
KP		 145static int
146intel_dp_mode_valid(struct drm_connector *connector,
147 struct drm_display_mode *mode)
148{
df0e9248 149 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 150 struct intel_connector *intel_connector = to_intel_connector(connector);
151 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 152 int target_clock = mode->clock;
153 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 154
dd06f90e
JN		 155 if (is_edp(intel_dp) && fixed_mode) {
156 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 157 return MODE_PANEL;
158
dd06f90e 159 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 160 return MODE_PANEL;
03afc4a2
DV		 161
162 target_clock = fixed_mode->clock;
7de56f43
ZY		 163 }
164
36008365
DV		 165 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
166 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
167
168 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
169 mode_rate = intel_dp_link_required(target_clock, 18);
170
171 if (mode_rate > max_rate)
c4867936 172 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 173
174 if (mode->clock < 10000)
175 return MODE_CLOCK_LOW;
176
0af78a2b
DV		 177 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
178 return MODE_H_ILLEGAL;
179
a4fc5ed6
KP		 180 return MODE_OK;
181}
182
183static uint32_t
184pack_aux(uint8_t *src, int src_bytes)
185{
186 int i;
187 uint32_t v = 0;
188
189 if (src_bytes > 4)
190 src_bytes = 4;
191 for (i = 0; i < src_bytes; i++)
192 v |= ((uint32_t) src[i]) << ((3-i) * 8);
193 return v;
194}
195
196static void
197unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
198{
199 int i;
200 if (dst_bytes > 4)
201 dst_bytes = 4;
202 for (i = 0; i < dst_bytes; i++)
203 dst[i] = src >> ((3-i) * 8);
204}
205
fb0f8fbf
KP		 206/* hrawclock is 1/4 the FSB frequency */
207static int
208intel_hrawclk(struct drm_device *dev)
209{
210 struct drm_i915_private *dev_priv = dev->dev_private;
211 uint32_t clkcfg;
212
9473c8f4
VP		 213 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
214 if (IS_VALLEYVIEW(dev))
215 return 200;
216
fb0f8fbf
KP		 217 clkcfg = I915_READ(CLKCFG);
218 switch (clkcfg & CLKCFG_FSB_MASK) {
219 case CLKCFG_FSB_400:
220 return 100;
221 case CLKCFG_FSB_533:
222 return 133;
223 case CLKCFG_FSB_667:
224 return 166;
225 case CLKCFG_FSB_800:
226 return 200;
227 case CLKCFG_FSB_1067:
228 return 266;
229 case CLKCFG_FSB_1333:
230 return 333;
231 /* these two are just a guess; one of them might be right */
232 case CLKCFG_FSB_1600:
233 case CLKCFG_FSB_1600_ALT:
234 return 400;
235 default:
236 return 133;
237 }
238}
239
bf13e81b
JN		 240static void
241intel_dp_init_panel_power_sequencer(struct drm_device *dev,
242 struct intel_dp *intel_dp,
243 struct edp_power_seq *out);
244static void
245intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
246 struct intel_dp *intel_dp,
247 struct edp_power_seq *out);
248
249static enum pipe
250vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
251{
252 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
253 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
254 struct drm_device *dev = intel_dig_port->base.base.dev;
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 enum port port = intel_dig_port->port;
257 enum pipe pipe;
258
259 /* modeset should have pipe */
260 if (crtc)
261 return to_intel_crtc(crtc)->pipe;
262
263 /* init time, try to find a pipe with this port selected */
264 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
265 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
266 PANEL_PORT_SELECT_MASK;
267 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
268 return pipe;
269 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
270 return pipe;
271 }
272
273 /* shrug */
274 return PIPE_A;
275}
276
277static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
278{
279 struct drm_device *dev = intel_dp_to_dev(intel_dp);
280
281 if (HAS_PCH_SPLIT(dev))
282 return PCH_PP_CONTROL;
283 else
284 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
285}
286
287static u32 _pp_stat_reg(struct intel_dp *intel_dp)
288{
289 struct drm_device *dev = intel_dp_to_dev(intel_dp);
290
291 if (HAS_PCH_SPLIT(dev))
292 return PCH_PP_STATUS;
293 else
294 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
295}
296
ebf33b18
KP		 297static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
298{
30add22d 299 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 300 struct drm_i915_private *dev_priv = dev->dev_private;
301
bf13e81b 302 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 303}
304
305static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
306{
30add22d 307 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 308 struct drm_i915_private *dev_priv = dev->dev_private;
309
bf13e81b 310 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 311}
312
9b984dae
KP		 313static void
314intel_dp_check_edp(struct intel_dp *intel_dp)
315{
30add22d 316 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 317 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 318
9b984dae
KP		 319 if (!is_edp(intel_dp))
320 return;
453c5420 321
ebf33b18 322 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 323 WARN(1, "eDP powered off while attempting aux channel communication.\n");
324 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 325 I915_READ(_pp_stat_reg(intel_dp)),
326 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 327 }
328}
329
9ee32fea
DV		 330static uint32_t
331intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
332{
333 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
334 struct drm_device *dev = intel_dig_port->base.base.dev;
335 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 336 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 337 uint32_t status;
338 bool done;
339
ef04f00d 340#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 341 if (has_aux_irq)
b18ac466 342 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 343 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 344 else
345 done = wait_for_atomic(C, 10) == 0;
346 if (!done)
347 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
348 has_aux_irq);
349#undef C
350
351 return status;
352}
353
bc86625a
CW		 354static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
355 int index)
a4fc5ed6 356{
174edf1f
PZ		 357 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
358 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 359 struct drm_i915_private *dev_priv = dev->dev_private;
9ee32fea 360
a4fc5ed6 361 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 362 * and would like to run at 2MHz. So, take the
363 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 364 *
365 * Note that PCH attached eDP panels should use a 125MHz input
366 * clock divider.
a4fc5ed6 367 */
a62d0834 368 if (IS_VALLEYVIEW(dev)) {
bc86625a 369 return index ? 0 : 100;
a62d0834 370 } else if (intel_dig_port->port == PORT_A) {
bc86625a
CW		 371 if (index)
372 return 0;
affa9354 373 if (HAS_DDI(dev))
bc86625a 374 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
9473c8f4 375 else if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 376 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 377 else
b84a1cf8 378 return 225; /* eDP input clock at 450Mhz */
2c55c336
JN		 379 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
380 /* Workaround for non-ULT HSW */
bc86625a
CW		 381 switch (index) {
382 case 0: return 63;
383 case 1: return 72;
384 default: return 0;
385 }
2c55c336 386 } else if (HAS_PCH_SPLIT(dev)) {
bc86625a 387 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 388 } else {
bc86625a 389 return index ? 0 :intel_hrawclk(dev) / 2;
2c55c336 390 }
b84a1cf8
RV		 391}
392
393static int
394intel_dp_aux_ch(struct intel_dp *intel_dp,
395 uint8_t *send, int send_bytes,
396 uint8_t *recv, int recv_size)
397{
398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
399 struct drm_device *dev = intel_dig_port->base.base.dev;
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
402 uint32_t ch_data = ch_ctl + 4;
bc86625a 403 uint32_t aux_clock_divider;
b84a1cf8
RV		 404 int i, ret, recv_bytes;
405 uint32_t status;
bc86625a 406 int try, precharge, clock = 0;
b84a1cf8
RV		 407 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
408
409 /* dp aux is extremely sensitive to irq latency, hence request the
410 * lowest possible wakeup latency and so prevent the cpu from going into
411 * deep sleep states.
412 */
413 pm_qos_update_request(&dev_priv->pm_qos, 0);
414
415 intel_dp_check_edp(intel_dp);
5eb08b69 416
6b4e0a93
DV		 417 if (IS_GEN6(dev))
418 precharge = 3;
419 else
420 precharge = 5;
421
c67a470b
PZ		 422 intel_aux_display_runtime_get(dev_priv);
423
11bee43e
JB		 424 /* Try to wait for any previous AUX channel activity */
425 for (try = 0; try < 3; try++) {
ef04f00d 426 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 427 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
428 break;
429 msleep(1);
430 }
431
432 if (try == 3) {
433 WARN(1, "dp_aux_ch not started status 0x%08x\n",
434 I915_READ(ch_ctl));
9ee32fea
DV		 435 ret = -EBUSY;
436 goto out;
4f7f7b7e
CW		 437 }
438
46a5ae9f
PZ		 439 /* Only 5 data registers! */
440 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
441 ret = -E2BIG;
442 goto out;
443 }
444
bc86625a
CW		 445 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
446 /* Must try at least 3 times according to DP spec */
447 for (try = 0; try < 5; try++) {
448 /* Load the send data into the aux channel data registers */
449 for (i = 0; i < send_bytes; i += 4)
450 I915_WRITE(ch_data + i,
451 pack_aux(send + i, send_bytes - i));
452
453 /* Send the command and wait for it to complete */
454 I915_WRITE(ch_ctl,
455 DP_AUX_CH_CTL_SEND_BUSY |
456 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
457 DP_AUX_CH_CTL_TIME_OUT_400us |
458 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
459 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
460 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
461 DP_AUX_CH_CTL_DONE |
462 DP_AUX_CH_CTL_TIME_OUT_ERROR |
463 DP_AUX_CH_CTL_RECEIVE_ERROR);
464
465 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
466
467 /* Clear done status and any errors */
468 I915_WRITE(ch_ctl,
469 status |
470 DP_AUX_CH_CTL_DONE |
471 DP_AUX_CH_CTL_TIME_OUT_ERROR |
472 DP_AUX_CH_CTL_RECEIVE_ERROR);
473
474 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
475 DP_AUX_CH_CTL_RECEIVE_ERROR))
476 continue;
477 if (status & DP_AUX_CH_CTL_DONE)
478 break;
479 }
4f7f7b7e 480 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 481 break;
482 }
483
a4fc5ed6 484 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 485 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 486 ret = -EBUSY;
487 goto out;
a4fc5ed6
KP		 488 }
489
490 /* Check for timeout or receive error.
491 * Timeouts occur when the sink is not connected
492 */
a5b3da54 493 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 494 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 495 ret = -EIO;
496 goto out;
a5b3da54 497 }
1ae8c0a5
KP		 498
499 /* Timeouts occur when the device isn't connected, so they're
500 * "normal" -- don't fill the kernel log with these */
a5b3da54 501 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 502 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 503 ret = -ETIMEDOUT;
504 goto out;
a4fc5ed6
KP		 505 }
506
507 /* Unload any bytes sent back from the other side */
508 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
509 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 510 if (recv_bytes > recv_size)
511 recv_bytes = recv_size;
0206e353 512
4f7f7b7e
CW		 513 for (i = 0; i < recv_bytes; i += 4)
514 unpack_aux(I915_READ(ch_data + i),
515 recv + i, recv_bytes - i);
a4fc5ed6 516
9ee32fea
DV		 517 ret = recv_bytes;
518out:
519 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 520 intel_aux_display_runtime_put(dev_priv);
9ee32fea
DV		 521
522 return ret;
a4fc5ed6
KP		 523}
524
525/* Write data to the aux channel in native mode */
526static int
ea5b213a 527intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 528 uint16_t address, uint8_t *send, int send_bytes)
529{
530 int ret;
531 uint8_t msg[20];
532 int msg_bytes;
533 uint8_t ack;
534
46a5ae9f
PZ		 535 if (WARN_ON(send_bytes > 16))
536 return -E2BIG;
537
9b984dae 538 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 539 msg[0] = AUX_NATIVE_WRITE << 4;
540 msg[1] = address >> 8;
eebc863e 541 msg[2] = address & 0xff;
a4fc5ed6
KP		 542 msg[3] = send_bytes - 1;
543 memcpy(&msg[4], send, send_bytes);
544 msg_bytes = send_bytes + 4;
545 for (;;) {
ea5b213a 546 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 547 if (ret < 0)
548 return ret;
549 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
550 break;
551 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
552 udelay(100);
553 else
a5b3da54 554 return -EIO;
a4fc5ed6
KP		 555 }
556 return send_bytes;
557}
558
559/* Write a single byte to the aux channel in native mode */
560static int
ea5b213a 561intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 562 uint16_t address, uint8_t byte)
563{
ea5b213a 564 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 565}
566
567/* read bytes from a native aux channel */
568static int
ea5b213a 569intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 570 uint16_t address, uint8_t *recv, int recv_bytes)
571{
572 uint8_t msg[4];
573 int msg_bytes;
574 uint8_t reply[20];
575 int reply_bytes;
576 uint8_t ack;
577 int ret;
578
46a5ae9f
PZ		 579 if (WARN_ON(recv_bytes > 19))
580 return -E2BIG;
581
9b984dae 582 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 583 msg[0] = AUX_NATIVE_READ << 4;
584 msg[1] = address >> 8;
585 msg[2] = address & 0xff;
586 msg[3] = recv_bytes - 1;
587
588 msg_bytes = 4;
589 reply_bytes = recv_bytes + 1;
590
591 for (;;) {
ea5b213a 592 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 593 reply, reply_bytes);
a5b3da54
KP		 594 if (ret == 0)
595 return -EPROTO;
596 if (ret < 0)
a4fc5ed6
KP		 597 return ret;
598 ack = reply[0];
599 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
600 memcpy(recv, reply + 1, ret - 1);
601 return ret - 1;
602 }
603 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
604 udelay(100);
605 else
a5b3da54 606 return -EIO;
a4fc5ed6
KP		 607 }
608}
609
610static int
ab2c0672
DA		 611intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
612 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 613{
ab2c0672 614 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 615 struct intel_dp *intel_dp = container_of(adapter,
616 struct intel_dp,
617 adapter);
ab2c0672
DA		 618 uint16_t address = algo_data->address;
619 uint8_t msg[5];
620 uint8_t reply[2];
8316f337 621 unsigned retry;
ab2c0672
DA		 622 int msg_bytes;
623 int reply_bytes;
624 int ret;
625
9b984dae 626 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 627 /* Set up the command byte */
628 if (mode & MODE_I2C_READ)
629 msg[0] = AUX_I2C_READ << 4;
630 else
631 msg[0] = AUX_I2C_WRITE << 4;
632
633 if (!(mode & MODE_I2C_STOP))
634 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 635
ab2c0672
DA		 636 msg[1] = address >> 8;
637 msg[2] = address;
638
639 switch (mode) {
640 case MODE_I2C_WRITE:
641 msg[3] = 0;
642 msg[4] = write_byte;
643 msg_bytes = 5;
644 reply_bytes = 1;
645 break;
646 case MODE_I2C_READ:
647 msg[3] = 0;
648 msg_bytes = 4;
649 reply_bytes = 2;
650 break;
651 default:
652 msg_bytes = 3;
653 reply_bytes = 1;
654 break;
655 }
656
8316f337
DF		 657 for (retry = 0; retry < 5; retry++) {
658 ret = intel_dp_aux_ch(intel_dp,
659 msg, msg_bytes,
660 reply, reply_bytes);
ab2c0672 661 if (ret < 0) {
3ff99164 662 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 663 return ret;
664 }
8316f337
DF		 665
666 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
667 case AUX_NATIVE_REPLY_ACK:
668 /* I2C-over-AUX Reply field is only valid
669 * when paired with AUX ACK.
670 */
671 break;
672 case AUX_NATIVE_REPLY_NACK:
673 DRM_DEBUG_KMS("aux_ch native nack\n");
674 return -EREMOTEIO;
675 case AUX_NATIVE_REPLY_DEFER:
8d16f258
JN		 676 /*
677 * For now, just give more slack to branch devices. We
678 * could check the DPCD for I2C bit rate capabilities,
679 * and if available, adjust the interval. We could also
680 * be more careful with DP-to-Legacy adapters where a
681 * long legacy cable may force very low I2C bit rates.
682 */
683 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
684 DP_DWN_STRM_PORT_PRESENT)
685 usleep_range(500, 600);
686 else
687 usleep_range(300, 400);
8316f337
DF		 688 continue;
689 default:
690 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
691 reply[0]);
692 return -EREMOTEIO;
693 }
694
ab2c0672
DA		 695 switch (reply[0] & AUX_I2C_REPLY_MASK) {
696 case AUX_I2C_REPLY_ACK:
697 if (mode == MODE_I2C_READ) {
698 *read_byte = reply[1];
699 }
700 return reply_bytes - 1;
701 case AUX_I2C_REPLY_NACK:
8316f337 702 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 703 return -EREMOTEIO;
704 case AUX_I2C_REPLY_DEFER:
8316f337 705 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 706 udelay(100);
707 break;
708 default:
8316f337 709 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 710 return -EREMOTEIO;
711 }
712 }
8316f337
DF		 713
714 DRM_ERROR("too many retries, giving up\n");
715 return -EREMOTEIO;
a4fc5ed6
KP		 716}
717
718static int
ea5b213a 719intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 720 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 721{
0b5c541b
KP		 722 int ret;
723
d54e9d28 724 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 725 intel_dp->algo.running = false;
726 intel_dp->algo.address = 0;
727 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
728
0206e353 729 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 730 intel_dp->adapter.owner = THIS_MODULE;
731 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 732 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 733 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
734 intel_dp->adapter.algo_data = &intel_dp->algo;
735 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
736
0b5c541b
KP		 737 ironlake_edp_panel_vdd_on(intel_dp);
738 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 739 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 740 return ret;
a4fc5ed6
KP		 741}
742
c6bb3538
DV		 743static void
744intel_dp_set_clock(struct intel_encoder *encoder,
745 struct intel_crtc_config *pipe_config, int link_bw)
746{
747 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 748 const struct dp_link_dpll *divisor = NULL;
749 int i, count = 0;
c6bb3538
DV		 750
751 if (IS_G4X(dev)) {
9dd4ffdf
CML		 752 divisor = gen4_dpll;
753 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 754 } else if (IS_HASWELL(dev)) {
755 /* Haswell has special-purpose DP DDI clocks. */
756 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 757 divisor = pch_dpll;
758 count = ARRAY_SIZE(pch_dpll);
c6bb3538 759 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 760 divisor = vlv_dpll;
761 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 762 }
9dd4ffdf
CML		 763
764 if (divisor && count) {
765 for (i = 0; i < count; i++) {
766 if (link_bw == divisor[i].link_bw) {
767 pipe_config->dpll = divisor[i].dpll;
768 pipe_config->clock_set = true;
769 break;
770 }
771 }
c6bb3538
DV		 772 }
773}
774
00c09d70 775bool
5bfe2ac0
DV		 776intel_dp_compute_config(struct intel_encoder *encoder,
777 struct intel_crtc_config *pipe_config)
a4fc5ed6 778{
5bfe2ac0 779 struct drm_device *dev = encoder->base.dev;
36008365 780 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 781 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 782 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 783 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 784 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 785 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 786 int lane_count, clock;
397fe157 787 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 788 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 789 int bpp, mode_rate;
a4fc5ed6 790 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
ff9a6750 791 int link_avail, link_clock;
a4fc5ed6 792
bc7d38a4 793 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 794 pipe_config->has_pch_encoder = true;
795
03afc4a2 796 pipe_config->has_dp_encoder = true;
a4fc5ed6 797
dd06f90e
JN		 798 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
799 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
800 adjusted_mode);
2dd24552
JB		 801 if (!HAS_PCH_SPLIT(dev))
802 intel_gmch_panel_fitting(intel_crtc, pipe_config,
803 intel_connector->panel.fitting_mode);
804 else
b074cec8
JB		 805 intel_pch_panel_fitting(intel_crtc, pipe_config,
806 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 807 }
808
cb1793ce 809 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 810 return false;
811
083f9560
DV		 812 DRM_DEBUG_KMS("DP link computation with max lane count %i "
813 "max bw %02x pixel clock %iKHz\n",
71244653 814 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 815
36008365
DV		 816 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
817 * bpc in between. */
3e7ca985 818 bpp = pipe_config->pipe_bpp;
7984211e
ID		 819 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) {
820 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
821 dev_priv->vbt.edp_bpp);
e1b73cba 822 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
7984211e 823 }
657445fe 824
36008365 825 for (; bpp >= 6*3; bpp -= 2*3) {
ff9a6750 826 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
36008365
DV		 827
828 for (clock = 0; clock <= max_clock; clock++) {
829 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
830 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
831 link_avail = intel_dp_max_data_rate(link_clock,
832 lane_count);
833
834 if (mode_rate <= link_avail) {
835 goto found;
836 }
837 }
838 }
839 }
c4867936 840
36008365 841 return false;
3685a8f3 842
36008365 843found:
55bc60db
VS		 844 if (intel_dp->color_range_auto) {
845 /*
846 * See:
847 * CEA-861-E - 5.1 Default Encoding Parameters
848 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
849 */
18316c8c 850 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 851 intel_dp->color_range = DP_COLOR_RANGE_16_235;
852 else
853 intel_dp->color_range = 0;
854 }
855
3685a8f3 856 if (intel_dp->color_range)
50f3b016 857 pipe_config->limited_color_range = true;
a4fc5ed6 858
36008365
DV		 859 intel_dp->link_bw = bws[clock];
860 intel_dp->lane_count = lane_count;
657445fe 861 pipe_config->pipe_bpp = bpp;
ff9a6750 862 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 863
36008365
DV		 864 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
865 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 866 pipe_config->port_clock, bpp);
36008365
DV		 867 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
868 mode_rate, link_avail);
a4fc5ed6 869
03afc4a2 870 intel_link_compute_m_n(bpp, lane_count,
ff9a6750 871 adjusted_mode->clock, pipe_config->port_clock,
03afc4a2 872 &pipe_config->dp_m_n);
9d1a455b 873
c6bb3538
DV		 874 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
875
03afc4a2 876 return true;
a4fc5ed6
KP		 877}
878
247d89f6
PZ		 879void intel_dp_init_link_config(struct intel_dp *intel_dp)
880{
881 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
882 intel_dp->link_configuration[0] = intel_dp->link_bw;
883 intel_dp->link_configuration[1] = intel_dp->lane_count;
884 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
885 /*
886 * Check for DPCD version > 1.1 and enhanced framing support
887 */
888 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
889 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
890 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
891 }
892}
893
7c62a164 894static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 895{
7c62a164
DV		 896 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
897 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
898 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 899 struct drm_i915_private *dev_priv = dev->dev_private;
900 u32 dpa_ctl;
901
ff9a6750 902 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 903 dpa_ctl = I915_READ(DP_A);
904 dpa_ctl &= ~DP_PLL_FREQ_MASK;
905
ff9a6750 906 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 907 /* For a long time we've carried around a ILK-DevA w/a for the
908 * 160MHz clock. If we're really unlucky, it's still required.
909 */
910 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 911 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 912 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 913 } else {
914 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 915 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 916 }
1ce17038 917
ea9b6006
DV		 918 I915_WRITE(DP_A, dpa_ctl);
919
920 POSTING_READ(DP_A);
921 udelay(500);
922}
923
b934223d 924static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 925{
b934223d 926 struct drm_device *dev = encoder->base.dev;
417e822d 927 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 928 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 929 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 930 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
931 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 932
417e822d 933 /*
1a2eb460 934 * There are four kinds of DP registers:
417e822d
KP		 935 *
936 * IBX PCH
1a2eb460
KP		 937 * SNB CPU
938 * IVB CPU
417e822d
KP		 939 * CPT PCH
940 *
941 * IBX PCH and CPU are the same for almost everything,
942 * except that the CPU DP PLL is configured in this
943 * register
944 *
945 * CPT PCH is quite different, having many bits moved
946 * to the TRANS_DP_CTL register instead. That
947 * configuration happens (oddly) in ironlake_pch_enable
948 */
9c9e7927 949
417e822d
KP		 950 /* Preserve the BIOS-computed detected bit. This is
951 * supposed to be read-only.
952 */
953 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 954
417e822d 955 /* Handle DP bits in common between all three register formats */
417e822d 956 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 957 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 958
e0dac65e
WF		 959 if (intel_dp->has_audio) {
960 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 961 pipe_name(crtc->pipe));
ea5b213a 962 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 963 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 964 }
247d89f6
PZ		 965
966 intel_dp_init_link_config(intel_dp);
a4fc5ed6 967
417e822d 968 /* Split out the IBX/CPU vs CPT settings */
32f9d658 969
bc7d38a4 970 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 971 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
972 intel_dp->DP |= DP_SYNC_HS_HIGH;
973 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
974 intel_dp->DP |= DP_SYNC_VS_HIGH;
975 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
976
977 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
978 intel_dp->DP |= DP_ENHANCED_FRAMING;
979
7c62a164 980 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 981 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 982 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 983 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 984
985 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
986 intel_dp->DP |= DP_SYNC_HS_HIGH;
987 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
988 intel_dp->DP |= DP_SYNC_VS_HIGH;
989 intel_dp->DP |= DP_LINK_TRAIN_OFF;
990
991 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
992 intel_dp->DP |= DP_ENHANCED_FRAMING;
993
7c62a164 994 if (crtc->pipe == 1)
417e822d 995 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 996 } else {
997 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 998 }
ea9b6006 999
bc7d38a4 1000 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 1001 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 1002}
1003
99ea7127
KP		 1004#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1005#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1006
1007#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1008#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1009
1010#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1011#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1012
1013static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1014 u32 mask,
1015 u32 value)
bd943159 1016{
30add22d 1017 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1018 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1019 u32 pp_stat_reg, pp_ctrl_reg;
1020
bf13e81b
JN		 1021 pp_stat_reg = _pp_stat_reg(intel_dp);
1022 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1023
99ea7127 1024 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1025 mask, value,
1026 I915_READ(pp_stat_reg),
1027 I915_READ(pp_ctrl_reg));
32ce697c 1028
453c5420 1029 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1030 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1031 I915_READ(pp_stat_reg),
1032 I915_READ(pp_ctrl_reg));
32ce697c 1033 }
99ea7127 1034}
32ce697c 1035
99ea7127
KP		 1036static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1037{
1038 DRM_DEBUG_KMS("Wait for panel power on\n");
1039 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1040}
1041
99ea7127
KP		 1042static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1043{
1044 DRM_DEBUG_KMS("Wait for panel power off time\n");
1045 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1046}
1047
1048static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1049{
1050 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1051 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1052}
1053
1054
832dd3c1
KP		 1055/* Read the current pp_control value, unlocking the register if it
1056 * is locked
1057 */
1058
453c5420 1059static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1060{
453c5420
JB		 1061 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1062 struct drm_i915_private *dev_priv = dev->dev_private;
1063 u32 control;
832dd3c1 1064
bf13e81b 1065 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1066 control &= ~PANEL_UNLOCK_MASK;
1067 control |= PANEL_UNLOCK_REGS;
1068 return control;
bd943159
KP		 1069}
1070
82a4d9c0 1071void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1072{
30add22d 1073 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1074 struct drm_i915_private *dev_priv = dev->dev_private;
1075 u32 pp;
453c5420 1076 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1077
97af61f5
KP		 1078 if (!is_edp(intel_dp))
1079 return;
f01eca2e 1080 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1081
bd943159
KP		 1082 WARN(intel_dp->want_panel_vdd,
1083 "eDP VDD already requested on\n");
1084
1085 intel_dp->want_panel_vdd = true;
99ea7127 1086
bd943159
KP		 1087 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1088 DRM_DEBUG_KMS("eDP VDD already on\n");
1089 return;
1090 }
1091
99ea7127
KP		 1092 if (!ironlake_edp_have_panel_power(intel_dp))
1093 ironlake_wait_panel_power_cycle(intel_dp);
1094
453c5420 1095 pp = ironlake_get_pp_control(intel_dp);
5d613501 1096 pp |= EDP_FORCE_VDD;
ebf33b18 1097
bf13e81b
JN		 1098 pp_stat_reg = _pp_stat_reg(intel_dp);
1099 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1100
1101 I915_WRITE(pp_ctrl_reg, pp);
1102 POSTING_READ(pp_ctrl_reg);
1103 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1104 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1105 /*
1106 * If the panel wasn't on, delay before accessing aux channel
1107 */
1108 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1109 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1110 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1111 }
5d613501
JB		 1112}
1113
bd943159 1114static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1115{
30add22d 1116 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1117 struct drm_i915_private *dev_priv = dev->dev_private;
1118 u32 pp;
453c5420 1119 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1120
a0e99e68
DV		 1121 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1122
bd943159 1123 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
453c5420 1124 pp = ironlake_get_pp_control(intel_dp);
bd943159 1125 pp &= ~EDP_FORCE_VDD;
bd943159 1126
bf13e81b
JN		 1127 pp_stat_reg = _pp_ctrl_reg(intel_dp);
1128 pp_ctrl_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1129
1130 I915_WRITE(pp_ctrl_reg, pp);
1131 POSTING_READ(pp_ctrl_reg);
99ea7127 1132
453c5420
JB		 1133 /* Make sure sequencer is idle before allowing subsequent activity */
1134 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1135 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
99ea7127 1136 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1137 }
1138}
5d613501 1139
bd943159
KP		 1140static void ironlake_panel_vdd_work(struct work_struct *__work)
1141{
1142 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1143 struct intel_dp, panel_vdd_work);
30add22d 1144 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1145
627f7675 1146 mutex_lock(&dev->mode_config.mutex);
bd943159 1147 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1148 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1149}
1150
82a4d9c0 1151void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1152{
97af61f5
KP		 1153 if (!is_edp(intel_dp))
1154 return;
5d613501 1155
bd943159
KP		 1156 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1157 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1158
bd943159
KP		 1159 intel_dp->want_panel_vdd = false;
1160
1161 if (sync) {
1162 ironlake_panel_vdd_off_sync(intel_dp);
1163 } else {
1164 /*
1165 * Queue the timer to fire a long
1166 * time from now (relative to the power down delay)
1167 * to keep the panel power up across a sequence of operations
1168 */
1169 schedule_delayed_work(&intel_dp->panel_vdd_work,
1170 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1171 }
5d613501
JB		 1172}
1173
82a4d9c0 1174void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1175{
30add22d 1176 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1177 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1178 u32 pp;
453c5420 1179 u32 pp_ctrl_reg;
9934c132 1180
97af61f5 1181 if (!is_edp(intel_dp))
bd943159 1182 return;
99ea7127
KP		 1183
1184 DRM_DEBUG_KMS("Turn eDP power on\n");
1185
1186 if (ironlake_edp_have_panel_power(intel_dp)) {
1187 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1188 return;
99ea7127 1189 }
9934c132 1190
99ea7127 1191 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1192
bf13e81b 1193 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1194 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1195 if (IS_GEN5(dev)) {
1196 /* ILK workaround: disable reset around power sequence */
1197 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1198 I915_WRITE(pp_ctrl_reg, pp);
1199 POSTING_READ(pp_ctrl_reg);
05ce1a49 1200 }
37c6c9b0 1201
1c0ae80a 1202 pp |= POWER_TARGET_ON;
99ea7127
KP		 1203 if (!IS_GEN5(dev))
1204 pp |= PANEL_POWER_RESET;
1205
453c5420
JB		 1206 I915_WRITE(pp_ctrl_reg, pp);
1207 POSTING_READ(pp_ctrl_reg);
9934c132 1208
99ea7127 1209 ironlake_wait_panel_on(intel_dp);
9934c132 1210
05ce1a49
KP		 1211 if (IS_GEN5(dev)) {
1212 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1213 I915_WRITE(pp_ctrl_reg, pp);
1214 POSTING_READ(pp_ctrl_reg);
05ce1a49 1215 }
9934c132
JB		 1216}
1217
82a4d9c0 1218void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1219{
30add22d 1220 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1221 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1222 u32 pp;
453c5420 1223 u32 pp_ctrl_reg;
9934c132 1224
97af61f5
KP		 1225 if (!is_edp(intel_dp))
1226 return;
37c6c9b0 1227
99ea7127 1228 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1229
6cb49835 1230 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1231
453c5420 1232 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1233 /* We need to switch off panel power _and_ force vdd, for otherwise some
1234 * panels get very unhappy and cease to work. */
1235 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
453c5420 1236
bf13e81b 1237 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1238
1239 I915_WRITE(pp_ctrl_reg, pp);
1240 POSTING_READ(pp_ctrl_reg);
9934c132 1241
35a38556
DV		 1242 intel_dp->want_panel_vdd = false;
1243
99ea7127 1244 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1245}
1246
d6c50ff8 1247void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1248{
da63a9f2
PZ		 1249 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1250 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1251 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1252 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658 1253 u32 pp;
453c5420 1254 u32 pp_ctrl_reg;
32f9d658 1255
f01eca2e
KP		 1256 if (!is_edp(intel_dp))
1257 return;
1258
28c97730 1259 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1260 /*
1261 * If we enable the backlight right away following a panel power
1262 * on, we may see slight flicker as the panel syncs with the eDP
1263 * link. So delay a bit to make sure the image is solid before
1264 * allowing it to appear.
1265 */
f01eca2e 1266 msleep(intel_dp->backlight_on_delay);
453c5420 1267 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1268 pp |= EDP_BLC_ENABLE;
453c5420 1269
bf13e81b 1270 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1271
1272 I915_WRITE(pp_ctrl_reg, pp);
1273 POSTING_READ(pp_ctrl_reg);
035aa3de
DV		 1274
1275 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1276}
1277
d6c50ff8 1278void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1279{
30add22d 1280 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1281 struct drm_i915_private *dev_priv = dev->dev_private;
1282 u32 pp;
453c5420 1283 u32 pp_ctrl_reg;
32f9d658 1284
f01eca2e
KP		 1285 if (!is_edp(intel_dp))
1286 return;
1287
035aa3de
DV		 1288 intel_panel_disable_backlight(dev);
1289
28c97730 1290 DRM_DEBUG_KMS("\n");
453c5420 1291 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1292 pp &= ~EDP_BLC_ENABLE;
453c5420 1293
bf13e81b 1294 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1295
1296 I915_WRITE(pp_ctrl_reg, pp);
1297 POSTING_READ(pp_ctrl_reg);
f01eca2e 1298 msleep(intel_dp->backlight_off_delay);
32f9d658 1299}
a4fc5ed6 1300
2bd2ad64 1301static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1302{
da63a9f2
PZ		 1303 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1304 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1305 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1306 struct drm_i915_private *dev_priv = dev->dev_private;
1307 u32 dpa_ctl;
1308
2bd2ad64
DV		 1309 assert_pipe_disabled(dev_priv,
1310 to_intel_crtc(crtc)->pipe);
1311
d240f20f
JB		 1312 DRM_DEBUG_KMS("\n");
1313 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1314 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1315 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1316
1317 /* We don't adjust intel_dp->DP while tearing down the link, to
1318 * facilitate link retraining (e.g. after hotplug). Hence clear all
1319 * enable bits here to ensure that we don't enable too much. */
1320 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1321 intel_dp->DP |= DP_PLL_ENABLE;
1322 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1323 POSTING_READ(DP_A);
1324 udelay(200);
d240f20f
JB		 1325}
1326
2bd2ad64 1327static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1328{
da63a9f2
PZ		 1329 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1330 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1331 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1332 struct drm_i915_private *dev_priv = dev->dev_private;
1333 u32 dpa_ctl;
1334
2bd2ad64
DV		 1335 assert_pipe_disabled(dev_priv,
1336 to_intel_crtc(crtc)->pipe);
1337
d240f20f 1338 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1339 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1340 "dp pll off, should be on\n");
1341 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1342
1343 /* We can't rely on the value tracked for the DP register in
1344 * intel_dp->DP because link_down must not change that (otherwise link
1345 * re-training will fail. */
298b0b39 1346 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1347 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1348 POSTING_READ(DP_A);
d240f20f
JB		 1349 udelay(200);
1350}
1351
c7ad3810 1352/* If the sink supports it, try to set the power state appropriately */
c19b0669 1353void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1354{
1355 int ret, i;
1356
1357 /* Should have a valid DPCD by this point */
1358 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1359 return;
1360
1361 if (mode != DRM_MODE_DPMS_ON) {
1362 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1363 DP_SET_POWER_D3);
1364 if (ret != 1)
1365 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1366 } else {
1367 /*
1368 * When turning on, we need to retry for 1ms to give the sink
1369 * time to wake up.
1370 */
1371 for (i = 0; i < 3; i++) {
1372 ret = intel_dp_aux_native_write_1(intel_dp,
1373 DP_SET_POWER,
1374 DP_SET_POWER_D0);
1375 if (ret == 1)
1376 break;
1377 msleep(1);
1378 }
1379 }
1380}
1381
19d8fe15
DV		 1382static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1383 enum pipe *pipe)
d240f20f 1384{
19d8fe15 1385 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1386 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1387 struct drm_device *dev = encoder->base.dev;
1388 struct drm_i915_private *dev_priv = dev->dev_private;
1389 u32 tmp = I915_READ(intel_dp->output_reg);
1390
1391 if (!(tmp & DP_PORT_EN))
1392 return false;
1393
bc7d38a4 1394 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1395 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1396 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1397 *pipe = PORT_TO_PIPE(tmp);
1398 } else {
1399 u32 trans_sel;
1400 u32 trans_dp;
1401 int i;
1402
1403 switch (intel_dp->output_reg) {
1404 case PCH_DP_B:
1405 trans_sel = TRANS_DP_PORT_SEL_B;
1406 break;
1407 case PCH_DP_C:
1408 trans_sel = TRANS_DP_PORT_SEL_C;
1409 break;
1410 case PCH_DP_D:
1411 trans_sel = TRANS_DP_PORT_SEL_D;
1412 break;
1413 default:
1414 return true;
1415 }
1416
1417 for_each_pipe(i) {
1418 trans_dp = I915_READ(TRANS_DP_CTL(i));
1419 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1420 *pipe = i;
1421 return true;
1422 }
1423 }
19d8fe15 1424
4a0833ec
DV		 1425 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1426 intel_dp->output_reg);
1427 }
d240f20f 1428
19d8fe15
DV		 1429 return true;
1430}
d240f20f 1431
045ac3b5
JB		 1432static void intel_dp_get_config(struct intel_encoder *encoder,
1433 struct intel_crtc_config *pipe_config)
1434{
1435 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1436 u32 tmp, flags = 0;
63000ef6
XZ		 1437 struct drm_device *dev = encoder->base.dev;
1438 struct drm_i915_private *dev_priv = dev->dev_private;
1439 enum port port = dp_to_dig_port(intel_dp)->port;
1440 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1441 int dotclock;
045ac3b5 1442
63000ef6
XZ		 1443 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1444 tmp = I915_READ(intel_dp->output_reg);
1445 if (tmp & DP_SYNC_HS_HIGH)
1446 flags |= DRM_MODE_FLAG_PHSYNC;
1447 else
1448 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1449
63000ef6
XZ		 1450 if (tmp & DP_SYNC_VS_HIGH)
1451 flags |= DRM_MODE_FLAG_PVSYNC;
1452 else
1453 flags |= DRM_MODE_FLAG_NVSYNC;
1454 } else {
1455 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1456 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1457 flags |= DRM_MODE_FLAG_PHSYNC;
1458 else
1459 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1460
63000ef6
XZ		 1461 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1462 flags |= DRM_MODE_FLAG_PVSYNC;
1463 else
1464 flags |= DRM_MODE_FLAG_NVSYNC;
1465 }
045ac3b5
JB		 1466
1467 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1468
eb14cb74
VS		 1469 pipe_config->has_dp_encoder = true;
1470
1471 intel_dp_get_m_n(crtc, pipe_config);
1472
18442d08 1473 if (port == PORT_A) {
f1f644dc
JB		 1474 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1475 pipe_config->port_clock = 162000;
1476 else
1477 pipe_config->port_clock = 270000;
1478 }
18442d08
VS		 1479
1480 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1481 &pipe_config->dp_m_n);
1482
1483 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1484 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1485
1486 pipe_config->adjusted_mode.clock = dotclock;
045ac3b5
JB		 1487}
1488
2293bb5c
SK		 1489static bool is_edp_psr(struct intel_dp *intel_dp)
1490{
1491 return is_edp(intel_dp) &&
1492 intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1493}
1494
2b28bb1b
RV		 1495static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1496{
1497 struct drm_i915_private *dev_priv = dev->dev_private;
1498
18b5992c 1499 if (!HAS_PSR(dev))
2b28bb1b
RV		 1500 return false;
1501
18b5992c 1502 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1503}
1504
1505static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1506 struct edp_vsc_psr *vsc_psr)
1507{
1508 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1509 struct drm_device *dev = dig_port->base.base.dev;
1510 struct drm_i915_private *dev_priv = dev->dev_private;
1511 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1512 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1513 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1514 uint32_t *data = (uint32_t *) vsc_psr;
1515 unsigned int i;
1516
1517 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1518 the video DIP being updated before program video DIP data buffer
1519 registers for DIP being updated. */
1520 I915_WRITE(ctl_reg, 0);
1521 POSTING_READ(ctl_reg);
1522
1523 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1524 if (i < sizeof(struct edp_vsc_psr))
1525 I915_WRITE(data_reg + i, *data++);
1526 else
1527 I915_WRITE(data_reg + i, 0);
1528 }
1529
1530 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1531 POSTING_READ(ctl_reg);
1532}
1533
1534static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1535{
1536 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1537 struct drm_i915_private *dev_priv = dev->dev_private;
1538 struct edp_vsc_psr psr_vsc;
1539
1540 if (intel_dp->psr_setup_done)
1541 return;
1542
1543 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1544 memset(&psr_vsc, 0, sizeof(psr_vsc));
1545 psr_vsc.sdp_header.HB0 = 0;
1546 psr_vsc.sdp_header.HB1 = 0x7;
1547 psr_vsc.sdp_header.HB2 = 0x2;
1548 psr_vsc.sdp_header.HB3 = 0x8;
1549 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1550
1551 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1552 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
2b28bb1b
RV		 1553 EDP_PSR_DEBUG_MASK_HPD);
1554
1555 intel_dp->psr_setup_done = true;
1556}
1557
1558static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1559{
1560 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1561 struct drm_i915_private *dev_priv = dev->dev_private;
bc86625a 1562 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
2b28bb1b
RV		 1563 int precharge = 0x3;
1564 int msg_size = 5; /* Header(4) + Message(1) */
1565
1566 /* Enable PSR in sink */
1567 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1568 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1569 DP_PSR_ENABLE &
1570 ~DP_PSR_MAIN_LINK_ACTIVE);
1571 else
1572 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1573 DP_PSR_ENABLE |
1574 DP_PSR_MAIN_LINK_ACTIVE);
1575
1576 /* Setup AUX registers */
18b5992c
BW		 1577 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1578 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1579 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1580 DP_AUX_CH_CTL_TIME_OUT_400us |
1581 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1582 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1583 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1584}
1585
1586static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1587{
1588 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1589 struct drm_i915_private *dev_priv = dev->dev_private;
1590 uint32_t max_sleep_time = 0x1f;
1591 uint32_t idle_frames = 1;
1592 uint32_t val = 0x0;
1593
1594 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1595 val |= EDP_PSR_LINK_STANDBY;
1596 val |= EDP_PSR_TP2_TP3_TIME_0us;
1597 val |= EDP_PSR_TP1_TIME_0us;
1598 val |= EDP_PSR_SKIP_AUX_EXIT;
1599 } else
1600 val |= EDP_PSR_LINK_DISABLE;
1601
18b5992c 1602 I915_WRITE(EDP_PSR_CTL(dev), val |
2b28bb1b
RV		 1603 EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
1604 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1605 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1606 EDP_PSR_ENABLE);
1607}
1608
3f51e471
RV		 1609static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1610{
1611 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1612 struct drm_device *dev = dig_port->base.base.dev;
1613 struct drm_i915_private *dev_priv = dev->dev_private;
1614 struct drm_crtc *crtc = dig_port->base.base.crtc;
1615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1616 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1617 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1618
18b5992c 1619 if (!HAS_PSR(dev)) {
3f51e471
RV		 1620 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1621 dev_priv->no_psr_reason = PSR_NO_SOURCE;
1622 return false;
1623 }
1624
1625 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1626 (dig_port->port != PORT_A)) {
1627 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1628 dev_priv->no_psr_reason = PSR_HSW_NOT_DDIA;
1629 return false;
1630 }
1631
1632 if (!is_edp_psr(intel_dp)) {
1633 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1634 dev_priv->no_psr_reason = PSR_NO_SINK;
1635 return false;
1636 }
1637
105b7c11
RV		 1638 if (!i915_enable_psr) {
1639 DRM_DEBUG_KMS("PSR disable by flag\n");
1640 dev_priv->no_psr_reason = PSR_MODULE_PARAM;
1641 return false;
1642 }
1643
cd234b0b
CW		 1644 crtc = dig_port->base.base.crtc;
1645 if (crtc == NULL) {
1646 DRM_DEBUG_KMS("crtc not active for PSR\n");
1647 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1648 return false;
1649 }
1650
1651 intel_crtc = to_intel_crtc(crtc);
20ddf665 1652 if (!intel_crtc_active(crtc)) {
3f51e471
RV		 1653 DRM_DEBUG_KMS("crtc not active for PSR\n");
1654 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1655 return false;
1656 }
1657
cd234b0b 1658 obj = to_intel_framebuffer(crtc->fb)->obj;
3f51e471
RV		 1659 if (obj->tiling_mode != I915_TILING_X ||
1660 obj->fence_reg == I915_FENCE_REG_NONE) {
1661 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1662 dev_priv->no_psr_reason = PSR_NOT_TILED;
1663 return false;
1664 }
1665
1666 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1667 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1668 dev_priv->no_psr_reason = PSR_SPRITE_ENABLED;
1669 return false;
1670 }
1671
1672 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1673 S3D_ENABLE) {
1674 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1675 dev_priv->no_psr_reason = PSR_S3D_ENABLED;
1676 return false;
1677 }
1678
ca73b4f0 1679 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471
RV		 1680 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1681 dev_priv->no_psr_reason = PSR_INTERLACED_ENABLED;
1682 return false;
1683 }
1684
1685 return true;
1686}
1687
3d739d92 1688static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1689{
1690 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1691
3f51e471
RV		 1692 if (!intel_edp_psr_match_conditions(intel_dp) ||
1693 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1694 return;
1695
1696 /* Setup PSR once */
1697 intel_edp_psr_setup(intel_dp);
1698
1699 /* Enable PSR on the panel */
1700 intel_edp_psr_enable_sink(intel_dp);
1701
1702 /* Enable PSR on the host */
1703 intel_edp_psr_enable_source(intel_dp);
1704}
1705
3d739d92
RV		 1706void intel_edp_psr_enable(struct intel_dp *intel_dp)
1707{
1708 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1709
1710 if (intel_edp_psr_match_conditions(intel_dp) &&
1711 !intel_edp_is_psr_enabled(dev))
1712 intel_edp_psr_do_enable(intel_dp);
1713}
1714
2b28bb1b
RV		 1715void intel_edp_psr_disable(struct intel_dp *intel_dp)
1716{
1717 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1718 struct drm_i915_private *dev_priv = dev->dev_private;
1719
1720 if (!intel_edp_is_psr_enabled(dev))
1721 return;
1722
18b5992c
BW		 1723 I915_WRITE(EDP_PSR_CTL(dev),
1724 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1725
1726 /* Wait till PSR is idle */
18b5992c 1727 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1728 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1729 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1730}
1731
3d739d92
RV		 1732void intel_edp_psr_update(struct drm_device *dev)
1733{
1734 struct intel_encoder *encoder;
1735 struct intel_dp *intel_dp = NULL;
1736
1737 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1738 if (encoder->type == INTEL_OUTPUT_EDP) {
1739 intel_dp = enc_to_intel_dp(&encoder->base);
1740
1741 if (!is_edp_psr(intel_dp))
1742 return;
1743
1744 if (!intel_edp_psr_match_conditions(intel_dp))
1745 intel_edp_psr_disable(intel_dp);
1746 else
1747 if (!intel_edp_is_psr_enabled(dev))
1748 intel_edp_psr_do_enable(intel_dp);
1749 }
1750}
1751
e8cb4558 1752static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1753{
e8cb4558 1754 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1755 enum port port = dp_to_dig_port(intel_dp)->port;
1756 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1757
1758 /* Make sure the panel is off before trying to change the mode. But also
1759 * ensure that we have vdd while we switch off the panel. */
1760 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1761 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1762 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1763 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1764
1765 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1766 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1767 intel_dp_link_down(intel_dp);
d240f20f
JB		 1768}
1769
2bd2ad64 1770static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1771{
2bd2ad64 1772 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1773 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1774 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1775
982a3866 1776 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1777 intel_dp_link_down(intel_dp);
b2634017
JB		 1778 if (!IS_VALLEYVIEW(dev))
1779 ironlake_edp_pll_off(intel_dp);
3739850b 1780 }
2bd2ad64
DV		 1781}
1782
e8cb4558 1783static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1784{
e8cb4558
DV		 1785 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1786 struct drm_device *dev = encoder->base.dev;
1787 struct drm_i915_private *dev_priv = dev->dev_private;
1788 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1789
0c33d8d7
DV		 1790 if (WARN_ON(dp_reg & DP_PORT_EN))
1791 return;
5d613501 1792
97af61f5 1793 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1794 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1795 intel_dp_start_link_train(intel_dp);
97af61f5 1796 ironlake_edp_panel_on(intel_dp);
bd943159 1797 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1798 intel_dp_complete_link_train(intel_dp);
3ab9c637 1799 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1800}
89b667f8 1801
ecff4f3b
JN		 1802static void g4x_enable_dp(struct intel_encoder *encoder)
1803{
828f5c6e
JN		 1804 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1805
ecff4f3b 1806 intel_enable_dp(encoder);
f01eca2e 1807 ironlake_edp_backlight_on(intel_dp);
ab1f90f9 1808}
89b667f8 1809
ab1f90f9
JN		 1810static void vlv_enable_dp(struct intel_encoder *encoder)
1811{
828f5c6e
JN		 1812 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1813
1814 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1815}
1816
ecff4f3b 1817static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1818{
1819 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1820 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1821
1822 if (dport->port == PORT_A)
1823 ironlake_edp_pll_on(intel_dp);
1824}
1825
1826static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1827{
2bd2ad64 1828 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1829 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1830 struct drm_device *dev = encoder->base.dev;
89b667f8 1831 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9
JN		 1832 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1833 int port = vlv_dport_to_channel(dport);
1834 int pipe = intel_crtc->pipe;
bf13e81b 1835 struct edp_power_seq power_seq;
ab1f90f9 1836 u32 val;
a4fc5ed6 1837
ab1f90f9 1838 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1839
5e69f97f 1840 val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port));
ab1f90f9
JN		 1841 val = 0;
1842 if (pipe)
1843 val |= (1<<21);
1844 else
1845 val &= ~(1<<21);
1846 val |= 0x001000c4;
5e69f97f
CML		 1847 vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val);
1848 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
1849 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
89b667f8 1850
ab1f90f9
JN		 1851 mutex_unlock(&dev_priv->dpio_lock);
1852
bf13e81b
JN		 1853 /* init power sequencer on this pipe and port */
1854 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1855 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1856 &power_seq);
1857
ab1f90f9
JN		 1858 intel_enable_dp(encoder);
1859
1860 vlv_wait_port_ready(dev_priv, port);
89b667f8
JB		 1861}
1862
ecff4f3b 1863static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1864{
1865 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1866 struct drm_device *dev = encoder->base.dev;
1867 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1868 struct intel_crtc *intel_crtc =
1869 to_intel_crtc(encoder->base.crtc);
89b667f8 1870 int port = vlv_dport_to_channel(dport);
5e69f97f 1871 int pipe = intel_crtc->pipe;
89b667f8 1872
89b667f8 1873 /* Program Tx lane resets to default */
0980a60f 1874 mutex_lock(&dev_priv->dpio_lock);
5e69f97f 1875 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port),
89b667f8
JB		 1876 DPIO_PCS_TX_LANE2_RESET |
1877 DPIO_PCS_TX_LANE1_RESET);
5e69f97f 1878 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port),
89b667f8
JB		 1879 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1880 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1881 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1882 DPIO_PCS_CLK_SOFT_RESET);
1883
1884 /* Fix up inter-pair skew failure */
5e69f97f
CML		 1885 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00);
1886 vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500);
1887 vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000);
0980a60f 1888 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 1889}
1890
1891/*
df0c237d
JB		 1892 * Native read with retry for link status and receiver capability reads for
1893 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1894 */
1895static bool
df0c237d
JB		 1896intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1897 uint8_t *recv, int recv_bytes)
a4fc5ed6 1898{
61da5fab
JB		 1899 int ret, i;
1900
df0c237d
JB		 1901 /*
1902 * Sinks are *supposed* to come up within 1ms from an off state,
1903 * but we're also supposed to retry 3 times per the spec.
1904 */
61da5fab 1905 for (i = 0; i < 3; i++) {
df0c237d
JB		 1906 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1907 recv_bytes);
1908 if (ret == recv_bytes)
61da5fab
JB		 1909 return true;
1910 msleep(1);
1911 }
a4fc5ed6 1912
61da5fab 1913 return false;
a4fc5ed6
KP		 1914}
1915
1916/*
1917 * Fetch AUX CH registers 0x202 - 0x207 which contain
1918 * link status information
1919 */
1920static bool
93f62dad 1921intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1922{
df0c237d
JB		 1923 return intel_dp_aux_native_read_retry(intel_dp,
1924 DP_LANE0_1_STATUS,
93f62dad 1925 link_status,
df0c237d 1926 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1927}
1928
a4fc5ed6
KP		 1929#if 0
1930static char *voltage_names[] = {
1931 "0.4V", "0.6V", "0.8V", "1.2V"
1932};
1933static char *pre_emph_names[] = {
1934 "0dB", "3.5dB", "6dB", "9.5dB"
1935};
1936static char *link_train_names[] = {
1937 "pattern 1", "pattern 2", "idle", "off"
1938};
1939#endif
1940
1941/*
1942 * These are source-specific values; current Intel hardware supports
1943 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1944 */
a4fc5ed6
KP		 1945
1946static uint8_t
1a2eb460 1947intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1948{
30add22d 1949 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1950 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1951
e2fa6fba
P		 1952 if (IS_VALLEYVIEW(dev))
1953 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 1954 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 1955 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 1956 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 1957 return DP_TRAIN_VOLTAGE_SWING_1200;
1958 else
1959 return DP_TRAIN_VOLTAGE_SWING_800;
1960}
1961
1962static uint8_t
1963intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1964{
30add22d 1965 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1966 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1967
22b8bf17 1968 if (HAS_DDI(dev)) {
d6c0d722
PZ		 1969 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1970 case DP_TRAIN_VOLTAGE_SWING_400:
1971 return DP_TRAIN_PRE_EMPHASIS_9_5;
1972 case DP_TRAIN_VOLTAGE_SWING_600:
1973 return DP_TRAIN_PRE_EMPHASIS_6;
1974 case DP_TRAIN_VOLTAGE_SWING_800:
1975 return DP_TRAIN_PRE_EMPHASIS_3_5;
1976 case DP_TRAIN_VOLTAGE_SWING_1200:
1977 default:
1978 return DP_TRAIN_PRE_EMPHASIS_0;
1979 }
e2fa6fba
P		 1980 } else if (IS_VALLEYVIEW(dev)) {
1981 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1982 case DP_TRAIN_VOLTAGE_SWING_400:
1983 return DP_TRAIN_PRE_EMPHASIS_9_5;
1984 case DP_TRAIN_VOLTAGE_SWING_600:
1985 return DP_TRAIN_PRE_EMPHASIS_6;
1986 case DP_TRAIN_VOLTAGE_SWING_800:
1987 return DP_TRAIN_PRE_EMPHASIS_3_5;
1988 case DP_TRAIN_VOLTAGE_SWING_1200:
1989 default:
1990 return DP_TRAIN_PRE_EMPHASIS_0;
1991 }
bc7d38a4 1992 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1993 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1994 case DP_TRAIN_VOLTAGE_SWING_400:
1995 return DP_TRAIN_PRE_EMPHASIS_6;
1996 case DP_TRAIN_VOLTAGE_SWING_600:
1997 case DP_TRAIN_VOLTAGE_SWING_800:
1998 return DP_TRAIN_PRE_EMPHASIS_3_5;
1999 default:
2000 return DP_TRAIN_PRE_EMPHASIS_0;
2001 }
2002 } else {
2003 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2004 case DP_TRAIN_VOLTAGE_SWING_400:
2005 return DP_TRAIN_PRE_EMPHASIS_6;
2006 case DP_TRAIN_VOLTAGE_SWING_600:
2007 return DP_TRAIN_PRE_EMPHASIS_6;
2008 case DP_TRAIN_VOLTAGE_SWING_800:
2009 return DP_TRAIN_PRE_EMPHASIS_3_5;
2010 case DP_TRAIN_VOLTAGE_SWING_1200:
2011 default:
2012 return DP_TRAIN_PRE_EMPHASIS_0;
2013 }
a4fc5ed6
KP		 2014 }
2015}
2016
e2fa6fba
P		 2017static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2018{
2019 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2020 struct drm_i915_private *dev_priv = dev->dev_private;
2021 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2022 struct intel_crtc *intel_crtc =
2023 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2024 unsigned long demph_reg_value, preemph_reg_value,
2025 uniqtranscale_reg_value;
2026 uint8_t train_set = intel_dp->train_set[0];
cece5d58 2027 int port = vlv_dport_to_channel(dport);
5e69f97f 2028 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2029
2030 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2031 case DP_TRAIN_PRE_EMPHASIS_0:
2032 preemph_reg_value = 0x0004000;
2033 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2034 case DP_TRAIN_VOLTAGE_SWING_400:
2035 demph_reg_value = 0x2B405555;
2036 uniqtranscale_reg_value = 0x552AB83A;
2037 break;
2038 case DP_TRAIN_VOLTAGE_SWING_600:
2039 demph_reg_value = 0x2B404040;
2040 uniqtranscale_reg_value = 0x5548B83A;
2041 break;
2042 case DP_TRAIN_VOLTAGE_SWING_800:
2043 demph_reg_value = 0x2B245555;
2044 uniqtranscale_reg_value = 0x5560B83A;
2045 break;
2046 case DP_TRAIN_VOLTAGE_SWING_1200:
2047 demph_reg_value = 0x2B405555;
2048 uniqtranscale_reg_value = 0x5598DA3A;
2049 break;
2050 default:
2051 return 0;
2052 }
2053 break;
2054 case DP_TRAIN_PRE_EMPHASIS_3_5:
2055 preemph_reg_value = 0x0002000;
2056 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2057 case DP_TRAIN_VOLTAGE_SWING_400:
2058 demph_reg_value = 0x2B404040;
2059 uniqtranscale_reg_value = 0x5552B83A;
2060 break;
2061 case DP_TRAIN_VOLTAGE_SWING_600:
2062 demph_reg_value = 0x2B404848;
2063 uniqtranscale_reg_value = 0x5580B83A;
2064 break;
2065 case DP_TRAIN_VOLTAGE_SWING_800:
2066 demph_reg_value = 0x2B404040;
2067 uniqtranscale_reg_value = 0x55ADDA3A;
2068 break;
2069 default:
2070 return 0;
2071 }
2072 break;
2073 case DP_TRAIN_PRE_EMPHASIS_6:
2074 preemph_reg_value = 0x0000000;
2075 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2076 case DP_TRAIN_VOLTAGE_SWING_400:
2077 demph_reg_value = 0x2B305555;
2078 uniqtranscale_reg_value = 0x5570B83A;
2079 break;
2080 case DP_TRAIN_VOLTAGE_SWING_600:
2081 demph_reg_value = 0x2B2B4040;
2082 uniqtranscale_reg_value = 0x55ADDA3A;
2083 break;
2084 default:
2085 return 0;
2086 }
2087 break;
2088 case DP_TRAIN_PRE_EMPHASIS_9_5:
2089 preemph_reg_value = 0x0006000;
2090 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2091 case DP_TRAIN_VOLTAGE_SWING_400:
2092 demph_reg_value = 0x1B405555;
2093 uniqtranscale_reg_value = 0x55ADDA3A;
2094 break;
2095 default:
2096 return 0;
2097 }
2098 break;
2099 default:
2100 return 0;
2101 }
2102
0980a60f 2103 mutex_lock(&dev_priv->dpio_lock);
5e69f97f
CML		 2104 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x00000000);
2105 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port), demph_reg_value);
2106 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port),
e2fa6fba 2107 uniqtranscale_reg_value);
5e69f97f
CML		 2108 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port), 0x0C782040);
2109 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000);
2110 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
2111 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x80000000);
0980a60f 2112 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2113
2114 return 0;
2115}
2116
a4fc5ed6 2117static void
93f62dad 2118intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2119{
2120 uint8_t v = 0;
2121 uint8_t p = 0;
2122 int lane;
1a2eb460
KP		 2123 uint8_t voltage_max;
2124 uint8_t preemph_max;
a4fc5ed6 2125
33a34e4e 2126 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2127 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2128 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2129
2130 if (this_v > v)
2131 v = this_v;
2132 if (this_p > p)
2133 p = this_p;
2134 }
2135
1a2eb460 2136 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2137 if (v >= voltage_max)
2138 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2139
1a2eb460
KP		 2140 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2141 if (p >= preemph_max)
2142 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2143
2144 for (lane = 0; lane < 4; lane++)
33a34e4e 2145 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2146}
2147
2148static uint32_t
f0a3424e 2149intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2150{
3cf2efb1 2151 uint32_t signal_levels = 0;
a4fc5ed6 2152
3cf2efb1 2153 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2154 case DP_TRAIN_VOLTAGE_SWING_400:
2155 default:
2156 signal_levels |= DP_VOLTAGE_0_4;
2157 break;
2158 case DP_TRAIN_VOLTAGE_SWING_600:
2159 signal_levels |= DP_VOLTAGE_0_6;
2160 break;
2161 case DP_TRAIN_VOLTAGE_SWING_800:
2162 signal_levels |= DP_VOLTAGE_0_8;
2163 break;
2164 case DP_TRAIN_VOLTAGE_SWING_1200:
2165 signal_levels |= DP_VOLTAGE_1_2;
2166 break;
2167 }
3cf2efb1 2168 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2169 case DP_TRAIN_PRE_EMPHASIS_0:
2170 default:
2171 signal_levels |= DP_PRE_EMPHASIS_0;
2172 break;
2173 case DP_TRAIN_PRE_EMPHASIS_3_5:
2174 signal_levels |= DP_PRE_EMPHASIS_3_5;
2175 break;
2176 case DP_TRAIN_PRE_EMPHASIS_6:
2177 signal_levels |= DP_PRE_EMPHASIS_6;
2178 break;
2179 case DP_TRAIN_PRE_EMPHASIS_9_5:
2180 signal_levels |= DP_PRE_EMPHASIS_9_5;
2181 break;
2182 }
2183 return signal_levels;
2184}
2185
e3421a18
ZW		 2186/* Gen6's DP voltage swing and pre-emphasis control */
2187static uint32_t
2188intel_gen6_edp_signal_levels(uint8_t train_set)
2189{
3c5a62b5
YL		 2190 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2191 DP_TRAIN_PRE_EMPHASIS_MASK);
2192 switch (signal_levels) {
e3421a18 2193 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2194 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2195 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2196 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2197 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2198 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2199 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2200 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2201 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2202 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2203 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2204 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2205 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2206 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2207 default:
3c5a62b5
YL		 2208 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2209 "0x%x\n", signal_levels);
2210 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2211 }
2212}
2213
1a2eb460
KP		 2214/* Gen7's DP voltage swing and pre-emphasis control */
2215static uint32_t
2216intel_gen7_edp_signal_levels(uint8_t train_set)
2217{
2218 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2219 DP_TRAIN_PRE_EMPHASIS_MASK);
2220 switch (signal_levels) {
2221 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2222 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2223 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2224 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2225 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2226 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2227
2228 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2229 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2230 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2231 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2232
2233 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2234 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2235 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2236 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2237
2238 default:
2239 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2240 "0x%x\n", signal_levels);
2241 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2242 }
2243}
2244
d6c0d722
PZ		 2245/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2246static uint32_t
f0a3424e 2247intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2248{
d6c0d722
PZ		 2249 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2250 DP_TRAIN_PRE_EMPHASIS_MASK);
2251 switch (signal_levels) {
2252 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2253 return DDI_BUF_EMP_400MV_0DB_HSW;
2254 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2255 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2256 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2257 return DDI_BUF_EMP_400MV_6DB_HSW;
2258 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2259 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2260
d6c0d722
PZ		 2261 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2262 return DDI_BUF_EMP_600MV_0DB_HSW;
2263 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2264 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2265 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2266 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2267
d6c0d722
PZ		 2268 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2269 return DDI_BUF_EMP_800MV_0DB_HSW;
2270 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2271 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2272 default:
2273 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2274 "0x%x\n", signal_levels);
2275 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2276 }
a4fc5ed6
KP		 2277}
2278
f0a3424e
PZ		 2279/* Properly updates "DP" with the correct signal levels. */
2280static void
2281intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2282{
2283 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2284 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2285 struct drm_device *dev = intel_dig_port->base.base.dev;
2286 uint32_t signal_levels, mask;
2287 uint8_t train_set = intel_dp->train_set[0];
2288
22b8bf17 2289 if (HAS_DDI(dev)) {
f0a3424e
PZ		 2290 signal_levels = intel_hsw_signal_levels(train_set);
2291 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2292 } else if (IS_VALLEYVIEW(dev)) {
2293 signal_levels = intel_vlv_signal_levels(intel_dp);
2294 mask = 0;
bc7d38a4 2295 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2296 signal_levels = intel_gen7_edp_signal_levels(train_set);
2297 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2298 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2299 signal_levels = intel_gen6_edp_signal_levels(train_set);
2300 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2301 } else {
2302 signal_levels = intel_gen4_signal_levels(train_set);
2303 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2304 }
2305
2306 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2307
2308 *DP = (*DP & ~mask) | signal_levels;
2309}
2310
a4fc5ed6 2311static bool
ea5b213a 2312intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 2313 uint32_t dp_reg_value,
58e10eb9 2314 uint8_t dp_train_pat)
a4fc5ed6 2315{
174edf1f
PZ		 2316 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2317 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2318 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2319 enum port port = intel_dig_port->port;
a4fc5ed6
KP		 2320 int ret;
2321
22b8bf17 2322 if (HAS_DDI(dev)) {
3ab9c637 2323 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2324
2325 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2326 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2327 else
2328 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2329
2330 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2331 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2332 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2333 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2334
2335 break;
2336 case DP_TRAINING_PATTERN_1:
2337 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2338 break;
2339 case DP_TRAINING_PATTERN_2:
2340 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2341 break;
2342 case DP_TRAINING_PATTERN_3:
2343 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2344 break;
2345 }
174edf1f 2346 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2347
bc7d38a4 2348 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
47ea7542
PZ		 2349 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
2350
2351 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2352 case DP_TRAINING_PATTERN_DISABLE:
2353 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
2354 break;
2355 case DP_TRAINING_PATTERN_1:
2356 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
2357 break;
2358 case DP_TRAINING_PATTERN_2:
2359 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2360 break;
2361 case DP_TRAINING_PATTERN_3:
2362 DRM_ERROR("DP training pattern 3 not supported\n");
2363 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2364 break;
2365 }
2366
2367 } else {
2368 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
2369
2370 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2371 case DP_TRAINING_PATTERN_DISABLE:
2372 dp_reg_value |= DP_LINK_TRAIN_OFF;
2373 break;
2374 case DP_TRAINING_PATTERN_1:
2375 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
2376 break;
2377 case DP_TRAINING_PATTERN_2:
2378 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2379 break;
2380 case DP_TRAINING_PATTERN_3:
2381 DRM_ERROR("DP training pattern 3 not supported\n");
2382 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2383 break;
2384 }
2385 }
2386
ea5b213a
CW		 2387 I915_WRITE(intel_dp->output_reg, dp_reg_value);
2388 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2389
ea5b213a 2390 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 2391 DP_TRAINING_PATTERN_SET,
2392 dp_train_pat);
2393
47ea7542
PZ		 2394 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
2395 DP_TRAINING_PATTERN_DISABLE) {
2396 ret = intel_dp_aux_native_write(intel_dp,
2397 DP_TRAINING_LANE0_SET,
2398 intel_dp->train_set,
2399 intel_dp->lane_count);
2400 if (ret != intel_dp->lane_count)
2401 return false;
2402 }
a4fc5ed6
KP		 2403
2404 return true;
2405}
2406
3ab9c637
ID		 2407static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2408{
2409 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2410 struct drm_device *dev = intel_dig_port->base.base.dev;
2411 struct drm_i915_private *dev_priv = dev->dev_private;
2412 enum port port = intel_dig_port->port;
2413 uint32_t val;
2414
2415 if (!HAS_DDI(dev))
2416 return;
2417
2418 val = I915_READ(DP_TP_CTL(port));
2419 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2420 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2421 I915_WRITE(DP_TP_CTL(port), val);
2422
2423 /*
2424 * On PORT_A we can have only eDP in SST mode. There the only reason
2425 * we need to set idle transmission mode is to work around a HW issue
2426 * where we enable the pipe while not in idle link-training mode.
2427 * In this case there is requirement to wait for a minimum number of
2428 * idle patterns to be sent.
2429 */
2430 if (port == PORT_A)
2431 return;
2432
2433 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2434 1))
2435 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2436}
2437
33a34e4e 2438/* Enable corresponding port and start training pattern 1 */
c19b0669 2439void
33a34e4e 2440intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2441{
da63a9f2 2442 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2443 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2444 int i;
2445 uint8_t voltage;
cdb0e95b 2446 int voltage_tries, loop_tries;
ea5b213a 2447 uint32_t DP = intel_dp->DP;
a4fc5ed6 2448
affa9354 2449 if (HAS_DDI(dev))
c19b0669
PZ		 2450 intel_ddi_prepare_link_retrain(encoder);
2451
3cf2efb1
CW		 2452 /* Write the link configuration data */
2453 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2454 intel_dp->link_configuration,
2455 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 2456
2457 DP |= DP_PORT_EN;
1a2eb460 2458
33a34e4e 2459 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 2460 voltage = 0xff;
cdb0e95b
KP		 2461 voltage_tries = 0;
2462 loop_tries = 0;
a4fc5ed6 2463 for (;;) {
33a34e4e 2464 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 2465 uint8_t link_status[DP_LINK_STATUS_SIZE];
f0a3424e
PZ		 2466
2467 intel_dp_set_signal_levels(intel_dp, &DP);
a4fc5ed6 2468
a7c9655f 2469 /* Set training pattern 1 */
47ea7542 2470 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2471 DP_TRAINING_PATTERN_1 |
2472 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 2473 break;
a4fc5ed6 2474
a7c9655f 2475 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2476 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2477 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2478 break;
93f62dad 2479 }
a4fc5ed6 2480
01916270 2481 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2482 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2483 break;
2484 }
2485
2486 /* Check to see if we've tried the max voltage */
2487 for (i = 0; i < intel_dp->lane_count; i++)
2488 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2489 break;
3b4f819d 2490 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2491 ++loop_tries;
2492 if (loop_tries == 5) {
cdb0e95b
KP		 2493 DRM_DEBUG_KMS("too many full retries, give up\n");
2494 break;
2495 }
2496 memset(intel_dp->train_set, 0, 4);
2497 voltage_tries = 0;
2498 continue;
2499 }
a4fc5ed6 2500
3cf2efb1 2501 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2502 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2503 ++voltage_tries;
b06fbda3
DV		 2504 if (voltage_tries == 5) {
2505 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2506 break;
2507 }
2508 } else
2509 voltage_tries = 0;
2510 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2511
3cf2efb1 2512 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2513 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 2514 }
2515
33a34e4e
JB		 2516 intel_dp->DP = DP;
2517}
2518
c19b0669 2519void
33a34e4e
JB		 2520intel_dp_complete_link_train(struct intel_dp *intel_dp)
2521{
33a34e4e 2522 bool channel_eq = false;
37f80975 2523 int tries, cr_tries;
33a34e4e
JB		 2524 uint32_t DP = intel_dp->DP;
2525
a4fc5ed6
KP		 2526 /* channel equalization */
2527 tries = 0;
37f80975 2528 cr_tries = 0;
a4fc5ed6
KP		 2529 channel_eq = false;
2530 for (;;) {
93f62dad 2531 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2532
37f80975
JB		 2533 if (cr_tries > 5) {
2534 DRM_ERROR("failed to train DP, aborting\n");
2535 intel_dp_link_down(intel_dp);
2536 break;
2537 }
2538
f0a3424e 2539 intel_dp_set_signal_levels(intel_dp, &DP);
e3421a18 2540
a4fc5ed6 2541 /* channel eq pattern */
47ea7542 2542 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2543 DP_TRAINING_PATTERN_2 |
2544 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 2545 break;
2546
a7c9655f 2547 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 2548 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 2549 break;
a4fc5ed6 2550
37f80975 2551 /* Make sure clock is still ok */
01916270 2552 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 2553 intel_dp_start_link_train(intel_dp);
2554 cr_tries++;
2555 continue;
2556 }
2557
1ffdff13 2558 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2559 channel_eq = true;
2560 break;
2561 }
a4fc5ed6 2562
37f80975
JB		 2563 /* Try 5 times, then try clock recovery if that fails */
2564 if (tries > 5) {
2565 intel_dp_link_down(intel_dp);
2566 intel_dp_start_link_train(intel_dp);
2567 tries = 0;
2568 cr_tries++;
2569 continue;
2570 }
a4fc5ed6 2571
3cf2efb1 2572 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2573 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 2574 ++tries;
869184a6 2575 }
3cf2efb1 2576
3ab9c637
ID		 2577 intel_dp_set_idle_link_train(intel_dp);
2578
2579 intel_dp->DP = DP;
2580
d6c0d722 2581 if (channel_eq)
07f42258 2582 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2583
3ab9c637
ID		 2584}
2585
2586void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2587{
2588 intel_dp_set_link_train(intel_dp, intel_dp->DP,
2589 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2590}
2591
2592static void
ea5b213a 2593intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2594{
da63a9f2 2595 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2596 enum port port = intel_dig_port->port;
da63a9f2 2597 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2598 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2599 struct intel_crtc *intel_crtc =
2600 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2601 uint32_t DP = intel_dp->DP;
a4fc5ed6 2602
c19b0669
PZ		 2603 /*
2604 * DDI code has a strict mode set sequence and we should try to respect
2605 * it, otherwise we might hang the machine in many different ways. So we
2606 * really should be disabling the port only on a complete crtc_disable
2607 * sequence. This function is just called under two conditions on DDI
2608 * code:
2609 * - Link train failed while doing crtc_enable, and on this case we
2610 * really should respect the mode set sequence and wait for a
2611 * crtc_disable.
2612 * - Someone turned the monitor off and intel_dp_check_link_status
2613 * called us. We don't need to disable the whole port on this case, so
2614 * when someone turns the monitor on again,
2615 * intel_ddi_prepare_link_retrain will take care of redoing the link
2616 * train.
2617 */
affa9354 2618 if (HAS_DDI(dev))
c19b0669
PZ		 2619 return;
2620
0c33d8d7 2621 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2622 return;
2623
28c97730 2624 DRM_DEBUG_KMS("\n");
32f9d658 2625
bc7d38a4 2626 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2627 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2628 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2629 } else {
2630 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2631 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2632 }
fe255d00 2633 POSTING_READ(intel_dp->output_reg);
5eb08b69 2634
ab527efc
DV		 2635 /* We don't really know why we're doing this */
2636 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2637
493a7081 2638 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2639 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2640 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2641
5bddd17f
EA		 2642 /* Hardware workaround: leaving our transcoder select
2643 * set to transcoder B while it's off will prevent the
2644 * corresponding HDMI output on transcoder A.
2645 *
2646 * Combine this with another hardware workaround:
2647 * transcoder select bit can only be cleared while the
2648 * port is enabled.
2649 */
2650 DP &= ~DP_PIPEB_SELECT;
2651 I915_WRITE(intel_dp->output_reg, DP);
2652
2653 /* Changes to enable or select take place the vblank
2654 * after being written.
2655 */
ff50afe9
DV		 2656 if (WARN_ON(crtc == NULL)) {
2657 /* We should never try to disable a port without a crtc
2658 * attached. For paranoia keep the code around for a
2659 * bit. */
31acbcc4
CW		 2660 POSTING_READ(intel_dp->output_reg);
2661 msleep(50);
2662 } else
ab527efc 2663 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2664 }
2665
832afda6 2666 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2667 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2668 POSTING_READ(intel_dp->output_reg);
f01eca2e 2669 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2670}
2671
26d61aad
KP		 2672static bool
2673intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2674{
577c7a50
DL		 2675 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2676
92fd8fd1 2677 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2678 sizeof(intel_dp->dpcd)) == 0)
2679 return false; /* aux transfer failed */
92fd8fd1 2680
577c7a50
DL		 2681 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2682 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2683 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2684
edb39244
AJ		 2685 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2686 return false; /* DPCD not present */
2687
2293bb5c
SK		 2688 /* Check if the panel supports PSR */
2689 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939
JN		 2690 if (is_edp(intel_dp)) {
2691 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2692 intel_dp->psr_dpcd,
2693 sizeof(intel_dp->psr_dpcd));
2694 if (is_edp_psr(intel_dp))
2695 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2696 }
2697
edb39244
AJ		 2698 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2699 DP_DWN_STRM_PORT_PRESENT))
2700 return true; /* native DP sink */
2701
2702 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2703 return true; /* no per-port downstream info */
2704
2705 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2706 intel_dp->downstream_ports,
2707 DP_MAX_DOWNSTREAM_PORTS) == 0)
2708 return false; /* downstream port status fetch failed */
2709
2710 return true;
92fd8fd1
KP		 2711}
2712
0d198328
AJ		 2713static void
2714intel_dp_probe_oui(struct intel_dp *intel_dp)
2715{
2716 u8 buf[3];
2717
2718 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2719 return;
2720
351cfc34
DV		 2721 ironlake_edp_panel_vdd_on(intel_dp);
2722
0d198328
AJ		 2723 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2724 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2725 buf[0], buf[1], buf[2]);
2726
2727 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2728 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2729 buf[0], buf[1], buf[2]);
351cfc34
DV		 2730
2731 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2732}
2733
a60f0e38
JB		 2734static bool
2735intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2736{
2737 int ret;
2738
2739 ret = intel_dp_aux_native_read_retry(intel_dp,
2740 DP_DEVICE_SERVICE_IRQ_VECTOR,
2741 sink_irq_vector, 1);
2742 if (!ret)
2743 return false;
2744
2745 return true;
2746}
2747
2748static void
2749intel_dp_handle_test_request(struct intel_dp *intel_dp)
2750{
2751 /* NAK by default */
9324cf7f 2752 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2753}
2754
a4fc5ed6
KP		 2755/*
2756 * According to DP spec
2757 * 5.1.2:
2758 * 1. Read DPCD
2759 * 2. Configure link according to Receiver Capabilities
2760 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2761 * 4. Check link status on receipt of hot-plug interrupt
2762 */
2763
00c09d70 2764void
ea5b213a 2765intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2766{
da63a9f2 2767 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2768 u8 sink_irq_vector;
93f62dad 2769 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2770
da63a9f2 2771 if (!intel_encoder->connectors_active)
d2b996ac 2772 return;
59cd09e1 2773
da63a9f2 2774 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2775 return;
2776
92fd8fd1 2777 /* Try to read receiver status if the link appears to be up */
93f62dad 2778 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2779 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2780 return;
2781 }
2782
92fd8fd1 2783 /* Now read the DPCD to see if it's actually running */
26d61aad 2784 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2785 intel_dp_link_down(intel_dp);
2786 return;
2787 }
2788
a60f0e38
JB		 2789 /* Try to read the source of the interrupt */
2790 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2791 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2792 /* Clear interrupt source */
2793 intel_dp_aux_native_write_1(intel_dp,
2794 DP_DEVICE_SERVICE_IRQ_VECTOR,
2795 sink_irq_vector);
2796
2797 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2798 intel_dp_handle_test_request(intel_dp);
2799 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2800 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2801 }
2802
1ffdff13 2803 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2804 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2805 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2806 intel_dp_start_link_train(intel_dp);
2807 intel_dp_complete_link_train(intel_dp);
3ab9c637 2808 intel_dp_stop_link_train(intel_dp);
33a34e4e 2809 }
a4fc5ed6 2810}
a4fc5ed6 2811
caf9ab24 2812/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2813static enum drm_connector_status
26d61aad 2814intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2815{
caf9ab24
AJ		 2816 uint8_t *dpcd = intel_dp->dpcd;
2817 bool hpd;
2818 uint8_t type;
2819
2820 if (!intel_dp_get_dpcd(intel_dp))
2821 return connector_status_disconnected;
2822
2823 /* if there's no downstream port, we're done */
2824 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2825 return connector_status_connected;
caf9ab24
AJ		 2826
2827 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2828 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2829 if (hpd) {
23235177 2830 uint8_t reg;
caf9ab24 2831 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2832 &reg, 1))
caf9ab24 2833 return connector_status_unknown;
23235177
AJ		 2834 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2835 : connector_status_disconnected;
caf9ab24
AJ		 2836 }
2837
2838 /* If no HPD, poke DDC gently */
2839 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2840 return connector_status_connected;
caf9ab24
AJ		 2841
2842 /* Well we tried, say unknown for unreliable port types */
2843 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2844 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2845 return connector_status_unknown;
2846
2847 /* Anything else is out of spec, warn and ignore */
2848 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2849 return connector_status_disconnected;
71ba9000
AJ		 2850}
2851
5eb08b69 2852static enum drm_connector_status
a9756bb5 2853ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2854{
30add22d 2855 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2856 struct drm_i915_private *dev_priv = dev->dev_private;
2857 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2858 enum drm_connector_status status;
2859
fe16d949
CW		 2860 /* Can't disconnect eDP, but you can close the lid... */
2861 if (is_edp(intel_dp)) {
30add22d 2862 status = intel_panel_detect(dev);
fe16d949
CW		 2863 if (status == connector_status_unknown)
2864 status = connector_status_connected;
2865 return status;
2866 }
01cb9ea6 2867
1b469639
DL		 2868 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2869 return connector_status_disconnected;
2870
26d61aad 2871 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2872}
2873
a4fc5ed6 2874static enum drm_connector_status
a9756bb5 2875g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2876{
30add22d 2877 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2878 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 2879 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 2880 uint32_t bit;
5eb08b69 2881
35aad75f
JB		 2882 /* Can't disconnect eDP, but you can close the lid... */
2883 if (is_edp(intel_dp)) {
2884 enum drm_connector_status status;
2885
2886 status = intel_panel_detect(dev);
2887 if (status == connector_status_unknown)
2888 status = connector_status_connected;
2889 return status;
2890 }
2891
34f2be46
VS		 2892 switch (intel_dig_port->port) {
2893 case PORT_B:
26739f12 2894 bit = PORTB_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2895 break;
34f2be46 2896 case PORT_C:
26739f12 2897 bit = PORTC_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2898 break;
34f2be46 2899 case PORT_D:
26739f12 2900 bit = PORTD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2901 break;
2902 default:
2903 return connector_status_unknown;
2904 }
2905
10f76a38 2906 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2907 return connector_status_disconnected;
2908
26d61aad 2909 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2910}
2911
8c241fef
KP		 2912static struct edid *
2913intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2914{
9cd300e0 2915 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2916
9cd300e0
JN		 2917 /* use cached edid if we have one */
2918 if (intel_connector->edid) {
2919 struct edid *edid;
2920 int size;
2921
2922 /* invalid edid */
2923 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2924 return NULL;
2925
9cd300e0 2926 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
edbe1581 2927 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
d6f24d0f
JB		 2928 if (!edid)
2929 return NULL;
2930
d6f24d0f
JB		 2931 return edid;
2932 }
8c241fef 2933
9cd300e0 2934 return drm_get_edid(connector, adapter);
8c241fef
KP		 2935}
2936
2937static int
2938intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2939{
9cd300e0 2940 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2941
9cd300e0
JN		 2942 /* use cached edid if we have one */
2943 if (intel_connector->edid) {
2944 /* invalid edid */
2945 if (IS_ERR(intel_connector->edid))
2946 return 0;
2947
2948 return intel_connector_update_modes(connector,
2949 intel_connector->edid);
d6f24d0f
JB		 2950 }
2951
9cd300e0 2952 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2953}
2954
a9756bb5
ZW		 2955static enum drm_connector_status
2956intel_dp_detect(struct drm_connector *connector, bool force)
2957{
2958 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2959 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2960 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2961 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 2962 enum drm_connector_status status;
2963 struct edid *edid = NULL;
2964
164c8598
CW		 2965 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2966 connector->base.id, drm_get_connector_name(connector));
2967
a9756bb5
ZW		 2968 intel_dp->has_audio = false;
2969
2970 if (HAS_PCH_SPLIT(dev))
2971 status = ironlake_dp_detect(intel_dp);
2972 else
2973 status = g4x_dp_detect(intel_dp);
1b9be9d0 2974
a9756bb5
ZW		 2975 if (status != connector_status_connected)
2976 return status;
2977
0d198328
AJ		 2978 intel_dp_probe_oui(intel_dp);
2979
c3e5f67b
DV		 2980 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2981 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2982 } else {
8c241fef 2983 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2984 if (edid) {
2985 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2986 kfree(edid);
2987 }
a9756bb5
ZW		 2988 }
2989
d63885da
PZ		 2990 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2991 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2992 return connector_status_connected;
a4fc5ed6
KP		 2993}
2994
2995static int intel_dp_get_modes(struct drm_connector *connector)
2996{
df0e9248 2997 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2998 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2999 struct drm_device *dev = connector->dev;
32f9d658 3000 int ret;
a4fc5ed6
KP		 3001
3002 /* We should parse the EDID data and find out if it has an audio sink
3003 */
3004
8c241fef 3005 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 3006 if (ret)
32f9d658
ZW		 3007 return ret;
3008
f8779fda 3009 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3010 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3011 struct drm_display_mode *mode;
dd06f90e
JN		 3012 mode = drm_mode_duplicate(dev,
3013 intel_connector->panel.fixed_mode);
f8779fda 3014 if (mode) {
32f9d658
ZW		 3015 drm_mode_probed_add(connector, mode);
3016 return 1;
3017 }
3018 }
3019 return 0;
a4fc5ed6
KP		 3020}
3021
1aad7ac0
CW		 3022static bool
3023intel_dp_detect_audio(struct drm_connector *connector)
3024{
3025 struct intel_dp *intel_dp = intel_attached_dp(connector);
3026 struct edid *edid;
3027 bool has_audio = false;
3028
8c241fef 3029 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 3030 if (edid) {
3031 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3032 kfree(edid);
3033 }
3034
3035 return has_audio;
3036}
3037
f684960e
CW		 3038static int
3039intel_dp_set_property(struct drm_connector *connector,
3040 struct drm_property *property,
3041 uint64_t val)
3042{
e953fd7b 3043 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3044 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3045 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3046 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3047 int ret;
3048
662595df 3049 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3050 if (ret)
3051 return ret;
3052
3f43c48d 3053 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3054 int i = val;
3055 bool has_audio;
3056
3057 if (i == intel_dp->force_audio)
f684960e
CW		 3058 return 0;
3059
1aad7ac0 3060 intel_dp->force_audio = i;
f684960e 3061
c3e5f67b 3062 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3063 has_audio = intel_dp_detect_audio(connector);
3064 else
c3e5f67b 3065 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3066
3067 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3068 return 0;
3069
1aad7ac0 3070 intel_dp->has_audio = has_audio;
f684960e
CW		 3071 goto done;
3072 }
3073
e953fd7b 3074 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3075 bool old_auto = intel_dp->color_range_auto;
3076 uint32_t old_range = intel_dp->color_range;
3077
55bc60db
VS		 3078 switch (val) {
3079 case INTEL_BROADCAST_RGB_AUTO:
3080 intel_dp->color_range_auto = true;
3081 break;
3082 case INTEL_BROADCAST_RGB_FULL:
3083 intel_dp->color_range_auto = false;
3084 intel_dp->color_range = 0;
3085 break;
3086 case INTEL_BROADCAST_RGB_LIMITED:
3087 intel_dp->color_range_auto = false;
3088 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3089 break;
3090 default:
3091 return -EINVAL;
3092 }
ae4edb80
DV		 3093
3094 if (old_auto == intel_dp->color_range_auto &&
3095 old_range == intel_dp->color_range)
3096 return 0;
3097
e953fd7b
CW		 3098 goto done;
3099 }
3100
53b41837
YN		 3101 if (is_edp(intel_dp) &&
3102 property == connector->dev->mode_config.scaling_mode_property) {
3103 if (val == DRM_MODE_SCALE_NONE) {
3104 DRM_DEBUG_KMS("no scaling not supported\n");
3105 return -EINVAL;
3106 }
3107
3108 if (intel_connector->panel.fitting_mode == val) {
3109 /* the eDP scaling property is not changed */
3110 return 0;
3111 }
3112 intel_connector->panel.fitting_mode = val;
3113
3114 goto done;
3115 }
3116
f684960e
CW		 3117 return -EINVAL;
3118
3119done:
c0c36b94
CW		 3120 if (intel_encoder->base.crtc)
3121 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3122
3123 return 0;
3124}
3125
a4fc5ed6 3126static void
73845adf 3127intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3128{
1d508706 3129 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3130
9cd300e0
JN		 3131 if (!IS_ERR_OR_NULL(intel_connector->edid))
3132 kfree(intel_connector->edid);
3133
acd8db10
PZ		 3134 /* Can't call is_edp() since the encoder may have been destroyed
3135 * already. */
3136 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3137 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3138
a4fc5ed6
KP		 3139 drm_sysfs_connector_remove(connector);
3140 drm_connector_cleanup(connector);
55f78c43 3141 kfree(connector);
a4fc5ed6
KP		 3142}
3143
00c09d70 3144void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3145{
da63a9f2
PZ		 3146 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3147 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3148 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927
DV		 3149
3150 i2c_del_adapter(&intel_dp->adapter);
3151 drm_encoder_cleanup(encoder);
bd943159
KP		 3152 if (is_edp(intel_dp)) {
3153 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3154 mutex_lock(&dev->mode_config.mutex);
bd943159 3155 ironlake_panel_vdd_off_sync(intel_dp);
bd173813 3156 mutex_unlock(&dev->mode_config.mutex);
bd943159 3157 }
da63a9f2 3158 kfree(intel_dig_port);
24d05927
DV		 3159}
3160
a4fc5ed6 3161static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3162 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3163 .detect = intel_dp_detect,
3164 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3165 .set_property = intel_dp_set_property,
73845adf 3166 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3167};
3168
3169static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3170 .get_modes = intel_dp_get_modes,
3171 .mode_valid = intel_dp_mode_valid,
df0e9248 3172 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3173};
3174
a4fc5ed6 3175static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3176 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3177};
3178
995b6762 3179static void
21d40d37 3180intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3181{
fa90ecef 3182 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3183
885a5014 3184 intel_dp_check_link_status(intel_dp);
c8110e52 3185}
6207937d 3186
e3421a18
ZW		 3187/* Return which DP Port should be selected for Transcoder DP control */
3188int
0206e353 3189intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3190{
3191 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3192 struct intel_encoder *intel_encoder;
3193 struct intel_dp *intel_dp;
e3421a18 3194
fa90ecef
PZ		 3195 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3196 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3197
fa90ecef
PZ		 3198 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3199 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3200 return intel_dp->output_reg;
e3421a18 3201 }
ea5b213a 3202
e3421a18
ZW		 3203 return -1;
3204}
3205
36e83a18 3206/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 3207bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 3208{
3209 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3210 union child_device_config *p_child;
36e83a18
ZY		 3211 int i;
3212
41aa3448 3213 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3214 return false;
3215
41aa3448
RV		 3216 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3217 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3218
768f69c9
PZ		 3219 if (p_child->common.dvo_port == PORT_IDPD &&
3220 p_child->common.device_type == DEVICE_TYPE_eDP)
36e83a18
ZY		 3221 return true;
3222 }
3223 return false;
3224}
3225
f684960e
CW		 3226static void
3227intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3228{
53b41837
YN		 3229 struct intel_connector *intel_connector = to_intel_connector(connector);
3230
3f43c48d 3231 intel_attach_force_audio_property(connector);
e953fd7b 3232 intel_attach_broadcast_rgb_property(connector);
55bc60db 3233 intel_dp->color_range_auto = true;
53b41837
YN		 3234
3235 if (is_edp(intel_dp)) {
3236 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3237 drm_object_attach_property(
3238 &connector->base,
53b41837 3239 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3240 DRM_MODE_SCALE_ASPECT);
3241 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3242 }
f684960e
CW		 3243}
3244
67a54566
DV		 3245static void
3246intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3247 struct intel_dp *intel_dp,
3248 struct edp_power_seq *out)
67a54566
DV		 3249{
3250 struct drm_i915_private *dev_priv = dev->dev_private;
3251 struct edp_power_seq cur, vbt, spec, final;
3252 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3253 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3254
3255 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3256 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3257 pp_on_reg = PCH_PP_ON_DELAYS;
3258 pp_off_reg = PCH_PP_OFF_DELAYS;
3259 pp_div_reg = PCH_PP_DIVISOR;
3260 } else {
bf13e81b
JN		 3261 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3262
3263 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3264 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3265 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3266 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3267 }
67a54566
DV		 3268
3269 /* Workaround: Need to write PP_CONTROL with the unlock key as
3270 * the very first thing. */
453c5420 3271 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3272 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3273
453c5420
JB		 3274 pp_on = I915_READ(pp_on_reg);
3275 pp_off = I915_READ(pp_off_reg);
3276 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3277
3278 /* Pull timing values out of registers */
3279 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3280 PANEL_POWER_UP_DELAY_SHIFT;
3281
3282 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3283 PANEL_LIGHT_ON_DELAY_SHIFT;
3284
3285 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3286 PANEL_LIGHT_OFF_DELAY_SHIFT;
3287
3288 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3289 PANEL_POWER_DOWN_DELAY_SHIFT;
3290
3291 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3292 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3293
3294 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3295 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3296
41aa3448 3297 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3298
3299 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3300 * our hw here, which are all in 100usec. */
3301 spec.t1_t3 = 210 * 10;
3302 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3303 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3304 spec.t10 = 500 * 10;
3305 /* This one is special and actually in units of 100ms, but zero
3306 * based in the hw (so we need to add 100 ms). But the sw vbt
3307 * table multiplies it with 1000 to make it in units of 100usec,
3308 * too. */
3309 spec.t11_t12 = (510 + 100) * 10;
3310
3311 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3312 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3313
3314 /* Use the max of the register settings and vbt. If both are
3315 * unset, fall back to the spec limits. */
3316#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3317 spec.field : \
3318 max(cur.field, vbt.field))
3319 assign_final(t1_t3);
3320 assign_final(t8);
3321 assign_final(t9);
3322 assign_final(t10);
3323 assign_final(t11_t12);
3324#undef assign_final
3325
3326#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3327 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3328 intel_dp->backlight_on_delay = get_delay(t8);
3329 intel_dp->backlight_off_delay = get_delay(t9);
3330 intel_dp->panel_power_down_delay = get_delay(t10);
3331 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3332#undef get_delay
3333
f30d26e4
JN		 3334 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3335 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3336 intel_dp->panel_power_cycle_delay);
3337
3338 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3339 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3340
3341 if (out)
3342 *out = final;
3343}
3344
3345static void
3346intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3347 struct intel_dp *intel_dp,
3348 struct edp_power_seq *seq)
3349{
3350 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3351 u32 pp_on, pp_off, pp_div, port_sel = 0;
3352 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3353 int pp_on_reg, pp_off_reg, pp_div_reg;
3354
3355 if (HAS_PCH_SPLIT(dev)) {
3356 pp_on_reg = PCH_PP_ON_DELAYS;
3357 pp_off_reg = PCH_PP_OFF_DELAYS;
3358 pp_div_reg = PCH_PP_DIVISOR;
3359 } else {
bf13e81b
JN		 3360 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3361
3362 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3363 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3364 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3365 }
3366
67a54566 3367 /* And finally store the new values in the power sequencer. */
f30d26e4
JN		 3368 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3369 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3370 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3371 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3372 /* Compute the divisor for the pp clock, simply match the Bspec
3373 * formula. */
453c5420 3374 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3375 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3376 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3377
3378 /* Haswell doesn't have any port selection bits for the panel
3379 * power sequencer any more. */
bc7d38a4 3380 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3381 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3382 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3383 else
3384 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3385 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3386 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3387 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3388 else
a24c144c 3389 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3390 }
3391
453c5420
JB		 3392 pp_on |= port_sel;
3393
3394 I915_WRITE(pp_on_reg, pp_on);
3395 I915_WRITE(pp_off_reg, pp_off);
3396 I915_WRITE(pp_div_reg, pp_div);
67a54566 3397
67a54566 3398 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3399 I915_READ(pp_on_reg),
3400 I915_READ(pp_off_reg),
3401 I915_READ(pp_div_reg));
f684960e
CW		 3402}
3403
ed92f0b2
PZ		 3404static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3405 struct intel_connector *intel_connector)
3406{
3407 struct drm_connector *connector = &intel_connector->base;
3408 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3409 struct drm_device *dev = intel_dig_port->base.base.dev;
3410 struct drm_i915_private *dev_priv = dev->dev_private;
3411 struct drm_display_mode *fixed_mode = NULL;
3412 struct edp_power_seq power_seq = { 0 };
3413 bool has_dpcd;
3414 struct drm_display_mode *scan;
3415 struct edid *edid;
3416
3417 if (!is_edp(intel_dp))
3418 return true;
3419
3420 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3421
3422 /* Cache DPCD and EDID for edp. */
3423 ironlake_edp_panel_vdd_on(intel_dp);
3424 has_dpcd = intel_dp_get_dpcd(intel_dp);
3425 ironlake_edp_panel_vdd_off(intel_dp, false);
3426
3427 if (has_dpcd) {
3428 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3429 dev_priv->no_aux_handshake =
3430 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3431 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3432 } else {
3433 /* if this fails, presume the device is a ghost */
3434 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3435 return false;
3436 }
3437
3438 /* We now know it's not a ghost, init power sequence regs. */
3439 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3440 &power_seq);
3441
3442 ironlake_edp_panel_vdd_on(intel_dp);
3443 edid = drm_get_edid(connector, &intel_dp->adapter);
3444 if (edid) {
3445 if (drm_add_edid_modes(connector, edid)) {
3446 drm_mode_connector_update_edid_property(connector,
3447 edid);
3448 drm_edid_to_eld(connector, edid);
3449 } else {
3450 kfree(edid);
3451 edid = ERR_PTR(-EINVAL);
3452 }
3453 } else {
3454 edid = ERR_PTR(-ENOENT);
3455 }
3456 intel_connector->edid = edid;
3457
3458 /* prefer fixed mode from EDID if available */
3459 list_for_each_entry(scan, &connector->probed_modes, head) {
3460 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3461 fixed_mode = drm_mode_duplicate(dev, scan);
3462 break;
3463 }
3464 }
3465
3466 /* fallback to VBT if available for eDP */
3467 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3468 fixed_mode = drm_mode_duplicate(dev,
3469 dev_priv->vbt.lfp_lvds_vbt_mode);
3470 if (fixed_mode)
3471 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3472 }
3473
3474 ironlake_edp_panel_vdd_off(intel_dp, false);
3475
3476 intel_panel_init(&intel_connector->panel, fixed_mode);
3477 intel_panel_setup_backlight(connector);
3478
3479 return true;
3480}
3481
16c25533 3482bool
f0fec3f2
PZ		 3483intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3484 struct intel_connector *intel_connector)
a4fc5ed6 3485{
f0fec3f2
PZ		 3486 struct drm_connector *connector = &intel_connector->base;
3487 struct intel_dp *intel_dp = &intel_dig_port->dp;
3488 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3489 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3490 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3491 enum port port = intel_dig_port->port;
5eb08b69 3492 const char *name = NULL;
b2a14755 3493 int type, error;
a4fc5ed6 3494
0767935e
DV		 3495 /* Preserve the current hw state. */
3496 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3497 intel_dp->attached_connector = intel_connector;
3d3dc149 3498
f7d24902 3499 type = DRM_MODE_CONNECTOR_DisplayPort;
19c03924
GB		 3500 /*
3501 * FIXME : We need to initialize built-in panels before external panels.
3502 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3503 */
f7d24902
ID		 3504 switch (port) {
3505 case PORT_A:
b329530c 3506 type = DRM_MODE_CONNECTOR_eDP;
f7d24902
ID		 3507 break;
3508 case PORT_C:
3509 if (IS_VALLEYVIEW(dev))
3510 type = DRM_MODE_CONNECTOR_eDP;
3511 break;
3512 case PORT_D:
3513 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3514 type = DRM_MODE_CONNECTOR_eDP;
3515 break;
3516 default: /* silence GCC warning */
3517 break;
b329530c
AJ		 3518 }
3519
f7d24902
ID		 3520 /*
3521 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3522 * for DP the encoder type can be set by the caller to
3523 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3524 */
3525 if (type == DRM_MODE_CONNECTOR_eDP)
3526 intel_encoder->type = INTEL_OUTPUT_EDP;
3527
e7281eab
ID		 3528 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3529 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3530 port_name(port));
3531
b329530c 3532 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3533 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3534
a4fc5ed6
KP		 3535 connector->interlace_allowed = true;
3536 connector->doublescan_allowed = 0;
3537
f0fec3f2
PZ		 3538 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3539 ironlake_panel_vdd_work);
a4fc5ed6 3540
df0e9248 3541 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3542 drm_sysfs_connector_add(connector);
3543
affa9354 3544 if (HAS_DDI(dev))
bcbc889b
PZ		 3545 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3546 else
3547 intel_connector->get_hw_state = intel_connector_get_hw_state;
3548
9ed35ab1
PZ		 3549 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3550 if (HAS_DDI(dev)) {
3551 switch (intel_dig_port->port) {
3552 case PORT_A:
3553 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3554 break;
3555 case PORT_B:
3556 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3557 break;
3558 case PORT_C:
3559 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3560 break;
3561 case PORT_D:
3562 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3563 break;
3564 default:
3565 BUG();
3566 }
3567 }
e8cb4558 3568
a4fc5ed6 3569 /* Set up the DDC bus. */
ab9d7c30
PZ		 3570 switch (port) {
3571 case PORT_A:
1d843f9d 3572 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3573 name = "DPDDC-A";
3574 break;
3575 case PORT_B:
1d843f9d 3576 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3577 name = "DPDDC-B";
3578 break;
3579 case PORT_C:
1d843f9d 3580 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3581 name = "DPDDC-C";
3582 break;
3583 case PORT_D:
1d843f9d 3584 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3585 name = "DPDDC-D";
3586 break;
3587 default:
ad1c0b19 3588 BUG();
5eb08b69
ZW		 3589 }
3590
b2a14755
PZ		 3591 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3592 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3593 error, port_name(port));
c1f05264 3594
2b28bb1b
RV		 3595 intel_dp->psr_setup_done = false;
3596
b2f246a8 3597 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
15b1d171
PZ		 3598 i2c_del_adapter(&intel_dp->adapter);
3599 if (is_edp(intel_dp)) {
3600 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3601 mutex_lock(&dev->mode_config.mutex);
3602 ironlake_panel_vdd_off_sync(intel_dp);
3603 mutex_unlock(&dev->mode_config.mutex);
3604 }
b2f246a8
PZ		 3605 drm_sysfs_connector_remove(connector);
3606 drm_connector_cleanup(connector);
16c25533 3607 return false;
b2f246a8 3608 }
32f9d658 3609
f684960e
CW		 3610 intel_dp_add_properties(intel_dp, connector);
3611
a4fc5ed6
KP		 3612 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3613 * 0xd. Failure to do so will result in spurious interrupts being
3614 * generated on the port when a cable is not attached.
3615 */
3616 if (IS_G4X(dev) && !IS_GM45(dev)) {
3617 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3618 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3619 }
16c25533
PZ		 3620
3621 return true;
a4fc5ed6 3622}
f0fec3f2
PZ		 3623
3624void
3625intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3626{
3627 struct intel_digital_port *intel_dig_port;
3628 struct intel_encoder *intel_encoder;
3629 struct drm_encoder *encoder;
3630 struct intel_connector *intel_connector;
3631
b14c5679 3632 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 3633 if (!intel_dig_port)
3634 return;
3635
b14c5679 3636 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 3637 if (!intel_connector) {
3638 kfree(intel_dig_port);
3639 return;
3640 }
3641
3642 intel_encoder = &intel_dig_port->base;
3643 encoder = &intel_encoder->base;
3644
3645 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3646 DRM_MODE_ENCODER_TMDS);
3647
5bfe2ac0 3648 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 3649 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70
PZ		 3650 intel_encoder->disable = intel_disable_dp;
3651 intel_encoder->post_disable = intel_post_disable_dp;
3652 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3653 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 3654 if (IS_VALLEYVIEW(dev)) {
ecff4f3b 3655 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 3656 intel_encoder->pre_enable = vlv_pre_enable_dp;
3657 intel_encoder->enable = vlv_enable_dp;
3658 } else {
ecff4f3b
JN		 3659 intel_encoder->pre_enable = g4x_pre_enable_dp;
3660 intel_encoder->enable = g4x_enable_dp;
ab1f90f9 3661 }
f0fec3f2 3662
174edf1f 3663 intel_dig_port->port = port;
f0fec3f2
PZ		 3664 intel_dig_port->dp.output_reg = output_reg;
3665
00c09d70 3666 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 3667 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3668 intel_encoder->cloneable = false;
3669 intel_encoder->hot_plug = intel_dp_hot_plug;
3670
15b1d171
PZ		 3671 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3672 drm_encoder_cleanup(encoder);
3673 kfree(intel_dig_port);
b2f246a8 3674 kfree(intel_connector);
15b1d171 3675 }
f0fec3f2 3676}
Linux kernel - Deliverables
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