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drm/i915: Modify DP set clock to accomodate more eDP timings v2
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
cfcb0fc9
JB		 60/**
61 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
62 * @intel_dp: DP struct
63 *
64 * If a CPU or PCH DP output is attached to an eDP panel, this function
65 * will return true, and false otherwise.
66 */
67static bool is_edp(struct intel_dp *intel_dp)
68{
da63a9f2
PZ		 69 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
70
71 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 72}
73
68b4d824 74static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 75{
68b4d824
ID		 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 79}
80
df0e9248
CW		 81static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
82{
fa90ecef 83 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 84}
85
ea5b213a 86static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 87
a4fc5ed6 88static int
ea5b213a 89intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 90{
7183dc29 91 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 92
93 switch (max_link_bw) {
94 case DP_LINK_BW_1_62:
95 case DP_LINK_BW_2_7:
96 break;
d4eead50
ID		 97 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
98 max_link_bw = DP_LINK_BW_2_7;
99 break;
a4fc5ed6 100 default:
d4eead50
ID		 101 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
102 max_link_bw);
a4fc5ed6
KP		 103 max_link_bw = DP_LINK_BW_1_62;
104 break;
105 }
106 return max_link_bw;
107}
108
cd9dde44
AJ		 109/*
110 * The units on the numbers in the next two are... bizarre. Examples will
111 * make it clearer; this one parallels an example in the eDP spec.
112 *
113 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
114 *
115 * 270000 * 1 * 8 / 10 == 216000
116 *
117 * The actual data capacity of that configuration is 2.16Gbit/s, so the
118 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
119 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
120 * 119000. At 18bpp that's 2142000 kilobits per second.
121 *
122 * Thus the strange-looking division by 10 in intel_dp_link_required, to
123 * get the result in decakilobits instead of kilobits.
124 */
125
a4fc5ed6 126static int
c898261c 127intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 128{
cd9dde44 129 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 130}
131
fe27d53e
DA		 132static int
133intel_dp_max_data_rate(int max_link_clock, int max_lanes)
134{
135 return (max_link_clock * max_lanes * 8) / 10;
136}
137
a4fc5ed6
KP		 138static int
139intel_dp_mode_valid(struct drm_connector *connector,
140 struct drm_display_mode *mode)
141{
df0e9248 142 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 143 struct intel_connector *intel_connector = to_intel_connector(connector);
144 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 145 int target_clock = mode->clock;
146 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 147
dd06f90e
JN		 148 if (is_edp(intel_dp) && fixed_mode) {
149 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 150 return MODE_PANEL;
151
dd06f90e 152 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 153 return MODE_PANEL;
03afc4a2
DV		 154
155 target_clock = fixed_mode->clock;
7de56f43
ZY		 156 }
157
36008365
DV		 158 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
159 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
160
161 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
162 mode_rate = intel_dp_link_required(target_clock, 18);
163
164 if (mode_rate > max_rate)
c4867936 165 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 166
167 if (mode->clock < 10000)
168 return MODE_CLOCK_LOW;
169
0af78a2b
DV		 170 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
171 return MODE_H_ILLEGAL;
172
a4fc5ed6
KP		 173 return MODE_OK;
174}
175
176static uint32_t
177pack_aux(uint8_t *src, int src_bytes)
178{
179 int i;
180 uint32_t v = 0;
181
182 if (src_bytes > 4)
183 src_bytes = 4;
184 for (i = 0; i < src_bytes; i++)
185 v |= ((uint32_t) src[i]) << ((3-i) * 8);
186 return v;
187}
188
189static void
190unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
191{
192 int i;
193 if (dst_bytes > 4)
194 dst_bytes = 4;
195 for (i = 0; i < dst_bytes; i++)
196 dst[i] = src >> ((3-i) * 8);
197}
198
fb0f8fbf
KP		 199/* hrawclock is 1/4 the FSB frequency */
200static int
201intel_hrawclk(struct drm_device *dev)
202{
203 struct drm_i915_private *dev_priv = dev->dev_private;
204 uint32_t clkcfg;
205
9473c8f4
VP		 206 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
207 if (IS_VALLEYVIEW(dev))
208 return 200;
209
fb0f8fbf
KP		 210 clkcfg = I915_READ(CLKCFG);
211 switch (clkcfg & CLKCFG_FSB_MASK) {
212 case CLKCFG_FSB_400:
213 return 100;
214 case CLKCFG_FSB_533:
215 return 133;
216 case CLKCFG_FSB_667:
217 return 166;
218 case CLKCFG_FSB_800:
219 return 200;
220 case CLKCFG_FSB_1067:
221 return 266;
222 case CLKCFG_FSB_1333:
223 return 333;
224 /* these two are just a guess; one of them might be right */
225 case CLKCFG_FSB_1600:
226 case CLKCFG_FSB_1600_ALT:
227 return 400;
228 default:
229 return 133;
230 }
231}
232
ebf33b18
KP		 233static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
234{
30add22d 235 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 236 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 237 u32 pp_stat_reg;
ebf33b18 238
453c5420
JB		 239 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
240 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
ebf33b18
KP		 241}
242
243static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
244{
30add22d 245 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 246 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 247 u32 pp_ctrl_reg;
ebf33b18 248
453c5420
JB		 249 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
250 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 251}
252
9b984dae
KP		 253static void
254intel_dp_check_edp(struct intel_dp *intel_dp)
255{
30add22d 256 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 257 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 258 u32 pp_stat_reg, pp_ctrl_reg;
ebf33b18 259
9b984dae
KP		 260 if (!is_edp(intel_dp))
261 return;
453c5420
JB		 262
263 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
264 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
265
ebf33b18 266 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 267 WARN(1, "eDP powered off while attempting aux channel communication.\n");
268 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
453c5420
JB		 269 I915_READ(pp_stat_reg),
270 I915_READ(pp_ctrl_reg));
9b984dae
KP		 271 }
272}
273
9ee32fea
DV		 274static uint32_t
275intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
276{
277 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
278 struct drm_device *dev = intel_dig_port->base.base.dev;
279 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 280 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 281 uint32_t status;
282 bool done;
283
ef04f00d 284#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 285 if (has_aux_irq)
b18ac466 286 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 287 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 288 else
289 done = wait_for_atomic(C, 10) == 0;
290 if (!done)
291 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
292 has_aux_irq);
293#undef C
294
295 return status;
296}
297
bc86625a
CW		 298static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
299 int index)
a4fc5ed6 300{
174edf1f
PZ		 301 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
302 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 303 struct drm_i915_private *dev_priv = dev->dev_private;
9ee32fea 304
a4fc5ed6 305 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 306 * and would like to run at 2MHz. So, take the
307 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 308 *
309 * Note that PCH attached eDP panels should use a 125MHz input
310 * clock divider.
a4fc5ed6 311 */
a62d0834 312 if (IS_VALLEYVIEW(dev)) {
bc86625a 313 return index ? 0 : 100;
a62d0834 314 } else if (intel_dig_port->port == PORT_A) {
bc86625a
CW		 315 if (index)
316 return 0;
affa9354 317 if (HAS_DDI(dev))
bc86625a 318 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
9473c8f4 319 else if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 320 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 321 else
b84a1cf8 322 return 225; /* eDP input clock at 450Mhz */
2c55c336
JN		 323 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
324 /* Workaround for non-ULT HSW */
bc86625a
CW		 325 switch (index) {
326 case 0: return 63;
327 case 1: return 72;
328 default: return 0;
329 }
2c55c336 330 } else if (HAS_PCH_SPLIT(dev)) {
bc86625a 331 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 332 } else {
bc86625a 333 return index ? 0 :intel_hrawclk(dev) / 2;
2c55c336 334 }
b84a1cf8
RV		 335}
336
337static int
338intel_dp_aux_ch(struct intel_dp *intel_dp,
339 uint8_t *send, int send_bytes,
340 uint8_t *recv, int recv_size)
341{
342 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
343 struct drm_device *dev = intel_dig_port->base.base.dev;
344 struct drm_i915_private *dev_priv = dev->dev_private;
345 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
346 uint32_t ch_data = ch_ctl + 4;
bc86625a 347 uint32_t aux_clock_divider;
b84a1cf8
RV		 348 int i, ret, recv_bytes;
349 uint32_t status;
bc86625a 350 int try, precharge, clock = 0;
b84a1cf8
RV		 351 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
352
353 /* dp aux is extremely sensitive to irq latency, hence request the
354 * lowest possible wakeup latency and so prevent the cpu from going into
355 * deep sleep states.
356 */
357 pm_qos_update_request(&dev_priv->pm_qos, 0);
358
359 intel_dp_check_edp(intel_dp);
5eb08b69 360
6b4e0a93
DV		 361 if (IS_GEN6(dev))
362 precharge = 3;
363 else
364 precharge = 5;
365
c67a470b
PZ		 366 intel_aux_display_runtime_get(dev_priv);
367
11bee43e
JB		 368 /* Try to wait for any previous AUX channel activity */
369 for (try = 0; try < 3; try++) {
ef04f00d 370 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 371 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
372 break;
373 msleep(1);
374 }
375
376 if (try == 3) {
377 WARN(1, "dp_aux_ch not started status 0x%08x\n",
378 I915_READ(ch_ctl));
9ee32fea
DV		 379 ret = -EBUSY;
380 goto out;
4f7f7b7e
CW		 381 }
382
bc86625a
CW		 383 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
384 /* Must try at least 3 times according to DP spec */
385 for (try = 0; try < 5; try++) {
386 /* Load the send data into the aux channel data registers */
387 for (i = 0; i < send_bytes; i += 4)
388 I915_WRITE(ch_data + i,
389 pack_aux(send + i, send_bytes - i));
390
391 /* Send the command and wait for it to complete */
392 I915_WRITE(ch_ctl,
393 DP_AUX_CH_CTL_SEND_BUSY |
394 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
395 DP_AUX_CH_CTL_TIME_OUT_400us |
396 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
397 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
398 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
399 DP_AUX_CH_CTL_DONE |
400 DP_AUX_CH_CTL_TIME_OUT_ERROR |
401 DP_AUX_CH_CTL_RECEIVE_ERROR);
402
403 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
404
405 /* Clear done status and any errors */
406 I915_WRITE(ch_ctl,
407 status |
408 DP_AUX_CH_CTL_DONE |
409 DP_AUX_CH_CTL_TIME_OUT_ERROR |
410 DP_AUX_CH_CTL_RECEIVE_ERROR);
411
412 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
413 DP_AUX_CH_CTL_RECEIVE_ERROR))
414 continue;
415 if (status & DP_AUX_CH_CTL_DONE)
416 break;
417 }
4f7f7b7e 418 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 419 break;
420 }
421
a4fc5ed6 422 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 423 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 424 ret = -EBUSY;
425 goto out;
a4fc5ed6
KP		 426 }
427
428 /* Check for timeout or receive error.
429 * Timeouts occur when the sink is not connected
430 */
a5b3da54 431 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 432 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 433 ret = -EIO;
434 goto out;
a5b3da54 435 }
1ae8c0a5
KP		 436
437 /* Timeouts occur when the device isn't connected, so they're
438 * "normal" -- don't fill the kernel log with these */
a5b3da54 439 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 440 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 441 ret = -ETIMEDOUT;
442 goto out;
a4fc5ed6
KP		 443 }
444
445 /* Unload any bytes sent back from the other side */
446 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
447 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 448 if (recv_bytes > recv_size)
449 recv_bytes = recv_size;
0206e353 450
4f7f7b7e
CW		 451 for (i = 0; i < recv_bytes; i += 4)
452 unpack_aux(I915_READ(ch_data + i),
453 recv + i, recv_bytes - i);
a4fc5ed6 454
9ee32fea
DV		 455 ret = recv_bytes;
456out:
457 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 458 intel_aux_display_runtime_put(dev_priv);
9ee32fea
DV		 459
460 return ret;
a4fc5ed6
KP		 461}
462
463/* Write data to the aux channel in native mode */
464static int
ea5b213a 465intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 466 uint16_t address, uint8_t *send, int send_bytes)
467{
468 int ret;
469 uint8_t msg[20];
470 int msg_bytes;
471 uint8_t ack;
472
9b984dae 473 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 474 if (send_bytes > 16)
475 return -1;
476 msg[0] = AUX_NATIVE_WRITE << 4;
477 msg[1] = address >> 8;
eebc863e 478 msg[2] = address & 0xff;
a4fc5ed6
KP		 479 msg[3] = send_bytes - 1;
480 memcpy(&msg[4], send, send_bytes);
481 msg_bytes = send_bytes + 4;
482 for (;;) {
ea5b213a 483 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 484 if (ret < 0)
485 return ret;
486 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
487 break;
488 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
489 udelay(100);
490 else
a5b3da54 491 return -EIO;
a4fc5ed6
KP		 492 }
493 return send_bytes;
494}
495
496/* Write a single byte to the aux channel in native mode */
497static int
ea5b213a 498intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 499 uint16_t address, uint8_t byte)
500{
ea5b213a 501 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 502}
503
504/* read bytes from a native aux channel */
505static int
ea5b213a 506intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 507 uint16_t address, uint8_t *recv, int recv_bytes)
508{
509 uint8_t msg[4];
510 int msg_bytes;
511 uint8_t reply[20];
512 int reply_bytes;
513 uint8_t ack;
514 int ret;
515
9b984dae 516 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 517 msg[0] = AUX_NATIVE_READ << 4;
518 msg[1] = address >> 8;
519 msg[2] = address & 0xff;
520 msg[3] = recv_bytes - 1;
521
522 msg_bytes = 4;
523 reply_bytes = recv_bytes + 1;
524
525 for (;;) {
ea5b213a 526 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 527 reply, reply_bytes);
a5b3da54
KP		 528 if (ret == 0)
529 return -EPROTO;
530 if (ret < 0)
a4fc5ed6
KP		 531 return ret;
532 ack = reply[0];
533 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
534 memcpy(recv, reply + 1, ret - 1);
535 return ret - 1;
536 }
537 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
538 udelay(100);
539 else
a5b3da54 540 return -EIO;
a4fc5ed6
KP		 541 }
542}
543
544static int
ab2c0672
DA		 545intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
546 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 547{
ab2c0672 548 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 549 struct intel_dp *intel_dp = container_of(adapter,
550 struct intel_dp,
551 adapter);
ab2c0672
DA		 552 uint16_t address = algo_data->address;
553 uint8_t msg[5];
554 uint8_t reply[2];
8316f337 555 unsigned retry;
ab2c0672
DA		 556 int msg_bytes;
557 int reply_bytes;
558 int ret;
559
9b984dae 560 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 561 /* Set up the command byte */
562 if (mode & MODE_I2C_READ)
563 msg[0] = AUX_I2C_READ << 4;
564 else
565 msg[0] = AUX_I2C_WRITE << 4;
566
567 if (!(mode & MODE_I2C_STOP))
568 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 569
ab2c0672
DA		 570 msg[1] = address >> 8;
571 msg[2] = address;
572
573 switch (mode) {
574 case MODE_I2C_WRITE:
575 msg[3] = 0;
576 msg[4] = write_byte;
577 msg_bytes = 5;
578 reply_bytes = 1;
579 break;
580 case MODE_I2C_READ:
581 msg[3] = 0;
582 msg_bytes = 4;
583 reply_bytes = 2;
584 break;
585 default:
586 msg_bytes = 3;
587 reply_bytes = 1;
588 break;
589 }
590
8316f337
DF		 591 for (retry = 0; retry < 5; retry++) {
592 ret = intel_dp_aux_ch(intel_dp,
593 msg, msg_bytes,
594 reply, reply_bytes);
ab2c0672 595 if (ret < 0) {
3ff99164 596 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 597 return ret;
598 }
8316f337
DF		 599
600 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
601 case AUX_NATIVE_REPLY_ACK:
602 /* I2C-over-AUX Reply field is only valid
603 * when paired with AUX ACK.
604 */
605 break;
606 case AUX_NATIVE_REPLY_NACK:
607 DRM_DEBUG_KMS("aux_ch native nack\n");
608 return -EREMOTEIO;
609 case AUX_NATIVE_REPLY_DEFER:
610 udelay(100);
611 continue;
612 default:
613 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
614 reply[0]);
615 return -EREMOTEIO;
616 }
617
ab2c0672
DA		 618 switch (reply[0] & AUX_I2C_REPLY_MASK) {
619 case AUX_I2C_REPLY_ACK:
620 if (mode == MODE_I2C_READ) {
621 *read_byte = reply[1];
622 }
623 return reply_bytes - 1;
624 case AUX_I2C_REPLY_NACK:
8316f337 625 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 626 return -EREMOTEIO;
627 case AUX_I2C_REPLY_DEFER:
8316f337 628 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 629 udelay(100);
630 break;
631 default:
8316f337 632 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 633 return -EREMOTEIO;
634 }
635 }
8316f337
DF		 636
637 DRM_ERROR("too many retries, giving up\n");
638 return -EREMOTEIO;
a4fc5ed6
KP		 639}
640
641static int
ea5b213a 642intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 643 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 644{
0b5c541b
KP		 645 int ret;
646
d54e9d28 647 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 648 intel_dp->algo.running = false;
649 intel_dp->algo.address = 0;
650 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
651
0206e353 652 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 653 intel_dp->adapter.owner = THIS_MODULE;
654 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 655 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 656 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
657 intel_dp->adapter.algo_data = &intel_dp->algo;
658 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
659
0b5c541b
KP		 660 ironlake_edp_panel_vdd_on(intel_dp);
661 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 662 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 663 return ret;
a4fc5ed6
KP		 664}
665
c6bb3538
DV		 666static void
667intel_dp_set_clock(struct intel_encoder *encoder,
668 struct intel_crtc_config *pipe_config, int link_bw)
669{
670 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 671 const struct dp_link_dpll *divisor = NULL;
672 int i, count = 0;
c6bb3538
DV		 673
674 if (IS_G4X(dev)) {
9dd4ffdf
CML		 675 divisor = gen4_dpll;
676 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 677 } else if (IS_HASWELL(dev)) {
678 /* Haswell has special-purpose DP DDI clocks. */
679 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 680 divisor = pch_dpll;
681 count = ARRAY_SIZE(pch_dpll);
c6bb3538
DV		 682 } else if (IS_VALLEYVIEW(dev)) {
683 /* FIXME: Need to figure out optimized DP clocks for vlv. */
684 }
9dd4ffdf
CML		 685
686 if (divisor && count) {
687 for (i = 0; i < count; i++) {
688 if (link_bw == divisor[i].link_bw) {
689 pipe_config->dpll = divisor[i].dpll;
690 pipe_config->clock_set = true;
691 break;
692 }
693 }
694 }
c6bb3538
DV		 695}
696
00c09d70 697bool
5bfe2ac0
DV		 698intel_dp_compute_config(struct intel_encoder *encoder,
699 struct intel_crtc_config *pipe_config)
a4fc5ed6 700{
5bfe2ac0 701 struct drm_device *dev = encoder->base.dev;
36008365 702 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 703 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 704 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 705 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 706 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 707 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 708 int lane_count, clock;
397fe157 709 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 710 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 711 int bpp, mode_rate;
a4fc5ed6 712 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
ff9a6750 713 int link_avail, link_clock;
a4fc5ed6 714
bc7d38a4 715 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 716 pipe_config->has_pch_encoder = true;
717
03afc4a2 718 pipe_config->has_dp_encoder = true;
a4fc5ed6 719
dd06f90e
JN		 720 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
721 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
722 adjusted_mode);
2dd24552
JB		 723 if (!HAS_PCH_SPLIT(dev))
724 intel_gmch_panel_fitting(intel_crtc, pipe_config,
725 intel_connector->panel.fitting_mode);
726 else
b074cec8
JB		 727 intel_pch_panel_fitting(intel_crtc, pipe_config,
728 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 729 }
730
cb1793ce 731 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 732 return false;
733
083f9560
DV		 734 DRM_DEBUG_KMS("DP link computation with max lane count %i "
735 "max bw %02x pixel clock %iKHz\n",
71244653 736 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 737
36008365
DV		 738 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
739 * bpc in between. */
3e7ca985 740 bpp = pipe_config->pipe_bpp;
7984211e
ID		 741 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) {
742 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
743 dev_priv->vbt.edp_bpp);
e1b73cba 744 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
7984211e 745 }
657445fe 746
36008365 747 for (; bpp >= 6*3; bpp -= 2*3) {
ff9a6750 748 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
36008365
DV		 749
750 for (clock = 0; clock <= max_clock; clock++) {
751 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
752 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
753 link_avail = intel_dp_max_data_rate(link_clock,
754 lane_count);
755
756 if (mode_rate <= link_avail) {
757 goto found;
758 }
759 }
760 }
761 }
c4867936 762
36008365 763 return false;
3685a8f3 764
36008365 765found:
55bc60db
VS		 766 if (intel_dp->color_range_auto) {
767 /*
768 * See:
769 * CEA-861-E - 5.1 Default Encoding Parameters
770 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
771 */
18316c8c 772 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 773 intel_dp->color_range = DP_COLOR_RANGE_16_235;
774 else
775 intel_dp->color_range = 0;
776 }
777
3685a8f3 778 if (intel_dp->color_range)
50f3b016 779 pipe_config->limited_color_range = true;
a4fc5ed6 780
36008365
DV		 781 intel_dp->link_bw = bws[clock];
782 intel_dp->lane_count = lane_count;
657445fe 783 pipe_config->pipe_bpp = bpp;
ff9a6750 784 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 785
36008365
DV		 786 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
787 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 788 pipe_config->port_clock, bpp);
36008365
DV		 789 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
790 mode_rate, link_avail);
a4fc5ed6 791
03afc4a2 792 intel_link_compute_m_n(bpp, lane_count,
ff9a6750 793 adjusted_mode->clock, pipe_config->port_clock,
03afc4a2 794 &pipe_config->dp_m_n);
9d1a455b 795
c6bb3538
DV		 796 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
797
03afc4a2 798 return true;
a4fc5ed6
KP		 799}
800
247d89f6
PZ		 801void intel_dp_init_link_config(struct intel_dp *intel_dp)
802{
803 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
804 intel_dp->link_configuration[0] = intel_dp->link_bw;
805 intel_dp->link_configuration[1] = intel_dp->lane_count;
806 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
807 /*
808 * Check for DPCD version > 1.1 and enhanced framing support
809 */
810 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
811 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
812 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
813 }
814}
815
7c62a164 816static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 817{
7c62a164
DV		 818 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
819 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
820 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 821 struct drm_i915_private *dev_priv = dev->dev_private;
822 u32 dpa_ctl;
823
ff9a6750 824 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 825 dpa_ctl = I915_READ(DP_A);
826 dpa_ctl &= ~DP_PLL_FREQ_MASK;
827
ff9a6750 828 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 829 /* For a long time we've carried around a ILK-DevA w/a for the
830 * 160MHz clock. If we're really unlucky, it's still required.
831 */
832 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 833 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 834 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 835 } else {
836 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 837 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 838 }
1ce17038 839
ea9b6006
DV		 840 I915_WRITE(DP_A, dpa_ctl);
841
842 POSTING_READ(DP_A);
843 udelay(500);
844}
845
b934223d 846static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 847{
b934223d 848 struct drm_device *dev = encoder->base.dev;
417e822d 849 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 850 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 851 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 852 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
853 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 854
417e822d 855 /*
1a2eb460 856 * There are four kinds of DP registers:
417e822d
KP		 857 *
858 * IBX PCH
1a2eb460
KP		 859 * SNB CPU
860 * IVB CPU
417e822d
KP		 861 * CPT PCH
862 *
863 * IBX PCH and CPU are the same for almost everything,
864 * except that the CPU DP PLL is configured in this
865 * register
866 *
867 * CPT PCH is quite different, having many bits moved
868 * to the TRANS_DP_CTL register instead. That
869 * configuration happens (oddly) in ironlake_pch_enable
870 */
9c9e7927 871
417e822d
KP		 872 /* Preserve the BIOS-computed detected bit. This is
873 * supposed to be read-only.
874 */
875 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 876
417e822d 877 /* Handle DP bits in common between all three register formats */
417e822d 878 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 879 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 880
e0dac65e
WF		 881 if (intel_dp->has_audio) {
882 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 883 pipe_name(crtc->pipe));
ea5b213a 884 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 885 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 886 }
247d89f6
PZ		 887
888 intel_dp_init_link_config(intel_dp);
a4fc5ed6 889
417e822d 890 /* Split out the IBX/CPU vs CPT settings */
32f9d658 891
bc7d38a4 892 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 893 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
894 intel_dp->DP |= DP_SYNC_HS_HIGH;
895 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
896 intel_dp->DP |= DP_SYNC_VS_HIGH;
897 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
898
899 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
900 intel_dp->DP |= DP_ENHANCED_FRAMING;
901
7c62a164 902 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 903 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 904 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 905 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 906
907 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
908 intel_dp->DP |= DP_SYNC_HS_HIGH;
909 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
910 intel_dp->DP |= DP_SYNC_VS_HIGH;
911 intel_dp->DP |= DP_LINK_TRAIN_OFF;
912
913 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
914 intel_dp->DP |= DP_ENHANCED_FRAMING;
915
7c62a164 916 if (crtc->pipe == 1)
417e822d 917 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 918 } else {
919 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 920 }
ea9b6006 921
bc7d38a4 922 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 923 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 924}
925
99ea7127
KP		 926#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
927#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
928
929#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
930#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
931
932#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
933#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
934
935static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
936 u32 mask,
937 u32 value)
bd943159 938{
30add22d 939 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 940 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 941 u32 pp_stat_reg, pp_ctrl_reg;
942
943 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
944 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
32ce697c 945
99ea7127 946 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 947 mask, value,
948 I915_READ(pp_stat_reg),
949 I915_READ(pp_ctrl_reg));
32ce697c 950
453c5420 951 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 952 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 953 I915_READ(pp_stat_reg),
954 I915_READ(pp_ctrl_reg));
32ce697c 955 }
99ea7127 956}
32ce697c 957
99ea7127
KP		 958static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
959{
960 DRM_DEBUG_KMS("Wait for panel power on\n");
961 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 962}
963
99ea7127
KP		 964static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
965{
966 DRM_DEBUG_KMS("Wait for panel power off time\n");
967 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
968}
969
970static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
971{
972 DRM_DEBUG_KMS("Wait for panel power cycle\n");
973 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
974}
975
976
832dd3c1
KP		 977/* Read the current pp_control value, unlocking the register if it
978 * is locked
979 */
980
453c5420 981static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 982{
453c5420
JB		 983 struct drm_device *dev = intel_dp_to_dev(intel_dp);
984 struct drm_i915_private *dev_priv = dev->dev_private;
985 u32 control;
986 u32 pp_ctrl_reg;
987
988 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
989 control = I915_READ(pp_ctrl_reg);
832dd3c1
KP		 990
991 control &= ~PANEL_UNLOCK_MASK;
992 control |= PANEL_UNLOCK_REGS;
993 return control;
bd943159
KP		 994}
995
82a4d9c0 996void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 997{
30add22d 998 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 999 struct drm_i915_private *dev_priv = dev->dev_private;
1000 u32 pp;
453c5420 1001 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1002
97af61f5
KP		 1003 if (!is_edp(intel_dp))
1004 return;
f01eca2e 1005 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1006
bd943159
KP		 1007 WARN(intel_dp->want_panel_vdd,
1008 "eDP VDD already requested on\n");
1009
1010 intel_dp->want_panel_vdd = true;
99ea7127 1011
bd943159
KP		 1012 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1013 DRM_DEBUG_KMS("eDP VDD already on\n");
1014 return;
1015 }
1016
99ea7127
KP		 1017 if (!ironlake_edp_have_panel_power(intel_dp))
1018 ironlake_wait_panel_power_cycle(intel_dp);
1019
453c5420 1020 pp = ironlake_get_pp_control(intel_dp);
5d613501 1021 pp |= EDP_FORCE_VDD;
ebf33b18 1022
453c5420
JB		 1023 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1024 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1025
1026 I915_WRITE(pp_ctrl_reg, pp);
1027 POSTING_READ(pp_ctrl_reg);
1028 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1029 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1030 /*
1031 * If the panel wasn't on, delay before accessing aux channel
1032 */
1033 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1034 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1035 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1036 }
5d613501
JB		 1037}
1038
bd943159 1039static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1040{
30add22d 1041 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1042 struct drm_i915_private *dev_priv = dev->dev_private;
1043 u32 pp;
453c5420 1044 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1045
a0e99e68
DV		 1046 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1047
bd943159 1048 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
453c5420 1049 pp = ironlake_get_pp_control(intel_dp);
bd943159 1050 pp &= ~EDP_FORCE_VDD;
bd943159 1051
453c5420
JB		 1052 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1053 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1054
1055 I915_WRITE(pp_ctrl_reg, pp);
1056 POSTING_READ(pp_ctrl_reg);
99ea7127 1057
453c5420
JB		 1058 /* Make sure sequencer is idle before allowing subsequent activity */
1059 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1060 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
99ea7127 1061 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1062 }
1063}
5d613501 1064
bd943159
KP		 1065static void ironlake_panel_vdd_work(struct work_struct *__work)
1066{
1067 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1068 struct intel_dp, panel_vdd_work);
30add22d 1069 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1070
627f7675 1071 mutex_lock(&dev->mode_config.mutex);
bd943159 1072 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1073 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1074}
1075
82a4d9c0 1076void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1077{
97af61f5
KP		 1078 if (!is_edp(intel_dp))
1079 return;
5d613501 1080
bd943159
KP		 1081 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1082 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1083
bd943159
KP		 1084 intel_dp->want_panel_vdd = false;
1085
1086 if (sync) {
1087 ironlake_panel_vdd_off_sync(intel_dp);
1088 } else {
1089 /*
1090 * Queue the timer to fire a long
1091 * time from now (relative to the power down delay)
1092 * to keep the panel power up across a sequence of operations
1093 */
1094 schedule_delayed_work(&intel_dp->panel_vdd_work,
1095 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1096 }
5d613501
JB		 1097}
1098
82a4d9c0 1099void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1100{
30add22d 1101 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1102 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1103 u32 pp;
453c5420 1104 u32 pp_ctrl_reg;
9934c132 1105
97af61f5 1106 if (!is_edp(intel_dp))
bd943159 1107 return;
99ea7127
KP		 1108
1109 DRM_DEBUG_KMS("Turn eDP power on\n");
1110
1111 if (ironlake_edp_have_panel_power(intel_dp)) {
1112 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1113 return;
99ea7127 1114 }
9934c132 1115
99ea7127 1116 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1117
453c5420 1118 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1119 if (IS_GEN5(dev)) {
1120 /* ILK workaround: disable reset around power sequence */
1121 pp &= ~PANEL_POWER_RESET;
1122 I915_WRITE(PCH_PP_CONTROL, pp);
1123 POSTING_READ(PCH_PP_CONTROL);
1124 }
37c6c9b0 1125
1c0ae80a 1126 pp |= POWER_TARGET_ON;
99ea7127
KP		 1127 if (!IS_GEN5(dev))
1128 pp |= PANEL_POWER_RESET;
1129
453c5420
JB		 1130 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1131
1132 I915_WRITE(pp_ctrl_reg, pp);
1133 POSTING_READ(pp_ctrl_reg);
9934c132 1134
99ea7127 1135 ironlake_wait_panel_on(intel_dp);
9934c132 1136
05ce1a49
KP		 1137 if (IS_GEN5(dev)) {
1138 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1139 I915_WRITE(PCH_PP_CONTROL, pp);
1140 POSTING_READ(PCH_PP_CONTROL);
1141 }
9934c132
JB		 1142}
1143
82a4d9c0 1144void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1145{
30add22d 1146 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1147 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1148 u32 pp;
453c5420 1149 u32 pp_ctrl_reg;
9934c132 1150
97af61f5
KP		 1151 if (!is_edp(intel_dp))
1152 return;
37c6c9b0 1153
99ea7127 1154 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1155
6cb49835 1156 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1157
453c5420 1158 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1159 /* We need to switch off panel power _and_ force vdd, for otherwise some
1160 * panels get very unhappy and cease to work. */
1161 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
453c5420
JB		 1162
1163 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1164
1165 I915_WRITE(pp_ctrl_reg, pp);
1166 POSTING_READ(pp_ctrl_reg);
9934c132 1167
35a38556
DV		 1168 intel_dp->want_panel_vdd = false;
1169
99ea7127 1170 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1171}
1172
d6c50ff8 1173void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1174{
da63a9f2
PZ		 1175 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1176 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1177 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1178 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658 1179 u32 pp;
453c5420 1180 u32 pp_ctrl_reg;
32f9d658 1181
f01eca2e
KP		 1182 if (!is_edp(intel_dp))
1183 return;
1184
28c97730 1185 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1186 /*
1187 * If we enable the backlight right away following a panel power
1188 * on, we may see slight flicker as the panel syncs with the eDP
1189 * link. So delay a bit to make sure the image is solid before
1190 * allowing it to appear.
1191 */
f01eca2e 1192 msleep(intel_dp->backlight_on_delay);
453c5420 1193 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1194 pp |= EDP_BLC_ENABLE;
453c5420
JB		 1195
1196 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1197
1198 I915_WRITE(pp_ctrl_reg, pp);
1199 POSTING_READ(pp_ctrl_reg);
035aa3de
DV		 1200
1201 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1202}
1203
d6c50ff8 1204void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1205{
30add22d 1206 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1207 struct drm_i915_private *dev_priv = dev->dev_private;
1208 u32 pp;
453c5420 1209 u32 pp_ctrl_reg;
32f9d658 1210
f01eca2e
KP		 1211 if (!is_edp(intel_dp))
1212 return;
1213
035aa3de
DV		 1214 intel_panel_disable_backlight(dev);
1215
28c97730 1216 DRM_DEBUG_KMS("\n");
453c5420 1217 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1218 pp &= ~EDP_BLC_ENABLE;
453c5420
JB		 1219
1220 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1221
1222 I915_WRITE(pp_ctrl_reg, pp);
1223 POSTING_READ(pp_ctrl_reg);
f01eca2e 1224 msleep(intel_dp->backlight_off_delay);
32f9d658 1225}
a4fc5ed6 1226
2bd2ad64 1227static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1228{
da63a9f2
PZ		 1229 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1230 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1231 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1232 struct drm_i915_private *dev_priv = dev->dev_private;
1233 u32 dpa_ctl;
1234
2bd2ad64
DV		 1235 assert_pipe_disabled(dev_priv,
1236 to_intel_crtc(crtc)->pipe);
1237
d240f20f
JB		 1238 DRM_DEBUG_KMS("\n");
1239 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1240 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1241 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1242
1243 /* We don't adjust intel_dp->DP while tearing down the link, to
1244 * facilitate link retraining (e.g. after hotplug). Hence clear all
1245 * enable bits here to ensure that we don't enable too much. */
1246 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1247 intel_dp->DP |= DP_PLL_ENABLE;
1248 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1249 POSTING_READ(DP_A);
1250 udelay(200);
d240f20f
JB		 1251}
1252
2bd2ad64 1253static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1254{
da63a9f2
PZ		 1255 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1256 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1257 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1258 struct drm_i915_private *dev_priv = dev->dev_private;
1259 u32 dpa_ctl;
1260
2bd2ad64
DV		 1261 assert_pipe_disabled(dev_priv,
1262 to_intel_crtc(crtc)->pipe);
1263
d240f20f 1264 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1265 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1266 "dp pll off, should be on\n");
1267 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1268
1269 /* We can't rely on the value tracked for the DP register in
1270 * intel_dp->DP because link_down must not change that (otherwise link
1271 * re-training will fail. */
298b0b39 1272 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1273 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1274 POSTING_READ(DP_A);
d240f20f
JB		 1275 udelay(200);
1276}
1277
c7ad3810 1278/* If the sink supports it, try to set the power state appropriately */
c19b0669 1279void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1280{
1281 int ret, i;
1282
1283 /* Should have a valid DPCD by this point */
1284 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1285 return;
1286
1287 if (mode != DRM_MODE_DPMS_ON) {
1288 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1289 DP_SET_POWER_D3);
1290 if (ret != 1)
1291 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1292 } else {
1293 /*
1294 * When turning on, we need to retry for 1ms to give the sink
1295 * time to wake up.
1296 */
1297 for (i = 0; i < 3; i++) {
1298 ret = intel_dp_aux_native_write_1(intel_dp,
1299 DP_SET_POWER,
1300 DP_SET_POWER_D0);
1301 if (ret == 1)
1302 break;
1303 msleep(1);
1304 }
1305 }
1306}
1307
19d8fe15
DV		 1308static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1309 enum pipe *pipe)
d240f20f 1310{
19d8fe15 1311 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1312 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1313 struct drm_device *dev = encoder->base.dev;
1314 struct drm_i915_private *dev_priv = dev->dev_private;
1315 u32 tmp = I915_READ(intel_dp->output_reg);
1316
1317 if (!(tmp & DP_PORT_EN))
1318 return false;
1319
bc7d38a4 1320 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1321 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1322 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1323 *pipe = PORT_TO_PIPE(tmp);
1324 } else {
1325 u32 trans_sel;
1326 u32 trans_dp;
1327 int i;
1328
1329 switch (intel_dp->output_reg) {
1330 case PCH_DP_B:
1331 trans_sel = TRANS_DP_PORT_SEL_B;
1332 break;
1333 case PCH_DP_C:
1334 trans_sel = TRANS_DP_PORT_SEL_C;
1335 break;
1336 case PCH_DP_D:
1337 trans_sel = TRANS_DP_PORT_SEL_D;
1338 break;
1339 default:
1340 return true;
1341 }
1342
1343 for_each_pipe(i) {
1344 trans_dp = I915_READ(TRANS_DP_CTL(i));
1345 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1346 *pipe = i;
1347 return true;
1348 }
1349 }
19d8fe15 1350
4a0833ec
DV		 1351 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1352 intel_dp->output_reg);
1353 }
d240f20f 1354
19d8fe15
DV		 1355 return true;
1356}
d240f20f 1357
045ac3b5
JB		 1358static void intel_dp_get_config(struct intel_encoder *encoder,
1359 struct intel_crtc_config *pipe_config)
1360{
1361 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1362 u32 tmp, flags = 0;
63000ef6
XZ		 1363 struct drm_device *dev = encoder->base.dev;
1364 struct drm_i915_private *dev_priv = dev->dev_private;
1365 enum port port = dp_to_dig_port(intel_dp)->port;
1366 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
045ac3b5 1367
63000ef6
XZ		 1368 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1369 tmp = I915_READ(intel_dp->output_reg);
1370 if (tmp & DP_SYNC_HS_HIGH)
1371 flags |= DRM_MODE_FLAG_PHSYNC;
1372 else
1373 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1374
63000ef6
XZ		 1375 if (tmp & DP_SYNC_VS_HIGH)
1376 flags |= DRM_MODE_FLAG_PVSYNC;
1377 else
1378 flags |= DRM_MODE_FLAG_NVSYNC;
1379 } else {
1380 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1381 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1382 flags |= DRM_MODE_FLAG_PHSYNC;
1383 else
1384 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1385
63000ef6
XZ		 1386 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1387 flags |= DRM_MODE_FLAG_PVSYNC;
1388 else
1389 flags |= DRM_MODE_FLAG_NVSYNC;
1390 }
045ac3b5
JB		 1391
1392 pipe_config->adjusted_mode.flags |= flags;
f1f644dc
JB		 1393
1394 if (dp_to_dig_port(intel_dp)->port == PORT_A) {
1395 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1396 pipe_config->port_clock = 162000;
1397 else
1398 pipe_config->port_clock = 270000;
1399 }
045ac3b5
JB		 1400}
1401
2293bb5c
SK		 1402static bool is_edp_psr(struct intel_dp *intel_dp)
1403{
1404 return is_edp(intel_dp) &&
1405 intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1406}
1407
2b28bb1b
RV		 1408static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1409{
1410 struct drm_i915_private *dev_priv = dev->dev_private;
1411
1412 if (!IS_HASWELL(dev))
1413 return false;
1414
1415 return I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
1416}
1417
1418static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1419 struct edp_vsc_psr *vsc_psr)
1420{
1421 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1422 struct drm_device *dev = dig_port->base.base.dev;
1423 struct drm_i915_private *dev_priv = dev->dev_private;
1424 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1425 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1426 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1427 uint32_t *data = (uint32_t *) vsc_psr;
1428 unsigned int i;
1429
1430 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1431 the video DIP being updated before program video DIP data buffer
1432 registers for DIP being updated. */
1433 I915_WRITE(ctl_reg, 0);
1434 POSTING_READ(ctl_reg);
1435
1436 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1437 if (i < sizeof(struct edp_vsc_psr))
1438 I915_WRITE(data_reg + i, *data++);
1439 else
1440 I915_WRITE(data_reg + i, 0);
1441 }
1442
1443 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1444 POSTING_READ(ctl_reg);
1445}
1446
1447static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1448{
1449 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1450 struct drm_i915_private *dev_priv = dev->dev_private;
1451 struct edp_vsc_psr psr_vsc;
1452
1453 if (intel_dp->psr_setup_done)
1454 return;
1455
1456 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1457 memset(&psr_vsc, 0, sizeof(psr_vsc));
1458 psr_vsc.sdp_header.HB0 = 0;
1459 psr_vsc.sdp_header.HB1 = 0x7;
1460 psr_vsc.sdp_header.HB2 = 0x2;
1461 psr_vsc.sdp_header.HB3 = 0x8;
1462 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1463
1464 /* Avoid continuous PSR exit by masking memup and hpd */
1465 I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
1466 EDP_PSR_DEBUG_MASK_HPD);
1467
1468 intel_dp->psr_setup_done = true;
1469}
1470
1471static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1472{
1473 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1474 struct drm_i915_private *dev_priv = dev->dev_private;
bc86625a 1475 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
2b28bb1b
RV		 1476 int precharge = 0x3;
1477 int msg_size = 5; /* Header(4) + Message(1) */
1478
1479 /* Enable PSR in sink */
1480 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1481 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1482 DP_PSR_ENABLE &
1483 ~DP_PSR_MAIN_LINK_ACTIVE);
1484 else
1485 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1486 DP_PSR_ENABLE |
1487 DP_PSR_MAIN_LINK_ACTIVE);
1488
1489 /* Setup AUX registers */
1490 I915_WRITE(EDP_PSR_AUX_DATA1, EDP_PSR_DPCD_COMMAND);
1491 I915_WRITE(EDP_PSR_AUX_DATA2, EDP_PSR_DPCD_NORMAL_OPERATION);
1492 I915_WRITE(EDP_PSR_AUX_CTL,
1493 DP_AUX_CH_CTL_TIME_OUT_400us |
1494 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1495 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1496 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1497}
1498
1499static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1500{
1501 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1502 struct drm_i915_private *dev_priv = dev->dev_private;
1503 uint32_t max_sleep_time = 0x1f;
1504 uint32_t idle_frames = 1;
1505 uint32_t val = 0x0;
1506
1507 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1508 val |= EDP_PSR_LINK_STANDBY;
1509 val |= EDP_PSR_TP2_TP3_TIME_0us;
1510 val |= EDP_PSR_TP1_TIME_0us;
1511 val |= EDP_PSR_SKIP_AUX_EXIT;
1512 } else
1513 val |= EDP_PSR_LINK_DISABLE;
1514
1515 I915_WRITE(EDP_PSR_CTL, val |
1516 EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
1517 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1518 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1519 EDP_PSR_ENABLE);
1520}
1521
3f51e471
RV		 1522static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1523{
1524 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1525 struct drm_device *dev = dig_port->base.base.dev;
1526 struct drm_i915_private *dev_priv = dev->dev_private;
1527 struct drm_crtc *crtc = dig_port->base.base.crtc;
1528 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1529 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1530 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1531
1532 if (!IS_HASWELL(dev)) {
1533 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1534 dev_priv->no_psr_reason = PSR_NO_SOURCE;
1535 return false;
1536 }
1537
1538 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1539 (dig_port->port != PORT_A)) {
1540 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1541 dev_priv->no_psr_reason = PSR_HSW_NOT_DDIA;
1542 return false;
1543 }
1544
1545 if (!is_edp_psr(intel_dp)) {
1546 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1547 dev_priv->no_psr_reason = PSR_NO_SINK;
1548 return false;
1549 }
1550
105b7c11
RV		 1551 if (!i915_enable_psr) {
1552 DRM_DEBUG_KMS("PSR disable by flag\n");
1553 dev_priv->no_psr_reason = PSR_MODULE_PARAM;
1554 return false;
1555 }
1556
cd234b0b
CW		 1557 crtc = dig_port->base.base.crtc;
1558 if (crtc == NULL) {
1559 DRM_DEBUG_KMS("crtc not active for PSR\n");
1560 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1561 return false;
1562 }
1563
1564 intel_crtc = to_intel_crtc(crtc);
3f51e471
RV		 1565 if (!intel_crtc->active || !crtc->fb || !crtc->mode.clock) {
1566 DRM_DEBUG_KMS("crtc not active for PSR\n");
1567 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1568 return false;
1569 }
1570
cd234b0b 1571 obj = to_intel_framebuffer(crtc->fb)->obj;
3f51e471
RV		 1572 if (obj->tiling_mode != I915_TILING_X ||
1573 obj->fence_reg == I915_FENCE_REG_NONE) {
1574 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1575 dev_priv->no_psr_reason = PSR_NOT_TILED;
1576 return false;
1577 }
1578
1579 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1580 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1581 dev_priv->no_psr_reason = PSR_SPRITE_ENABLED;
1582 return false;
1583 }
1584
1585 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1586 S3D_ENABLE) {
1587 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1588 dev_priv->no_psr_reason = PSR_S3D_ENABLED;
1589 return false;
1590 }
1591
1592 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
1593 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1594 dev_priv->no_psr_reason = PSR_INTERLACED_ENABLED;
1595 return false;
1596 }
1597
1598 return true;
1599}
1600
3d739d92 1601static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1602{
1603 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1604
3f51e471
RV		 1605 if (!intel_edp_psr_match_conditions(intel_dp) ||
1606 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1607 return;
1608
1609 /* Setup PSR once */
1610 intel_edp_psr_setup(intel_dp);
1611
1612 /* Enable PSR on the panel */
1613 intel_edp_psr_enable_sink(intel_dp);
1614
1615 /* Enable PSR on the host */
1616 intel_edp_psr_enable_source(intel_dp);
1617}
1618
3d739d92
RV		 1619void intel_edp_psr_enable(struct intel_dp *intel_dp)
1620{
1621 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1622
1623 if (intel_edp_psr_match_conditions(intel_dp) &&
1624 !intel_edp_is_psr_enabled(dev))
1625 intel_edp_psr_do_enable(intel_dp);
1626}
1627
2b28bb1b
RV		 1628void intel_edp_psr_disable(struct intel_dp *intel_dp)
1629{
1630 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1631 struct drm_i915_private *dev_priv = dev->dev_private;
1632
1633 if (!intel_edp_is_psr_enabled(dev))
1634 return;
1635
1636 I915_WRITE(EDP_PSR_CTL, I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
1637
1638 /* Wait till PSR is idle */
1639 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
1640 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1641 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1642}
1643
3d739d92
RV		 1644void intel_edp_psr_update(struct drm_device *dev)
1645{
1646 struct intel_encoder *encoder;
1647 struct intel_dp *intel_dp = NULL;
1648
1649 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1650 if (encoder->type == INTEL_OUTPUT_EDP) {
1651 intel_dp = enc_to_intel_dp(&encoder->base);
1652
1653 if (!is_edp_psr(intel_dp))
1654 return;
1655
1656 if (!intel_edp_psr_match_conditions(intel_dp))
1657 intel_edp_psr_disable(intel_dp);
1658 else
1659 if (!intel_edp_is_psr_enabled(dev))
1660 intel_edp_psr_do_enable(intel_dp);
1661 }
1662}
1663
e8cb4558 1664static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1665{
e8cb4558 1666 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1667 enum port port = dp_to_dig_port(intel_dp)->port;
1668 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1669
1670 /* Make sure the panel is off before trying to change the mode. But also
1671 * ensure that we have vdd while we switch off the panel. */
1672 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1673 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1674 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1675 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1676
1677 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1678 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1679 intel_dp_link_down(intel_dp);
d240f20f
JB		 1680}
1681
2bd2ad64 1682static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1683{
2bd2ad64 1684 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1685 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1686 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1687
982a3866 1688 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1689 intel_dp_link_down(intel_dp);
b2634017
JB		 1690 if (!IS_VALLEYVIEW(dev))
1691 ironlake_edp_pll_off(intel_dp);
3739850b 1692 }
2bd2ad64
DV		 1693}
1694
e8cb4558 1695static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1696{
e8cb4558
DV		 1697 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1698 struct drm_device *dev = encoder->base.dev;
1699 struct drm_i915_private *dev_priv = dev->dev_private;
1700 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1701
0c33d8d7
DV		 1702 if (WARN_ON(dp_reg & DP_PORT_EN))
1703 return;
5d613501 1704
97af61f5 1705 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1706 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1707 intel_dp_start_link_train(intel_dp);
97af61f5 1708 ironlake_edp_panel_on(intel_dp);
bd943159 1709 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1710 intel_dp_complete_link_train(intel_dp);
3ab9c637 1711 intel_dp_stop_link_train(intel_dp);
f01eca2e 1712 ironlake_edp_backlight_on(intel_dp);
ab1f90f9 1713}
89b667f8 1714
ab1f90f9
JN		 1715static void vlv_enable_dp(struct intel_encoder *encoder)
1716{
d240f20f
JB		 1717}
1718
2bd2ad64 1719static void intel_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1720{
1721 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1722 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1723
1724 if (dport->port == PORT_A)
1725 ironlake_edp_pll_on(intel_dp);
1726}
1727
1728static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1729{
2bd2ad64 1730 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1731 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1732 struct drm_device *dev = encoder->base.dev;
89b667f8 1733 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9
JN		 1734 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1735 int port = vlv_dport_to_channel(dport);
1736 int pipe = intel_crtc->pipe;
1737 u32 val;
a4fc5ed6 1738
ab1f90f9 1739 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1740
ab1f90f9
JN		 1741 val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1742 val = 0;
1743 if (pipe)
1744 val |= (1<<21);
1745 else
1746 val &= ~(1<<21);
1747 val |= 0x001000c4;
1748 vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1749 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
1750 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
89b667f8 1751
ab1f90f9
JN		 1752 mutex_unlock(&dev_priv->dpio_lock);
1753
1754 intel_enable_dp(encoder);
1755
1756 vlv_wait_port_ready(dev_priv, port);
89b667f8
JB		 1757}
1758
1759static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1760{
1761 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1762 struct drm_device *dev = encoder->base.dev;
1763 struct drm_i915_private *dev_priv = dev->dev_private;
1764 int port = vlv_dport_to_channel(dport);
1765
1766 if (!IS_VALLEYVIEW(dev))
1767 return;
1768
89b667f8 1769 /* Program Tx lane resets to default */
0980a60f 1770 mutex_lock(&dev_priv->dpio_lock);
ae99258f 1771 vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
89b667f8
JB		 1772 DPIO_PCS_TX_LANE2_RESET |
1773 DPIO_PCS_TX_LANE1_RESET);
ae99258f 1774 vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
89b667f8
JB		 1775 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1776 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1777 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1778 DPIO_PCS_CLK_SOFT_RESET);
1779
1780 /* Fix up inter-pair skew failure */
ae99258f
JN		 1781 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1782 vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1783 vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
0980a60f 1784 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 1785}
1786
1787/*
df0c237d
JB		 1788 * Native read with retry for link status and receiver capability reads for
1789 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1790 */
1791static bool
df0c237d
JB		 1792intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1793 uint8_t *recv, int recv_bytes)
a4fc5ed6 1794{
61da5fab
JB		 1795 int ret, i;
1796
df0c237d
JB		 1797 /*
1798 * Sinks are *supposed* to come up within 1ms from an off state,
1799 * but we're also supposed to retry 3 times per the spec.
1800 */
61da5fab 1801 for (i = 0; i < 3; i++) {
df0c237d
JB		 1802 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1803 recv_bytes);
1804 if (ret == recv_bytes)
61da5fab
JB		 1805 return true;
1806 msleep(1);
1807 }
a4fc5ed6 1808
61da5fab 1809 return false;
a4fc5ed6
KP		 1810}
1811
1812/*
1813 * Fetch AUX CH registers 0x202 - 0x207 which contain
1814 * link status information
1815 */
1816static bool
93f62dad 1817intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1818{
df0c237d
JB		 1819 return intel_dp_aux_native_read_retry(intel_dp,
1820 DP_LANE0_1_STATUS,
93f62dad 1821 link_status,
df0c237d 1822 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1823}
1824
a4fc5ed6
KP		 1825#if 0
1826static char *voltage_names[] = {
1827 "0.4V", "0.6V", "0.8V", "1.2V"
1828};
1829static char *pre_emph_names[] = {
1830 "0dB", "3.5dB", "6dB", "9.5dB"
1831};
1832static char *link_train_names[] = {
1833 "pattern 1", "pattern 2", "idle", "off"
1834};
1835#endif
1836
1837/*
1838 * These are source-specific values; current Intel hardware supports
1839 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1840 */
a4fc5ed6
KP		 1841
1842static uint8_t
1a2eb460 1843intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1844{
30add22d 1845 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1846 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1847
e2fa6fba
P		 1848 if (IS_VALLEYVIEW(dev))
1849 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 1850 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 1851 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 1852 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 1853 return DP_TRAIN_VOLTAGE_SWING_1200;
1854 else
1855 return DP_TRAIN_VOLTAGE_SWING_800;
1856}
1857
1858static uint8_t
1859intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1860{
30add22d 1861 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1862 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1863
22b8bf17 1864 if (HAS_DDI(dev)) {
d6c0d722
PZ		 1865 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1866 case DP_TRAIN_VOLTAGE_SWING_400:
1867 return DP_TRAIN_PRE_EMPHASIS_9_5;
1868 case DP_TRAIN_VOLTAGE_SWING_600:
1869 return DP_TRAIN_PRE_EMPHASIS_6;
1870 case DP_TRAIN_VOLTAGE_SWING_800:
1871 return DP_TRAIN_PRE_EMPHASIS_3_5;
1872 case DP_TRAIN_VOLTAGE_SWING_1200:
1873 default:
1874 return DP_TRAIN_PRE_EMPHASIS_0;
1875 }
e2fa6fba
P		 1876 } else if (IS_VALLEYVIEW(dev)) {
1877 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1878 case DP_TRAIN_VOLTAGE_SWING_400:
1879 return DP_TRAIN_PRE_EMPHASIS_9_5;
1880 case DP_TRAIN_VOLTAGE_SWING_600:
1881 return DP_TRAIN_PRE_EMPHASIS_6;
1882 case DP_TRAIN_VOLTAGE_SWING_800:
1883 return DP_TRAIN_PRE_EMPHASIS_3_5;
1884 case DP_TRAIN_VOLTAGE_SWING_1200:
1885 default:
1886 return DP_TRAIN_PRE_EMPHASIS_0;
1887 }
bc7d38a4 1888 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1889 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1890 case DP_TRAIN_VOLTAGE_SWING_400:
1891 return DP_TRAIN_PRE_EMPHASIS_6;
1892 case DP_TRAIN_VOLTAGE_SWING_600:
1893 case DP_TRAIN_VOLTAGE_SWING_800:
1894 return DP_TRAIN_PRE_EMPHASIS_3_5;
1895 default:
1896 return DP_TRAIN_PRE_EMPHASIS_0;
1897 }
1898 } else {
1899 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1900 case DP_TRAIN_VOLTAGE_SWING_400:
1901 return DP_TRAIN_PRE_EMPHASIS_6;
1902 case DP_TRAIN_VOLTAGE_SWING_600:
1903 return DP_TRAIN_PRE_EMPHASIS_6;
1904 case DP_TRAIN_VOLTAGE_SWING_800:
1905 return DP_TRAIN_PRE_EMPHASIS_3_5;
1906 case DP_TRAIN_VOLTAGE_SWING_1200:
1907 default:
1908 return DP_TRAIN_PRE_EMPHASIS_0;
1909 }
a4fc5ed6
KP		 1910 }
1911}
1912
e2fa6fba
P		 1913static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1914{
1915 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1916 struct drm_i915_private *dev_priv = dev->dev_private;
1917 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1918 unsigned long demph_reg_value, preemph_reg_value,
1919 uniqtranscale_reg_value;
1920 uint8_t train_set = intel_dp->train_set[0];
cece5d58 1921 int port = vlv_dport_to_channel(dport);
e2fa6fba
P		 1922
1923 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1924 case DP_TRAIN_PRE_EMPHASIS_0:
1925 preemph_reg_value = 0x0004000;
1926 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1927 case DP_TRAIN_VOLTAGE_SWING_400:
1928 demph_reg_value = 0x2B405555;
1929 uniqtranscale_reg_value = 0x552AB83A;
1930 break;
1931 case DP_TRAIN_VOLTAGE_SWING_600:
1932 demph_reg_value = 0x2B404040;
1933 uniqtranscale_reg_value = 0x5548B83A;
1934 break;
1935 case DP_TRAIN_VOLTAGE_SWING_800:
1936 demph_reg_value = 0x2B245555;
1937 uniqtranscale_reg_value = 0x5560B83A;
1938 break;
1939 case DP_TRAIN_VOLTAGE_SWING_1200:
1940 demph_reg_value = 0x2B405555;
1941 uniqtranscale_reg_value = 0x5598DA3A;
1942 break;
1943 default:
1944 return 0;
1945 }
1946 break;
1947 case DP_TRAIN_PRE_EMPHASIS_3_5:
1948 preemph_reg_value = 0x0002000;
1949 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1950 case DP_TRAIN_VOLTAGE_SWING_400:
1951 demph_reg_value = 0x2B404040;
1952 uniqtranscale_reg_value = 0x5552B83A;
1953 break;
1954 case DP_TRAIN_VOLTAGE_SWING_600:
1955 demph_reg_value = 0x2B404848;
1956 uniqtranscale_reg_value = 0x5580B83A;
1957 break;
1958 case DP_TRAIN_VOLTAGE_SWING_800:
1959 demph_reg_value = 0x2B404040;
1960 uniqtranscale_reg_value = 0x55ADDA3A;
1961 break;
1962 default:
1963 return 0;
1964 }
1965 break;
1966 case DP_TRAIN_PRE_EMPHASIS_6:
1967 preemph_reg_value = 0x0000000;
1968 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1969 case DP_TRAIN_VOLTAGE_SWING_400:
1970 demph_reg_value = 0x2B305555;
1971 uniqtranscale_reg_value = 0x5570B83A;
1972 break;
1973 case DP_TRAIN_VOLTAGE_SWING_600:
1974 demph_reg_value = 0x2B2B4040;
1975 uniqtranscale_reg_value = 0x55ADDA3A;
1976 break;
1977 default:
1978 return 0;
1979 }
1980 break;
1981 case DP_TRAIN_PRE_EMPHASIS_9_5:
1982 preemph_reg_value = 0x0006000;
1983 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1984 case DP_TRAIN_VOLTAGE_SWING_400:
1985 demph_reg_value = 0x1B405555;
1986 uniqtranscale_reg_value = 0x55ADDA3A;
1987 break;
1988 default:
1989 return 0;
1990 }
1991 break;
1992 default:
1993 return 0;
1994 }
1995
0980a60f 1996 mutex_lock(&dev_priv->dpio_lock);
ae99258f
JN		 1997 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1998 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1999 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
e2fa6fba 2000 uniqtranscale_reg_value);
ae99258f
JN		 2001 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
2002 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
2003 vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
2004 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
0980a60f 2005 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2006
2007 return 0;
2008}
2009
a4fc5ed6 2010static void
93f62dad 2011intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2012{
2013 uint8_t v = 0;
2014 uint8_t p = 0;
2015 int lane;
1a2eb460
KP		 2016 uint8_t voltage_max;
2017 uint8_t preemph_max;
a4fc5ed6 2018
33a34e4e 2019 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2020 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2021 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2022
2023 if (this_v > v)
2024 v = this_v;
2025 if (this_p > p)
2026 p = this_p;
2027 }
2028
1a2eb460 2029 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2030 if (v >= voltage_max)
2031 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2032
1a2eb460
KP		 2033 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2034 if (p >= preemph_max)
2035 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2036
2037 for (lane = 0; lane < 4; lane++)
33a34e4e 2038 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2039}
2040
2041static uint32_t
f0a3424e 2042intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2043{
3cf2efb1 2044 uint32_t signal_levels = 0;
a4fc5ed6 2045
3cf2efb1 2046 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2047 case DP_TRAIN_VOLTAGE_SWING_400:
2048 default:
2049 signal_levels |= DP_VOLTAGE_0_4;
2050 break;
2051 case DP_TRAIN_VOLTAGE_SWING_600:
2052 signal_levels |= DP_VOLTAGE_0_6;
2053 break;
2054 case DP_TRAIN_VOLTAGE_SWING_800:
2055 signal_levels |= DP_VOLTAGE_0_8;
2056 break;
2057 case DP_TRAIN_VOLTAGE_SWING_1200:
2058 signal_levels |= DP_VOLTAGE_1_2;
2059 break;
2060 }
3cf2efb1 2061 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2062 case DP_TRAIN_PRE_EMPHASIS_0:
2063 default:
2064 signal_levels |= DP_PRE_EMPHASIS_0;
2065 break;
2066 case DP_TRAIN_PRE_EMPHASIS_3_5:
2067 signal_levels |= DP_PRE_EMPHASIS_3_5;
2068 break;
2069 case DP_TRAIN_PRE_EMPHASIS_6:
2070 signal_levels |= DP_PRE_EMPHASIS_6;
2071 break;
2072 case DP_TRAIN_PRE_EMPHASIS_9_5:
2073 signal_levels |= DP_PRE_EMPHASIS_9_5;
2074 break;
2075 }
2076 return signal_levels;
2077}
2078
e3421a18
ZW		 2079/* Gen6's DP voltage swing and pre-emphasis control */
2080static uint32_t
2081intel_gen6_edp_signal_levels(uint8_t train_set)
2082{
3c5a62b5
YL		 2083 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2084 DP_TRAIN_PRE_EMPHASIS_MASK);
2085 switch (signal_levels) {
e3421a18 2086 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2087 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2088 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2089 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2090 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2091 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2092 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2093 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2094 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2095 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2096 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2097 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2098 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2099 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2100 default:
3c5a62b5
YL		 2101 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2102 "0x%x\n", signal_levels);
2103 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2104 }
2105}
2106
1a2eb460
KP		 2107/* Gen7's DP voltage swing and pre-emphasis control */
2108static uint32_t
2109intel_gen7_edp_signal_levels(uint8_t train_set)
2110{
2111 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2112 DP_TRAIN_PRE_EMPHASIS_MASK);
2113 switch (signal_levels) {
2114 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2115 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2116 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2117 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2118 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2119 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2120
2121 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2122 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2123 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2124 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2125
2126 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2127 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2128 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2129 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2130
2131 default:
2132 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2133 "0x%x\n", signal_levels);
2134 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2135 }
2136}
2137
d6c0d722
PZ		 2138/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2139static uint32_t
f0a3424e 2140intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2141{
d6c0d722
PZ		 2142 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2143 DP_TRAIN_PRE_EMPHASIS_MASK);
2144 switch (signal_levels) {
2145 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2146 return DDI_BUF_EMP_400MV_0DB_HSW;
2147 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2148 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2149 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2150 return DDI_BUF_EMP_400MV_6DB_HSW;
2151 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2152 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2153
d6c0d722
PZ		 2154 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2155 return DDI_BUF_EMP_600MV_0DB_HSW;
2156 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2157 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2158 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2159 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2160
d6c0d722
PZ		 2161 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2162 return DDI_BUF_EMP_800MV_0DB_HSW;
2163 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2164 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2165 default:
2166 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2167 "0x%x\n", signal_levels);
2168 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2169 }
a4fc5ed6
KP		 2170}
2171
f0a3424e
PZ		 2172/* Properly updates "DP" with the correct signal levels. */
2173static void
2174intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2175{
2176 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2177 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2178 struct drm_device *dev = intel_dig_port->base.base.dev;
2179 uint32_t signal_levels, mask;
2180 uint8_t train_set = intel_dp->train_set[0];
2181
22b8bf17 2182 if (HAS_DDI(dev)) {
f0a3424e
PZ		 2183 signal_levels = intel_hsw_signal_levels(train_set);
2184 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2185 } else if (IS_VALLEYVIEW(dev)) {
2186 signal_levels = intel_vlv_signal_levels(intel_dp);
2187 mask = 0;
bc7d38a4 2188 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2189 signal_levels = intel_gen7_edp_signal_levels(train_set);
2190 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2191 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2192 signal_levels = intel_gen6_edp_signal_levels(train_set);
2193 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2194 } else {
2195 signal_levels = intel_gen4_signal_levels(train_set);
2196 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2197 }
2198
2199 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2200
2201 *DP = (*DP & ~mask) | signal_levels;
2202}
2203
a4fc5ed6 2204static bool
ea5b213a 2205intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 2206 uint32_t dp_reg_value,
58e10eb9 2207 uint8_t dp_train_pat)
a4fc5ed6 2208{
174edf1f
PZ		 2209 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2210 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2211 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2212 enum port port = intel_dig_port->port;
a4fc5ed6
KP		 2213 int ret;
2214
22b8bf17 2215 if (HAS_DDI(dev)) {
3ab9c637 2216 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2217
2218 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2219 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2220 else
2221 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2222
2223 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2224 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2225 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2226 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2227
2228 break;
2229 case DP_TRAINING_PATTERN_1:
2230 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2231 break;
2232 case DP_TRAINING_PATTERN_2:
2233 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2234 break;
2235 case DP_TRAINING_PATTERN_3:
2236 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2237 break;
2238 }
174edf1f 2239 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2240
bc7d38a4 2241 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
47ea7542
PZ		 2242 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
2243
2244 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2245 case DP_TRAINING_PATTERN_DISABLE:
2246 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
2247 break;
2248 case DP_TRAINING_PATTERN_1:
2249 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
2250 break;
2251 case DP_TRAINING_PATTERN_2:
2252 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2253 break;
2254 case DP_TRAINING_PATTERN_3:
2255 DRM_ERROR("DP training pattern 3 not supported\n");
2256 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2257 break;
2258 }
2259
2260 } else {
2261 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
2262
2263 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2264 case DP_TRAINING_PATTERN_DISABLE:
2265 dp_reg_value |= DP_LINK_TRAIN_OFF;
2266 break;
2267 case DP_TRAINING_PATTERN_1:
2268 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
2269 break;
2270 case DP_TRAINING_PATTERN_2:
2271 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2272 break;
2273 case DP_TRAINING_PATTERN_3:
2274 DRM_ERROR("DP training pattern 3 not supported\n");
2275 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2276 break;
2277 }
2278 }
2279
ea5b213a
CW		 2280 I915_WRITE(intel_dp->output_reg, dp_reg_value);
2281 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2282
ea5b213a 2283 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 2284 DP_TRAINING_PATTERN_SET,
2285 dp_train_pat);
2286
47ea7542
PZ		 2287 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
2288 DP_TRAINING_PATTERN_DISABLE) {
2289 ret = intel_dp_aux_native_write(intel_dp,
2290 DP_TRAINING_LANE0_SET,
2291 intel_dp->train_set,
2292 intel_dp->lane_count);
2293 if (ret != intel_dp->lane_count)
2294 return false;
2295 }
a4fc5ed6
KP		 2296
2297 return true;
2298}
2299
3ab9c637
ID		 2300static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2301{
2302 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2303 struct drm_device *dev = intel_dig_port->base.base.dev;
2304 struct drm_i915_private *dev_priv = dev->dev_private;
2305 enum port port = intel_dig_port->port;
2306 uint32_t val;
2307
2308 if (!HAS_DDI(dev))
2309 return;
2310
2311 val = I915_READ(DP_TP_CTL(port));
2312 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2313 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2314 I915_WRITE(DP_TP_CTL(port), val);
2315
2316 /*
2317 * On PORT_A we can have only eDP in SST mode. There the only reason
2318 * we need to set idle transmission mode is to work around a HW issue
2319 * where we enable the pipe while not in idle link-training mode.
2320 * In this case there is requirement to wait for a minimum number of
2321 * idle patterns to be sent.
2322 */
2323 if (port == PORT_A)
2324 return;
2325
2326 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2327 1))
2328 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2329}
2330
33a34e4e 2331/* Enable corresponding port and start training pattern 1 */
c19b0669 2332void
33a34e4e 2333intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2334{
da63a9f2 2335 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2336 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2337 int i;
2338 uint8_t voltage;
cdb0e95b 2339 int voltage_tries, loop_tries;
ea5b213a 2340 uint32_t DP = intel_dp->DP;
a4fc5ed6 2341
affa9354 2342 if (HAS_DDI(dev))
c19b0669
PZ		 2343 intel_ddi_prepare_link_retrain(encoder);
2344
3cf2efb1
CW		 2345 /* Write the link configuration data */
2346 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2347 intel_dp->link_configuration,
2348 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 2349
2350 DP |= DP_PORT_EN;
1a2eb460 2351
33a34e4e 2352 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 2353 voltage = 0xff;
cdb0e95b
KP		 2354 voltage_tries = 0;
2355 loop_tries = 0;
a4fc5ed6 2356 for (;;) {
33a34e4e 2357 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 2358 uint8_t link_status[DP_LINK_STATUS_SIZE];
f0a3424e
PZ		 2359
2360 intel_dp_set_signal_levels(intel_dp, &DP);
a4fc5ed6 2361
a7c9655f 2362 /* Set training pattern 1 */
47ea7542 2363 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2364 DP_TRAINING_PATTERN_1 |
2365 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 2366 break;
a4fc5ed6 2367
a7c9655f 2368 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2369 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2370 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2371 break;
93f62dad 2372 }
a4fc5ed6 2373
01916270 2374 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2375 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2376 break;
2377 }
2378
2379 /* Check to see if we've tried the max voltage */
2380 for (i = 0; i < intel_dp->lane_count; i++)
2381 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2382 break;
3b4f819d 2383 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2384 ++loop_tries;
2385 if (loop_tries == 5) {
cdb0e95b
KP		 2386 DRM_DEBUG_KMS("too many full retries, give up\n");
2387 break;
2388 }
2389 memset(intel_dp->train_set, 0, 4);
2390 voltage_tries = 0;
2391 continue;
2392 }
a4fc5ed6 2393
3cf2efb1 2394 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2395 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2396 ++voltage_tries;
b06fbda3
DV		 2397 if (voltage_tries == 5) {
2398 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2399 break;
2400 }
2401 } else
2402 voltage_tries = 0;
2403 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2404
3cf2efb1 2405 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2406 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 2407 }
2408
33a34e4e
JB		 2409 intel_dp->DP = DP;
2410}
2411
c19b0669 2412void
33a34e4e
JB		 2413intel_dp_complete_link_train(struct intel_dp *intel_dp)
2414{
33a34e4e 2415 bool channel_eq = false;
37f80975 2416 int tries, cr_tries;
33a34e4e
JB		 2417 uint32_t DP = intel_dp->DP;
2418
a4fc5ed6
KP		 2419 /* channel equalization */
2420 tries = 0;
37f80975 2421 cr_tries = 0;
a4fc5ed6
KP		 2422 channel_eq = false;
2423 for (;;) {
93f62dad 2424 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2425
37f80975
JB		 2426 if (cr_tries > 5) {
2427 DRM_ERROR("failed to train DP, aborting\n");
2428 intel_dp_link_down(intel_dp);
2429 break;
2430 }
2431
f0a3424e 2432 intel_dp_set_signal_levels(intel_dp, &DP);
e3421a18 2433
a4fc5ed6 2434 /* channel eq pattern */
47ea7542 2435 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2436 DP_TRAINING_PATTERN_2 |
2437 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 2438 break;
2439
a7c9655f 2440 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 2441 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 2442 break;
a4fc5ed6 2443
37f80975 2444 /* Make sure clock is still ok */
01916270 2445 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 2446 intel_dp_start_link_train(intel_dp);
2447 cr_tries++;
2448 continue;
2449 }
2450
1ffdff13 2451 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2452 channel_eq = true;
2453 break;
2454 }
a4fc5ed6 2455
37f80975
JB		 2456 /* Try 5 times, then try clock recovery if that fails */
2457 if (tries > 5) {
2458 intel_dp_link_down(intel_dp);
2459 intel_dp_start_link_train(intel_dp);
2460 tries = 0;
2461 cr_tries++;
2462 continue;
2463 }
a4fc5ed6 2464
3cf2efb1 2465 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2466 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 2467 ++tries;
869184a6 2468 }
3cf2efb1 2469
3ab9c637
ID		 2470 intel_dp_set_idle_link_train(intel_dp);
2471
2472 intel_dp->DP = DP;
2473
d6c0d722 2474 if (channel_eq)
07f42258 2475 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2476
3ab9c637
ID		 2477}
2478
2479void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2480{
2481 intel_dp_set_link_train(intel_dp, intel_dp->DP,
2482 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2483}
2484
2485static void
ea5b213a 2486intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2487{
da63a9f2 2488 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2489 enum port port = intel_dig_port->port;
da63a9f2 2490 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2491 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2492 struct intel_crtc *intel_crtc =
2493 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2494 uint32_t DP = intel_dp->DP;
a4fc5ed6 2495
c19b0669
PZ		 2496 /*
2497 * DDI code has a strict mode set sequence and we should try to respect
2498 * it, otherwise we might hang the machine in many different ways. So we
2499 * really should be disabling the port only on a complete crtc_disable
2500 * sequence. This function is just called under two conditions on DDI
2501 * code:
2502 * - Link train failed while doing crtc_enable, and on this case we
2503 * really should respect the mode set sequence and wait for a
2504 * crtc_disable.
2505 * - Someone turned the monitor off and intel_dp_check_link_status
2506 * called us. We don't need to disable the whole port on this case, so
2507 * when someone turns the monitor on again,
2508 * intel_ddi_prepare_link_retrain will take care of redoing the link
2509 * train.
2510 */
affa9354 2511 if (HAS_DDI(dev))
c19b0669
PZ		 2512 return;
2513
0c33d8d7 2514 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2515 return;
2516
28c97730 2517 DRM_DEBUG_KMS("\n");
32f9d658 2518
bc7d38a4 2519 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2520 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2521 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2522 } else {
2523 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2524 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2525 }
fe255d00 2526 POSTING_READ(intel_dp->output_reg);
5eb08b69 2527
ab527efc
DV		 2528 /* We don't really know why we're doing this */
2529 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2530
493a7081 2531 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2532 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2533 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2534
5bddd17f
EA		 2535 /* Hardware workaround: leaving our transcoder select
2536 * set to transcoder B while it's off will prevent the
2537 * corresponding HDMI output on transcoder A.
2538 *
2539 * Combine this with another hardware workaround:
2540 * transcoder select bit can only be cleared while the
2541 * port is enabled.
2542 */
2543 DP &= ~DP_PIPEB_SELECT;
2544 I915_WRITE(intel_dp->output_reg, DP);
2545
2546 /* Changes to enable or select take place the vblank
2547 * after being written.
2548 */
ff50afe9
DV		 2549 if (WARN_ON(crtc == NULL)) {
2550 /* We should never try to disable a port without a crtc
2551 * attached. For paranoia keep the code around for a
2552 * bit. */
31acbcc4
CW		 2553 POSTING_READ(intel_dp->output_reg);
2554 msleep(50);
2555 } else
ab527efc 2556 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2557 }
2558
832afda6 2559 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2560 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2561 POSTING_READ(intel_dp->output_reg);
f01eca2e 2562 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2563}
2564
26d61aad
KP		 2565static bool
2566intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2567{
577c7a50
DL		 2568 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2569
92fd8fd1 2570 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2571 sizeof(intel_dp->dpcd)) == 0)
2572 return false; /* aux transfer failed */
92fd8fd1 2573
577c7a50
DL		 2574 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2575 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2576 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2577
edb39244
AJ		 2578 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2579 return false; /* DPCD not present */
2580
2293bb5c
SK		 2581 /* Check if the panel supports PSR */
2582 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2583 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2584 intel_dp->psr_dpcd,
2585 sizeof(intel_dp->psr_dpcd));
2586 if (is_edp_psr(intel_dp))
2587 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
edb39244
AJ		 2588 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2589 DP_DWN_STRM_PORT_PRESENT))
2590 return true; /* native DP sink */
2591
2592 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2593 return true; /* no per-port downstream info */
2594
2595 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2596 intel_dp->downstream_ports,
2597 DP_MAX_DOWNSTREAM_PORTS) == 0)
2598 return false; /* downstream port status fetch failed */
2599
2600 return true;
92fd8fd1
KP		 2601}
2602
0d198328
AJ		 2603static void
2604intel_dp_probe_oui(struct intel_dp *intel_dp)
2605{
2606 u8 buf[3];
2607
2608 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2609 return;
2610
351cfc34
DV		 2611 ironlake_edp_panel_vdd_on(intel_dp);
2612
0d198328
AJ		 2613 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2614 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2615 buf[0], buf[1], buf[2]);
2616
2617 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2618 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2619 buf[0], buf[1], buf[2]);
351cfc34
DV		 2620
2621 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2622}
2623
a60f0e38
JB		 2624static bool
2625intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2626{
2627 int ret;
2628
2629 ret = intel_dp_aux_native_read_retry(intel_dp,
2630 DP_DEVICE_SERVICE_IRQ_VECTOR,
2631 sink_irq_vector, 1);
2632 if (!ret)
2633 return false;
2634
2635 return true;
2636}
2637
2638static void
2639intel_dp_handle_test_request(struct intel_dp *intel_dp)
2640{
2641 /* NAK by default */
9324cf7f 2642 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2643}
2644
a4fc5ed6
KP		 2645/*
2646 * According to DP spec
2647 * 5.1.2:
2648 * 1. Read DPCD
2649 * 2. Configure link according to Receiver Capabilities
2650 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2651 * 4. Check link status on receipt of hot-plug interrupt
2652 */
2653
00c09d70 2654void
ea5b213a 2655intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2656{
da63a9f2 2657 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2658 u8 sink_irq_vector;
93f62dad 2659 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2660
da63a9f2 2661 if (!intel_encoder->connectors_active)
d2b996ac 2662 return;
59cd09e1 2663
da63a9f2 2664 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2665 return;
2666
92fd8fd1 2667 /* Try to read receiver status if the link appears to be up */
93f62dad 2668 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2669 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2670 return;
2671 }
2672
92fd8fd1 2673 /* Now read the DPCD to see if it's actually running */
26d61aad 2674 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2675 intel_dp_link_down(intel_dp);
2676 return;
2677 }
2678
a60f0e38
JB		 2679 /* Try to read the source of the interrupt */
2680 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2681 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2682 /* Clear interrupt source */
2683 intel_dp_aux_native_write_1(intel_dp,
2684 DP_DEVICE_SERVICE_IRQ_VECTOR,
2685 sink_irq_vector);
2686
2687 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2688 intel_dp_handle_test_request(intel_dp);
2689 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2690 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2691 }
2692
1ffdff13 2693 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2694 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2695 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2696 intel_dp_start_link_train(intel_dp);
2697 intel_dp_complete_link_train(intel_dp);
3ab9c637 2698 intel_dp_stop_link_train(intel_dp);
33a34e4e 2699 }
a4fc5ed6 2700}
a4fc5ed6 2701
caf9ab24 2702/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2703static enum drm_connector_status
26d61aad 2704intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2705{
caf9ab24
AJ		 2706 uint8_t *dpcd = intel_dp->dpcd;
2707 bool hpd;
2708 uint8_t type;
2709
2710 if (!intel_dp_get_dpcd(intel_dp))
2711 return connector_status_disconnected;
2712
2713 /* if there's no downstream port, we're done */
2714 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2715 return connector_status_connected;
caf9ab24
AJ		 2716
2717 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2718 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2719 if (hpd) {
23235177 2720 uint8_t reg;
caf9ab24 2721 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2722 &reg, 1))
caf9ab24 2723 return connector_status_unknown;
23235177
AJ		 2724 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2725 : connector_status_disconnected;
caf9ab24
AJ		 2726 }
2727
2728 /* If no HPD, poke DDC gently */
2729 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2730 return connector_status_connected;
caf9ab24
AJ		 2731
2732 /* Well we tried, say unknown for unreliable port types */
2733 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2734 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2735 return connector_status_unknown;
2736
2737 /* Anything else is out of spec, warn and ignore */
2738 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2739 return connector_status_disconnected;
71ba9000
AJ		 2740}
2741
5eb08b69 2742static enum drm_connector_status
a9756bb5 2743ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2744{
30add22d 2745 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2746 struct drm_i915_private *dev_priv = dev->dev_private;
2747 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2748 enum drm_connector_status status;
2749
fe16d949
CW		 2750 /* Can't disconnect eDP, but you can close the lid... */
2751 if (is_edp(intel_dp)) {
30add22d 2752 status = intel_panel_detect(dev);
fe16d949
CW		 2753 if (status == connector_status_unknown)
2754 status = connector_status_connected;
2755 return status;
2756 }
01cb9ea6 2757
1b469639
DL		 2758 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2759 return connector_status_disconnected;
2760
26d61aad 2761 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2762}
2763
a4fc5ed6 2764static enum drm_connector_status
a9756bb5 2765g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2766{
30add22d 2767 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2768 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 2769 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 2770 uint32_t bit;
5eb08b69 2771
35aad75f
JB		 2772 /* Can't disconnect eDP, but you can close the lid... */
2773 if (is_edp(intel_dp)) {
2774 enum drm_connector_status status;
2775
2776 status = intel_panel_detect(dev);
2777 if (status == connector_status_unknown)
2778 status = connector_status_connected;
2779 return status;
2780 }
2781
34f2be46
VS		 2782 switch (intel_dig_port->port) {
2783 case PORT_B:
26739f12 2784 bit = PORTB_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2785 break;
34f2be46 2786 case PORT_C:
26739f12 2787 bit = PORTC_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2788 break;
34f2be46 2789 case PORT_D:
26739f12 2790 bit = PORTD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2791 break;
2792 default:
2793 return connector_status_unknown;
2794 }
2795
10f76a38 2796 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2797 return connector_status_disconnected;
2798
26d61aad 2799 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2800}
2801
8c241fef
KP		 2802static struct edid *
2803intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2804{
9cd300e0 2805 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2806
9cd300e0
JN		 2807 /* use cached edid if we have one */
2808 if (intel_connector->edid) {
2809 struct edid *edid;
2810 int size;
2811
2812 /* invalid edid */
2813 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2814 return NULL;
2815
9cd300e0 2816 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
edbe1581 2817 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
d6f24d0f
JB		 2818 if (!edid)
2819 return NULL;
2820
d6f24d0f
JB		 2821 return edid;
2822 }
8c241fef 2823
9cd300e0 2824 return drm_get_edid(connector, adapter);
8c241fef
KP		 2825}
2826
2827static int
2828intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2829{
9cd300e0 2830 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2831
9cd300e0
JN		 2832 /* use cached edid if we have one */
2833 if (intel_connector->edid) {
2834 /* invalid edid */
2835 if (IS_ERR(intel_connector->edid))
2836 return 0;
2837
2838 return intel_connector_update_modes(connector,
2839 intel_connector->edid);
d6f24d0f
JB		 2840 }
2841
9cd300e0 2842 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2843}
2844
a9756bb5
ZW		 2845static enum drm_connector_status
2846intel_dp_detect(struct drm_connector *connector, bool force)
2847{
2848 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2849 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2850 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2851 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 2852 enum drm_connector_status status;
2853 struct edid *edid = NULL;
2854
164c8598
CW		 2855 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2856 connector->base.id, drm_get_connector_name(connector));
2857
a9756bb5
ZW		 2858 intel_dp->has_audio = false;
2859
2860 if (HAS_PCH_SPLIT(dev))
2861 status = ironlake_dp_detect(intel_dp);
2862 else
2863 status = g4x_dp_detect(intel_dp);
1b9be9d0 2864
a9756bb5
ZW		 2865 if (status != connector_status_connected)
2866 return status;
2867
0d198328
AJ		 2868 intel_dp_probe_oui(intel_dp);
2869
c3e5f67b
DV		 2870 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2871 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2872 } else {
8c241fef 2873 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2874 if (edid) {
2875 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2876 kfree(edid);
2877 }
a9756bb5
ZW		 2878 }
2879
d63885da
PZ		 2880 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2881 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2882 return connector_status_connected;
a4fc5ed6
KP		 2883}
2884
2885static int intel_dp_get_modes(struct drm_connector *connector)
2886{
df0e9248 2887 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2888 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2889 struct drm_device *dev = connector->dev;
32f9d658 2890 int ret;
a4fc5ed6
KP		 2891
2892 /* We should parse the EDID data and find out if it has an audio sink
2893 */
2894
8c241fef 2895 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2896 if (ret)
32f9d658
ZW		 2897 return ret;
2898
f8779fda 2899 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2900 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2901 struct drm_display_mode *mode;
dd06f90e
JN		 2902 mode = drm_mode_duplicate(dev,
2903 intel_connector->panel.fixed_mode);
f8779fda 2904 if (mode) {
32f9d658
ZW		 2905 drm_mode_probed_add(connector, mode);
2906 return 1;
2907 }
2908 }
2909 return 0;
a4fc5ed6
KP		 2910}
2911
1aad7ac0
CW		 2912static bool
2913intel_dp_detect_audio(struct drm_connector *connector)
2914{
2915 struct intel_dp *intel_dp = intel_attached_dp(connector);
2916 struct edid *edid;
2917 bool has_audio = false;
2918
8c241fef 2919 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2920 if (edid) {
2921 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2922 kfree(edid);
2923 }
2924
2925 return has_audio;
2926}
2927
f684960e
CW		 2928static int
2929intel_dp_set_property(struct drm_connector *connector,
2930 struct drm_property *property,
2931 uint64_t val)
2932{
e953fd7b 2933 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 2934 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 2935 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2936 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 2937 int ret;
2938
662595df 2939 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 2940 if (ret)
2941 return ret;
2942
3f43c48d 2943 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2944 int i = val;
2945 bool has_audio;
2946
2947 if (i == intel_dp->force_audio)
f684960e
CW		 2948 return 0;
2949
1aad7ac0 2950 intel_dp->force_audio = i;
f684960e 2951
c3e5f67b 2952 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2953 has_audio = intel_dp_detect_audio(connector);
2954 else
c3e5f67b 2955 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2956
2957 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2958 return 0;
2959
1aad7ac0 2960 intel_dp->has_audio = has_audio;
f684960e
CW		 2961 goto done;
2962 }
2963
e953fd7b 2964 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 2965 bool old_auto = intel_dp->color_range_auto;
2966 uint32_t old_range = intel_dp->color_range;
2967
55bc60db
VS		 2968 switch (val) {
2969 case INTEL_BROADCAST_RGB_AUTO:
2970 intel_dp->color_range_auto = true;
2971 break;
2972 case INTEL_BROADCAST_RGB_FULL:
2973 intel_dp->color_range_auto = false;
2974 intel_dp->color_range = 0;
2975 break;
2976 case INTEL_BROADCAST_RGB_LIMITED:
2977 intel_dp->color_range_auto = false;
2978 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2979 break;
2980 default:
2981 return -EINVAL;
2982 }
ae4edb80
DV		 2983
2984 if (old_auto == intel_dp->color_range_auto &&
2985 old_range == intel_dp->color_range)
2986 return 0;
2987
e953fd7b
CW		 2988 goto done;
2989 }
2990
53b41837
YN		 2991 if (is_edp(intel_dp) &&
2992 property == connector->dev->mode_config.scaling_mode_property) {
2993 if (val == DRM_MODE_SCALE_NONE) {
2994 DRM_DEBUG_KMS("no scaling not supported\n");
2995 return -EINVAL;
2996 }
2997
2998 if (intel_connector->panel.fitting_mode == val) {
2999 /* the eDP scaling property is not changed */
3000 return 0;
3001 }
3002 intel_connector->panel.fitting_mode = val;
3003
3004 goto done;
3005 }
3006
f684960e
CW		 3007 return -EINVAL;
3008
3009done:
c0c36b94
CW		 3010 if (intel_encoder->base.crtc)
3011 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3012
3013 return 0;
3014}
3015
a4fc5ed6 3016static void
73845adf 3017intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3018{
1d508706 3019 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3020
9cd300e0
JN		 3021 if (!IS_ERR_OR_NULL(intel_connector->edid))
3022 kfree(intel_connector->edid);
3023
acd8db10
PZ		 3024 /* Can't call is_edp() since the encoder may have been destroyed
3025 * already. */
3026 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3027 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3028
a4fc5ed6
KP		 3029 drm_sysfs_connector_remove(connector);
3030 drm_connector_cleanup(connector);
55f78c43 3031 kfree(connector);
a4fc5ed6
KP		 3032}
3033
00c09d70 3034void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3035{
da63a9f2
PZ		 3036 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3037 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3038 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927
DV		 3039
3040 i2c_del_adapter(&intel_dp->adapter);
3041 drm_encoder_cleanup(encoder);
bd943159
KP		 3042 if (is_edp(intel_dp)) {
3043 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3044 mutex_lock(&dev->mode_config.mutex);
bd943159 3045 ironlake_panel_vdd_off_sync(intel_dp);
bd173813 3046 mutex_unlock(&dev->mode_config.mutex);
bd943159 3047 }
da63a9f2 3048 kfree(intel_dig_port);
24d05927
DV		 3049}
3050
a4fc5ed6 3051static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3052 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3053 .detect = intel_dp_detect,
3054 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3055 .set_property = intel_dp_set_property,
73845adf 3056 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3057};
3058
3059static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3060 .get_modes = intel_dp_get_modes,
3061 .mode_valid = intel_dp_mode_valid,
df0e9248 3062 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3063};
3064
a4fc5ed6 3065static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3066 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3067};
3068
995b6762 3069static void
21d40d37 3070intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3071{
fa90ecef 3072 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3073
885a5014 3074 intel_dp_check_link_status(intel_dp);
c8110e52 3075}
6207937d 3076
e3421a18
ZW		 3077/* Return which DP Port should be selected for Transcoder DP control */
3078int
0206e353 3079intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3080{
3081 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3082 struct intel_encoder *intel_encoder;
3083 struct intel_dp *intel_dp;
e3421a18 3084
fa90ecef
PZ		 3085 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3086 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3087
fa90ecef
PZ		 3088 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3089 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3090 return intel_dp->output_reg;
e3421a18 3091 }
ea5b213a 3092
e3421a18
ZW		 3093 return -1;
3094}
3095
36e83a18 3096/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 3097bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 3098{
3099 struct drm_i915_private *dev_priv = dev->dev_private;
3100 struct child_device_config *p_child;
3101 int i;
3102
41aa3448 3103 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3104 return false;
3105
41aa3448
RV		 3106 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3107 p_child = dev_priv->vbt.child_dev + i;
36e83a18
ZY		 3108
3109 if (p_child->dvo_port == PORT_IDPD &&
3110 p_child->device_type == DEVICE_TYPE_eDP)
3111 return true;
3112 }
3113 return false;
3114}
3115
f684960e
CW		 3116static void
3117intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3118{
53b41837
YN		 3119 struct intel_connector *intel_connector = to_intel_connector(connector);
3120
3f43c48d 3121 intel_attach_force_audio_property(connector);
e953fd7b 3122 intel_attach_broadcast_rgb_property(connector);
55bc60db 3123 intel_dp->color_range_auto = true;
53b41837
YN		 3124
3125 if (is_edp(intel_dp)) {
3126 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3127 drm_object_attach_property(
3128 &connector->base,
53b41837 3129 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3130 DRM_MODE_SCALE_ASPECT);
3131 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3132 }
f684960e
CW		 3133}
3134
67a54566
DV		 3135static void
3136intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3137 struct intel_dp *intel_dp,
3138 struct edp_power_seq *out)
67a54566
DV		 3139{
3140 struct drm_i915_private *dev_priv = dev->dev_private;
3141 struct edp_power_seq cur, vbt, spec, final;
3142 u32 pp_on, pp_off, pp_div, pp;
453c5420
JB		 3143 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3144
3145 if (HAS_PCH_SPLIT(dev)) {
3146 pp_control_reg = PCH_PP_CONTROL;
3147 pp_on_reg = PCH_PP_ON_DELAYS;
3148 pp_off_reg = PCH_PP_OFF_DELAYS;
3149 pp_div_reg = PCH_PP_DIVISOR;
3150 } else {
3151 pp_control_reg = PIPEA_PP_CONTROL;
3152 pp_on_reg = PIPEA_PP_ON_DELAYS;
3153 pp_off_reg = PIPEA_PP_OFF_DELAYS;
3154 pp_div_reg = PIPEA_PP_DIVISOR;
3155 }
67a54566
DV		 3156
3157 /* Workaround: Need to write PP_CONTROL with the unlock key as
3158 * the very first thing. */
453c5420
JB		 3159 pp = ironlake_get_pp_control(intel_dp);
3160 I915_WRITE(pp_control_reg, pp);
67a54566 3161
453c5420
JB		 3162 pp_on = I915_READ(pp_on_reg);
3163 pp_off = I915_READ(pp_off_reg);
3164 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3165
3166 /* Pull timing values out of registers */
3167 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3168 PANEL_POWER_UP_DELAY_SHIFT;
3169
3170 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3171 PANEL_LIGHT_ON_DELAY_SHIFT;
3172
3173 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3174 PANEL_LIGHT_OFF_DELAY_SHIFT;
3175
3176 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3177 PANEL_POWER_DOWN_DELAY_SHIFT;
3178
3179 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3180 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3181
3182 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3183 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3184
41aa3448 3185 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3186
3187 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3188 * our hw here, which are all in 100usec. */
3189 spec.t1_t3 = 210 * 10;
3190 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3191 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3192 spec.t10 = 500 * 10;
3193 /* This one is special and actually in units of 100ms, but zero
3194 * based in the hw (so we need to add 100 ms). But the sw vbt
3195 * table multiplies it with 1000 to make it in units of 100usec,
3196 * too. */
3197 spec.t11_t12 = (510 + 100) * 10;
3198
3199 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3200 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3201
3202 /* Use the max of the register settings and vbt. If both are
3203 * unset, fall back to the spec limits. */
3204#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3205 spec.field : \
3206 max(cur.field, vbt.field))
3207 assign_final(t1_t3);
3208 assign_final(t8);
3209 assign_final(t9);
3210 assign_final(t10);
3211 assign_final(t11_t12);
3212#undef assign_final
3213
3214#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3215 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3216 intel_dp->backlight_on_delay = get_delay(t8);
3217 intel_dp->backlight_off_delay = get_delay(t9);
3218 intel_dp->panel_power_down_delay = get_delay(t10);
3219 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3220#undef get_delay
3221
f30d26e4
JN		 3222 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3223 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3224 intel_dp->panel_power_cycle_delay);
3225
3226 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3227 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3228
3229 if (out)
3230 *out = final;
3231}
3232
3233static void
3234intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3235 struct intel_dp *intel_dp,
3236 struct edp_power_seq *seq)
3237{
3238 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3239 u32 pp_on, pp_off, pp_div, port_sel = 0;
3240 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3241 int pp_on_reg, pp_off_reg, pp_div_reg;
3242
3243 if (HAS_PCH_SPLIT(dev)) {
3244 pp_on_reg = PCH_PP_ON_DELAYS;
3245 pp_off_reg = PCH_PP_OFF_DELAYS;
3246 pp_div_reg = PCH_PP_DIVISOR;
3247 } else {
3248 pp_on_reg = PIPEA_PP_ON_DELAYS;
3249 pp_off_reg = PIPEA_PP_OFF_DELAYS;
3250 pp_div_reg = PIPEA_PP_DIVISOR;
3251 }
3252
67a54566 3253 /* And finally store the new values in the power sequencer. */
f30d26e4
JN		 3254 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3255 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3256 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3257 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3258 /* Compute the divisor for the pp clock, simply match the Bspec
3259 * formula. */
453c5420 3260 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3261 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3262 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3263
3264 /* Haswell doesn't have any port selection bits for the panel
3265 * power sequencer any more. */
bc7d38a4
ID		 3266 if (IS_VALLEYVIEW(dev)) {
3267 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
3268 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3269 if (dp_to_dig_port(intel_dp)->port == PORT_A)
453c5420 3270 port_sel = PANEL_POWER_PORT_DP_A;
67a54566 3271 else
453c5420 3272 port_sel = PANEL_POWER_PORT_DP_D;
67a54566
DV		 3273 }
3274
453c5420
JB		 3275 pp_on |= port_sel;
3276
3277 I915_WRITE(pp_on_reg, pp_on);
3278 I915_WRITE(pp_off_reg, pp_off);
3279 I915_WRITE(pp_div_reg, pp_div);
67a54566 3280
67a54566 3281 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3282 I915_READ(pp_on_reg),
3283 I915_READ(pp_off_reg),
3284 I915_READ(pp_div_reg));
f684960e
CW		 3285}
3286
ed92f0b2
PZ		 3287static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3288 struct intel_connector *intel_connector)
3289{
3290 struct drm_connector *connector = &intel_connector->base;
3291 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3292 struct drm_device *dev = intel_dig_port->base.base.dev;
3293 struct drm_i915_private *dev_priv = dev->dev_private;
3294 struct drm_display_mode *fixed_mode = NULL;
3295 struct edp_power_seq power_seq = { 0 };
3296 bool has_dpcd;
3297 struct drm_display_mode *scan;
3298 struct edid *edid;
3299
3300 if (!is_edp(intel_dp))
3301 return true;
3302
3303 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3304
3305 /* Cache DPCD and EDID for edp. */
3306 ironlake_edp_panel_vdd_on(intel_dp);
3307 has_dpcd = intel_dp_get_dpcd(intel_dp);
3308 ironlake_edp_panel_vdd_off(intel_dp, false);
3309
3310 if (has_dpcd) {
3311 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3312 dev_priv->no_aux_handshake =
3313 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3314 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3315 } else {
3316 /* if this fails, presume the device is a ghost */
3317 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3318 return false;
3319 }
3320
3321 /* We now know it's not a ghost, init power sequence regs. */
3322 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3323 &power_seq);
3324
3325 ironlake_edp_panel_vdd_on(intel_dp);
3326 edid = drm_get_edid(connector, &intel_dp->adapter);
3327 if (edid) {
3328 if (drm_add_edid_modes(connector, edid)) {
3329 drm_mode_connector_update_edid_property(connector,
3330 edid);
3331 drm_edid_to_eld(connector, edid);
3332 } else {
3333 kfree(edid);
3334 edid = ERR_PTR(-EINVAL);
3335 }
3336 } else {
3337 edid = ERR_PTR(-ENOENT);
3338 }
3339 intel_connector->edid = edid;
3340
3341 /* prefer fixed mode from EDID if available */
3342 list_for_each_entry(scan, &connector->probed_modes, head) {
3343 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3344 fixed_mode = drm_mode_duplicate(dev, scan);
3345 break;
3346 }
3347 }
3348
3349 /* fallback to VBT if available for eDP */
3350 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3351 fixed_mode = drm_mode_duplicate(dev,
3352 dev_priv->vbt.lfp_lvds_vbt_mode);
3353 if (fixed_mode)
3354 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3355 }
3356
3357 ironlake_edp_panel_vdd_off(intel_dp, false);
3358
3359 intel_panel_init(&intel_connector->panel, fixed_mode);
3360 intel_panel_setup_backlight(connector);
3361
3362 return true;
3363}
3364
16c25533 3365bool
f0fec3f2
PZ		 3366intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3367 struct intel_connector *intel_connector)
a4fc5ed6 3368{
f0fec3f2
PZ		 3369 struct drm_connector *connector = &intel_connector->base;
3370 struct intel_dp *intel_dp = &intel_dig_port->dp;
3371 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3372 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3373 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3374 enum port port = intel_dig_port->port;
5eb08b69 3375 const char *name = NULL;
b2a14755 3376 int type, error;
a4fc5ed6 3377
0767935e
DV		 3378 /* Preserve the current hw state. */
3379 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3380 intel_dp->attached_connector = intel_connector;
3d3dc149 3381
f7d24902 3382 type = DRM_MODE_CONNECTOR_DisplayPort;
19c03924
GB		 3383 /*
3384 * FIXME : We need to initialize built-in panels before external panels.
3385 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3386 */
f7d24902
ID		 3387 switch (port) {
3388 case PORT_A:
b329530c 3389 type = DRM_MODE_CONNECTOR_eDP;
f7d24902
ID		 3390 break;
3391 case PORT_C:
3392 if (IS_VALLEYVIEW(dev))
3393 type = DRM_MODE_CONNECTOR_eDP;
3394 break;
3395 case PORT_D:
3396 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3397 type = DRM_MODE_CONNECTOR_eDP;
3398 break;
3399 default: /* silence GCC warning */
3400 break;
b329530c
AJ		 3401 }
3402
f7d24902
ID		 3403 /*
3404 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3405 * for DP the encoder type can be set by the caller to
3406 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3407 */
3408 if (type == DRM_MODE_CONNECTOR_eDP)
3409 intel_encoder->type = INTEL_OUTPUT_EDP;
3410
e7281eab
ID		 3411 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3412 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3413 port_name(port));
3414
b329530c 3415 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3416 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3417
a4fc5ed6
KP		 3418 connector->interlace_allowed = true;
3419 connector->doublescan_allowed = 0;
3420
f0fec3f2
PZ		 3421 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3422 ironlake_panel_vdd_work);
a4fc5ed6 3423
df0e9248 3424 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3425 drm_sysfs_connector_add(connector);
3426
affa9354 3427 if (HAS_DDI(dev))
bcbc889b
PZ		 3428 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3429 else
3430 intel_connector->get_hw_state = intel_connector_get_hw_state;
3431
9ed35ab1
PZ		 3432 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3433 if (HAS_DDI(dev)) {
3434 switch (intel_dig_port->port) {
3435 case PORT_A:
3436 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3437 break;
3438 case PORT_B:
3439 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3440 break;
3441 case PORT_C:
3442 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3443 break;
3444 case PORT_D:
3445 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3446 break;
3447 default:
3448 BUG();
3449 }
3450 }
e8cb4558 3451
a4fc5ed6 3452 /* Set up the DDC bus. */
ab9d7c30
PZ		 3453 switch (port) {
3454 case PORT_A:
1d843f9d 3455 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3456 name = "DPDDC-A";
3457 break;
3458 case PORT_B:
1d843f9d 3459 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3460 name = "DPDDC-B";
3461 break;
3462 case PORT_C:
1d843f9d 3463 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3464 name = "DPDDC-C";
3465 break;
3466 case PORT_D:
1d843f9d 3467 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3468 name = "DPDDC-D";
3469 break;
3470 default:
ad1c0b19 3471 BUG();
5eb08b69
ZW		 3472 }
3473
b2a14755
PZ		 3474 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3475 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3476 error, port_name(port));
c1f05264 3477
2b28bb1b
RV		 3478 intel_dp->psr_setup_done = false;
3479
b2f246a8 3480 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
15b1d171
PZ		 3481 i2c_del_adapter(&intel_dp->adapter);
3482 if (is_edp(intel_dp)) {
3483 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3484 mutex_lock(&dev->mode_config.mutex);
3485 ironlake_panel_vdd_off_sync(intel_dp);
3486 mutex_unlock(&dev->mode_config.mutex);
3487 }
b2f246a8
PZ		 3488 drm_sysfs_connector_remove(connector);
3489 drm_connector_cleanup(connector);
16c25533 3490 return false;
b2f246a8 3491 }
32f9d658 3492
f684960e
CW		 3493 intel_dp_add_properties(intel_dp, connector);
3494
a4fc5ed6
KP		 3495 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3496 * 0xd. Failure to do so will result in spurious interrupts being
3497 * generated on the port when a cable is not attached.
3498 */
3499 if (IS_G4X(dev) && !IS_GM45(dev)) {
3500 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3501 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3502 }
16c25533
PZ		 3503
3504 return true;
a4fc5ed6 3505}
f0fec3f2
PZ		 3506
3507void
3508intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3509{
3510 struct intel_digital_port *intel_dig_port;
3511 struct intel_encoder *intel_encoder;
3512 struct drm_encoder *encoder;
3513 struct intel_connector *intel_connector;
3514
3515 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3516 if (!intel_dig_port)
3517 return;
3518
3519 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3520 if (!intel_connector) {
3521 kfree(intel_dig_port);
3522 return;
3523 }
3524
3525 intel_encoder = &intel_dig_port->base;
3526 encoder = &intel_encoder->base;
3527
3528 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3529 DRM_MODE_ENCODER_TMDS);
3530
5bfe2ac0 3531 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 3532 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70
PZ		 3533 intel_encoder->disable = intel_disable_dp;
3534 intel_encoder->post_disable = intel_post_disable_dp;
3535 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3536 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 3537 if (IS_VALLEYVIEW(dev)) {
89b667f8 3538 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
ab1f90f9
JN		 3539 intel_encoder->pre_enable = vlv_pre_enable_dp;
3540 intel_encoder->enable = vlv_enable_dp;
3541 } else {
3542 intel_encoder->pre_enable = intel_pre_enable_dp;
3543 intel_encoder->enable = intel_enable_dp;
3544 }
f0fec3f2 3545
174edf1f 3546 intel_dig_port->port = port;
f0fec3f2
PZ		 3547 intel_dig_port->dp.output_reg = output_reg;
3548
00c09d70 3549 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 3550 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3551 intel_encoder->cloneable = false;
3552 intel_encoder->hot_plug = intel_dp_hot_plug;
3553
15b1d171
PZ		 3554 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3555 drm_encoder_cleanup(encoder);
3556 kfree(intel_dig_port);
b2f246a8 3557 kfree(intel_connector);
15b1d171 3558 }
f0fec3f2 3559}
Linux kernel - Deliverables
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