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drm/i915/dp: split edp_panel_vdd_on() for reuse
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
cfcb0fc9
JB		 67/**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74static bool is_edp(struct intel_dp *intel_dp)
75{
da63a9f2
PZ		 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 79}
80
68b4d824 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 82{
68b4d824
ID		 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 86}
87
df0e9248
CW		 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89{
fa90ecef 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 91}
92
ea5b213a 93static void intel_dp_link_down(struct intel_dp *intel_dp);
adddaaf4 94static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780
DV		 95static void edp_panel_vdd_on(struct intel_dp *intel_dp);
96static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 97
a4fc5ed6 98static int
ea5b213a 99intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 100{
7183dc29 101 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 102 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 103
104 switch (max_link_bw) {
105 case DP_LINK_BW_1_62:
106 case DP_LINK_BW_2_7:
107 break;
d4eead50 108 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
06ea66b6
TP		 109 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
110 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
111 max_link_bw = DP_LINK_BW_5_4;
112 else
113 max_link_bw = DP_LINK_BW_2_7;
d4eead50 114 break;
a4fc5ed6 115 default:
d4eead50
ID		 116 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
117 max_link_bw);
a4fc5ed6
KP		 118 max_link_bw = DP_LINK_BW_1_62;
119 break;
120 }
121 return max_link_bw;
122}
123
cd9dde44
AJ		 124/*
125 * The units on the numbers in the next two are... bizarre. Examples will
126 * make it clearer; this one parallels an example in the eDP spec.
127 *
128 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
129 *
130 * 270000 * 1 * 8 / 10 == 216000
131 *
132 * The actual data capacity of that configuration is 2.16Gbit/s, so the
133 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
134 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
135 * 119000. At 18bpp that's 2142000 kilobits per second.
136 *
137 * Thus the strange-looking division by 10 in intel_dp_link_required, to
138 * get the result in decakilobits instead of kilobits.
139 */
140
a4fc5ed6 141static int
c898261c 142intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 143{
cd9dde44 144 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 145}
146
fe27d53e
DA		 147static int
148intel_dp_max_data_rate(int max_link_clock, int max_lanes)
149{
150 return (max_link_clock * max_lanes * 8) / 10;
151}
152
c19de8eb 153static enum drm_mode_status
a4fc5ed6
KP		 154intel_dp_mode_valid(struct drm_connector *connector,
155 struct drm_display_mode *mode)
156{
df0e9248 157 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 158 struct intel_connector *intel_connector = to_intel_connector(connector);
159 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 160 int target_clock = mode->clock;
161 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 162
dd06f90e
JN		 163 if (is_edp(intel_dp) && fixed_mode) {
164 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 165 return MODE_PANEL;
166
dd06f90e 167 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 168 return MODE_PANEL;
03afc4a2
DV		 169
170 target_clock = fixed_mode->clock;
7de56f43
ZY		 171 }
172
36008365
DV		 173 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
174 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
175
176 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
177 mode_rate = intel_dp_link_required(target_clock, 18);
178
179 if (mode_rate > max_rate)
c4867936 180 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 181
182 if (mode->clock < 10000)
183 return MODE_CLOCK_LOW;
184
0af78a2b
DV		 185 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
186 return MODE_H_ILLEGAL;
187
a4fc5ed6
KP		 188 return MODE_OK;
189}
190
191static uint32_t
192pack_aux(uint8_t *src, int src_bytes)
193{
194 int i;
195 uint32_t v = 0;
196
197 if (src_bytes > 4)
198 src_bytes = 4;
199 for (i = 0; i < src_bytes; i++)
200 v |= ((uint32_t) src[i]) << ((3-i) * 8);
201 return v;
202}
203
204static void
205unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
206{
207 int i;
208 if (dst_bytes > 4)
209 dst_bytes = 4;
210 for (i = 0; i < dst_bytes; i++)
211 dst[i] = src >> ((3-i) * 8);
212}
213
fb0f8fbf
KP		 214/* hrawclock is 1/4 the FSB frequency */
215static int
216intel_hrawclk(struct drm_device *dev)
217{
218 struct drm_i915_private *dev_priv = dev->dev_private;
219 uint32_t clkcfg;
220
9473c8f4
VP		 221 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
222 if (IS_VALLEYVIEW(dev))
223 return 200;
224
fb0f8fbf
KP		 225 clkcfg = I915_READ(CLKCFG);
226 switch (clkcfg & CLKCFG_FSB_MASK) {
227 case CLKCFG_FSB_400:
228 return 100;
229 case CLKCFG_FSB_533:
230 return 133;
231 case CLKCFG_FSB_667:
232 return 166;
233 case CLKCFG_FSB_800:
234 return 200;
235 case CLKCFG_FSB_1067:
236 return 266;
237 case CLKCFG_FSB_1333:
238 return 333;
239 /* these two are just a guess; one of them might be right */
240 case CLKCFG_FSB_1600:
241 case CLKCFG_FSB_1600_ALT:
242 return 400;
243 default:
244 return 133;
245 }
246}
247
bf13e81b
JN		 248static void
249intel_dp_init_panel_power_sequencer(struct drm_device *dev,
250 struct intel_dp *intel_dp,
251 struct edp_power_seq *out);
252static void
253intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
254 struct intel_dp *intel_dp,
255 struct edp_power_seq *out);
256
257static enum pipe
258vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
259{
260 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
261 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
262 struct drm_device *dev = intel_dig_port->base.base.dev;
263 struct drm_i915_private *dev_priv = dev->dev_private;
264 enum port port = intel_dig_port->port;
265 enum pipe pipe;
266
267 /* modeset should have pipe */
268 if (crtc)
269 return to_intel_crtc(crtc)->pipe;
270
271 /* init time, try to find a pipe with this port selected */
272 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
273 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
274 PANEL_PORT_SELECT_MASK;
275 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
276 return pipe;
277 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
278 return pipe;
279 }
280
281 /* shrug */
282 return PIPE_A;
283}
284
285static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
286{
287 struct drm_device *dev = intel_dp_to_dev(intel_dp);
288
289 if (HAS_PCH_SPLIT(dev))
290 return PCH_PP_CONTROL;
291 else
292 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
293}
294
295static u32 _pp_stat_reg(struct intel_dp *intel_dp)
296{
297 struct drm_device *dev = intel_dp_to_dev(intel_dp);
298
299 if (HAS_PCH_SPLIT(dev))
300 return PCH_PP_STATUS;
301 else
302 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
303}
304
4be73780 305static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 306{
30add22d 307 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 308 struct drm_i915_private *dev_priv = dev->dev_private;
309
bf13e81b 310 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 311}
312
4be73780 313static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 314{
30add22d 315 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 316 struct drm_i915_private *dev_priv = dev->dev_private;
317
bf13e81b 318 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 319}
320
9b984dae
KP		 321static void
322intel_dp_check_edp(struct intel_dp *intel_dp)
323{
30add22d 324 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 325 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 326
9b984dae
KP		 327 if (!is_edp(intel_dp))
328 return;
453c5420 329
4be73780 330 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 331 WARN(1, "eDP powered off while attempting aux channel communication.\n");
332 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 333 I915_READ(_pp_stat_reg(intel_dp)),
334 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 335 }
336}
337
9ee32fea
DV		 338static uint32_t
339intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
340{
341 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
342 struct drm_device *dev = intel_dig_port->base.base.dev;
343 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 344 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 345 uint32_t status;
346 bool done;
347
ef04f00d 348#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 349 if (has_aux_irq)
b18ac466 350 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 351 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 352 else
353 done = wait_for_atomic(C, 10) == 0;
354 if (!done)
355 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
356 has_aux_irq);
357#undef C
358
359 return status;
360}
361
ec5b01dd 362static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 363{
174edf1f
PZ		 364 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
365 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 366
ec5b01dd
DL		 367 /*
368 * The clock divider is based off the hrawclk, and would like to run at
369 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 370 */
ec5b01dd
DL		 371 return index ? 0 : intel_hrawclk(dev) / 2;
372}
373
374static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
375{
376 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
377 struct drm_device *dev = intel_dig_port->base.base.dev;
378
379 if (index)
380 return 0;
381
382 if (intel_dig_port->port == PORT_A) {
383 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 384 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 385 else
b84a1cf8 386 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 387 } else {
388 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
389 }
390}
391
392static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
393{
394 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
395 struct drm_device *dev = intel_dig_port->base.base.dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
397
398 if (intel_dig_port->port == PORT_A) {
399 if (index)
400 return 0;
401 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 402 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
403 /* Workaround for non-ULT HSW */
bc86625a
CW		 404 switch (index) {
405 case 0: return 63;
406 case 1: return 72;
407 default: return 0;
408 }
ec5b01dd 409 } else {
bc86625a 410 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 411 }
b84a1cf8
RV		 412}
413
ec5b01dd
DL		 414static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
415{
416 return index ? 0 : 100;
417}
418
5ed12a19
DL		 419static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
420 bool has_aux_irq,
421 int send_bytes,
422 uint32_t aux_clock_divider)
423{
424 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
425 struct drm_device *dev = intel_dig_port->base.base.dev;
426 uint32_t precharge, timeout;
427
428 if (IS_GEN6(dev))
429 precharge = 3;
430 else
431 precharge = 5;
432
433 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
434 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
435 else
436 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
437
438 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 439 DP_AUX_CH_CTL_DONE |
5ed12a19 440 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 441 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 442 timeout |
788d4433 443 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 444 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
445 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 446 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 447}
448
b84a1cf8
RV		 449static int
450intel_dp_aux_ch(struct intel_dp *intel_dp,
451 uint8_t *send, int send_bytes,
452 uint8_t *recv, int recv_size)
453{
454 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
455 struct drm_device *dev = intel_dig_port->base.base.dev;
456 struct drm_i915_private *dev_priv = dev->dev_private;
457 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
458 uint32_t ch_data = ch_ctl + 4;
bc86625a 459 uint32_t aux_clock_divider;
b84a1cf8
RV		 460 int i, ret, recv_bytes;
461 uint32_t status;
5ed12a19 462 int try, clock = 0;
4e6b788c 463 bool has_aux_irq = HAS_AUX_IRQ(dev);
b84a1cf8
RV		 464
465 /* dp aux is extremely sensitive to irq latency, hence request the
466 * lowest possible wakeup latency and so prevent the cpu from going into
467 * deep sleep states.
468 */
469 pm_qos_update_request(&dev_priv->pm_qos, 0);
470
471 intel_dp_check_edp(intel_dp);
5eb08b69 472
c67a470b
PZ		 473 intel_aux_display_runtime_get(dev_priv);
474
11bee43e
JB		 475 /* Try to wait for any previous AUX channel activity */
476 for (try = 0; try < 3; try++) {
ef04f00d 477 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 478 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
479 break;
480 msleep(1);
481 }
482
483 if (try == 3) {
484 WARN(1, "dp_aux_ch not started status 0x%08x\n",
485 I915_READ(ch_ctl));
9ee32fea
DV		 486 ret = -EBUSY;
487 goto out;
4f7f7b7e
CW		 488 }
489
46a5ae9f
PZ		 490 /* Only 5 data registers! */
491 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
492 ret = -E2BIG;
493 goto out;
494 }
495
ec5b01dd 496 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 497 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
498 has_aux_irq,
499 send_bytes,
500 aux_clock_divider);
5ed12a19 501
bc86625a
CW		 502 /* Must try at least 3 times according to DP spec */
503 for (try = 0; try < 5; try++) {
504 /* Load the send data into the aux channel data registers */
505 for (i = 0; i < send_bytes; i += 4)
506 I915_WRITE(ch_data + i,
507 pack_aux(send + i, send_bytes - i));
508
509 /* Send the command and wait for it to complete */
5ed12a19 510 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 511
512 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
513
514 /* Clear done status and any errors */
515 I915_WRITE(ch_ctl,
516 status |
517 DP_AUX_CH_CTL_DONE |
518 DP_AUX_CH_CTL_TIME_OUT_ERROR |
519 DP_AUX_CH_CTL_RECEIVE_ERROR);
520
521 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
522 DP_AUX_CH_CTL_RECEIVE_ERROR))
523 continue;
524 if (status & DP_AUX_CH_CTL_DONE)
525 break;
526 }
4f7f7b7e 527 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 528 break;
529 }
530
a4fc5ed6 531 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 532 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 533 ret = -EBUSY;
534 goto out;
a4fc5ed6
KP		 535 }
536
537 /* Check for timeout or receive error.
538 * Timeouts occur when the sink is not connected
539 */
a5b3da54 540 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 541 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 542 ret = -EIO;
543 goto out;
a5b3da54 544 }
1ae8c0a5
KP		 545
546 /* Timeouts occur when the device isn't connected, so they're
547 * "normal" -- don't fill the kernel log with these */
a5b3da54 548 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 549 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 550 ret = -ETIMEDOUT;
551 goto out;
a4fc5ed6
KP		 552 }
553
554 /* Unload any bytes sent back from the other side */
555 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
556 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 557 if (recv_bytes > recv_size)
558 recv_bytes = recv_size;
0206e353 559
4f7f7b7e
CW		 560 for (i = 0; i < recv_bytes; i += 4)
561 unpack_aux(I915_READ(ch_data + i),
562 recv + i, recv_bytes - i);
a4fc5ed6 563
9ee32fea
DV		 564 ret = recv_bytes;
565out:
566 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 567 intel_aux_display_runtime_put(dev_priv);
9ee32fea
DV		 568
569 return ret;
a4fc5ed6
KP		 570}
571
572/* Write data to the aux channel in native mode */
573static int
ea5b213a 574intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 575 uint16_t address, uint8_t *send, int send_bytes)
576{
577 int ret;
578 uint8_t msg[20];
579 int msg_bytes;
580 uint8_t ack;
f51a44b9 581 int retry;
a4fc5ed6 582
46a5ae9f
PZ		 583 if (WARN_ON(send_bytes > 16))
584 return -E2BIG;
585
9b984dae 586 intel_dp_check_edp(intel_dp);
6b27f7f0 587 msg[0] = DP_AUX_NATIVE_WRITE << 4;
a4fc5ed6 588 msg[1] = address >> 8;
eebc863e 589 msg[2] = address & 0xff;
a4fc5ed6
KP		 590 msg[3] = send_bytes - 1;
591 memcpy(&msg[4], send, send_bytes);
592 msg_bytes = send_bytes + 4;
f51a44b9 593 for (retry = 0; retry < 7; retry++) {
ea5b213a 594 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 595 if (ret < 0)
596 return ret;
6b27f7f0
TR		 597 ack >>= 4;
598 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
f51a44b9 599 return send_bytes;
6b27f7f0 600 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
04eada25 601 usleep_range(400, 500);
a4fc5ed6 602 else
a5b3da54 603 return -EIO;
a4fc5ed6 604 }
f51a44b9
JN		 605
606 DRM_ERROR("too many retries, giving up\n");
607 return -EIO;
a4fc5ed6
KP		 608}
609
610/* Write a single byte to the aux channel in native mode */
611static int
ea5b213a 612intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 613 uint16_t address, uint8_t byte)
614{
ea5b213a 615 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 616}
617
618/* read bytes from a native aux channel */
619static int
ea5b213a 620intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 621 uint16_t address, uint8_t *recv, int recv_bytes)
622{
623 uint8_t msg[4];
624 int msg_bytes;
625 uint8_t reply[20];
626 int reply_bytes;
627 uint8_t ack;
628 int ret;
f51a44b9 629 int retry;
a4fc5ed6 630
46a5ae9f
PZ		 631 if (WARN_ON(recv_bytes > 19))
632 return -E2BIG;
633
9b984dae 634 intel_dp_check_edp(intel_dp);
6b27f7f0 635 msg[0] = DP_AUX_NATIVE_READ << 4;
a4fc5ed6
KP		 636 msg[1] = address >> 8;
637 msg[2] = address & 0xff;
638 msg[3] = recv_bytes - 1;
639
640 msg_bytes = 4;
641 reply_bytes = recv_bytes + 1;
642
f51a44b9 643 for (retry = 0; retry < 7; retry++) {
ea5b213a 644 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 645 reply, reply_bytes);
a5b3da54
KP		 646 if (ret == 0)
647 return -EPROTO;
648 if (ret < 0)
a4fc5ed6 649 return ret;
6b27f7f0
TR		 650 ack = reply[0] >> 4;
651 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) {
a4fc5ed6
KP		 652 memcpy(recv, reply + 1, ret - 1);
653 return ret - 1;
654 }
6b27f7f0 655 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
04eada25 656 usleep_range(400, 500);
a4fc5ed6 657 else
a5b3da54 658 return -EIO;
a4fc5ed6 659 }
f51a44b9
JN		 660
661 DRM_ERROR("too many retries, giving up\n");
662 return -EIO;
a4fc5ed6
KP		 663}
664
665static int
ab2c0672
DA		 666intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
667 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 668{
ab2c0672 669 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 670 struct intel_dp *intel_dp = container_of(adapter,
671 struct intel_dp,
672 adapter);
ab2c0672
DA		 673 uint16_t address = algo_data->address;
674 uint8_t msg[5];
675 uint8_t reply[2];
8316f337 676 unsigned retry;
ab2c0672
DA		 677 int msg_bytes;
678 int reply_bytes;
679 int ret;
680
4be73780 681 edp_panel_vdd_on(intel_dp);
9b984dae 682 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 683 /* Set up the command byte */
684 if (mode & MODE_I2C_READ)
6b27f7f0 685 msg[0] = DP_AUX_I2C_READ << 4;
ab2c0672 686 else
6b27f7f0 687 msg[0] = DP_AUX_I2C_WRITE << 4;
ab2c0672
DA		 688
689 if (!(mode & MODE_I2C_STOP))
6b27f7f0 690 msg[0] |= DP_AUX_I2C_MOT << 4;
a4fc5ed6 691
ab2c0672
DA		 692 msg[1] = address >> 8;
693 msg[2] = address;
694
695 switch (mode) {
696 case MODE_I2C_WRITE:
697 msg[3] = 0;
698 msg[4] = write_byte;
699 msg_bytes = 5;
700 reply_bytes = 1;
701 break;
702 case MODE_I2C_READ:
703 msg[3] = 0;
704 msg_bytes = 4;
705 reply_bytes = 2;
706 break;
707 default:
708 msg_bytes = 3;
709 reply_bytes = 1;
710 break;
711 }
712
58c67ce9
JN		 713 /*
714 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
715 * required to retry at least seven times upon receiving AUX_DEFER
716 * before giving up the AUX transaction.
717 */
718 for (retry = 0; retry < 7; retry++) {
8316f337
DF		 719 ret = intel_dp_aux_ch(intel_dp,
720 msg, msg_bytes,
721 reply, reply_bytes);
ab2c0672 722 if (ret < 0) {
3ff99164 723 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
8a5e6aeb 724 goto out;
ab2c0672 725 }
8316f337 726
6b27f7f0
TR		 727 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
728 case DP_AUX_NATIVE_REPLY_ACK:
8316f337
DF		 729 /* I2C-over-AUX Reply field is only valid
730 * when paired with AUX ACK.
731 */
732 break;
6b27f7f0 733 case DP_AUX_NATIVE_REPLY_NACK:
8316f337 734 DRM_DEBUG_KMS("aux_ch native nack\n");
8a5e6aeb
PZ		 735 ret = -EREMOTEIO;
736 goto out;
6b27f7f0 737 case DP_AUX_NATIVE_REPLY_DEFER:
8d16f258
JN		 738 /*
739 * For now, just give more slack to branch devices. We
740 * could check the DPCD for I2C bit rate capabilities,
741 * and if available, adjust the interval. We could also
742 * be more careful with DP-to-Legacy adapters where a
743 * long legacy cable may force very low I2C bit rates.
744 */
745 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
746 DP_DWN_STRM_PORT_PRESENT)
747 usleep_range(500, 600);
748 else
749 usleep_range(300, 400);
8316f337
DF		 750 continue;
751 default:
752 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
753 reply[0]);
8a5e6aeb
PZ		 754 ret = -EREMOTEIO;
755 goto out;
8316f337
DF		 756 }
757
6b27f7f0
TR		 758 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
759 case DP_AUX_I2C_REPLY_ACK:
ab2c0672
DA		 760 if (mode == MODE_I2C_READ) {
761 *read_byte = reply[1];
762 }
8a5e6aeb
PZ		 763 ret = reply_bytes - 1;
764 goto out;
6b27f7f0 765 case DP_AUX_I2C_REPLY_NACK:
8316f337 766 DRM_DEBUG_KMS("aux_i2c nack\n");
8a5e6aeb
PZ		 767 ret = -EREMOTEIO;
768 goto out;
6b27f7f0 769 case DP_AUX_I2C_REPLY_DEFER:
8316f337 770 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 771 udelay(100);
772 break;
773 default:
8316f337 774 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
8a5e6aeb
PZ		 775 ret = -EREMOTEIO;
776 goto out;
ab2c0672
DA		 777 }
778 }
8316f337
DF		 779
780 DRM_ERROR("too many retries, giving up\n");
8a5e6aeb
PZ		 781 ret = -EREMOTEIO;
782
783out:
4be73780 784 edp_panel_vdd_off(intel_dp, false);
8a5e6aeb 785 return ret;
a4fc5ed6
KP		 786}
787
80f65de3
ID		 788static void
789intel_dp_connector_unregister(struct intel_connector *intel_connector)
790{
791 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
792
793 sysfs_remove_link(&intel_connector->base.kdev->kobj,
794 intel_dp->adapter.dev.kobj.name);
795 intel_connector_unregister(intel_connector);
796}
797
a4fc5ed6 798static int
ea5b213a 799intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 800 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 801{
0b5c541b
KP		 802 int ret;
803
d54e9d28 804 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 805 intel_dp->algo.running = false;
806 intel_dp->algo.address = 0;
807 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
808
0206e353 809 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 810 intel_dp->adapter.owner = THIS_MODULE;
811 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 812 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 813 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
814 intel_dp->adapter.algo_data = &intel_dp->algo;
80f65de3 815 intel_dp->adapter.dev.parent = intel_connector->base.dev->dev;
ea5b213a 816
0b5c541b 817 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
80f65de3
ID		 818 if (ret < 0)
819 return ret;
820
821 ret = sysfs_create_link(&intel_connector->base.kdev->kobj,
822 &intel_dp->adapter.dev.kobj,
823 intel_dp->adapter.dev.kobj.name);
824
825 if (ret < 0)
826 i2c_del_adapter(&intel_dp->adapter);
827
0b5c541b 828 return ret;
a4fc5ed6
KP		 829}
830
c6bb3538
DV		 831static void
832intel_dp_set_clock(struct intel_encoder *encoder,
833 struct intel_crtc_config *pipe_config, int link_bw)
834{
835 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 836 const struct dp_link_dpll *divisor = NULL;
837 int i, count = 0;
c6bb3538
DV		 838
839 if (IS_G4X(dev)) {
9dd4ffdf
CML		 840 divisor = gen4_dpll;
841 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 842 } else if (IS_HASWELL(dev)) {
843 /* Haswell has special-purpose DP DDI clocks. */
844 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 845 divisor = pch_dpll;
846 count = ARRAY_SIZE(pch_dpll);
c6bb3538 847 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 848 divisor = vlv_dpll;
849 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 850 }
9dd4ffdf
CML		 851
852 if (divisor && count) {
853 for (i = 0; i < count; i++) {
854 if (link_bw == divisor[i].link_bw) {
855 pipe_config->dpll = divisor[i].dpll;
856 pipe_config->clock_set = true;
857 break;
858 }
859 }
c6bb3538
DV		 860 }
861}
862
00c09d70 863bool
5bfe2ac0
DV		 864intel_dp_compute_config(struct intel_encoder *encoder,
865 struct intel_crtc_config *pipe_config)
a4fc5ed6 866{
5bfe2ac0 867 struct drm_device *dev = encoder->base.dev;
36008365 868 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 869 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 870 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 871 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 872 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 873 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 874 int lane_count, clock;
397fe157 875 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
06ea66b6
TP		 876 /* Conveniently, the link BW constants become indices with a shift...*/
877 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 878 int bpp, mode_rate;
06ea66b6 879 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 880 int link_avail, link_clock;
a4fc5ed6 881
bc7d38a4 882 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 883 pipe_config->has_pch_encoder = true;
884
03afc4a2 885 pipe_config->has_dp_encoder = true;
a4fc5ed6 886
dd06f90e
JN		 887 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
888 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
889 adjusted_mode);
2dd24552
JB		 890 if (!HAS_PCH_SPLIT(dev))
891 intel_gmch_panel_fitting(intel_crtc, pipe_config,
892 intel_connector->panel.fitting_mode);
893 else
b074cec8
JB		 894 intel_pch_panel_fitting(intel_crtc, pipe_config,
895 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 896 }
897
cb1793ce 898 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 899 return false;
900
083f9560
DV		 901 DRM_DEBUG_KMS("DP link computation with max lane count %i "
902 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 903 max_lane_count, bws[max_clock],
904 adjusted_mode->crtc_clock);
083f9560 905
36008365
DV		 906 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
907 * bpc in between. */
3e7ca985 908 bpp = pipe_config->pipe_bpp;
6da7f10d
JN		 909 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
910 dev_priv->vbt.edp_bpp < bpp) {
7984211e
ID		 911 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
912 dev_priv->vbt.edp_bpp);
6da7f10d 913 bpp = dev_priv->vbt.edp_bpp;
7984211e 914 }
657445fe 915
36008365 916 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 917 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
918 bpp);
36008365 919
38aecea0
DV		 920 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
921 for (clock = 0; clock <= max_clock; clock++) {
36008365
DV		 922 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
923 link_avail = intel_dp_max_data_rate(link_clock,
924 lane_count);
925
926 if (mode_rate <= link_avail) {
927 goto found;
928 }
929 }
930 }
931 }
c4867936 932
36008365 933 return false;
3685a8f3 934
36008365 935found:
55bc60db
VS		 936 if (intel_dp->color_range_auto) {
937 /*
938 * See:
939 * CEA-861-E - 5.1 Default Encoding Parameters
940 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
941 */
18316c8c 942 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 943 intel_dp->color_range = DP_COLOR_RANGE_16_235;
944 else
945 intel_dp->color_range = 0;
946 }
947
3685a8f3 948 if (intel_dp->color_range)
50f3b016 949 pipe_config->limited_color_range = true;
a4fc5ed6 950
36008365
DV		 951 intel_dp->link_bw = bws[clock];
952 intel_dp->lane_count = lane_count;
657445fe 953 pipe_config->pipe_bpp = bpp;
ff9a6750 954 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 955
36008365
DV		 956 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
957 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 958 pipe_config->port_clock, bpp);
36008365
DV		 959 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
960 mode_rate, link_avail);
a4fc5ed6 961
03afc4a2 962 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 963 adjusted_mode->crtc_clock,
964 pipe_config->port_clock,
03afc4a2 965 &pipe_config->dp_m_n);
9d1a455b 966
c6bb3538
DV		 967 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
968
03afc4a2 969 return true;
a4fc5ed6
KP		 970}
971
7c62a164 972static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 973{
7c62a164
DV		 974 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
975 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
976 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 977 struct drm_i915_private *dev_priv = dev->dev_private;
978 u32 dpa_ctl;
979
ff9a6750 980 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 981 dpa_ctl = I915_READ(DP_A);
982 dpa_ctl &= ~DP_PLL_FREQ_MASK;
983
ff9a6750 984 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 985 /* For a long time we've carried around a ILK-DevA w/a for the
986 * 160MHz clock. If we're really unlucky, it's still required.
987 */
988 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 989 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 990 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 991 } else {
992 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 993 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 994 }
1ce17038 995
ea9b6006
DV		 996 I915_WRITE(DP_A, dpa_ctl);
997
998 POSTING_READ(DP_A);
999 udelay(500);
1000}
1001
b934223d 1002static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 1003{
b934223d 1004 struct drm_device *dev = encoder->base.dev;
417e822d 1005 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1006 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1007 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1008 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1009 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1010
417e822d 1011 /*
1a2eb460 1012 * There are four kinds of DP registers:
417e822d
KP		 1013 *
1014 * IBX PCH
1a2eb460
KP		 1015 * SNB CPU
1016 * IVB CPU
417e822d
KP		 1017 * CPT PCH
1018 *
1019 * IBX PCH and CPU are the same for almost everything,
1020 * except that the CPU DP PLL is configured in this
1021 * register
1022 *
1023 * CPT PCH is quite different, having many bits moved
1024 * to the TRANS_DP_CTL register instead. That
1025 * configuration happens (oddly) in ironlake_pch_enable
1026 */
9c9e7927 1027
417e822d
KP		 1028 /* Preserve the BIOS-computed detected bit. This is
1029 * supposed to be read-only.
1030 */
1031 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1032
417e822d 1033 /* Handle DP bits in common between all three register formats */
417e822d 1034 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1035 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1036
e0dac65e
WF		 1037 if (intel_dp->has_audio) {
1038 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1039 pipe_name(crtc->pipe));
ea5b213a 1040 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1041 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1042 }
247d89f6 1043
417e822d 1044 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1045
bc7d38a4 1046 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1047 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1048 intel_dp->DP |= DP_SYNC_HS_HIGH;
1049 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1050 intel_dp->DP |= DP_SYNC_VS_HIGH;
1051 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1052
6aba5b6c 1053 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1054 intel_dp->DP |= DP_ENHANCED_FRAMING;
1055
7c62a164 1056 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1057 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1058 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1059 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1060
1061 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1062 intel_dp->DP |= DP_SYNC_HS_HIGH;
1063 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1064 intel_dp->DP |= DP_SYNC_VS_HIGH;
1065 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1066
6aba5b6c 1067 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1068 intel_dp->DP |= DP_ENHANCED_FRAMING;
1069
7c62a164 1070 if (crtc->pipe == 1)
417e822d 1071 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 1072 } else {
1073 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1074 }
ea9b6006 1075
bc7d38a4 1076 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 1077 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 1078}
1079
ffd6749d
PZ		 1080#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1081#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1082
1a5ef5b7
PZ		 1083#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1084#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1085
ffd6749d
PZ		 1086#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1087#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1088
4be73780 1089static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1090 u32 mask,
1091 u32 value)
bd943159 1092{
30add22d 1093 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1094 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1095 u32 pp_stat_reg, pp_ctrl_reg;
1096
bf13e81b
JN		 1097 pp_stat_reg = _pp_stat_reg(intel_dp);
1098 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1099
99ea7127 1100 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1101 mask, value,
1102 I915_READ(pp_stat_reg),
1103 I915_READ(pp_ctrl_reg));
32ce697c 1104
453c5420 1105 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1106 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1107 I915_READ(pp_stat_reg),
1108 I915_READ(pp_ctrl_reg));
32ce697c 1109 }
54c136d4
CW		 1110
1111 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1112}
32ce697c 1113
4be73780 1114static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1115{
1116 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1117 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1118}
1119
4be73780 1120static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1121{
1122 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1123 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1124}
1125
4be73780 1126static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1127{
1128 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1129
1130 /* When we disable the VDD override bit last we have to do the manual
1131 * wait. */
1132 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1133 intel_dp->panel_power_cycle_delay);
1134
4be73780 1135 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1136}
1137
4be73780 1138static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1139{
1140 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1141 intel_dp->backlight_on_delay);
1142}
1143
4be73780 1144static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1145{
1146 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1147 intel_dp->backlight_off_delay);
1148}
99ea7127 1149
832dd3c1
KP		 1150/* Read the current pp_control value, unlocking the register if it
1151 * is locked
1152 */
1153
453c5420 1154static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1155{
453c5420
JB		 1156 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1157 struct drm_i915_private *dev_priv = dev->dev_private;
1158 u32 control;
832dd3c1 1159
bf13e81b 1160 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1161 control &= ~PANEL_UNLOCK_MASK;
1162 control |= PANEL_UNLOCK_REGS;
1163 return control;
bd943159
KP		 1164}
1165
adddaaf4 1166static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1167{
30add22d 1168 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1169 struct drm_i915_private *dev_priv = dev->dev_private;
1170 u32 pp;
453c5420 1171 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1172 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1173
97af61f5 1174 if (!is_edp(intel_dp))
adddaaf4 1175 return false;
bd943159
KP		 1176
1177 intel_dp->want_panel_vdd = true;
99ea7127 1178
4be73780 1179 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1180 return need_to_disable;
b0665d57 1181
e9cb81a2
PZ		 1182 intel_runtime_pm_get(dev_priv);
1183
b0665d57 1184 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1185
4be73780
DV		 1186 if (!edp_have_panel_power(intel_dp))
1187 wait_panel_power_cycle(intel_dp);
99ea7127 1188
453c5420 1189 pp = ironlake_get_pp_control(intel_dp);
5d613501 1190 pp |= EDP_FORCE_VDD;
ebf33b18 1191
bf13e81b
JN		 1192 pp_stat_reg = _pp_stat_reg(intel_dp);
1193 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1194
1195 I915_WRITE(pp_ctrl_reg, pp);
1196 POSTING_READ(pp_ctrl_reg);
1197 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1198 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1199 /*
1200 * If the panel wasn't on, delay before accessing aux channel
1201 */
4be73780 1202 if (!edp_have_panel_power(intel_dp)) {
bd943159 1203 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1204 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1205 }
adddaaf4
JN		 1206
1207 return need_to_disable;
1208}
1209
1210static void edp_panel_vdd_on(struct intel_dp *intel_dp)
1211{
1212 if (is_edp(intel_dp)) {
1213 bool vdd = _edp_panel_vdd_on(intel_dp);
1214
1215 WARN(!vdd, "eDP VDD already requested on\n");
1216 }
5d613501
JB		 1217}
1218
4be73780 1219static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1220{
30add22d 1221 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1222 struct drm_i915_private *dev_priv = dev->dev_private;
1223 u32 pp;
453c5420 1224 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1225
a0e99e68
DV		 1226 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1227
4be73780 1228 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
b0665d57
PZ		 1229 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1230
453c5420 1231 pp = ironlake_get_pp_control(intel_dp);
bd943159 1232 pp &= ~EDP_FORCE_VDD;
bd943159 1233
9f08ef59
PZ		 1234 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1235 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1236
1237 I915_WRITE(pp_ctrl_reg, pp);
1238 POSTING_READ(pp_ctrl_reg);
99ea7127 1239
453c5420
JB		 1240 /* Make sure sequencer is idle before allowing subsequent activity */
1241 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1242 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1243
1244 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1245 intel_dp->last_power_cycle = jiffies;
e9cb81a2
PZ		 1246
1247 intel_runtime_pm_put(dev_priv);
bd943159
KP		 1248 }
1249}
5d613501 1250
4be73780 1251static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1252{
1253 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1254 struct intel_dp, panel_vdd_work);
30add22d 1255 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1256
627f7675 1257 mutex_lock(&dev->mode_config.mutex);
4be73780 1258 edp_panel_vdd_off_sync(intel_dp);
627f7675 1259 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1260}
1261
4be73780 1262static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1263{
97af61f5
KP		 1264 if (!is_edp(intel_dp))
1265 return;
5d613501 1266
bd943159 1267 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1268
bd943159
KP		 1269 intel_dp->want_panel_vdd = false;
1270
1271 if (sync) {
4be73780 1272 edp_panel_vdd_off_sync(intel_dp);
bd943159
KP		 1273 } else {
1274 /*
1275 * Queue the timer to fire a long
1276 * time from now (relative to the power down delay)
1277 * to keep the panel power up across a sequence of operations
1278 */
1279 schedule_delayed_work(&intel_dp->panel_vdd_work,
1280 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1281 }
5d613501
JB		 1282}
1283
4be73780 1284void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1285{
30add22d 1286 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1287 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1288 u32 pp;
453c5420 1289 u32 pp_ctrl_reg;
9934c132 1290
97af61f5 1291 if (!is_edp(intel_dp))
bd943159 1292 return;
99ea7127
KP		 1293
1294 DRM_DEBUG_KMS("Turn eDP power on\n");
1295
4be73780 1296 if (edp_have_panel_power(intel_dp)) {
99ea7127 1297 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1298 return;
99ea7127 1299 }
9934c132 1300
4be73780 1301 wait_panel_power_cycle(intel_dp);
37c6c9b0 1302
bf13e81b 1303 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1304 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1305 if (IS_GEN5(dev)) {
1306 /* ILK workaround: disable reset around power sequence */
1307 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1308 I915_WRITE(pp_ctrl_reg, pp);
1309 POSTING_READ(pp_ctrl_reg);
05ce1a49 1310 }
37c6c9b0 1311
1c0ae80a 1312 pp |= POWER_TARGET_ON;
99ea7127
KP		 1313 if (!IS_GEN5(dev))
1314 pp |= PANEL_POWER_RESET;
1315
453c5420
JB		 1316 I915_WRITE(pp_ctrl_reg, pp);
1317 POSTING_READ(pp_ctrl_reg);
9934c132 1318
4be73780 1319 wait_panel_on(intel_dp);
dce56b3c 1320 intel_dp->last_power_on = jiffies;
9934c132 1321
05ce1a49
KP		 1322 if (IS_GEN5(dev)) {
1323 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1324 I915_WRITE(pp_ctrl_reg, pp);
1325 POSTING_READ(pp_ctrl_reg);
05ce1a49 1326 }
9934c132
JB		 1327}
1328
4be73780 1329void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1330{
30add22d 1331 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1332 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1333 u32 pp;
453c5420 1334 u32 pp_ctrl_reg;
9934c132 1335
97af61f5
KP		 1336 if (!is_edp(intel_dp))
1337 return;
37c6c9b0 1338
99ea7127 1339 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1340
4be73780 1341 edp_wait_backlight_off(intel_dp);
dce56b3c 1342
453c5420 1343 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1344 /* We need to switch off panel power _and_ force vdd, for otherwise some
1345 * panels get very unhappy and cease to work. */
b3064154
PJ		 1346 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1347 EDP_BLC_ENABLE);
453c5420 1348
bf13e81b 1349 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1350
1351 I915_WRITE(pp_ctrl_reg, pp);
1352 POSTING_READ(pp_ctrl_reg);
9934c132 1353
dce56b3c 1354 intel_dp->last_power_cycle = jiffies;
4be73780 1355 wait_panel_off(intel_dp);
9934c132
JB		 1356}
1357
4be73780 1358void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1359{
da63a9f2
PZ		 1360 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1361 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1362 struct drm_i915_private *dev_priv = dev->dev_private;
1363 u32 pp;
453c5420 1364 u32 pp_ctrl_reg;
32f9d658 1365
f01eca2e
KP		 1366 if (!is_edp(intel_dp))
1367 return;
1368
28c97730 1369 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1370 /*
1371 * If we enable the backlight right away following a panel power
1372 * on, we may see slight flicker as the panel syncs with the eDP
1373 * link. So delay a bit to make sure the image is solid before
1374 * allowing it to appear.
1375 */
4be73780 1376 wait_backlight_on(intel_dp);
453c5420 1377 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1378 pp |= EDP_BLC_ENABLE;
453c5420 1379
bf13e81b 1380 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1381
1382 I915_WRITE(pp_ctrl_reg, pp);
1383 POSTING_READ(pp_ctrl_reg);
035aa3de 1384
752aa88a 1385 intel_panel_enable_backlight(intel_dp->attached_connector);
32f9d658
ZW		 1386}
1387
4be73780 1388void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1389{
30add22d 1390 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1391 struct drm_i915_private *dev_priv = dev->dev_private;
1392 u32 pp;
453c5420 1393 u32 pp_ctrl_reg;
32f9d658 1394
f01eca2e
KP		 1395 if (!is_edp(intel_dp))
1396 return;
1397
752aa88a 1398 intel_panel_disable_backlight(intel_dp->attached_connector);
035aa3de 1399
28c97730 1400 DRM_DEBUG_KMS("\n");
453c5420 1401 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1402 pp &= ~EDP_BLC_ENABLE;
453c5420 1403
bf13e81b 1404 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1405
1406 I915_WRITE(pp_ctrl_reg, pp);
1407 POSTING_READ(pp_ctrl_reg);
dce56b3c 1408 intel_dp->last_backlight_off = jiffies;
32f9d658 1409}
a4fc5ed6 1410
2bd2ad64 1411static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1412{
da63a9f2
PZ		 1413 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1414 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1415 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1416 struct drm_i915_private *dev_priv = dev->dev_private;
1417 u32 dpa_ctl;
1418
2bd2ad64
DV		 1419 assert_pipe_disabled(dev_priv,
1420 to_intel_crtc(crtc)->pipe);
1421
d240f20f
JB		 1422 DRM_DEBUG_KMS("\n");
1423 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1424 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1425 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1426
1427 /* We don't adjust intel_dp->DP while tearing down the link, to
1428 * facilitate link retraining (e.g. after hotplug). Hence clear all
1429 * enable bits here to ensure that we don't enable too much. */
1430 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1431 intel_dp->DP |= DP_PLL_ENABLE;
1432 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1433 POSTING_READ(DP_A);
1434 udelay(200);
d240f20f
JB		 1435}
1436
2bd2ad64 1437static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1438{
da63a9f2
PZ		 1439 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1440 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1441 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1442 struct drm_i915_private *dev_priv = dev->dev_private;
1443 u32 dpa_ctl;
1444
2bd2ad64
DV		 1445 assert_pipe_disabled(dev_priv,
1446 to_intel_crtc(crtc)->pipe);
1447
d240f20f 1448 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1449 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1450 "dp pll off, should be on\n");
1451 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1452
1453 /* We can't rely on the value tracked for the DP register in
1454 * intel_dp->DP because link_down must not change that (otherwise link
1455 * re-training will fail. */
298b0b39 1456 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1457 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1458 POSTING_READ(DP_A);
d240f20f
JB		 1459 udelay(200);
1460}
1461
c7ad3810 1462/* If the sink supports it, try to set the power state appropriately */
c19b0669 1463void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1464{
1465 int ret, i;
1466
1467 /* Should have a valid DPCD by this point */
1468 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1469 return;
1470
1471 if (mode != DRM_MODE_DPMS_ON) {
1472 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1473 DP_SET_POWER_D3);
1474 if (ret != 1)
1475 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1476 } else {
1477 /*
1478 * When turning on, we need to retry for 1ms to give the sink
1479 * time to wake up.
1480 */
1481 for (i = 0; i < 3; i++) {
1482 ret = intel_dp_aux_native_write_1(intel_dp,
1483 DP_SET_POWER,
1484 DP_SET_POWER_D0);
1485 if (ret == 1)
1486 break;
1487 msleep(1);
1488 }
1489 }
1490}
1491
19d8fe15
DV		 1492static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1493 enum pipe *pipe)
d240f20f 1494{
19d8fe15 1495 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1496 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1497 struct drm_device *dev = encoder->base.dev;
1498 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1499 enum intel_display_power_domain power_domain;
1500 u32 tmp;
1501
1502 power_domain = intel_display_port_power_domain(encoder);
1503 if (!intel_display_power_enabled(dev_priv, power_domain))
1504 return false;
1505
1506 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1507
1508 if (!(tmp & DP_PORT_EN))
1509 return false;
1510
bc7d38a4 1511 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1512 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1513 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1514 *pipe = PORT_TO_PIPE(tmp);
1515 } else {
1516 u32 trans_sel;
1517 u32 trans_dp;
1518 int i;
1519
1520 switch (intel_dp->output_reg) {
1521 case PCH_DP_B:
1522 trans_sel = TRANS_DP_PORT_SEL_B;
1523 break;
1524 case PCH_DP_C:
1525 trans_sel = TRANS_DP_PORT_SEL_C;
1526 break;
1527 case PCH_DP_D:
1528 trans_sel = TRANS_DP_PORT_SEL_D;
1529 break;
1530 default:
1531 return true;
1532 }
1533
1534 for_each_pipe(i) {
1535 trans_dp = I915_READ(TRANS_DP_CTL(i));
1536 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1537 *pipe = i;
1538 return true;
1539 }
1540 }
19d8fe15 1541
4a0833ec
DV		 1542 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1543 intel_dp->output_reg);
1544 }
d240f20f 1545
19d8fe15
DV		 1546 return true;
1547}
d240f20f 1548
045ac3b5
JB		 1549static void intel_dp_get_config(struct intel_encoder *encoder,
1550 struct intel_crtc_config *pipe_config)
1551{
1552 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1553 u32 tmp, flags = 0;
63000ef6
XZ		 1554 struct drm_device *dev = encoder->base.dev;
1555 struct drm_i915_private *dev_priv = dev->dev_private;
1556 enum port port = dp_to_dig_port(intel_dp)->port;
1557 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1558 int dotclock;
045ac3b5 1559
63000ef6
XZ		 1560 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1561 tmp = I915_READ(intel_dp->output_reg);
1562 if (tmp & DP_SYNC_HS_HIGH)
1563 flags |= DRM_MODE_FLAG_PHSYNC;
1564 else
1565 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1566
63000ef6
XZ		 1567 if (tmp & DP_SYNC_VS_HIGH)
1568 flags |= DRM_MODE_FLAG_PVSYNC;
1569 else
1570 flags |= DRM_MODE_FLAG_NVSYNC;
1571 } else {
1572 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1573 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1574 flags |= DRM_MODE_FLAG_PHSYNC;
1575 else
1576 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1577
63000ef6
XZ		 1578 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1579 flags |= DRM_MODE_FLAG_PVSYNC;
1580 else
1581 flags |= DRM_MODE_FLAG_NVSYNC;
1582 }
045ac3b5
JB		 1583
1584 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1585
eb14cb74
VS		 1586 pipe_config->has_dp_encoder = true;
1587
1588 intel_dp_get_m_n(crtc, pipe_config);
1589
18442d08 1590 if (port == PORT_A) {
f1f644dc
JB		 1591 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1592 pipe_config->port_clock = 162000;
1593 else
1594 pipe_config->port_clock = 270000;
1595 }
18442d08
VS		 1596
1597 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1598 &pipe_config->dp_m_n);
1599
1600 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1601 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1602
241bfc38 1603 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1604
c6cd2ee2
JN		 1605 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1606 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1607 /*
1608 * This is a big fat ugly hack.
1609 *
1610 * Some machines in UEFI boot mode provide us a VBT that has 18
1611 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1612 * unknown we fail to light up. Yet the same BIOS boots up with
1613 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1614 * max, not what it tells us to use.
1615 *
1616 * Note: This will still be broken if the eDP panel is not lit
1617 * up by the BIOS, and thus we can't get the mode at module
1618 * load.
1619 */
1620 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1621 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1622 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1623 }
045ac3b5
JB		 1624}
1625
a031d709 1626static bool is_edp_psr(struct drm_device *dev)
2293bb5c 1627{
a031d709
RV		 1628 struct drm_i915_private *dev_priv = dev->dev_private;
1629
1630 return dev_priv->psr.sink_support;
2293bb5c
SK		 1631}
1632
2b28bb1b
RV		 1633static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1634{
1635 struct drm_i915_private *dev_priv = dev->dev_private;
1636
18b5992c 1637 if (!HAS_PSR(dev))
2b28bb1b
RV		 1638 return false;
1639
18b5992c 1640 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1641}
1642
1643static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1644 struct edp_vsc_psr *vsc_psr)
1645{
1646 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1647 struct drm_device *dev = dig_port->base.base.dev;
1648 struct drm_i915_private *dev_priv = dev->dev_private;
1649 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1650 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1651 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1652 uint32_t *data = (uint32_t *) vsc_psr;
1653 unsigned int i;
1654
1655 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1656 the video DIP being updated before program video DIP data buffer
1657 registers for DIP being updated. */
1658 I915_WRITE(ctl_reg, 0);
1659 POSTING_READ(ctl_reg);
1660
1661 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1662 if (i < sizeof(struct edp_vsc_psr))
1663 I915_WRITE(data_reg + i, *data++);
1664 else
1665 I915_WRITE(data_reg + i, 0);
1666 }
1667
1668 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1669 POSTING_READ(ctl_reg);
1670}
1671
1672static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1673{
1674 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1675 struct drm_i915_private *dev_priv = dev->dev_private;
1676 struct edp_vsc_psr psr_vsc;
1677
1678 if (intel_dp->psr_setup_done)
1679 return;
1680
1681 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1682 memset(&psr_vsc, 0, sizeof(psr_vsc));
1683 psr_vsc.sdp_header.HB0 = 0;
1684 psr_vsc.sdp_header.HB1 = 0x7;
1685 psr_vsc.sdp_header.HB2 = 0x2;
1686 psr_vsc.sdp_header.HB3 = 0x8;
1687 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1688
1689 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1690 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1691 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1692
1693 intel_dp->psr_setup_done = true;
1694}
1695
1696static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1697{
1698 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1699 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1700 uint32_t aux_clock_divider;
2b28bb1b
RV		 1701 int precharge = 0x3;
1702 int msg_size = 5; /* Header(4) + Message(1) */
1703
ec5b01dd
DL		 1704 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1705
2b28bb1b
RV		 1706 /* Enable PSR in sink */
1707 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1708 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1709 DP_PSR_ENABLE &
1710 ~DP_PSR_MAIN_LINK_ACTIVE);
1711 else
1712 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1713 DP_PSR_ENABLE |
1714 DP_PSR_MAIN_LINK_ACTIVE);
1715
1716 /* Setup AUX registers */
18b5992c
BW		 1717 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1718 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1719 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1720 DP_AUX_CH_CTL_TIME_OUT_400us |
1721 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1722 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1723 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1724}
1725
1726static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1727{
1728 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1729 struct drm_i915_private *dev_priv = dev->dev_private;
1730 uint32_t max_sleep_time = 0x1f;
1731 uint32_t idle_frames = 1;
1732 uint32_t val = 0x0;
ed8546ac 1733 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2b28bb1b
RV		 1734
1735 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1736 val |= EDP_PSR_LINK_STANDBY;
1737 val |= EDP_PSR_TP2_TP3_TIME_0us;
1738 val |= EDP_PSR_TP1_TIME_0us;
1739 val |= EDP_PSR_SKIP_AUX_EXIT;
1740 } else
1741 val |= EDP_PSR_LINK_DISABLE;
1742
18b5992c 1743 I915_WRITE(EDP_PSR_CTL(dev), val |
ed8546ac 1744 IS_BROADWELL(dev) ? 0 : link_entry_time |
2b28bb1b
RV		 1745 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1746 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1747 EDP_PSR_ENABLE);
1748}
1749
3f51e471
RV		 1750static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1751{
1752 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1753 struct drm_device *dev = dig_port->base.base.dev;
1754 struct drm_i915_private *dev_priv = dev->dev_private;
1755 struct drm_crtc *crtc = dig_port->base.base.crtc;
1756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1757 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1758 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1759
a031d709
RV		 1760 dev_priv->psr.source_ok = false;
1761
18b5992c 1762 if (!HAS_PSR(dev)) {
3f51e471 1763 DRM_DEBUG_KMS("PSR not supported on this platform\n");
3f51e471
RV		 1764 return false;
1765 }
1766
1767 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1768 (dig_port->port != PORT_A)) {
1769 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1770 return false;
1771 }
1772
d330a953 1773 if (!i915.enable_psr) {
105b7c11 1774 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1775 return false;
1776 }
1777
cd234b0b
CW		 1778 crtc = dig_port->base.base.crtc;
1779 if (crtc == NULL) {
1780 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1781 return false;
1782 }
1783
1784 intel_crtc = to_intel_crtc(crtc);
20ddf665 1785 if (!intel_crtc_active(crtc)) {
3f51e471 1786 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1787 return false;
1788 }
1789
cd234b0b 1790 obj = to_intel_framebuffer(crtc->fb)->obj;
3f51e471
RV		 1791 if (obj->tiling_mode != I915_TILING_X ||
1792 obj->fence_reg == I915_FENCE_REG_NONE) {
1793 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1794 return false;
1795 }
1796
1797 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1798 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1799 return false;
1800 }
1801
1802 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1803 S3D_ENABLE) {
1804 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1805 return false;
1806 }
1807
ca73b4f0 1808 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1809 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1810 return false;
1811 }
1812
a031d709 1813 dev_priv->psr.source_ok = true;
3f51e471
RV		 1814 return true;
1815}
1816
3d739d92 1817static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1818{
1819 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1820
3f51e471
RV		 1821 if (!intel_edp_psr_match_conditions(intel_dp) ||
1822 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1823 return;
1824
1825 /* Setup PSR once */
1826 intel_edp_psr_setup(intel_dp);
1827
1828 /* Enable PSR on the panel */
1829 intel_edp_psr_enable_sink(intel_dp);
1830
1831 /* Enable PSR on the host */
1832 intel_edp_psr_enable_source(intel_dp);
1833}
1834
3d739d92
RV		 1835void intel_edp_psr_enable(struct intel_dp *intel_dp)
1836{
1837 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1838
1839 if (intel_edp_psr_match_conditions(intel_dp) &&
1840 !intel_edp_is_psr_enabled(dev))
1841 intel_edp_psr_do_enable(intel_dp);
1842}
1843
2b28bb1b
RV		 1844void intel_edp_psr_disable(struct intel_dp *intel_dp)
1845{
1846 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1847 struct drm_i915_private *dev_priv = dev->dev_private;
1848
1849 if (!intel_edp_is_psr_enabled(dev))
1850 return;
1851
18b5992c
BW		 1852 I915_WRITE(EDP_PSR_CTL(dev),
1853 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1854
1855 /* Wait till PSR is idle */
18b5992c 1856 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1857 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1858 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1859}
1860
3d739d92
RV		 1861void intel_edp_psr_update(struct drm_device *dev)
1862{
1863 struct intel_encoder *encoder;
1864 struct intel_dp *intel_dp = NULL;
1865
1866 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1867 if (encoder->type == INTEL_OUTPUT_EDP) {
1868 intel_dp = enc_to_intel_dp(&encoder->base);
1869
a031d709 1870 if (!is_edp_psr(dev))
3d739d92
RV		 1871 return;
1872
1873 if (!intel_edp_psr_match_conditions(intel_dp))
1874 intel_edp_psr_disable(intel_dp);
1875 else
1876 if (!intel_edp_is_psr_enabled(dev))
1877 intel_edp_psr_do_enable(intel_dp);
1878 }
1879}
1880
e8cb4558 1881static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1882{
e8cb4558 1883 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1884 enum port port = dp_to_dig_port(intel_dp)->port;
1885 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1886
1887 /* Make sure the panel is off before trying to change the mode. But also
1888 * ensure that we have vdd while we switch off the panel. */
b3064154 1889 edp_panel_vdd_on(intel_dp);
4be73780 1890 intel_edp_backlight_off(intel_dp);
fdbc3b1f 1891 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 1892 intel_edp_panel_off(intel_dp);
b3064154 1893 edp_panel_vdd_off(intel_dp, true);
3739850b
DV		 1894
1895 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1896 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1897 intel_dp_link_down(intel_dp);
d240f20f
JB		 1898}
1899
2bd2ad64 1900static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1901{
2bd2ad64 1902 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1903 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1904 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1905
982a3866 1906 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1907 intel_dp_link_down(intel_dp);
b2634017
JB		 1908 if (!IS_VALLEYVIEW(dev))
1909 ironlake_edp_pll_off(intel_dp);
3739850b 1910 }
2bd2ad64
DV		 1911}
1912
e8cb4558 1913static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1914{
e8cb4558
DV		 1915 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1916 struct drm_device *dev = encoder->base.dev;
1917 struct drm_i915_private *dev_priv = dev->dev_private;
1918 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1919
0c33d8d7
DV		 1920 if (WARN_ON(dp_reg & DP_PORT_EN))
1921 return;
5d613501 1922
4be73780 1923 edp_panel_vdd_on(intel_dp);
f01eca2e 1924 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1925 intel_dp_start_link_train(intel_dp);
4be73780
DV		 1926 intel_edp_panel_on(intel_dp);
1927 edp_panel_vdd_off(intel_dp, true);
33a34e4e 1928 intel_dp_complete_link_train(intel_dp);
3ab9c637 1929 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1930}
89b667f8 1931
ecff4f3b
JN		 1932static void g4x_enable_dp(struct intel_encoder *encoder)
1933{
828f5c6e
JN		 1934 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1935
ecff4f3b 1936 intel_enable_dp(encoder);
4be73780 1937 intel_edp_backlight_on(intel_dp);
ab1f90f9 1938}
89b667f8 1939
ab1f90f9
JN		 1940static void vlv_enable_dp(struct intel_encoder *encoder)
1941{
828f5c6e
JN		 1942 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1943
4be73780 1944 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 1945}
1946
ecff4f3b 1947static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1948{
1949 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1950 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1951
1952 if (dport->port == PORT_A)
1953 ironlake_edp_pll_on(intel_dp);
1954}
1955
1956static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1957{
2bd2ad64 1958 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1959 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1960 struct drm_device *dev = encoder->base.dev;
89b667f8 1961 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 1962 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 1963 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 1964 int pipe = intel_crtc->pipe;
bf13e81b 1965 struct edp_power_seq power_seq;
ab1f90f9 1966 u32 val;
a4fc5ed6 1967
ab1f90f9 1968 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1969
ab3c759a 1970 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 1971 val = 0;
1972 if (pipe)
1973 val |= (1<<21);
1974 else
1975 val &= ~(1<<21);
1976 val |= 0x001000c4;
ab3c759a
CML		 1977 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1978 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1979 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 1980
ab1f90f9
JN		 1981 mutex_unlock(&dev_priv->dpio_lock);
1982
2cac613b
ID		 1983 if (is_edp(intel_dp)) {
1984 /* init power sequencer on this pipe and port */
1985 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1986 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1987 &power_seq);
1988 }
bf13e81b 1989
ab1f90f9
JN		 1990 intel_enable_dp(encoder);
1991
e4607fcf 1992 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 1993}
1994
ecff4f3b 1995static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1996{
1997 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1998 struct drm_device *dev = encoder->base.dev;
1999 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2000 struct intel_crtc *intel_crtc =
2001 to_intel_crtc(encoder->base.crtc);
e4607fcf 2002 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2003 int pipe = intel_crtc->pipe;
89b667f8 2004
89b667f8 2005 /* Program Tx lane resets to default */
0980a60f 2006 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2007 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2008 DPIO_PCS_TX_LANE2_RESET |
2009 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2010 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2011 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2012 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2013 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2014 DPIO_PCS_CLK_SOFT_RESET);
2015
2016 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2017 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2018 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2019 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2020 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2021}
2022
2023/*
df0c237d
JB		 2024 * Native read with retry for link status and receiver capability reads for
2025 * cases where the sink may still be asleep.
a4fc5ed6
KP		 2026 */
2027static bool
df0c237d
JB		 2028intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
2029 uint8_t *recv, int recv_bytes)
a4fc5ed6 2030{
61da5fab
JB		 2031 int ret, i;
2032
df0c237d
JB		 2033 /*
2034 * Sinks are *supposed* to come up within 1ms from an off state,
2035 * but we're also supposed to retry 3 times per the spec.
2036 */
61da5fab 2037 for (i = 0; i < 3; i++) {
df0c237d
JB		 2038 ret = intel_dp_aux_native_read(intel_dp, address, recv,
2039 recv_bytes);
2040 if (ret == recv_bytes)
61da5fab
JB		 2041 return true;
2042 msleep(1);
2043 }
a4fc5ed6 2044
61da5fab 2045 return false;
a4fc5ed6
KP		 2046}
2047
2048/*
2049 * Fetch AUX CH registers 0x202 - 0x207 which contain
2050 * link status information
2051 */
2052static bool
93f62dad 2053intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2054{
df0c237d
JB		 2055 return intel_dp_aux_native_read_retry(intel_dp,
2056 DP_LANE0_1_STATUS,
93f62dad 2057 link_status,
df0c237d 2058 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 2059}
2060
a4fc5ed6
KP		 2061/*
2062 * These are source-specific values; current Intel hardware supports
2063 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
2064 */
a4fc5ed6
KP		 2065
2066static uint8_t
1a2eb460 2067intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2068{
30add22d 2069 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2070 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2071
8f93f4f1 2072 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
e2fa6fba 2073 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 2074 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 2075 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 2076 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 2077 return DP_TRAIN_VOLTAGE_SWING_1200;
2078 else
2079 return DP_TRAIN_VOLTAGE_SWING_800;
2080}
2081
2082static uint8_t
2083intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2084{
30add22d 2085 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2086 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2087
8f93f4f1
PZ		 2088 if (IS_BROADWELL(dev)) {
2089 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2090 case DP_TRAIN_VOLTAGE_SWING_400:
2091 case DP_TRAIN_VOLTAGE_SWING_600:
2092 return DP_TRAIN_PRE_EMPHASIS_6;
2093 case DP_TRAIN_VOLTAGE_SWING_800:
2094 return DP_TRAIN_PRE_EMPHASIS_3_5;
2095 case DP_TRAIN_VOLTAGE_SWING_1200:
2096 default:
2097 return DP_TRAIN_PRE_EMPHASIS_0;
2098 }
2099 } else if (IS_HASWELL(dev)) {
d6c0d722
PZ		 2100 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2101 case DP_TRAIN_VOLTAGE_SWING_400:
2102 return DP_TRAIN_PRE_EMPHASIS_9_5;
2103 case DP_TRAIN_VOLTAGE_SWING_600:
2104 return DP_TRAIN_PRE_EMPHASIS_6;
2105 case DP_TRAIN_VOLTAGE_SWING_800:
2106 return DP_TRAIN_PRE_EMPHASIS_3_5;
2107 case DP_TRAIN_VOLTAGE_SWING_1200:
2108 default:
2109 return DP_TRAIN_PRE_EMPHASIS_0;
2110 }
e2fa6fba
P		 2111 } else if (IS_VALLEYVIEW(dev)) {
2112 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2113 case DP_TRAIN_VOLTAGE_SWING_400:
2114 return DP_TRAIN_PRE_EMPHASIS_9_5;
2115 case DP_TRAIN_VOLTAGE_SWING_600:
2116 return DP_TRAIN_PRE_EMPHASIS_6;
2117 case DP_TRAIN_VOLTAGE_SWING_800:
2118 return DP_TRAIN_PRE_EMPHASIS_3_5;
2119 case DP_TRAIN_VOLTAGE_SWING_1200:
2120 default:
2121 return DP_TRAIN_PRE_EMPHASIS_0;
2122 }
bc7d38a4 2123 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2124 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2125 case DP_TRAIN_VOLTAGE_SWING_400:
2126 return DP_TRAIN_PRE_EMPHASIS_6;
2127 case DP_TRAIN_VOLTAGE_SWING_600:
2128 case DP_TRAIN_VOLTAGE_SWING_800:
2129 return DP_TRAIN_PRE_EMPHASIS_3_5;
2130 default:
2131 return DP_TRAIN_PRE_EMPHASIS_0;
2132 }
2133 } else {
2134 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2135 case DP_TRAIN_VOLTAGE_SWING_400:
2136 return DP_TRAIN_PRE_EMPHASIS_6;
2137 case DP_TRAIN_VOLTAGE_SWING_600:
2138 return DP_TRAIN_PRE_EMPHASIS_6;
2139 case DP_TRAIN_VOLTAGE_SWING_800:
2140 return DP_TRAIN_PRE_EMPHASIS_3_5;
2141 case DP_TRAIN_VOLTAGE_SWING_1200:
2142 default:
2143 return DP_TRAIN_PRE_EMPHASIS_0;
2144 }
a4fc5ed6
KP		 2145 }
2146}
2147
e2fa6fba
P		 2148static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2149{
2150 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2151 struct drm_i915_private *dev_priv = dev->dev_private;
2152 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2153 struct intel_crtc *intel_crtc =
2154 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2155 unsigned long demph_reg_value, preemph_reg_value,
2156 uniqtranscale_reg_value;
2157 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2158 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2159 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2160
2161 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2162 case DP_TRAIN_PRE_EMPHASIS_0:
2163 preemph_reg_value = 0x0004000;
2164 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2165 case DP_TRAIN_VOLTAGE_SWING_400:
2166 demph_reg_value = 0x2B405555;
2167 uniqtranscale_reg_value = 0x552AB83A;
2168 break;
2169 case DP_TRAIN_VOLTAGE_SWING_600:
2170 demph_reg_value = 0x2B404040;
2171 uniqtranscale_reg_value = 0x5548B83A;
2172 break;
2173 case DP_TRAIN_VOLTAGE_SWING_800:
2174 demph_reg_value = 0x2B245555;
2175 uniqtranscale_reg_value = 0x5560B83A;
2176 break;
2177 case DP_TRAIN_VOLTAGE_SWING_1200:
2178 demph_reg_value = 0x2B405555;
2179 uniqtranscale_reg_value = 0x5598DA3A;
2180 break;
2181 default:
2182 return 0;
2183 }
2184 break;
2185 case DP_TRAIN_PRE_EMPHASIS_3_5:
2186 preemph_reg_value = 0x0002000;
2187 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2188 case DP_TRAIN_VOLTAGE_SWING_400:
2189 demph_reg_value = 0x2B404040;
2190 uniqtranscale_reg_value = 0x5552B83A;
2191 break;
2192 case DP_TRAIN_VOLTAGE_SWING_600:
2193 demph_reg_value = 0x2B404848;
2194 uniqtranscale_reg_value = 0x5580B83A;
2195 break;
2196 case DP_TRAIN_VOLTAGE_SWING_800:
2197 demph_reg_value = 0x2B404040;
2198 uniqtranscale_reg_value = 0x55ADDA3A;
2199 break;
2200 default:
2201 return 0;
2202 }
2203 break;
2204 case DP_TRAIN_PRE_EMPHASIS_6:
2205 preemph_reg_value = 0x0000000;
2206 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2207 case DP_TRAIN_VOLTAGE_SWING_400:
2208 demph_reg_value = 0x2B305555;
2209 uniqtranscale_reg_value = 0x5570B83A;
2210 break;
2211 case DP_TRAIN_VOLTAGE_SWING_600:
2212 demph_reg_value = 0x2B2B4040;
2213 uniqtranscale_reg_value = 0x55ADDA3A;
2214 break;
2215 default:
2216 return 0;
2217 }
2218 break;
2219 case DP_TRAIN_PRE_EMPHASIS_9_5:
2220 preemph_reg_value = 0x0006000;
2221 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2222 case DP_TRAIN_VOLTAGE_SWING_400:
2223 demph_reg_value = 0x1B405555;
2224 uniqtranscale_reg_value = 0x55ADDA3A;
2225 break;
2226 default:
2227 return 0;
2228 }
2229 break;
2230 default:
2231 return 0;
2232 }
2233
0980a60f 2234 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2235 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2236 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2237 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2238 uniqtranscale_reg_value);
ab3c759a
CML		 2239 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2240 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2241 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2242 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2243 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2244
2245 return 0;
2246}
2247
a4fc5ed6 2248static void
0301b3ac
JN		 2249intel_get_adjust_train(struct intel_dp *intel_dp,
2250 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2251{
2252 uint8_t v = 0;
2253 uint8_t p = 0;
2254 int lane;
1a2eb460
KP		 2255 uint8_t voltage_max;
2256 uint8_t preemph_max;
a4fc5ed6 2257
33a34e4e 2258 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2259 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2260 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2261
2262 if (this_v > v)
2263 v = this_v;
2264 if (this_p > p)
2265 p = this_p;
2266 }
2267
1a2eb460 2268 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2269 if (v >= voltage_max)
2270 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2271
1a2eb460
KP		 2272 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2273 if (p >= preemph_max)
2274 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2275
2276 for (lane = 0; lane < 4; lane++)
33a34e4e 2277 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2278}
2279
2280static uint32_t
f0a3424e 2281intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2282{
3cf2efb1 2283 uint32_t signal_levels = 0;
a4fc5ed6 2284
3cf2efb1 2285 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2286 case DP_TRAIN_VOLTAGE_SWING_400:
2287 default:
2288 signal_levels |= DP_VOLTAGE_0_4;
2289 break;
2290 case DP_TRAIN_VOLTAGE_SWING_600:
2291 signal_levels |= DP_VOLTAGE_0_6;
2292 break;
2293 case DP_TRAIN_VOLTAGE_SWING_800:
2294 signal_levels |= DP_VOLTAGE_0_8;
2295 break;
2296 case DP_TRAIN_VOLTAGE_SWING_1200:
2297 signal_levels |= DP_VOLTAGE_1_2;
2298 break;
2299 }
3cf2efb1 2300 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2301 case DP_TRAIN_PRE_EMPHASIS_0:
2302 default:
2303 signal_levels |= DP_PRE_EMPHASIS_0;
2304 break;
2305 case DP_TRAIN_PRE_EMPHASIS_3_5:
2306 signal_levels |= DP_PRE_EMPHASIS_3_5;
2307 break;
2308 case DP_TRAIN_PRE_EMPHASIS_6:
2309 signal_levels |= DP_PRE_EMPHASIS_6;
2310 break;
2311 case DP_TRAIN_PRE_EMPHASIS_9_5:
2312 signal_levels |= DP_PRE_EMPHASIS_9_5;
2313 break;
2314 }
2315 return signal_levels;
2316}
2317
e3421a18
ZW		 2318/* Gen6's DP voltage swing and pre-emphasis control */
2319static uint32_t
2320intel_gen6_edp_signal_levels(uint8_t train_set)
2321{
3c5a62b5
YL		 2322 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2323 DP_TRAIN_PRE_EMPHASIS_MASK);
2324 switch (signal_levels) {
e3421a18 2325 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2326 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2327 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2328 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2329 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2330 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2331 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2332 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2333 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2334 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2335 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2336 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2337 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2338 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2339 default:
3c5a62b5
YL		 2340 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2341 "0x%x\n", signal_levels);
2342 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2343 }
2344}
2345
1a2eb460
KP		 2346/* Gen7's DP voltage swing and pre-emphasis control */
2347static uint32_t
2348intel_gen7_edp_signal_levels(uint8_t train_set)
2349{
2350 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2351 DP_TRAIN_PRE_EMPHASIS_MASK);
2352 switch (signal_levels) {
2353 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2354 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2355 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2356 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2357 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2358 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2359
2360 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2361 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2362 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2363 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2364
2365 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2366 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2367 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2368 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2369
2370 default:
2371 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2372 "0x%x\n", signal_levels);
2373 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2374 }
2375}
2376
d6c0d722
PZ		 2377/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2378static uint32_t
f0a3424e 2379intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2380{
d6c0d722
PZ		 2381 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2382 DP_TRAIN_PRE_EMPHASIS_MASK);
2383 switch (signal_levels) {
2384 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2385 return DDI_BUF_EMP_400MV_0DB_HSW;
2386 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2387 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2388 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2389 return DDI_BUF_EMP_400MV_6DB_HSW;
2390 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2391 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2392
d6c0d722
PZ		 2393 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2394 return DDI_BUF_EMP_600MV_0DB_HSW;
2395 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2396 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2397 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2398 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2399
d6c0d722
PZ		 2400 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2401 return DDI_BUF_EMP_800MV_0DB_HSW;
2402 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2403 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2404 default:
2405 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2406 "0x%x\n", signal_levels);
2407 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2408 }
a4fc5ed6
KP		 2409}
2410
8f93f4f1
PZ		 2411static uint32_t
2412intel_bdw_signal_levels(uint8_t train_set)
2413{
2414 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2415 DP_TRAIN_PRE_EMPHASIS_MASK);
2416 switch (signal_levels) {
2417 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2418 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2419 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2420 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2421 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2422 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2423
2424 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2425 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2426 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2427 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2428 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2429 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2430
2431 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2432 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2433 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2434 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2435
2436 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2437 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2438
2439 default:
2440 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2441 "0x%x\n", signal_levels);
2442 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2443 }
2444}
2445
f0a3424e
PZ		 2446/* Properly updates "DP" with the correct signal levels. */
2447static void
2448intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2449{
2450 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2451 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2452 struct drm_device *dev = intel_dig_port->base.base.dev;
2453 uint32_t signal_levels, mask;
2454 uint8_t train_set = intel_dp->train_set[0];
2455
8f93f4f1
PZ		 2456 if (IS_BROADWELL(dev)) {
2457 signal_levels = intel_bdw_signal_levels(train_set);
2458 mask = DDI_BUF_EMP_MASK;
2459 } else if (IS_HASWELL(dev)) {
f0a3424e
PZ		 2460 signal_levels = intel_hsw_signal_levels(train_set);
2461 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2462 } else if (IS_VALLEYVIEW(dev)) {
2463 signal_levels = intel_vlv_signal_levels(intel_dp);
2464 mask = 0;
bc7d38a4 2465 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2466 signal_levels = intel_gen7_edp_signal_levels(train_set);
2467 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2468 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2469 signal_levels = intel_gen6_edp_signal_levels(train_set);
2470 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2471 } else {
2472 signal_levels = intel_gen4_signal_levels(train_set);
2473 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2474 }
2475
2476 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2477
2478 *DP = (*DP & ~mask) | signal_levels;
2479}
2480
a4fc5ed6 2481static bool
ea5b213a 2482intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2483 uint32_t *DP,
58e10eb9 2484 uint8_t dp_train_pat)
a4fc5ed6 2485{
174edf1f
PZ		 2486 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2487 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2488 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2489 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2490 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2491 int ret, len;
a4fc5ed6 2492
22b8bf17 2493 if (HAS_DDI(dev)) {
3ab9c637 2494 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2495
2496 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2497 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2498 else
2499 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2500
2501 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2502 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2503 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2504 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2505
2506 break;
2507 case DP_TRAINING_PATTERN_1:
2508 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2509 break;
2510 case DP_TRAINING_PATTERN_2:
2511 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2512 break;
2513 case DP_TRAINING_PATTERN_3:
2514 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2515 break;
2516 }
174edf1f 2517 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2518
bc7d38a4 2519 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2520 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2521
2522 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2523 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2524 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2525 break;
2526 case DP_TRAINING_PATTERN_1:
70aff66c 2527 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2528 break;
2529 case DP_TRAINING_PATTERN_2:
70aff66c 2530 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2531 break;
2532 case DP_TRAINING_PATTERN_3:
2533 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2534 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2535 break;
2536 }
2537
2538 } else {
70aff66c 2539 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2540
2541 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2542 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2543 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2544 break;
2545 case DP_TRAINING_PATTERN_1:
70aff66c 2546 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2547 break;
2548 case DP_TRAINING_PATTERN_2:
70aff66c 2549 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2550 break;
2551 case DP_TRAINING_PATTERN_3:
2552 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2553 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2554 break;
2555 }
2556 }
2557
70aff66c 2558 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2559 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2560
2cdfe6c8
JN		 2561 buf[0] = dp_train_pat;
2562 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2563 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2564 /* don't write DP_TRAINING_LANEx_SET on disable */
2565 len = 1;
2566 } else {
2567 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2568 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2569 len = intel_dp->lane_count + 1;
47ea7542 2570 }
a4fc5ed6 2571
2cdfe6c8
JN		 2572 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
2573 buf, len);
2574
2575 return ret == len;
a4fc5ed6
KP		 2576}
2577
70aff66c
JN		 2578static bool
2579intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2580 uint8_t dp_train_pat)
2581{
953d22e8 2582 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2583 intel_dp_set_signal_levels(intel_dp, DP);
2584 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2585}
2586
2587static bool
2588intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2589 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2590{
2591 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2592 struct drm_device *dev = intel_dig_port->base.base.dev;
2593 struct drm_i915_private *dev_priv = dev->dev_private;
2594 int ret;
2595
2596 intel_get_adjust_train(intel_dp, link_status);
2597 intel_dp_set_signal_levels(intel_dp, DP);
2598
2599 I915_WRITE(intel_dp->output_reg, *DP);
2600 POSTING_READ(intel_dp->output_reg);
2601
2602 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
2603 intel_dp->train_set,
2604 intel_dp->lane_count);
2605
2606 return ret == intel_dp->lane_count;
2607}
2608
3ab9c637
ID		 2609static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2610{
2611 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2612 struct drm_device *dev = intel_dig_port->base.base.dev;
2613 struct drm_i915_private *dev_priv = dev->dev_private;
2614 enum port port = intel_dig_port->port;
2615 uint32_t val;
2616
2617 if (!HAS_DDI(dev))
2618 return;
2619
2620 val = I915_READ(DP_TP_CTL(port));
2621 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2622 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2623 I915_WRITE(DP_TP_CTL(port), val);
2624
2625 /*
2626 * On PORT_A we can have only eDP in SST mode. There the only reason
2627 * we need to set idle transmission mode is to work around a HW issue
2628 * where we enable the pipe while not in idle link-training mode.
2629 * In this case there is requirement to wait for a minimum number of
2630 * idle patterns to be sent.
2631 */
2632 if (port == PORT_A)
2633 return;
2634
2635 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2636 1))
2637 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2638}
2639
33a34e4e 2640/* Enable corresponding port and start training pattern 1 */
c19b0669 2641void
33a34e4e 2642intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2643{
da63a9f2 2644 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2645 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2646 int i;
2647 uint8_t voltage;
cdb0e95b 2648 int voltage_tries, loop_tries;
ea5b213a 2649 uint32_t DP = intel_dp->DP;
6aba5b6c 2650 uint8_t link_config[2];
a4fc5ed6 2651
affa9354 2652 if (HAS_DDI(dev))
c19b0669
PZ		 2653 intel_ddi_prepare_link_retrain(encoder);
2654
3cf2efb1 2655 /* Write the link configuration data */
6aba5b6c
JN		 2656 link_config[0] = intel_dp->link_bw;
2657 link_config[1] = intel_dp->lane_count;
2658 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2659 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2660 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
2661
2662 link_config[0] = 0;
2663 link_config[1] = DP_SET_ANSI_8B10B;
2664 intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 2665
2666 DP |= DP_PORT_EN;
1a2eb460 2667
70aff66c
JN		 2668 /* clock recovery */
2669 if (!intel_dp_reset_link_train(intel_dp, &DP,
2670 DP_TRAINING_PATTERN_1 |
2671 DP_LINK_SCRAMBLING_DISABLE)) {
2672 DRM_ERROR("failed to enable link training\n");
2673 return;
2674 }
2675
a4fc5ed6 2676 voltage = 0xff;
cdb0e95b
KP		 2677 voltage_tries = 0;
2678 loop_tries = 0;
a4fc5ed6 2679 for (;;) {
70aff66c 2680 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 2681
a7c9655f 2682 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2683 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2684 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2685 break;
93f62dad 2686 }
a4fc5ed6 2687
01916270 2688 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2689 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2690 break;
2691 }
2692
2693 /* Check to see if we've tried the max voltage */
2694 for (i = 0; i < intel_dp->lane_count; i++)
2695 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2696 break;
3b4f819d 2697 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2698 ++loop_tries;
2699 if (loop_tries == 5) {
3def84b3 2700 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 2701 break;
2702 }
70aff66c
JN		 2703 intel_dp_reset_link_train(intel_dp, &DP,
2704 DP_TRAINING_PATTERN_1 |
2705 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 2706 voltage_tries = 0;
2707 continue;
2708 }
a4fc5ed6 2709
3cf2efb1 2710 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2711 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2712 ++voltage_tries;
b06fbda3 2713 if (voltage_tries == 5) {
3def84b3 2714 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 2715 break;
2716 }
2717 } else
2718 voltage_tries = 0;
2719 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2720
70aff66c
JN		 2721 /* Update training set as requested by target */
2722 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2723 DRM_ERROR("failed to update link training\n");
2724 break;
2725 }
a4fc5ed6
KP		 2726 }
2727
33a34e4e
JB		 2728 intel_dp->DP = DP;
2729}
2730
c19b0669 2731void
33a34e4e
JB		 2732intel_dp_complete_link_train(struct intel_dp *intel_dp)
2733{
33a34e4e 2734 bool channel_eq = false;
37f80975 2735 int tries, cr_tries;
33a34e4e 2736 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 2737 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2738
2739 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2740 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2741 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 2742
a4fc5ed6 2743 /* channel equalization */
70aff66c 2744 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2745 training_pattern |
70aff66c
JN		 2746 DP_LINK_SCRAMBLING_DISABLE)) {
2747 DRM_ERROR("failed to start channel equalization\n");
2748 return;
2749 }
2750
a4fc5ed6 2751 tries = 0;
37f80975 2752 cr_tries = 0;
a4fc5ed6
KP		 2753 channel_eq = false;
2754 for (;;) {
70aff66c 2755 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2756
37f80975
JB		 2757 if (cr_tries > 5) {
2758 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 2759 break;
2760 }
2761
a7c9655f 2762 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 2763 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2764 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2765 break;
70aff66c 2766 }
a4fc5ed6 2767
37f80975 2768 /* Make sure clock is still ok */
01916270 2769 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 2770 intel_dp_start_link_train(intel_dp);
70aff66c 2771 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2772 training_pattern |
70aff66c 2773 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2774 cr_tries++;
2775 continue;
2776 }
2777
1ffdff13 2778 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2779 channel_eq = true;
2780 break;
2781 }
a4fc5ed6 2782
37f80975
JB		 2783 /* Try 5 times, then try clock recovery if that fails */
2784 if (tries > 5) {
2785 intel_dp_link_down(intel_dp);
2786 intel_dp_start_link_train(intel_dp);
70aff66c 2787 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2788 training_pattern |
70aff66c 2789 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2790 tries = 0;
2791 cr_tries++;
2792 continue;
2793 }
a4fc5ed6 2794
70aff66c
JN		 2795 /* Update training set as requested by target */
2796 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2797 DRM_ERROR("failed to update link training\n");
2798 break;
2799 }
3cf2efb1 2800 ++tries;
869184a6 2801 }
3cf2efb1 2802
3ab9c637
ID		 2803 intel_dp_set_idle_link_train(intel_dp);
2804
2805 intel_dp->DP = DP;
2806
d6c0d722 2807 if (channel_eq)
07f42258 2808 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2809
3ab9c637
ID		 2810}
2811
2812void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2813{
70aff66c 2814 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 2815 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2816}
2817
2818static void
ea5b213a 2819intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2820{
da63a9f2 2821 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2822 enum port port = intel_dig_port->port;
da63a9f2 2823 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2824 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2825 struct intel_crtc *intel_crtc =
2826 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2827 uint32_t DP = intel_dp->DP;
a4fc5ed6 2828
c19b0669
PZ		 2829 /*
2830 * DDI code has a strict mode set sequence and we should try to respect
2831 * it, otherwise we might hang the machine in many different ways. So we
2832 * really should be disabling the port only on a complete crtc_disable
2833 * sequence. This function is just called under two conditions on DDI
2834 * code:
2835 * - Link train failed while doing crtc_enable, and on this case we
2836 * really should respect the mode set sequence and wait for a
2837 * crtc_disable.
2838 * - Someone turned the monitor off and intel_dp_check_link_status
2839 * called us. We don't need to disable the whole port on this case, so
2840 * when someone turns the monitor on again,
2841 * intel_ddi_prepare_link_retrain will take care of redoing the link
2842 * train.
2843 */
affa9354 2844 if (HAS_DDI(dev))
c19b0669
PZ		 2845 return;
2846
0c33d8d7 2847 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2848 return;
2849
28c97730 2850 DRM_DEBUG_KMS("\n");
32f9d658 2851
bc7d38a4 2852 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2853 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2854 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2855 } else {
2856 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2857 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2858 }
fe255d00 2859 POSTING_READ(intel_dp->output_reg);
5eb08b69 2860
ab527efc
DV		 2861 /* We don't really know why we're doing this */
2862 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2863
493a7081 2864 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2865 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2866 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2867
5bddd17f
EA		 2868 /* Hardware workaround: leaving our transcoder select
2869 * set to transcoder B while it's off will prevent the
2870 * corresponding HDMI output on transcoder A.
2871 *
2872 * Combine this with another hardware workaround:
2873 * transcoder select bit can only be cleared while the
2874 * port is enabled.
2875 */
2876 DP &= ~DP_PIPEB_SELECT;
2877 I915_WRITE(intel_dp->output_reg, DP);
2878
2879 /* Changes to enable or select take place the vblank
2880 * after being written.
2881 */
ff50afe9
DV		 2882 if (WARN_ON(crtc == NULL)) {
2883 /* We should never try to disable a port without a crtc
2884 * attached. For paranoia keep the code around for a
2885 * bit. */
31acbcc4
CW		 2886 POSTING_READ(intel_dp->output_reg);
2887 msleep(50);
2888 } else
ab527efc 2889 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2890 }
2891
832afda6 2892 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2893 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2894 POSTING_READ(intel_dp->output_reg);
f01eca2e 2895 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2896}
2897
26d61aad
KP		 2898static bool
2899intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2900{
a031d709
RV		 2901 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2902 struct drm_device *dev = dig_port->base.base.dev;
2903 struct drm_i915_private *dev_priv = dev->dev_private;
2904
577c7a50
DL		 2905 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2906
92fd8fd1 2907 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2908 sizeof(intel_dp->dpcd)) == 0)
2909 return false; /* aux transfer failed */
92fd8fd1 2910
577c7a50
DL		 2911 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2912 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2913 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2914
edb39244
AJ		 2915 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2916 return false; /* DPCD not present */
2917
2293bb5c
SK		 2918 /* Check if the panel supports PSR */
2919 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939
JN		 2920 if (is_edp(intel_dp)) {
2921 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2922 intel_dp->psr_dpcd,
2923 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 2924 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2925 dev_priv->psr.sink_support = true;
50003939 2926 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 2927 }
50003939
JN		 2928 }
2929
06ea66b6
TP		 2930 /* Training Pattern 3 support */
2931 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2932 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2933 intel_dp->use_tps3 = true;
2934 DRM_DEBUG_KMS("Displayport TPS3 supported");
2935 } else
2936 intel_dp->use_tps3 = false;
2937
edb39244
AJ		 2938 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2939 DP_DWN_STRM_PORT_PRESENT))
2940 return true; /* native DP sink */
2941
2942 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2943 return true; /* no per-port downstream info */
2944
2945 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2946 intel_dp->downstream_ports,
2947 DP_MAX_DOWNSTREAM_PORTS) == 0)
2948 return false; /* downstream port status fetch failed */
2949
2950 return true;
92fd8fd1
KP		 2951}
2952
0d198328
AJ		 2953static void
2954intel_dp_probe_oui(struct intel_dp *intel_dp)
2955{
2956 u8 buf[3];
2957
2958 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2959 return;
2960
4be73780 2961 edp_panel_vdd_on(intel_dp);
351cfc34 2962
0d198328
AJ		 2963 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2964 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2965 buf[0], buf[1], buf[2]);
2966
2967 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2968 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2969 buf[0], buf[1], buf[2]);
351cfc34 2970
4be73780 2971 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2972}
2973
d2e216d0
RV		 2974int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2975{
2976 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2977 struct drm_device *dev = intel_dig_port->base.base.dev;
2978 struct intel_crtc *intel_crtc =
2979 to_intel_crtc(intel_dig_port->base.base.crtc);
2980 u8 buf[1];
2981
2982 if (!intel_dp_aux_native_read(intel_dp, DP_TEST_SINK_MISC, buf, 1))
2983 return -EAGAIN;
2984
2985 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2986 return -ENOTTY;
2987
2988 if (!intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK,
2989 DP_TEST_SINK_START))
2990 return -EAGAIN;
2991
2992 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2993 intel_wait_for_vblank(dev, intel_crtc->pipe);
2994 intel_wait_for_vblank(dev, intel_crtc->pipe);
2995
2996 if (!intel_dp_aux_native_read(intel_dp, DP_TEST_CRC_R_CR, crc, 6))
2997 return -EAGAIN;
2998
2999 intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK, 0);
3000 return 0;
3001}
3002
a60f0e38
JB		 3003static bool
3004intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3005{
3006 int ret;
3007
3008 ret = intel_dp_aux_native_read_retry(intel_dp,
3009 DP_DEVICE_SERVICE_IRQ_VECTOR,
3010 sink_irq_vector, 1);
3011 if (!ret)
3012 return false;
3013
3014 return true;
3015}
3016
3017static void
3018intel_dp_handle_test_request(struct intel_dp *intel_dp)
3019{
3020 /* NAK by default */
9324cf7f 3021 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3022}
3023
a4fc5ed6
KP		 3024/*
3025 * According to DP spec
3026 * 5.1.2:
3027 * 1. Read DPCD
3028 * 2. Configure link according to Receiver Capabilities
3029 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3030 * 4. Check link status on receipt of hot-plug interrupt
3031 */
3032
00c09d70 3033void
ea5b213a 3034intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3035{
da63a9f2 3036 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3037 u8 sink_irq_vector;
93f62dad 3038 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3039
da63a9f2 3040 if (!intel_encoder->connectors_active)
d2b996ac 3041 return;
59cd09e1 3042
da63a9f2 3043 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3044 return;
3045
92fd8fd1 3046 /* Try to read receiver status if the link appears to be up */
93f62dad 3047 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3048 return;
3049 }
3050
92fd8fd1 3051 /* Now read the DPCD to see if it's actually running */
26d61aad 3052 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3053 return;
3054 }
3055
a60f0e38
JB		 3056 /* Try to read the source of the interrupt */
3057 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3058 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3059 /* Clear interrupt source */
3060 intel_dp_aux_native_write_1(intel_dp,
3061 DP_DEVICE_SERVICE_IRQ_VECTOR,
3062 sink_irq_vector);
3063
3064 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3065 intel_dp_handle_test_request(intel_dp);
3066 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3067 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3068 }
3069
1ffdff13 3070 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3071 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 3072 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 3073 intel_dp_start_link_train(intel_dp);
3074 intel_dp_complete_link_train(intel_dp);
3ab9c637 3075 intel_dp_stop_link_train(intel_dp);
33a34e4e 3076 }
a4fc5ed6 3077}
a4fc5ed6 3078
caf9ab24 3079/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3080static enum drm_connector_status
26d61aad 3081intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3082{
caf9ab24 3083 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3084 uint8_t type;
3085
3086 if (!intel_dp_get_dpcd(intel_dp))
3087 return connector_status_disconnected;
3088
3089 /* if there's no downstream port, we're done */
3090 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3091 return connector_status_connected;
caf9ab24
AJ		 3092
3093 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3094 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3095 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3096 uint8_t reg;
caf9ab24 3097 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 3098 &reg, 1))
caf9ab24 3099 return connector_status_unknown;
23235177
AJ		 3100 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3101 : connector_status_disconnected;
caf9ab24
AJ		 3102 }
3103
3104 /* If no HPD, poke DDC gently */
3105 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 3106 return connector_status_connected;
caf9ab24
AJ		 3107
3108 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3109 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3110 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3111 if (type == DP_DS_PORT_TYPE_VGA ||
3112 type == DP_DS_PORT_TYPE_NON_EDID)
3113 return connector_status_unknown;
3114 } else {
3115 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3116 DP_DWN_STRM_PORT_TYPE_MASK;
3117 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3118 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3119 return connector_status_unknown;
3120 }
caf9ab24
AJ		 3121
3122 /* Anything else is out of spec, warn and ignore */
3123 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3124 return connector_status_disconnected;
71ba9000
AJ		 3125}
3126
5eb08b69 3127static enum drm_connector_status
a9756bb5 3128ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3129{
30add22d 3130 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3131 struct drm_i915_private *dev_priv = dev->dev_private;
3132 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3133 enum drm_connector_status status;
3134
fe16d949
CW		 3135 /* Can't disconnect eDP, but you can close the lid... */
3136 if (is_edp(intel_dp)) {
30add22d 3137 status = intel_panel_detect(dev);
fe16d949
CW		 3138 if (status == connector_status_unknown)
3139 status = connector_status_connected;
3140 return status;
3141 }
01cb9ea6 3142
1b469639
DL		 3143 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3144 return connector_status_disconnected;
3145
26d61aad 3146 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3147}
3148
a4fc5ed6 3149static enum drm_connector_status
a9756bb5 3150g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3151{
30add22d 3152 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3153 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3154 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3155 uint32_t bit;
5eb08b69 3156
35aad75f
JB		 3157 /* Can't disconnect eDP, but you can close the lid... */
3158 if (is_edp(intel_dp)) {
3159 enum drm_connector_status status;
3160
3161 status = intel_panel_detect(dev);
3162 if (status == connector_status_unknown)
3163 status = connector_status_connected;
3164 return status;
3165 }
3166
232a6ee9
TP		 3167 if (IS_VALLEYVIEW(dev)) {
3168 switch (intel_dig_port->port) {
3169 case PORT_B:
3170 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3171 break;
3172 case PORT_C:
3173 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3174 break;
3175 case PORT_D:
3176 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3177 break;
3178 default:
3179 return connector_status_unknown;
3180 }
3181 } else {
3182 switch (intel_dig_port->port) {
3183 case PORT_B:
3184 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3185 break;
3186 case PORT_C:
3187 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3188 break;
3189 case PORT_D:
3190 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3191 break;
3192 default:
3193 return connector_status_unknown;
3194 }
a4fc5ed6
KP		 3195 }
3196
10f76a38 3197 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3198 return connector_status_disconnected;
3199
26d61aad 3200 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3201}
3202
8c241fef
KP		 3203static struct edid *
3204intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3205{
9cd300e0 3206 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3207
9cd300e0
JN		 3208 /* use cached edid if we have one */
3209 if (intel_connector->edid) {
9cd300e0
JN		 3210 /* invalid edid */
3211 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3212 return NULL;
3213
55e9edeb 3214 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3215 }
8c241fef 3216
9cd300e0 3217 return drm_get_edid(connector, adapter);
8c241fef
KP		 3218}
3219
3220static int
3221intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3222{
9cd300e0 3223 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3224
9cd300e0
JN		 3225 /* use cached edid if we have one */
3226 if (intel_connector->edid) {
3227 /* invalid edid */
3228 if (IS_ERR(intel_connector->edid))
3229 return 0;
3230
3231 return intel_connector_update_modes(connector,
3232 intel_connector->edid);
d6f24d0f
JB		 3233 }
3234
9cd300e0 3235 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3236}
3237
a9756bb5
ZW		 3238static enum drm_connector_status
3239intel_dp_detect(struct drm_connector *connector, bool force)
3240{
3241 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3242 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3243 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3244 struct drm_device *dev = connector->dev;
c8c8fb33 3245 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3246 enum drm_connector_status status;
671dedd2 3247 enum intel_display_power_domain power_domain;
a9756bb5
ZW		 3248 struct edid *edid = NULL;
3249
c8c8fb33
PZ		 3250 intel_runtime_pm_get(dev_priv);
3251
671dedd2
ID		 3252 power_domain = intel_display_port_power_domain(intel_encoder);
3253 intel_display_power_get(dev_priv, power_domain);
3254
164c8598
CW		 3255 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3256 connector->base.id, drm_get_connector_name(connector));
3257
a9756bb5
ZW		 3258 intel_dp->has_audio = false;
3259
3260 if (HAS_PCH_SPLIT(dev))
3261 status = ironlake_dp_detect(intel_dp);
3262 else
3263 status = g4x_dp_detect(intel_dp);
1b9be9d0 3264
a9756bb5 3265 if (status != connector_status_connected)
c8c8fb33 3266 goto out;
a9756bb5 3267
0d198328
AJ		 3268 intel_dp_probe_oui(intel_dp);
3269
c3e5f67b
DV		 3270 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3271 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3272 } else {
8c241fef 3273 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 3274 if (edid) {
3275 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3276 kfree(edid);
3277 }
a9756bb5
ZW		 3278 }
3279
d63885da
PZ		 3280 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3281 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3282 status = connector_status_connected;
3283
3284out:
671dedd2
ID		 3285 intel_display_power_put(dev_priv, power_domain);
3286
c8c8fb33 3287 intel_runtime_pm_put(dev_priv);
671dedd2 3288
c8c8fb33 3289 return status;
a4fc5ed6
KP		 3290}
3291
3292static int intel_dp_get_modes(struct drm_connector *connector)
3293{
df0e9248 3294 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3296 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3297 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3298 struct drm_device *dev = connector->dev;
671dedd2
ID		 3299 struct drm_i915_private *dev_priv = dev->dev_private;
3300 enum intel_display_power_domain power_domain;
32f9d658 3301 int ret;
a4fc5ed6
KP		 3302
3303 /* We should parse the EDID data and find out if it has an audio sink
3304 */
3305
671dedd2
ID		 3306 power_domain = intel_display_port_power_domain(intel_encoder);
3307 intel_display_power_get(dev_priv, power_domain);
3308
8c241fef 3309 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
671dedd2 3310 intel_display_power_put(dev_priv, power_domain);
f8779fda 3311 if (ret)
32f9d658
ZW		 3312 return ret;
3313
f8779fda 3314 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3315 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3316 struct drm_display_mode *mode;
dd06f90e
JN		 3317 mode = drm_mode_duplicate(dev,
3318 intel_connector->panel.fixed_mode);
f8779fda 3319 if (mode) {
32f9d658
ZW		 3320 drm_mode_probed_add(connector, mode);
3321 return 1;
3322 }
3323 }
3324 return 0;
a4fc5ed6
KP		 3325}
3326
1aad7ac0
CW		 3327static bool
3328intel_dp_detect_audio(struct drm_connector *connector)
3329{
3330 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3331 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3332 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3333 struct drm_device *dev = connector->dev;
3334 struct drm_i915_private *dev_priv = dev->dev_private;
3335 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3336 struct edid *edid;
3337 bool has_audio = false;
3338
671dedd2
ID		 3339 power_domain = intel_display_port_power_domain(intel_encoder);
3340 intel_display_power_get(dev_priv, power_domain);
3341
8c241fef 3342 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 3343 if (edid) {
3344 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3345 kfree(edid);
3346 }
3347
671dedd2
ID		 3348 intel_display_power_put(dev_priv, power_domain);
3349
1aad7ac0
CW		 3350 return has_audio;
3351}
3352
f684960e
CW		 3353static int
3354intel_dp_set_property(struct drm_connector *connector,
3355 struct drm_property *property,
3356 uint64_t val)
3357{
e953fd7b 3358 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3359 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3360 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3361 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3362 int ret;
3363
662595df 3364 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3365 if (ret)
3366 return ret;
3367
3f43c48d 3368 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3369 int i = val;
3370 bool has_audio;
3371
3372 if (i == intel_dp->force_audio)
f684960e
CW		 3373 return 0;
3374
1aad7ac0 3375 intel_dp->force_audio = i;
f684960e 3376
c3e5f67b 3377 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3378 has_audio = intel_dp_detect_audio(connector);
3379 else
c3e5f67b 3380 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3381
3382 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3383 return 0;
3384
1aad7ac0 3385 intel_dp->has_audio = has_audio;
f684960e
CW		 3386 goto done;
3387 }
3388
e953fd7b 3389 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3390 bool old_auto = intel_dp->color_range_auto;
3391 uint32_t old_range = intel_dp->color_range;
3392
55bc60db
VS		 3393 switch (val) {
3394 case INTEL_BROADCAST_RGB_AUTO:
3395 intel_dp->color_range_auto = true;
3396 break;
3397 case INTEL_BROADCAST_RGB_FULL:
3398 intel_dp->color_range_auto = false;
3399 intel_dp->color_range = 0;
3400 break;
3401 case INTEL_BROADCAST_RGB_LIMITED:
3402 intel_dp->color_range_auto = false;
3403 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3404 break;
3405 default:
3406 return -EINVAL;
3407 }
ae4edb80
DV		 3408
3409 if (old_auto == intel_dp->color_range_auto &&
3410 old_range == intel_dp->color_range)
3411 return 0;
3412
e953fd7b
CW		 3413 goto done;
3414 }
3415
53b41837
YN		 3416 if (is_edp(intel_dp) &&
3417 property == connector->dev->mode_config.scaling_mode_property) {
3418 if (val == DRM_MODE_SCALE_NONE) {
3419 DRM_DEBUG_KMS("no scaling not supported\n");
3420 return -EINVAL;
3421 }
3422
3423 if (intel_connector->panel.fitting_mode == val) {
3424 /* the eDP scaling property is not changed */
3425 return 0;
3426 }
3427 intel_connector->panel.fitting_mode = val;
3428
3429 goto done;
3430 }
3431
f684960e
CW		 3432 return -EINVAL;
3433
3434done:
c0c36b94
CW		 3435 if (intel_encoder->base.crtc)
3436 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3437
3438 return 0;
3439}
3440
a4fc5ed6 3441static void
73845adf 3442intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3443{
1d508706 3444 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3445
9cd300e0
JN		 3446 if (!IS_ERR_OR_NULL(intel_connector->edid))
3447 kfree(intel_connector->edid);
3448
acd8db10
PZ		 3449 /* Can't call is_edp() since the encoder may have been destroyed
3450 * already. */
3451 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3452 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3453
a4fc5ed6 3454 drm_connector_cleanup(connector);
55f78c43 3455 kfree(connector);
a4fc5ed6
KP		 3456}
3457
00c09d70 3458void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3459{
da63a9f2
PZ		 3460 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3461 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3462 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927
DV		 3463
3464 i2c_del_adapter(&intel_dp->adapter);
3465 drm_encoder_cleanup(encoder);
bd943159
KP		 3466 if (is_edp(intel_dp)) {
3467 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3468 mutex_lock(&dev->mode_config.mutex);
4be73780 3469 edp_panel_vdd_off_sync(intel_dp);
bd173813 3470 mutex_unlock(&dev->mode_config.mutex);
bd943159 3471 }
da63a9f2 3472 kfree(intel_dig_port);
24d05927
DV		 3473}
3474
a4fc5ed6 3475static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3476 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3477 .detect = intel_dp_detect,
3478 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3479 .set_property = intel_dp_set_property,
73845adf 3480 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3481};
3482
3483static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3484 .get_modes = intel_dp_get_modes,
3485 .mode_valid = intel_dp_mode_valid,
df0e9248 3486 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3487};
3488
a4fc5ed6 3489static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3490 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3491};
3492
995b6762 3493static void
21d40d37 3494intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3495{
fa90ecef 3496 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3497
885a5014 3498 intel_dp_check_link_status(intel_dp);
c8110e52 3499}
6207937d 3500
e3421a18
ZW		 3501/* Return which DP Port should be selected for Transcoder DP control */
3502int
0206e353 3503intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3504{
3505 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3506 struct intel_encoder *intel_encoder;
3507 struct intel_dp *intel_dp;
e3421a18 3508
fa90ecef
PZ		 3509 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3510 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3511
fa90ecef
PZ		 3512 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3513 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3514 return intel_dp->output_reg;
e3421a18 3515 }
ea5b213a 3516
e3421a18
ZW		 3517 return -1;
3518}
3519
36e83a18 3520/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3521bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3522{
3523 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3524 union child_device_config *p_child;
36e83a18 3525 int i;
5d8a7752
VS		 3526 static const short port_mapping[] = {
3527 [PORT_B] = PORT_IDPB,
3528 [PORT_C] = PORT_IDPC,
3529 [PORT_D] = PORT_IDPD,
3530 };
36e83a18 3531
3b32a35b
VS		 3532 if (port == PORT_A)
3533 return true;
3534
41aa3448 3535 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3536 return false;
3537
41aa3448
RV		 3538 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3539 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3540
5d8a7752 3541 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3542 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3543 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3544 return true;
3545 }
3546 return false;
3547}
3548
f684960e
CW		 3549static void
3550intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3551{
53b41837
YN		 3552 struct intel_connector *intel_connector = to_intel_connector(connector);
3553
3f43c48d 3554 intel_attach_force_audio_property(connector);
e953fd7b 3555 intel_attach_broadcast_rgb_property(connector);
55bc60db 3556 intel_dp->color_range_auto = true;
53b41837
YN		 3557
3558 if (is_edp(intel_dp)) {
3559 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3560 drm_object_attach_property(
3561 &connector->base,
53b41837 3562 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3563 DRM_MODE_SCALE_ASPECT);
3564 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3565 }
f684960e
CW		 3566}
3567
dada1a9f
ID		 3568static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3569{
3570 intel_dp->last_power_cycle = jiffies;
3571 intel_dp->last_power_on = jiffies;
3572 intel_dp->last_backlight_off = jiffies;
3573}
3574
67a54566
DV		 3575static void
3576intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3577 struct intel_dp *intel_dp,
3578 struct edp_power_seq *out)
67a54566
DV		 3579{
3580 struct drm_i915_private *dev_priv = dev->dev_private;
3581 struct edp_power_seq cur, vbt, spec, final;
3582 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3583 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3584
3585 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3586 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3587 pp_on_reg = PCH_PP_ON_DELAYS;
3588 pp_off_reg = PCH_PP_OFF_DELAYS;
3589 pp_div_reg = PCH_PP_DIVISOR;
3590 } else {
bf13e81b
JN		 3591 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3592
3593 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3594 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3595 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3596 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3597 }
67a54566
DV		 3598
3599 /* Workaround: Need to write PP_CONTROL with the unlock key as
3600 * the very first thing. */
453c5420 3601 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3602 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3603
453c5420
JB		 3604 pp_on = I915_READ(pp_on_reg);
3605 pp_off = I915_READ(pp_off_reg);
3606 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3607
3608 /* Pull timing values out of registers */
3609 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3610 PANEL_POWER_UP_DELAY_SHIFT;
3611
3612 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3613 PANEL_LIGHT_ON_DELAY_SHIFT;
3614
3615 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3616 PANEL_LIGHT_OFF_DELAY_SHIFT;
3617
3618 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3619 PANEL_POWER_DOWN_DELAY_SHIFT;
3620
3621 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3622 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3623
3624 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3625 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3626
41aa3448 3627 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3628
3629 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3630 * our hw here, which are all in 100usec. */
3631 spec.t1_t3 = 210 * 10;
3632 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3633 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3634 spec.t10 = 500 * 10;
3635 /* This one is special and actually in units of 100ms, but zero
3636 * based in the hw (so we need to add 100 ms). But the sw vbt
3637 * table multiplies it with 1000 to make it in units of 100usec,
3638 * too. */
3639 spec.t11_t12 = (510 + 100) * 10;
3640
3641 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3642 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3643
3644 /* Use the max of the register settings and vbt. If both are
3645 * unset, fall back to the spec limits. */
3646#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3647 spec.field : \
3648 max(cur.field, vbt.field))
3649 assign_final(t1_t3);
3650 assign_final(t8);
3651 assign_final(t9);
3652 assign_final(t10);
3653 assign_final(t11_t12);
3654#undef assign_final
3655
3656#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3657 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3658 intel_dp->backlight_on_delay = get_delay(t8);
3659 intel_dp->backlight_off_delay = get_delay(t9);
3660 intel_dp->panel_power_down_delay = get_delay(t10);
3661 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3662#undef get_delay
3663
f30d26e4
JN		 3664 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3665 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3666 intel_dp->panel_power_cycle_delay);
3667
3668 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3669 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3670
3671 if (out)
3672 *out = final;
3673}
3674
3675static void
3676intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3677 struct intel_dp *intel_dp,
3678 struct edp_power_seq *seq)
3679{
3680 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3681 u32 pp_on, pp_off, pp_div, port_sel = 0;
3682 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3683 int pp_on_reg, pp_off_reg, pp_div_reg;
3684
3685 if (HAS_PCH_SPLIT(dev)) {
3686 pp_on_reg = PCH_PP_ON_DELAYS;
3687 pp_off_reg = PCH_PP_OFF_DELAYS;
3688 pp_div_reg = PCH_PP_DIVISOR;
3689 } else {
bf13e81b
JN		 3690 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3691
3692 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3693 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3694 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3695 }
3696
b2f19d1a
PZ		 3697 /*
3698 * And finally store the new values in the power sequencer. The
3699 * backlight delays are set to 1 because we do manual waits on them. For
3700 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3701 * we'll end up waiting for the backlight off delay twice: once when we
3702 * do the manual sleep, and once when we disable the panel and wait for
3703 * the PP_STATUS bit to become zero.
3704 */
f30d26e4 3705 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 3706 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3707 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 3708 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3709 /* Compute the divisor for the pp clock, simply match the Bspec
3710 * formula. */
453c5420 3711 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3712 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3713 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3714
3715 /* Haswell doesn't have any port selection bits for the panel
3716 * power sequencer any more. */
bc7d38a4 3717 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3718 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3719 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3720 else
3721 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3722 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3723 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3724 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3725 else
a24c144c 3726 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3727 }
3728
453c5420
JB		 3729 pp_on |= port_sel;
3730
3731 I915_WRITE(pp_on_reg, pp_on);
3732 I915_WRITE(pp_off_reg, pp_off);
3733 I915_WRITE(pp_div_reg, pp_div);
67a54566 3734
67a54566 3735 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3736 I915_READ(pp_on_reg),
3737 I915_READ(pp_off_reg),
3738 I915_READ(pp_div_reg));
f684960e
CW		 3739}
3740
ed92f0b2 3741static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 3742 struct intel_connector *intel_connector,
3743 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 3744{
3745 struct drm_connector *connector = &intel_connector->base;
3746 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3747 struct drm_device *dev = intel_dig_port->base.base.dev;
3748 struct drm_i915_private *dev_priv = dev->dev_private;
3749 struct drm_display_mode *fixed_mode = NULL;
ed92f0b2
PZ		 3750 bool has_dpcd;
3751 struct drm_display_mode *scan;
3752 struct edid *edid;
3753
3754 if (!is_edp(intel_dp))
3755 return true;
3756
ed92f0b2 3757 /* Cache DPCD and EDID for edp. */
4be73780 3758 edp_panel_vdd_on(intel_dp);
ed92f0b2 3759 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 3760 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 3761
3762 if (has_dpcd) {
3763 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3764 dev_priv->no_aux_handshake =
3765 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3766 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3767 } else {
3768 /* if this fails, presume the device is a ghost */
3769 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3770 return false;
3771 }
3772
3773 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 3774 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 3775
ed92f0b2
PZ		 3776 edid = drm_get_edid(connector, &intel_dp->adapter);
3777 if (edid) {
3778 if (drm_add_edid_modes(connector, edid)) {
3779 drm_mode_connector_update_edid_property(connector,
3780 edid);
3781 drm_edid_to_eld(connector, edid);
3782 } else {
3783 kfree(edid);
3784 edid = ERR_PTR(-EINVAL);
3785 }
3786 } else {
3787 edid = ERR_PTR(-ENOENT);
3788 }
3789 intel_connector->edid = edid;
3790
3791 /* prefer fixed mode from EDID if available */
3792 list_for_each_entry(scan, &connector->probed_modes, head) {
3793 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3794 fixed_mode = drm_mode_duplicate(dev, scan);
3795 break;
3796 }
3797 }
3798
3799 /* fallback to VBT if available for eDP */
3800 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3801 fixed_mode = drm_mode_duplicate(dev,
3802 dev_priv->vbt.lfp_lvds_vbt_mode);
3803 if (fixed_mode)
3804 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3805 }
3806
4b6ed685 3807 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
ed92f0b2
PZ		 3808 intel_panel_setup_backlight(connector);
3809
3810 return true;
3811}
3812
16c25533 3813bool
f0fec3f2
PZ		 3814intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3815 struct intel_connector *intel_connector)
a4fc5ed6 3816{
f0fec3f2
PZ		 3817 struct drm_connector *connector = &intel_connector->base;
3818 struct intel_dp *intel_dp = &intel_dig_port->dp;
3819 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3820 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3821 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3822 enum port port = intel_dig_port->port;
0095e6dc 3823 struct edp_power_seq power_seq = { 0 };
5eb08b69 3824 const char *name = NULL;
b2a14755 3825 int type, error;
a4fc5ed6 3826
ec5b01dd
DL		 3827 /* intel_dp vfuncs */
3828 if (IS_VALLEYVIEW(dev))
3829 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3830 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3831 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3832 else if (HAS_PCH_SPLIT(dev))
3833 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3834 else
3835 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3836
153b1100
DL		 3837 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3838
0767935e
DV		 3839 /* Preserve the current hw state. */
3840 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3841 intel_dp->attached_connector = intel_connector;
3d3dc149 3842
3b32a35b 3843 if (intel_dp_is_edp(dev, port))
b329530c 3844 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 3845 else
3846 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 3847
f7d24902
ID		 3848 /*
3849 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3850 * for DP the encoder type can be set by the caller to
3851 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3852 */
3853 if (type == DRM_MODE_CONNECTOR_eDP)
3854 intel_encoder->type = INTEL_OUTPUT_EDP;
3855
e7281eab
ID		 3856 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3857 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3858 port_name(port));
3859
b329530c 3860 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3861 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3862
a4fc5ed6
KP		 3863 connector->interlace_allowed = true;
3864 connector->doublescan_allowed = 0;
3865
f0fec3f2 3866 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 3867 edp_panel_vdd_work);
a4fc5ed6 3868
df0e9248 3869 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3870 drm_sysfs_connector_add(connector);
3871
affa9354 3872 if (HAS_DDI(dev))
bcbc889b
PZ		 3873 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3874 else
3875 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 3876 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 3877
9ed35ab1
PZ		 3878 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3879 if (HAS_DDI(dev)) {
3880 switch (intel_dig_port->port) {
3881 case PORT_A:
3882 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3883 break;
3884 case PORT_B:
3885 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3886 break;
3887 case PORT_C:
3888 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3889 break;
3890 case PORT_D:
3891 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3892 break;
3893 default:
3894 BUG();
3895 }
3896 }
e8cb4558 3897
a4fc5ed6 3898 /* Set up the DDC bus. */
ab9d7c30
PZ		 3899 switch (port) {
3900 case PORT_A:
1d843f9d 3901 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3902 name = "DPDDC-A";
3903 break;
3904 case PORT_B:
1d843f9d 3905 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3906 name = "DPDDC-B";
3907 break;
3908 case PORT_C:
1d843f9d 3909 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3910 name = "DPDDC-C";
3911 break;
3912 case PORT_D:
1d843f9d 3913 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3914 name = "DPDDC-D";
3915 break;
3916 default:
ad1c0b19 3917 BUG();
5eb08b69
ZW		 3918 }
3919
dada1a9f
ID		 3920 if (is_edp(intel_dp)) {
3921 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 3922 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 3923 }
0095e6dc 3924
b2a14755
PZ		 3925 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3926 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3927 error, port_name(port));
c1f05264 3928
2b28bb1b
RV		 3929 intel_dp->psr_setup_done = false;
3930
0095e6dc 3931 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
15b1d171
PZ		 3932 i2c_del_adapter(&intel_dp->adapter);
3933 if (is_edp(intel_dp)) {
3934 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3935 mutex_lock(&dev->mode_config.mutex);
4be73780 3936 edp_panel_vdd_off_sync(intel_dp);
15b1d171
PZ		 3937 mutex_unlock(&dev->mode_config.mutex);
3938 }
b2f246a8
PZ		 3939 drm_sysfs_connector_remove(connector);
3940 drm_connector_cleanup(connector);
16c25533 3941 return false;
b2f246a8 3942 }
32f9d658 3943
f684960e
CW		 3944 intel_dp_add_properties(intel_dp, connector);
3945
a4fc5ed6
KP		 3946 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3947 * 0xd. Failure to do so will result in spurious interrupts being
3948 * generated on the port when a cable is not attached.
3949 */
3950 if (IS_G4X(dev) && !IS_GM45(dev)) {
3951 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3952 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3953 }
16c25533
PZ		 3954
3955 return true;
a4fc5ed6 3956}
f0fec3f2
PZ		 3957
3958void
3959intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3960{
3961 struct intel_digital_port *intel_dig_port;
3962 struct intel_encoder *intel_encoder;
3963 struct drm_encoder *encoder;
3964 struct intel_connector *intel_connector;
3965
b14c5679 3966 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 3967 if (!intel_dig_port)
3968 return;
3969
b14c5679 3970 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 3971 if (!intel_connector) {
3972 kfree(intel_dig_port);
3973 return;
3974 }
3975
3976 intel_encoder = &intel_dig_port->base;
3977 encoder = &intel_encoder->base;
3978
3979 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3980 DRM_MODE_ENCODER_TMDS);
3981
5bfe2ac0 3982 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 3983 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70
PZ		 3984 intel_encoder->disable = intel_disable_dp;
3985 intel_encoder->post_disable = intel_post_disable_dp;
3986 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3987 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 3988 if (IS_VALLEYVIEW(dev)) {
ecff4f3b 3989 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 3990 intel_encoder->pre_enable = vlv_pre_enable_dp;
3991 intel_encoder->enable = vlv_enable_dp;
3992 } else {
ecff4f3b
JN		 3993 intel_encoder->pre_enable = g4x_pre_enable_dp;
3994 intel_encoder->enable = g4x_enable_dp;
ab1f90f9 3995 }
f0fec3f2 3996
174edf1f 3997 intel_dig_port->port = port;
f0fec3f2
PZ		 3998 intel_dig_port->dp.output_reg = output_reg;
3999
00c09d70 4000 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 4001 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4002 intel_encoder->cloneable = false;
4003 intel_encoder->hot_plug = intel_dp_hot_plug;
4004
15b1d171
PZ		 4005 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4006 drm_encoder_cleanup(encoder);
4007 kfree(intel_dig_port);
b2f246a8 4008 kfree(intel_connector);
15b1d171 4009 }
f0fec3f2 4010}
Linux kernel - Deliverables
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