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drm/i915: add missing error capturing of the PIPESTAT reg
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
cfcb0fc9
JB		 67/**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74static bool is_edp(struct intel_dp *intel_dp)
75{
da63a9f2
PZ		 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 79}
80
68b4d824 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 82{
68b4d824
ID		 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 86}
87
df0e9248
CW		 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89{
fa90ecef 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 91}
92
ea5b213a 93static void intel_dp_link_down(struct intel_dp *intel_dp);
adddaaf4 94static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 95static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 96
a4fc5ed6 97static int
ea5b213a 98intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 99{
7183dc29 100 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 101 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 102
103 switch (max_link_bw) {
104 case DP_LINK_BW_1_62:
105 case DP_LINK_BW_2_7:
106 break;
d4eead50 107 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
06ea66b6
TP		 108 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
109 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
110 max_link_bw = DP_LINK_BW_5_4;
111 else
112 max_link_bw = DP_LINK_BW_2_7;
d4eead50 113 break;
a4fc5ed6 114 default:
d4eead50
ID		 115 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
116 max_link_bw);
a4fc5ed6
KP		 117 max_link_bw = DP_LINK_BW_1_62;
118 break;
119 }
120 return max_link_bw;
121}
122
cd9dde44
AJ		 123/*
124 * The units on the numbers in the next two are... bizarre. Examples will
125 * make it clearer; this one parallels an example in the eDP spec.
126 *
127 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
128 *
129 * 270000 * 1 * 8 / 10 == 216000
130 *
131 * The actual data capacity of that configuration is 2.16Gbit/s, so the
132 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
133 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
134 * 119000. At 18bpp that's 2142000 kilobits per second.
135 *
136 * Thus the strange-looking division by 10 in intel_dp_link_required, to
137 * get the result in decakilobits instead of kilobits.
138 */
139
a4fc5ed6 140static int
c898261c 141intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 142{
cd9dde44 143 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 144}
145
fe27d53e
DA		 146static int
147intel_dp_max_data_rate(int max_link_clock, int max_lanes)
148{
149 return (max_link_clock * max_lanes * 8) / 10;
150}
151
c19de8eb 152static enum drm_mode_status
a4fc5ed6
KP		 153intel_dp_mode_valid(struct drm_connector *connector,
154 struct drm_display_mode *mode)
155{
df0e9248 156 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 157 struct intel_connector *intel_connector = to_intel_connector(connector);
158 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 159 int target_clock = mode->clock;
160 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 161
dd06f90e
JN		 162 if (is_edp(intel_dp) && fixed_mode) {
163 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 164 return MODE_PANEL;
165
dd06f90e 166 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 167 return MODE_PANEL;
03afc4a2
DV		 168
169 target_clock = fixed_mode->clock;
7de56f43
ZY		 170 }
171
36008365
DV		 172 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
173 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
174
175 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
176 mode_rate = intel_dp_link_required(target_clock, 18);
177
178 if (mode_rate > max_rate)
c4867936 179 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 180
181 if (mode->clock < 10000)
182 return MODE_CLOCK_LOW;
183
0af78a2b
DV		 184 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
185 return MODE_H_ILLEGAL;
186
a4fc5ed6
KP		 187 return MODE_OK;
188}
189
190static uint32_t
191pack_aux(uint8_t *src, int src_bytes)
192{
193 int i;
194 uint32_t v = 0;
195
196 if (src_bytes > 4)
197 src_bytes = 4;
198 for (i = 0; i < src_bytes; i++)
199 v |= ((uint32_t) src[i]) << ((3-i) * 8);
200 return v;
201}
202
203static void
204unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
205{
206 int i;
207 if (dst_bytes > 4)
208 dst_bytes = 4;
209 for (i = 0; i < dst_bytes; i++)
210 dst[i] = src >> ((3-i) * 8);
211}
212
fb0f8fbf
KP		 213/* hrawclock is 1/4 the FSB frequency */
214static int
215intel_hrawclk(struct drm_device *dev)
216{
217 struct drm_i915_private *dev_priv = dev->dev_private;
218 uint32_t clkcfg;
219
9473c8f4
VP		 220 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
221 if (IS_VALLEYVIEW(dev))
222 return 200;
223
fb0f8fbf
KP		 224 clkcfg = I915_READ(CLKCFG);
225 switch (clkcfg & CLKCFG_FSB_MASK) {
226 case CLKCFG_FSB_400:
227 return 100;
228 case CLKCFG_FSB_533:
229 return 133;
230 case CLKCFG_FSB_667:
231 return 166;
232 case CLKCFG_FSB_800:
233 return 200;
234 case CLKCFG_FSB_1067:
235 return 266;
236 case CLKCFG_FSB_1333:
237 return 333;
238 /* these two are just a guess; one of them might be right */
239 case CLKCFG_FSB_1600:
240 case CLKCFG_FSB_1600_ALT:
241 return 400;
242 default:
243 return 133;
244 }
245}
246
bf13e81b
JN		 247static void
248intel_dp_init_panel_power_sequencer(struct drm_device *dev,
249 struct intel_dp *intel_dp,
250 struct edp_power_seq *out);
251static void
252intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
253 struct intel_dp *intel_dp,
254 struct edp_power_seq *out);
255
256static enum pipe
257vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
258{
259 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
260 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
261 struct drm_device *dev = intel_dig_port->base.base.dev;
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 enum port port = intel_dig_port->port;
264 enum pipe pipe;
265
266 /* modeset should have pipe */
267 if (crtc)
268 return to_intel_crtc(crtc)->pipe;
269
270 /* init time, try to find a pipe with this port selected */
271 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
272 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
273 PANEL_PORT_SELECT_MASK;
274 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
275 return pipe;
276 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
277 return pipe;
278 }
279
280 /* shrug */
281 return PIPE_A;
282}
283
284static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
285{
286 struct drm_device *dev = intel_dp_to_dev(intel_dp);
287
288 if (HAS_PCH_SPLIT(dev))
289 return PCH_PP_CONTROL;
290 else
291 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
292}
293
294static u32 _pp_stat_reg(struct intel_dp *intel_dp)
295{
296 struct drm_device *dev = intel_dp_to_dev(intel_dp);
297
298 if (HAS_PCH_SPLIT(dev))
299 return PCH_PP_STATUS;
300 else
301 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
302}
303
4be73780 304static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 305{
30add22d 306 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 307 struct drm_i915_private *dev_priv = dev->dev_private;
308
bf13e81b 309 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 310}
311
4be73780 312static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 313{
30add22d 314 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 315 struct drm_i915_private *dev_priv = dev->dev_private;
316
efbc20ab
PZ		 317 return !dev_priv->pm.suspended &&
318 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 319}
320
9b984dae
KP		 321static void
322intel_dp_check_edp(struct intel_dp *intel_dp)
323{
30add22d 324 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 325 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 326
9b984dae
KP		 327 if (!is_edp(intel_dp))
328 return;
453c5420 329
4be73780 330 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 331 WARN(1, "eDP powered off while attempting aux channel communication.\n");
332 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 333 I915_READ(_pp_stat_reg(intel_dp)),
334 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 335 }
336}
337
9ee32fea
DV		 338static uint32_t
339intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
340{
341 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
342 struct drm_device *dev = intel_dig_port->base.base.dev;
343 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 344 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 345 uint32_t status;
346 bool done;
347
ef04f00d 348#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 349 if (has_aux_irq)
b18ac466 350 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 351 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 352 else
353 done = wait_for_atomic(C, 10) == 0;
354 if (!done)
355 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
356 has_aux_irq);
357#undef C
358
359 return status;
360}
361
ec5b01dd 362static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 363{
174edf1f
PZ		 364 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
365 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 366
ec5b01dd
DL		 367 /*
368 * The clock divider is based off the hrawclk, and would like to run at
369 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 370 */
ec5b01dd
DL		 371 return index ? 0 : intel_hrawclk(dev) / 2;
372}
373
374static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
375{
376 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
377 struct drm_device *dev = intel_dig_port->base.base.dev;
378
379 if (index)
380 return 0;
381
382 if (intel_dig_port->port == PORT_A) {
383 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 384 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 385 else
b84a1cf8 386 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 387 } else {
388 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
389 }
390}
391
392static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
393{
394 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
395 struct drm_device *dev = intel_dig_port->base.base.dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
397
398 if (intel_dig_port->port == PORT_A) {
399 if (index)
400 return 0;
401 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 402 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
403 /* Workaround for non-ULT HSW */
bc86625a
CW		 404 switch (index) {
405 case 0: return 63;
406 case 1: return 72;
407 default: return 0;
408 }
ec5b01dd 409 } else {
bc86625a 410 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 411 }
b84a1cf8
RV		 412}
413
ec5b01dd
DL		 414static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
415{
416 return index ? 0 : 100;
417}
418
5ed12a19
DL		 419static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
420 bool has_aux_irq,
421 int send_bytes,
422 uint32_t aux_clock_divider)
423{
424 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
425 struct drm_device *dev = intel_dig_port->base.base.dev;
426 uint32_t precharge, timeout;
427
428 if (IS_GEN6(dev))
429 precharge = 3;
430 else
431 precharge = 5;
432
433 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
434 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
435 else
436 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
437
438 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 439 DP_AUX_CH_CTL_DONE |
5ed12a19 440 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 441 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 442 timeout |
788d4433 443 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 444 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
445 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 446 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 447}
448
b84a1cf8
RV		 449static int
450intel_dp_aux_ch(struct intel_dp *intel_dp,
451 uint8_t *send, int send_bytes,
452 uint8_t *recv, int recv_size)
453{
454 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
455 struct drm_device *dev = intel_dig_port->base.base.dev;
456 struct drm_i915_private *dev_priv = dev->dev_private;
457 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
458 uint32_t ch_data = ch_ctl + 4;
bc86625a 459 uint32_t aux_clock_divider;
b84a1cf8
RV		 460 int i, ret, recv_bytes;
461 uint32_t status;
5ed12a19 462 int try, clock = 0;
4e6b788c 463 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 464 bool vdd;
465
466 vdd = _edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 467
468 /* dp aux is extremely sensitive to irq latency, hence request the
469 * lowest possible wakeup latency and so prevent the cpu from going into
470 * deep sleep states.
471 */
472 pm_qos_update_request(&dev_priv->pm_qos, 0);
473
474 intel_dp_check_edp(intel_dp);
5eb08b69 475
c67a470b
PZ		 476 intel_aux_display_runtime_get(dev_priv);
477
11bee43e
JB		 478 /* Try to wait for any previous AUX channel activity */
479 for (try = 0; try < 3; try++) {
ef04f00d 480 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 481 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
482 break;
483 msleep(1);
484 }
485
486 if (try == 3) {
487 WARN(1, "dp_aux_ch not started status 0x%08x\n",
488 I915_READ(ch_ctl));
9ee32fea
DV		 489 ret = -EBUSY;
490 goto out;
4f7f7b7e
CW		 491 }
492
46a5ae9f
PZ		 493 /* Only 5 data registers! */
494 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
495 ret = -E2BIG;
496 goto out;
497 }
498
ec5b01dd 499 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 500 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
501 has_aux_irq,
502 send_bytes,
503 aux_clock_divider);
5ed12a19 504
bc86625a
CW		 505 /* Must try at least 3 times according to DP spec */
506 for (try = 0; try < 5; try++) {
507 /* Load the send data into the aux channel data registers */
508 for (i = 0; i < send_bytes; i += 4)
509 I915_WRITE(ch_data + i,
510 pack_aux(send + i, send_bytes - i));
511
512 /* Send the command and wait for it to complete */
5ed12a19 513 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 514
515 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
516
517 /* Clear done status and any errors */
518 I915_WRITE(ch_ctl,
519 status |
520 DP_AUX_CH_CTL_DONE |
521 DP_AUX_CH_CTL_TIME_OUT_ERROR |
522 DP_AUX_CH_CTL_RECEIVE_ERROR);
523
524 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
525 DP_AUX_CH_CTL_RECEIVE_ERROR))
526 continue;
527 if (status & DP_AUX_CH_CTL_DONE)
528 break;
529 }
4f7f7b7e 530 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 531 break;
532 }
533
a4fc5ed6 534 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 535 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 536 ret = -EBUSY;
537 goto out;
a4fc5ed6
KP		 538 }
539
540 /* Check for timeout or receive error.
541 * Timeouts occur when the sink is not connected
542 */
a5b3da54 543 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 544 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 545 ret = -EIO;
546 goto out;
a5b3da54 547 }
1ae8c0a5
KP		 548
549 /* Timeouts occur when the device isn't connected, so they're
550 * "normal" -- don't fill the kernel log with these */
a5b3da54 551 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 552 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 553 ret = -ETIMEDOUT;
554 goto out;
a4fc5ed6
KP		 555 }
556
557 /* Unload any bytes sent back from the other side */
558 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
559 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 560 if (recv_bytes > recv_size)
561 recv_bytes = recv_size;
0206e353 562
4f7f7b7e
CW		 563 for (i = 0; i < recv_bytes; i += 4)
564 unpack_aux(I915_READ(ch_data + i),
565 recv + i, recv_bytes - i);
a4fc5ed6 566
9ee32fea
DV		 567 ret = recv_bytes;
568out:
569 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 570 intel_aux_display_runtime_put(dev_priv);
9ee32fea 571
884f19e9
JN		 572 if (vdd)
573 edp_panel_vdd_off(intel_dp, false);
574
9ee32fea 575 return ret;
a4fc5ed6
KP		 576}
577
a6c8aff0
JN		 578#define BARE_ADDRESS_SIZE 3
579#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 580static ssize_t
581intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 582{
9d1a1031
JN		 583 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
584 uint8_t txbuf[20], rxbuf[20];
585 size_t txsize, rxsize;
a4fc5ed6 586 int ret;
a4fc5ed6 587
9d1a1031
JN		 588 txbuf[0] = msg->request << 4;
589 txbuf[1] = msg->address >> 8;
590 txbuf[2] = msg->address & 0xff;
591 txbuf[3] = msg->size - 1;
46a5ae9f 592
9d1a1031
JN		 593 switch (msg->request & ~DP_AUX_I2C_MOT) {
594 case DP_AUX_NATIVE_WRITE:
595 case DP_AUX_I2C_WRITE:
a6c8aff0 596 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 597 rxsize = 1;
f51a44b9 598
9d1a1031
JN		 599 if (WARN_ON(txsize > 20))
600 return -E2BIG;
a4fc5ed6 601
9d1a1031 602 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 603
9d1a1031
JN		 604 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
605 if (ret > 0) {
606 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 607
9d1a1031
JN		 608 /* Return payload size. */
609 ret = msg->size;
610 }
611 break;
46a5ae9f 612
9d1a1031
JN		 613 case DP_AUX_NATIVE_READ:
614 case DP_AUX_I2C_READ:
a6c8aff0 615 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 616 rxsize = msg->size + 1;
a4fc5ed6 617
9d1a1031
JN		 618 if (WARN_ON(rxsize > 20))
619 return -E2BIG;
a4fc5ed6 620
9d1a1031
JN		 621 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
622 if (ret > 0) {
623 msg->reply = rxbuf[0] >> 4;
624 /*
625 * Assume happy day, and copy the data. The caller is
626 * expected to check msg->reply before touching it.
627 *
628 * Return payload size.
629 */
630 ret--;
631 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 632 }
9d1a1031
JN		 633 break;
634
635 default:
636 ret = -EINVAL;
637 break;
a4fc5ed6 638 }
f51a44b9 639
9d1a1031 640 return ret;
a4fc5ed6
KP		 641}
642
9d1a1031
JN		 643static void
644intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
645{
646 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 647 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
648 enum port port = intel_dig_port->port;
0b99836f 649 const char *name = NULL;
ab2c0672
DA		 650 int ret;
651
33ad6626
JN		 652 switch (port) {
653 case PORT_A:
654 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 655 name = "DPDDC-A";
ab2c0672 656 break;
33ad6626
JN		 657 case PORT_B:
658 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 659 name = "DPDDC-B";
ab2c0672 660 break;
33ad6626
JN		 661 case PORT_C:
662 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 663 name = "DPDDC-C";
ab2c0672 664 break;
33ad6626
JN		 665 case PORT_D:
666 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 667 name = "DPDDC-D";
33ad6626
JN		 668 break;
669 default:
670 BUG();
ab2c0672
DA		 671 }
672
33ad6626
JN		 673 if (!HAS_DDI(dev))
674 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 675
0b99836f 676 intel_dp->aux.name = name;
9d1a1031
JN		 677 intel_dp->aux.dev = dev->dev;
678 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 679
0b99836f
JN		 680 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
681 connector->base.kdev->kobj.name);
8316f337 682
0b99836f
JN		 683 ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux);
684 if (ret < 0) {
685 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n",
686 name, ret);
687 return;
ab2c0672 688 }
8a5e6aeb 689
0b99836f
JN		 690 ret = sysfs_create_link(&connector->base.kdev->kobj,
691 &intel_dp->aux.ddc.dev.kobj,
692 intel_dp->aux.ddc.dev.kobj.name);
693 if (ret < 0) {
694 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
695 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
ab2c0672 696 }
a4fc5ed6
KP		 697}
698
80f65de3
ID		 699static void
700intel_dp_connector_unregister(struct intel_connector *intel_connector)
701{
702 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
703
704 sysfs_remove_link(&intel_connector->base.kdev->kobj,
0b99836f 705 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 706 intel_connector_unregister(intel_connector);
707}
708
c6bb3538
DV		 709static void
710intel_dp_set_clock(struct intel_encoder *encoder,
711 struct intel_crtc_config *pipe_config, int link_bw)
712{
713 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 714 const struct dp_link_dpll *divisor = NULL;
715 int i, count = 0;
c6bb3538
DV		 716
717 if (IS_G4X(dev)) {
9dd4ffdf
CML		 718 divisor = gen4_dpll;
719 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 720 } else if (IS_HASWELL(dev)) {
721 /* Haswell has special-purpose DP DDI clocks. */
722 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 723 divisor = pch_dpll;
724 count = ARRAY_SIZE(pch_dpll);
c6bb3538 725 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 726 divisor = vlv_dpll;
727 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 728 }
9dd4ffdf
CML		 729
730 if (divisor && count) {
731 for (i = 0; i < count; i++) {
732 if (link_bw == divisor[i].link_bw) {
733 pipe_config->dpll = divisor[i].dpll;
734 pipe_config->clock_set = true;
735 break;
736 }
737 }
c6bb3538
DV		 738 }
739}
740
439d7ac0
PB		 741static void
742intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
743{
744 struct drm_device *dev = crtc->base.dev;
745 struct drm_i915_private *dev_priv = dev->dev_private;
746 enum transcoder transcoder = crtc->config.cpu_transcoder;
747
748 I915_WRITE(PIPE_DATA_M2(transcoder),
749 TU_SIZE(m_n->tu) | m_n->gmch_m);
750 I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
751 I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
752 I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
753}
754
00c09d70 755bool
5bfe2ac0
DV		 756intel_dp_compute_config(struct intel_encoder *encoder,
757 struct intel_crtc_config *pipe_config)
a4fc5ed6 758{
5bfe2ac0 759 struct drm_device *dev = encoder->base.dev;
36008365 760 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 761 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 762 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 763 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 764 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 765 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 766 int lane_count, clock;
397fe157 767 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
06ea66b6
TP		 768 /* Conveniently, the link BW constants become indices with a shift...*/
769 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 770 int bpp, mode_rate;
06ea66b6 771 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 772 int link_avail, link_clock;
a4fc5ed6 773
bc7d38a4 774 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 775 pipe_config->has_pch_encoder = true;
776
03afc4a2 777 pipe_config->has_dp_encoder = true;
a4fc5ed6 778
dd06f90e
JN		 779 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
780 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
781 adjusted_mode);
2dd24552
JB		 782 if (!HAS_PCH_SPLIT(dev))
783 intel_gmch_panel_fitting(intel_crtc, pipe_config,
784 intel_connector->panel.fitting_mode);
785 else
b074cec8
JB		 786 intel_pch_panel_fitting(intel_crtc, pipe_config,
787 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 788 }
789
cb1793ce 790 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 791 return false;
792
083f9560
DV		 793 DRM_DEBUG_KMS("DP link computation with max lane count %i "
794 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 795 max_lane_count, bws[max_clock],
796 adjusted_mode->crtc_clock);
083f9560 797
36008365
DV		 798 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
799 * bpc in between. */
3e7ca985 800 bpp = pipe_config->pipe_bpp;
6da7f10d
JN		 801 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
802 dev_priv->vbt.edp_bpp < bpp) {
7984211e
ID		 803 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
804 dev_priv->vbt.edp_bpp);
6da7f10d 805 bpp = dev_priv->vbt.edp_bpp;
7984211e 806 }
657445fe 807
36008365 808 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 809 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
810 bpp);
36008365 811
38aecea0
DV		 812 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
813 for (clock = 0; clock <= max_clock; clock++) {
36008365
DV		 814 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
815 link_avail = intel_dp_max_data_rate(link_clock,
816 lane_count);
817
818 if (mode_rate <= link_avail) {
819 goto found;
820 }
821 }
822 }
823 }
c4867936 824
36008365 825 return false;
3685a8f3 826
36008365 827found:
55bc60db
VS		 828 if (intel_dp->color_range_auto) {
829 /*
830 * See:
831 * CEA-861-E - 5.1 Default Encoding Parameters
832 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
833 */
18316c8c 834 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 835 intel_dp->color_range = DP_COLOR_RANGE_16_235;
836 else
837 intel_dp->color_range = 0;
838 }
839
3685a8f3 840 if (intel_dp->color_range)
50f3b016 841 pipe_config->limited_color_range = true;
a4fc5ed6 842
36008365
DV		 843 intel_dp->link_bw = bws[clock];
844 intel_dp->lane_count = lane_count;
657445fe 845 pipe_config->pipe_bpp = bpp;
ff9a6750 846 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 847
36008365
DV		 848 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
849 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 850 pipe_config->port_clock, bpp);
36008365
DV		 851 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
852 mode_rate, link_avail);
a4fc5ed6 853
03afc4a2 854 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 855 adjusted_mode->crtc_clock,
856 pipe_config->port_clock,
03afc4a2 857 &pipe_config->dp_m_n);
9d1a455b 858
439d7ac0
PB		 859 if (intel_connector->panel.downclock_mode != NULL &&
860 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
861 intel_link_compute_m_n(bpp, lane_count,
862 intel_connector->panel.downclock_mode->clock,
863 pipe_config->port_clock,
864 &pipe_config->dp_m2_n2);
865 }
866
c6bb3538
DV		 867 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
868
03afc4a2 869 return true;
a4fc5ed6
KP		 870}
871
7c62a164 872static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 873{
7c62a164
DV		 874 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
875 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
876 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 877 struct drm_i915_private *dev_priv = dev->dev_private;
878 u32 dpa_ctl;
879
ff9a6750 880 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 881 dpa_ctl = I915_READ(DP_A);
882 dpa_ctl &= ~DP_PLL_FREQ_MASK;
883
ff9a6750 884 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 885 /* For a long time we've carried around a ILK-DevA w/a for the
886 * 160MHz clock. If we're really unlucky, it's still required.
887 */
888 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 889 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 890 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 891 } else {
892 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 893 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 894 }
1ce17038 895
ea9b6006
DV		 896 I915_WRITE(DP_A, dpa_ctl);
897
898 POSTING_READ(DP_A);
899 udelay(500);
900}
901
b934223d 902static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 903{
b934223d 904 struct drm_device *dev = encoder->base.dev;
417e822d 905 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 906 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 907 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 908 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
909 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 910
417e822d 911 /*
1a2eb460 912 * There are four kinds of DP registers:
417e822d
KP		 913 *
914 * IBX PCH
1a2eb460
KP		 915 * SNB CPU
916 * IVB CPU
417e822d
KP		 917 * CPT PCH
918 *
919 * IBX PCH and CPU are the same for almost everything,
920 * except that the CPU DP PLL is configured in this
921 * register
922 *
923 * CPT PCH is quite different, having many bits moved
924 * to the TRANS_DP_CTL register instead. That
925 * configuration happens (oddly) in ironlake_pch_enable
926 */
9c9e7927 927
417e822d
KP		 928 /* Preserve the BIOS-computed detected bit. This is
929 * supposed to be read-only.
930 */
931 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 932
417e822d 933 /* Handle DP bits in common between all three register formats */
417e822d 934 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 935 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 936
e0dac65e
WF		 937 if (intel_dp->has_audio) {
938 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 939 pipe_name(crtc->pipe));
ea5b213a 940 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 941 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 942 }
247d89f6 943
417e822d 944 /* Split out the IBX/CPU vs CPT settings */
32f9d658 945
bc7d38a4 946 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 947 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
948 intel_dp->DP |= DP_SYNC_HS_HIGH;
949 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
950 intel_dp->DP |= DP_SYNC_VS_HIGH;
951 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
952
6aba5b6c 953 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 954 intel_dp->DP |= DP_ENHANCED_FRAMING;
955
7c62a164 956 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 957 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 958 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 959 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 960
961 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
962 intel_dp->DP |= DP_SYNC_HS_HIGH;
963 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
964 intel_dp->DP |= DP_SYNC_VS_HIGH;
965 intel_dp->DP |= DP_LINK_TRAIN_OFF;
966
6aba5b6c 967 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 968 intel_dp->DP |= DP_ENHANCED_FRAMING;
969
7c62a164 970 if (crtc->pipe == 1)
417e822d 971 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 972 } else {
973 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 974 }
ea9b6006 975
bc7d38a4 976 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 977 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 978}
979
ffd6749d
PZ		 980#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
981#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 982
1a5ef5b7
PZ		 983#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
984#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 985
ffd6749d
PZ		 986#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
987#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 988
4be73780 989static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 990 u32 mask,
991 u32 value)
bd943159 992{
30add22d 993 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 994 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 995 u32 pp_stat_reg, pp_ctrl_reg;
996
bf13e81b
JN		 997 pp_stat_reg = _pp_stat_reg(intel_dp);
998 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 999
99ea7127 1000 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1001 mask, value,
1002 I915_READ(pp_stat_reg),
1003 I915_READ(pp_ctrl_reg));
32ce697c 1004
453c5420 1005 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1006 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1007 I915_READ(pp_stat_reg),
1008 I915_READ(pp_ctrl_reg));
32ce697c 1009 }
54c136d4
CW		 1010
1011 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1012}
32ce697c 1013
4be73780 1014static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1015{
1016 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1017 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1018}
1019
4be73780 1020static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1021{
1022 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1023 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1024}
1025
4be73780 1026static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1027{
1028 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1029
1030 /* When we disable the VDD override bit last we have to do the manual
1031 * wait. */
1032 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1033 intel_dp->panel_power_cycle_delay);
1034
4be73780 1035 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1036}
1037
4be73780 1038static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1039{
1040 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1041 intel_dp->backlight_on_delay);
1042}
1043
4be73780 1044static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1045{
1046 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1047 intel_dp->backlight_off_delay);
1048}
99ea7127 1049
832dd3c1
KP		 1050/* Read the current pp_control value, unlocking the register if it
1051 * is locked
1052 */
1053
453c5420 1054static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1055{
453c5420
JB		 1056 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1057 struct drm_i915_private *dev_priv = dev->dev_private;
1058 u32 control;
832dd3c1 1059
bf13e81b 1060 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1061 control &= ~PANEL_UNLOCK_MASK;
1062 control |= PANEL_UNLOCK_REGS;
1063 return control;
bd943159
KP		 1064}
1065
adddaaf4 1066static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1067{
30add22d 1068 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1069 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1070 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1071 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1072 enum intel_display_power_domain power_domain;
5d613501 1073 u32 pp;
453c5420 1074 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1075 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1076
97af61f5 1077 if (!is_edp(intel_dp))
adddaaf4 1078 return false;
bd943159
KP		 1079
1080 intel_dp->want_panel_vdd = true;
99ea7127 1081
4be73780 1082 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1083 return need_to_disable;
b0665d57 1084
4e6e1a54
ID		 1085 power_domain = intel_display_port_power_domain(intel_encoder);
1086 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1087
b0665d57 1088 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1089
4be73780
DV		 1090 if (!edp_have_panel_power(intel_dp))
1091 wait_panel_power_cycle(intel_dp);
99ea7127 1092
453c5420 1093 pp = ironlake_get_pp_control(intel_dp);
5d613501 1094 pp |= EDP_FORCE_VDD;
ebf33b18 1095
bf13e81b
JN		 1096 pp_stat_reg = _pp_stat_reg(intel_dp);
1097 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1098
1099 I915_WRITE(pp_ctrl_reg, pp);
1100 POSTING_READ(pp_ctrl_reg);
1101 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1102 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1103 /*
1104 * If the panel wasn't on, delay before accessing aux channel
1105 */
4be73780 1106 if (!edp_have_panel_power(intel_dp)) {
bd943159 1107 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1108 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1109 }
adddaaf4
JN		 1110
1111 return need_to_disable;
1112}
1113
b80d6c78 1114void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4
JN		 1115{
1116 if (is_edp(intel_dp)) {
1117 bool vdd = _edp_panel_vdd_on(intel_dp);
1118
1119 WARN(!vdd, "eDP VDD already requested on\n");
1120 }
5d613501
JB		 1121}
1122
4be73780 1123static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1124{
30add22d 1125 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1126 struct drm_i915_private *dev_priv = dev->dev_private;
1127 u32 pp;
453c5420 1128 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1129
a0e99e68
DV		 1130 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1131
4be73780 1132 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
4e6e1a54
ID		 1133 struct intel_digital_port *intel_dig_port =
1134 dp_to_dig_port(intel_dp);
1135 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1136 enum intel_display_power_domain power_domain;
1137
b0665d57
PZ		 1138 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1139
453c5420 1140 pp = ironlake_get_pp_control(intel_dp);
bd943159 1141 pp &= ~EDP_FORCE_VDD;
bd943159 1142
9f08ef59
PZ		 1143 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1144 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1145
1146 I915_WRITE(pp_ctrl_reg, pp);
1147 POSTING_READ(pp_ctrl_reg);
99ea7127 1148
453c5420
JB		 1149 /* Make sure sequencer is idle before allowing subsequent activity */
1150 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1151 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1152
1153 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1154 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1155
4e6e1a54
ID		 1156 power_domain = intel_display_port_power_domain(intel_encoder);
1157 intel_display_power_put(dev_priv, power_domain);
bd943159
KP		 1158 }
1159}
5d613501 1160
4be73780 1161static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1162{
1163 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1164 struct intel_dp, panel_vdd_work);
30add22d 1165 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1166
627f7675 1167 mutex_lock(&dev->mode_config.mutex);
4be73780 1168 edp_panel_vdd_off_sync(intel_dp);
627f7675 1169 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1170}
1171
4be73780 1172static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1173{
97af61f5
KP		 1174 if (!is_edp(intel_dp))
1175 return;
5d613501 1176
bd943159 1177 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1178
bd943159
KP		 1179 intel_dp->want_panel_vdd = false;
1180
1181 if (sync) {
4be73780 1182 edp_panel_vdd_off_sync(intel_dp);
bd943159
KP		 1183 } else {
1184 /*
1185 * Queue the timer to fire a long
1186 * time from now (relative to the power down delay)
1187 * to keep the panel power up across a sequence of operations
1188 */
1189 schedule_delayed_work(&intel_dp->panel_vdd_work,
1190 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1191 }
5d613501
JB		 1192}
1193
4be73780 1194void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1195{
30add22d 1196 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1197 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1198 u32 pp;
453c5420 1199 u32 pp_ctrl_reg;
9934c132 1200
97af61f5 1201 if (!is_edp(intel_dp))
bd943159 1202 return;
99ea7127
KP		 1203
1204 DRM_DEBUG_KMS("Turn eDP power on\n");
1205
4be73780 1206 if (edp_have_panel_power(intel_dp)) {
99ea7127 1207 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1208 return;
99ea7127 1209 }
9934c132 1210
4be73780 1211 wait_panel_power_cycle(intel_dp);
37c6c9b0 1212
bf13e81b 1213 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1214 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1215 if (IS_GEN5(dev)) {
1216 /* ILK workaround: disable reset around power sequence */
1217 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1218 I915_WRITE(pp_ctrl_reg, pp);
1219 POSTING_READ(pp_ctrl_reg);
05ce1a49 1220 }
37c6c9b0 1221
1c0ae80a 1222 pp |= POWER_TARGET_ON;
99ea7127
KP		 1223 if (!IS_GEN5(dev))
1224 pp |= PANEL_POWER_RESET;
1225
453c5420
JB		 1226 I915_WRITE(pp_ctrl_reg, pp);
1227 POSTING_READ(pp_ctrl_reg);
9934c132 1228
4be73780 1229 wait_panel_on(intel_dp);
dce56b3c 1230 intel_dp->last_power_on = jiffies;
9934c132 1231
05ce1a49
KP		 1232 if (IS_GEN5(dev)) {
1233 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1234 I915_WRITE(pp_ctrl_reg, pp);
1235 POSTING_READ(pp_ctrl_reg);
05ce1a49 1236 }
9934c132
JB		 1237}
1238
4be73780 1239void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1240{
4e6e1a54
ID		 1241 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1242 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1243 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1244 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1245 enum intel_display_power_domain power_domain;
99ea7127 1246 u32 pp;
453c5420 1247 u32 pp_ctrl_reg;
9934c132 1248
97af61f5
KP		 1249 if (!is_edp(intel_dp))
1250 return;
37c6c9b0 1251
99ea7127 1252 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1253
4be73780 1254 edp_wait_backlight_off(intel_dp);
dce56b3c 1255
24f3e092
JN		 1256 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1257
453c5420 1258 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1259 /* We need to switch off panel power _and_ force vdd, for otherwise some
1260 * panels get very unhappy and cease to work. */
b3064154
PJ		 1261 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1262 EDP_BLC_ENABLE);
453c5420 1263
bf13e81b 1264 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1265
849e39f5
PZ		 1266 intel_dp->want_panel_vdd = false;
1267
453c5420
JB		 1268 I915_WRITE(pp_ctrl_reg, pp);
1269 POSTING_READ(pp_ctrl_reg);
9934c132 1270
dce56b3c 1271 intel_dp->last_power_cycle = jiffies;
4be73780 1272 wait_panel_off(intel_dp);
849e39f5
PZ		 1273
1274 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1275 power_domain = intel_display_port_power_domain(intel_encoder);
1276 intel_display_power_put(dev_priv, power_domain);
9934c132
JB		 1277}
1278
4be73780 1279void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1280{
da63a9f2
PZ		 1281 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1282 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1283 struct drm_i915_private *dev_priv = dev->dev_private;
1284 u32 pp;
453c5420 1285 u32 pp_ctrl_reg;
32f9d658 1286
f01eca2e
KP		 1287 if (!is_edp(intel_dp))
1288 return;
1289
28c97730 1290 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1291 /*
1292 * If we enable the backlight right away following a panel power
1293 * on, we may see slight flicker as the panel syncs with the eDP
1294 * link. So delay a bit to make sure the image is solid before
1295 * allowing it to appear.
1296 */
4be73780 1297 wait_backlight_on(intel_dp);
453c5420 1298 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1299 pp |= EDP_BLC_ENABLE;
453c5420 1300
bf13e81b 1301 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1302
1303 I915_WRITE(pp_ctrl_reg, pp);
1304 POSTING_READ(pp_ctrl_reg);
035aa3de 1305
752aa88a 1306 intel_panel_enable_backlight(intel_dp->attached_connector);
32f9d658
ZW		 1307}
1308
4be73780 1309void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1310{
30add22d 1311 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1312 struct drm_i915_private *dev_priv = dev->dev_private;
1313 u32 pp;
453c5420 1314 u32 pp_ctrl_reg;
32f9d658 1315
f01eca2e
KP		 1316 if (!is_edp(intel_dp))
1317 return;
1318
752aa88a 1319 intel_panel_disable_backlight(intel_dp->attached_connector);
035aa3de 1320
28c97730 1321 DRM_DEBUG_KMS("\n");
453c5420 1322 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1323 pp &= ~EDP_BLC_ENABLE;
453c5420 1324
bf13e81b 1325 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1326
1327 I915_WRITE(pp_ctrl_reg, pp);
1328 POSTING_READ(pp_ctrl_reg);
dce56b3c 1329 intel_dp->last_backlight_off = jiffies;
32f9d658 1330}
a4fc5ed6 1331
2bd2ad64 1332static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1333{
da63a9f2
PZ		 1334 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1335 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1336 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1337 struct drm_i915_private *dev_priv = dev->dev_private;
1338 u32 dpa_ctl;
1339
2bd2ad64
DV		 1340 assert_pipe_disabled(dev_priv,
1341 to_intel_crtc(crtc)->pipe);
1342
d240f20f
JB		 1343 DRM_DEBUG_KMS("\n");
1344 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1345 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1346 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1347
1348 /* We don't adjust intel_dp->DP while tearing down the link, to
1349 * facilitate link retraining (e.g. after hotplug). Hence clear all
1350 * enable bits here to ensure that we don't enable too much. */
1351 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1352 intel_dp->DP |= DP_PLL_ENABLE;
1353 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1354 POSTING_READ(DP_A);
1355 udelay(200);
d240f20f
JB		 1356}
1357
2bd2ad64 1358static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1359{
da63a9f2
PZ		 1360 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1361 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1362 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1363 struct drm_i915_private *dev_priv = dev->dev_private;
1364 u32 dpa_ctl;
1365
2bd2ad64
DV		 1366 assert_pipe_disabled(dev_priv,
1367 to_intel_crtc(crtc)->pipe);
1368
d240f20f 1369 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1370 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1371 "dp pll off, should be on\n");
1372 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1373
1374 /* We can't rely on the value tracked for the DP register in
1375 * intel_dp->DP because link_down must not change that (otherwise link
1376 * re-training will fail. */
298b0b39 1377 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1378 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1379 POSTING_READ(DP_A);
d240f20f
JB		 1380 udelay(200);
1381}
1382
c7ad3810 1383/* If the sink supports it, try to set the power state appropriately */
c19b0669 1384void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1385{
1386 int ret, i;
1387
1388 /* Should have a valid DPCD by this point */
1389 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1390 return;
1391
1392 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1393 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1394 DP_SET_POWER_D3);
c7ad3810
JB		 1395 if (ret != 1)
1396 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1397 } else {
1398 /*
1399 * When turning on, we need to retry for 1ms to give the sink
1400 * time to wake up.
1401 */
1402 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1403 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1404 DP_SET_POWER_D0);
c7ad3810
JB		 1405 if (ret == 1)
1406 break;
1407 msleep(1);
1408 }
1409 }
1410}
1411
19d8fe15
DV		 1412static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1413 enum pipe *pipe)
d240f20f 1414{
19d8fe15 1415 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1416 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1417 struct drm_device *dev = encoder->base.dev;
1418 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1419 enum intel_display_power_domain power_domain;
1420 u32 tmp;
1421
1422 power_domain = intel_display_port_power_domain(encoder);
1423 if (!intel_display_power_enabled(dev_priv, power_domain))
1424 return false;
1425
1426 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1427
1428 if (!(tmp & DP_PORT_EN))
1429 return false;
1430
bc7d38a4 1431 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1432 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1433 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1434 *pipe = PORT_TO_PIPE(tmp);
1435 } else {
1436 u32 trans_sel;
1437 u32 trans_dp;
1438 int i;
1439
1440 switch (intel_dp->output_reg) {
1441 case PCH_DP_B:
1442 trans_sel = TRANS_DP_PORT_SEL_B;
1443 break;
1444 case PCH_DP_C:
1445 trans_sel = TRANS_DP_PORT_SEL_C;
1446 break;
1447 case PCH_DP_D:
1448 trans_sel = TRANS_DP_PORT_SEL_D;
1449 break;
1450 default:
1451 return true;
1452 }
1453
1454 for_each_pipe(i) {
1455 trans_dp = I915_READ(TRANS_DP_CTL(i));
1456 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1457 *pipe = i;
1458 return true;
1459 }
1460 }
19d8fe15 1461
4a0833ec
DV		 1462 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1463 intel_dp->output_reg);
1464 }
d240f20f 1465
19d8fe15
DV		 1466 return true;
1467}
d240f20f 1468
045ac3b5
JB		 1469static void intel_dp_get_config(struct intel_encoder *encoder,
1470 struct intel_crtc_config *pipe_config)
1471{
1472 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1473 u32 tmp, flags = 0;
63000ef6
XZ		 1474 struct drm_device *dev = encoder->base.dev;
1475 struct drm_i915_private *dev_priv = dev->dev_private;
1476 enum port port = dp_to_dig_port(intel_dp)->port;
1477 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1478 int dotclock;
045ac3b5 1479
63000ef6
XZ		 1480 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1481 tmp = I915_READ(intel_dp->output_reg);
1482 if (tmp & DP_SYNC_HS_HIGH)
1483 flags |= DRM_MODE_FLAG_PHSYNC;
1484 else
1485 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1486
63000ef6
XZ		 1487 if (tmp & DP_SYNC_VS_HIGH)
1488 flags |= DRM_MODE_FLAG_PVSYNC;
1489 else
1490 flags |= DRM_MODE_FLAG_NVSYNC;
1491 } else {
1492 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1493 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1494 flags |= DRM_MODE_FLAG_PHSYNC;
1495 else
1496 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1497
63000ef6
XZ		 1498 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1499 flags |= DRM_MODE_FLAG_PVSYNC;
1500 else
1501 flags |= DRM_MODE_FLAG_NVSYNC;
1502 }
045ac3b5
JB		 1503
1504 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1505
eb14cb74
VS		 1506 pipe_config->has_dp_encoder = true;
1507
1508 intel_dp_get_m_n(crtc, pipe_config);
1509
18442d08 1510 if (port == PORT_A) {
f1f644dc
JB		 1511 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1512 pipe_config->port_clock = 162000;
1513 else
1514 pipe_config->port_clock = 270000;
1515 }
18442d08
VS		 1516
1517 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1518 &pipe_config->dp_m_n);
1519
1520 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1521 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1522
241bfc38 1523 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1524
c6cd2ee2
JN		 1525 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1526 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1527 /*
1528 * This is a big fat ugly hack.
1529 *
1530 * Some machines in UEFI boot mode provide us a VBT that has 18
1531 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1532 * unknown we fail to light up. Yet the same BIOS boots up with
1533 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1534 * max, not what it tells us to use.
1535 *
1536 * Note: This will still be broken if the eDP panel is not lit
1537 * up by the BIOS, and thus we can't get the mode at module
1538 * load.
1539 */
1540 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1541 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1542 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1543 }
045ac3b5
JB		 1544}
1545
a031d709 1546static bool is_edp_psr(struct drm_device *dev)
2293bb5c 1547{
a031d709
RV		 1548 struct drm_i915_private *dev_priv = dev->dev_private;
1549
1550 return dev_priv->psr.sink_support;
2293bb5c
SK		 1551}
1552
2b28bb1b
RV		 1553static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1554{
1555 struct drm_i915_private *dev_priv = dev->dev_private;
1556
18b5992c 1557 if (!HAS_PSR(dev))
2b28bb1b
RV		 1558 return false;
1559
18b5992c 1560 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1561}
1562
1563static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1564 struct edp_vsc_psr *vsc_psr)
1565{
1566 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1567 struct drm_device *dev = dig_port->base.base.dev;
1568 struct drm_i915_private *dev_priv = dev->dev_private;
1569 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1570 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1571 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1572 uint32_t *data = (uint32_t *) vsc_psr;
1573 unsigned int i;
1574
1575 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1576 the video DIP being updated before program video DIP data buffer
1577 registers for DIP being updated. */
1578 I915_WRITE(ctl_reg, 0);
1579 POSTING_READ(ctl_reg);
1580
1581 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1582 if (i < sizeof(struct edp_vsc_psr))
1583 I915_WRITE(data_reg + i, *data++);
1584 else
1585 I915_WRITE(data_reg + i, 0);
1586 }
1587
1588 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1589 POSTING_READ(ctl_reg);
1590}
1591
1592static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1593{
1594 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1595 struct drm_i915_private *dev_priv = dev->dev_private;
1596 struct edp_vsc_psr psr_vsc;
1597
1598 if (intel_dp->psr_setup_done)
1599 return;
1600
1601 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1602 memset(&psr_vsc, 0, sizeof(psr_vsc));
1603 psr_vsc.sdp_header.HB0 = 0;
1604 psr_vsc.sdp_header.HB1 = 0x7;
1605 psr_vsc.sdp_header.HB2 = 0x2;
1606 psr_vsc.sdp_header.HB3 = 0x8;
1607 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1608
1609 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1610 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1611 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1612
1613 intel_dp->psr_setup_done = true;
1614}
1615
1616static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1617{
1618 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1619 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1620 uint32_t aux_clock_divider;
2b28bb1b
RV		 1621 int precharge = 0x3;
1622 int msg_size = 5; /* Header(4) + Message(1) */
1623
ec5b01dd
DL		 1624 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1625
2b28bb1b
RV		 1626 /* Enable PSR in sink */
1627 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
9d1a1031
JN		 1628 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1629 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1630 else
9d1a1031
JN		 1631 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1632 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1633
1634 /* Setup AUX registers */
18b5992c
BW		 1635 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1636 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1637 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1638 DP_AUX_CH_CTL_TIME_OUT_400us |
1639 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1640 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1641 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1642}
1643
1644static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1645{
1646 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1647 struct drm_i915_private *dev_priv = dev->dev_private;
1648 uint32_t max_sleep_time = 0x1f;
1649 uint32_t idle_frames = 1;
1650 uint32_t val = 0x0;
ed8546ac 1651 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2b28bb1b
RV		 1652
1653 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1654 val |= EDP_PSR_LINK_STANDBY;
1655 val |= EDP_PSR_TP2_TP3_TIME_0us;
1656 val |= EDP_PSR_TP1_TIME_0us;
1657 val |= EDP_PSR_SKIP_AUX_EXIT;
1658 } else
1659 val |= EDP_PSR_LINK_DISABLE;
1660
18b5992c 1661 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1662 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1663 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1664 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1665 EDP_PSR_ENABLE);
1666}
1667
3f51e471
RV		 1668static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1669{
1670 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1671 struct drm_device *dev = dig_port->base.base.dev;
1672 struct drm_i915_private *dev_priv = dev->dev_private;
1673 struct drm_crtc *crtc = dig_port->base.base.crtc;
1674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
f4510a27 1675 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
3f51e471
RV		 1676 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1677
a031d709
RV		 1678 dev_priv->psr.source_ok = false;
1679
18b5992c 1680 if (!HAS_PSR(dev)) {
3f51e471 1681 DRM_DEBUG_KMS("PSR not supported on this platform\n");
3f51e471
RV		 1682 return false;
1683 }
1684
1685 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1686 (dig_port->port != PORT_A)) {
1687 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1688 return false;
1689 }
1690
d330a953 1691 if (!i915.enable_psr) {
105b7c11 1692 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1693 return false;
1694 }
1695
cd234b0b
CW		 1696 crtc = dig_port->base.base.crtc;
1697 if (crtc == NULL) {
1698 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1699 return false;
1700 }
1701
1702 intel_crtc = to_intel_crtc(crtc);
20ddf665 1703 if (!intel_crtc_active(crtc)) {
3f51e471 1704 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1705 return false;
1706 }
1707
f4510a27 1708 obj = to_intel_framebuffer(crtc->primary->fb)->obj;
3f51e471
RV		 1709 if (obj->tiling_mode != I915_TILING_X ||
1710 obj->fence_reg == I915_FENCE_REG_NONE) {
1711 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1712 return false;
1713 }
1714
1715 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1716 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1717 return false;
1718 }
1719
1720 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1721 S3D_ENABLE) {
1722 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1723 return false;
1724 }
1725
ca73b4f0 1726 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1727 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1728 return false;
1729 }
1730
a031d709 1731 dev_priv->psr.source_ok = true;
3f51e471
RV		 1732 return true;
1733}
1734
3d739d92 1735static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1736{
1737 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1738
3f51e471
RV		 1739 if (!intel_edp_psr_match_conditions(intel_dp) ||
1740 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1741 return;
1742
1743 /* Setup PSR once */
1744 intel_edp_psr_setup(intel_dp);
1745
1746 /* Enable PSR on the panel */
1747 intel_edp_psr_enable_sink(intel_dp);
1748
1749 /* Enable PSR on the host */
1750 intel_edp_psr_enable_source(intel_dp);
1751}
1752
3d739d92
RV		 1753void intel_edp_psr_enable(struct intel_dp *intel_dp)
1754{
1755 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1756
1757 if (intel_edp_psr_match_conditions(intel_dp) &&
1758 !intel_edp_is_psr_enabled(dev))
1759 intel_edp_psr_do_enable(intel_dp);
1760}
1761
2b28bb1b
RV		 1762void intel_edp_psr_disable(struct intel_dp *intel_dp)
1763{
1764 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1765 struct drm_i915_private *dev_priv = dev->dev_private;
1766
1767 if (!intel_edp_is_psr_enabled(dev))
1768 return;
1769
18b5992c
BW		 1770 I915_WRITE(EDP_PSR_CTL(dev),
1771 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1772
1773 /* Wait till PSR is idle */
18b5992c 1774 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1775 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1776 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1777}
1778
3d739d92
RV		 1779void intel_edp_psr_update(struct drm_device *dev)
1780{
1781 struct intel_encoder *encoder;
1782 struct intel_dp *intel_dp = NULL;
1783
1784 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1785 if (encoder->type == INTEL_OUTPUT_EDP) {
1786 intel_dp = enc_to_intel_dp(&encoder->base);
1787
a031d709 1788 if (!is_edp_psr(dev))
3d739d92
RV		 1789 return;
1790
1791 if (!intel_edp_psr_match_conditions(intel_dp))
1792 intel_edp_psr_disable(intel_dp);
1793 else
1794 if (!intel_edp_is_psr_enabled(dev))
1795 intel_edp_psr_do_enable(intel_dp);
1796 }
1797}
1798
e8cb4558 1799static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1800{
e8cb4558 1801 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1802 enum port port = dp_to_dig_port(intel_dp)->port;
1803 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1804
1805 /* Make sure the panel is off before trying to change the mode. But also
1806 * ensure that we have vdd while we switch off the panel. */
24f3e092 1807 intel_edp_panel_vdd_on(intel_dp);
4be73780 1808 intel_edp_backlight_off(intel_dp);
fdbc3b1f 1809 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 1810 intel_edp_panel_off(intel_dp);
3739850b
DV		 1811
1812 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1813 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1814 intel_dp_link_down(intel_dp);
d240f20f
JB		 1815}
1816
49277c31 1817static void g4x_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1818{
2bd2ad64 1819 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1820 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 1821
49277c31
VS		 1822 if (port != PORT_A)
1823 return;
1824
1825 intel_dp_link_down(intel_dp);
1826 ironlake_edp_pll_off(intel_dp);
1827}
1828
1829static void vlv_post_disable_dp(struct intel_encoder *encoder)
1830{
1831 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1832
1833 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 1834}
1835
e8cb4558 1836static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1837{
e8cb4558
DV		 1838 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1839 struct drm_device *dev = encoder->base.dev;
1840 struct drm_i915_private *dev_priv = dev->dev_private;
1841 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1842
0c33d8d7
DV		 1843 if (WARN_ON(dp_reg & DP_PORT_EN))
1844 return;
5d613501 1845
24f3e092 1846 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 1847 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1848 intel_dp_start_link_train(intel_dp);
4be73780
DV		 1849 intel_edp_panel_on(intel_dp);
1850 edp_panel_vdd_off(intel_dp, true);
33a34e4e 1851 intel_dp_complete_link_train(intel_dp);
3ab9c637 1852 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1853}
89b667f8 1854
ecff4f3b
JN		 1855static void g4x_enable_dp(struct intel_encoder *encoder)
1856{
828f5c6e
JN		 1857 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1858
ecff4f3b 1859 intel_enable_dp(encoder);
4be73780 1860 intel_edp_backlight_on(intel_dp);
ab1f90f9 1861}
89b667f8 1862
ab1f90f9
JN		 1863static void vlv_enable_dp(struct intel_encoder *encoder)
1864{
828f5c6e
JN		 1865 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1866
4be73780 1867 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 1868}
1869
ecff4f3b 1870static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1871{
1872 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1873 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1874
1875 if (dport->port == PORT_A)
1876 ironlake_edp_pll_on(intel_dp);
1877}
1878
1879static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1880{
2bd2ad64 1881 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1882 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1883 struct drm_device *dev = encoder->base.dev;
89b667f8 1884 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 1885 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 1886 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 1887 int pipe = intel_crtc->pipe;
bf13e81b 1888 struct edp_power_seq power_seq;
ab1f90f9 1889 u32 val;
a4fc5ed6 1890
ab1f90f9 1891 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1892
ab3c759a 1893 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 1894 val = 0;
1895 if (pipe)
1896 val |= (1<<21);
1897 else
1898 val &= ~(1<<21);
1899 val |= 0x001000c4;
ab3c759a
CML		 1900 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1901 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1902 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 1903
ab1f90f9
JN		 1904 mutex_unlock(&dev_priv->dpio_lock);
1905
2cac613b
ID		 1906 if (is_edp(intel_dp)) {
1907 /* init power sequencer on this pipe and port */
1908 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1909 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1910 &power_seq);
1911 }
bf13e81b 1912
ab1f90f9
JN		 1913 intel_enable_dp(encoder);
1914
e4607fcf 1915 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 1916}
1917
ecff4f3b 1918static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1919{
1920 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1921 struct drm_device *dev = encoder->base.dev;
1922 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1923 struct intel_crtc *intel_crtc =
1924 to_intel_crtc(encoder->base.crtc);
e4607fcf 1925 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 1926 int pipe = intel_crtc->pipe;
89b667f8 1927
89b667f8 1928 /* Program Tx lane resets to default */
0980a60f 1929 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 1930 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 1931 DPIO_PCS_TX_LANE2_RESET |
1932 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 1933 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 1934 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1935 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1936 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1937 DPIO_PCS_CLK_SOFT_RESET);
1938
1939 /* Fix up inter-pair skew failure */
ab3c759a
CML		 1940 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1941 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1942 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 1943 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 1944}
1945
1946/*
df0c237d
JB		 1947 * Native read with retry for link status and receiver capability reads for
1948 * cases where the sink may still be asleep.
9d1a1031
JN		 1949 *
1950 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
1951 * supposed to retry 3 times per the spec.
a4fc5ed6 1952 */
9d1a1031
JN		 1953static ssize_t
1954intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
1955 void *buffer, size_t size)
a4fc5ed6 1956{
9d1a1031
JN		 1957 ssize_t ret;
1958 int i;
61da5fab 1959
61da5fab 1960 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1961 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
1962 if (ret == size)
1963 return ret;
61da5fab
JB		 1964 msleep(1);
1965 }
a4fc5ed6 1966
9d1a1031 1967 return ret;
a4fc5ed6
KP		 1968}
1969
1970/*
1971 * Fetch AUX CH registers 0x202 - 0x207 which contain
1972 * link status information
1973 */
1974static bool
93f62dad 1975intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1976{
9d1a1031
JN		 1977 return intel_dp_dpcd_read_wake(&intel_dp->aux,
1978 DP_LANE0_1_STATUS,
1979 link_status,
1980 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 1981}
1982
a4fc5ed6
KP		 1983/*
1984 * These are source-specific values; current Intel hardware supports
1985 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1986 */
a4fc5ed6
KP		 1987
1988static uint8_t
1a2eb460 1989intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1990{
30add22d 1991 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1992 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1993
8f93f4f1 1994 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
e2fa6fba 1995 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 1996 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 1997 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 1998 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 1999 return DP_TRAIN_VOLTAGE_SWING_1200;
2000 else
2001 return DP_TRAIN_VOLTAGE_SWING_800;
2002}
2003
2004static uint8_t
2005intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2006{
30add22d 2007 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2008 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2009
8f93f4f1
PZ		 2010 if (IS_BROADWELL(dev)) {
2011 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2012 case DP_TRAIN_VOLTAGE_SWING_400:
2013 case DP_TRAIN_VOLTAGE_SWING_600:
2014 return DP_TRAIN_PRE_EMPHASIS_6;
2015 case DP_TRAIN_VOLTAGE_SWING_800:
2016 return DP_TRAIN_PRE_EMPHASIS_3_5;
2017 case DP_TRAIN_VOLTAGE_SWING_1200:
2018 default:
2019 return DP_TRAIN_PRE_EMPHASIS_0;
2020 }
2021 } else if (IS_HASWELL(dev)) {
d6c0d722
PZ		 2022 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2023 case DP_TRAIN_VOLTAGE_SWING_400:
2024 return DP_TRAIN_PRE_EMPHASIS_9_5;
2025 case DP_TRAIN_VOLTAGE_SWING_600:
2026 return DP_TRAIN_PRE_EMPHASIS_6;
2027 case DP_TRAIN_VOLTAGE_SWING_800:
2028 return DP_TRAIN_PRE_EMPHASIS_3_5;
2029 case DP_TRAIN_VOLTAGE_SWING_1200:
2030 default:
2031 return DP_TRAIN_PRE_EMPHASIS_0;
2032 }
e2fa6fba
P		 2033 } else if (IS_VALLEYVIEW(dev)) {
2034 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2035 case DP_TRAIN_VOLTAGE_SWING_400:
2036 return DP_TRAIN_PRE_EMPHASIS_9_5;
2037 case DP_TRAIN_VOLTAGE_SWING_600:
2038 return DP_TRAIN_PRE_EMPHASIS_6;
2039 case DP_TRAIN_VOLTAGE_SWING_800:
2040 return DP_TRAIN_PRE_EMPHASIS_3_5;
2041 case DP_TRAIN_VOLTAGE_SWING_1200:
2042 default:
2043 return DP_TRAIN_PRE_EMPHASIS_0;
2044 }
bc7d38a4 2045 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2046 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2047 case DP_TRAIN_VOLTAGE_SWING_400:
2048 return DP_TRAIN_PRE_EMPHASIS_6;
2049 case DP_TRAIN_VOLTAGE_SWING_600:
2050 case DP_TRAIN_VOLTAGE_SWING_800:
2051 return DP_TRAIN_PRE_EMPHASIS_3_5;
2052 default:
2053 return DP_TRAIN_PRE_EMPHASIS_0;
2054 }
2055 } else {
2056 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2057 case DP_TRAIN_VOLTAGE_SWING_400:
2058 return DP_TRAIN_PRE_EMPHASIS_6;
2059 case DP_TRAIN_VOLTAGE_SWING_600:
2060 return DP_TRAIN_PRE_EMPHASIS_6;
2061 case DP_TRAIN_VOLTAGE_SWING_800:
2062 return DP_TRAIN_PRE_EMPHASIS_3_5;
2063 case DP_TRAIN_VOLTAGE_SWING_1200:
2064 default:
2065 return DP_TRAIN_PRE_EMPHASIS_0;
2066 }
a4fc5ed6
KP		 2067 }
2068}
2069
e2fa6fba
P		 2070static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2071{
2072 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2073 struct drm_i915_private *dev_priv = dev->dev_private;
2074 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2075 struct intel_crtc *intel_crtc =
2076 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2077 unsigned long demph_reg_value, preemph_reg_value,
2078 uniqtranscale_reg_value;
2079 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2080 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2081 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2082
2083 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2084 case DP_TRAIN_PRE_EMPHASIS_0:
2085 preemph_reg_value = 0x0004000;
2086 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2087 case DP_TRAIN_VOLTAGE_SWING_400:
2088 demph_reg_value = 0x2B405555;
2089 uniqtranscale_reg_value = 0x552AB83A;
2090 break;
2091 case DP_TRAIN_VOLTAGE_SWING_600:
2092 demph_reg_value = 0x2B404040;
2093 uniqtranscale_reg_value = 0x5548B83A;
2094 break;
2095 case DP_TRAIN_VOLTAGE_SWING_800:
2096 demph_reg_value = 0x2B245555;
2097 uniqtranscale_reg_value = 0x5560B83A;
2098 break;
2099 case DP_TRAIN_VOLTAGE_SWING_1200:
2100 demph_reg_value = 0x2B405555;
2101 uniqtranscale_reg_value = 0x5598DA3A;
2102 break;
2103 default:
2104 return 0;
2105 }
2106 break;
2107 case DP_TRAIN_PRE_EMPHASIS_3_5:
2108 preemph_reg_value = 0x0002000;
2109 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2110 case DP_TRAIN_VOLTAGE_SWING_400:
2111 demph_reg_value = 0x2B404040;
2112 uniqtranscale_reg_value = 0x5552B83A;
2113 break;
2114 case DP_TRAIN_VOLTAGE_SWING_600:
2115 demph_reg_value = 0x2B404848;
2116 uniqtranscale_reg_value = 0x5580B83A;
2117 break;
2118 case DP_TRAIN_VOLTAGE_SWING_800:
2119 demph_reg_value = 0x2B404040;
2120 uniqtranscale_reg_value = 0x55ADDA3A;
2121 break;
2122 default:
2123 return 0;
2124 }
2125 break;
2126 case DP_TRAIN_PRE_EMPHASIS_6:
2127 preemph_reg_value = 0x0000000;
2128 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2129 case DP_TRAIN_VOLTAGE_SWING_400:
2130 demph_reg_value = 0x2B305555;
2131 uniqtranscale_reg_value = 0x5570B83A;
2132 break;
2133 case DP_TRAIN_VOLTAGE_SWING_600:
2134 demph_reg_value = 0x2B2B4040;
2135 uniqtranscale_reg_value = 0x55ADDA3A;
2136 break;
2137 default:
2138 return 0;
2139 }
2140 break;
2141 case DP_TRAIN_PRE_EMPHASIS_9_5:
2142 preemph_reg_value = 0x0006000;
2143 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2144 case DP_TRAIN_VOLTAGE_SWING_400:
2145 demph_reg_value = 0x1B405555;
2146 uniqtranscale_reg_value = 0x55ADDA3A;
2147 break;
2148 default:
2149 return 0;
2150 }
2151 break;
2152 default:
2153 return 0;
2154 }
2155
0980a60f 2156 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2157 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2158 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2159 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2160 uniqtranscale_reg_value);
ab3c759a
CML		 2161 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2162 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2163 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2164 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2165 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2166
2167 return 0;
2168}
2169
a4fc5ed6 2170static void
0301b3ac
JN		 2171intel_get_adjust_train(struct intel_dp *intel_dp,
2172 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2173{
2174 uint8_t v = 0;
2175 uint8_t p = 0;
2176 int lane;
1a2eb460
KP		 2177 uint8_t voltage_max;
2178 uint8_t preemph_max;
a4fc5ed6 2179
33a34e4e 2180 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2181 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2182 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2183
2184 if (this_v > v)
2185 v = this_v;
2186 if (this_p > p)
2187 p = this_p;
2188 }
2189
1a2eb460 2190 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2191 if (v >= voltage_max)
2192 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2193
1a2eb460
KP		 2194 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2195 if (p >= preemph_max)
2196 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2197
2198 for (lane = 0; lane < 4; lane++)
33a34e4e 2199 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2200}
2201
2202static uint32_t
f0a3424e 2203intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2204{
3cf2efb1 2205 uint32_t signal_levels = 0;
a4fc5ed6 2206
3cf2efb1 2207 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2208 case DP_TRAIN_VOLTAGE_SWING_400:
2209 default:
2210 signal_levels |= DP_VOLTAGE_0_4;
2211 break;
2212 case DP_TRAIN_VOLTAGE_SWING_600:
2213 signal_levels |= DP_VOLTAGE_0_6;
2214 break;
2215 case DP_TRAIN_VOLTAGE_SWING_800:
2216 signal_levels |= DP_VOLTAGE_0_8;
2217 break;
2218 case DP_TRAIN_VOLTAGE_SWING_1200:
2219 signal_levels |= DP_VOLTAGE_1_2;
2220 break;
2221 }
3cf2efb1 2222 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2223 case DP_TRAIN_PRE_EMPHASIS_0:
2224 default:
2225 signal_levels |= DP_PRE_EMPHASIS_0;
2226 break;
2227 case DP_TRAIN_PRE_EMPHASIS_3_5:
2228 signal_levels |= DP_PRE_EMPHASIS_3_5;
2229 break;
2230 case DP_TRAIN_PRE_EMPHASIS_6:
2231 signal_levels |= DP_PRE_EMPHASIS_6;
2232 break;
2233 case DP_TRAIN_PRE_EMPHASIS_9_5:
2234 signal_levels |= DP_PRE_EMPHASIS_9_5;
2235 break;
2236 }
2237 return signal_levels;
2238}
2239
e3421a18
ZW		 2240/* Gen6's DP voltage swing and pre-emphasis control */
2241static uint32_t
2242intel_gen6_edp_signal_levels(uint8_t train_set)
2243{
3c5a62b5
YL		 2244 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2245 DP_TRAIN_PRE_EMPHASIS_MASK);
2246 switch (signal_levels) {
e3421a18 2247 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2248 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2249 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2250 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2251 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2252 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2253 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2254 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2255 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2256 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2257 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2258 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2259 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2260 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2261 default:
3c5a62b5
YL		 2262 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2263 "0x%x\n", signal_levels);
2264 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2265 }
2266}
2267
1a2eb460
KP		 2268/* Gen7's DP voltage swing and pre-emphasis control */
2269static uint32_t
2270intel_gen7_edp_signal_levels(uint8_t train_set)
2271{
2272 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2273 DP_TRAIN_PRE_EMPHASIS_MASK);
2274 switch (signal_levels) {
2275 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2276 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2277 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2278 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2279 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2280 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2281
2282 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2283 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2284 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2285 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2286
2287 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2288 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2289 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2290 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2291
2292 default:
2293 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2294 "0x%x\n", signal_levels);
2295 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2296 }
2297}
2298
d6c0d722
PZ		 2299/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2300static uint32_t
f0a3424e 2301intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2302{
d6c0d722
PZ		 2303 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2304 DP_TRAIN_PRE_EMPHASIS_MASK);
2305 switch (signal_levels) {
2306 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2307 return DDI_BUF_EMP_400MV_0DB_HSW;
2308 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2309 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2310 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2311 return DDI_BUF_EMP_400MV_6DB_HSW;
2312 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2313 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2314
d6c0d722
PZ		 2315 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2316 return DDI_BUF_EMP_600MV_0DB_HSW;
2317 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2318 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2319 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2320 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2321
d6c0d722
PZ		 2322 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2323 return DDI_BUF_EMP_800MV_0DB_HSW;
2324 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2325 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2326 default:
2327 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2328 "0x%x\n", signal_levels);
2329 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2330 }
a4fc5ed6
KP		 2331}
2332
8f93f4f1
PZ		 2333static uint32_t
2334intel_bdw_signal_levels(uint8_t train_set)
2335{
2336 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2337 DP_TRAIN_PRE_EMPHASIS_MASK);
2338 switch (signal_levels) {
2339 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2340 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2341 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2342 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2343 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2344 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2345
2346 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2347 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2348 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2349 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2350 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2351 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2352
2353 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2354 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2355 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2356 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2357
2358 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2359 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2360
2361 default:
2362 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2363 "0x%x\n", signal_levels);
2364 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2365 }
2366}
2367
f0a3424e
PZ		 2368/* Properly updates "DP" with the correct signal levels. */
2369static void
2370intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2371{
2372 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2373 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2374 struct drm_device *dev = intel_dig_port->base.base.dev;
2375 uint32_t signal_levels, mask;
2376 uint8_t train_set = intel_dp->train_set[0];
2377
8f93f4f1
PZ		 2378 if (IS_BROADWELL(dev)) {
2379 signal_levels = intel_bdw_signal_levels(train_set);
2380 mask = DDI_BUF_EMP_MASK;
2381 } else if (IS_HASWELL(dev)) {
f0a3424e
PZ		 2382 signal_levels = intel_hsw_signal_levels(train_set);
2383 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2384 } else if (IS_VALLEYVIEW(dev)) {
2385 signal_levels = intel_vlv_signal_levels(intel_dp);
2386 mask = 0;
bc7d38a4 2387 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2388 signal_levels = intel_gen7_edp_signal_levels(train_set);
2389 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2390 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2391 signal_levels = intel_gen6_edp_signal_levels(train_set);
2392 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2393 } else {
2394 signal_levels = intel_gen4_signal_levels(train_set);
2395 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2396 }
2397
2398 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2399
2400 *DP = (*DP & ~mask) | signal_levels;
2401}
2402
a4fc5ed6 2403static bool
ea5b213a 2404intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2405 uint32_t *DP,
58e10eb9 2406 uint8_t dp_train_pat)
a4fc5ed6 2407{
174edf1f
PZ		 2408 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2409 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2410 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2411 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2412 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2413 int ret, len;
a4fc5ed6 2414
22b8bf17 2415 if (HAS_DDI(dev)) {
3ab9c637 2416 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2417
2418 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2419 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2420 else
2421 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2422
2423 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2424 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2425 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2426 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2427
2428 break;
2429 case DP_TRAINING_PATTERN_1:
2430 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2431 break;
2432 case DP_TRAINING_PATTERN_2:
2433 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2434 break;
2435 case DP_TRAINING_PATTERN_3:
2436 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2437 break;
2438 }
174edf1f 2439 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2440
bc7d38a4 2441 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2442 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2443
2444 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2445 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2446 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2447 break;
2448 case DP_TRAINING_PATTERN_1:
70aff66c 2449 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2450 break;
2451 case DP_TRAINING_PATTERN_2:
70aff66c 2452 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2453 break;
2454 case DP_TRAINING_PATTERN_3:
2455 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2456 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2457 break;
2458 }
2459
2460 } else {
70aff66c 2461 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2462
2463 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2464 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2465 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2466 break;
2467 case DP_TRAINING_PATTERN_1:
70aff66c 2468 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2469 break;
2470 case DP_TRAINING_PATTERN_2:
70aff66c 2471 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2472 break;
2473 case DP_TRAINING_PATTERN_3:
2474 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2475 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2476 break;
2477 }
2478 }
2479
70aff66c 2480 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2481 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2482
2cdfe6c8
JN		 2483 buf[0] = dp_train_pat;
2484 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2485 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2486 /* don't write DP_TRAINING_LANEx_SET on disable */
2487 len = 1;
2488 } else {
2489 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2490 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2491 len = intel_dp->lane_count + 1;
47ea7542 2492 }
a4fc5ed6 2493
9d1a1031
JN		 2494 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2495 buf, len);
2cdfe6c8
JN		 2496
2497 return ret == len;
a4fc5ed6
KP		 2498}
2499
70aff66c
JN		 2500static bool
2501intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2502 uint8_t dp_train_pat)
2503{
953d22e8 2504 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2505 intel_dp_set_signal_levels(intel_dp, DP);
2506 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2507}
2508
2509static bool
2510intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2511 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2512{
2513 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2514 struct drm_device *dev = intel_dig_port->base.base.dev;
2515 struct drm_i915_private *dev_priv = dev->dev_private;
2516 int ret;
2517
2518 intel_get_adjust_train(intel_dp, link_status);
2519 intel_dp_set_signal_levels(intel_dp, DP);
2520
2521 I915_WRITE(intel_dp->output_reg, *DP);
2522 POSTING_READ(intel_dp->output_reg);
2523
9d1a1031
JN		 2524 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2525 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 2526
2527 return ret == intel_dp->lane_count;
2528}
2529
3ab9c637
ID		 2530static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2531{
2532 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2533 struct drm_device *dev = intel_dig_port->base.base.dev;
2534 struct drm_i915_private *dev_priv = dev->dev_private;
2535 enum port port = intel_dig_port->port;
2536 uint32_t val;
2537
2538 if (!HAS_DDI(dev))
2539 return;
2540
2541 val = I915_READ(DP_TP_CTL(port));
2542 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2543 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2544 I915_WRITE(DP_TP_CTL(port), val);
2545
2546 /*
2547 * On PORT_A we can have only eDP in SST mode. There the only reason
2548 * we need to set idle transmission mode is to work around a HW issue
2549 * where we enable the pipe while not in idle link-training mode.
2550 * In this case there is requirement to wait for a minimum number of
2551 * idle patterns to be sent.
2552 */
2553 if (port == PORT_A)
2554 return;
2555
2556 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2557 1))
2558 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2559}
2560
33a34e4e 2561/* Enable corresponding port and start training pattern 1 */
c19b0669 2562void
33a34e4e 2563intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2564{
da63a9f2 2565 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2566 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2567 int i;
2568 uint8_t voltage;
cdb0e95b 2569 int voltage_tries, loop_tries;
ea5b213a 2570 uint32_t DP = intel_dp->DP;
6aba5b6c 2571 uint8_t link_config[2];
a4fc5ed6 2572
affa9354 2573 if (HAS_DDI(dev))
c19b0669
PZ		 2574 intel_ddi_prepare_link_retrain(encoder);
2575
3cf2efb1 2576 /* Write the link configuration data */
6aba5b6c
JN		 2577 link_config[0] = intel_dp->link_bw;
2578 link_config[1] = intel_dp->lane_count;
2579 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2580 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 2581 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 2582
2583 link_config[0] = 0;
2584 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 2585 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 2586
2587 DP |= DP_PORT_EN;
1a2eb460 2588
70aff66c
JN		 2589 /* clock recovery */
2590 if (!intel_dp_reset_link_train(intel_dp, &DP,
2591 DP_TRAINING_PATTERN_1 |
2592 DP_LINK_SCRAMBLING_DISABLE)) {
2593 DRM_ERROR("failed to enable link training\n");
2594 return;
2595 }
2596
a4fc5ed6 2597 voltage = 0xff;
cdb0e95b
KP		 2598 voltage_tries = 0;
2599 loop_tries = 0;
a4fc5ed6 2600 for (;;) {
70aff66c 2601 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 2602
a7c9655f 2603 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2604 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2605 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2606 break;
93f62dad 2607 }
a4fc5ed6 2608
01916270 2609 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2610 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2611 break;
2612 }
2613
2614 /* Check to see if we've tried the max voltage */
2615 for (i = 0; i < intel_dp->lane_count; i++)
2616 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2617 break;
3b4f819d 2618 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2619 ++loop_tries;
2620 if (loop_tries == 5) {
3def84b3 2621 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 2622 break;
2623 }
70aff66c
JN		 2624 intel_dp_reset_link_train(intel_dp, &DP,
2625 DP_TRAINING_PATTERN_1 |
2626 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 2627 voltage_tries = 0;
2628 continue;
2629 }
a4fc5ed6 2630
3cf2efb1 2631 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2632 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2633 ++voltage_tries;
b06fbda3 2634 if (voltage_tries == 5) {
3def84b3 2635 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 2636 break;
2637 }
2638 } else
2639 voltage_tries = 0;
2640 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2641
70aff66c
JN		 2642 /* Update training set as requested by target */
2643 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2644 DRM_ERROR("failed to update link training\n");
2645 break;
2646 }
a4fc5ed6
KP		 2647 }
2648
33a34e4e
JB		 2649 intel_dp->DP = DP;
2650}
2651
c19b0669 2652void
33a34e4e
JB		 2653intel_dp_complete_link_train(struct intel_dp *intel_dp)
2654{
33a34e4e 2655 bool channel_eq = false;
37f80975 2656 int tries, cr_tries;
33a34e4e 2657 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 2658 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2659
2660 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2661 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2662 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 2663
a4fc5ed6 2664 /* channel equalization */
70aff66c 2665 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2666 training_pattern |
70aff66c
JN		 2667 DP_LINK_SCRAMBLING_DISABLE)) {
2668 DRM_ERROR("failed to start channel equalization\n");
2669 return;
2670 }
2671
a4fc5ed6 2672 tries = 0;
37f80975 2673 cr_tries = 0;
a4fc5ed6
KP		 2674 channel_eq = false;
2675 for (;;) {
70aff66c 2676 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2677
37f80975
JB		 2678 if (cr_tries > 5) {
2679 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 2680 break;
2681 }
2682
a7c9655f 2683 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 2684 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2685 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2686 break;
70aff66c 2687 }
a4fc5ed6 2688
37f80975 2689 /* Make sure clock is still ok */
01916270 2690 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 2691 intel_dp_start_link_train(intel_dp);
70aff66c 2692 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2693 training_pattern |
70aff66c 2694 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2695 cr_tries++;
2696 continue;
2697 }
2698
1ffdff13 2699 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2700 channel_eq = true;
2701 break;
2702 }
a4fc5ed6 2703
37f80975
JB		 2704 /* Try 5 times, then try clock recovery if that fails */
2705 if (tries > 5) {
2706 intel_dp_link_down(intel_dp);
2707 intel_dp_start_link_train(intel_dp);
70aff66c 2708 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2709 training_pattern |
70aff66c 2710 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2711 tries = 0;
2712 cr_tries++;
2713 continue;
2714 }
a4fc5ed6 2715
70aff66c
JN		 2716 /* Update training set as requested by target */
2717 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2718 DRM_ERROR("failed to update link training\n");
2719 break;
2720 }
3cf2efb1 2721 ++tries;
869184a6 2722 }
3cf2efb1 2723
3ab9c637
ID		 2724 intel_dp_set_idle_link_train(intel_dp);
2725
2726 intel_dp->DP = DP;
2727
d6c0d722 2728 if (channel_eq)
07f42258 2729 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2730
3ab9c637
ID		 2731}
2732
2733void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2734{
70aff66c 2735 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 2736 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2737}
2738
2739static void
ea5b213a 2740intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2741{
da63a9f2 2742 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2743 enum port port = intel_dig_port->port;
da63a9f2 2744 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2745 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2746 struct intel_crtc *intel_crtc =
2747 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2748 uint32_t DP = intel_dp->DP;
a4fc5ed6 2749
c19b0669
PZ		 2750 /*
2751 * DDI code has a strict mode set sequence and we should try to respect
2752 * it, otherwise we might hang the machine in many different ways. So we
2753 * really should be disabling the port only on a complete crtc_disable
2754 * sequence. This function is just called under two conditions on DDI
2755 * code:
2756 * - Link train failed while doing crtc_enable, and on this case we
2757 * really should respect the mode set sequence and wait for a
2758 * crtc_disable.
2759 * - Someone turned the monitor off and intel_dp_check_link_status
2760 * called us. We don't need to disable the whole port on this case, so
2761 * when someone turns the monitor on again,
2762 * intel_ddi_prepare_link_retrain will take care of redoing the link
2763 * train.
2764 */
affa9354 2765 if (HAS_DDI(dev))
c19b0669
PZ		 2766 return;
2767
0c33d8d7 2768 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2769 return;
2770
28c97730 2771 DRM_DEBUG_KMS("\n");
32f9d658 2772
bc7d38a4 2773 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2774 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2775 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2776 } else {
2777 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2778 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2779 }
fe255d00 2780 POSTING_READ(intel_dp->output_reg);
5eb08b69 2781
493a7081 2782 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2783 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2784 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2785
5bddd17f
EA		 2786 /* Hardware workaround: leaving our transcoder select
2787 * set to transcoder B while it's off will prevent the
2788 * corresponding HDMI output on transcoder A.
2789 *
2790 * Combine this with another hardware workaround:
2791 * transcoder select bit can only be cleared while the
2792 * port is enabled.
2793 */
2794 DP &= ~DP_PIPEB_SELECT;
2795 I915_WRITE(intel_dp->output_reg, DP);
2796
2797 /* Changes to enable or select take place the vblank
2798 * after being written.
2799 */
ff50afe9
DV		 2800 if (WARN_ON(crtc == NULL)) {
2801 /* We should never try to disable a port without a crtc
2802 * attached. For paranoia keep the code around for a
2803 * bit. */
31acbcc4
CW		 2804 POSTING_READ(intel_dp->output_reg);
2805 msleep(50);
2806 } else
ab527efc 2807 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2808 }
2809
832afda6 2810 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2811 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2812 POSTING_READ(intel_dp->output_reg);
f01eca2e 2813 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2814}
2815
26d61aad
KP		 2816static bool
2817intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2818{
a031d709
RV		 2819 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2820 struct drm_device *dev = dig_port->base.base.dev;
2821 struct drm_i915_private *dev_priv = dev->dev_private;
2822
577c7a50
DL		 2823 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2824
9d1a1031
JN		 2825 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
2826 sizeof(intel_dp->dpcd)) < 0)
edb39244 2827 return false; /* aux transfer failed */
92fd8fd1 2828
577c7a50
DL		 2829 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2830 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2831 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2832
edb39244
AJ		 2833 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2834 return false; /* DPCD not present */
2835
2293bb5c
SK		 2836 /* Check if the panel supports PSR */
2837 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 2838 if (is_edp(intel_dp)) {
9d1a1031
JN		 2839 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
2840 intel_dp->psr_dpcd,
2841 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 2842 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2843 dev_priv->psr.sink_support = true;
50003939 2844 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 2845 }
50003939
JN		 2846 }
2847
06ea66b6
TP		 2848 /* Training Pattern 3 support */
2849 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2850 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2851 intel_dp->use_tps3 = true;
2852 DRM_DEBUG_KMS("Displayport TPS3 supported");
2853 } else
2854 intel_dp->use_tps3 = false;
2855
edb39244
AJ		 2856 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2857 DP_DWN_STRM_PORT_PRESENT))
2858 return true; /* native DP sink */
2859
2860 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2861 return true; /* no per-port downstream info */
2862
9d1a1031
JN		 2863 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
2864 intel_dp->downstream_ports,
2865 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 2866 return false; /* downstream port status fetch failed */
2867
2868 return true;
92fd8fd1
KP		 2869}
2870
0d198328
AJ		 2871static void
2872intel_dp_probe_oui(struct intel_dp *intel_dp)
2873{
2874 u8 buf[3];
2875
2876 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2877 return;
2878
24f3e092 2879 intel_edp_panel_vdd_on(intel_dp);
351cfc34 2880
9d1a1031 2881 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 2882 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2883 buf[0], buf[1], buf[2]);
2884
9d1a1031 2885 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 2886 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2887 buf[0], buf[1], buf[2]);
351cfc34 2888
4be73780 2889 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2890}
2891
d2e216d0
RV		 2892int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2893{
2894 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2895 struct drm_device *dev = intel_dig_port->base.base.dev;
2896 struct intel_crtc *intel_crtc =
2897 to_intel_crtc(intel_dig_port->base.base.crtc);
2898 u8 buf[1];
2899
9d1a1031 2900 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 2901 return -EAGAIN;
2902
2903 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2904 return -ENOTTY;
2905
9d1a1031
JN		 2906 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
2907 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 2908 return -EAGAIN;
2909
2910 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2911 intel_wait_for_vblank(dev, intel_crtc->pipe);
2912 intel_wait_for_vblank(dev, intel_crtc->pipe);
2913
9d1a1031 2914 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 2915 return -EAGAIN;
2916
9d1a1031 2917 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 2918 return 0;
2919}
2920
a60f0e38
JB		 2921static bool
2922intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2923{
9d1a1031
JN		 2924 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2925 DP_DEVICE_SERVICE_IRQ_VECTOR,
2926 sink_irq_vector, 1) == 1;
a60f0e38
JB		 2927}
2928
2929static void
2930intel_dp_handle_test_request(struct intel_dp *intel_dp)
2931{
2932 /* NAK by default */
9d1a1031 2933 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2934}
2935
a4fc5ed6
KP		 2936/*
2937 * According to DP spec
2938 * 5.1.2:
2939 * 1. Read DPCD
2940 * 2. Configure link according to Receiver Capabilities
2941 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2942 * 4. Check link status on receipt of hot-plug interrupt
2943 */
2944
00c09d70 2945void
ea5b213a 2946intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2947{
da63a9f2 2948 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2949 u8 sink_irq_vector;
93f62dad 2950 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2951
da63a9f2 2952 if (!intel_encoder->connectors_active)
d2b996ac 2953 return;
59cd09e1 2954
da63a9f2 2955 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2956 return;
2957
92fd8fd1 2958 /* Try to read receiver status if the link appears to be up */
93f62dad 2959 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 2960 return;
2961 }
2962
92fd8fd1 2963 /* Now read the DPCD to see if it's actually running */
26d61aad 2964 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2965 return;
2966 }
2967
a60f0e38
JB		 2968 /* Try to read the source of the interrupt */
2969 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2970 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2971 /* Clear interrupt source */
9d1a1031
JN		 2972 drm_dp_dpcd_writeb(&intel_dp->aux,
2973 DP_DEVICE_SERVICE_IRQ_VECTOR,
2974 sink_irq_vector);
a60f0e38
JB		 2975
2976 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2977 intel_dp_handle_test_request(intel_dp);
2978 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2979 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2980 }
2981
1ffdff13 2982 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2983 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2984 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2985 intel_dp_start_link_train(intel_dp);
2986 intel_dp_complete_link_train(intel_dp);
3ab9c637 2987 intel_dp_stop_link_train(intel_dp);
33a34e4e 2988 }
a4fc5ed6 2989}
a4fc5ed6 2990
caf9ab24 2991/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2992static enum drm_connector_status
26d61aad 2993intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2994{
caf9ab24 2995 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 2996 uint8_t type;
2997
2998 if (!intel_dp_get_dpcd(intel_dp))
2999 return connector_status_disconnected;
3000
3001 /* if there's no downstream port, we're done */
3002 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3003 return connector_status_connected;
caf9ab24
AJ		 3004
3005 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3006 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3007 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3008 uint8_t reg;
9d1a1031
JN		 3009
3010 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3011 &reg, 1) < 0)
caf9ab24 3012 return connector_status_unknown;
9d1a1031 3013
23235177
AJ		 3014 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3015 : connector_status_disconnected;
caf9ab24
AJ		 3016 }
3017
3018 /* If no HPD, poke DDC gently */
0b99836f 3019 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3020 return connector_status_connected;
caf9ab24
AJ		 3021
3022 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3023 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3024 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3025 if (type == DP_DS_PORT_TYPE_VGA ||
3026 type == DP_DS_PORT_TYPE_NON_EDID)
3027 return connector_status_unknown;
3028 } else {
3029 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3030 DP_DWN_STRM_PORT_TYPE_MASK;
3031 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3032 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3033 return connector_status_unknown;
3034 }
caf9ab24
AJ		 3035
3036 /* Anything else is out of spec, warn and ignore */
3037 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3038 return connector_status_disconnected;
71ba9000
AJ		 3039}
3040
5eb08b69 3041static enum drm_connector_status
a9756bb5 3042ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3043{
30add22d 3044 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3045 struct drm_i915_private *dev_priv = dev->dev_private;
3046 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3047 enum drm_connector_status status;
3048
fe16d949
CW		 3049 /* Can't disconnect eDP, but you can close the lid... */
3050 if (is_edp(intel_dp)) {
30add22d 3051 status = intel_panel_detect(dev);
fe16d949
CW		 3052 if (status == connector_status_unknown)
3053 status = connector_status_connected;
3054 return status;
3055 }
01cb9ea6 3056
1b469639
DL		 3057 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3058 return connector_status_disconnected;
3059
26d61aad 3060 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3061}
3062
a4fc5ed6 3063static enum drm_connector_status
a9756bb5 3064g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3065{
30add22d 3066 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3067 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3068 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3069 uint32_t bit;
5eb08b69 3070
35aad75f
JB		 3071 /* Can't disconnect eDP, but you can close the lid... */
3072 if (is_edp(intel_dp)) {
3073 enum drm_connector_status status;
3074
3075 status = intel_panel_detect(dev);
3076 if (status == connector_status_unknown)
3077 status = connector_status_connected;
3078 return status;
3079 }
3080
232a6ee9
TP		 3081 if (IS_VALLEYVIEW(dev)) {
3082 switch (intel_dig_port->port) {
3083 case PORT_B:
3084 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3085 break;
3086 case PORT_C:
3087 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3088 break;
3089 case PORT_D:
3090 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3091 break;
3092 default:
3093 return connector_status_unknown;
3094 }
3095 } else {
3096 switch (intel_dig_port->port) {
3097 case PORT_B:
3098 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3099 break;
3100 case PORT_C:
3101 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3102 break;
3103 case PORT_D:
3104 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3105 break;
3106 default:
3107 return connector_status_unknown;
3108 }
a4fc5ed6
KP		 3109 }
3110
10f76a38 3111 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3112 return connector_status_disconnected;
3113
26d61aad 3114 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3115}
3116
8c241fef
KP		 3117static struct edid *
3118intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3119{
9cd300e0 3120 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3121
9cd300e0
JN		 3122 /* use cached edid if we have one */
3123 if (intel_connector->edid) {
9cd300e0
JN		 3124 /* invalid edid */
3125 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3126 return NULL;
3127
55e9edeb 3128 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3129 }
8c241fef 3130
9cd300e0 3131 return drm_get_edid(connector, adapter);
8c241fef
KP		 3132}
3133
3134static int
3135intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3136{
9cd300e0 3137 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3138
9cd300e0
JN		 3139 /* use cached edid if we have one */
3140 if (intel_connector->edid) {
3141 /* invalid edid */
3142 if (IS_ERR(intel_connector->edid))
3143 return 0;
3144
3145 return intel_connector_update_modes(connector,
3146 intel_connector->edid);
d6f24d0f
JB		 3147 }
3148
9cd300e0 3149 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3150}
3151
a9756bb5
ZW		 3152static enum drm_connector_status
3153intel_dp_detect(struct drm_connector *connector, bool force)
3154{
3155 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3156 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3157 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3158 struct drm_device *dev = connector->dev;
c8c8fb33 3159 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3160 enum drm_connector_status status;
671dedd2 3161 enum intel_display_power_domain power_domain;
a9756bb5
ZW		 3162 struct edid *edid = NULL;
3163
c8c8fb33
PZ		 3164 intel_runtime_pm_get(dev_priv);
3165
671dedd2
ID		 3166 power_domain = intel_display_port_power_domain(intel_encoder);
3167 intel_display_power_get(dev_priv, power_domain);
3168
164c8598
CW		 3169 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3170 connector->base.id, drm_get_connector_name(connector));
3171
a9756bb5
ZW		 3172 intel_dp->has_audio = false;
3173
3174 if (HAS_PCH_SPLIT(dev))
3175 status = ironlake_dp_detect(intel_dp);
3176 else
3177 status = g4x_dp_detect(intel_dp);
1b9be9d0 3178
a9756bb5 3179 if (status != connector_status_connected)
c8c8fb33 3180 goto out;
a9756bb5 3181
0d198328
AJ		 3182 intel_dp_probe_oui(intel_dp);
3183
c3e5f67b
DV		 3184 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3185 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3186 } else {
0b99836f 3187 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
f684960e
CW		 3188 if (edid) {
3189 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3190 kfree(edid);
3191 }
a9756bb5
ZW		 3192 }
3193
d63885da
PZ		 3194 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3195 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3196 status = connector_status_connected;
3197
3198out:
671dedd2
ID		 3199 intel_display_power_put(dev_priv, power_domain);
3200
c8c8fb33 3201 intel_runtime_pm_put(dev_priv);
671dedd2 3202
c8c8fb33 3203 return status;
a4fc5ed6
KP		 3204}
3205
3206static int intel_dp_get_modes(struct drm_connector *connector)
3207{
df0e9248 3208 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3209 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3210 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3211 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3212 struct drm_device *dev = connector->dev;
671dedd2
ID		 3213 struct drm_i915_private *dev_priv = dev->dev_private;
3214 enum intel_display_power_domain power_domain;
32f9d658 3215 int ret;
a4fc5ed6
KP		 3216
3217 /* We should parse the EDID data and find out if it has an audio sink
3218 */
3219
671dedd2
ID		 3220 power_domain = intel_display_port_power_domain(intel_encoder);
3221 intel_display_power_get(dev_priv, power_domain);
3222
0b99836f 3223 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
671dedd2 3224 intel_display_power_put(dev_priv, power_domain);
f8779fda 3225 if (ret)
32f9d658
ZW		 3226 return ret;
3227
f8779fda 3228 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3229 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3230 struct drm_display_mode *mode;
dd06f90e
JN		 3231 mode = drm_mode_duplicate(dev,
3232 intel_connector->panel.fixed_mode);
f8779fda 3233 if (mode) {
32f9d658
ZW		 3234 drm_mode_probed_add(connector, mode);
3235 return 1;
3236 }
3237 }
3238 return 0;
a4fc5ed6
KP		 3239}
3240
1aad7ac0
CW		 3241static bool
3242intel_dp_detect_audio(struct drm_connector *connector)
3243{
3244 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3245 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3246 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3247 struct drm_device *dev = connector->dev;
3248 struct drm_i915_private *dev_priv = dev->dev_private;
3249 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3250 struct edid *edid;
3251 bool has_audio = false;
3252
671dedd2
ID		 3253 power_domain = intel_display_port_power_domain(intel_encoder);
3254 intel_display_power_get(dev_priv, power_domain);
3255
0b99836f 3256 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
1aad7ac0
CW		 3257 if (edid) {
3258 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3259 kfree(edid);
3260 }
3261
671dedd2
ID		 3262 intel_display_power_put(dev_priv, power_domain);
3263
1aad7ac0
CW		 3264 return has_audio;
3265}
3266
f684960e
CW		 3267static int
3268intel_dp_set_property(struct drm_connector *connector,
3269 struct drm_property *property,
3270 uint64_t val)
3271{
e953fd7b 3272 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3273 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3274 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3275 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3276 int ret;
3277
662595df 3278 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3279 if (ret)
3280 return ret;
3281
3f43c48d 3282 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3283 int i = val;
3284 bool has_audio;
3285
3286 if (i == intel_dp->force_audio)
f684960e
CW		 3287 return 0;
3288
1aad7ac0 3289 intel_dp->force_audio = i;
f684960e 3290
c3e5f67b 3291 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3292 has_audio = intel_dp_detect_audio(connector);
3293 else
c3e5f67b 3294 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3295
3296 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3297 return 0;
3298
1aad7ac0 3299 intel_dp->has_audio = has_audio;
f684960e
CW		 3300 goto done;
3301 }
3302
e953fd7b 3303 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3304 bool old_auto = intel_dp->color_range_auto;
3305 uint32_t old_range = intel_dp->color_range;
3306
55bc60db
VS		 3307 switch (val) {
3308 case INTEL_BROADCAST_RGB_AUTO:
3309 intel_dp->color_range_auto = true;
3310 break;
3311 case INTEL_BROADCAST_RGB_FULL:
3312 intel_dp->color_range_auto = false;
3313 intel_dp->color_range = 0;
3314 break;
3315 case INTEL_BROADCAST_RGB_LIMITED:
3316 intel_dp->color_range_auto = false;
3317 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3318 break;
3319 default:
3320 return -EINVAL;
3321 }
ae4edb80
DV		 3322
3323 if (old_auto == intel_dp->color_range_auto &&
3324 old_range == intel_dp->color_range)
3325 return 0;
3326
e953fd7b
CW		 3327 goto done;
3328 }
3329
53b41837
YN		 3330 if (is_edp(intel_dp) &&
3331 property == connector->dev->mode_config.scaling_mode_property) {
3332 if (val == DRM_MODE_SCALE_NONE) {
3333 DRM_DEBUG_KMS("no scaling not supported\n");
3334 return -EINVAL;
3335 }
3336
3337 if (intel_connector->panel.fitting_mode == val) {
3338 /* the eDP scaling property is not changed */
3339 return 0;
3340 }
3341 intel_connector->panel.fitting_mode = val;
3342
3343 goto done;
3344 }
3345
f684960e
CW		 3346 return -EINVAL;
3347
3348done:
c0c36b94
CW		 3349 if (intel_encoder->base.crtc)
3350 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3351
3352 return 0;
3353}
3354
a4fc5ed6 3355static void
73845adf 3356intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3357{
1d508706 3358 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3359
9cd300e0
JN		 3360 if (!IS_ERR_OR_NULL(intel_connector->edid))
3361 kfree(intel_connector->edid);
3362
acd8db10
PZ		 3363 /* Can't call is_edp() since the encoder may have been destroyed
3364 * already. */
3365 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3366 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3367
a4fc5ed6 3368 drm_connector_cleanup(connector);
55f78c43 3369 kfree(connector);
a4fc5ed6
KP		 3370}
3371
00c09d70 3372void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3373{
da63a9f2
PZ		 3374 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3375 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3376 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927 3377
0b99836f 3378 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
24d05927 3379 drm_encoder_cleanup(encoder);
bd943159
KP		 3380 if (is_edp(intel_dp)) {
3381 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3382 mutex_lock(&dev->mode_config.mutex);
4be73780 3383 edp_panel_vdd_off_sync(intel_dp);
bd173813 3384 mutex_unlock(&dev->mode_config.mutex);
bd943159 3385 }
da63a9f2 3386 kfree(intel_dig_port);
24d05927
DV		 3387}
3388
a4fc5ed6 3389static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3390 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3391 .detect = intel_dp_detect,
3392 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3393 .set_property = intel_dp_set_property,
73845adf 3394 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3395};
3396
3397static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3398 .get_modes = intel_dp_get_modes,
3399 .mode_valid = intel_dp_mode_valid,
df0e9248 3400 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3401};
3402
a4fc5ed6 3403static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3404 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3405};
3406
995b6762 3407static void
21d40d37 3408intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3409{
fa90ecef 3410 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3411
885a5014 3412 intel_dp_check_link_status(intel_dp);
c8110e52 3413}
6207937d 3414
e3421a18
ZW		 3415/* Return which DP Port should be selected for Transcoder DP control */
3416int
0206e353 3417intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3418{
3419 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3420 struct intel_encoder *intel_encoder;
3421 struct intel_dp *intel_dp;
e3421a18 3422
fa90ecef
PZ		 3423 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3424 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3425
fa90ecef
PZ		 3426 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3427 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3428 return intel_dp->output_reg;
e3421a18 3429 }
ea5b213a 3430
e3421a18
ZW		 3431 return -1;
3432}
3433
36e83a18 3434/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3435bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3436{
3437 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3438 union child_device_config *p_child;
36e83a18 3439 int i;
5d8a7752
VS		 3440 static const short port_mapping[] = {
3441 [PORT_B] = PORT_IDPB,
3442 [PORT_C] = PORT_IDPC,
3443 [PORT_D] = PORT_IDPD,
3444 };
36e83a18 3445
3b32a35b
VS		 3446 if (port == PORT_A)
3447 return true;
3448
41aa3448 3449 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3450 return false;
3451
41aa3448
RV		 3452 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3453 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3454
5d8a7752 3455 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3456 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3457 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3458 return true;
3459 }
3460 return false;
3461}
3462
f684960e
CW		 3463static void
3464intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3465{
53b41837
YN		 3466 struct intel_connector *intel_connector = to_intel_connector(connector);
3467
3f43c48d 3468 intel_attach_force_audio_property(connector);
e953fd7b 3469 intel_attach_broadcast_rgb_property(connector);
55bc60db 3470 intel_dp->color_range_auto = true;
53b41837
YN		 3471
3472 if (is_edp(intel_dp)) {
3473 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3474 drm_object_attach_property(
3475 &connector->base,
53b41837 3476 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3477 DRM_MODE_SCALE_ASPECT);
3478 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3479 }
f684960e
CW		 3480}
3481
dada1a9f
ID		 3482static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3483{
3484 intel_dp->last_power_cycle = jiffies;
3485 intel_dp->last_power_on = jiffies;
3486 intel_dp->last_backlight_off = jiffies;
3487}
3488
67a54566
DV		 3489static void
3490intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3491 struct intel_dp *intel_dp,
3492 struct edp_power_seq *out)
67a54566
DV		 3493{
3494 struct drm_i915_private *dev_priv = dev->dev_private;
3495 struct edp_power_seq cur, vbt, spec, final;
3496 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3497 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3498
3499 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3500 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3501 pp_on_reg = PCH_PP_ON_DELAYS;
3502 pp_off_reg = PCH_PP_OFF_DELAYS;
3503 pp_div_reg = PCH_PP_DIVISOR;
3504 } else {
bf13e81b
JN		 3505 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3506
3507 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3508 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3509 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3510 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3511 }
67a54566
DV		 3512
3513 /* Workaround: Need to write PP_CONTROL with the unlock key as
3514 * the very first thing. */
453c5420 3515 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3516 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3517
453c5420
JB		 3518 pp_on = I915_READ(pp_on_reg);
3519 pp_off = I915_READ(pp_off_reg);
3520 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3521
3522 /* Pull timing values out of registers */
3523 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3524 PANEL_POWER_UP_DELAY_SHIFT;
3525
3526 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3527 PANEL_LIGHT_ON_DELAY_SHIFT;
3528
3529 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3530 PANEL_LIGHT_OFF_DELAY_SHIFT;
3531
3532 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3533 PANEL_POWER_DOWN_DELAY_SHIFT;
3534
3535 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3536 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3537
3538 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3539 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3540
41aa3448 3541 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3542
3543 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3544 * our hw here, which are all in 100usec. */
3545 spec.t1_t3 = 210 * 10;
3546 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3547 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3548 spec.t10 = 500 * 10;
3549 /* This one is special and actually in units of 100ms, but zero
3550 * based in the hw (so we need to add 100 ms). But the sw vbt
3551 * table multiplies it with 1000 to make it in units of 100usec,
3552 * too. */
3553 spec.t11_t12 = (510 + 100) * 10;
3554
3555 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3556 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3557
3558 /* Use the max of the register settings and vbt. If both are
3559 * unset, fall back to the spec limits. */
3560#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3561 spec.field : \
3562 max(cur.field, vbt.field))
3563 assign_final(t1_t3);
3564 assign_final(t8);
3565 assign_final(t9);
3566 assign_final(t10);
3567 assign_final(t11_t12);
3568#undef assign_final
3569
3570#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3571 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3572 intel_dp->backlight_on_delay = get_delay(t8);
3573 intel_dp->backlight_off_delay = get_delay(t9);
3574 intel_dp->panel_power_down_delay = get_delay(t10);
3575 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3576#undef get_delay
3577
f30d26e4
JN		 3578 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3579 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3580 intel_dp->panel_power_cycle_delay);
3581
3582 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3583 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3584
3585 if (out)
3586 *out = final;
3587}
3588
3589static void
3590intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3591 struct intel_dp *intel_dp,
3592 struct edp_power_seq *seq)
3593{
3594 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3595 u32 pp_on, pp_off, pp_div, port_sel = 0;
3596 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3597 int pp_on_reg, pp_off_reg, pp_div_reg;
3598
3599 if (HAS_PCH_SPLIT(dev)) {
3600 pp_on_reg = PCH_PP_ON_DELAYS;
3601 pp_off_reg = PCH_PP_OFF_DELAYS;
3602 pp_div_reg = PCH_PP_DIVISOR;
3603 } else {
bf13e81b
JN		 3604 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3605
3606 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3607 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3608 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3609 }
3610
b2f19d1a
PZ		 3611 /*
3612 * And finally store the new values in the power sequencer. The
3613 * backlight delays are set to 1 because we do manual waits on them. For
3614 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3615 * we'll end up waiting for the backlight off delay twice: once when we
3616 * do the manual sleep, and once when we disable the panel and wait for
3617 * the PP_STATUS bit to become zero.
3618 */
f30d26e4 3619 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 3620 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3621 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 3622 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3623 /* Compute the divisor for the pp clock, simply match the Bspec
3624 * formula. */
453c5420 3625 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3626 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3627 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3628
3629 /* Haswell doesn't have any port selection bits for the panel
3630 * power sequencer any more. */
bc7d38a4 3631 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3632 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3633 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3634 else
3635 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3636 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3637 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3638 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3639 else
a24c144c 3640 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3641 }
3642
453c5420
JB		 3643 pp_on |= port_sel;
3644
3645 I915_WRITE(pp_on_reg, pp_on);
3646 I915_WRITE(pp_off_reg, pp_off);
3647 I915_WRITE(pp_div_reg, pp_div);
67a54566 3648
67a54566 3649 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3650 I915_READ(pp_on_reg),
3651 I915_READ(pp_off_reg),
3652 I915_READ(pp_div_reg));
f684960e
CW		 3653}
3654
439d7ac0
PB		 3655void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
3656{
3657 struct drm_i915_private *dev_priv = dev->dev_private;
3658 struct intel_encoder *encoder;
3659 struct intel_dp *intel_dp = NULL;
3660 struct intel_crtc_config *config = NULL;
3661 struct intel_crtc *intel_crtc = NULL;
3662 struct intel_connector *intel_connector = dev_priv->drrs.connector;
3663 u32 reg, val;
3664 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
3665
3666 if (refresh_rate <= 0) {
3667 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
3668 return;
3669 }
3670
3671 if (intel_connector == NULL) {
3672 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
3673 return;
3674 }
3675
3676 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
3677 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
3678 return;
3679 }
3680
3681 encoder = intel_attached_encoder(&intel_connector->base);
3682 intel_dp = enc_to_intel_dp(&encoder->base);
3683 intel_crtc = encoder->new_crtc;
3684
3685 if (!intel_crtc) {
3686 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
3687 return;
3688 }
3689
3690 config = &intel_crtc->config;
3691
3692 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
3693 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
3694 return;
3695 }
3696
3697 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
3698 index = DRRS_LOW_RR;
3699
3700 if (index == intel_dp->drrs_state.refresh_rate_type) {
3701 DRM_DEBUG_KMS(
3702 "DRRS requested for previously set RR...ignoring\n");
3703 return;
3704 }
3705
3706 if (!intel_crtc->active) {
3707 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
3708 return;
3709 }
3710
3711 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
3712 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
3713 val = I915_READ(reg);
3714 if (index > DRRS_HIGH_RR) {
3715 val |= PIPECONF_EDP_RR_MODE_SWITCH;
3716 intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
3717 } else {
3718 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
3719 }
3720 I915_WRITE(reg, val);
3721 }
3722
3723 /*
3724 * mutex taken to ensure that there is no race between differnt
3725 * drrs calls trying to update refresh rate. This scenario may occur
3726 * in future when idleness detection based DRRS in kernel and
3727 * possible calls from user space to set differnt RR are made.
3728 */
3729
3730 mutex_lock(&intel_dp->drrs_state.mutex);
3731
3732 intel_dp->drrs_state.refresh_rate_type = index;
3733
3734 mutex_unlock(&intel_dp->drrs_state.mutex);
3735
3736 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
3737}
3738
4f9db5b5
PB		 3739static struct drm_display_mode *
3740intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
3741 struct intel_connector *intel_connector,
3742 struct drm_display_mode *fixed_mode)
3743{
3744 struct drm_connector *connector = &intel_connector->base;
3745 struct intel_dp *intel_dp = &intel_dig_port->dp;
3746 struct drm_device *dev = intel_dig_port->base.base.dev;
3747 struct drm_i915_private *dev_priv = dev->dev_private;
3748 struct drm_display_mode *downclock_mode = NULL;
3749
3750 if (INTEL_INFO(dev)->gen <= 6) {
3751 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
3752 return NULL;
3753 }
3754
3755 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
3756 DRM_INFO("VBT doesn't support DRRS\n");
3757 return NULL;
3758 }
3759
3760 downclock_mode = intel_find_panel_downclock
3761 (dev, fixed_mode, connector);
3762
3763 if (!downclock_mode) {
3764 DRM_INFO("DRRS not supported\n");
3765 return NULL;
3766 }
3767
439d7ac0
PB		 3768 dev_priv->drrs.connector = intel_connector;
3769
3770 mutex_init(&intel_dp->drrs_state.mutex);
3771
4f9db5b5
PB		 3772 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
3773
3774 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
3775 DRM_INFO("seamless DRRS supported for eDP panel.\n");
3776 return downclock_mode;
3777}
3778
ed92f0b2 3779static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 3780 struct intel_connector *intel_connector,
3781 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 3782{
3783 struct drm_connector *connector = &intel_connector->base;
3784 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 3785 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3786 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 3787 struct drm_i915_private *dev_priv = dev->dev_private;
3788 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 3789 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 3790 bool has_dpcd;
3791 struct drm_display_mode *scan;
3792 struct edid *edid;
3793
4f9db5b5
PB		 3794 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
3795
ed92f0b2
PZ		 3796 if (!is_edp(intel_dp))
3797 return true;
3798
63635217
PZ		 3799 /* The VDD bit needs a power domain reference, so if the bit is already
3800 * enabled when we boot, grab this reference. */
3801 if (edp_have_panel_vdd(intel_dp)) {
3802 enum intel_display_power_domain power_domain;
3803 power_domain = intel_display_port_power_domain(intel_encoder);
3804 intel_display_power_get(dev_priv, power_domain);
3805 }
3806
ed92f0b2 3807 /* Cache DPCD and EDID for edp. */
24f3e092 3808 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 3809 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 3810 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 3811
3812 if (has_dpcd) {
3813 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3814 dev_priv->no_aux_handshake =
3815 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3816 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3817 } else {
3818 /* if this fails, presume the device is a ghost */
3819 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3820 return false;
3821 }
3822
3823 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 3824 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 3825
060c8778 3826 mutex_lock(&dev->mode_config.mutex);
0b99836f 3827 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 3828 if (edid) {
3829 if (drm_add_edid_modes(connector, edid)) {
3830 drm_mode_connector_update_edid_property(connector,
3831 edid);
3832 drm_edid_to_eld(connector, edid);
3833 } else {
3834 kfree(edid);
3835 edid = ERR_PTR(-EINVAL);
3836 }
3837 } else {
3838 edid = ERR_PTR(-ENOENT);
3839 }
3840 intel_connector->edid = edid;
3841
3842 /* prefer fixed mode from EDID if available */
3843 list_for_each_entry(scan, &connector->probed_modes, head) {
3844 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3845 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 3846 downclock_mode = intel_dp_drrs_init(
3847 intel_dig_port,
3848 intel_connector, fixed_mode);
ed92f0b2
PZ		 3849 break;
3850 }
3851 }
3852
3853 /* fallback to VBT if available for eDP */
3854 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3855 fixed_mode = drm_mode_duplicate(dev,
3856 dev_priv->vbt.lfp_lvds_vbt_mode);
3857 if (fixed_mode)
3858 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3859 }
060c8778 3860 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 3861
4f9db5b5 3862 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
ed92f0b2
PZ		 3863 intel_panel_setup_backlight(connector);
3864
3865 return true;
3866}
3867
16c25533 3868bool
f0fec3f2
PZ		 3869intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3870 struct intel_connector *intel_connector)
a4fc5ed6 3871{
f0fec3f2
PZ		 3872 struct drm_connector *connector = &intel_connector->base;
3873 struct intel_dp *intel_dp = &intel_dig_port->dp;
3874 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3875 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3876 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3877 enum port port = intel_dig_port->port;
0095e6dc 3878 struct edp_power_seq power_seq = { 0 };
0b99836f 3879 int type;
a4fc5ed6 3880
ec5b01dd
DL		 3881 /* intel_dp vfuncs */
3882 if (IS_VALLEYVIEW(dev))
3883 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3884 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3885 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3886 else if (HAS_PCH_SPLIT(dev))
3887 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3888 else
3889 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3890
153b1100
DL		 3891 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3892
0767935e
DV		 3893 /* Preserve the current hw state. */
3894 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3895 intel_dp->attached_connector = intel_connector;
3d3dc149 3896
3b32a35b 3897 if (intel_dp_is_edp(dev, port))
b329530c 3898 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 3899 else
3900 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 3901
f7d24902
ID		 3902 /*
3903 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3904 * for DP the encoder type can be set by the caller to
3905 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3906 */
3907 if (type == DRM_MODE_CONNECTOR_eDP)
3908 intel_encoder->type = INTEL_OUTPUT_EDP;
3909
e7281eab
ID		 3910 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3911 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3912 port_name(port));
3913
b329530c 3914 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3915 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3916
a4fc5ed6
KP		 3917 connector->interlace_allowed = true;
3918 connector->doublescan_allowed = 0;
3919
f0fec3f2 3920 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 3921 edp_panel_vdd_work);
a4fc5ed6 3922
df0e9248 3923 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3924 drm_sysfs_connector_add(connector);
3925
affa9354 3926 if (HAS_DDI(dev))
bcbc889b
PZ		 3927 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3928 else
3929 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 3930 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 3931
0b99836f 3932 /* Set up the hotplug pin. */
ab9d7c30
PZ		 3933 switch (port) {
3934 case PORT_A:
1d843f9d 3935 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3936 break;
3937 case PORT_B:
1d843f9d 3938 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3939 break;
3940 case PORT_C:
1d843f9d 3941 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3942 break;
3943 case PORT_D:
1d843f9d 3944 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3945 break;
3946 default:
ad1c0b19 3947 BUG();
5eb08b69
ZW		 3948 }
3949
dada1a9f
ID		 3950 if (is_edp(intel_dp)) {
3951 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 3952 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 3953 }
0095e6dc 3954
9d1a1031 3955 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 3956
2b28bb1b
RV		 3957 intel_dp->psr_setup_done = false;
3958
0095e6dc 3959 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
0b99836f 3960 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
15b1d171
PZ		 3961 if (is_edp(intel_dp)) {
3962 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3963 mutex_lock(&dev->mode_config.mutex);
4be73780 3964 edp_panel_vdd_off_sync(intel_dp);
15b1d171
PZ		 3965 mutex_unlock(&dev->mode_config.mutex);
3966 }
b2f246a8
PZ		 3967 drm_sysfs_connector_remove(connector);
3968 drm_connector_cleanup(connector);
16c25533 3969 return false;
b2f246a8 3970 }
32f9d658 3971
f684960e
CW		 3972 intel_dp_add_properties(intel_dp, connector);
3973
a4fc5ed6
KP		 3974 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3975 * 0xd. Failure to do so will result in spurious interrupts being
3976 * generated on the port when a cable is not attached.
3977 */
3978 if (IS_G4X(dev) && !IS_GM45(dev)) {
3979 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3980 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3981 }
16c25533
PZ		 3982
3983 return true;
a4fc5ed6 3984}
f0fec3f2
PZ		 3985
3986void
3987intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3988{
3989 struct intel_digital_port *intel_dig_port;
3990 struct intel_encoder *intel_encoder;
3991 struct drm_encoder *encoder;
3992 struct intel_connector *intel_connector;
3993
b14c5679 3994 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 3995 if (!intel_dig_port)
3996 return;
3997
b14c5679 3998 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 3999 if (!intel_connector) {
4000 kfree(intel_dig_port);
4001 return;
4002 }
4003
4004 intel_encoder = &intel_dig_port->base;
4005 encoder = &intel_encoder->base;
4006
4007 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4008 DRM_MODE_ENCODER_TMDS);
4009
5bfe2ac0 4010 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 4011 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70 4012 intel_encoder->disable = intel_disable_dp;
00c09d70 4013 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 4014 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 4015 if (IS_VALLEYVIEW(dev)) {
ecff4f3b 4016 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 4017 intel_encoder->pre_enable = vlv_pre_enable_dp;
4018 intel_encoder->enable = vlv_enable_dp;
49277c31 4019 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 4020 } else {
ecff4f3b
JN		 4021 intel_encoder->pre_enable = g4x_pre_enable_dp;
4022 intel_encoder->enable = g4x_enable_dp;
49277c31 4023 intel_encoder->post_disable = g4x_post_disable_dp;
ab1f90f9 4024 }
f0fec3f2 4025
174edf1f 4026 intel_dig_port->port = port;
f0fec3f2
PZ		 4027 intel_dig_port->dp.output_reg = output_reg;
4028
00c09d70 4029 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2 4030 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 4031 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 4032 intel_encoder->hot_plug = intel_dp_hot_plug;
4033
15b1d171
PZ		 4034 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4035 drm_encoder_cleanup(encoder);
4036 kfree(intel_dig_port);
b2f246a8 4037 kfree(intel_connector);
15b1d171 4038 }
f0fec3f2 4039}
Linux kernel - Deliverables
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