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perf: Fix ring_buffer_attach() RCU sync, again
[deliverable/linux.git] / arch / x86 / kernel / cpu / perf_event_intel.c
CommitLineData
a7e3ed1e 1/*
efc9f05d
SE		 2 * Per core/cpu state
3 *
4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
a7e3ed1e 6 */
de0428a7 7
c767a54b
JP		 8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
de0428a7
KW		 10#include <linux/stddef.h>
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/slab.h>
69c60c88 14#include <linux/export.h>
b37609c3 15#include <linux/watchdog.h>
de0428a7 16
3a632cb2 17#include <asm/cpufeature.h>
de0428a7
KW		 18#include <asm/hardirq.h>
19#include <asm/apic.h>
20
21#include "perf_event.h"
a7e3ed1e 22
f22f54f4 23/*
b622d644 24 * Intel PerfMon, used on Core and later.
f22f54f4 25 */
ec75a716 26static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
f22f54f4 27{
c3b7cdf1
PE		 28 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
29 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
30 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
31 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
32 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
33 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
34 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
35 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
f22f54f4
PZ		 36};
37
5c543e3c 38static struct event_constraint intel_core_event_constraints[] __read_mostly =
f22f54f4
PZ		 39{
40 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
41 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
42 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
43 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
44 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
45 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
46 EVENT_CONSTRAINT_END
47};
48
5c543e3c 49static struct event_constraint intel_core2_event_constraints[] __read_mostly =
f22f54f4 50{
b622d644
PZ		 51 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
52 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 53 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 54 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
55 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
56 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
57 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
58 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
59 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
60 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
61 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
b622d644 62 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
f22f54f4
PZ		 63 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
64 EVENT_CONSTRAINT_END
65};
66
5c543e3c 67static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
f22f54f4 68{
b622d644
PZ		 69 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
70 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 71 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 72 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
73 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
74 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
75 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
76 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
77 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
78 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
79 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
80 EVENT_CONSTRAINT_END
81};
82
5c543e3c 83static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
a7e3ed1e 84{
53ad0447
YZ		 85 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
86 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
f20093ee 87 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 88 EVENT_EXTRA_END
89};
90
5c543e3c 91static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
f22f54f4 92{
b622d644
PZ		 93 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
94 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 95 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 96 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
97 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
98 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
d1100770 99 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
f22f54f4
PZ		 100 EVENT_CONSTRAINT_END
101};
102
5c543e3c 103static struct event_constraint intel_snb_event_constraints[] __read_mostly =
b06b3d49
LM		 104{
105 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
106 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 107 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
fd4a5aef
SE		 108 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
109 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
110 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
111 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
b06b3d49 112 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
b06b3d49
LM		 113 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
114 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
f8378f52
AK		 115 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
116 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
93fcf72c
MD		 117
118 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
119 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
120 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
121 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
122
b06b3d49
LM		 123 EVENT_CONSTRAINT_END
124};
125
69943182
SE		 126static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
127{
128 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
129 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
130 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
131 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
132 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
133 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
6113af14 134 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
69943182
SE		 135 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
136 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
137 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
138 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
139 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
140 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
93fcf72c
MD		 141
142 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
143 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
144 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
145 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
146
69943182
SE		 147 EVENT_CONSTRAINT_END
148};
149
5c543e3c 150static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
a7e3ed1e 151{
53ad0447
YZ		 152 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
153 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
154 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
f20093ee 155 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 156 EVENT_EXTRA_END
157};
158
0af3ac1f
AK		 159static struct event_constraint intel_v1_event_constraints[] __read_mostly =
160{
161 EVENT_CONSTRAINT_END
162};
163
5c543e3c 164static struct event_constraint intel_gen_event_constraints[] __read_mostly =
f22f54f4 165{
b622d644
PZ		 166 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
167 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 168 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 169 EVENT_CONSTRAINT_END
170};
171
1fa64180
YZ		 172static struct event_constraint intel_slm_event_constraints[] __read_mostly =
173{
174 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
175 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
1fa64180
YZ		 176 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
177 EVENT_CONSTRAINT_END
178};
179
ee89cbc2 180static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
53ad0447
YZ		 181 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
182 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
183 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
f20093ee 184 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
f1923820
SE		 185 EVENT_EXTRA_END
186};
187
188static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
53ad0447
YZ		 189 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
190 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
191 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
f1a52789 192 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
ee89cbc2
SE		 193 EVENT_EXTRA_END
194};
195
7f2ee91f
IM		 196EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
197EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
198EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
f20093ee
SE		 199
200struct attribute *nhm_events_attrs[] = {
201 EVENT_PTR(mem_ld_nhm),
202 NULL,
203};
204
205struct attribute *snb_events_attrs[] = {
206 EVENT_PTR(mem_ld_snb),
9ad64c0f 207 EVENT_PTR(mem_st_snb),
f20093ee
SE		 208 NULL,
209};
210
3a632cb2
AK		 211static struct event_constraint intel_hsw_event_constraints[] = {
212 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
213 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
214 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
215 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.* */
216 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
217 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
218 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
c420f19b 219 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
3a632cb2 220 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
c420f19b 221 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
3a632cb2 222 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
c420f19b 223 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
93fcf72c
MD		 224
225 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
226 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
227 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
228 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
229
3a632cb2
AK		 230 EVENT_CONSTRAINT_END
231};
232
91f1b705
AK		 233struct event_constraint intel_bdw_event_constraints[] = {
234 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
235 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
236 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
237 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
238 INTEL_EVENT_CONSTRAINT(0xa3, 0x4), /* CYCLE_ACTIVITY.* */
239 EVENT_CONSTRAINT_END
240};
241
f22f54f4
PZ		 242static u64 intel_pmu_event_map(int hw_event)
243{
244 return intel_perfmon_event_map[hw_event];
245}
246
74e6543f
YZ		 247#define SNB_DMND_DATA_RD (1ULL << 0)
248#define SNB_DMND_RFO (1ULL << 1)
249#define SNB_DMND_IFETCH (1ULL << 2)
250#define SNB_DMND_WB (1ULL << 3)
251#define SNB_PF_DATA_RD (1ULL << 4)
252#define SNB_PF_RFO (1ULL << 5)
253#define SNB_PF_IFETCH (1ULL << 6)
254#define SNB_LLC_DATA_RD (1ULL << 7)
255#define SNB_LLC_RFO (1ULL << 8)
256#define SNB_LLC_IFETCH (1ULL << 9)
257#define SNB_BUS_LOCKS (1ULL << 10)
258#define SNB_STRM_ST (1ULL << 11)
259#define SNB_OTHER (1ULL << 15)
260#define SNB_RESP_ANY (1ULL << 16)
261#define SNB_NO_SUPP (1ULL << 17)
262#define SNB_LLC_HITM (1ULL << 18)
263#define SNB_LLC_HITE (1ULL << 19)
264#define SNB_LLC_HITS (1ULL << 20)
265#define SNB_LLC_HITF (1ULL << 21)
266#define SNB_LOCAL (1ULL << 22)
267#define SNB_REMOTE (0xffULL << 23)
268#define SNB_SNP_NONE (1ULL << 31)
269#define SNB_SNP_NOT_NEEDED (1ULL << 32)
270#define SNB_SNP_MISS (1ULL << 33)
271#define SNB_NO_FWD (1ULL << 34)
272#define SNB_SNP_FWD (1ULL << 35)
273#define SNB_HITM (1ULL << 36)
274#define SNB_NON_DRAM (1ULL << 37)
275
276#define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
277#define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
278#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
279
280#define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
281 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
282 SNB_HITM)
283
284#define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
285#define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
286
287#define SNB_L3_ACCESS SNB_RESP_ANY
288#define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
289
290static __initconst const u64 snb_hw_cache_extra_regs
291 [PERF_COUNT_HW_CACHE_MAX]
292 [PERF_COUNT_HW_CACHE_OP_MAX]
293 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
294{
295 [ C(LL ) ] = {
296 [ C(OP_READ) ] = {
297 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
298 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
299 },
300 [ C(OP_WRITE) ] = {
301 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
302 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
303 },
304 [ C(OP_PREFETCH) ] = {
305 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
306 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
307 },
308 },
309 [ C(NODE) ] = {
310 [ C(OP_READ) ] = {
311 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
312 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
313 },
314 [ C(OP_WRITE) ] = {
315 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
316 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
317 },
318 [ C(OP_PREFETCH) ] = {
319 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
320 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
321 },
322 },
323};
324
b06b3d49
LM		 325static __initconst const u64 snb_hw_cache_event_ids
326 [PERF_COUNT_HW_CACHE_MAX]
327 [PERF_COUNT_HW_CACHE_OP_MAX]
328 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
329{
330 [ C(L1D) ] = {
331 [ C(OP_READ) ] = {
332 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
333 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
334 },
335 [ C(OP_WRITE) ] = {
336 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
337 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
338 },
339 [ C(OP_PREFETCH) ] = {
340 [ C(RESULT_ACCESS) ] = 0x0,
341 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
342 },
343 },
344 [ C(L1I ) ] = {
345 [ C(OP_READ) ] = {
346 [ C(RESULT_ACCESS) ] = 0x0,
347 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
348 },
349 [ C(OP_WRITE) ] = {
350 [ C(RESULT_ACCESS) ] = -1,
351 [ C(RESULT_MISS) ] = -1,
352 },
353 [ C(OP_PREFETCH) ] = {
354 [ C(RESULT_ACCESS) ] = 0x0,
355 [ C(RESULT_MISS) ] = 0x0,
356 },
357 },
358 [ C(LL ) ] = {
b06b3d49 359 [ C(OP_READ) ] = {
63b6a675 360 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
b06b3d49 361 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 362 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
363 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 364 },
365 [ C(OP_WRITE) ] = {
63b6a675 366 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
b06b3d49 367 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 368 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
369 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 370 },
371 [ C(OP_PREFETCH) ] = {
63b6a675 372 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
b06b3d49 373 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 374 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
375 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 376 },
377 },
378 [ C(DTLB) ] = {
379 [ C(OP_READ) ] = {
380 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
381 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
382 },
383 [ C(OP_WRITE) ] = {
384 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
385 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
386 },
387 [ C(OP_PREFETCH) ] = {
388 [ C(RESULT_ACCESS) ] = 0x0,
389 [ C(RESULT_MISS) ] = 0x0,
390 },
391 },
392 [ C(ITLB) ] = {
393 [ C(OP_READ) ] = {
394 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
395 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
396 },
397 [ C(OP_WRITE) ] = {
398 [ C(RESULT_ACCESS) ] = -1,
399 [ C(RESULT_MISS) ] = -1,
400 },
401 [ C(OP_PREFETCH) ] = {
402 [ C(RESULT_ACCESS) ] = -1,
403 [ C(RESULT_MISS) ] = -1,
404 },
405 },
406 [ C(BPU ) ] = {
407 [ C(OP_READ) ] = {
408 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
409 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
410 },
411 [ C(OP_WRITE) ] = {
412 [ C(RESULT_ACCESS) ] = -1,
413 [ C(RESULT_MISS) ] = -1,
414 },
415 [ C(OP_PREFETCH) ] = {
416 [ C(RESULT_ACCESS) ] = -1,
417 [ C(RESULT_MISS) ] = -1,
418 },
419 },
89d6c0b5
PZ		 420 [ C(NODE) ] = {
421 [ C(OP_READ) ] = {
74e6543f
YZ		 422 [ C(RESULT_ACCESS) ] = 0x01b7,
423 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 424 },
425 [ C(OP_WRITE) ] = {
74e6543f
YZ		 426 [ C(RESULT_ACCESS) ] = 0x01b7,
427 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 428 },
429 [ C(OP_PREFETCH) ] = {
74e6543f
YZ		 430 [ C(RESULT_ACCESS) ] = 0x01b7,
431 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 432 },
433 },
434
b06b3d49
LM		 435};
436
0f1b5ca2
AK		 437/*
438 * Notes on the events:
439 * - data reads do not include code reads (comparable to earlier tables)
440 * - data counts include speculative execution (except L1 write, dtlb, bpu)
441 * - remote node access includes remote memory, remote cache, remote mmio.
442 * - prefetches are not included in the counts because they are not
443 * reliably counted.
444 */
445
446#define HSW_DEMAND_DATA_RD BIT_ULL(0)
447#define HSW_DEMAND_RFO BIT_ULL(1)
448#define HSW_ANY_RESPONSE BIT_ULL(16)
449#define HSW_SUPPLIER_NONE BIT_ULL(17)
450#define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
451#define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
452#define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
453#define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
454#define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
455 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
456 HSW_L3_MISS_REMOTE_HOP2P)
457#define HSW_SNOOP_NONE BIT_ULL(31)
458#define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
459#define HSW_SNOOP_MISS BIT_ULL(33)
460#define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
461#define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
462#define HSW_SNOOP_HITM BIT_ULL(36)
463#define HSW_SNOOP_NON_DRAM BIT_ULL(37)
464#define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
465 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
466 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
467 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
468#define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
469#define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
470#define HSW_DEMAND_WRITE HSW_DEMAND_RFO
471#define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
472 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
473#define HSW_LLC_ACCESS HSW_ANY_RESPONSE
474
91f1b705
AK		 475#define BDW_L3_MISS_LOCAL BIT(26)
476#define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
477 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
478 HSW_L3_MISS_REMOTE_HOP2P)
479
480
0f1b5ca2
AK		 481static __initconst const u64 hsw_hw_cache_event_ids
482 [PERF_COUNT_HW_CACHE_MAX]
483 [PERF_COUNT_HW_CACHE_OP_MAX]
484 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
485{
486 [ C(L1D ) ] = {
487 [ C(OP_READ) ] = {
488 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
489 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
490 },
491 [ C(OP_WRITE) ] = {
492 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
493 [ C(RESULT_MISS) ] = 0x0,
494 },
495 [ C(OP_PREFETCH) ] = {
496 [ C(RESULT_ACCESS) ] = 0x0,
497 [ C(RESULT_MISS) ] = 0x0,
498 },
499 },
500 [ C(L1I ) ] = {
501 [ C(OP_READ) ] = {
502 [ C(RESULT_ACCESS) ] = 0x0,
503 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
504 },
505 [ C(OP_WRITE) ] = {
506 [ C(RESULT_ACCESS) ] = -1,
507 [ C(RESULT_MISS) ] = -1,
508 },
509 [ C(OP_PREFETCH) ] = {
510 [ C(RESULT_ACCESS) ] = 0x0,
511 [ C(RESULT_MISS) ] = 0x0,
512 },
513 },
514 [ C(LL ) ] = {
515 [ C(OP_READ) ] = {
516 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
517 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
518 },
519 [ C(OP_WRITE) ] = {
520 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
521 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
522 },
523 [ C(OP_PREFETCH) ] = {
524 [ C(RESULT_ACCESS) ] = 0x0,
525 [ C(RESULT_MISS) ] = 0x0,
526 },
527 },
528 [ C(DTLB) ] = {
529 [ C(OP_READ) ] = {
530 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
531 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
532 },
533 [ C(OP_WRITE) ] = {
534 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
535 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
536 },
537 [ C(OP_PREFETCH) ] = {
538 [ C(RESULT_ACCESS) ] = 0x0,
539 [ C(RESULT_MISS) ] = 0x0,
540 },
541 },
542 [ C(ITLB) ] = {
543 [ C(OP_READ) ] = {
544 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
545 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
546 },
547 [ C(OP_WRITE) ] = {
548 [ C(RESULT_ACCESS) ] = -1,
549 [ C(RESULT_MISS) ] = -1,
550 },
551 [ C(OP_PREFETCH) ] = {
552 [ C(RESULT_ACCESS) ] = -1,
553 [ C(RESULT_MISS) ] = -1,
554 },
555 },
556 [ C(BPU ) ] = {
557 [ C(OP_READ) ] = {
558 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
559 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
560 },
561 [ C(OP_WRITE) ] = {
562 [ C(RESULT_ACCESS) ] = -1,
563 [ C(RESULT_MISS) ] = -1,
564 },
565 [ C(OP_PREFETCH) ] = {
566 [ C(RESULT_ACCESS) ] = -1,
567 [ C(RESULT_MISS) ] = -1,
568 },
569 },
570 [ C(NODE) ] = {
571 [ C(OP_READ) ] = {
572 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
573 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
574 },
575 [ C(OP_WRITE) ] = {
576 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
577 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
578 },
579 [ C(OP_PREFETCH) ] = {
580 [ C(RESULT_ACCESS) ] = 0x0,
581 [ C(RESULT_MISS) ] = 0x0,
582 },
583 },
584};
585
586static __initconst const u64 hsw_hw_cache_extra_regs
587 [PERF_COUNT_HW_CACHE_MAX]
588 [PERF_COUNT_HW_CACHE_OP_MAX]
589 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
590{
591 [ C(LL ) ] = {
592 [ C(OP_READ) ] = {
593 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
594 HSW_LLC_ACCESS,
595 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
596 HSW_L3_MISS|HSW_ANY_SNOOP,
597 },
598 [ C(OP_WRITE) ] = {
599 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
600 HSW_LLC_ACCESS,
601 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
602 HSW_L3_MISS|HSW_ANY_SNOOP,
603 },
604 [ C(OP_PREFETCH) ] = {
605 [ C(RESULT_ACCESS) ] = 0x0,
606 [ C(RESULT_MISS) ] = 0x0,
607 },
608 },
609 [ C(NODE) ] = {
610 [ C(OP_READ) ] = {
611 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
612 HSW_L3_MISS_LOCAL_DRAM|
613 HSW_SNOOP_DRAM,
614 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
615 HSW_L3_MISS_REMOTE|
616 HSW_SNOOP_DRAM,
617 },
618 [ C(OP_WRITE) ] = {
619 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
620 HSW_L3_MISS_LOCAL_DRAM|
621 HSW_SNOOP_DRAM,
622 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
623 HSW_L3_MISS_REMOTE|
624 HSW_SNOOP_DRAM,
625 },
626 [ C(OP_PREFETCH) ] = {
627 [ C(RESULT_ACCESS) ] = 0x0,
628 [ C(RESULT_MISS) ] = 0x0,
629 },
630 },
631};
632
caaa8be3 633static __initconst const u64 westmere_hw_cache_event_ids
f22f54f4
PZ		 634 [PERF_COUNT_HW_CACHE_MAX]
635 [PERF_COUNT_HW_CACHE_OP_MAX]
636 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
637{
638 [ C(L1D) ] = {
639 [ C(OP_READ) ] = {
640 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
641 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
642 },
643 [ C(OP_WRITE) ] = {
644 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
645 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
646 },
647 [ C(OP_PREFETCH) ] = {
648 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
649 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
650 },
651 },
652 [ C(L1I ) ] = {
653 [ C(OP_READ) ] = {
654 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
655 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
656 },
657 [ C(OP_WRITE) ] = {
658 [ C(RESULT_ACCESS) ] = -1,
659 [ C(RESULT_MISS) ] = -1,
660 },
661 [ C(OP_PREFETCH) ] = {
662 [ C(RESULT_ACCESS) ] = 0x0,
663 [ C(RESULT_MISS) ] = 0x0,
664 },
665 },
666 [ C(LL ) ] = {
667 [ C(OP_READ) ] = {
63b6a675 668 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
e994d7d2 669 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 670 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
671 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 672 },
e994d7d2
AK		 673 /*
674 * Use RFO, not WRITEBACK, because a write miss would typically occur
675 * on RFO.
676 */
f22f54f4 677 [ C(OP_WRITE) ] = {
63b6a675
PZ		 678 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
679 [ C(RESULT_ACCESS) ] = 0x01b7,
680 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
e994d7d2 681 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 682 },
683 [ C(OP_PREFETCH) ] = {
63b6a675 684 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
e994d7d2 685 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 686 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
687 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 688 },
689 },
690 [ C(DTLB) ] = {
691 [ C(OP_READ) ] = {
692 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
693 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
694 },
695 [ C(OP_WRITE) ] = {
696 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
697 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
698 },
699 [ C(OP_PREFETCH) ] = {
700 [ C(RESULT_ACCESS) ] = 0x0,
701 [ C(RESULT_MISS) ] = 0x0,
702 },
703 },
704 [ C(ITLB) ] = {
705 [ C(OP_READ) ] = {
706 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
707 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
708 },
709 [ C(OP_WRITE) ] = {
710 [ C(RESULT_ACCESS) ] = -1,
711 [ C(RESULT_MISS) ] = -1,
712 },
713 [ C(OP_PREFETCH) ] = {
714 [ C(RESULT_ACCESS) ] = -1,
715 [ C(RESULT_MISS) ] = -1,
716 },
717 },
718 [ C(BPU ) ] = {
719 [ C(OP_READ) ] = {
720 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
721 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
722 },
723 [ C(OP_WRITE) ] = {
724 [ C(RESULT_ACCESS) ] = -1,
725 [ C(RESULT_MISS) ] = -1,
726 },
727 [ C(OP_PREFETCH) ] = {
728 [ C(RESULT_ACCESS) ] = -1,
729 [ C(RESULT_MISS) ] = -1,
730 },
731 },
89d6c0b5
PZ		 732 [ C(NODE) ] = {
733 [ C(OP_READ) ] = {
734 [ C(RESULT_ACCESS) ] = 0x01b7,
735 [ C(RESULT_MISS) ] = 0x01b7,
736 },
737 [ C(OP_WRITE) ] = {
738 [ C(RESULT_ACCESS) ] = 0x01b7,
739 [ C(RESULT_MISS) ] = 0x01b7,
740 },
741 [ C(OP_PREFETCH) ] = {
742 [ C(RESULT_ACCESS) ] = 0x01b7,
743 [ C(RESULT_MISS) ] = 0x01b7,
744 },
745 },
f22f54f4
PZ		 746};
747
e994d7d2 748/*
63b6a675
PZ		 749 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
750 * See IA32 SDM Vol 3B 30.6.1.3
e994d7d2
AK		 751 */
752
63b6a675
PZ		 753#define NHM_DMND_DATA_RD (1 << 0)
754#define NHM_DMND_RFO (1 << 1)
755#define NHM_DMND_IFETCH (1 << 2)
756#define NHM_DMND_WB (1 << 3)
757#define NHM_PF_DATA_RD (1 << 4)
758#define NHM_PF_DATA_RFO (1 << 5)
759#define NHM_PF_IFETCH (1 << 6)
760#define NHM_OFFCORE_OTHER (1 << 7)
761#define NHM_UNCORE_HIT (1 << 8)
762#define NHM_OTHER_CORE_HIT_SNP (1 << 9)
763#define NHM_OTHER_CORE_HITM (1 << 10)
764 /* reserved */
765#define NHM_REMOTE_CACHE_FWD (1 << 12)
766#define NHM_REMOTE_DRAM (1 << 13)
767#define NHM_LOCAL_DRAM (1 << 14)
768#define NHM_NON_DRAM (1 << 15)
769
87e24f4b
PZ		 770#define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
771#define NHM_REMOTE (NHM_REMOTE_DRAM)
63b6a675
PZ		 772
773#define NHM_DMND_READ (NHM_DMND_DATA_RD)
774#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
775#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
776
777#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
87e24f4b 778#define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
63b6a675 779#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
e994d7d2
AK		 780
781static __initconst const u64 nehalem_hw_cache_extra_regs
782 [PERF_COUNT_HW_CACHE_MAX]
783 [PERF_COUNT_HW_CACHE_OP_MAX]
784 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
785{
786 [ C(LL ) ] = {
787 [ C(OP_READ) ] = {
63b6a675
PZ		 788 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
789 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
e994d7d2
AK		 790 },
791 [ C(OP_WRITE) ] = {
63b6a675
PZ		 792 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
793 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
e994d7d2
AK		 794 },
795 [ C(OP_PREFETCH) ] = {
63b6a675
PZ		 796 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
797 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
e994d7d2 798 },
89d6c0b5
PZ		 799 },
800 [ C(NODE) ] = {
801 [ C(OP_READ) ] = {
87e24f4b
PZ		 802 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
803 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
89d6c0b5
PZ		 804 },
805 [ C(OP_WRITE) ] = {
87e24f4b
PZ		 806 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
807 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
89d6c0b5
PZ		 808 },
809 [ C(OP_PREFETCH) ] = {
87e24f4b
PZ		 810 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
811 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
89d6c0b5
PZ		 812 },
813 },
e994d7d2
AK		 814};
815
caaa8be3 816static __initconst const u64 nehalem_hw_cache_event_ids
f22f54f4
PZ		 817 [PERF_COUNT_HW_CACHE_MAX]
818 [PERF_COUNT_HW_CACHE_OP_MAX]
819 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
820{
821 [ C(L1D) ] = {
822 [ C(OP_READ) ] = {
f4929bd3
PZ		 823 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
824 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
f22f54f4
PZ		 825 },
826 [ C(OP_WRITE) ] = {
f4929bd3
PZ		 827 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
828 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
f22f54f4
PZ		 829 },
830 [ C(OP_PREFETCH) ] = {
831 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
832 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
833 },
834 },
835 [ C(L1I ) ] = {
836 [ C(OP_READ) ] = {
837 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
838 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
839 },
840 [ C(OP_WRITE) ] = {
841 [ C(RESULT_ACCESS) ] = -1,
842 [ C(RESULT_MISS) ] = -1,
843 },
844 [ C(OP_PREFETCH) ] = {
845 [ C(RESULT_ACCESS) ] = 0x0,
846 [ C(RESULT_MISS) ] = 0x0,
847 },
848 },
849 [ C(LL ) ] = {
850 [ C(OP_READ) ] = {
e994d7d2
AK		 851 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
852 [ C(RESULT_ACCESS) ] = 0x01b7,
853 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
854 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 855 },
e994d7d2
AK		 856 /*
857 * Use RFO, not WRITEBACK, because a write miss would typically occur
858 * on RFO.
859 */
f22f54f4 860 [ C(OP_WRITE) ] = {
e994d7d2
AK		 861 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
862 [ C(RESULT_ACCESS) ] = 0x01b7,
863 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
864 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 865 },
866 [ C(OP_PREFETCH) ] = {
e994d7d2
AK		 867 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
868 [ C(RESULT_ACCESS) ] = 0x01b7,
869 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
870 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 871 },
872 },
873 [ C(DTLB) ] = {
874 [ C(OP_READ) ] = {
875 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
876 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
877 },
878 [ C(OP_WRITE) ] = {
879 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
880 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
881 },
882 [ C(OP_PREFETCH) ] = {
883 [ C(RESULT_ACCESS) ] = 0x0,
884 [ C(RESULT_MISS) ] = 0x0,
885 },
886 },
887 [ C(ITLB) ] = {
888 [ C(OP_READ) ] = {
889 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
890 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
891 },
892 [ C(OP_WRITE) ] = {
893 [ C(RESULT_ACCESS) ] = -1,
894 [ C(RESULT_MISS) ] = -1,
895 },
896 [ C(OP_PREFETCH) ] = {
897 [ C(RESULT_ACCESS) ] = -1,
898 [ C(RESULT_MISS) ] = -1,
899 },
900 },
901 [ C(BPU ) ] = {
902 [ C(OP_READ) ] = {
903 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
904 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
905 },
906 [ C(OP_WRITE) ] = {
907 [ C(RESULT_ACCESS) ] = -1,
908 [ C(RESULT_MISS) ] = -1,
909 },
910 [ C(OP_PREFETCH) ] = {
911 [ C(RESULT_ACCESS) ] = -1,
912 [ C(RESULT_MISS) ] = -1,
913 },
914 },
89d6c0b5
PZ		 915 [ C(NODE) ] = {
916 [ C(OP_READ) ] = {
917 [ C(RESULT_ACCESS) ] = 0x01b7,
918 [ C(RESULT_MISS) ] = 0x01b7,
919 },
920 [ C(OP_WRITE) ] = {
921 [ C(RESULT_ACCESS) ] = 0x01b7,
922 [ C(RESULT_MISS) ] = 0x01b7,
923 },
924 [ C(OP_PREFETCH) ] = {
925 [ C(RESULT_ACCESS) ] = 0x01b7,
926 [ C(RESULT_MISS) ] = 0x01b7,
927 },
928 },
f22f54f4
PZ		 929};
930
caaa8be3 931static __initconst const u64 core2_hw_cache_event_ids
f22f54f4
PZ		 932 [PERF_COUNT_HW_CACHE_MAX]
933 [PERF_COUNT_HW_CACHE_OP_MAX]
934 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
935{
936 [ C(L1D) ] = {
937 [ C(OP_READ) ] = {
938 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
939 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
940 },
941 [ C(OP_WRITE) ] = {
942 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
943 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
944 },
945 [ C(OP_PREFETCH) ] = {
946 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
947 [ C(RESULT_MISS) ] = 0,
948 },
949 },
950 [ C(L1I ) ] = {
951 [ C(OP_READ) ] = {
952 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
953 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
954 },
955 [ C(OP_WRITE) ] = {
956 [ C(RESULT_ACCESS) ] = -1,
957 [ C(RESULT_MISS) ] = -1,
958 },
959 [ C(OP_PREFETCH) ] = {
960 [ C(RESULT_ACCESS) ] = 0,
961 [ C(RESULT_MISS) ] = 0,
962 },
963 },
964 [ C(LL ) ] = {
965 [ C(OP_READ) ] = {
966 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
967 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
968 },
969 [ C(OP_WRITE) ] = {
970 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
971 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
972 },
973 [ C(OP_PREFETCH) ] = {
974 [ C(RESULT_ACCESS) ] = 0,
975 [ C(RESULT_MISS) ] = 0,
976 },
977 },
978 [ C(DTLB) ] = {
979 [ C(OP_READ) ] = {
980 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
981 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
982 },
983 [ C(OP_WRITE) ] = {
984 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
985 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
986 },
987 [ C(OP_PREFETCH) ] = {
988 [ C(RESULT_ACCESS) ] = 0,
989 [ C(RESULT_MISS) ] = 0,
990 },
991 },
992 [ C(ITLB) ] = {
993 [ C(OP_READ) ] = {
994 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
995 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
996 },
997 [ C(OP_WRITE) ] = {
998 [ C(RESULT_ACCESS) ] = -1,
999 [ C(RESULT_MISS) ] = -1,
1000 },
1001 [ C(OP_PREFETCH) ] = {
1002 [ C(RESULT_ACCESS) ] = -1,
1003 [ C(RESULT_MISS) ] = -1,
1004 },
1005 },
1006 [ C(BPU ) ] = {
1007 [ C(OP_READ) ] = {
1008 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1009 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1010 },
1011 [ C(OP_WRITE) ] = {
1012 [ C(RESULT_ACCESS) ] = -1,
1013 [ C(RESULT_MISS) ] = -1,
1014 },
1015 [ C(OP_PREFETCH) ] = {
1016 [ C(RESULT_ACCESS) ] = -1,
1017 [ C(RESULT_MISS) ] = -1,
1018 },
1019 },
1020};
1021
caaa8be3 1022static __initconst const u64 atom_hw_cache_event_ids
f22f54f4
PZ		 1023 [PERF_COUNT_HW_CACHE_MAX]
1024 [PERF_COUNT_HW_CACHE_OP_MAX]
1025 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1026{
1027 [ C(L1D) ] = {
1028 [ C(OP_READ) ] = {
1029 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1030 [ C(RESULT_MISS) ] = 0,
1031 },
1032 [ C(OP_WRITE) ] = {
1033 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1034 [ C(RESULT_MISS) ] = 0,
1035 },
1036 [ C(OP_PREFETCH) ] = {
1037 [ C(RESULT_ACCESS) ] = 0x0,
1038 [ C(RESULT_MISS) ] = 0,
1039 },
1040 },
1041 [ C(L1I ) ] = {
1042 [ C(OP_READ) ] = {
1043 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1044 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1045 },
1046 [ C(OP_WRITE) ] = {
1047 [ C(RESULT_ACCESS) ] = -1,
1048 [ C(RESULT_MISS) ] = -1,
1049 },
1050 [ C(OP_PREFETCH) ] = {
1051 [ C(RESULT_ACCESS) ] = 0,
1052 [ C(RESULT_MISS) ] = 0,
1053 },
1054 },
1055 [ C(LL ) ] = {
1056 [ C(OP_READ) ] = {
1057 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1058 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1059 },
1060 [ C(OP_WRITE) ] = {
1061 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1062 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1063 },
1064 [ C(OP_PREFETCH) ] = {
1065 [ C(RESULT_ACCESS) ] = 0,
1066 [ C(RESULT_MISS) ] = 0,
1067 },
1068 },
1069 [ C(DTLB) ] = {
1070 [ C(OP_READ) ] = {
1071 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1072 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1073 },
1074 [ C(OP_WRITE) ] = {
1075 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1076 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1077 },
1078 [ C(OP_PREFETCH) ] = {
1079 [ C(RESULT_ACCESS) ] = 0,
1080 [ C(RESULT_MISS) ] = 0,
1081 },
1082 },
1083 [ C(ITLB) ] = {
1084 [ C(OP_READ) ] = {
1085 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1086 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1087 },
1088 [ C(OP_WRITE) ] = {
1089 [ C(RESULT_ACCESS) ] = -1,
1090 [ C(RESULT_MISS) ] = -1,
1091 },
1092 [ C(OP_PREFETCH) ] = {
1093 [ C(RESULT_ACCESS) ] = -1,
1094 [ C(RESULT_MISS) ] = -1,
1095 },
1096 },
1097 [ C(BPU ) ] = {
1098 [ C(OP_READ) ] = {
1099 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1100 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1101 },
1102 [ C(OP_WRITE) ] = {
1103 [ C(RESULT_ACCESS) ] = -1,
1104 [ C(RESULT_MISS) ] = -1,
1105 },
1106 [ C(OP_PREFETCH) ] = {
1107 [ C(RESULT_ACCESS) ] = -1,
1108 [ C(RESULT_MISS) ] = -1,
1109 },
1110 },
1111};
1112
1fa64180
YZ		 1113static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1114{
1115 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
06c939c1
PZ		 1116 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1117 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x768005ffffull, RSP_1),
1fa64180
YZ		 1118 EVENT_EXTRA_END
1119};
1120
1121#define SLM_DMND_READ SNB_DMND_DATA_RD
1122#define SLM_DMND_WRITE SNB_DMND_RFO
1123#define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1124
1125#define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1126#define SLM_LLC_ACCESS SNB_RESP_ANY
1127#define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1128
1129static __initconst const u64 slm_hw_cache_extra_regs
1130 [PERF_COUNT_HW_CACHE_MAX]
1131 [PERF_COUNT_HW_CACHE_OP_MAX]
1132 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1133{
1134 [ C(LL ) ] = {
1135 [ C(OP_READ) ] = {
1136 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
6d374056 1137 [ C(RESULT_MISS) ] = 0,
1fa64180
YZ		 1138 },
1139 [ C(OP_WRITE) ] = {
1140 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1141 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1142 },
1143 [ C(OP_PREFETCH) ] = {
1144 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1145 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1146 },
1147 },
1148};
1149
1150static __initconst const u64 slm_hw_cache_event_ids
1151 [PERF_COUNT_HW_CACHE_MAX]
1152 [PERF_COUNT_HW_CACHE_OP_MAX]
1153 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1154{
1155 [ C(L1D) ] = {
1156 [ C(OP_READ) ] = {
1157 [ C(RESULT_ACCESS) ] = 0,
1158 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1159 },
1160 [ C(OP_WRITE) ] = {
1161 [ C(RESULT_ACCESS) ] = 0,
1162 [ C(RESULT_MISS) ] = 0,
1163 },
1164 [ C(OP_PREFETCH) ] = {
1165 [ C(RESULT_ACCESS) ] = 0,
1166 [ C(RESULT_MISS) ] = 0,
1167 },
1168 },
1169 [ C(L1I ) ] = {
1170 [ C(OP_READ) ] = {
1171 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1172 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1173 },
1174 [ C(OP_WRITE) ] = {
1175 [ C(RESULT_ACCESS) ] = -1,
1176 [ C(RESULT_MISS) ] = -1,
1177 },
1178 [ C(OP_PREFETCH) ] = {
1179 [ C(RESULT_ACCESS) ] = 0,
1180 [ C(RESULT_MISS) ] = 0,
1181 },
1182 },
1183 [ C(LL ) ] = {
1184 [ C(OP_READ) ] = {
1185 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1186 [ C(RESULT_ACCESS) ] = 0x01b7,
6d374056 1187 [ C(RESULT_MISS) ] = 0,
1fa64180
YZ		 1188 },
1189 [ C(OP_WRITE) ] = {
1190 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1191 [ C(RESULT_ACCESS) ] = 0x01b7,
1192 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1193 [ C(RESULT_MISS) ] = 0x01b7,
1194 },
1195 [ C(OP_PREFETCH) ] = {
1196 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1197 [ C(RESULT_ACCESS) ] = 0x01b7,
1198 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1199 [ C(RESULT_MISS) ] = 0x01b7,
1200 },
1201 },
1202 [ C(DTLB) ] = {
1203 [ C(OP_READ) ] = {
1204 [ C(RESULT_ACCESS) ] = 0,
1205 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1206 },
1207 [ C(OP_WRITE) ] = {
1208 [ C(RESULT_ACCESS) ] = 0,
1209 [ C(RESULT_MISS) ] = 0,
1210 },
1211 [ C(OP_PREFETCH) ] = {
1212 [ C(RESULT_ACCESS) ] = 0,
1213 [ C(RESULT_MISS) ] = 0,
1214 },
1215 },
1216 [ C(ITLB) ] = {
1217 [ C(OP_READ) ] = {
1218 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
6d374056 1219 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1fa64180
YZ		 1220 },
1221 [ C(OP_WRITE) ] = {
1222 [ C(RESULT_ACCESS) ] = -1,
1223 [ C(RESULT_MISS) ] = -1,
1224 },
1225 [ C(OP_PREFETCH) ] = {
1226 [ C(RESULT_ACCESS) ] = -1,
1227 [ C(RESULT_MISS) ] = -1,
1228 },
1229 },
1230 [ C(BPU ) ] = {
1231 [ C(OP_READ) ] = {
1232 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1233 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1234 },
1235 [ C(OP_WRITE) ] = {
1236 [ C(RESULT_ACCESS) ] = -1,
1237 [ C(RESULT_MISS) ] = -1,
1238 },
1239 [ C(OP_PREFETCH) ] = {
1240 [ C(RESULT_ACCESS) ] = -1,
1241 [ C(RESULT_MISS) ] = -1,
1242 },
1243 },
1244};
1245
1a78d937
AK		 1246/*
1247 * Use from PMIs where the LBRs are already disabled.
1248 */
1249static void __intel_pmu_disable_all(void)
f22f54f4 1250{
89cbc767 1251 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
f22f54f4
PZ		 1252
1253 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1254
15c7ad51 1255 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
f22f54f4 1256 intel_pmu_disable_bts();
8062382c
AS		 1257 else
1258 intel_bts_disable_local();
ca037701
PZ		 1259
1260 intel_pmu_pebs_disable_all();
1a78d937
AK		 1261}
1262
1263static void intel_pmu_disable_all(void)
1264{
1265 __intel_pmu_disable_all();
caff2bef 1266 intel_pmu_lbr_disable_all();
f22f54f4
PZ		 1267}
1268
1a78d937 1269static void __intel_pmu_enable_all(int added, bool pmi)
f22f54f4 1270{
89cbc767 1271 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
f22f54f4 1272
d329527e 1273 intel_pmu_pebs_enable_all();
1a78d937 1274 intel_pmu_lbr_enable_all(pmi);
144d31e6
GN		 1275 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1276 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
f22f54f4 1277
15c7ad51 1278 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
f22f54f4 1279 struct perf_event *event =
15c7ad51 1280 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
f22f54f4
PZ		 1281
1282 if (WARN_ON_ONCE(!event))
1283 return;
1284
1285 intel_pmu_enable_bts(event->hw.config);
8062382c
AS		 1286 } else
1287 intel_bts_enable_local();
f22f54f4
PZ		 1288}
1289
1a78d937
AK		 1290static void intel_pmu_enable_all(int added)
1291{
1292 __intel_pmu_enable_all(added, false);
1293}
1294
11164cd4
PZ		 1295/*
1296 * Workaround for:
1297 * Intel Errata AAK100 (model 26)
1298 * Intel Errata AAP53 (model 30)
40b91cd1 1299 * Intel Errata BD53 (model 44)
11164cd4 1300 *
351af072
ZY		 1301 * The official story:
1302 * These chips need to be 'reset' when adding counters by programming the
1303 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
1304 * in sequence on the same PMC or on different PMCs.
1305 *
1306 * In practise it appears some of these events do in fact count, and
1307 * we need to programm all 4 events.
11164cd4 1308 */
351af072 1309static void intel_pmu_nhm_workaround(void)
11164cd4 1310{
89cbc767 1311 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
351af072
ZY		 1312 static const unsigned long nhm_magic[4] = {
1313 0x4300B5,
1314 0x4300D2,
1315 0x4300B1,
1316 0x4300B1
1317 };
1318 struct perf_event *event;
1319 int i;
11164cd4 1320
351af072
ZY		 1321 /*
1322 * The Errata requires below steps:
1323 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
1324 * 2) Configure 4 PERFEVTSELx with the magic events and clear
1325 * the corresponding PMCx;
1326 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
1327 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
1328 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
1329 */
11164cd4 1330
351af072
ZY		 1331 /*
1332 * The real steps we choose are a little different from above.
1333 * A) To reduce MSR operations, we don't run step 1) as they
1334 * are already cleared before this function is called;
1335 * B) Call x86_perf_event_update to save PMCx before configuring
1336 * PERFEVTSELx with magic number;
1337 * C) With step 5), we do clear only when the PERFEVTSELx is
1338 * not used currently.
1339 * D) Call x86_perf_event_set_period to restore PMCx;
1340 */
11164cd4 1341
351af072
ZY		 1342 /* We always operate 4 pairs of PERF Counters */
1343 for (i = 0; i < 4; i++) {
1344 event = cpuc->events[i];
1345 if (event)
1346 x86_perf_event_update(event);
1347 }
11164cd4 1348
351af072
ZY		 1349 for (i = 0; i < 4; i++) {
1350 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
1351 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
1352 }
1353
1354 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
1355 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
11164cd4 1356
351af072
ZY		 1357 for (i = 0; i < 4; i++) {
1358 event = cpuc->events[i];
1359
1360 if (event) {
1361 x86_perf_event_set_period(event);
31fa58af 1362 __x86_pmu_enable_event(&event->hw,
351af072
ZY		 1363 ARCH_PERFMON_EVENTSEL_ENABLE);
1364 } else
1365 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
11164cd4 1366 }
351af072
ZY		 1367}
1368
1369static void intel_pmu_nhm_enable_all(int added)
1370{
1371 if (added)
1372 intel_pmu_nhm_workaround();
11164cd4
PZ		 1373 intel_pmu_enable_all(added);
1374}
1375
f22f54f4
PZ		 1376static inline u64 intel_pmu_get_status(void)
1377{
1378 u64 status;
1379
1380 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1381
1382 return status;
1383}
1384
1385static inline void intel_pmu_ack_status(u64 ack)
1386{
1387 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1388}
1389
ca037701 1390static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
f22f54f4 1391{
15c7ad51 1392 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4
PZ		 1393 u64 ctrl_val, mask;
1394
1395 mask = 0xfULL << (idx * 4);
1396
1397 rdmsrl(hwc->config_base, ctrl_val);
1398 ctrl_val &= ~mask;
7645a24c 1399 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1400}
1401
2b9e344d
PZ		 1402static inline bool event_is_checkpointed(struct perf_event *event)
1403{
1404 return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
1405}
1406
ca037701 1407static void intel_pmu_disable_event(struct perf_event *event)
f22f54f4 1408{
aff3d91a 1409 struct hw_perf_event *hwc = &event->hw;
89cbc767 1410 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
aff3d91a 1411
15c7ad51 1412 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
f22f54f4
PZ		 1413 intel_pmu_disable_bts();
1414 intel_pmu_drain_bts_buffer();
1415 return;
1416 }
1417
144d31e6
GN		 1418 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1419 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
2b9e344d 1420 cpuc->intel_cp_status &= ~(1ull << hwc->idx);
144d31e6 1421
60ce0fbd
SE		 1422 /*
1423 * must disable before any actual event
1424 * because any event may be combined with LBR
1425 */
a46a2300 1426 if (needs_branch_stack(event))
60ce0fbd
SE		 1427 intel_pmu_lbr_disable(event);
1428
f22f54f4 1429 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1430 intel_pmu_disable_fixed(hwc);
f22f54f4
PZ		 1431 return;
1432 }
1433
aff3d91a 1434 x86_pmu_disable_event(event);
ca037701 1435
ab608344 1436 if (unlikely(event->attr.precise_ip))
ef21f683 1437 intel_pmu_pebs_disable(event);
f22f54f4
PZ		 1438}
1439
ca037701 1440static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
f22f54f4 1441{
15c7ad51 1442 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4 1443 u64 ctrl_val, bits, mask;
f22f54f4
PZ		 1444
1445 /*
1446 * Enable IRQ generation (0x8),
1447 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1448 * if requested:
1449 */
1450 bits = 0x8ULL;
1451 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1452 bits |= 0x2;
1453 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1454 bits |= 0x1;
1455
1456 /*
1457 * ANY bit is supported in v3 and up
1458 */
1459 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1460 bits |= 0x4;
1461
1462 bits <<= (idx * 4);
1463 mask = 0xfULL << (idx * 4);
1464
1465 rdmsrl(hwc->config_base, ctrl_val);
1466 ctrl_val &= ~mask;
1467 ctrl_val |= bits;
7645a24c 1468 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1469}
1470
aff3d91a 1471static void intel_pmu_enable_event(struct perf_event *event)
f22f54f4 1472{
aff3d91a 1473 struct hw_perf_event *hwc = &event->hw;
89cbc767 1474 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
aff3d91a 1475
15c7ad51 1476 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
0a3aee0d 1477 if (!__this_cpu_read(cpu_hw_events.enabled))
f22f54f4
PZ		 1478 return;
1479
1480 intel_pmu_enable_bts(hwc->config);
1481 return;
1482 }
60ce0fbd
SE		 1483 /*
1484 * must enabled before any actual event
1485 * because any event may be combined with LBR
1486 */
a46a2300 1487 if (needs_branch_stack(event))
60ce0fbd 1488 intel_pmu_lbr_enable(event);
f22f54f4 1489
144d31e6
GN		 1490 if (event->attr.exclude_host)
1491 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1492 if (event->attr.exclude_guest)
1493 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1494
2b9e344d
PZ		 1495 if (unlikely(event_is_checkpointed(event)))
1496 cpuc->intel_cp_status |= (1ull << hwc->idx);
1497
f22f54f4 1498 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1499 intel_pmu_enable_fixed(hwc);
f22f54f4
PZ		 1500 return;
1501 }
1502
ab608344 1503 if (unlikely(event->attr.precise_ip))
ef21f683 1504 intel_pmu_pebs_enable(event);
ca037701 1505
31fa58af 1506 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
f22f54f4
PZ		 1507}
1508
1509/*
1510 * Save and restart an expired event. Called by NMI contexts,
1511 * so it has to be careful about preempting normal event ops:
1512 */
de0428a7 1513int intel_pmu_save_and_restart(struct perf_event *event)
f22f54f4 1514{
cc2ad4ba 1515 x86_perf_event_update(event);
2dbf0116
AK		 1516 /*
1517 * For a checkpointed counter always reset back to 0. This
1518 * avoids a situation where the counter overflows, aborts the
1519 * transaction and is then set back to shortly before the
1520 * overflow, and overflows and aborts again.
1521 */
1522 if (unlikely(event_is_checkpointed(event))) {
1523 /* No race with NMIs because the counter should not be armed */
1524 wrmsrl(event->hw.event_base, 0);
1525 local64_set(&event->hw.prev_count, 0);
1526 }
cc2ad4ba 1527 return x86_perf_event_set_period(event);
f22f54f4
PZ		 1528}
1529
1530static void intel_pmu_reset(void)
1531{
0a3aee0d 1532 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
f22f54f4
PZ		 1533 unsigned long flags;
1534 int idx;
1535
948b1bb8 1536 if (!x86_pmu.num_counters)
f22f54f4
PZ		 1537 return;
1538
1539 local_irq_save(flags);
1540
c767a54b 1541 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
f22f54f4 1542
948b1bb8 1543 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
715c85b1
PA		 1544 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
1545 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
f22f54f4 1546 }
948b1bb8 1547 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
715c85b1 1548 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
948b1bb8 1549
f22f54f4
PZ		 1550 if (ds)
1551 ds->bts_index = ds->bts_buffer_base;
1552
8882edf7
AK		 1553 /* Ack all overflows and disable fixed counters */
1554 if (x86_pmu.version >= 2) {
1555 intel_pmu_ack_status(intel_pmu_get_status());
1556 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1557 }
1558
1559 /* Reset LBRs and LBR freezing */
1560 if (x86_pmu.lbr_nr) {
1561 update_debugctlmsr(get_debugctlmsr() &
1562 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
1563 }
1564
f22f54f4
PZ		 1565 local_irq_restore(flags);
1566}
1567
1568/*
1569 * This handler is triggered by the local APIC, so the APIC IRQ handling
1570 * rules apply:
1571 */
1572static int intel_pmu_handle_irq(struct pt_regs *regs)
1573{
1574 struct perf_sample_data data;
1575 struct cpu_hw_events *cpuc;
1576 int bit, loops;
2e556b5b 1577 u64 status;
b0b2072d 1578 int handled;
f22f54f4 1579
89cbc767 1580 cpuc = this_cpu_ptr(&cpu_hw_events);
f22f54f4 1581
2bce5dac 1582 /*
72db5596
AK		 1583 * No known reason to not always do late ACK,
1584 * but just in case do it opt-in.
2bce5dac 1585 */
72db5596
AK		 1586 if (!x86_pmu.late_ack)
1587 apic_write(APIC_LVTPC, APIC_DM_NMI);
1a78d937 1588 __intel_pmu_disable_all();
b0b2072d 1589 handled = intel_pmu_drain_bts_buffer();
8062382c 1590 handled += intel_bts_interrupt();
f22f54f4 1591 status = intel_pmu_get_status();
a3ef2229
MM		 1592 if (!status)
1593 goto done;
f22f54f4
PZ		 1594
1595 loops = 0;
1596again:
2e556b5b 1597 intel_pmu_ack_status(status);
f22f54f4 1598 if (++loops > 100) {
ae0def05
DH		 1599 static bool warned = false;
1600 if (!warned) {
1601 WARN(1, "perfevents: irq loop stuck!\n");
1602 perf_event_print_debug();
1603 warned = true;
1604 }
f22f54f4 1605 intel_pmu_reset();
3fb2b8dd 1606 goto done;
f22f54f4
PZ		 1607 }
1608
1609 inc_irq_stat(apic_perf_irqs);
ca037701 1610
caff2bef
PZ		 1611 intel_pmu_lbr_read();
1612
b292d7a1
HD		 1613 /*
1614 * CondChgd bit 63 doesn't mean any overflow status. Ignore
1615 * and clear the bit.
1616 */
1617 if (__test_and_clear_bit(63, (unsigned long *)&status)) {
1618 if (!status)
1619 goto done;
1620 }
1621
ca037701
PZ		 1622 /*
1623 * PEBS overflow sets bit 62 in the global status register
1624 */
de725dec
PZ		 1625 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1626 handled++;
ca037701 1627 x86_pmu.drain_pebs(regs);
de725dec 1628 }
ca037701 1629
52ca9ced
AS		 1630 /*
1631 * Intel PT
1632 */
1633 if (__test_and_clear_bit(55, (unsigned long *)&status)) {
1634 handled++;
1635 intel_pt_interrupt();
1636 }
1637
2dbf0116 1638 /*
2b9e344d
PZ		 1639 * Checkpointed counters can lead to 'spurious' PMIs because the
1640 * rollback caused by the PMI will have cleared the overflow status
1641 * bit. Therefore always force probe these counters.
2dbf0116 1642 */
2b9e344d 1643 status |= cpuc->intel_cp_status;
2dbf0116 1644
984b3f57 1645 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
f22f54f4
PZ		 1646 struct perf_event *event = cpuc->events[bit];
1647
de725dec
PZ		 1648 handled++;
1649
f22f54f4
PZ		 1650 if (!test_bit(bit, cpuc->active_mask))
1651 continue;
1652
1653 if (!intel_pmu_save_and_restart(event))
1654 continue;
1655
fd0d000b 1656 perf_sample_data_init(&data, 0, event->hw.last_period);
f22f54f4 1657
60ce0fbd
SE		 1658 if (has_branch_stack(event))
1659 data.br_stack = &cpuc->lbr_stack;
1660
a8b0ca17 1661 if (perf_event_overflow(event, &data, regs))
a4eaf7f1 1662 x86_pmu_stop(event, 0);
f22f54f4
PZ		 1663 }
1664
f22f54f4
PZ		 1665 /*
1666 * Repeat if there is more work to be done:
1667 */
1668 status = intel_pmu_get_status();
1669 if (status)
1670 goto again;
1671
3fb2b8dd 1672done:
1a78d937 1673 __intel_pmu_enable_all(0, true);
72db5596
AK		 1674 /*
1675 * Only unmask the NMI after the overflow counters
1676 * have been reset. This avoids spurious NMIs on
1677 * Haswell CPUs.
1678 */
1679 if (x86_pmu.late_ack)
1680 apic_write(APIC_LVTPC, APIC_DM_NMI);
de725dec 1681 return handled;
f22f54f4
PZ		 1682}
1683
f22f54f4 1684static struct event_constraint *
ca037701 1685intel_bts_constraints(struct perf_event *event)
f22f54f4 1686{
ca037701
PZ		 1687 struct hw_perf_event *hwc = &event->hw;
1688 unsigned int hw_event, bts_event;
f22f54f4 1689
18a073a3
PZ		 1690 if (event->attr.freq)
1691 return NULL;
1692
ca037701
PZ		 1693 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1694 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
f22f54f4 1695
ca037701 1696 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
f22f54f4 1697 return &bts_constraint;
ca037701 1698
f22f54f4
PZ		 1699 return NULL;
1700}
1701
5a425294 1702static int intel_alt_er(int idx)
b79e8941 1703{
9a5e3fb5 1704 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
5a425294 1705 return idx;
b79e8941 1706
5a425294
PZ		 1707 if (idx == EXTRA_REG_RSP_0)
1708 return EXTRA_REG_RSP_1;
1709
1710 if (idx == EXTRA_REG_RSP_1)
1711 return EXTRA_REG_RSP_0;
1712
1713 return idx;
1714}
1715
1716static void intel_fixup_er(struct perf_event *event, int idx)
1717{
1718 event->hw.extra_reg.idx = idx;
1719
1720 if (idx == EXTRA_REG_RSP_0) {
b79e8941 1721 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
53ad0447 1722 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
b79e8941 1723 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
5a425294
PZ		 1724 } else if (idx == EXTRA_REG_RSP_1) {
1725 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
53ad0447 1726 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
5a425294 1727 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
b79e8941 1728 }
b79e8941
PZ		 1729}
1730
efc9f05d
SE		 1731/*
1732 * manage allocation of shared extra msr for certain events
1733 *
1734 * sharing can be:
1735 * per-cpu: to be shared between the various events on a single PMU
1736 * per-core: per-cpu + shared by HT threads
1737 */
a7e3ed1e 1738static struct event_constraint *
efc9f05d 1739__intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
b36817e8
SE		 1740 struct perf_event *event,
1741 struct hw_perf_event_extra *reg)
a7e3ed1e 1742{
efc9f05d 1743 struct event_constraint *c = &emptyconstraint;
a7e3ed1e 1744 struct er_account *era;
cd8a38d3 1745 unsigned long flags;
5a425294 1746 int idx = reg->idx;
a7e3ed1e 1747
5a425294
PZ		 1748 /*
1749 * reg->alloc can be set due to existing state, so for fake cpuc we
1750 * need to ignore this, otherwise we might fail to allocate proper fake
1751 * state for this extra reg constraint. Also see the comment below.
1752 */
1753 if (reg->alloc && !cpuc->is_fake)
b36817e8 1754 return NULL; /* call x86_get_event_constraint() */
a7e3ed1e 1755
b79e8941 1756again:
5a425294 1757 era = &cpuc->shared_regs->regs[idx];
cd8a38d3
SE		 1758 /*
1759 * we use spin_lock_irqsave() to avoid lockdep issues when
1760 * passing a fake cpuc
1761 */
1762 raw_spin_lock_irqsave(&era->lock, flags);
efc9f05d
SE		 1763
1764 if (!atomic_read(&era->ref) || era->config == reg->config) {
1765
5a425294
PZ		 1766 /*
1767 * If its a fake cpuc -- as per validate_{group,event}() we
1768 * shouldn't touch event state and we can avoid doing so
1769 * since both will only call get_event_constraints() once
1770 * on each event, this avoids the need for reg->alloc.
1771 *
1772 * Not doing the ER fixup will only result in era->reg being
1773 * wrong, but since we won't actually try and program hardware
1774 * this isn't a problem either.
1775 */
1776 if (!cpuc->is_fake) {
1777 if (idx != reg->idx)
1778 intel_fixup_er(event, idx);
1779
1780 /*
1781 * x86_schedule_events() can call get_event_constraints()
1782 * multiple times on events in the case of incremental
1783 * scheduling(). reg->alloc ensures we only do the ER
1784 * allocation once.
1785 */
1786 reg->alloc = 1;
1787 }
1788
efc9f05d
SE		 1789 /* lock in msr value */
1790 era->config = reg->config;
1791 era->reg = reg->reg;
1792
1793 /* one more user */
1794 atomic_inc(&era->ref);
1795
a7e3ed1e 1796 /*
b36817e8
SE		 1797 * need to call x86_get_event_constraint()
1798 * to check if associated event has constraints
a7e3ed1e 1799 */
b36817e8 1800 c = NULL;
5a425294
PZ		 1801 } else {
1802 idx = intel_alt_er(idx);
1803 if (idx != reg->idx) {
1804 raw_spin_unlock_irqrestore(&era->lock, flags);
1805 goto again;
1806 }
a7e3ed1e 1807 }
cd8a38d3 1808 raw_spin_unlock_irqrestore(&era->lock, flags);
a7e3ed1e 1809
efc9f05d
SE		 1810 return c;
1811}
1812
1813static void
1814__intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
1815 struct hw_perf_event_extra *reg)
1816{
1817 struct er_account *era;
1818
1819 /*
5a425294
PZ		 1820 * Only put constraint if extra reg was actually allocated. Also takes
1821 * care of event which do not use an extra shared reg.
1822 *
1823 * Also, if this is a fake cpuc we shouldn't touch any event state
1824 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
1825 * either since it'll be thrown out.
efc9f05d 1826 */
5a425294 1827 if (!reg->alloc || cpuc->is_fake)
efc9f05d
SE		 1828 return;
1829
1830 era = &cpuc->shared_regs->regs[reg->idx];
1831
1832 /* one fewer user */
1833 atomic_dec(&era->ref);
1834
1835 /* allocate again next time */
1836 reg->alloc = 0;
1837}
1838
1839static struct event_constraint *
1840intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
1841 struct perf_event *event)
1842{
b36817e8
SE		 1843 struct event_constraint *c = NULL, *d;
1844 struct hw_perf_event_extra *xreg, *breg;
1845
1846 xreg = &event->hw.extra_reg;
1847 if (xreg->idx != EXTRA_REG_NONE) {
1848 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
1849 if (c == &emptyconstraint)
1850 return c;
1851 }
1852 breg = &event->hw.branch_reg;
1853 if (breg->idx != EXTRA_REG_NONE) {
1854 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
1855 if (d == &emptyconstraint) {
1856 __intel_shared_reg_put_constraints(cpuc, xreg);
1857 c = d;
1858 }
1859 }
efc9f05d 1860 return c;
a7e3ed1e
AK		 1861}
1862
de0428a7 1863struct event_constraint *
79cba822
SE		 1864x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
1865 struct perf_event *event)
de0428a7
KW		 1866{
1867 struct event_constraint *c;
1868
1869 if (x86_pmu.event_constraints) {
1870 for_each_event_constraint(c, x86_pmu.event_constraints) {
9fac2cf3 1871 if ((event->hw.config & c->cmask) == c->code) {
9fac2cf3 1872 event->hw.flags |= c->flags;
de0428a7 1873 return c;
9fac2cf3 1874 }
de0428a7
KW		 1875 }
1876 }
1877
1878 return &unconstrained;
1879}
1880
f22f54f4 1881static struct event_constraint *
e979121b 1882__intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
79cba822 1883 struct perf_event *event)
f22f54f4
PZ		 1884{
1885 struct event_constraint *c;
1886
ca037701
PZ		 1887 c = intel_bts_constraints(event);
1888 if (c)
1889 return c;
1890
687805e4 1891 c = intel_shared_regs_constraints(cpuc, event);
f22f54f4
PZ		 1892 if (c)
1893 return c;
1894
687805e4 1895 c = intel_pebs_constraints(event);
a7e3ed1e
AK		 1896 if (c)
1897 return c;
1898
79cba822 1899 return x86_get_event_constraints(cpuc, idx, event);
f22f54f4
PZ		 1900}
1901
e979121b
MD		 1902static void
1903intel_start_scheduling(struct cpu_hw_events *cpuc)
1904{
1905 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1906 struct intel_excl_states *xl, *xlo;
1907 int tid = cpuc->excl_thread_id;
1908 int o_tid = 1 - tid; /* sibling thread */
1909
1910 /*
1911 * nothing needed if in group validation mode
1912 */
b37609c3 1913 if (cpuc->is_fake || !is_ht_workaround_enabled())
e979121b 1914 return;
b37609c3 1915
e979121b
MD		 1916 /*
1917 * no exclusion needed
1918 */
1919 if (!excl_cntrs)
1920 return;
1921
1922 xlo = &excl_cntrs->states[o_tid];
1923 xl = &excl_cntrs->states[tid];
1924
1925 xl->sched_started = true;
e979121b
MD		 1926 /*
1927 * lock shared state until we are done scheduling
1928 * in stop_event_scheduling()
1929 * makes scheduling appear as a transaction
1930 */
1931 WARN_ON_ONCE(!irqs_disabled());
1932 raw_spin_lock(&excl_cntrs->lock);
1933
1934 /*
1935 * save initial state of sibling thread
1936 */
1937 memcpy(xlo->init_state, xlo->state, sizeof(xlo->init_state));
1938}
1939
1940static void
1941intel_stop_scheduling(struct cpu_hw_events *cpuc)
1942{
1943 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1944 struct intel_excl_states *xl, *xlo;
1945 int tid = cpuc->excl_thread_id;
1946 int o_tid = 1 - tid; /* sibling thread */
1947
1948 /*
1949 * nothing needed if in group validation mode
1950 */
b37609c3 1951 if (cpuc->is_fake || !is_ht_workaround_enabled())
e979121b
MD		 1952 return;
1953 /*
1954 * no exclusion needed
1955 */
1956 if (!excl_cntrs)
1957 return;
1958
1959 xlo = &excl_cntrs->states[o_tid];
1960 xl = &excl_cntrs->states[tid];
1961
1962 /*
1963 * make new sibling thread state visible
1964 */
1965 memcpy(xlo->state, xlo->init_state, sizeof(xlo->state));
1966
1967 xl->sched_started = false;
1968 /*
1969 * release shared state lock (acquired in intel_start_scheduling())
1970 */
1971 raw_spin_unlock(&excl_cntrs->lock);
1972}
1973
1974static struct event_constraint *
1975intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
1976 int idx, struct event_constraint *c)
1977{
1978 struct event_constraint *cx;
1979 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1980 struct intel_excl_states *xl, *xlo;
1981 int is_excl, i;
1982 int tid = cpuc->excl_thread_id;
1983 int o_tid = 1 - tid; /* alternate */
1984
1985 /*
1986 * validating a group does not require
1987 * enforcing cross-thread exclusion
1988 */
b37609c3
SE		 1989 if (cpuc->is_fake || !is_ht_workaround_enabled())
1990 return c;
1991
1992 /*
1993 * no exclusion needed
1994 */
1995 if (!excl_cntrs)
e979121b 1996 return c;
e979121b
MD		 1997 /*
1998 * event requires exclusive counter access
1999 * across HT threads
2000 */
2001 is_excl = c->flags & PERF_X86_EVENT_EXCL;
cc1790cf
PZ		 2002 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
2003 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
2004 if (!cpuc->n_excl++)
2005 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
2006 }
e979121b
MD		 2007
2008 /*
2009 * xl = state of current HT
2010 * xlo = state of sibling HT
2011 */
2012 xl = &excl_cntrs->states[tid];
2013 xlo = &excl_cntrs->states[o_tid];
2014
2015 cx = c;
2016
2017 /*
2018 * because we modify the constraint, we need
2019 * to make a copy. Static constraints come
2020 * from static const tables.
2021 *
2022 * only needed when constraint has not yet
2023 * been cloned (marked dynamic)
2024 */
2025 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
2026
2027 /* sanity check */
2028 if (idx < 0)
2029 return &emptyconstraint;
2030
2031 /*
2032 * grab pre-allocated constraint entry
2033 */
2034 cx = &cpuc->constraint_list[idx];
2035
2036 /*
2037 * initialize dynamic constraint
2038 * with static constraint
2039 */
2040 memcpy(cx, c, sizeof(*cx));
2041
2042 /*
2043 * mark constraint as dynamic, so we
2044 * can free it later on
2045 */
2046 cx->flags |= PERF_X86_EVENT_DYNAMIC;
2047 }
2048
2049 /*
2050 * From here on, the constraint is dynamic.
2051 * Either it was just allocated above, or it
2052 * was allocated during a earlier invocation
2053 * of this function
2054 */
2055
2056 /*
2057 * Modify static constraint with current dynamic
2058 * state of thread
2059 *
2060 * EXCLUSIVE: sibling counter measuring exclusive event
2061 * SHARED : sibling counter measuring non-exclusive event
2062 * UNUSED : sibling counter unused
2063 */
2064 for_each_set_bit(i, cx->idxmsk, X86_PMC_IDX_MAX) {
2065 /*
2066 * exclusive event in sibling counter
2067 * our corresponding counter cannot be used
2068 * regardless of our event
2069 */
2070 if (xl->state[i] == INTEL_EXCL_EXCLUSIVE)
2071 __clear_bit(i, cx->idxmsk);
2072 /*
2073 * if measuring an exclusive event, sibling
2074 * measuring non-exclusive, then counter cannot
2075 * be used
2076 */
2077 if (is_excl && xl->state[i] == INTEL_EXCL_SHARED)
2078 __clear_bit(i, cx->idxmsk);
2079 }
2080
2081 /*
2082 * recompute actual bit weight for scheduling algorithm
2083 */
2084 cx->weight = hweight64(cx->idxmsk64);
2085
2086 /*
2087 * if we return an empty mask, then switch
2088 * back to static empty constraint to avoid
2089 * the cost of freeing later on
2090 */
2091 if (cx->weight == 0)
2092 cx = &emptyconstraint;
2093
2094 return cx;
2095}
2096
2097static struct event_constraint *
2098intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2099 struct perf_event *event)
2100{
b371b594 2101 struct event_constraint *c1 = cpuc->event_constraint[idx];
a90738c2 2102 struct event_constraint *c2;
e979121b
MD		 2103
2104 /*
2105 * first time only
2106 * - static constraint: no change across incremental scheduling calls
2107 * - dynamic constraint: handled by intel_get_excl_constraints()
2108 */
a90738c2
SE		 2109 c2 = __intel_get_event_constraints(cpuc, idx, event);
2110 if (c1 && (c1->flags & PERF_X86_EVENT_DYNAMIC)) {
2111 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
2112 c1->weight = c2->weight;
2113 c2 = c1;
2114 }
e979121b
MD		 2115
2116 if (cpuc->excl_cntrs)
a90738c2 2117 return intel_get_excl_constraints(cpuc, event, idx, c2);
e979121b 2118
a90738c2 2119 return c2;
e979121b
MD		 2120}
2121
2122static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
2123 struct perf_event *event)
2124{
2125 struct hw_perf_event *hwc = &event->hw;
2126 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2127 struct intel_excl_states *xlo, *xl;
2128 unsigned long flags = 0; /* keep compiler happy */
2129 int tid = cpuc->excl_thread_id;
2130 int o_tid = 1 - tid;
2131
2132 /*
2133 * nothing needed if in group validation mode
2134 */
2135 if (cpuc->is_fake)
2136 return;
2137
2138 WARN_ON_ONCE(!excl_cntrs);
2139
2140 if (!excl_cntrs)
2141 return;
2142
2143 xl = &excl_cntrs->states[tid];
2144 xlo = &excl_cntrs->states[o_tid];
cc1790cf
PZ		 2145 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
2146 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
2147 if (!--cpuc->n_excl)
2148 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
2149 }
e979121b
MD		 2150
2151 /*
2152 * put_constraint may be called from x86_schedule_events()
2153 * which already has the lock held so here make locking
2154 * conditional
2155 */
2156 if (!xl->sched_started)
2157 raw_spin_lock_irqsave(&excl_cntrs->lock, flags);
2158
2159 /*
2160 * if event was actually assigned, then mark the
2161 * counter state as unused now
2162 */
2163 if (hwc->idx >= 0)
2164 xlo->state[hwc->idx] = INTEL_EXCL_UNUSED;
2165
2166 if (!xl->sched_started)
2167 raw_spin_unlock_irqrestore(&excl_cntrs->lock, flags);
2168}
2169
efc9f05d
SE		 2170static void
2171intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
a7e3ed1e
AK		 2172 struct perf_event *event)
2173{
efc9f05d 2174 struct hw_perf_event_extra *reg;
a7e3ed1e 2175
efc9f05d
SE		 2176 reg = &event->hw.extra_reg;
2177 if (reg->idx != EXTRA_REG_NONE)
2178 __intel_shared_reg_put_constraints(cpuc, reg);
b36817e8
SE		 2179
2180 reg = &event->hw.branch_reg;
2181 if (reg->idx != EXTRA_REG_NONE)
2182 __intel_shared_reg_put_constraints(cpuc, reg);
efc9f05d 2183}
a7e3ed1e 2184
efc9f05d
SE		 2185static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
2186 struct perf_event *event)
2187{
2188 intel_put_shared_regs_event_constraints(cpuc, event);
e979121b
MD		 2189
2190 /*
2191 * is PMU has exclusive counter restrictions, then
2192 * all events are subject to and must call the
2193 * put_excl_constraints() routine
2194 */
b371b594 2195 if (cpuc->excl_cntrs)
e979121b 2196 intel_put_excl_constraints(cpuc, event);
e979121b
MD		 2197}
2198
b371b594 2199static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
e979121b
MD		 2200{
2201 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
b371b594 2202 struct event_constraint *c = cpuc->event_constraint[idx];
e979121b
MD		 2203 struct intel_excl_states *xlo, *xl;
2204 int tid = cpuc->excl_thread_id;
2205 int o_tid = 1 - tid;
2206 int is_excl;
2207
2208 if (cpuc->is_fake || !c)
2209 return;
2210
2211 is_excl = c->flags & PERF_X86_EVENT_EXCL;
2212
2213 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
2214 return;
2215
2216 WARN_ON_ONCE(!excl_cntrs);
2217
2218 if (!excl_cntrs)
2219 return;
2220
2221 xl = &excl_cntrs->states[tid];
2222 xlo = &excl_cntrs->states[o_tid];
2223
2224 WARN_ON_ONCE(!raw_spin_is_locked(&excl_cntrs->lock));
2225
2226 if (cntr >= 0) {
2227 if (is_excl)
2228 xlo->init_state[cntr] = INTEL_EXCL_EXCLUSIVE;
2229 else
2230 xlo->init_state[cntr] = INTEL_EXCL_SHARED;
2231 }
a7e3ed1e
AK		 2232}
2233
0780c927 2234static void intel_pebs_aliases_core2(struct perf_event *event)
b4cdc5c2 2235{
0780c927 2236 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
7639dae0
PZ		 2237 /*
2238 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2239 * (0x003c) so that we can use it with PEBS.
2240 *
2241 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2242 * PEBS capable. However we can use INST_RETIRED.ANY_P
2243 * (0x00c0), which is a PEBS capable event, to get the same
2244 * count.
2245 *
2246 * INST_RETIRED.ANY_P counts the number of cycles that retires
2247 * CNTMASK instructions. By setting CNTMASK to a value (16)
2248 * larger than the maximum number of instructions that can be
2249 * retired per cycle (4) and then inverting the condition, we
2250 * count all cycles that retire 16 or less instructions, which
2251 * is every cycle.
2252 *
2253 * Thereby we gain a PEBS capable cycle counter.
2254 */
f9b4eeb8
PZ		 2255 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
2256
0780c927
PZ		 2257 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2258 event->hw.config = alt_config;
2259 }
2260}
2261
2262static void intel_pebs_aliases_snb(struct perf_event *event)
2263{
2264 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2265 /*
2266 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2267 * (0x003c) so that we can use it with PEBS.
2268 *
2269 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2270 * PEBS capable. However we can use UOPS_RETIRED.ALL
2271 * (0x01c2), which is a PEBS capable event, to get the same
2272 * count.
2273 *
2274 * UOPS_RETIRED.ALL counts the number of cycles that retires
2275 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
2276 * larger than the maximum number of micro-ops that can be
2277 * retired per cycle (4) and then inverting the condition, we
2278 * count all cycles that retire 16 or less micro-ops, which
2279 * is every cycle.
2280 *
2281 * Thereby we gain a PEBS capable cycle counter.
2282 */
2283 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
7639dae0
PZ		 2284
2285 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2286 event->hw.config = alt_config;
2287 }
0780c927
PZ		 2288}
2289
2290static int intel_pmu_hw_config(struct perf_event *event)
2291{
2292 int ret = x86_pmu_hw_config(event);
2293
2294 if (ret)
2295 return ret;
2296
2297 if (event->attr.precise_ip && x86_pmu.pebs_aliases)
2298 x86_pmu.pebs_aliases(event);
7639dae0 2299
a46a2300 2300 if (needs_branch_stack(event)) {
60ce0fbd
SE		 2301 ret = intel_pmu_setup_lbr_filter(event);
2302 if (ret)
2303 return ret;
48070342
AS		 2304
2305 /*
2306 * BTS is set up earlier in this path, so don't account twice
2307 */
2308 if (!intel_pmu_has_bts(event)) {
2309 /* disallow lbr if conflicting events are present */
2310 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
2311 return -EBUSY;
2312
2313 event->destroy = hw_perf_lbr_event_destroy;
2314 }
60ce0fbd
SE		 2315 }
2316
b4cdc5c2
PZ		 2317 if (event->attr.type != PERF_TYPE_RAW)
2318 return 0;
2319
2320 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
2321 return 0;
2322
2323 if (x86_pmu.version < 3)
2324 return -EINVAL;
2325
2326 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
2327 return -EACCES;
2328
2329 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
2330
2331 return 0;
2332}
2333
144d31e6
GN		 2334struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
2335{
2336 if (x86_pmu.guest_get_msrs)
2337 return x86_pmu.guest_get_msrs(nr);
2338 *nr = 0;
2339 return NULL;
2340}
2341EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
2342
2343static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
2344{
89cbc767 2345 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 2346 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2347
2348 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
2349 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
2350 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
26a4f3c0
GN		 2351 /*
2352 * If PMU counter has PEBS enabled it is not enough to disable counter
2353 * on a guest entry since PEBS memory write can overshoot guest entry
2354 * and corrupt guest memory. Disabling PEBS solves the problem.
2355 */
2356 arr[1].msr = MSR_IA32_PEBS_ENABLE;
2357 arr[1].host = cpuc->pebs_enabled;
2358 arr[1].guest = 0;
144d31e6 2359
26a4f3c0 2360 *nr = 2;
144d31e6
GN		 2361 return arr;
2362}
2363
2364static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
2365{
89cbc767 2366 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 2367 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2368 int idx;
2369
2370 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2371 struct perf_event *event = cpuc->events[idx];
2372
2373 arr[idx].msr = x86_pmu_config_addr(idx);
2374 arr[idx].host = arr[idx].guest = 0;
2375
2376 if (!test_bit(idx, cpuc->active_mask))
2377 continue;
2378
2379 arr[idx].host = arr[idx].guest =
2380 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
2381
2382 if (event->attr.exclude_host)
2383 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2384 else if (event->attr.exclude_guest)
2385 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2386 }
2387
2388 *nr = x86_pmu.num_counters;
2389 return arr;
2390}
2391
2392static void core_pmu_enable_event(struct perf_event *event)
2393{
2394 if (!event->attr.exclude_host)
2395 x86_pmu_enable_event(event);
2396}
2397
2398static void core_pmu_enable_all(int added)
2399{
89cbc767 2400 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 2401 int idx;
2402
2403 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2404 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
2405
2406 if (!test_bit(idx, cpuc->active_mask) ||
2407 cpuc->events[idx]->attr.exclude_host)
2408 continue;
2409
2410 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2411 }
2412}
2413
3a632cb2
AK		 2414static int hsw_hw_config(struct perf_event *event)
2415{
2416 int ret = intel_pmu_hw_config(event);
2417
2418 if (ret)
2419 return ret;
2420 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
2421 return 0;
2422 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
2423
2424 /*
2425 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
2426 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
2427 * this combination.
2428 */
2429 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
2430 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
2431 event->attr.precise_ip > 0))
2432 return -EOPNOTSUPP;
2433
2dbf0116
AK		 2434 if (event_is_checkpointed(event)) {
2435 /*
2436 * Sampling of checkpointed events can cause situations where
2437 * the CPU constantly aborts because of a overflow, which is
2438 * then checkpointed back and ignored. Forbid checkpointing
2439 * for sampling.
2440 *
2441 * But still allow a long sampling period, so that perf stat
2442 * from KVM works.
2443 */
2444 if (event->attr.sample_period > 0 &&
2445 event->attr.sample_period < 0x7fffffff)
2446 return -EOPNOTSUPP;
2447 }
3a632cb2
AK		 2448 return 0;
2449}
2450
2451static struct event_constraint counter2_constraint =
2452 EVENT_CONSTRAINT(0, 0x4, 0);
2453
2454static struct event_constraint *
79cba822
SE		 2455hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2456 struct perf_event *event)
3a632cb2 2457{
79cba822
SE		 2458 struct event_constraint *c;
2459
2460 c = intel_get_event_constraints(cpuc, idx, event);
3a632cb2
AK		 2461
2462 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
2463 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
2464 if (c->idxmsk64 & (1U << 2))
2465 return &counter2_constraint;
2466 return &emptyconstraint;
2467 }
2468
2469 return c;
2470}
2471
294fe0f5
AK		 2472/*
2473 * Broadwell:
2474 *
2475 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
2476 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
2477 * the two to enforce a minimum period of 128 (the smallest value that has bits
2478 * 0-5 cleared and >= 100).
2479 *
2480 * Because of how the code in x86_perf_event_set_period() works, the truncation
2481 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
2482 * to make up for the 'lost' events due to carrying the 'error' in period_left.
2483 *
2484 * Therefore the effective (average) period matches the requested period,
2485 * despite coarser hardware granularity.
2486 */
2487static unsigned bdw_limit_period(struct perf_event *event, unsigned left)
2488{
2489 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
2490 X86_CONFIG(.event=0xc0, .umask=0x01)) {
2491 if (left < 128)
2492 left = 128;
2493 left &= ~0x3fu;
2494 }
2495 return left;
2496}
2497
641cc938
JO		 2498PMU_FORMAT_ATTR(event, "config:0-7" );
2499PMU_FORMAT_ATTR(umask, "config:8-15" );
2500PMU_FORMAT_ATTR(edge, "config:18" );
2501PMU_FORMAT_ATTR(pc, "config:19" );
2502PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
2503PMU_FORMAT_ATTR(inv, "config:23" );
2504PMU_FORMAT_ATTR(cmask, "config:24-31" );
3a632cb2
AK		 2505PMU_FORMAT_ATTR(in_tx, "config:32");
2506PMU_FORMAT_ATTR(in_tx_cp, "config:33");
641cc938
JO		 2507
2508static struct attribute *intel_arch_formats_attr[] = {
2509 &format_attr_event.attr,
2510 &format_attr_umask.attr,
2511 &format_attr_edge.attr,
2512 &format_attr_pc.attr,
2513 &format_attr_inv.attr,
2514 &format_attr_cmask.attr,
2515 NULL,
2516};
2517
0bf79d44
JO		 2518ssize_t intel_event_sysfs_show(char *page, u64 config)
2519{
2520 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
2521
2522 return x86_event_sysfs_show(page, config, event);
2523}
2524
de0428a7 2525struct intel_shared_regs *allocate_shared_regs(int cpu)
efc9f05d
SE		 2526{
2527 struct intel_shared_regs *regs;
2528 int i;
2529
2530 regs = kzalloc_node(sizeof(struct intel_shared_regs),
2531 GFP_KERNEL, cpu_to_node(cpu));
2532 if (regs) {
2533 /*
2534 * initialize the locks to keep lockdep happy
2535 */
2536 for (i = 0; i < EXTRA_REG_MAX; i++)
2537 raw_spin_lock_init(&regs->regs[i].lock);
2538
2539 regs->core_id = -1;
2540 }
2541 return regs;
2542}
2543
6f6539ca
MD		 2544static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
2545{
2546 struct intel_excl_cntrs *c;
2547 int i;
2548
2549 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
2550 GFP_KERNEL, cpu_to_node(cpu));
2551 if (c) {
2552 raw_spin_lock_init(&c->lock);
2553 for (i = 0; i < X86_PMC_IDX_MAX; i++) {
2554 c->states[0].state[i] = INTEL_EXCL_UNUSED;
2555 c->states[0].init_state[i] = INTEL_EXCL_UNUSED;
2556
2557 c->states[1].state[i] = INTEL_EXCL_UNUSED;
2558 c->states[1].init_state[i] = INTEL_EXCL_UNUSED;
2559 }
2560 c->core_id = -1;
2561 }
2562 return c;
2563}
2564
a7e3ed1e
AK		 2565static int intel_pmu_cpu_prepare(int cpu)
2566{
2567 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2568
6f6539ca
MD		 2569 if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
2570 cpuc->shared_regs = allocate_shared_regs(cpu);
2571 if (!cpuc->shared_regs)
2572 return NOTIFY_BAD;
2573 }
69092624 2574
6f6539ca
MD		 2575 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
2576 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
2577
2578 cpuc->constraint_list = kzalloc(sz, GFP_KERNEL);
2579 if (!cpuc->constraint_list)
2580 return NOTIFY_BAD;
2581
2582 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
2583 if (!cpuc->excl_cntrs) {
2584 kfree(cpuc->constraint_list);
2585 kfree(cpuc->shared_regs);
2586 return NOTIFY_BAD;
2587 }
2588 cpuc->excl_thread_id = 0;
2589 }
a7e3ed1e 2590
a7e3ed1e
AK		 2591 return NOTIFY_OK;
2592}
2593
74846d35
PZ		 2594static void intel_pmu_cpu_starting(int cpu)
2595{
a7e3ed1e
AK		 2596 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2597 int core_id = topology_core_id(cpu);
2598 int i;
2599
69092624
LM		 2600 init_debug_store_on_cpu(cpu);
2601 /*
2602 * Deal with CPUs that don't clear their LBRs on power-up.
2603 */
2604 intel_pmu_lbr_reset();
2605
b36817e8
SE		 2606 cpuc->lbr_sel = NULL;
2607
2608 if (!cpuc->shared_regs)
69092624
LM		 2609 return;
2610
9a5e3fb5 2611 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
90413464
SE		 2612 void **onln = &cpuc->kfree_on_online[X86_PERF_KFREE_SHARED];
2613
b36817e8
SE		 2614 for_each_cpu(i, topology_thread_cpumask(cpu)) {
2615 struct intel_shared_regs *pc;
a7e3ed1e 2616
b36817e8
SE		 2617 pc = per_cpu(cpu_hw_events, i).shared_regs;
2618 if (pc && pc->core_id == core_id) {
90413464 2619 *onln = cpuc->shared_regs;
b36817e8
SE		 2620 cpuc->shared_regs = pc;
2621 break;
2622 }
a7e3ed1e 2623 }
b36817e8
SE		 2624 cpuc->shared_regs->core_id = core_id;
2625 cpuc->shared_regs->refcnt++;
a7e3ed1e
AK		 2626 }
2627
b36817e8
SE		 2628 if (x86_pmu.lbr_sel_map)
2629 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
6f6539ca
MD		 2630
2631 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
2632 for_each_cpu(i, topology_thread_cpumask(cpu)) {
2633 struct intel_excl_cntrs *c;
2634
2635 c = per_cpu(cpu_hw_events, i).excl_cntrs;
2636 if (c && c->core_id == core_id) {
2637 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
2638 cpuc->excl_cntrs = c;
2639 cpuc->excl_thread_id = 1;
2640 break;
2641 }
2642 }
2643 cpuc->excl_cntrs->core_id = core_id;
2644 cpuc->excl_cntrs->refcnt++;
2645 }
74846d35
PZ		 2646}
2647
b37609c3 2648static void free_excl_cntrs(int cpu)
74846d35 2649{
a7e3ed1e 2650 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
6f6539ca 2651 struct intel_excl_cntrs *c;
a7e3ed1e 2652
6f6539ca
MD		 2653 c = cpuc->excl_cntrs;
2654 if (c) {
2655 if (c->core_id == -1 || --c->refcnt == 0)
2656 kfree(c);
2657 cpuc->excl_cntrs = NULL;
2658 kfree(cpuc->constraint_list);
2659 cpuc->constraint_list = NULL;
2660 }
b37609c3 2661}
a7e3ed1e 2662
b37609c3
SE		 2663static void intel_pmu_cpu_dying(int cpu)
2664{
2665 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2666 struct intel_shared_regs *pc;
2667
2668 pc = cpuc->shared_regs;
2669 if (pc) {
2670 if (pc->core_id == -1 || --pc->refcnt == 0)
2671 kfree(pc);
2672 cpuc->shared_regs = NULL;
e979121b
MD		 2673 }
2674
b37609c3
SE		 2675 free_excl_cntrs(cpu);
2676
74846d35
PZ		 2677 fini_debug_store_on_cpu(cpu);
2678}
2679
641cc938
JO		 2680PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
2681
a63fcab4
SE		 2682PMU_FORMAT_ATTR(ldlat, "config1:0-15");
2683
641cc938
JO		 2684static struct attribute *intel_arch3_formats_attr[] = {
2685 &format_attr_event.attr,
2686 &format_attr_umask.attr,
2687 &format_attr_edge.attr,
2688 &format_attr_pc.attr,
2689 &format_attr_any.attr,
2690 &format_attr_inv.attr,
2691 &format_attr_cmask.attr,
3a632cb2
AK		 2692 &format_attr_in_tx.attr,
2693 &format_attr_in_tx_cp.attr,
641cc938
JO		 2694
2695 &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
a63fcab4 2696 &format_attr_ldlat.attr, /* PEBS load latency */
641cc938
JO		 2697 NULL,
2698};
2699
3b6e0421
JO		 2700static __initconst const struct x86_pmu core_pmu = {
2701 .name = "core",
2702 .handle_irq = x86_pmu_handle_irq,
2703 .disable_all = x86_pmu_disable_all,
2704 .enable_all = core_pmu_enable_all,
2705 .enable = core_pmu_enable_event,
2706 .disable = x86_pmu_disable_event,
2707 .hw_config = x86_pmu_hw_config,
2708 .schedule_events = x86_schedule_events,
2709 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
2710 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
2711 .event_map = intel_pmu_event_map,
2712 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
2713 .apic = 1,
2714 /*
2715 * Intel PMCs cannot be accessed sanely above 32-bit width,
2716 * so we install an artificial 1<<31 period regardless of
2717 * the generic event period:
2718 */
2719 .max_period = (1ULL<<31) - 1,
2720 .get_event_constraints = intel_get_event_constraints,
2721 .put_event_constraints = intel_put_event_constraints,
2722 .event_constraints = intel_core_event_constraints,
2723 .guest_get_msrs = core_guest_get_msrs,
2724 .format_attrs = intel_arch_formats_attr,
2725 .events_sysfs_show = intel_event_sysfs_show,
2726
2727 /*
2728 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
2729 * together with PMU version 1 and thus be using core_pmu with
2730 * shared_regs. We need following callbacks here to allocate
2731 * it properly.
2732 */
2733 .cpu_prepare = intel_pmu_cpu_prepare,
2734 .cpu_starting = intel_pmu_cpu_starting,
2735 .cpu_dying = intel_pmu_cpu_dying,
2736};
2737
caaa8be3 2738static __initconst const struct x86_pmu intel_pmu = {
f22f54f4
PZ		 2739 .name = "Intel",
2740 .handle_irq = intel_pmu_handle_irq,
2741 .disable_all = intel_pmu_disable_all,
2742 .enable_all = intel_pmu_enable_all,
2743 .enable = intel_pmu_enable_event,
2744 .disable = intel_pmu_disable_event,
b4cdc5c2 2745 .hw_config = intel_pmu_hw_config,
a072738e 2746 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 2747 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
2748 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
2749 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 2750 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
2751 .apic = 1,
2752 /*
2753 * Intel PMCs cannot be accessed sanely above 32 bit width,
2754 * so we install an artificial 1<<31 period regardless of
2755 * the generic event period:
2756 */
2757 .max_period = (1ULL << 31) - 1,
3f6da390 2758 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 2759 .put_event_constraints = intel_put_event_constraints,
0780c927 2760 .pebs_aliases = intel_pebs_aliases_core2,
3f6da390 2761
641cc938 2762 .format_attrs = intel_arch3_formats_attr,
0bf79d44 2763 .events_sysfs_show = intel_event_sysfs_show,
641cc938 2764
a7e3ed1e 2765 .cpu_prepare = intel_pmu_cpu_prepare,
74846d35
PZ		 2766 .cpu_starting = intel_pmu_cpu_starting,
2767 .cpu_dying = intel_pmu_cpu_dying,
144d31e6 2768 .guest_get_msrs = intel_guest_get_msrs,
2a0ad3b3 2769 .sched_task = intel_pmu_lbr_sched_task,
f22f54f4
PZ		 2770};
2771
c1d6f42f 2772static __init void intel_clovertown_quirk(void)
3c44780b
PZ		 2773{
2774 /*
2775 * PEBS is unreliable due to:
2776 *
2777 * AJ67 - PEBS may experience CPL leaks
2778 * AJ68 - PEBS PMI may be delayed by one event
2779 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
2780 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
2781 *
2782 * AJ67 could be worked around by restricting the OS/USR flags.
2783 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
2784 *
2785 * AJ106 could possibly be worked around by not allowing LBR
2786 * usage from PEBS, including the fixup.
2787 * AJ68 could possibly be worked around by always programming
ec75a716 2788 * a pebs_event_reset[0] value and coping with the lost events.
3c44780b
PZ		 2789 *
2790 * But taken together it might just make sense to not enable PEBS on
2791 * these chips.
2792 */
c767a54b 2793 pr_warn("PEBS disabled due to CPU errata\n");
3c44780b
PZ		 2794 x86_pmu.pebs = 0;
2795 x86_pmu.pebs_constraints = NULL;
2796}
2797
c93dc84c
PZ		 2798static int intel_snb_pebs_broken(int cpu)
2799{
2800 u32 rev = UINT_MAX; /* default to broken for unknown models */
2801
2802 switch (cpu_data(cpu).x86_model) {
2803 case 42: /* SNB */
2804 rev = 0x28;
2805 break;
2806
2807 case 45: /* SNB-EP */
2808 switch (cpu_data(cpu).x86_mask) {
2809 case 6: rev = 0x618; break;
2810 case 7: rev = 0x70c; break;
2811 }
2812 }
2813
2814 return (cpu_data(cpu).microcode < rev);
2815}
2816
2817static void intel_snb_check_microcode(void)
2818{
2819 int pebs_broken = 0;
2820 int cpu;
2821
2822 get_online_cpus();
2823 for_each_online_cpu(cpu) {
2824 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
2825 break;
2826 }
2827 put_online_cpus();
2828
2829 if (pebs_broken == x86_pmu.pebs_broken)
2830 return;
2831
2832 /*
2833 * Serialized by the microcode lock..
2834 */
2835 if (x86_pmu.pebs_broken) {
2836 pr_info("PEBS enabled due to microcode update\n");
2837 x86_pmu.pebs_broken = 0;
2838 } else {
2839 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
2840 x86_pmu.pebs_broken = 1;
2841 }
2842}
2843
338b522c
KL		 2844/*
2845 * Under certain circumstances, access certain MSR may cause #GP.
2846 * The function tests if the input MSR can be safely accessed.
2847 */
2848static bool check_msr(unsigned long msr, u64 mask)
2849{
2850 u64 val_old, val_new, val_tmp;
2851
2852 /*
2853 * Read the current value, change it and read it back to see if it
2854 * matches, this is needed to detect certain hardware emulators
2855 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
2856 */
2857 if (rdmsrl_safe(msr, &val_old))
2858 return false;
2859
2860 /*
2861 * Only change the bits which can be updated by wrmsrl.
2862 */
2863 val_tmp = val_old ^ mask;
2864 if (wrmsrl_safe(msr, val_tmp) ||
2865 rdmsrl_safe(msr, &val_new))
2866 return false;
2867
2868 if (val_new != val_tmp)
2869 return false;
2870
2871 /* Here it's sure that the MSR can be safely accessed.
2872 * Restore the old value and return.
2873 */
2874 wrmsrl(msr, val_old);
2875
2876 return true;
2877}
2878
c1d6f42f 2879static __init void intel_sandybridge_quirk(void)
6a600a8b 2880{
c93dc84c
PZ		 2881 x86_pmu.check_microcode = intel_snb_check_microcode;
2882 intel_snb_check_microcode();
6a600a8b
PZ		 2883}
2884
c1d6f42f
PZ		 2885static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
2886 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
2887 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
2888 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
2889 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
2890 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
2891 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
2892 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
ffb871bc
GN		 2893};
2894
c1d6f42f
PZ		 2895static __init void intel_arch_events_quirk(void)
2896{
2897 int bit;
2898
2899 /* disable event that reported as not presend by cpuid */
2900 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
2901 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
c767a54b
JP		 2902 pr_warn("CPUID marked event: \'%s\' unavailable\n",
2903 intel_arch_events_map[bit].name);
c1d6f42f
PZ		 2904 }
2905}
2906
2907static __init void intel_nehalem_quirk(void)
2908{
2909 union cpuid10_ebx ebx;
2910
2911 ebx.full = x86_pmu.events_maskl;
2912 if (ebx.split.no_branch_misses_retired) {
2913 /*
2914 * Erratum AAJ80 detected, we work it around by using
2915 * the BR_MISP_EXEC.ANY event. This will over-count
2916 * branch-misses, but it's still much better than the
2917 * architectural event which is often completely bogus:
2918 */
2919 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
2920 ebx.split.no_branch_misses_retired = 0;
2921 x86_pmu.events_maskl = ebx.full;
c767a54b 2922 pr_info("CPU erratum AAJ80 worked around\n");
c1d6f42f
PZ		 2923 }
2924}
2925
93fcf72c
MD		 2926/*
2927 * enable software workaround for errata:
2928 * SNB: BJ122
2929 * IVB: BV98
2930 * HSW: HSD29
2931 *
2932 * Only needed when HT is enabled. However detecting
b37609c3
SE		 2933 * if HT is enabled is difficult (model specific). So instead,
2934 * we enable the workaround in the early boot, and verify if
2935 * it is needed in a later initcall phase once we have valid
2936 * topology information to check if HT is actually enabled
93fcf72c
MD		 2937 */
2938static __init void intel_ht_bug(void)
2939{
b37609c3 2940 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
93fcf72c
MD		 2941
2942 x86_pmu.commit_scheduling = intel_commit_scheduling;
2943 x86_pmu.start_scheduling = intel_start_scheduling;
2944 x86_pmu.stop_scheduling = intel_stop_scheduling;
93fcf72c
MD		 2945}
2946
7f2ee91f
IM		 2947EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
2948EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
f9134f36 2949
4b2c4f1f 2950/* Haswell special events */
7f2ee91f
IM		 2951EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
2952EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
2953EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
2954EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
2955EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
2956EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
2957EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
2958EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
2959EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
2960EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
2961EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
2962EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
4b2c4f1f 2963
f9134f36 2964static struct attribute *hsw_events_attrs[] = {
4b2c4f1f
AK		 2965 EVENT_PTR(tx_start),
2966 EVENT_PTR(tx_commit),
2967 EVENT_PTR(tx_abort),
2968 EVENT_PTR(tx_capacity),
2969 EVENT_PTR(tx_conflict),
2970 EVENT_PTR(el_start),
2971 EVENT_PTR(el_commit),
2972 EVENT_PTR(el_abort),
2973 EVENT_PTR(el_capacity),
2974 EVENT_PTR(el_conflict),
2975 EVENT_PTR(cycles_t),
2976 EVENT_PTR(cycles_ct),
f9134f36
AK		 2977 EVENT_PTR(mem_ld_hsw),
2978 EVENT_PTR(mem_st_hsw),
2979 NULL
2980};
2981
de0428a7 2982__init int intel_pmu_init(void)
f22f54f4
PZ		 2983{
2984 union cpuid10_edx edx;
2985 union cpuid10_eax eax;
ffb871bc 2986 union cpuid10_ebx ebx;
a1eac7ac 2987 struct event_constraint *c;
f22f54f4 2988 unsigned int unused;
338b522c
KL		 2989 struct extra_reg *er;
2990 int version, i;
f22f54f4
PZ		 2991
2992 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
a072738e
CG		 2993 switch (boot_cpu_data.x86) {
2994 case 0x6:
2995 return p6_pmu_init();
e717bf4e
VW		 2996 case 0xb:
2997 return knc_pmu_init();
a072738e
CG		 2998 case 0xf:
2999 return p4_pmu_init();
3000 }
f22f54f4 3001 return -ENODEV;
f22f54f4
PZ		 3002 }
3003
3004 /*
3005 * Check whether the Architectural PerfMon supports
3006 * Branch Misses Retired hw_event or not.
3007 */
ffb871bc
GN		 3008 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
3009 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
f22f54f4
PZ		 3010 return -ENODEV;
3011
3012 version = eax.split.version_id;
3013 if (version < 2)
3014 x86_pmu = core_pmu;
3015 else
3016 x86_pmu = intel_pmu;
3017
3018 x86_pmu.version = version;
948b1bb8
RR		 3019 x86_pmu.num_counters = eax.split.num_counters;
3020 x86_pmu.cntval_bits = eax.split.bit_width;
3021 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
f22f54f4 3022
c1d6f42f
PZ		 3023 x86_pmu.events_maskl = ebx.full;
3024 x86_pmu.events_mask_len = eax.split.mask_length;
3025
70ab7003
AK		 3026 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
3027
f22f54f4
PZ		 3028 /*
3029 * Quirk: v2 perfmon does not report fixed-purpose events, so
3030 * assume at least 3 events:
3031 */
3032 if (version > 1)
948b1bb8 3033 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
f22f54f4 3034
c9b08884 3035 if (boot_cpu_has(X86_FEATURE_PDCM)) {
8db909a7
PZ		 3036 u64 capabilities;
3037
3038 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
3039 x86_pmu.intel_cap.capabilities = capabilities;
3040 }
3041
ca037701
PZ		 3042 intel_ds_init();
3043
c1d6f42f
PZ		 3044 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
3045
f22f54f4
PZ		 3046 /*
3047 * Install the hw-cache-events table:
3048 */
3049 switch (boot_cpu_data.x86_model) {
0f7c29ce 3050 case 14: /* 65nm Core "Yonah" */
f22f54f4
PZ		 3051 pr_cont("Core events, ");
3052 break;
3053
0f7c29ce 3054 case 15: /* 65nm Core2 "Merom" */
c1d6f42f 3055 x86_add_quirk(intel_clovertown_quirk);
0f7c29ce
PZ		 3056 case 22: /* 65nm Core2 "Merom-L" */
3057 case 23: /* 45nm Core2 "Penryn" */
3058 case 29: /* 45nm Core2 "Dunnington (MP) */
f22f54f4
PZ		 3059 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
3060 sizeof(hw_cache_event_ids));
3061
caff2bef
PZ		 3062 intel_pmu_lbr_init_core();
3063
f22f54f4 3064 x86_pmu.event_constraints = intel_core2_event_constraints;
17e31629 3065 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
f22f54f4
PZ		 3066 pr_cont("Core2 events, ");
3067 break;
3068
0f7c29ce
PZ		 3069 case 30: /* 45nm Nehalem */
3070 case 26: /* 45nm Nehalem-EP */
3071 case 46: /* 45nm Nehalem-EX */
f22f54f4
PZ		 3072 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
3073 sizeof(hw_cache_event_ids));
e994d7d2
AK		 3074 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3075 sizeof(hw_cache_extra_regs));
f22f54f4 3076
caff2bef
PZ		 3077 intel_pmu_lbr_init_nhm();
3078
f22f54f4 3079 x86_pmu.event_constraints = intel_nehalem_event_constraints;
17e31629 3080 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
11164cd4 3081 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
a7e3ed1e 3082 x86_pmu.extra_regs = intel_nehalem_extra_regs;
ec75a716 3083
f20093ee
SE		 3084 x86_pmu.cpu_events = nhm_events_attrs;
3085
91fc4cc0 3086 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 3087 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3088 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
91fc4cc0 3089 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 3090 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3091 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
94403f88 3092
c1d6f42f 3093 x86_add_quirk(intel_nehalem_quirk);
ec75a716 3094
11164cd4 3095 pr_cont("Nehalem events, ");
f22f54f4 3096 break;
caff2bef 3097
0f7c29ce
PZ		 3098 case 28: /* 45nm Atom "Pineview" */
3099 case 38: /* 45nm Atom "Lincroft" */
3100 case 39: /* 32nm Atom "Penwell" */
3101 case 53: /* 32nm Atom "Cloverview" */
3102 case 54: /* 32nm Atom "Cedarview" */
f22f54f4
PZ		 3103 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
3104 sizeof(hw_cache_event_ids));
3105
caff2bef
PZ		 3106 intel_pmu_lbr_init_atom();
3107
f22f54f4 3108 x86_pmu.event_constraints = intel_gen_event_constraints;
17e31629 3109 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
f22f54f4
PZ		 3110 pr_cont("Atom events, ");
3111 break;
3112
0f7c29ce 3113 case 55: /* 22nm Atom "Silvermont" */
ef454cae 3114 case 76: /* 14nm Atom "Airmont" */
0f7c29ce 3115 case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
1fa64180
YZ		 3116 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
3117 sizeof(hw_cache_event_ids));
3118 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
3119 sizeof(hw_cache_extra_regs));
3120
3121 intel_pmu_lbr_init_atom();
3122
3123 x86_pmu.event_constraints = intel_slm_event_constraints;
3124 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
3125 x86_pmu.extra_regs = intel_slm_extra_regs;
9a5e3fb5 3126 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
1fa64180
YZ		 3127 pr_cont("Silvermont events, ");
3128 break;
3129
0f7c29ce
PZ		 3130 case 37: /* 32nm Westmere */
3131 case 44: /* 32nm Westmere-EP */
3132 case 47: /* 32nm Westmere-EX */
f22f54f4
PZ		 3133 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
3134 sizeof(hw_cache_event_ids));
e994d7d2
AK		 3135 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3136 sizeof(hw_cache_extra_regs));
f22f54f4 3137
caff2bef
PZ		 3138 intel_pmu_lbr_init_nhm();
3139
f22f54f4 3140 x86_pmu.event_constraints = intel_westmere_event_constraints;
40b91cd1 3141 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
17e31629 3142 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
a7e3ed1e 3143 x86_pmu.extra_regs = intel_westmere_extra_regs;
9a5e3fb5 3144 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
30112039 3145
f20093ee
SE		 3146 x86_pmu.cpu_events = nhm_events_attrs;
3147
30112039 3148 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 3149 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3150 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
30112039 3151 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 3152 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3153 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
30112039 3154
f22f54f4
PZ		 3155 pr_cont("Westmere events, ");
3156 break;
b622d644 3157
0f7c29ce
PZ		 3158 case 42: /* 32nm SandyBridge */
3159 case 45: /* 32nm SandyBridge-E/EN/EP */
47a8863d 3160 x86_add_quirk(intel_sandybridge_quirk);
93fcf72c 3161 x86_add_quirk(intel_ht_bug);
b06b3d49
LM		 3162 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3163 sizeof(hw_cache_event_ids));
74e6543f
YZ		 3164 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3165 sizeof(hw_cache_extra_regs));
b06b3d49 3166
c5cc2cd9 3167 intel_pmu_lbr_init_snb();
b06b3d49
LM		 3168
3169 x86_pmu.event_constraints = intel_snb_event_constraints;
de0428a7 3170 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
0780c927 3171 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
f1923820
SE		 3172 if (boot_cpu_data.x86_model == 45)
3173 x86_pmu.extra_regs = intel_snbep_extra_regs;
3174 else
3175 x86_pmu.extra_regs = intel_snb_extra_regs;
93fcf72c
MD		 3176
3177
ee89cbc2 3178 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3179 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3180 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
e04d1b23 3181
f20093ee
SE		 3182 x86_pmu.cpu_events = snb_events_attrs;
3183
e04d1b23 3184 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
f9b4eeb8
PZ		 3185 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3186 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 3187 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
f9b4eeb8
PZ		 3188 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3189 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 3190
b06b3d49
LM		 3191 pr_cont("SandyBridge events, ");
3192 break;
0f7c29ce
PZ		 3193
3194 case 58: /* 22nm IvyBridge */
3195 case 62: /* 22nm IvyBridge-EP/EX */
93fcf72c 3196 x86_add_quirk(intel_ht_bug);
20a36e39
SE		 3197 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3198 sizeof(hw_cache_event_ids));
1996388e
VW		 3199 /* dTLB-load-misses on IVB is different than SNB */
3200 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
3201
20a36e39
SE		 3202 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3203 sizeof(hw_cache_extra_regs));
3204
3205 intel_pmu_lbr_init_snb();
3206
69943182 3207 x86_pmu.event_constraints = intel_ivb_event_constraints;
20a36e39
SE		 3208 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
3209 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
f1923820
SE		 3210 if (boot_cpu_data.x86_model == 62)
3211 x86_pmu.extra_regs = intel_snbep_extra_regs;
3212 else
3213 x86_pmu.extra_regs = intel_snb_extra_regs;
20a36e39 3214 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3215 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3216 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
20a36e39 3217
f20093ee
SE		 3218 x86_pmu.cpu_events = snb_events_attrs;
3219
20a36e39
SE		 3220 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
3221 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3222 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3223
3224 pr_cont("IvyBridge events, ");
3225 break;
3226
b06b3d49 3227
d86c8eaf
AK		 3228 case 60: /* 22nm Haswell Core */
3229 case 63: /* 22nm Haswell Server */
3230 case 69: /* 22nm Haswell ULT */
3231 case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
93fcf72c 3232 x86_add_quirk(intel_ht_bug);
72db5596 3233 x86_pmu.late_ack = true;
0f1b5ca2
AK		 3234 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3235 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3a632cb2 3236
e9d7f7cd 3237 intel_pmu_lbr_init_hsw();
3a632cb2
AK		 3238
3239 x86_pmu.event_constraints = intel_hsw_event_constraints;
3044318f 3240 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
36bbb2f2 3241 x86_pmu.extra_regs = intel_snbep_extra_regs;
3044318f 3242 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3a632cb2 3243 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3244 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3245 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3a632cb2
AK		 3246
3247 x86_pmu.hw_config = hsw_hw_config;
3248 x86_pmu.get_event_constraints = hsw_get_event_constraints;
f9134f36 3249 x86_pmu.cpu_events = hsw_events_attrs;
b7af41a1 3250 x86_pmu.lbr_double_abort = true;
3a632cb2
AK		 3251 pr_cont("Haswell events, ");
3252 break;
3253
91f1b705
AK		 3254 case 61: /* 14nm Broadwell Core-M */
3255 case 86: /* 14nm Broadwell Xeon D */
3256 x86_pmu.late_ack = true;
3257 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3258 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3259
3260 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
3261 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
3262 BDW_L3_MISS|HSW_SNOOP_DRAM;
3263 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
3264 HSW_SNOOP_DRAM;
3265 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
3266 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3267 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
3268 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3269
78d504bc 3270 intel_pmu_lbr_init_hsw();
91f1b705
AK		 3271
3272 x86_pmu.event_constraints = intel_bdw_event_constraints;
3273 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
3274 x86_pmu.extra_regs = intel_snbep_extra_regs;
3275 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3276 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3277 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3278 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
91f1b705
AK		 3279
3280 x86_pmu.hw_config = hsw_hw_config;
3281 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3282 x86_pmu.cpu_events = hsw_events_attrs;
294fe0f5 3283 x86_pmu.limit_period = bdw_limit_period;
91f1b705
AK		 3284 pr_cont("Broadwell events, ");
3285 break;
3286
f22f54f4 3287 default:
0af3ac1f
AK		 3288 switch (x86_pmu.version) {
3289 case 1:
3290 x86_pmu.event_constraints = intel_v1_event_constraints;
3291 pr_cont("generic architected perfmon v1, ");
3292 break;
3293 default:
3294 /*
3295 * default constraints for v2 and up
3296 */
3297 x86_pmu.event_constraints = intel_gen_event_constraints;
3298 pr_cont("generic architected perfmon, ");
3299 break;
3300 }
f22f54f4 3301 }
ffb871bc 3302
a1eac7ac
RR		 3303 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
3304 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
3305 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
3306 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
3307 }
3308 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
3309
3310 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
3311 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
3312 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
3313 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
3314 }
3315
3316 x86_pmu.intel_ctrl |=
3317 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
3318
3319 if (x86_pmu.event_constraints) {
3320 /*
3321 * event on fixed counter2 (REF_CYCLES) only works on this
3322 * counter, so do not extend mask to generic counters
3323 */
3324 for_each_event_constraint(c, x86_pmu.event_constraints) {
3a632cb2 3325 if (c->cmask != FIXED_EVENT_FLAGS
a1eac7ac
RR		 3326 || c->idxmsk64 == INTEL_PMC_MSK_FIXED_REF_CYCLES) {
3327 continue;
3328 }
3329
3330 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
3331 c->weight += x86_pmu.num_counters;
3332 }
3333 }
3334
338b522c
KL		 3335 /*
3336 * Access LBR MSR may cause #GP under certain circumstances.
3337 * E.g. KVM doesn't support LBR MSR
3338 * Check all LBT MSR here.
3339 * Disable LBR access if any LBR MSRs can not be accessed.
3340 */
3341 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
3342 x86_pmu.lbr_nr = 0;
3343 for (i = 0; i < x86_pmu.lbr_nr; i++) {
3344 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
3345 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
3346 x86_pmu.lbr_nr = 0;
3347 }
3348
3349 /*
3350 * Access extra MSR may cause #GP under certain circumstances.
3351 * E.g. KVM doesn't support offcore event
3352 * Check all extra_regs here.
3353 */
3354 if (x86_pmu.extra_regs) {
3355 for (er = x86_pmu.extra_regs; er->msr; er++) {
3356 er->extra_msr_access = check_msr(er->msr, 0x1ffUL);
3357 /* Disable LBR select mapping */
3358 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
3359 x86_pmu.lbr_sel_map = NULL;
3360 }
3361 }
3362
069e0c3c
AK		 3363 /* Support full width counters using alternative MSR range */
3364 if (x86_pmu.intel_cap.full_width_write) {
3365 x86_pmu.max_period = x86_pmu.cntval_mask;
3366 x86_pmu.perfctr = MSR_IA32_PMC0;
3367 pr_cont("full-width counters, ");
3368 }
3369
f22f54f4
PZ		 3370 return 0;
3371}
b37609c3
SE		 3372
3373/*
3374 * HT bug: phase 2 init
3375 * Called once we have valid topology information to check
3376 * whether or not HT is enabled
3377 * If HT is off, then we disable the workaround
3378 */
3379static __init int fixup_ht_bug(void)
3380{
3381 int cpu = smp_processor_id();
3382 int w, c;
3383 /*
3384 * problem not present on this CPU model, nothing to do
3385 */
3386 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
3387 return 0;
3388
3389 w = cpumask_weight(topology_thread_cpumask(cpu));
3390 if (w > 1) {
3391 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
3392 return 0;
3393 }
3394
3395 watchdog_nmi_disable_all();
3396
3397 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
3398
3399 x86_pmu.commit_scheduling = NULL;
3400 x86_pmu.start_scheduling = NULL;
3401 x86_pmu.stop_scheduling = NULL;
3402
3403 watchdog_nmi_enable_all();
3404
3405 get_online_cpus();
3406
3407 for_each_online_cpu(c) {
3408 free_excl_cntrs(c);
3409 }
3410
3411 put_online_cpus();
3412 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
3413 return 0;
3414}
3415subsys_initcall(fixup_ht_bug)
Linux kernel - Deliverables
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