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KVM guest: KVM Steal time registration
[deliverable/linux.git] / arch / x86 / kvm / mmu.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
9611c187 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 11 *
12 * Authors:
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
e495606d 20
af585b92 21#include "irq.h"
1d737c8a 22#include "mmu.h"
836a1b3c 23#include "x86.h"
6de4f3ad 24#include "kvm_cache_regs.h"
af585b92 25#include "x86.h"
e495606d 26
edf88417 27#include <linux/kvm_host.h>
6aa8b732
AK		 28#include <linux/types.h>
29#include <linux/string.h>
6aa8b732
AK		 30#include <linux/mm.h>
31#include <linux/highmem.h>
32#include <linux/module.h>
448353ca 33#include <linux/swap.h>
05da4558 34#include <linux/hugetlb.h>
2f333bcb 35#include <linux/compiler.h>
bc6678a3 36#include <linux/srcu.h>
5a0e3ad6 37#include <linux/slab.h>
bf998156 38#include <linux/uaccess.h>
6aa8b732 39
e495606d
AK		 40#include <asm/page.h>
41#include <asm/cmpxchg.h>
4e542370 42#include <asm/io.h>
13673a90 43#include <asm/vmx.h>
6aa8b732 44
18552672
JR		 45/*
46 * When setting this variable to true it enables Two-Dimensional-Paging
47 * where the hardware walks 2 page tables:
48 * 1. the guest-virtual to guest-physical
49 * 2. while doing 1. it walks guest-physical to host-physical
50 * If the hardware supports that we don't need to do shadow paging.
51 */
2f333bcb 52bool tdp_enabled = false;
18552672 53
8b1fe17c
XG		 54enum {
55 AUDIT_PRE_PAGE_FAULT,
56 AUDIT_POST_PAGE_FAULT,
57 AUDIT_PRE_PTE_WRITE,
6903074c
XG		 58 AUDIT_POST_PTE_WRITE,
59 AUDIT_PRE_SYNC,
60 AUDIT_POST_SYNC
8b1fe17c 61};
37a7d8b0 62
8b1fe17c
XG		 63char *audit_point_name[] = {
64 "pre page fault",
65 "post page fault",
66 "pre pte write",
6903074c
XG		 67 "post pte write",
68 "pre sync",
69 "post sync"
8b1fe17c 70};
37a7d8b0 71
8b1fe17c 72#undef MMU_DEBUG
37a7d8b0
AK		 73
74#ifdef MMU_DEBUG
75
76#define pgprintk(x...) do { if (dbg) printk(x); } while (0)
77#define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
78
79#else
80
81#define pgprintk(x...) do { } while (0)
82#define rmap_printk(x...) do { } while (0)
83
84#endif
85
8b1fe17c 86#ifdef MMU_DEBUG
6ada8cca
AK		 87static int dbg = 0;
88module_param(dbg, bool, 0644);
37a7d8b0 89#endif
6aa8b732 90
582801a9
MT		 91static int oos_shadow = 1;
92module_param(oos_shadow, bool, 0644);
93
d6c69ee9
YD		 94#ifndef MMU_DEBUG
95#define ASSERT(x) do { } while (0)
96#else
6aa8b732
AK		 97#define ASSERT(x) \
98 if (!(x)) { \
99 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
100 __FILE__, __LINE__, #x); \
101 }
d6c69ee9 102#endif
6aa8b732 103
957ed9ef
XG		 104#define PTE_PREFETCH_NUM 8
105
6aa8b732
AK		 106#define PT_FIRST_AVAIL_BITS_SHIFT 9
107#define PT64_SECOND_AVAIL_BITS_SHIFT 52
108
6aa8b732
AK		 109#define PT64_LEVEL_BITS 9
110
111#define PT64_LEVEL_SHIFT(level) \
d77c26fc 112 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
6aa8b732 113
6aa8b732
AK		 114#define PT64_INDEX(address, level)\
115 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
116
117
118#define PT32_LEVEL_BITS 10
119
120#define PT32_LEVEL_SHIFT(level) \
d77c26fc 121 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
6aa8b732 122
e04da980
JR		 123#define PT32_LVL_OFFSET_MASK(level) \
124 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
125 * PT32_LEVEL_BITS))) - 1))
6aa8b732
AK		 126
127#define PT32_INDEX(address, level)\
128 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
129
130
27aba766 131#define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
6aa8b732
AK		 132#define PT64_DIR_BASE_ADDR_MASK \
133 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
e04da980
JR		 134#define PT64_LVL_ADDR_MASK(level) \
135 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
136 * PT64_LEVEL_BITS))) - 1))
137#define PT64_LVL_OFFSET_MASK(level) \
138 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
139 * PT64_LEVEL_BITS))) - 1))
6aa8b732
AK		 140
141#define PT32_BASE_ADDR_MASK PAGE_MASK
142#define PT32_DIR_BASE_ADDR_MASK \
143 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
e04da980
JR		 144#define PT32_LVL_ADDR_MASK(level) \
145 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
146 * PT32_LEVEL_BITS))) - 1))
6aa8b732 147
79539cec
AK		 148#define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
149 | PT64_NX_MASK)
6aa8b732 150
53c07b18 151#define PTE_LIST_EXT 4
cd4a4e53 152
fe135d2c
AK		 153#define ACC_EXEC_MASK 1
154#define ACC_WRITE_MASK PT_WRITABLE_MASK
155#define ACC_USER_MASK PT_USER_MASK
156#define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
157
90bb6fc5
AK		 158#include <trace/events/kvm.h>
159
07420171
AK		 160#define CREATE_TRACE_POINTS
161#include "mmutrace.h"
162
1403283a
IE		 163#define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
164
135f8c2b
AK		 165#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
166
53c07b18
XG		 167struct pte_list_desc {
168 u64 *sptes[PTE_LIST_EXT];
169 struct pte_list_desc *more;
cd4a4e53
AK		 170};
171
2d11123a
AK		 172struct kvm_shadow_walk_iterator {
173 u64 addr;
174 hpa_t shadow_addr;
175 int level;
176 u64 *sptep;
177 unsigned index;
178};
179
180#define for_each_shadow_entry(_vcpu, _addr, _walker) \
181 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
182 shadow_walk_okay(&(_walker)); \
183 shadow_walk_next(&(_walker)))
184
53c07b18 185static struct kmem_cache *pte_list_desc_cache;
d3d25b04 186static struct kmem_cache *mmu_page_header_cache;
45221ab6 187static struct percpu_counter kvm_total_used_mmu_pages;
b5a33a75 188
c7addb90
AK		 189static u64 __read_mostly shadow_trap_nonpresent_pte;
190static u64 __read_mostly shadow_notrap_nonpresent_pte;
7b52345e
SY		 191static u64 __read_mostly shadow_nx_mask;
192static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
193static u64 __read_mostly shadow_user_mask;
194static u64 __read_mostly shadow_accessed_mask;
195static u64 __read_mostly shadow_dirty_mask;
c7addb90 196
82725b20
DE		 197static inline u64 rsvd_bits(int s, int e)
198{
199 return ((1ULL << (e - s + 1)) - 1) << s;
200}
201
c7addb90
AK		 202void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
203{
204 shadow_trap_nonpresent_pte = trap_pte;
205 shadow_notrap_nonpresent_pte = notrap_pte;
206}
207EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
208
7b52345e 209void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
4b12f0de 210 u64 dirty_mask, u64 nx_mask, u64 x_mask)
7b52345e
SY		 211{
212 shadow_user_mask = user_mask;
213 shadow_accessed_mask = accessed_mask;
214 shadow_dirty_mask = dirty_mask;
215 shadow_nx_mask = nx_mask;
216 shadow_x_mask = x_mask;
217}
218EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
219
3dbe1415 220static bool is_write_protection(struct kvm_vcpu *vcpu)
6aa8b732 221{
4d4ec087 222 return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
6aa8b732
AK		 223}
224
225static int is_cpuid_PSE36(void)
226{
227 return 1;
228}
229
73b1087e
AK		 230static int is_nx(struct kvm_vcpu *vcpu)
231{
f6801dff 232 return vcpu->arch.efer & EFER_NX;
73b1087e
AK		 233}
234
c7addb90
AK		 235static int is_shadow_present_pte(u64 pte)
236{
c7addb90
AK		 237 return pte != shadow_trap_nonpresent_pte
238 && pte != shadow_notrap_nonpresent_pte;
239}
240
05da4558
MT		 241static int is_large_pte(u64 pte)
242{
243 return pte & PT_PAGE_SIZE_MASK;
244}
245
8dae4445 246static int is_writable_pte(unsigned long pte)
6aa8b732
AK		 247{
248 return pte & PT_WRITABLE_MASK;
249}
250
43a3795a 251static int is_dirty_gpte(unsigned long pte)
e3c5e7ec 252{
439e218a 253 return pte & PT_DIRTY_MASK;
e3c5e7ec
AK		 254}
255
43a3795a 256static int is_rmap_spte(u64 pte)
cd4a4e53 257{
4b1a80fa 258 return is_shadow_present_pte(pte);
cd4a4e53
AK		 259}
260
776e6633
MT		 261static int is_last_spte(u64 pte, int level)
262{
263 if (level == PT_PAGE_TABLE_LEVEL)
264 return 1;
852e3c19 265 if (is_large_pte(pte))
776e6633
MT		 266 return 1;
267 return 0;
268}
269
35149e21 270static pfn_t spte_to_pfn(u64 pte)
0b49ea86 271{
35149e21 272 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
0b49ea86
AK		 273}
274
da928521
AK		 275static gfn_t pse36_gfn_delta(u32 gpte)
276{
277 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
278
279 return (gpte & PT32_DIR_PSE36_MASK) << shift;
280}
281
d555c333 282static void __set_spte(u64 *sptep, u64 spte)
e663ee64 283{
7645e432 284 set_64bit(sptep, spte);
e663ee64
AK		 285}
286
a9221dd5
AK		 287static u64 __xchg_spte(u64 *sptep, u64 new_spte)
288{
289#ifdef CONFIG_X86_64
290 return xchg(sptep, new_spte);
291#else
292 u64 old_spte;
293
294 do {
295 old_spte = *sptep;
296 } while (cmpxchg64(sptep, old_spte, new_spte) != old_spte);
297
298 return old_spte;
299#endif
300}
301
8672b721
XG		 302static bool spte_has_volatile_bits(u64 spte)
303{
304 if (!shadow_accessed_mask)
305 return false;
306
307 if (!is_shadow_present_pte(spte))
308 return false;
309
4132779b
XG		 310 if ((spte & shadow_accessed_mask) &&
311 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
8672b721
XG		 312 return false;
313
314 return true;
315}
316
4132779b
XG		 317static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
318{
319 return (old_spte & bit_mask) && !(new_spte & bit_mask);
320}
321
b79b93f9
AK		 322static void update_spte(u64 *sptep, u64 new_spte)
323{
4132779b
XG		 324 u64 mask, old_spte = *sptep;
325
326 WARN_ON(!is_rmap_spte(new_spte));
b79b93f9 327
4132779b
XG		 328 new_spte |= old_spte & shadow_dirty_mask;
329
330 mask = shadow_accessed_mask;
331 if (is_writable_pte(old_spte))
332 mask |= shadow_dirty_mask;
333
334 if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask)
b79b93f9 335 __set_spte(sptep, new_spte);
4132779b 336 else
b79b93f9 337 old_spte = __xchg_spte(sptep, new_spte);
4132779b
XG		 338
339 if (!shadow_accessed_mask)
340 return;
341
342 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
343 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
344 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
345 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
b79b93f9
AK		 346}
347
e2dec939 348static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
2e3e5882 349 struct kmem_cache *base_cache, int min)
714b93da
AK		 350{
351 void *obj;
352
353 if (cache->nobjs >= min)
e2dec939 354 return 0;
714b93da 355 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 356 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
714b93da 357 if (!obj)
e2dec939 358 return -ENOMEM;
714b93da
AK		 359 cache->objects[cache->nobjs++] = obj;
360 }
e2dec939 361 return 0;
714b93da
AK		 362}
363
e8ad9a70
XG		 364static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
365 struct kmem_cache *cache)
714b93da
AK		 366{
367 while (mc->nobjs)
e8ad9a70 368 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
714b93da
AK		 369}
370
c1158e63 371static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
2e3e5882 372 int min)
c1158e63 373{
842f22ed 374 void *page;
c1158e63
AK		 375
376 if (cache->nobjs >= min)
377 return 0;
378 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
842f22ed 379 page = (void *)__get_free_page(GFP_KERNEL);
c1158e63
AK		 380 if (!page)
381 return -ENOMEM;
842f22ed 382 cache->objects[cache->nobjs++] = page;
c1158e63
AK		 383 }
384 return 0;
385}
386
387static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
388{
389 while (mc->nobjs)
c4d198d5 390 free_page((unsigned long)mc->objects[--mc->nobjs]);
c1158e63
AK		 391}
392
2e3e5882 393static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
714b93da 394{
e2dec939
AK		 395 int r;
396
53c07b18 397 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
67052b35 398 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
d3d25b04
AK		 399 if (r)
400 goto out;
ad312c7c 401 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
d3d25b04
AK		 402 if (r)
403 goto out;
ad312c7c 404 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
2e3e5882 405 mmu_page_header_cache, 4);
e2dec939
AK		 406out:
407 return r;
714b93da
AK		 408}
409
410static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
411{
53c07b18
XG		 412 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
413 pte_list_desc_cache);
ad312c7c 414 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
e8ad9a70
XG		 415 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
416 mmu_page_header_cache);
714b93da
AK		 417}
418
419static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
420 size_t size)
421{
422 void *p;
423
424 BUG_ON(!mc->nobjs);
425 p = mc->objects[--mc->nobjs];
714b93da
AK		 426 return p;
427}
428
53c07b18 429static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
714b93da 430{
53c07b18
XG		 431 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache,
432 sizeof(struct pte_list_desc));
714b93da
AK		 433}
434
53c07b18 435static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
714b93da 436{
53c07b18 437 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
714b93da
AK		 438}
439
2032a93d
LJ		 440static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
441{
442 if (!sp->role.direct)
443 return sp->gfns[index];
444
445 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
446}
447
448static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
449{
450 if (sp->role.direct)
451 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
452 else
453 sp->gfns[index] = gfn;
454}
455
05da4558 456/*
d4dbf470
TY		 457 * Return the pointer to the large page information for a given gfn,
458 * handling slots that are not large page aligned.
05da4558 459 */
d4dbf470
TY		 460static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
461 struct kvm_memory_slot *slot,
462 int level)
05da4558
MT		 463{
464 unsigned long idx;
465
82855413
JR		 466 idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
467 (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
d4dbf470 468 return &slot->lpage_info[level - 2][idx];
05da4558
MT		 469}
470
471static void account_shadowed(struct kvm *kvm, gfn_t gfn)
472{
d25797b2 473 struct kvm_memory_slot *slot;
d4dbf470 474 struct kvm_lpage_info *linfo;
d25797b2 475 int i;
05da4558 476
a1f4d395 477 slot = gfn_to_memslot(kvm, gfn);
d25797b2
JR		 478 for (i = PT_DIRECTORY_LEVEL;
479 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
d4dbf470
TY		 480 linfo = lpage_info_slot(gfn, slot, i);
481 linfo->write_count += 1;
d25797b2 482 }
332b207d 483 kvm->arch.indirect_shadow_pages++;
05da4558
MT		 484}
485
486static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
487{
d25797b2 488 struct kvm_memory_slot *slot;
d4dbf470 489 struct kvm_lpage_info *linfo;
d25797b2 490 int i;
05da4558 491
a1f4d395 492 slot = gfn_to_memslot(kvm, gfn);
d25797b2
JR		 493 for (i = PT_DIRECTORY_LEVEL;
494 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
d4dbf470
TY		 495 linfo = lpage_info_slot(gfn, slot, i);
496 linfo->write_count -= 1;
497 WARN_ON(linfo->write_count < 0);
d25797b2 498 }
332b207d 499 kvm->arch.indirect_shadow_pages--;
05da4558
MT		 500}
501
d25797b2
JR		 502static int has_wrprotected_page(struct kvm *kvm,
503 gfn_t gfn,
504 int level)
05da4558 505{
2843099f 506 struct kvm_memory_slot *slot;
d4dbf470 507 struct kvm_lpage_info *linfo;
05da4558 508
a1f4d395 509 slot = gfn_to_memslot(kvm, gfn);
05da4558 510 if (slot) {
d4dbf470
TY		 511 linfo = lpage_info_slot(gfn, slot, level);
512 return linfo->write_count;
05da4558
MT		 513 }
514
515 return 1;
516}
517
d25797b2 518static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
05da4558 519{
8f0b1ab6 520 unsigned long page_size;
d25797b2 521 int i, ret = 0;
05da4558 522
8f0b1ab6 523 page_size = kvm_host_page_size(kvm, gfn);
05da4558 524
d25797b2
JR		 525 for (i = PT_PAGE_TABLE_LEVEL;
526 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
527 if (page_size >= KVM_HPAGE_SIZE(i))
528 ret = i;
529 else
530 break;
531 }
532
4c2155ce 533 return ret;
05da4558
MT		 534}
535
5d163b1c
XG		 536static struct kvm_memory_slot *
537gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
538 bool no_dirty_log)
05da4558
MT		 539{
540 struct kvm_memory_slot *slot;
5d163b1c
XG		 541
542 slot = gfn_to_memslot(vcpu->kvm, gfn);
543 if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
544 (no_dirty_log && slot->dirty_bitmap))
545 slot = NULL;
546
547 return slot;
548}
549
550static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
551{
a0a8eaba 552 return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
936a5fe6
AA		 553}
554
555static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
556{
557 int host_level, level, max_level;
05da4558 558
d25797b2
JR		 559 host_level = host_mapping_level(vcpu->kvm, large_gfn);
560
561 if (host_level == PT_PAGE_TABLE_LEVEL)
562 return host_level;
563
878403b7
SY		 564 max_level = kvm_x86_ops->get_lpage_level() < host_level ?
565 kvm_x86_ops->get_lpage_level() : host_level;
566
567 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
d25797b2
JR		 568 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
569 break;
d25797b2
JR		 570
571 return level - 1;
05da4558
MT		 572}
573
290fc38d 574/*
53c07b18 575 * Pte mapping structures:
cd4a4e53 576 *
53c07b18 577 * If pte_list bit zero is zero, then pte_list point to the spte.
cd4a4e53 578 *
53c07b18
XG		 579 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
580 * pte_list_desc containing more mappings.
53a27b39 581 *
53c07b18 582 * Returns the number of pte entries before the spte was added or zero if
53a27b39
MT		 583 * the spte was not added.
584 *
cd4a4e53 585 */
53c07b18
XG		 586static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
587 unsigned long *pte_list)
cd4a4e53 588{
53c07b18 589 struct pte_list_desc *desc;
53a27b39 590 int i, count = 0;
cd4a4e53 591
53c07b18
XG		 592 if (!*pte_list) {
593 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
594 *pte_list = (unsigned long)spte;
595 } else if (!(*pte_list & 1)) {
596 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
597 desc = mmu_alloc_pte_list_desc(vcpu);
598 desc->sptes[0] = (u64 *)*pte_list;
d555c333 599 desc->sptes[1] = spte;
53c07b18 600 *pte_list = (unsigned long)desc | 1;
cb16a7b3 601 ++count;
cd4a4e53 602 } else {
53c07b18
XG		 603 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
604 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
605 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
cd4a4e53 606 desc = desc->more;
53c07b18 607 count += PTE_LIST_EXT;
53a27b39 608 }
53c07b18
XG		 609 if (desc->sptes[PTE_LIST_EXT-1]) {
610 desc->more = mmu_alloc_pte_list_desc(vcpu);
cd4a4e53
AK		 611 desc = desc->more;
612 }
d555c333 613 for (i = 0; desc->sptes[i]; ++i)
cb16a7b3 614 ++count;
d555c333 615 desc->sptes[i] = spte;
cd4a4e53 616 }
53a27b39 617 return count;
cd4a4e53
AK		 618}
619
53c07b18
XG		 620static u64 *pte_list_next(unsigned long *pte_list, u64 *spte)
621{
622 struct pte_list_desc *desc;
623 u64 *prev_spte;
624 int i;
625
626 if (!*pte_list)
627 return NULL;
628 else if (!(*pte_list & 1)) {
629 if (!spte)
630 return (u64 *)*pte_list;
631 return NULL;
632 }
633 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
634 prev_spte = NULL;
635 while (desc) {
636 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
637 if (prev_spte == spte)
638 return desc->sptes[i];
639 prev_spte = desc->sptes[i];
640 }
641 desc = desc->more;
642 }
643 return NULL;
644}
645
646static void
647pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
648 int i, struct pte_list_desc *prev_desc)
cd4a4e53
AK		 649{
650 int j;
651
53c07b18 652 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
cd4a4e53 653 ;
d555c333
AK		 654 desc->sptes[i] = desc->sptes[j];
655 desc->sptes[j] = NULL;
cd4a4e53
AK		 656 if (j != 0)
657 return;
658 if (!prev_desc && !desc->more)
53c07b18 659 *pte_list = (unsigned long)desc->sptes[0];
cd4a4e53
AK		 660 else
661 if (prev_desc)
662 prev_desc->more = desc->more;
663 else
53c07b18
XG		 664 *pte_list = (unsigned long)desc->more | 1;
665 mmu_free_pte_list_desc(desc);
cd4a4e53
AK		 666}
667
53c07b18 668static void pte_list_remove(u64 *spte, unsigned long *pte_list)
cd4a4e53 669{
53c07b18
XG		 670 struct pte_list_desc *desc;
671 struct pte_list_desc *prev_desc;
cd4a4e53
AK		 672 int i;
673
53c07b18
XG		 674 if (!*pte_list) {
675 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
cd4a4e53 676 BUG();
53c07b18
XG		 677 } else if (!(*pte_list & 1)) {
678 rmap_printk("pte_list_remove: %p 1->0\n", spte);
679 if ((u64 *)*pte_list != spte) {
680 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
cd4a4e53
AK		 681 BUG();
682 }
53c07b18 683 *pte_list = 0;
cd4a4e53 684 } else {
53c07b18
XG		 685 rmap_printk("pte_list_remove: %p many->many\n", spte);
686 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
cd4a4e53
AK		 687 prev_desc = NULL;
688 while (desc) {
53c07b18 689 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
d555c333 690 if (desc->sptes[i] == spte) {
53c07b18 691 pte_list_desc_remove_entry(pte_list,
714b93da 692 desc, i,
cd4a4e53
AK		 693 prev_desc);
694 return;
695 }
696 prev_desc = desc;
697 desc = desc->more;
698 }
53c07b18 699 pr_err("pte_list_remove: %p many->many\n", spte);
cd4a4e53
AK		 700 BUG();
701 }
702}
703
67052b35
XG		 704typedef void (*pte_list_walk_fn) (u64 *spte);
705static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
706{
707 struct pte_list_desc *desc;
708 int i;
709
710 if (!*pte_list)
711 return;
712
713 if (!(*pte_list & 1))
714 return fn((u64 *)*pte_list);
715
716 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
717 while (desc) {
718 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
719 fn(desc->sptes[i]);
720 desc = desc->more;
721 }
722}
723
53c07b18
XG		 724/*
725 * Take gfn and return the reverse mapping to it.
726 */
727static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
728{
729 struct kvm_memory_slot *slot;
730 struct kvm_lpage_info *linfo;
731
732 slot = gfn_to_memslot(kvm, gfn);
733 if (likely(level == PT_PAGE_TABLE_LEVEL))
734 return &slot->rmap[gfn - slot->base_gfn];
735
736 linfo = lpage_info_slot(gfn, slot, level);
737
738 return &linfo->rmap_pde;
739}
740
741static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
742{
743 struct kvm_mmu_page *sp;
744 unsigned long *rmapp;
745
746 if (!is_rmap_spte(*spte))
747 return 0;
748
749 sp = page_header(__pa(spte));
750 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
751 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
752 return pte_list_add(vcpu, spte, rmapp);
753}
754
755static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
756{
757 return pte_list_next(rmapp, spte);
758}
759
760static void rmap_remove(struct kvm *kvm, u64 *spte)
761{
762 struct kvm_mmu_page *sp;
763 gfn_t gfn;
764 unsigned long *rmapp;
765
766 sp = page_header(__pa(spte));
767 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
768 rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
769 pte_list_remove(spte, rmapp);
770}
771
eb45fda4 772static int set_spte_track_bits(u64 *sptep, u64 new_spte)
be38d276 773{
ce061867 774 pfn_t pfn;
9a3aad70
XG		 775 u64 old_spte = *sptep;
776
8672b721 777 if (!spte_has_volatile_bits(old_spte))
9a3aad70 778 __set_spte(sptep, new_spte);
8672b721 779 else
9a3aad70 780 old_spte = __xchg_spte(sptep, new_spte);
ce061867 781
a9221dd5 782 if (!is_rmap_spte(old_spte))
eb45fda4 783 return 0;
8672b721 784
a9221dd5 785 pfn = spte_to_pfn(old_spte);
daa3db69 786 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
ce061867 787 kvm_set_pfn_accessed(pfn);
4132779b 788 if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
ce061867 789 kvm_set_pfn_dirty(pfn);
eb45fda4 790 return 1;
e4b502ea
XG		 791}
792
793static void drop_spte(struct kvm *kvm, u64 *sptep, u64 new_spte)
794{
eb45fda4
MT		 795 if (set_spte_track_bits(sptep, new_spte))
796 rmap_remove(kvm, sptep);
be38d276
AK		 797}
798
b1a36821 799static int rmap_write_protect(struct kvm *kvm, u64 gfn)
98348e95 800{
290fc38d 801 unsigned long *rmapp;
374cbac0 802 u64 *spte;
44ad9944 803 int i, write_protected = 0;
374cbac0 804
44ad9944 805 rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
374cbac0 806
98348e95
IE		 807 spte = rmap_next(kvm, rmapp, NULL);
808 while (spte) {
374cbac0 809 BUG_ON(!spte);
374cbac0 810 BUG_ON(!(*spte & PT_PRESENT_MASK));
374cbac0 811 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
8dae4445 812 if (is_writable_pte(*spte)) {
b79b93f9 813 update_spte(spte, *spte & ~PT_WRITABLE_MASK);
caa5b8a5
ED		 814 write_protected = 1;
815 }
9647c14c 816 spte = rmap_next(kvm, rmapp, spte);
374cbac0 817 }
855149aa 818
05da4558 819 /* check for huge page mappings */
44ad9944
JR		 820 for (i = PT_DIRECTORY_LEVEL;
821 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
822 rmapp = gfn_to_rmap(kvm, gfn, i);
823 spte = rmap_next(kvm, rmapp, NULL);
824 while (spte) {
825 BUG_ON(!spte);
826 BUG_ON(!(*spte & PT_PRESENT_MASK));
827 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
828 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
8dae4445 829 if (is_writable_pte(*spte)) {
be38d276
AK		 830 drop_spte(kvm, spte,
831 shadow_trap_nonpresent_pte);
44ad9944 832 --kvm->stat.lpages;
44ad9944
JR		 833 spte = NULL;
834 write_protected = 1;
835 }
836 spte = rmap_next(kvm, rmapp, spte);
05da4558 837 }
05da4558
MT		 838 }
839
b1a36821 840 return write_protected;
374cbac0
AK		 841}
842
8a8365c5
FD		 843static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
844 unsigned long data)
e930bffe
AA		 845{
846 u64 *spte;
847 int need_tlb_flush = 0;
848
849 while ((spte = rmap_next(kvm, rmapp, NULL))) {
850 BUG_ON(!(*spte & PT_PRESENT_MASK));
851 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
be38d276 852 drop_spte(kvm, spte, shadow_trap_nonpresent_pte);
e930bffe
AA		 853 need_tlb_flush = 1;
854 }
855 return need_tlb_flush;
856}
857
8a8365c5
FD		 858static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
859 unsigned long data)
3da0dd43
IE		 860{
861 int need_flush = 0;
e4b502ea 862 u64 *spte, new_spte;
3da0dd43
IE		 863 pte_t *ptep = (pte_t *)data;
864 pfn_t new_pfn;
865
866 WARN_ON(pte_huge(*ptep));
867 new_pfn = pte_pfn(*ptep);
868 spte = rmap_next(kvm, rmapp, NULL);
869 while (spte) {
870 BUG_ON(!is_shadow_present_pte(*spte));
871 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
872 need_flush = 1;
873 if (pte_write(*ptep)) {
be38d276 874 drop_spte(kvm, spte, shadow_trap_nonpresent_pte);
3da0dd43
IE		 875 spte = rmap_next(kvm, rmapp, NULL);
876 } else {
877 new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
878 new_spte |= (u64)new_pfn << PAGE_SHIFT;
879
880 new_spte &= ~PT_WRITABLE_MASK;
881 new_spte &= ~SPTE_HOST_WRITEABLE;
b79b93f9 882 new_spte &= ~shadow_accessed_mask;
e4b502ea 883 set_spte_track_bits(spte, new_spte);
3da0dd43
IE		 884 spte = rmap_next(kvm, rmapp, spte);
885 }
886 }
887 if (need_flush)
888 kvm_flush_remote_tlbs(kvm);
889
890 return 0;
891}
892
8a8365c5
FD		 893static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
894 unsigned long data,
3da0dd43 895 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
8a8365c5 896 unsigned long data))
e930bffe 897{
852e3c19 898 int i, j;
90bb6fc5 899 int ret;
e930bffe 900 int retval = 0;
bc6678a3
MT		 901 struct kvm_memslots *slots;
902
90d83dc3 903 slots = kvm_memslots(kvm);
e930bffe 904
46a26bf5
MT		 905 for (i = 0; i < slots->nmemslots; i++) {
906 struct kvm_memory_slot *memslot = &slots->memslots[i];
e930bffe
AA		 907 unsigned long start = memslot->userspace_addr;
908 unsigned long end;
909
e930bffe
AA		 910 end = start + (memslot->npages << PAGE_SHIFT);
911 if (hva >= start && hva < end) {
912 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
d4dbf470 913 gfn_t gfn = memslot->base_gfn + gfn_offset;
852e3c19 914
90bb6fc5 915 ret = handler(kvm, &memslot->rmap[gfn_offset], data);
852e3c19
JR		 916
917 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
d4dbf470
TY		 918 struct kvm_lpage_info *linfo;
919
920 linfo = lpage_info_slot(gfn, memslot,
921 PT_DIRECTORY_LEVEL + j);
922 ret |= handler(kvm, &linfo->rmap_pde, data);
852e3c19 923 }
90bb6fc5
AK		 924 trace_kvm_age_page(hva, memslot, ret);
925 retval |= ret;
e930bffe
AA		 926 }
927 }
928
929 return retval;
930}
931
932int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
933{
3da0dd43
IE		 934 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
935}
936
937void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
938{
8a8365c5 939 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
e930bffe
AA		 940}
941
8a8365c5
FD		 942static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
943 unsigned long data)
e930bffe
AA		 944{
945 u64 *spte;
946 int young = 0;
947
6316e1c8
RR		 948 /*
949 * Emulate the accessed bit for EPT, by checking if this page has
950 * an EPT mapping, and clearing it if it does. On the next access,
951 * a new EPT mapping will be established.
952 * This has some overhead, but not as much as the cost of swapping
953 * out actively used pages or breaking up actively used hugepages.
954 */
534e38b4 955 if (!shadow_accessed_mask)
6316e1c8 956 return kvm_unmap_rmapp(kvm, rmapp, data);
534e38b4 957
e930bffe
AA		 958 spte = rmap_next(kvm, rmapp, NULL);
959 while (spte) {
960 int _young;
961 u64 _spte = *spte;
962 BUG_ON(!(_spte & PT_PRESENT_MASK));
963 _young = _spte & PT_ACCESSED_MASK;
964 if (_young) {
965 young = 1;
966 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
967 }
968 spte = rmap_next(kvm, rmapp, spte);
969 }
970 return young;
971}
972
8ee53820
AA		 973static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
974 unsigned long data)
975{
976 u64 *spte;
977 int young = 0;
978
979 /*
980 * If there's no access bit in the secondary pte set by the
981 * hardware it's up to gup-fast/gup to set the access bit in
982 * the primary pte or in the page structure.
983 */
984 if (!shadow_accessed_mask)
985 goto out;
986
987 spte = rmap_next(kvm, rmapp, NULL);
988 while (spte) {
989 u64 _spte = *spte;
990 BUG_ON(!(_spte & PT_PRESENT_MASK));
991 young = _spte & PT_ACCESSED_MASK;
992 if (young) {
993 young = 1;
994 break;
995 }
996 spte = rmap_next(kvm, rmapp, spte);
997 }
998out:
999 return young;
1000}
1001
53a27b39
MT		 1002#define RMAP_RECYCLE_THRESHOLD 1000
1003
852e3c19 1004static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
53a27b39
MT		 1005{
1006 unsigned long *rmapp;
852e3c19
JR		 1007 struct kvm_mmu_page *sp;
1008
1009 sp = page_header(__pa(spte));
53a27b39 1010
852e3c19 1011 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
53a27b39 1012
3da0dd43 1013 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
53a27b39
MT		 1014 kvm_flush_remote_tlbs(vcpu->kvm);
1015}
1016
e930bffe
AA		 1017int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1018{
3da0dd43 1019 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
e930bffe
AA		 1020}
1021
8ee53820
AA		 1022int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1023{
1024 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1025}
1026
d6c69ee9 1027#ifdef MMU_DEBUG
47ad8e68 1028static int is_empty_shadow_page(u64 *spt)
6aa8b732 1029{
139bdb2d
AK		 1030 u64 *pos;
1031 u64 *end;
1032
47ad8e68 1033 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
3c915510 1034 if (is_shadow_present_pte(*pos)) {
b8688d51 1035 printk(KERN_ERR "%s: %p %llx\n", __func__,
139bdb2d 1036 pos, *pos);
6aa8b732 1037 return 0;
139bdb2d 1038 }
6aa8b732
AK		 1039 return 1;
1040}
d6c69ee9 1041#endif
6aa8b732 1042
45221ab6
DH		 1043/*
1044 * This value is the sum of all of the kvm instances's
1045 * kvm->arch.n_used_mmu_pages values. We need a global,
1046 * aggregate version in order to make the slab shrinker
1047 * faster
1048 */
1049static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1050{
1051 kvm->arch.n_used_mmu_pages += nr;
1052 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1053}
1054
4db35314 1055static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
260746c0 1056{
4db35314 1057 ASSERT(is_empty_shadow_page(sp->spt));
7775834a 1058 hlist_del(&sp->hash_link);
4db35314 1059 list_del(&sp->link);
842f22ed 1060 free_page((unsigned long)sp->spt);
2032a93d 1061 if (!sp->role.direct)
842f22ed 1062 free_page((unsigned long)sp->gfns);
e8ad9a70 1063 kmem_cache_free(mmu_page_header_cache, sp);
45221ab6 1064 kvm_mod_used_mmu_pages(kvm, -1);
260746c0
AK		 1065}
1066
cea0f0e7
AK		 1067static unsigned kvm_page_table_hashfn(gfn_t gfn)
1068{
1ae0a13d 1069 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
cea0f0e7
AK		 1070}
1071
714b93da 1072static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
4db35314 1073 struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7 1074{
cea0f0e7
AK		 1075 if (!parent_pte)
1076 return;
cea0f0e7 1077
67052b35 1078 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
cea0f0e7
AK		 1079}
1080
4db35314 1081static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
cea0f0e7
AK		 1082 u64 *parent_pte)
1083{
67052b35 1084 pte_list_remove(parent_pte, &sp->parent_ptes);
cea0f0e7
AK		 1085}
1086
bcdd9a93
XG		 1087static void drop_parent_pte(struct kvm_mmu_page *sp,
1088 u64 *parent_pte)
1089{
1090 mmu_page_remove_parent_pte(sp, parent_pte);
1091 __set_spte(parent_pte, shadow_trap_nonpresent_pte);
1092}
1093
67052b35
XG		 1094static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1095 u64 *parent_pte, int direct)
ad8cfbe3 1096{
67052b35
XG		 1097 struct kvm_mmu_page *sp;
1098 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache,
1099 sizeof *sp);
1100 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
1101 if (!direct)
1102 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache,
1103 PAGE_SIZE);
1104 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1105 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1106 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
1107 sp->parent_ptes = 0;
1108 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1109 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1110 return sp;
ad8cfbe3
MT		 1111}
1112
67052b35 1113static void mark_unsync(u64 *spte);
1047df1f 1114static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
0074ff63 1115{
67052b35 1116 pte_list_walk(&sp->parent_ptes, mark_unsync);
0074ff63
MT		 1117}
1118
67052b35 1119static void mark_unsync(u64 *spte)
0074ff63 1120{
67052b35 1121 struct kvm_mmu_page *sp;
1047df1f 1122 unsigned int index;
0074ff63 1123
67052b35 1124 sp = page_header(__pa(spte));
1047df1f
XG		 1125 index = spte - sp->spt;
1126 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
0074ff63 1127 return;
1047df1f 1128 if (sp->unsync_children++)
0074ff63 1129 return;
1047df1f 1130 kvm_mmu_mark_parents_unsync(sp);
0074ff63
MT		 1131}
1132
d761a501
AK		 1133static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
1134 struct kvm_mmu_page *sp)
1135{
1136 int i;
1137
1138 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1139 sp->spt[i] = shadow_trap_nonpresent_pte;
1140}
1141
e8bc217a 1142static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
a4a8e6f7 1143 struct kvm_mmu_page *sp)
e8bc217a
MT		 1144{
1145 return 1;
1146}
1147
a7052897
MT		 1148static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1149{
1150}
1151
0f53b5b1
XG		 1152static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1153 struct kvm_mmu_page *sp, u64 *spte,
7c562522 1154 const void *pte)
0f53b5b1
XG		 1155{
1156 WARN_ON(1);
1157}
1158
60c8aec6
MT		 1159#define KVM_PAGE_ARRAY_NR 16
1160
1161struct kvm_mmu_pages {
1162 struct mmu_page_and_offset {
1163 struct kvm_mmu_page *sp;
1164 unsigned int idx;
1165 } page[KVM_PAGE_ARRAY_NR];
1166 unsigned int nr;
1167};
1168
0074ff63
MT		 1169#define for_each_unsync_children(bitmap, idx) \
1170 for (idx = find_first_bit(bitmap, 512); \
1171 idx < 512; \
1172 idx = find_next_bit(bitmap, 512, idx+1))
1173
cded19f3
HE		 1174static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1175 int idx)
4731d4c7 1176{
60c8aec6 1177 int i;
4731d4c7 1178
60c8aec6
MT		 1179 if (sp->unsync)
1180 for (i=0; i < pvec->nr; i++)
1181 if (pvec->page[i].sp == sp)
1182 return 0;
1183
1184 pvec->page[pvec->nr].sp = sp;
1185 pvec->page[pvec->nr].idx = idx;
1186 pvec->nr++;
1187 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1188}
1189
1190static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1191 struct kvm_mmu_pages *pvec)
1192{
1193 int i, ret, nr_unsync_leaf = 0;
4731d4c7 1194
0074ff63 1195 for_each_unsync_children(sp->unsync_child_bitmap, i) {
7a8f1a74 1196 struct kvm_mmu_page *child;
4731d4c7
MT		 1197 u64 ent = sp->spt[i];
1198
7a8f1a74
XG		 1199 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1200 goto clear_child_bitmap;
1201
1202 child = page_header(ent & PT64_BASE_ADDR_MASK);
1203
1204 if (child->unsync_children) {
1205 if (mmu_pages_add(pvec, child, i))
1206 return -ENOSPC;
1207
1208 ret = __mmu_unsync_walk(child, pvec);
1209 if (!ret)
1210 goto clear_child_bitmap;
1211 else if (ret > 0)
1212 nr_unsync_leaf += ret;
1213 else
1214 return ret;
1215 } else if (child->unsync) {
1216 nr_unsync_leaf++;
1217 if (mmu_pages_add(pvec, child, i))
1218 return -ENOSPC;
1219 } else
1220 goto clear_child_bitmap;
1221
1222 continue;
1223
1224clear_child_bitmap:
1225 __clear_bit(i, sp->unsync_child_bitmap);
1226 sp->unsync_children--;
1227 WARN_ON((int)sp->unsync_children < 0);
4731d4c7
MT		 1228 }
1229
4731d4c7 1230
60c8aec6
MT		 1231 return nr_unsync_leaf;
1232}
1233
1234static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1235 struct kvm_mmu_pages *pvec)
1236{
1237 if (!sp->unsync_children)
1238 return 0;
1239
1240 mmu_pages_add(pvec, sp, 0);
1241 return __mmu_unsync_walk(sp, pvec);
4731d4c7
MT		 1242}
1243
4731d4c7
MT		 1244static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1245{
1246 WARN_ON(!sp->unsync);
5e1b3ddb 1247 trace_kvm_mmu_sync_page(sp);
4731d4c7
MT		 1248 sp->unsync = 0;
1249 --kvm->stat.mmu_unsync;
1250}
1251
7775834a
XG		 1252static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1253 struct list_head *invalid_list);
1254static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1255 struct list_head *invalid_list);
4731d4c7 1256
f41d335a
XG		 1257#define for_each_gfn_sp(kvm, sp, gfn, pos) \
1258 hlist_for_each_entry(sp, pos, \
7ae680eb
XG		 1259 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1260 if ((sp)->gfn != (gfn)) {} else
1261
f41d335a
XG		 1262#define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \
1263 hlist_for_each_entry(sp, pos, \
7ae680eb
XG		 1264 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1265 if ((sp)->gfn != (gfn) || (sp)->role.direct || \
1266 (sp)->role.invalid) {} else
1267
f918b443 1268/* @sp->gfn should be write-protected at the call site */
1d9dc7e0 1269static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
d98ba053 1270 struct list_head *invalid_list, bool clear_unsync)
4731d4c7 1271{
5b7e0102 1272 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
d98ba053 1273 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
4731d4c7
MT		 1274 return 1;
1275 }
1276
f918b443 1277 if (clear_unsync)
1d9dc7e0 1278 kvm_unlink_unsync_page(vcpu->kvm, sp);
1d9dc7e0 1279
a4a8e6f7 1280 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
d98ba053 1281 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
4731d4c7
MT		 1282 return 1;
1283 }
1284
1285 kvm_mmu_flush_tlb(vcpu);
4731d4c7
MT		 1286 return 0;
1287}
1288
1d9dc7e0
XG		 1289static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1290 struct kvm_mmu_page *sp)
1291{
d98ba053 1292 LIST_HEAD(invalid_list);
1d9dc7e0
XG		 1293 int ret;
1294
d98ba053 1295 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
be71e061 1296 if (ret)
d98ba053
XG		 1297 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1298
1d9dc7e0
XG		 1299 return ret;
1300}
1301
d98ba053
XG		 1302static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1303 struct list_head *invalid_list)
1d9dc7e0 1304{
d98ba053 1305 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1d9dc7e0
XG		 1306}
1307
9f1a122f
XG		 1308/* @gfn should be write-protected at the call site */
1309static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1310{
9f1a122f 1311 struct kvm_mmu_page *s;
f41d335a 1312 struct hlist_node *node;
d98ba053 1313 LIST_HEAD(invalid_list);
9f1a122f
XG		 1314 bool flush = false;
1315
f41d335a 1316 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
7ae680eb 1317 if (!s->unsync)
9f1a122f
XG		 1318 continue;
1319
1320 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
a4a8e6f7 1321 kvm_unlink_unsync_page(vcpu->kvm, s);
9f1a122f 1322 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
a4a8e6f7 1323 (vcpu->arch.mmu.sync_page(vcpu, s))) {
d98ba053 1324 kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
9f1a122f
XG		 1325 continue;
1326 }
9f1a122f
XG		 1327 flush = true;
1328 }
1329
d98ba053 1330 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
9f1a122f
XG		 1331 if (flush)
1332 kvm_mmu_flush_tlb(vcpu);
1333}
1334
60c8aec6
MT		 1335struct mmu_page_path {
1336 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1337 unsigned int idx[PT64_ROOT_LEVEL-1];
4731d4c7
MT		 1338};
1339
60c8aec6
MT		 1340#define for_each_sp(pvec, sp, parents, i) \
1341 for (i = mmu_pages_next(&pvec, &parents, -1), \
1342 sp = pvec.page[i].sp; \
1343 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1344 i = mmu_pages_next(&pvec, &parents, i))
1345
cded19f3
HE		 1346static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1347 struct mmu_page_path *parents,
1348 int i)
60c8aec6
MT		 1349{
1350 int n;
1351
1352 for (n = i+1; n < pvec->nr; n++) {
1353 struct kvm_mmu_page *sp = pvec->page[n].sp;
1354
1355 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1356 parents->idx[0] = pvec->page[n].idx;
1357 return n;
1358 }
1359
1360 parents->parent[sp->role.level-2] = sp;
1361 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1362 }
1363
1364 return n;
1365}
1366
cded19f3 1367static void mmu_pages_clear_parents(struct mmu_page_path *parents)
4731d4c7 1368{
60c8aec6
MT		 1369 struct kvm_mmu_page *sp;
1370 unsigned int level = 0;
1371
1372 do {
1373 unsigned int idx = parents->idx[level];
4731d4c7 1374
60c8aec6
MT		 1375 sp = parents->parent[level];
1376 if (!sp)
1377 return;
1378
1379 --sp->unsync_children;
1380 WARN_ON((int)sp->unsync_children < 0);
1381 __clear_bit(idx, sp->unsync_child_bitmap);
1382 level++;
1383 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
4731d4c7
MT		 1384}
1385
60c8aec6
MT		 1386static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1387 struct mmu_page_path *parents,
1388 struct kvm_mmu_pages *pvec)
4731d4c7 1389{
60c8aec6
MT		 1390 parents->parent[parent->role.level-1] = NULL;
1391 pvec->nr = 0;
1392}
4731d4c7 1393
60c8aec6
MT		 1394static void mmu_sync_children(struct kvm_vcpu *vcpu,
1395 struct kvm_mmu_page *parent)
1396{
1397 int i;
1398 struct kvm_mmu_page *sp;
1399 struct mmu_page_path parents;
1400 struct kvm_mmu_pages pages;
d98ba053 1401 LIST_HEAD(invalid_list);
60c8aec6
MT		 1402
1403 kvm_mmu_pages_init(parent, &parents, &pages);
1404 while (mmu_unsync_walk(parent, &pages)) {
b1a36821
MT		 1405 int protected = 0;
1406
1407 for_each_sp(pages, sp, parents, i)
1408 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1409
1410 if (protected)
1411 kvm_flush_remote_tlbs(vcpu->kvm);
1412
60c8aec6 1413 for_each_sp(pages, sp, parents, i) {
d98ba053 1414 kvm_sync_page(vcpu, sp, &invalid_list);
60c8aec6
MT		 1415 mmu_pages_clear_parents(&parents);
1416 }
d98ba053 1417 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4731d4c7 1418 cond_resched_lock(&vcpu->kvm->mmu_lock);
60c8aec6
MT		 1419 kvm_mmu_pages_init(parent, &parents, &pages);
1420 }
4731d4c7
MT		 1421}
1422
cea0f0e7
AK		 1423static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1424 gfn_t gfn,
1425 gva_t gaddr,
1426 unsigned level,
f6e2c02b 1427 int direct,
41074d07 1428 unsigned access,
f7d9c7b7 1429 u64 *parent_pte)
cea0f0e7
AK		 1430{
1431 union kvm_mmu_page_role role;
cea0f0e7 1432 unsigned quadrant;
9f1a122f 1433 struct kvm_mmu_page *sp;
f41d335a 1434 struct hlist_node *node;
9f1a122f 1435 bool need_sync = false;
cea0f0e7 1436
a770f6f2 1437 role = vcpu->arch.mmu.base_role;
cea0f0e7 1438 role.level = level;
f6e2c02b 1439 role.direct = direct;
84b0c8c6 1440 if (role.direct)
5b7e0102 1441 role.cr4_pae = 0;
41074d07 1442 role.access = access;
c5a78f2b
JR		 1443 if (!vcpu->arch.mmu.direct_map
1444 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
cea0f0e7
AK		 1445 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1446 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1447 role.quadrant = quadrant;
1448 }
f41d335a 1449 for_each_gfn_sp(vcpu->kvm, sp, gfn, node) {
7ae680eb
XG		 1450 if (!need_sync && sp->unsync)
1451 need_sync = true;
4731d4c7 1452
7ae680eb
XG		 1453 if (sp->role.word != role.word)
1454 continue;
4731d4c7 1455
7ae680eb
XG		 1456 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1457 break;
e02aa901 1458
7ae680eb
XG		 1459 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1460 if (sp->unsync_children) {
a8eeb04a 1461 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
7ae680eb
XG		 1462 kvm_mmu_mark_parents_unsync(sp);
1463 } else if (sp->unsync)
1464 kvm_mmu_mark_parents_unsync(sp);
e02aa901 1465
7ae680eb
XG		 1466 trace_kvm_mmu_get_page(sp, false);
1467 return sp;
1468 }
dfc5aa00 1469 ++vcpu->kvm->stat.mmu_cache_miss;
2032a93d 1470 sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
4db35314
AK		 1471 if (!sp)
1472 return sp;
4db35314
AK		 1473 sp->gfn = gfn;
1474 sp->role = role;
7ae680eb
XG		 1475 hlist_add_head(&sp->hash_link,
1476 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
f6e2c02b 1477 if (!direct) {
b1a36821
MT		 1478 if (rmap_write_protect(vcpu->kvm, gfn))
1479 kvm_flush_remote_tlbs(vcpu->kvm);
9f1a122f
XG		 1480 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1481 kvm_sync_pages(vcpu, gfn);
1482
4731d4c7
MT		 1483 account_shadowed(vcpu->kvm, gfn);
1484 }
131d8279
AK		 1485 if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte)
1486 vcpu->arch.mmu.prefetch_page(vcpu, sp);
1487 else
1488 nonpaging_prefetch_page(vcpu, sp);
f691fe1d 1489 trace_kvm_mmu_get_page(sp, true);
4db35314 1490 return sp;
cea0f0e7
AK		 1491}
1492
2d11123a
AK		 1493static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1494 struct kvm_vcpu *vcpu, u64 addr)
1495{
1496 iterator->addr = addr;
1497 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1498 iterator->level = vcpu->arch.mmu.shadow_root_level;
81407ca5
JR		 1499
1500 if (iterator->level == PT64_ROOT_LEVEL &&
1501 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
1502 !vcpu->arch.mmu.direct_map)
1503 --iterator->level;
1504
2d11123a
AK		 1505 if (iterator->level == PT32E_ROOT_LEVEL) {
1506 iterator->shadow_addr
1507 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1508 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1509 --iterator->level;
1510 if (!iterator->shadow_addr)
1511 iterator->level = 0;
1512 }
1513}
1514
1515static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1516{
1517 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1518 return false;
4d88954d
MT		 1519
1520 if (iterator->level == PT_PAGE_TABLE_LEVEL)
1521 if (is_large_pte(*iterator->sptep))
1522 return false;
1523
2d11123a
AK		 1524 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1525 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1526 return true;
1527}
1528
1529static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1530{
1531 iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK;
1532 --iterator->level;
1533}
1534
32ef26a3
AK		 1535static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
1536{
1537 u64 spte;
1538
1539 spte = __pa(sp->spt)
1540 | PT_PRESENT_MASK | PT_ACCESSED_MASK
1541 | PT_WRITABLE_MASK | PT_USER_MASK;
121eee97 1542 __set_spte(sptep, spte);
32ef26a3
AK		 1543}
1544
a3aa51cf
AK		 1545static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1546{
1547 if (is_large_pte(*sptep)) {
1548 drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte);
1549 kvm_flush_remote_tlbs(vcpu->kvm);
1550 }
1551}
1552
a357bd22
AK		 1553static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1554 unsigned direct_access)
1555{
1556 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
1557 struct kvm_mmu_page *child;
1558
1559 /*
1560 * For the direct sp, if the guest pte's dirty bit
1561 * changed form clean to dirty, it will corrupt the
1562 * sp's access: allow writable in the read-only sp,
1563 * so we should update the spte at this point to get
1564 * a new sp with the correct access.
1565 */
1566 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
1567 if (child->role.access == direct_access)
1568 return;
1569
bcdd9a93 1570 drop_parent_pte(child, sptep);
a357bd22
AK		 1571 kvm_flush_remote_tlbs(vcpu->kvm);
1572 }
1573}
1574
38e3b2b2
XG		 1575static void mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
1576 u64 *spte)
1577{
1578 u64 pte;
1579 struct kvm_mmu_page *child;
1580
1581 pte = *spte;
1582 if (is_shadow_present_pte(pte)) {
1583 if (is_last_spte(pte, sp->role.level))
1584 drop_spte(kvm, spte, shadow_trap_nonpresent_pte);
1585 else {
1586 child = page_header(pte & PT64_BASE_ADDR_MASK);
bcdd9a93 1587 drop_parent_pte(child, spte);
38e3b2b2
XG		 1588 }
1589 }
1590 __set_spte(spte, shadow_trap_nonpresent_pte);
1591 if (is_large_pte(pte))
1592 --kvm->stat.lpages;
1593}
1594
90cb0529 1595static void kvm_mmu_page_unlink_children(struct kvm *kvm,
4db35314 1596 struct kvm_mmu_page *sp)
a436036b 1597{
697fe2e2 1598 unsigned i;
697fe2e2 1599
38e3b2b2
XG		 1600 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1601 mmu_page_zap_pte(kvm, sp, sp->spt + i);
a436036b
AK		 1602}
1603
4db35314 1604static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7 1605{
4db35314 1606 mmu_page_remove_parent_pte(sp, parent_pte);
a436036b
AK		 1607}
1608
12b7d28f
AK		 1609static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1610{
1611 int i;
988a2cae 1612 struct kvm_vcpu *vcpu;
12b7d28f 1613
988a2cae
GN		 1614 kvm_for_each_vcpu(i, vcpu, kvm)
1615 vcpu->arch.last_pte_updated = NULL;
12b7d28f
AK		 1616}
1617
31aa2b44 1618static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
a436036b
AK		 1619{
1620 u64 *parent_pte;
1621
bcdd9a93
XG		 1622 while ((parent_pte = pte_list_next(&sp->parent_ptes, NULL)))
1623 drop_parent_pte(sp, parent_pte);
31aa2b44
AK		 1624}
1625
60c8aec6 1626static int mmu_zap_unsync_children(struct kvm *kvm,
7775834a
XG		 1627 struct kvm_mmu_page *parent,
1628 struct list_head *invalid_list)
4731d4c7 1629{
60c8aec6
MT		 1630 int i, zapped = 0;
1631 struct mmu_page_path parents;
1632 struct kvm_mmu_pages pages;
4731d4c7 1633
60c8aec6 1634 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
4731d4c7 1635 return 0;
60c8aec6
MT		 1636
1637 kvm_mmu_pages_init(parent, &parents, &pages);
1638 while (mmu_unsync_walk(parent, &pages)) {
1639 struct kvm_mmu_page *sp;
1640
1641 for_each_sp(pages, sp, parents, i) {
7775834a 1642 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
60c8aec6 1643 mmu_pages_clear_parents(&parents);
77662e00 1644 zapped++;
60c8aec6 1645 }
60c8aec6
MT		 1646 kvm_mmu_pages_init(parent, &parents, &pages);
1647 }
1648
1649 return zapped;
4731d4c7
MT		 1650}
1651
7775834a
XG		 1652static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1653 struct list_head *invalid_list)
31aa2b44 1654{
4731d4c7 1655 int ret;
f691fe1d 1656
7775834a 1657 trace_kvm_mmu_prepare_zap_page(sp);
31aa2b44 1658 ++kvm->stat.mmu_shadow_zapped;
7775834a 1659 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
4db35314 1660 kvm_mmu_page_unlink_children(kvm, sp);
31aa2b44 1661 kvm_mmu_unlink_parents(kvm, sp);
f6e2c02b 1662 if (!sp->role.invalid && !sp->role.direct)
5b5c6a5a 1663 unaccount_shadowed(kvm, sp->gfn);
4731d4c7
MT		 1664 if (sp->unsync)
1665 kvm_unlink_unsync_page(kvm, sp);
4db35314 1666 if (!sp->root_count) {
54a4f023
GJ		 1667 /* Count self */
1668 ret++;
7775834a 1669 list_move(&sp->link, invalid_list);
2e53d63a 1670 } else {
5b5c6a5a 1671 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2e53d63a
MT		 1672 kvm_reload_remote_mmus(kvm);
1673 }
7775834a
XG		 1674
1675 sp->role.invalid = 1;
12b7d28f 1676 kvm_mmu_reset_last_pte_updated(kvm);
4731d4c7 1677 return ret;
a436036b
AK		 1678}
1679
7775834a
XG		 1680static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1681 struct list_head *invalid_list)
1682{
1683 struct kvm_mmu_page *sp;
1684
1685 if (list_empty(invalid_list))
1686 return;
1687
1688 kvm_flush_remote_tlbs(kvm);
1689
1690 do {
1691 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
1692 WARN_ON(!sp->role.invalid || sp->root_count);
1693 kvm_mmu_free_page(kvm, sp);
1694 } while (!list_empty(invalid_list));
1695
1696}
1697
82ce2c96
IE		 1698/*
1699 * Changing the number of mmu pages allocated to the vm
49d5ca26 1700 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
82ce2c96 1701 */
49d5ca26 1702void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
82ce2c96 1703{
d98ba053 1704 LIST_HEAD(invalid_list);
82ce2c96
IE		 1705 /*
1706 * If we set the number of mmu pages to be smaller be than the
1707 * number of actived pages , we must to free some mmu pages before we
1708 * change the value
1709 */
1710
49d5ca26
DH		 1711 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
1712 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages &&
77662e00 1713 !list_empty(&kvm->arch.active_mmu_pages)) {
82ce2c96
IE		 1714 struct kvm_mmu_page *page;
1715
f05e70ac 1716 page = container_of(kvm->arch.active_mmu_pages.prev,
82ce2c96 1717 struct kvm_mmu_page, link);
80b63faf
XF		 1718 kvm_mmu_prepare_zap_page(kvm, page, &invalid_list);
1719 kvm_mmu_commit_zap_page(kvm, &invalid_list);
82ce2c96 1720 }
49d5ca26 1721 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
82ce2c96 1722 }
82ce2c96 1723
49d5ca26 1724 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
82ce2c96
IE		 1725}
1726
f67a46f4 1727static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
a436036b 1728{
4db35314 1729 struct kvm_mmu_page *sp;
f41d335a 1730 struct hlist_node *node;
d98ba053 1731 LIST_HEAD(invalid_list);
a436036b
AK		 1732 int r;
1733
9ad17b10 1734 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
a436036b 1735 r = 0;
f41d335a
XG		 1736
1737 for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
9ad17b10 1738 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
7ae680eb
XG		 1739 sp->role.word);
1740 r = 1;
f41d335a 1741 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
7ae680eb 1742 }
d98ba053 1743 kvm_mmu_commit_zap_page(kvm, &invalid_list);
a436036b 1744 return r;
cea0f0e7
AK		 1745}
1746
f67a46f4 1747static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
97a0a01e 1748{
4db35314 1749 struct kvm_mmu_page *sp;
f41d335a 1750 struct hlist_node *node;
d98ba053 1751 LIST_HEAD(invalid_list);
97a0a01e 1752
f41d335a 1753 for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
9ad17b10 1754 pgprintk("%s: zap %llx %x\n",
7ae680eb 1755 __func__, gfn, sp->role.word);
f41d335a 1756 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
97a0a01e 1757 }
d98ba053 1758 kvm_mmu_commit_zap_page(kvm, &invalid_list);
97a0a01e
AK		 1759}
1760
38c335f1 1761static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
6aa8b732 1762{
bc6678a3 1763 int slot = memslot_id(kvm, gfn);
4db35314 1764 struct kvm_mmu_page *sp = page_header(__pa(pte));
6aa8b732 1765
291f26bc 1766 __set_bit(slot, sp->slot_bitmap);
6aa8b732
AK		 1767}
1768
6844dec6
MT		 1769static void mmu_convert_notrap(struct kvm_mmu_page *sp)
1770{
1771 int i;
1772 u64 *pt = sp->spt;
1773
1774 if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte)
1775 return;
1776
1777 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1778 if (pt[i] == shadow_notrap_nonpresent_pte)
d555c333 1779 __set_spte(&pt[i], shadow_trap_nonpresent_pte);
6844dec6
MT		 1780 }
1781}
1782
74be52e3
SY		 1783/*
1784 * The function is based on mtrr_type_lookup() in
1785 * arch/x86/kernel/cpu/mtrr/generic.c
1786 */
1787static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
1788 u64 start, u64 end)
1789{
1790 int i;
1791 u64 base, mask;
1792 u8 prev_match, curr_match;
1793 int num_var_ranges = KVM_NR_VAR_MTRR;
1794
1795 if (!mtrr_state->enabled)
1796 return 0xFF;
1797
1798 /* Make end inclusive end, instead of exclusive */
1799 end--;
1800
1801 /* Look in fixed ranges. Just return the type as per start */
1802 if (mtrr_state->have_fixed && (start < 0x100000)) {
1803 int idx;
1804
1805 if (start < 0x80000) {
1806 idx = 0;
1807 idx += (start >> 16);
1808 return mtrr_state->fixed_ranges[idx];
1809 } else if (start < 0xC0000) {
1810 idx = 1 * 8;
1811 idx += ((start - 0x80000) >> 14);
1812 return mtrr_state->fixed_ranges[idx];
1813 } else if (start < 0x1000000) {
1814 idx = 3 * 8;
1815 idx += ((start - 0xC0000) >> 12);
1816 return mtrr_state->fixed_ranges[idx];
1817 }
1818 }
1819
1820 /*
1821 * Look in variable ranges
1822 * Look of multiple ranges matching this address and pick type
1823 * as per MTRR precedence
1824 */
1825 if (!(mtrr_state->enabled & 2))
1826 return mtrr_state->def_type;
1827
1828 prev_match = 0xFF;
1829 for (i = 0; i < num_var_ranges; ++i) {
1830 unsigned short start_state, end_state;
1831
1832 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
1833 continue;
1834
1835 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
1836 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
1837 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
1838 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
1839
1840 start_state = ((start & mask) == (base & mask));
1841 end_state = ((end & mask) == (base & mask));
1842 if (start_state != end_state)
1843 return 0xFE;
1844
1845 if ((start & mask) != (base & mask))
1846 continue;
1847
1848 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
1849 if (prev_match == 0xFF) {
1850 prev_match = curr_match;
1851 continue;
1852 }
1853
1854 if (prev_match == MTRR_TYPE_UNCACHABLE ||
1855 curr_match == MTRR_TYPE_UNCACHABLE)
1856 return MTRR_TYPE_UNCACHABLE;
1857
1858 if ((prev_match == MTRR_TYPE_WRBACK &&
1859 curr_match == MTRR_TYPE_WRTHROUGH) ||
1860 (prev_match == MTRR_TYPE_WRTHROUGH &&
1861 curr_match == MTRR_TYPE_WRBACK)) {
1862 prev_match = MTRR_TYPE_WRTHROUGH;
1863 curr_match = MTRR_TYPE_WRTHROUGH;
1864 }
1865
1866 if (prev_match != curr_match)
1867 return MTRR_TYPE_UNCACHABLE;
1868 }
1869
1870 if (prev_match != 0xFF)
1871 return prev_match;
1872
1873 return mtrr_state->def_type;
1874}
1875
4b12f0de 1876u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
74be52e3
SY		 1877{
1878 u8 mtrr;
1879
1880 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
1881 (gfn << PAGE_SHIFT) + PAGE_SIZE);
1882 if (mtrr == 0xfe || mtrr == 0xff)
1883 mtrr = MTRR_TYPE_WRBACK;
1884 return mtrr;
1885}
4b12f0de 1886EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
74be52e3 1887
9cf5cf5a
XG		 1888static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1889{
1890 trace_kvm_mmu_unsync_page(sp);
1891 ++vcpu->kvm->stat.mmu_unsync;
1892 sp->unsync = 1;
1893
1894 kvm_mmu_mark_parents_unsync(sp);
1895 mmu_convert_notrap(sp);
1896}
1897
1898static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
4731d4c7 1899{
4731d4c7 1900 struct kvm_mmu_page *s;
f41d335a 1901 struct hlist_node *node;
9cf5cf5a 1902
f41d335a 1903 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
7ae680eb 1904 if (s->unsync)
4731d4c7 1905 continue;
9cf5cf5a
XG		 1906 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1907 __kvm_unsync_page(vcpu, s);
4731d4c7 1908 }
4731d4c7
MT		 1909}
1910
1911static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
1912 bool can_unsync)
1913{
9cf5cf5a 1914 struct kvm_mmu_page *s;
f41d335a 1915 struct hlist_node *node;
9cf5cf5a
XG		 1916 bool need_unsync = false;
1917
f41d335a 1918 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
36a2e677
XG		 1919 if (!can_unsync)
1920 return 1;
1921
9cf5cf5a 1922 if (s->role.level != PT_PAGE_TABLE_LEVEL)
4731d4c7 1923 return 1;
9cf5cf5a
XG		 1924
1925 if (!need_unsync && !s->unsync) {
36a2e677 1926 if (!oos_shadow)
9cf5cf5a
XG		 1927 return 1;
1928 need_unsync = true;
1929 }
4731d4c7 1930 }
9cf5cf5a
XG		 1931 if (need_unsync)
1932 kvm_unsync_pages(vcpu, gfn);
4731d4c7
MT		 1933 return 0;
1934}
1935
d555c333 1936static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd 1937 unsigned pte_access, int user_fault,
852e3c19 1938 int write_fault, int dirty, int level,
c2d0ee46 1939 gfn_t gfn, pfn_t pfn, bool speculative,
9bdbba13 1940 bool can_unsync, bool host_writable)
1c4f1fd6 1941{
b330aa0c 1942 u64 spte, entry = *sptep;
1e73f9dd 1943 int ret = 0;
64d4d521 1944
1c4f1fd6
AK		 1945 /*
1946 * We don't set the accessed bit, since we sometimes want to see
1947 * whether the guest actually used the pte (in order to detect
1948 * demand paging).
1949 */
982c2565 1950 spte = PT_PRESENT_MASK;
947da538 1951 if (!speculative)
3201b5d9 1952 spte |= shadow_accessed_mask;
1c4f1fd6
AK		 1953 if (!dirty)
1954 pte_access &= ~ACC_WRITE_MASK;
7b52345e
SY		 1955 if (pte_access & ACC_EXEC_MASK)
1956 spte |= shadow_x_mask;
1957 else
1958 spte |= shadow_nx_mask;
1c4f1fd6 1959 if (pte_access & ACC_USER_MASK)
7b52345e 1960 spte |= shadow_user_mask;
852e3c19 1961 if (level > PT_PAGE_TABLE_LEVEL)
05da4558 1962 spte |= PT_PAGE_SIZE_MASK;
b0bc3ee2 1963 if (tdp_enabled)
4b12f0de
SY		 1964 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
1965 kvm_is_mmio_pfn(pfn));
1c4f1fd6 1966
9bdbba13 1967 if (host_writable)
1403283a 1968 spte |= SPTE_HOST_WRITEABLE;
f8e453b0
XG		 1969 else
1970 pte_access &= ~ACC_WRITE_MASK;
1403283a 1971
35149e21 1972 spte |= (u64)pfn << PAGE_SHIFT;
1c4f1fd6
AK		 1973
1974 if ((pte_access & ACC_WRITE_MASK)
c5a78f2b
JR		 1975 || (!vcpu->arch.mmu.direct_map && write_fault
1976 && !is_write_protection(vcpu) && !user_fault)) {
1c4f1fd6 1977
852e3c19
JR		 1978 if (level > PT_PAGE_TABLE_LEVEL &&
1979 has_wrprotected_page(vcpu->kvm, gfn, level)) {
38187c83 1980 ret = 1;
be38d276
AK		 1981 drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte);
1982 goto done;
38187c83
MT		 1983 }
1984
1c4f1fd6 1985 spte |= PT_WRITABLE_MASK;
1c4f1fd6 1986
c5a78f2b 1987 if (!vcpu->arch.mmu.direct_map
411c588d 1988 && !(pte_access & ACC_WRITE_MASK)) {
69325a12 1989 spte &= ~PT_USER_MASK;
411c588d
AK		 1990 /*
1991 * If we converted a user page to a kernel page,
1992 * so that the kernel can write to it when cr0.wp=0,
1993 * then we should prevent the kernel from executing it
1994 * if SMEP is enabled.
1995 */
1996 if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
1997 spte |= PT64_NX_MASK;
1998 }
69325a12 1999
ecc5589f
MT		 2000 /*
2001 * Optimization: for pte sync, if spte was writable the hash
2002 * lookup is unnecessary (and expensive). Write protection
2003 * is responsibility of mmu_get_page / kvm_sync_page.
2004 * Same reasoning can be applied to dirty page accounting.
2005 */
8dae4445 2006 if (!can_unsync && is_writable_pte(*sptep))
ecc5589f
MT		 2007 goto set_pte;
2008
4731d4c7 2009 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
9ad17b10 2010 pgprintk("%s: found shadow page for %llx, marking ro\n",
b8688d51 2011 __func__, gfn);
1e73f9dd 2012 ret = 1;
1c4f1fd6 2013 pte_access &= ~ACC_WRITE_MASK;
8dae4445 2014 if (is_writable_pte(spte))
1c4f1fd6 2015 spte &= ~PT_WRITABLE_MASK;
1c4f1fd6
AK		 2016 }
2017 }
2018
1c4f1fd6
AK		 2019 if (pte_access & ACC_WRITE_MASK)
2020 mark_page_dirty(vcpu->kvm, gfn);
2021
38187c83 2022set_pte:
b79b93f9 2023 update_spte(sptep, spte);
b330aa0c
XG		 2024 /*
2025 * If we overwrite a writable spte with a read-only one we
2026 * should flush remote TLBs. Otherwise rmap_write_protect
2027 * will find a read-only spte, even though the writable spte
2028 * might be cached on a CPU's TLB.
2029 */
2030 if (is_writable_pte(entry) && !is_writable_pte(*sptep))
2031 kvm_flush_remote_tlbs(vcpu->kvm);
be38d276 2032done:
1e73f9dd
MT		 2033 return ret;
2034}
2035
d555c333 2036static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1e73f9dd
MT		 2037 unsigned pt_access, unsigned pte_access,
2038 int user_fault, int write_fault, int dirty,
852e3c19 2039 int *ptwrite, int level, gfn_t gfn,
1403283a 2040 pfn_t pfn, bool speculative,
9bdbba13 2041 bool host_writable)
1e73f9dd
MT		 2042{
2043 int was_rmapped = 0;
53a27b39 2044 int rmap_count;
1e73f9dd
MT		 2045
2046 pgprintk("%s: spte %llx access %x write_fault %d"
9ad17b10 2047 " user_fault %d gfn %llx\n",
d555c333 2048 __func__, *sptep, pt_access,
1e73f9dd
MT		 2049 write_fault, user_fault, gfn);
2050
d555c333 2051 if (is_rmap_spte(*sptep)) {
1e73f9dd
MT		 2052 /*
2053 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2054 * the parent of the now unreachable PTE.
2055 */
852e3c19
JR		 2056 if (level > PT_PAGE_TABLE_LEVEL &&
2057 !is_large_pte(*sptep)) {
1e73f9dd 2058 struct kvm_mmu_page *child;
d555c333 2059 u64 pte = *sptep;
1e73f9dd
MT		 2060
2061 child = page_header(pte & PT64_BASE_ADDR_MASK);
bcdd9a93 2062 drop_parent_pte(child, sptep);
3be2264b 2063 kvm_flush_remote_tlbs(vcpu->kvm);
d555c333 2064 } else if (pfn != spte_to_pfn(*sptep)) {
9ad17b10 2065 pgprintk("hfn old %llx new %llx\n",
d555c333 2066 spte_to_pfn(*sptep), pfn);
be38d276 2067 drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte);
91546356 2068 kvm_flush_remote_tlbs(vcpu->kvm);
6bed6b9e
JR		 2069 } else
2070 was_rmapped = 1;
1e73f9dd 2071 }
852e3c19 2072
d555c333 2073 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
1403283a 2074 dirty, level, gfn, pfn, speculative, true,
9bdbba13 2075 host_writable)) {
1e73f9dd
MT		 2076 if (write_fault)
2077 *ptwrite = 1;
5304efde 2078 kvm_mmu_flush_tlb(vcpu);
a378b4e6 2079 }
1e73f9dd 2080
d555c333 2081 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
9ad17b10 2082 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
d555c333 2083 is_large_pte(*sptep)? "2MB" : "4kB",
a205bc19
JR		 2084 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2085 *sptep, sptep);
d555c333 2086 if (!was_rmapped && is_large_pte(*sptep))
05da4558
MT		 2087 ++vcpu->kvm->stat.lpages;
2088
d555c333 2089 page_header_update_slot(vcpu->kvm, sptep, gfn);
1c4f1fd6 2090 if (!was_rmapped) {
44ad9944 2091 rmap_count = rmap_add(vcpu, sptep, gfn);
53a27b39 2092 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
852e3c19 2093 rmap_recycle(vcpu, sptep, gfn);
1c4f1fd6 2094 }
9ed5520d 2095 kvm_release_pfn_clean(pfn);
1b7fcd32 2096 if (speculative) {
d555c333 2097 vcpu->arch.last_pte_updated = sptep;
1b7fcd32
AK		 2098 vcpu->arch.last_pte_gfn = gfn;
2099 }
1c4f1fd6
AK		 2100}
2101
6aa8b732
AK		 2102static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2103{
2104}
2105
957ed9ef
XG		 2106static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2107 bool no_dirty_log)
2108{
2109 struct kvm_memory_slot *slot;
2110 unsigned long hva;
2111
5d163b1c 2112 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
957ed9ef
XG		 2113 if (!slot) {
2114 get_page(bad_page);
2115 return page_to_pfn(bad_page);
2116 }
2117
2118 hva = gfn_to_hva_memslot(slot, gfn);
2119
2120 return hva_to_pfn_atomic(vcpu->kvm, hva);
2121}
2122
2123static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2124 struct kvm_mmu_page *sp,
2125 u64 *start, u64 *end)
2126{
2127 struct page *pages[PTE_PREFETCH_NUM];
2128 unsigned access = sp->role.access;
2129 int i, ret;
2130 gfn_t gfn;
2131
2132 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
5d163b1c 2133 if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
957ed9ef
XG		 2134 return -1;
2135
2136 ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2137 if (ret <= 0)
2138 return -1;
2139
2140 for (i = 0; i < ret; i++, gfn++, start++)
2141 mmu_set_spte(vcpu, start, ACC_ALL,
2142 access, 0, 0, 1, NULL,
2143 sp->role.level, gfn,
2144 page_to_pfn(pages[i]), true, true);
2145
2146 return 0;
2147}
2148
2149static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2150 struct kvm_mmu_page *sp, u64 *sptep)
2151{
2152 u64 *spte, *start = NULL;
2153 int i;
2154
2155 WARN_ON(!sp->role.direct);
2156
2157 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2158 spte = sp->spt + i;
2159
2160 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2161 if (*spte != shadow_trap_nonpresent_pte || spte == sptep) {
2162 if (!start)
2163 continue;
2164 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2165 break;
2166 start = NULL;
2167 } else if (!start)
2168 start = spte;
2169 }
2170}
2171
2172static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2173{
2174 struct kvm_mmu_page *sp;
2175
2176 /*
2177 * Since it's no accessed bit on EPT, it's no way to
2178 * distinguish between actually accessed translations
2179 * and prefetched, so disable pte prefetch if EPT is
2180 * enabled.
2181 */
2182 if (!shadow_accessed_mask)
2183 return;
2184
2185 sp = page_header(__pa(sptep));
2186 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2187 return;
2188
2189 __direct_pte_prefetch(vcpu, sp, sptep);
2190}
2191
9f652d21 2192static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2ec4739d
XG		 2193 int map_writable, int level, gfn_t gfn, pfn_t pfn,
2194 bool prefault)
140754bc 2195{
9f652d21 2196 struct kvm_shadow_walk_iterator iterator;
140754bc 2197 struct kvm_mmu_page *sp;
9f652d21 2198 int pt_write = 0;
140754bc 2199 gfn_t pseudo_gfn;
6aa8b732 2200
9f652d21 2201 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
852e3c19 2202 if (iterator.level == level) {
612819c3
MT		 2203 unsigned pte_access = ACC_ALL;
2204
612819c3 2205 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, pte_access,
9f652d21 2206 0, write, 1, &pt_write,
2ec4739d 2207 level, gfn, pfn, prefault, map_writable);
957ed9ef 2208 direct_pte_prefetch(vcpu, iterator.sptep);
9f652d21
AK		 2209 ++vcpu->stat.pf_fixed;
2210 break;
6aa8b732
AK		 2211 }
2212
9f652d21 2213 if (*iterator.sptep == shadow_trap_nonpresent_pte) {
c9fa0b3b
LJ		 2214 u64 base_addr = iterator.addr;
2215
2216 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2217 pseudo_gfn = base_addr >> PAGE_SHIFT;
9f652d21
AK		 2218 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2219 iterator.level - 1,
2220 1, ACC_ALL, iterator.sptep);
2221 if (!sp) {
2222 pgprintk("nonpaging_map: ENOMEM\n");
2223 kvm_release_pfn_clean(pfn);
2224 return -ENOMEM;
2225 }
140754bc 2226
d555c333
AK		 2227 __set_spte(iterator.sptep,
2228 __pa(sp->spt)
2229 | PT_PRESENT_MASK | PT_WRITABLE_MASK
33f91edb
XG		 2230 | shadow_user_mask | shadow_x_mask
2231 | shadow_accessed_mask);
9f652d21
AK		 2232 }
2233 }
2234 return pt_write;
6aa8b732
AK		 2235}
2236
77db5cbd 2237static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
bf998156 2238{
77db5cbd
HY		 2239 siginfo_t info;
2240
2241 info.si_signo = SIGBUS;
2242 info.si_errno = 0;
2243 info.si_code = BUS_MCEERR_AR;
2244 info.si_addr = (void __user *)address;
2245 info.si_addr_lsb = PAGE_SHIFT;
bf998156 2246
77db5cbd 2247 send_sig_info(SIGBUS, &info, tsk);
bf998156
HY		 2248}
2249
2250static int kvm_handle_bad_page(struct kvm *kvm, gfn_t gfn, pfn_t pfn)
2251{
2252 kvm_release_pfn_clean(pfn);
2253 if (is_hwpoison_pfn(pfn)) {
77db5cbd 2254 kvm_send_hwpoison_signal(gfn_to_hva(kvm, gfn), current);
bf998156 2255 return 0;
edba23e5
GN		 2256 } else if (is_fault_pfn(pfn))
2257 return -EFAULT;
2258
bf998156
HY		 2259 return 1;
2260}
2261
936a5fe6
AA		 2262static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2263 gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2264{
2265 pfn_t pfn = *pfnp;
2266 gfn_t gfn = *gfnp;
2267 int level = *levelp;
2268
2269 /*
2270 * Check if it's a transparent hugepage. If this would be an
2271 * hugetlbfs page, level wouldn't be set to
2272 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2273 * here.
2274 */
2275 if (!is_error_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2276 level == PT_PAGE_TABLE_LEVEL &&
2277 PageTransCompound(pfn_to_page(pfn)) &&
2278 !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2279 unsigned long mask;
2280 /*
2281 * mmu_notifier_retry was successful and we hold the
2282 * mmu_lock here, so the pmd can't become splitting
2283 * from under us, and in turn
2284 * __split_huge_page_refcount() can't run from under
2285 * us and we can safely transfer the refcount from
2286 * PG_tail to PG_head as we switch the pfn to tail to
2287 * head.
2288 */
2289 *levelp = level = PT_DIRECTORY_LEVEL;
2290 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2291 VM_BUG_ON((gfn & mask) != (pfn & mask));
2292 if (pfn & mask) {
2293 gfn &= ~mask;
2294 *gfnp = gfn;
2295 kvm_release_pfn_clean(pfn);
2296 pfn &= ~mask;
2297 if (!get_page_unless_zero(pfn_to_page(pfn)))
2298 BUG();
2299 *pfnp = pfn;
2300 }
2301 }
2302}
2303
78b2c54a 2304static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
060c2abe
XG		 2305 gva_t gva, pfn_t *pfn, bool write, bool *writable);
2306
2307static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn,
78b2c54a 2308 bool prefault)
10589a46
MT		 2309{
2310 int r;
852e3c19 2311 int level;
936a5fe6 2312 int force_pt_level;
35149e21 2313 pfn_t pfn;
e930bffe 2314 unsigned long mmu_seq;
612819c3 2315 bool map_writable;
aaee2c94 2316
936a5fe6
AA		 2317 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2318 if (likely(!force_pt_level)) {
2319 level = mapping_level(vcpu, gfn);
2320 /*
2321 * This path builds a PAE pagetable - so we can map
2322 * 2mb pages at maximum. Therefore check if the level
2323 * is larger than that.
2324 */
2325 if (level > PT_DIRECTORY_LEVEL)
2326 level = PT_DIRECTORY_LEVEL;
852e3c19 2327
936a5fe6
AA		 2328 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2329 } else
2330 level = PT_PAGE_TABLE_LEVEL;
05da4558 2331
e930bffe 2332 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2333 smp_rmb();
060c2abe 2334
78b2c54a 2335 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
060c2abe 2336 return 0;
aaee2c94 2337
d196e343 2338 /* mmio */
bf998156
HY		 2339 if (is_error_pfn(pfn))
2340 return kvm_handle_bad_page(vcpu->kvm, gfn, pfn);
d196e343 2341
aaee2c94 2342 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2343 if (mmu_notifier_retry(vcpu, mmu_seq))
2344 goto out_unlock;
eb787d10 2345 kvm_mmu_free_some_pages(vcpu);
936a5fe6
AA		 2346 if (likely(!force_pt_level))
2347 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2ec4739d
XG		 2348 r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2349 prefault);
aaee2c94
MT		 2350 spin_unlock(&vcpu->kvm->mmu_lock);
2351
aaee2c94 2352
10589a46 2353 return r;
e930bffe
AA		 2354
2355out_unlock:
2356 spin_unlock(&vcpu->kvm->mmu_lock);
2357 kvm_release_pfn_clean(pfn);
2358 return 0;
10589a46
MT		 2359}
2360
2361
17ac10ad
AK		 2362static void mmu_free_roots(struct kvm_vcpu *vcpu)
2363{
2364 int i;
4db35314 2365 struct kvm_mmu_page *sp;
d98ba053 2366 LIST_HEAD(invalid_list);
17ac10ad 2367
ad312c7c 2368 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
7b53aa56 2369 return;
aaee2c94 2370 spin_lock(&vcpu->kvm->mmu_lock);
81407ca5
JR		 2371 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2372 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2373 vcpu->arch.mmu.direct_map)) {
ad312c7c 2374 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad 2375
4db35314
AK		 2376 sp = page_header(root);
2377 --sp->root_count;
d98ba053
XG		 2378 if (!sp->root_count && sp->role.invalid) {
2379 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2380 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2381 }
ad312c7c 2382 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
aaee2c94 2383 spin_unlock(&vcpu->kvm->mmu_lock);
17ac10ad
AK		 2384 return;
2385 }
17ac10ad 2386 for (i = 0; i < 4; ++i) {
ad312c7c 2387 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad 2388
417726a3 2389 if (root) {
417726a3 2390 root &= PT64_BASE_ADDR_MASK;
4db35314
AK		 2391 sp = page_header(root);
2392 --sp->root_count;
2e53d63a 2393 if (!sp->root_count && sp->role.invalid)
d98ba053
XG		 2394 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2395 &invalid_list);
417726a3 2396 }
ad312c7c 2397 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 2398 }
d98ba053 2399 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
aaee2c94 2400 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 2401 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
17ac10ad
AK		 2402}
2403
8986ecc0
MT		 2404static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2405{
2406 int ret = 0;
2407
2408 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
a8eeb04a 2409 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
8986ecc0
MT		 2410 ret = 1;
2411 }
2412
2413 return ret;
2414}
2415
651dd37a
JR		 2416static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
2417{
2418 struct kvm_mmu_page *sp;
7ebaf15e 2419 unsigned i;
651dd37a
JR		 2420
2421 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2422 spin_lock(&vcpu->kvm->mmu_lock);
2423 kvm_mmu_free_some_pages(vcpu);
2424 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
2425 1, ACC_ALL, NULL);
2426 ++sp->root_count;
2427 spin_unlock(&vcpu->kvm->mmu_lock);
2428 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
2429 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
2430 for (i = 0; i < 4; ++i) {
2431 hpa_t root = vcpu->arch.mmu.pae_root[i];
2432
2433 ASSERT(!VALID_PAGE(root));
2434 spin_lock(&vcpu->kvm->mmu_lock);
2435 kvm_mmu_free_some_pages(vcpu);
649497d1
AK		 2436 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
2437 i << 30,
651dd37a
JR		 2438 PT32_ROOT_LEVEL, 1, ACC_ALL,
2439 NULL);
2440 root = __pa(sp->spt);
2441 ++sp->root_count;
2442 spin_unlock(&vcpu->kvm->mmu_lock);
2443 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
651dd37a 2444 }
6292757f 2445 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
651dd37a
JR		 2446 } else
2447 BUG();
2448
2449 return 0;
2450}
2451
2452static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
17ac10ad 2453{
4db35314 2454 struct kvm_mmu_page *sp;
81407ca5
JR		 2455 u64 pdptr, pm_mask;
2456 gfn_t root_gfn;
2457 int i;
3bb65a22 2458
5777ed34 2459 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
17ac10ad 2460
651dd37a
JR		 2461 if (mmu_check_root(vcpu, root_gfn))
2462 return 1;
2463
2464 /*
2465 * Do we shadow a long mode page table? If so we need to
2466 * write-protect the guests page table root.
2467 */
2468 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
ad312c7c 2469 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad
AK		 2470
2471 ASSERT(!VALID_PAGE(root));
651dd37a 2472
8facbbff 2473 spin_lock(&vcpu->kvm->mmu_lock);
24955b6c 2474 kvm_mmu_free_some_pages(vcpu);
651dd37a
JR		 2475 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
2476 0, ACC_ALL, NULL);
4db35314
AK		 2477 root = __pa(sp->spt);
2478 ++sp->root_count;
8facbbff 2479 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 2480 vcpu->arch.mmu.root_hpa = root;
8986ecc0 2481 return 0;
17ac10ad 2482 }
f87f9288 2483
651dd37a
JR		 2484 /*
2485 * We shadow a 32 bit page table. This may be a legacy 2-level
81407ca5
JR		 2486 * or a PAE 3-level page table. In either case we need to be aware that
2487 * the shadow page table may be a PAE or a long mode page table.
651dd37a 2488 */
81407ca5
JR		 2489 pm_mask = PT_PRESENT_MASK;
2490 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
2491 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
2492
17ac10ad 2493 for (i = 0; i < 4; ++i) {
ad312c7c 2494 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad
AK		 2495
2496 ASSERT(!VALID_PAGE(root));
ad312c7c 2497 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
d41d1895 2498 pdptr = kvm_pdptr_read_mmu(vcpu, &vcpu->arch.mmu, i);
43a3795a 2499 if (!is_present_gpte(pdptr)) {
ad312c7c 2500 vcpu->arch.mmu.pae_root[i] = 0;
417726a3
AK		 2501 continue;
2502 }
6de4f3ad 2503 root_gfn = pdptr >> PAGE_SHIFT;
f87f9288
JR		 2504 if (mmu_check_root(vcpu, root_gfn))
2505 return 1;
5a7388c2 2506 }
8facbbff 2507 spin_lock(&vcpu->kvm->mmu_lock);
24955b6c 2508 kvm_mmu_free_some_pages(vcpu);
4db35314 2509 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
651dd37a 2510 PT32_ROOT_LEVEL, 0,
f7d9c7b7 2511 ACC_ALL, NULL);
4db35314
AK		 2512 root = __pa(sp->spt);
2513 ++sp->root_count;
8facbbff
AK		 2514 spin_unlock(&vcpu->kvm->mmu_lock);
2515
81407ca5 2516 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
17ac10ad 2517 }
6292757f 2518 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
81407ca5
JR		 2519
2520 /*
2521 * If we shadow a 32 bit page table with a long mode page
2522 * table we enter this path.
2523 */
2524 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2525 if (vcpu->arch.mmu.lm_root == NULL) {
2526 /*
2527 * The additional page necessary for this is only
2528 * allocated on demand.
2529 */
2530
2531 u64 *lm_root;
2532
2533 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
2534 if (lm_root == NULL)
2535 return 1;
2536
2537 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
2538
2539 vcpu->arch.mmu.lm_root = lm_root;
2540 }
2541
2542 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
2543 }
2544
8986ecc0 2545 return 0;
17ac10ad
AK		 2546}
2547
651dd37a
JR		 2548static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
2549{
2550 if (vcpu->arch.mmu.direct_map)
2551 return mmu_alloc_direct_roots(vcpu);
2552 else
2553 return mmu_alloc_shadow_roots(vcpu);
2554}
2555
0ba73cda
MT		 2556static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2557{
2558 int i;
2559 struct kvm_mmu_page *sp;
2560
81407ca5
JR		 2561 if (vcpu->arch.mmu.direct_map)
2562 return;
2563
0ba73cda
MT		 2564 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2565 return;
6903074c
XG		 2566
2567 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
81407ca5 2568 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
0ba73cda
MT		 2569 hpa_t root = vcpu->arch.mmu.root_hpa;
2570 sp = page_header(root);
2571 mmu_sync_children(vcpu, sp);
5054c0de 2572 trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
0ba73cda
MT		 2573 return;
2574 }
2575 for (i = 0; i < 4; ++i) {
2576 hpa_t root = vcpu->arch.mmu.pae_root[i];
2577
8986ecc0 2578 if (root && VALID_PAGE(root)) {
0ba73cda
MT		 2579 root &= PT64_BASE_ADDR_MASK;
2580 sp = page_header(root);
2581 mmu_sync_children(vcpu, sp);
2582 }
2583 }
6903074c 2584 trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
0ba73cda
MT		 2585}
2586
2587void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2588{
2589 spin_lock(&vcpu->kvm->mmu_lock);
2590 mmu_sync_roots(vcpu);
6cffe8ca 2591 spin_unlock(&vcpu->kvm->mmu_lock);
0ba73cda
MT		 2592}
2593
1871c602 2594static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
ab9ae313 2595 u32 access, struct x86_exception *exception)
6aa8b732 2596{
ab9ae313
AK		 2597 if (exception)
2598 exception->error_code = 0;
6aa8b732
AK		 2599 return vaddr;
2600}
2601
6539e738 2602static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
ab9ae313
AK		 2603 u32 access,
2604 struct x86_exception *exception)
6539e738 2605{
ab9ae313
AK		 2606 if (exception)
2607 exception->error_code = 0;
6539e738
JR		 2608 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
2609}
2610
6aa8b732 2611static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
78b2c54a 2612 u32 error_code, bool prefault)
6aa8b732 2613{
e833240f 2614 gfn_t gfn;
e2dec939 2615 int r;
6aa8b732 2616
b8688d51 2617 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
e2dec939
AK		 2618 r = mmu_topup_memory_caches(vcpu);
2619 if (r)
2620 return r;
714b93da 2621
6aa8b732 2622 ASSERT(vcpu);
ad312c7c 2623 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 2624
e833240f 2625 gfn = gva >> PAGE_SHIFT;
6aa8b732 2626
e833240f 2627 return nonpaging_map(vcpu, gva & PAGE_MASK,
78b2c54a 2628 error_code & PFERR_WRITE_MASK, gfn, prefault);
6aa8b732
AK		 2629}
2630
7e1fbeac 2631static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
af585b92
GN		 2632{
2633 struct kvm_arch_async_pf arch;
fb67e14f 2634
7c90705b 2635 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
af585b92 2636 arch.gfn = gfn;
c4806acd 2637 arch.direct_map = vcpu->arch.mmu.direct_map;
fb67e14f 2638 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
af585b92
GN		 2639
2640 return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
2641}
2642
2643static bool can_do_async_pf(struct kvm_vcpu *vcpu)
2644{
2645 if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
2646 kvm_event_needs_reinjection(vcpu)))
2647 return false;
2648
2649 return kvm_x86_ops->interrupt_allowed(vcpu);
2650}
2651
78b2c54a 2652static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
612819c3 2653 gva_t gva, pfn_t *pfn, bool write, bool *writable)
af585b92
GN		 2654{
2655 bool async;
2656
612819c3 2657 *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
af585b92
GN		 2658
2659 if (!async)
2660 return false; /* *pfn has correct page already */
2661
2662 put_page(pfn_to_page(*pfn));
2663
78b2c54a 2664 if (!prefault && can_do_async_pf(vcpu)) {
c9b263d2 2665 trace_kvm_try_async_get_page(gva, gfn);
af585b92
GN		 2666 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
2667 trace_kvm_async_pf_doublefault(gva, gfn);
2668 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
2669 return true;
2670 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
2671 return true;
2672 }
2673
612819c3 2674 *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
af585b92
GN		 2675
2676 return false;
2677}
2678
56028d08 2679static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
78b2c54a 2680 bool prefault)
fb72d167 2681{
35149e21 2682 pfn_t pfn;
fb72d167 2683 int r;
852e3c19 2684 int level;
936a5fe6 2685 int force_pt_level;
05da4558 2686 gfn_t gfn = gpa >> PAGE_SHIFT;
e930bffe 2687 unsigned long mmu_seq;
612819c3
MT		 2688 int write = error_code & PFERR_WRITE_MASK;
2689 bool map_writable;
fb72d167
JR		 2690
2691 ASSERT(vcpu);
2692 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2693
2694 r = mmu_topup_memory_caches(vcpu);
2695 if (r)
2696 return r;
2697
936a5fe6
AA		 2698 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2699 if (likely(!force_pt_level)) {
2700 level = mapping_level(vcpu, gfn);
2701 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2702 } else
2703 level = PT_PAGE_TABLE_LEVEL;
852e3c19 2704
e930bffe 2705 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 2706 smp_rmb();
af585b92 2707
78b2c54a 2708 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
af585b92
GN		 2709 return 0;
2710
2711 /* mmio */
bf998156
HY		 2712 if (is_error_pfn(pfn))
2713 return kvm_handle_bad_page(vcpu->kvm, gfn, pfn);
fb72d167 2714 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA		 2715 if (mmu_notifier_retry(vcpu, mmu_seq))
2716 goto out_unlock;
fb72d167 2717 kvm_mmu_free_some_pages(vcpu);
936a5fe6
AA		 2718 if (likely(!force_pt_level))
2719 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
612819c3 2720 r = __direct_map(vcpu, gpa, write, map_writable,
2ec4739d 2721 level, gfn, pfn, prefault);
fb72d167 2722 spin_unlock(&vcpu->kvm->mmu_lock);
fb72d167
JR		 2723
2724 return r;
e930bffe
AA		 2725
2726out_unlock:
2727 spin_unlock(&vcpu->kvm->mmu_lock);
2728 kvm_release_pfn_clean(pfn);
2729 return 0;
fb72d167
JR		 2730}
2731
6aa8b732
AK		 2732static void nonpaging_free(struct kvm_vcpu *vcpu)
2733{
17ac10ad 2734 mmu_free_roots(vcpu);
6aa8b732
AK		 2735}
2736
52fde8df
JR		 2737static int nonpaging_init_context(struct kvm_vcpu *vcpu,
2738 struct kvm_mmu *context)
6aa8b732 2739{
6aa8b732
AK		 2740 context->new_cr3 = nonpaging_new_cr3;
2741 context->page_fault = nonpaging_page_fault;
6aa8b732
AK		 2742 context->gva_to_gpa = nonpaging_gva_to_gpa;
2743 context->free = nonpaging_free;
c7addb90 2744 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2745 context->sync_page = nonpaging_sync_page;
a7052897 2746 context->invlpg = nonpaging_invlpg;
0f53b5b1 2747 context->update_pte = nonpaging_update_pte;
cea0f0e7 2748 context->root_level = 0;
6aa8b732 2749 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2750 context->root_hpa = INVALID_PAGE;
c5a78f2b 2751 context->direct_map = true;
2d48a985 2752 context->nx = false;
6aa8b732
AK		 2753 return 0;
2754}
2755
d835dfec 2756void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
6aa8b732 2757{
1165f5fe 2758 ++vcpu->stat.tlb_flush;
a8eeb04a 2759 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
6aa8b732
AK		 2760}
2761
2762static void paging_new_cr3(struct kvm_vcpu *vcpu)
2763{
9f8fe504 2764 pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu));
cea0f0e7 2765 mmu_free_roots(vcpu);
6aa8b732
AK		 2766}
2767
5777ed34
JR		 2768static unsigned long get_cr3(struct kvm_vcpu *vcpu)
2769{
9f8fe504 2770 return kvm_read_cr3(vcpu);
5777ed34
JR		 2771}
2772
6389ee94
AK		 2773static void inject_page_fault(struct kvm_vcpu *vcpu,
2774 struct x86_exception *fault)
6aa8b732 2775{
6389ee94 2776 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
6aa8b732
AK		 2777}
2778
6aa8b732
AK		 2779static void paging_free(struct kvm_vcpu *vcpu)
2780{
2781 nonpaging_free(vcpu);
2782}
2783
3241f22d 2784static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
82725b20
DE		 2785{
2786 int bit7;
2787
2788 bit7 = (gpte >> 7) & 1;
3241f22d 2789 return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
82725b20
DE		 2790}
2791
6aa8b732
AK		 2792#define PTTYPE 64
2793#include "paging_tmpl.h"
2794#undef PTTYPE
2795
2796#define PTTYPE 32
2797#include "paging_tmpl.h"
2798#undef PTTYPE
2799
52fde8df
JR		 2800static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
2801 struct kvm_mmu *context,
2802 int level)
82725b20 2803{
82725b20
DE		 2804 int maxphyaddr = cpuid_maxphyaddr(vcpu);
2805 u64 exb_bit_rsvd = 0;
2806
2d48a985 2807 if (!context->nx)
82725b20
DE		 2808 exb_bit_rsvd = rsvd_bits(63, 63);
2809 switch (level) {
2810 case PT32_ROOT_LEVEL:
2811 /* no rsvd bits for 2 level 4K page table entries */
2812 context->rsvd_bits_mask[0][1] = 0;
2813 context->rsvd_bits_mask[0][0] = 0;
f815bce8
XG		 2814 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
2815
2816 if (!is_pse(vcpu)) {
2817 context->rsvd_bits_mask[1][1] = 0;
2818 break;
2819 }
2820
82725b20
DE		 2821 if (is_cpuid_PSE36())
2822 /* 36bits PSE 4MB page */
2823 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
2824 else
2825 /* 32 bits PSE 4MB page */
2826 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
82725b20
DE		 2827 break;
2828 case PT32E_ROOT_LEVEL:
20c466b5
DE		 2829 context->rsvd_bits_mask[0][2] =
2830 rsvd_bits(maxphyaddr, 63) |
2831 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
82725b20 2832 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2833 rsvd_bits(maxphyaddr, 62); /* PDE */
82725b20
DE		 2834 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2835 rsvd_bits(maxphyaddr, 62); /* PTE */
2836 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2837 rsvd_bits(maxphyaddr, 62) |
2838 rsvd_bits(13, 20); /* large page */
f815bce8 2839 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
82725b20
DE		 2840 break;
2841 case PT64_ROOT_LEVEL:
2842 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
2843 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2844 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
2845 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2846 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
4c26b4cd 2847 rsvd_bits(maxphyaddr, 51);
82725b20
DE		 2848 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2849 rsvd_bits(maxphyaddr, 51);
2850 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
e04da980
JR		 2851 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
2852 rsvd_bits(maxphyaddr, 51) |
2853 rsvd_bits(13, 29);
82725b20 2854 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
4c26b4cd
SY		 2855 rsvd_bits(maxphyaddr, 51) |
2856 rsvd_bits(13, 20); /* large page */
f815bce8 2857 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
82725b20
DE		 2858 break;
2859 }
2860}
2861
52fde8df
JR		 2862static int paging64_init_context_common(struct kvm_vcpu *vcpu,
2863 struct kvm_mmu *context,
2864 int level)
6aa8b732 2865{
2d48a985
JR		 2866 context->nx = is_nx(vcpu);
2867
52fde8df 2868 reset_rsvds_bits_mask(vcpu, context, level);
6aa8b732
AK		 2869
2870 ASSERT(is_pae(vcpu));
2871 context->new_cr3 = paging_new_cr3;
2872 context->page_fault = paging64_page_fault;
6aa8b732 2873 context->gva_to_gpa = paging64_gva_to_gpa;
c7addb90 2874 context->prefetch_page = paging64_prefetch_page;
e8bc217a 2875 context->sync_page = paging64_sync_page;
a7052897 2876 context->invlpg = paging64_invlpg;
0f53b5b1 2877 context->update_pte = paging64_update_pte;
6aa8b732 2878 context->free = paging_free;
17ac10ad
AK		 2879 context->root_level = level;
2880 context->shadow_root_level = level;
17c3ba9d 2881 context->root_hpa = INVALID_PAGE;
c5a78f2b 2882 context->direct_map = false;
6aa8b732
AK		 2883 return 0;
2884}
2885
52fde8df
JR		 2886static int paging64_init_context(struct kvm_vcpu *vcpu,
2887 struct kvm_mmu *context)
17ac10ad 2888{
52fde8df 2889 return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
17ac10ad
AK		 2890}
2891
52fde8df
JR		 2892static int paging32_init_context(struct kvm_vcpu *vcpu,
2893 struct kvm_mmu *context)
6aa8b732 2894{
2d48a985
JR		 2895 context->nx = false;
2896
52fde8df 2897 reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
6aa8b732
AK		 2898
2899 context->new_cr3 = paging_new_cr3;
2900 context->page_fault = paging32_page_fault;
6aa8b732
AK		 2901 context->gva_to_gpa = paging32_gva_to_gpa;
2902 context->free = paging_free;
c7addb90 2903 context->prefetch_page = paging32_prefetch_page;
e8bc217a 2904 context->sync_page = paging32_sync_page;
a7052897 2905 context->invlpg = paging32_invlpg;
0f53b5b1 2906 context->update_pte = paging32_update_pte;
6aa8b732
AK		 2907 context->root_level = PT32_ROOT_LEVEL;
2908 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 2909 context->root_hpa = INVALID_PAGE;
c5a78f2b 2910 context->direct_map = false;
6aa8b732
AK		 2911 return 0;
2912}
2913
52fde8df
JR		 2914static int paging32E_init_context(struct kvm_vcpu *vcpu,
2915 struct kvm_mmu *context)
6aa8b732 2916{
52fde8df 2917 return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
6aa8b732
AK		 2918}
2919
fb72d167
JR		 2920static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
2921{
14dfe855 2922 struct kvm_mmu *context = vcpu->arch.walk_mmu;
fb72d167 2923
c445f8ef 2924 context->base_role.word = 0;
fb72d167
JR		 2925 context->new_cr3 = nonpaging_new_cr3;
2926 context->page_fault = tdp_page_fault;
2927 context->free = nonpaging_free;
2928 context->prefetch_page = nonpaging_prefetch_page;
e8bc217a 2929 context->sync_page = nonpaging_sync_page;
a7052897 2930 context->invlpg = nonpaging_invlpg;
0f53b5b1 2931 context->update_pte = nonpaging_update_pte;
67253af5 2932 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
fb72d167 2933 context->root_hpa = INVALID_PAGE;
c5a78f2b 2934 context->direct_map = true;
1c97f0a0 2935 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
5777ed34 2936 context->get_cr3 = get_cr3;
cb659db8 2937 context->inject_page_fault = kvm_inject_page_fault;
2d48a985 2938 context->nx = is_nx(vcpu);
fb72d167
JR		 2939
2940 if (!is_paging(vcpu)) {
2d48a985 2941 context->nx = false;
fb72d167
JR		 2942 context->gva_to_gpa = nonpaging_gva_to_gpa;
2943 context->root_level = 0;
2944 } else if (is_long_mode(vcpu)) {
2d48a985 2945 context->nx = is_nx(vcpu);
52fde8df 2946 reset_rsvds_bits_mask(vcpu, context, PT64_ROOT_LEVEL);
fb72d167
JR		 2947 context->gva_to_gpa = paging64_gva_to_gpa;
2948 context->root_level = PT64_ROOT_LEVEL;
2949 } else if (is_pae(vcpu)) {
2d48a985 2950 context->nx = is_nx(vcpu);
52fde8df 2951 reset_rsvds_bits_mask(vcpu, context, PT32E_ROOT_LEVEL);
fb72d167
JR		 2952 context->gva_to_gpa = paging64_gva_to_gpa;
2953 context->root_level = PT32E_ROOT_LEVEL;
2954 } else {
2d48a985 2955 context->nx = false;
52fde8df 2956 reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
fb72d167
JR		 2957 context->gva_to_gpa = paging32_gva_to_gpa;
2958 context->root_level = PT32_ROOT_LEVEL;
2959 }
2960
2961 return 0;
2962}
2963
52fde8df 2964int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
6aa8b732 2965{
a770f6f2 2966 int r;
411c588d 2967 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
6aa8b732 2968 ASSERT(vcpu);
ad312c7c 2969 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732
AK		 2970
2971 if (!is_paging(vcpu))
52fde8df 2972 r = nonpaging_init_context(vcpu, context);
a9058ecd 2973 else if (is_long_mode(vcpu))
52fde8df 2974 r = paging64_init_context(vcpu, context);
6aa8b732 2975 else if (is_pae(vcpu))
52fde8df 2976 r = paging32E_init_context(vcpu, context);
6aa8b732 2977 else
52fde8df 2978 r = paging32_init_context(vcpu, context);
a770f6f2 2979
5b7e0102 2980 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
f43addd4 2981 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
411c588d
AK		 2982 vcpu->arch.mmu.base_role.smep_andnot_wp
2983 = smep && !is_write_protection(vcpu);
52fde8df
JR		 2984
2985 return r;
2986}
2987EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
2988
2989static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
2990{
14dfe855 2991 int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
52fde8df 2992
14dfe855
JR		 2993 vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3;
2994 vcpu->arch.walk_mmu->get_cr3 = get_cr3;
2995 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
a770f6f2
AK		 2996
2997 return r;
6aa8b732
AK		 2998}
2999
02f59dc9
JR		 3000static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
3001{
3002 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
3003
3004 g_context->get_cr3 = get_cr3;
3005 g_context->inject_page_fault = kvm_inject_page_fault;
3006
3007 /*
3008 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3009 * translation of l2_gpa to l1_gpa addresses is done using the
3010 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3011 * functions between mmu and nested_mmu are swapped.
3012 */
3013 if (!is_paging(vcpu)) {
2d48a985 3014 g_context->nx = false;
02f59dc9
JR		 3015 g_context->root_level = 0;
3016 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3017 } else if (is_long_mode(vcpu)) {
2d48a985 3018 g_context->nx = is_nx(vcpu);
02f59dc9
JR		 3019 reset_rsvds_bits_mask(vcpu, g_context, PT64_ROOT_LEVEL);
3020 g_context->root_level = PT64_ROOT_LEVEL;
3021 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3022 } else if (is_pae(vcpu)) {
2d48a985 3023 g_context->nx = is_nx(vcpu);
02f59dc9
JR		 3024 reset_rsvds_bits_mask(vcpu, g_context, PT32E_ROOT_LEVEL);
3025 g_context->root_level = PT32E_ROOT_LEVEL;
3026 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3027 } else {
2d48a985 3028 g_context->nx = false;
02f59dc9
JR		 3029 reset_rsvds_bits_mask(vcpu, g_context, PT32_ROOT_LEVEL);
3030 g_context->root_level = PT32_ROOT_LEVEL;
3031 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3032 }
3033
3034 return 0;
3035}
3036
fb72d167
JR		 3037static int init_kvm_mmu(struct kvm_vcpu *vcpu)
3038{
02f59dc9
JR		 3039 if (mmu_is_nested(vcpu))
3040 return init_kvm_nested_mmu(vcpu);
3041 else if (tdp_enabled)
fb72d167
JR		 3042 return init_kvm_tdp_mmu(vcpu);
3043 else
3044 return init_kvm_softmmu(vcpu);
3045}
3046
6aa8b732
AK		 3047static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
3048{
3049 ASSERT(vcpu);
62ad0755
SY		 3050 if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
3051 /* mmu.free() should set root_hpa = INVALID_PAGE */
ad312c7c 3052 vcpu->arch.mmu.free(vcpu);
6aa8b732
AK		 3053}
3054
3055int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
17c3ba9d
AK		 3056{
3057 destroy_kvm_mmu(vcpu);
f8f7e5ee 3058 return init_kvm_mmu(vcpu);
17c3ba9d 3059}
8668a3c4 3060EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
17c3ba9d
AK		 3061
3062int kvm_mmu_load(struct kvm_vcpu *vcpu)
6aa8b732 3063{
714b93da
AK		 3064 int r;
3065
e2dec939 3066 r = mmu_topup_memory_caches(vcpu);
17c3ba9d
AK		 3067 if (r)
3068 goto out;
8986ecc0 3069 r = mmu_alloc_roots(vcpu);
8facbbff 3070 spin_lock(&vcpu->kvm->mmu_lock);
0ba73cda 3071 mmu_sync_roots(vcpu);
aaee2c94 3072 spin_unlock(&vcpu->kvm->mmu_lock);
8986ecc0
MT		 3073 if (r)
3074 goto out;
3662cb1c 3075 /* set_cr3() should ensure TLB has been flushed */
f43addd4 3076 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
714b93da
AK		 3077out:
3078 return r;
6aa8b732 3079}
17c3ba9d
AK		 3080EXPORT_SYMBOL_GPL(kvm_mmu_load);
3081
3082void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3083{
3084 mmu_free_roots(vcpu);
3085}
4b16184c 3086EXPORT_SYMBOL_GPL(kvm_mmu_unload);
6aa8b732 3087
0028425f 3088static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
7c562522
XG		 3089 struct kvm_mmu_page *sp, u64 *spte,
3090 const void *new)
0028425f 3091{
30945387 3092 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
7e4e4056
JR		 3093 ++vcpu->kvm->stat.mmu_pde_zapped;
3094 return;
30945387 3095 }
0028425f 3096
4cee5764 3097 ++vcpu->kvm->stat.mmu_pte_updated;
7c562522 3098 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
0028425f
AK		 3099}
3100
79539cec
AK		 3101static bool need_remote_flush(u64 old, u64 new)
3102{
3103 if (!is_shadow_present_pte(old))
3104 return false;
3105 if (!is_shadow_present_pte(new))
3106 return true;
3107 if ((old ^ new) & PT64_BASE_ADDR_MASK)
3108 return true;
3109 old ^= PT64_NX_MASK;
3110 new ^= PT64_NX_MASK;
3111 return (old & ~new & PT64_PERM_MASK) != 0;
3112}
3113
0671a8e7
XG		 3114static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3115 bool remote_flush, bool local_flush)
79539cec 3116{
0671a8e7
XG		 3117 if (zap_page)
3118 return;
3119
3120 if (remote_flush)
79539cec 3121 kvm_flush_remote_tlbs(vcpu->kvm);
0671a8e7 3122 else if (local_flush)
79539cec
AK		 3123 kvm_mmu_flush_tlb(vcpu);
3124}
3125
12b7d28f
AK		 3126static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
3127{
ad312c7c 3128 u64 *spte = vcpu->arch.last_pte_updated;
12b7d28f 3129
7b52345e 3130 return !!(spte && (*spte & shadow_accessed_mask));
12b7d28f
AK		 3131}
3132
1b7fcd32
AK		 3133static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
3134{
3135 u64 *spte = vcpu->arch.last_pte_updated;
3136
3137 if (spte
3138 && vcpu->arch.last_pte_gfn == gfn
3139 && shadow_accessed_mask
3140 && !(*spte & shadow_accessed_mask)
3141 && is_shadow_present_pte(*spte))
3142 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
3143}
3144
09072daf 3145void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
ad218f85
MT		 3146 const u8 *new, int bytes,
3147 bool guest_initiated)
da4a00f0 3148{
9b7a0325 3149 gfn_t gfn = gpa >> PAGE_SHIFT;
fa1de2bf 3150 union kvm_mmu_page_role mask = { .word = 0 };
4db35314 3151 struct kvm_mmu_page *sp;
f41d335a 3152 struct hlist_node *node;
d98ba053 3153 LIST_HEAD(invalid_list);
0f53b5b1
XG		 3154 u64 entry, gentry, *spte;
3155 unsigned pte_size, page_offset, misaligned, quadrant, offset;
3156 int level, npte, invlpg_counter, r, flooded = 0;
0671a8e7
XG		 3157 bool remote_flush, local_flush, zap_page;
3158
332b207d
XG		 3159 /*
3160 * If we don't have indirect shadow pages, it means no page is
3161 * write-protected, so we can exit simply.
3162 */
3163 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
3164 return;
3165
0671a8e7 3166 zap_page = remote_flush = local_flush = false;
0f53b5b1 3167 offset = offset_in_page(gpa);
9b7a0325 3168
b8688d51 3169 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
72016f3a 3170
08e850c6 3171 invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter);
72016f3a
AK		 3172
3173 /*
3174 * Assume that the pte write on a page table of the same type
49b26e26
XG		 3175 * as the current vcpu paging mode since we update the sptes only
3176 * when they have the same mode.
72016f3a 3177 */
08e850c6 3178 if ((is_pae(vcpu) && bytes == 4) || !new) {
72016f3a 3179 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
08e850c6
AK		 3180 if (is_pae(vcpu)) {
3181 gpa &= ~(gpa_t)7;
3182 bytes = 8;
3183 }
3184 r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8));
72016f3a
AK		 3185 if (r)
3186 gentry = 0;
08e850c6
AK		 3187 new = (const u8 *)&gentry;
3188 }
3189
3190 switch (bytes) {
3191 case 4:
3192 gentry = *(const u32 *)new;
3193 break;
3194 case 8:
3195 gentry = *(const u64 *)new;
3196 break;
3197 default:
3198 gentry = 0;
3199 break;
72016f3a
AK		 3200 }
3201
aaee2c94 3202 spin_lock(&vcpu->kvm->mmu_lock);
08e850c6
AK		 3203 if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter)
3204 gentry = 0;
eb787d10 3205 kvm_mmu_free_some_pages(vcpu);
4cee5764 3206 ++vcpu->kvm->stat.mmu_pte_write;
8b1fe17c 3207 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
ad218f85 3208 if (guest_initiated) {
1b7fd45c 3209 kvm_mmu_access_page(vcpu, gfn);
ad218f85
MT		 3210 if (gfn == vcpu->arch.last_pt_write_gfn
3211 && !last_updated_pte_accessed(vcpu)) {
3212 ++vcpu->arch.last_pt_write_count;
3213 if (vcpu->arch.last_pt_write_count >= 3)
3214 flooded = 1;
3215 } else {
3216 vcpu->arch.last_pt_write_gfn = gfn;
3217 vcpu->arch.last_pt_write_count = 1;
3218 vcpu->arch.last_pte_updated = NULL;
3219 }
86a5ba02 3220 }
3246af0e 3221
fa1de2bf 3222 mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
f41d335a 3223 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) {
5b7e0102 3224 pte_size = sp->role.cr4_pae ? 8 : 4;
0e7bc4b9 3225 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
e925c5ba 3226 misaligned |= bytes < 4;
86a5ba02 3227 if (misaligned || flooded) {
0e7bc4b9
AK		 3228 /*
3229 * Misaligned accesses are too much trouble to fix
3230 * up; also, they usually indicate a page is not used
3231 * as a page table.
86a5ba02
AK		 3232 *
3233 * If we're seeing too many writes to a page,
3234 * it may no longer be a page table, or we may be
3235 * forking, in which case it is better to unmap the
3236 * page.
0e7bc4b9
AK		 3237 */
3238 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4db35314 3239 gpa, bytes, sp->role.word);
0671a8e7 3240 zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
f41d335a 3241 &invalid_list);
4cee5764 3242 ++vcpu->kvm->stat.mmu_flooded;
0e7bc4b9
AK		 3243 continue;
3244 }
9b7a0325 3245 page_offset = offset;
4db35314 3246 level = sp->role.level;
ac1b714e 3247 npte = 1;
5b7e0102 3248 if (!sp->role.cr4_pae) {
ac1b714e
AK		 3249 page_offset <<= 1; /* 32->64 */
3250 /*
3251 * A 32-bit pde maps 4MB while the shadow pdes map
3252 * only 2MB. So we need to double the offset again
3253 * and zap two pdes instead of one.
3254 */
3255 if (level == PT32_ROOT_LEVEL) {
6b8d0f9b 3256 page_offset &= ~7; /* kill rounding error */
ac1b714e
AK		 3257 page_offset <<= 1;
3258 npte = 2;
3259 }
fce0657f 3260 quadrant = page_offset >> PAGE_SHIFT;
9b7a0325 3261 page_offset &= ~PAGE_MASK;
4db35314 3262 if (quadrant != sp->role.quadrant)
fce0657f 3263 continue;
9b7a0325 3264 }
0671a8e7 3265 local_flush = true;
4db35314 3266 spte = &sp->spt[page_offset / sizeof(*spte)];
ac1b714e 3267 while (npte--) {
79539cec 3268 entry = *spte;
38e3b2b2 3269 mmu_page_zap_pte(vcpu->kvm, sp, spte);
fa1de2bf
XG		 3270 if (gentry &&
3271 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
3272 & mask.word))
7c562522 3273 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
0671a8e7
XG		 3274 if (!remote_flush && need_remote_flush(entry, *spte))
3275 remote_flush = true;
ac1b714e 3276 ++spte;
9b7a0325 3277 }
9b7a0325 3278 }
0671a8e7 3279 mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
d98ba053 3280 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
8b1fe17c 3281 trace_kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
aaee2c94 3282 spin_unlock(&vcpu->kvm->mmu_lock);
da4a00f0
AK		 3283}
3284
a436036b
AK		 3285int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
3286{
10589a46
MT		 3287 gpa_t gpa;
3288 int r;
a436036b 3289
c5a78f2b 3290 if (vcpu->arch.mmu.direct_map)
60f24784
AK		 3291 return 0;
3292
1871c602 3293 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
10589a46 3294
aaee2c94 3295 spin_lock(&vcpu->kvm->mmu_lock);
10589a46 3296 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
aaee2c94 3297 spin_unlock(&vcpu->kvm->mmu_lock);
10589a46 3298 return r;
a436036b 3299}
577bdc49 3300EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
a436036b 3301
22d95b12 3302void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
ebeace86 3303{
d98ba053 3304 LIST_HEAD(invalid_list);
103ad25a 3305
e0df7b9f 3306 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES &&
3b80fffe 3307 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
4db35314 3308 struct kvm_mmu_page *sp;
ebeace86 3309
f05e70ac 3310 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
4db35314 3311 struct kvm_mmu_page, link);
e0df7b9f 3312 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
80b63faf 3313 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4cee5764 3314 ++vcpu->kvm->stat.mmu_recycled;
ebeace86
AK		 3315 }
3316}
ebeace86 3317
dc25e89e
AP		 3318int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
3319 void *insn, int insn_len)
3067714c
AK		 3320{
3321 int r;
3322 enum emulation_result er;
3323
56028d08 3324 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
3067714c
AK		 3325 if (r < 0)
3326 goto out;
3327
3328 if (!r) {
3329 r = 1;
3330 goto out;
3331 }
3332
b733bfb5
AK		 3333 r = mmu_topup_memory_caches(vcpu);
3334 if (r)
3335 goto out;
3336
dc25e89e 3337 er = x86_emulate_instruction(vcpu, cr2, 0, insn, insn_len);
3067714c
AK		 3338
3339 switch (er) {
3340 case EMULATE_DONE:
3341 return 1;
3342 case EMULATE_DO_MMIO:
3343 ++vcpu->stat.mmio_exits;
6d77dbfc 3344 /* fall through */
3067714c 3345 case EMULATE_FAIL:
3f5d18a9 3346 return 0;
3067714c
AK		 3347 default:
3348 BUG();
3349 }
3350out:
3067714c
AK		 3351 return r;
3352}
3353EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
3354
a7052897
MT		 3355void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
3356{
a7052897 3357 vcpu->arch.mmu.invlpg(vcpu, gva);
a7052897
MT		 3358 kvm_mmu_flush_tlb(vcpu);
3359 ++vcpu->stat.invlpg;
3360}
3361EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
3362
18552672
JR		 3363void kvm_enable_tdp(void)
3364{
3365 tdp_enabled = true;
3366}
3367EXPORT_SYMBOL_GPL(kvm_enable_tdp);
3368
5f4cb662
JR		 3369void kvm_disable_tdp(void)
3370{
3371 tdp_enabled = false;
3372}
3373EXPORT_SYMBOL_GPL(kvm_disable_tdp);
3374
6aa8b732
AK		 3375static void free_mmu_pages(struct kvm_vcpu *vcpu)
3376{
ad312c7c 3377 free_page((unsigned long)vcpu->arch.mmu.pae_root);
81407ca5
JR		 3378 if (vcpu->arch.mmu.lm_root != NULL)
3379 free_page((unsigned long)vcpu->arch.mmu.lm_root);
6aa8b732
AK		 3380}
3381
3382static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
3383{
17ac10ad 3384 struct page *page;
6aa8b732
AK		 3385 int i;
3386
3387 ASSERT(vcpu);
3388
17ac10ad
AK		 3389 /*
3390 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
3391 * Therefore we need to allocate shadow page tables in the first
3392 * 4GB of memory, which happens to fit the DMA32 zone.
3393 */
3394 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
3395 if (!page)
d7fa6ab2
WY		 3396 return -ENOMEM;
3397
ad312c7c 3398 vcpu->arch.mmu.pae_root = page_address(page);
17ac10ad 3399 for (i = 0; i < 4; ++i)
ad312c7c 3400 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 3401
6aa8b732 3402 return 0;
6aa8b732
AK		 3403}
3404
8018c27b 3405int kvm_mmu_create(struct kvm_vcpu *vcpu)
6aa8b732 3406{
6aa8b732 3407 ASSERT(vcpu);
ad312c7c 3408 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 3409
8018c27b
IM		 3410 return alloc_mmu_pages(vcpu);
3411}
6aa8b732 3412
8018c27b
IM		 3413int kvm_mmu_setup(struct kvm_vcpu *vcpu)
3414{
3415 ASSERT(vcpu);
ad312c7c 3416 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2c264957 3417
8018c27b 3418 return init_kvm_mmu(vcpu);
6aa8b732
AK		 3419}
3420
90cb0529 3421void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
6aa8b732 3422{
4db35314 3423 struct kvm_mmu_page *sp;
6aa8b732 3424
f05e70ac 3425 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
6aa8b732
AK		 3426 int i;
3427 u64 *pt;
3428
291f26bc 3429 if (!test_bit(slot, sp->slot_bitmap))
6aa8b732
AK		 3430 continue;
3431
4db35314 3432 pt = sp->spt;
8234b22e 3433 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
da8dc75f
XG		 3434 if (!is_shadow_present_pte(pt[i]) ||
3435 !is_last_spte(pt[i], sp->role.level))
3436 continue;
3437
3438 if (is_large_pte(pt[i])) {
8234b22e
AK		 3439 drop_spte(kvm, &pt[i],
3440 shadow_trap_nonpresent_pte);
3441 --kvm->stat.lpages;
da8dc75f 3442 continue;
8234b22e 3443 }
da8dc75f 3444
6aa8b732 3445 /* avoid RMW */
01c168ac 3446 if (is_writable_pte(pt[i]))
700e1b12 3447 update_spte(&pt[i], pt[i] & ~PT_WRITABLE_MASK);
8234b22e 3448 }
6aa8b732 3449 }
171d595d 3450 kvm_flush_remote_tlbs(kvm);
6aa8b732 3451}
37a7d8b0 3452
90cb0529 3453void kvm_mmu_zap_all(struct kvm *kvm)
e0fa826f 3454{
4db35314 3455 struct kvm_mmu_page *sp, *node;
d98ba053 3456 LIST_HEAD(invalid_list);
e0fa826f 3457
aaee2c94 3458 spin_lock(&kvm->mmu_lock);
3246af0e 3459restart:
f05e70ac 3460 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
d98ba053 3461 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
3246af0e
XG		 3462 goto restart;
3463
d98ba053 3464 kvm_mmu_commit_zap_page(kvm, &invalid_list);
aaee2c94 3465 spin_unlock(&kvm->mmu_lock);
e0fa826f
DL		 3466}
3467
d98ba053
XG		 3468static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
3469 struct list_head *invalid_list)
3ee16c81
IE		 3470{
3471 struct kvm_mmu_page *page;
3472
3473 page = container_of(kvm->arch.active_mmu_pages.prev,
3474 struct kvm_mmu_page, link);
d98ba053 3475 return kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
3ee16c81
IE		 3476}
3477
1495f230 3478static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
3ee16c81
IE		 3479{
3480 struct kvm *kvm;
3481 struct kvm *kvm_freed = NULL;
1495f230 3482 int nr_to_scan = sc->nr_to_scan;
45221ab6
DH		 3483
3484 if (nr_to_scan == 0)
3485 goto out;
3ee16c81 3486
e935b837 3487 raw_spin_lock(&kvm_lock);
3ee16c81
IE		 3488
3489 list_for_each_entry(kvm, &vm_list, vm_list) {
45221ab6 3490 int idx, freed_pages;
d98ba053 3491 LIST_HEAD(invalid_list);
3ee16c81 3492
f656ce01 3493 idx = srcu_read_lock(&kvm->srcu);
3ee16c81 3494 spin_lock(&kvm->mmu_lock);
45221ab6
DH		 3495 if (!kvm_freed && nr_to_scan > 0 &&
3496 kvm->arch.n_used_mmu_pages > 0) {
d98ba053
XG		 3497 freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm,
3498 &invalid_list);
3ee16c81
IE		 3499 kvm_freed = kvm;
3500 }
3501 nr_to_scan--;
3502
d98ba053 3503 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3ee16c81 3504 spin_unlock(&kvm->mmu_lock);
f656ce01 3505 srcu_read_unlock(&kvm->srcu, idx);
3ee16c81
IE		 3506 }
3507 if (kvm_freed)
3508 list_move_tail(&kvm_freed->vm_list, &vm_list);
3509
e935b837 3510 raw_spin_unlock(&kvm_lock);
3ee16c81 3511
45221ab6
DH		 3512out:
3513 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
3ee16c81
IE		 3514}
3515
3516static struct shrinker mmu_shrinker = {
3517 .shrink = mmu_shrink,
3518 .seeks = DEFAULT_SEEKS * 10,
3519};
3520
2ddfd20e 3521static void mmu_destroy_caches(void)
b5a33a75 3522{
53c07b18
XG		 3523 if (pte_list_desc_cache)
3524 kmem_cache_destroy(pte_list_desc_cache);
d3d25b04
AK		 3525 if (mmu_page_header_cache)
3526 kmem_cache_destroy(mmu_page_header_cache);
b5a33a75
AK		 3527}
3528
3529int kvm_mmu_module_init(void)
3530{
53c07b18
XG		 3531 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
3532 sizeof(struct pte_list_desc),
20c2df83 3533 0, 0, NULL);
53c07b18 3534 if (!pte_list_desc_cache)
b5a33a75
AK		 3535 goto nomem;
3536
d3d25b04
AK		 3537 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
3538 sizeof(struct kvm_mmu_page),
20c2df83 3539 0, 0, NULL);
d3d25b04
AK		 3540 if (!mmu_page_header_cache)
3541 goto nomem;
3542
45bf21a8
WY		 3543 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
3544 goto nomem;
3545
3ee16c81
IE		 3546 register_shrinker(&mmu_shrinker);
3547
b5a33a75
AK		 3548 return 0;
3549
3550nomem:
3ee16c81 3551 mmu_destroy_caches();
b5a33a75
AK		 3552 return -ENOMEM;
3553}
3554
3ad82a7e
ZX		 3555/*
3556 * Caculate mmu pages needed for kvm.
3557 */
3558unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3559{
3560 int i;
3561 unsigned int nr_mmu_pages;
3562 unsigned int nr_pages = 0;
bc6678a3 3563 struct kvm_memslots *slots;
3ad82a7e 3564
90d83dc3
LJ		 3565 slots = kvm_memslots(kvm);
3566
bc6678a3
MT		 3567 for (i = 0; i < slots->nmemslots; i++)
3568 nr_pages += slots->memslots[i].npages;
3ad82a7e
ZX		 3569
3570 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3571 nr_mmu_pages = max(nr_mmu_pages,
3572 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3573
3574 return nr_mmu_pages;
3575}
3576
2f333bcb
MT		 3577static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3578 unsigned len)
3579{
3580 if (len > buffer->len)
3581 return NULL;
3582 return buffer->ptr;
3583}
3584
3585static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3586 unsigned len)
3587{
3588 void *ret;
3589
3590 ret = pv_mmu_peek_buffer(buffer, len);
3591 if (!ret)
3592 return ret;
3593 buffer->ptr += len;
3594 buffer->len -= len;
3595 buffer->processed += len;
3596 return ret;
3597}
3598
3599static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3600 gpa_t addr, gpa_t value)
3601{
3602 int bytes = 8;
3603 int r;
3604
3605 if (!is_long_mode(vcpu) && !is_pae(vcpu))
3606 bytes = 4;
3607
3608 r = mmu_topup_memory_caches(vcpu);
3609 if (r)
3610 return r;
3611
3200f405 3612 if (!emulator_write_phys(vcpu, addr, &value, bytes))
2f333bcb
MT		 3613 return -EFAULT;
3614
3615 return 1;
3616}
3617
3618static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3619{
9f8fe504 3620 (void)kvm_set_cr3(vcpu, kvm_read_cr3(vcpu));
2f333bcb
MT		 3621 return 1;
3622}
3623
3624static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
3625{
3626 spin_lock(&vcpu->kvm->mmu_lock);
3627 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
3628 spin_unlock(&vcpu->kvm->mmu_lock);
3629 return 1;
3630}
3631
3632static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
3633 struct kvm_pv_mmu_op_buffer *buffer)
3634{
3635 struct kvm_mmu_op_header *header;
3636
3637 header = pv_mmu_peek_buffer(buffer, sizeof *header);
3638 if (!header)
3639 return 0;
3640 switch (header->op) {
3641 case KVM_MMU_OP_WRITE_PTE: {
3642 struct kvm_mmu_op_write_pte *wpte;
3643
3644 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
3645 if (!wpte)
3646 return 0;
3647 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
3648 wpte->pte_val);
3649 }
3650 case KVM_MMU_OP_FLUSH_TLB: {
3651 struct kvm_mmu_op_flush_tlb *ftlb;
3652
3653 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
3654 if (!ftlb)
3655 return 0;
3656 return kvm_pv_mmu_flush_tlb(vcpu);
3657 }
3658 case KVM_MMU_OP_RELEASE_PT: {
3659 struct kvm_mmu_op_release_pt *rpt;
3660
3661 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
3662 if (!rpt)
3663 return 0;
3664 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
3665 }
3666 default: return 0;
3667 }
3668}
3669
3670int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
3671 gpa_t addr, unsigned long *ret)
3672{
3673 int r;
6ad18fba 3674 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
2f333bcb 3675
6ad18fba
DH		 3676 buffer->ptr = buffer->buf;
3677 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
3678 buffer->processed = 0;
2f333bcb 3679
6ad18fba 3680 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
2f333bcb
MT		 3681 if (r)
3682 goto out;
3683
6ad18fba
DH		 3684 while (buffer->len) {
3685 r = kvm_pv_mmu_op_one(vcpu, buffer);
2f333bcb
MT		 3686 if (r < 0)
3687 goto out;
3688 if (r == 0)
3689 break;
3690 }
3691
3692 r = 1;
3693out:
6ad18fba 3694 *ret = buffer->processed;
2f333bcb
MT		 3695 return r;
3696}
3697
94d8b056
MT		 3698int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
3699{
3700 struct kvm_shadow_walk_iterator iterator;
3701 int nr_sptes = 0;
3702
3703 spin_lock(&vcpu->kvm->mmu_lock);
3704 for_each_shadow_entry(vcpu, addr, iterator) {
3705 sptes[iterator.level-1] = *iterator.sptep;
3706 nr_sptes++;
3707 if (!is_shadow_present_pte(*iterator.sptep))
3708 break;
3709 }
3710 spin_unlock(&vcpu->kvm->mmu_lock);
3711
3712 return nr_sptes;
3713}
3714EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
3715
c42fffe3
XG		 3716void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
3717{
3718 ASSERT(vcpu);
3719
3720 destroy_kvm_mmu(vcpu);
3721 free_mmu_pages(vcpu);
3722 mmu_free_memory_caches(vcpu);
b034cf01
XG		 3723}
3724
3725#ifdef CONFIG_KVM_MMU_AUDIT
3726#include "mmu_audit.c"
3727#else
3728static void mmu_audit_disable(void) { }
3729#endif
3730
3731void kvm_mmu_module_exit(void)
3732{
3733 mmu_destroy_caches();
3734 percpu_counter_destroy(&kvm_total_used_mmu_pages);
3735 unregister_shrinker(&mmu_shrinker);
c42fffe3
XG		 3736 mmu_audit_disable();
3737}
Linux kernel - Deliverables
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