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drm/i915: Rename struct intel_crtc_config to intel_crtc_state
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34};
35
45244b87
ED		 36/* HDMI/DVI modes ignore everything but the last 2 items. So we share
37 * them for both DP and FDI transports, allowing those ports to
38 * automatically adapt to HDMI connections as well
39 */
10122051
JN		 40static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
41 { 0x00FFFFFF, 0x0006000E },
42 { 0x00D75FFF, 0x0005000A },
43 { 0x00C30FFF, 0x00040006 },
44 { 0x80AAAFFF, 0x000B0000 },
45 { 0x00FFFFFF, 0x0005000A },
46 { 0x00D75FFF, 0x000C0004 },
47 { 0x80C30FFF, 0x000B0000 },
48 { 0x00FFFFFF, 0x00040006 },
49 { 0x80D75FFF, 0x000B0000 },
45244b87
ED		 50};
51
10122051
JN		 52static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
53 { 0x00FFFFFF, 0x0007000E },
54 { 0x00D75FFF, 0x000F000A },
55 { 0x00C30FFF, 0x00060006 },
56 { 0x00AAAFFF, 0x001E0000 },
57 { 0x00FFFFFF, 0x000F000A },
58 { 0x00D75FFF, 0x00160004 },
59 { 0x00C30FFF, 0x001E0000 },
60 { 0x00FFFFFF, 0x00060006 },
61 { 0x00D75FFF, 0x001E0000 },
6acab15a
PZ		 62};
63
10122051
JN		 64static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
65 /* Idx NT mV d T mV d db */
66 { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */
67 { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */
68 { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */
69 { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */
70 { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */
71 { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */
72 { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */
73 { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */
74 { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */
75 { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */
76 { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */
77 { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */
45244b87
ED		 78};
79
10122051
JN		 80static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
81 { 0x00FFFFFF, 0x00000012 },
82 { 0x00EBAFFF, 0x00020011 },
83 { 0x00C71FFF, 0x0006000F },
84 { 0x00AAAFFF, 0x000E000A },
85 { 0x00FFFFFF, 0x00020011 },
86 { 0x00DB6FFF, 0x0005000F },
87 { 0x00BEEFFF, 0x000A000C },
88 { 0x00FFFFFF, 0x0005000F },
89 { 0x00DB6FFF, 0x000A000C },
300644c7
PZ		 90};
91
10122051
JN		 92static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
93 { 0x00FFFFFF, 0x0007000E },
94 { 0x00D75FFF, 0x000E000A },
95 { 0x00BEFFFF, 0x00140006 },
96 { 0x80B2CFFF, 0x001B0002 },
97 { 0x00FFFFFF, 0x000E000A },
17b523ba 98 { 0x00DB6FFF, 0x00160005 },
6805b2a7 99 { 0x80C71FFF, 0x001A0002 },
10122051
JN		 100 { 0x00F7DFFF, 0x00180004 },
101 { 0x80D75FFF, 0x001B0002 },
e58623cb
AR		 102};
103
10122051
JN		 104static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
105 { 0x00FFFFFF, 0x0001000E },
106 { 0x00D75FFF, 0x0004000A },
107 { 0x00C30FFF, 0x00070006 },
108 { 0x00AAAFFF, 0x000C0000 },
109 { 0x00FFFFFF, 0x0004000A },
110 { 0x00D75FFF, 0x00090004 },
111 { 0x00C30FFF, 0x000C0000 },
112 { 0x00FFFFFF, 0x00070006 },
113 { 0x00D75FFF, 0x000C0000 },
e58623cb
AR		 114};
115
10122051
JN		 116static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
117 /* Idx NT mV d T mV df db */
118 { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */
119 { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */
120 { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */
121 { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */
122 { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */
123 { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */
124 { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */
125 { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */
126 { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */
127 { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */
a26aa8ba
DL		 128};
129
7f88e3af 130static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
6c930688
DL		 131 { 0x00000018, 0x000000a2 },
132 { 0x00004014, 0x0000009B },
7f88e3af 133 { 0x00006012, 0x00000088 },
6c930688
DL		 134 { 0x00008010, 0x00000087 },
135 { 0x00000018, 0x0000009B },
7f88e3af 136 { 0x00004014, 0x00000088 },
6c930688 137 { 0x00006012, 0x00000087 },
7f88e3af 138 { 0x00000018, 0x00000088 },
6c930688 139 { 0x00004014, 0x00000087 },
7f88e3af
DL		 140};
141
142static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
143 /* Idx NT mV T mV db */
144 { 0x00000018, 0x000000a0 }, /* 0: 400 400 0 */
145 { 0x00004014, 0x00000098 }, /* 1: 400 600 3.5 */
146 { 0x00006012, 0x00000088 }, /* 2: 400 800 6 */
147 { 0x00000018, 0x0000003c }, /* 3: 450 450 0 */
148 { 0x00000018, 0x00000098 }, /* 4: 600 600 0 */
149 { 0x00003015, 0x00000088 }, /* 5: 600 800 2.5 */
150 { 0x00005013, 0x00000080 }, /* 6: 600 1000 4.5 */
151 { 0x00000018, 0x00000088 }, /* 7: 800 800 0 */
152 { 0x00000096, 0x00000080 }, /* 8: 800 1000 2 */
153 { 0x00000018, 0x00000080 }, /* 9: 1200 1200 0 */
154};
155
20f4dbe4 156enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
fc914639 157{
0bdee30e 158 struct drm_encoder *encoder = &intel_encoder->base;
fc914639
PZ		 159 int type = intel_encoder->type;
160
0e32b39c
DA		 161 if (type == INTEL_OUTPUT_DP_MST) {
162 struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary;
163 return intel_dig_port->port;
164 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
00c09d70 165 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
174edf1f
PZ		 166 struct intel_digital_port *intel_dig_port =
167 enc_to_dig_port(encoder);
168 return intel_dig_port->port;
0bdee30e 169
fc914639
PZ		 170 } else if (type == INTEL_OUTPUT_ANALOG) {
171 return PORT_E;
0bdee30e 172
fc914639
PZ		 173 } else {
174 DRM_ERROR("Invalid DDI encoder type %d\n", type);
175 BUG();
176 }
177}
178
e58623cb
AR		 179/*
180 * Starting with Haswell, DDI port buffers must be programmed with correct
181 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 182 * but the HDMI/DVI fields are shared among those. So we program the DDI
183 * in either FDI or DP modes only, as HDMI connections will work with both
184 * of those
185 */
ad8d270c 186static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
45244b87
ED		 187{
188 struct drm_i915_private *dev_priv = dev->dev_private;
189 u32 reg;
ce4dd49e 190 int i, n_hdmi_entries, hdmi_800mV_0dB;
6acab15a 191 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
10122051
JN		 192 const struct ddi_buf_trans *ddi_translations_fdi;
193 const struct ddi_buf_trans *ddi_translations_dp;
194 const struct ddi_buf_trans *ddi_translations_edp;
195 const struct ddi_buf_trans *ddi_translations_hdmi;
196 const struct ddi_buf_trans *ddi_translations;
e58623cb 197
7f88e3af
DL		 198 if (IS_SKYLAKE(dev)) {
199 ddi_translations_fdi = NULL;
200 ddi_translations_dp = skl_ddi_translations_dp;
201 ddi_translations_edp = skl_ddi_translations_dp;
202 ddi_translations_hdmi = skl_ddi_translations_hdmi;
203 n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
204 hdmi_800mV_0dB = 7;
205 } else if (IS_BROADWELL(dev)) {
e58623cb
AR		 206 ddi_translations_fdi = bdw_ddi_translations_fdi;
207 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 208 ddi_translations_edp = bdw_ddi_translations_edp;
a26aa8ba 209 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
10122051 210 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
a26aa8ba 211 hdmi_800mV_0dB = 7;
e58623cb
AR		 212 } else if (IS_HASWELL(dev)) {
213 ddi_translations_fdi = hsw_ddi_translations_fdi;
214 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 215 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 216 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
10122051 217 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
ce4dd49e 218 hdmi_800mV_0dB = 6;
e58623cb
AR		 219 } else {
220 WARN(1, "ddi translation table missing\n");
300644c7 221 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 222 ddi_translations_fdi = bdw_ddi_translations_fdi;
223 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 224 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
10122051 225 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
a26aa8ba 226 hdmi_800mV_0dB = 7;
e58623cb
AR		 227 }
228
300644c7
PZ		 229 switch (port) {
230 case PORT_A:
231 ddi_translations = ddi_translations_edp;
232 break;
233 case PORT_B:
234 case PORT_C:
300644c7
PZ		 235 ddi_translations = ddi_translations_dp;
236 break;
77d8d009 237 case PORT_D:
5d8a7752 238 if (intel_dp_is_edp(dev, PORT_D))
77d8d009
PZ		 239 ddi_translations = ddi_translations_edp;
240 else
241 ddi_translations = ddi_translations_dp;
242 break;
300644c7 243 case PORT_E:
7f88e3af
DL		 244 if (ddi_translations_fdi)
245 ddi_translations = ddi_translations_fdi;
246 else
247 ddi_translations = ddi_translations_dp;
300644c7
PZ		 248 break;
249 default:
250 BUG();
251 }
45244b87 252
f72d19f0
PZ		 253 for (i = 0, reg = DDI_BUF_TRANS(port);
254 i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
10122051
JN		 255 I915_WRITE(reg, ddi_translations[i].trans1);
256 reg += 4;
257 I915_WRITE(reg, ddi_translations[i].trans2);
45244b87
ED		 258 reg += 4;
259 }
ce4dd49e
DL		 260
261 /* Choose a good default if VBT is badly populated */
262 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
263 hdmi_level >= n_hdmi_entries)
264 hdmi_level = hdmi_800mV_0dB;
265
6acab15a 266 /* Entry 9 is for HDMI: */
10122051
JN		 267 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
268 reg += 4;
269 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
270 reg += 4;
45244b87
ED		 271}
272
273/* Program DDI buffers translations for DP. By default, program ports A-D in DP
274 * mode and port E for FDI.
275 */
276void intel_prepare_ddi(struct drm_device *dev)
277{
278 int port;
279
0d536cb4
PZ		 280 if (!HAS_DDI(dev))
281 return;
45244b87 282
ad8d270c
PZ		 283 for (port = PORT_A; port <= PORT_E; port++)
284 intel_prepare_ddi_buffers(dev, port);
45244b87 285}
c82e4d26 286
248138b5
PZ		 287static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
288 enum port port)
289{
290 uint32_t reg = DDI_BUF_CTL(port);
291 int i;
292
293 for (i = 0; i < 8; i++) {
294 udelay(1);
295 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
296 return;
297 }
298 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
299}
c82e4d26
ED		 300
301/* Starting with Haswell, different DDI ports can work in FDI mode for
302 * connection to the PCH-located connectors. For this, it is necessary to train
303 * both the DDI port and PCH receiver for the desired DDI buffer settings.
304 *
305 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
306 * please note that when FDI mode is active on DDI E, it shares 2 lines with
307 * DDI A (which is used for eDP)
308 */
309
310void hsw_fdi_link_train(struct drm_crtc *crtc)
311{
312 struct drm_device *dev = crtc->dev;
313 struct drm_i915_private *dev_priv = dev->dev_private;
314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 315 u32 temp, i, rx_ctl_val;
c82e4d26 316
04945641
PZ		 317 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
318 * mode set "sequence for CRT port" document:
319 * - TP1 to TP2 time with the default value
320 * - FDI delay to 90h
8693a824
DL		 321 *
322 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641
PZ		 323 */
324 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
325 FDI_RX_PWRDN_LANE0_VAL(2) |
326 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
327
328 /* Enable the PCH Receiver FDI PLL */
3e68320e 329 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 330 FDI_RX_PLL_ENABLE |
627eb5a3 331 FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
04945641
PZ		 332 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
333 POSTING_READ(_FDI_RXA_CTL);
334 udelay(220);
335
336 /* Switch from Rawclk to PCDclk */
337 rx_ctl_val |= FDI_PCDCLK;
338 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
339
340 /* Configure Port Clock Select */
de7cfc63
DV		 341 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel);
342 WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 343
344 /* Start the training iterating through available voltages and emphasis,
345 * testing each value twice. */
10122051 346 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 347 /* Configure DP_TP_CTL with auto-training */
348 I915_WRITE(DP_TP_CTL(PORT_E),
349 DP_TP_CTL_FDI_AUTOTRAIN |
350 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
351 DP_TP_CTL_LINK_TRAIN_PAT1 |
352 DP_TP_CTL_ENABLE);
353
876a8cdf
DL		 354 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
355 * DDI E does not support port reversal, the functionality is
356 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
357 * port reversal bit */
c82e4d26 358 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 359 DDI_BUF_CTL_ENABLE |
33d29b14 360 ((intel_crtc->config.fdi_lanes - 1) << 1) |
c5fe6a06 361 DDI_BUF_TRANS_SELECT(i / 2));
04945641 362 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 363
364 udelay(600);
365
04945641
PZ		 366 /* Program PCH FDI Receiver TU */
367 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
368
369 /* Enable PCH FDI Receiver with auto-training */
370 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
371 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
372 POSTING_READ(_FDI_RXA_CTL);
373
374 /* Wait for FDI receiver lane calibration */
375 udelay(30);
376
377 /* Unset FDI_RX_MISC pwrdn lanes */
378 temp = I915_READ(_FDI_RXA_MISC);
379 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
380 I915_WRITE(_FDI_RXA_MISC, temp);
381 POSTING_READ(_FDI_RXA_MISC);
382
383 /* Wait for FDI auto training time */
384 udelay(5);
c82e4d26
ED		 385
386 temp = I915_READ(DP_TP_STATUS(PORT_E));
387 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 388 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
c82e4d26
ED		 389
390 /* Enable normal pixel sending for FDI */
391 I915_WRITE(DP_TP_CTL(PORT_E),
04945641
PZ		 392 DP_TP_CTL_FDI_AUTOTRAIN |
393 DP_TP_CTL_LINK_TRAIN_NORMAL |
394 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
395 DP_TP_CTL_ENABLE);
c82e4d26 396
04945641 397 return;
c82e4d26 398 }
04945641 399
248138b5
PZ		 400 temp = I915_READ(DDI_BUF_CTL(PORT_E));
401 temp &= ~DDI_BUF_CTL_ENABLE;
402 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
403 POSTING_READ(DDI_BUF_CTL(PORT_E));
404
04945641 405 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 406 temp = I915_READ(DP_TP_CTL(PORT_E));
407 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
408 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
409 I915_WRITE(DP_TP_CTL(PORT_E), temp);
410 POSTING_READ(DP_TP_CTL(PORT_E));
411
412 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 413
414 rx_ctl_val &= ~FDI_RX_ENABLE;
415 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
248138b5 416 POSTING_READ(_FDI_RXA_CTL);
04945641
PZ		 417
418 /* Reset FDI_RX_MISC pwrdn lanes */
419 temp = I915_READ(_FDI_RXA_MISC);
420 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
421 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
422 I915_WRITE(_FDI_RXA_MISC, temp);
248138b5 423 POSTING_READ(_FDI_RXA_MISC);
c82e4d26
ED		 424 }
425
04945641 426 DRM_ERROR("FDI link training failed!\n");
c82e4d26 427}
0e72a5b5 428
44905a27
DA		 429void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
430{
431 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
432 struct intel_digital_port *intel_dig_port =
433 enc_to_dig_port(&encoder->base);
434
435 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 436 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
44905a27
DA		 437 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
438
439}
440
8d9ddbcb
PZ		 441static struct intel_encoder *
442intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
443{
444 struct drm_device *dev = crtc->dev;
445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
446 struct intel_encoder *intel_encoder, *ret = NULL;
447 int num_encoders = 0;
448
449 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
450 ret = intel_encoder;
451 num_encoders++;
452 }
453
454 if (num_encoders != 1)
84f44ce7
VS		 455 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
456 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 457
458 BUG_ON(ret == NULL);
459 return ret;
460}
461
d0737e1d
ACO		 462static struct intel_encoder *
463intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc)
464{
465 struct drm_device *dev = crtc->base.dev;
466 struct intel_encoder *intel_encoder, *ret = NULL;
467 int num_encoders = 0;
468
469 for_each_intel_encoder(dev, intel_encoder) {
470 if (intel_encoder->new_crtc == crtc) {
471 ret = intel_encoder;
472 num_encoders++;
473 }
474 }
475
476 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
477 pipe_name(crtc->pipe));
478
479 BUG_ON(ret == NULL);
480 return ret;
481}
482
1c0b85c5 483#define LC_FREQ 2700
27893390 484#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
1c0b85c5
DL		 485
486#define P_MIN 2
487#define P_MAX 64
488#define P_INC 2
489
490/* Constraints for PLL good behavior */
491#define REF_MIN 48
492#define REF_MAX 400
493#define VCO_MIN 2400
494#define VCO_MAX 4800
495
27893390
DL		 496#define abs_diff(a, b) ({ \
497 typeof(a) __a = (a); \
498 typeof(b) __b = (b); \
499 (void) (&__a == &__b); \
500 __a > __b ? (__a - __b) : (__b - __a); })
1c0b85c5
DL		 501
502struct wrpll_rnp {
503 unsigned p, n2, r2;
504};
505
506static unsigned wrpll_get_budget_for_freq(int clock)
6441ab5f 507{
1c0b85c5
DL		 508 unsigned budget;
509
510 switch (clock) {
511 case 25175000:
512 case 25200000:
513 case 27000000:
514 case 27027000:
515 case 37762500:
516 case 37800000:
517 case 40500000:
518 case 40541000:
519 case 54000000:
520 case 54054000:
521 case 59341000:
522 case 59400000:
523 case 72000000:
524 case 74176000:
525 case 74250000:
526 case 81000000:
527 case 81081000:
528 case 89012000:
529 case 89100000:
530 case 108000000:
531 case 108108000:
532 case 111264000:
533 case 111375000:
534 case 148352000:
535 case 148500000:
536 case 162000000:
537 case 162162000:
538 case 222525000:
539 case 222750000:
540 case 296703000:
541 case 297000000:
542 budget = 0;
543 break;
544 case 233500000:
545 case 245250000:
546 case 247750000:
547 case 253250000:
548 case 298000000:
549 budget = 1500;
550 break;
551 case 169128000:
552 case 169500000:
553 case 179500000:
554 case 202000000:
555 budget = 2000;
556 break;
557 case 256250000:
558 case 262500000:
559 case 270000000:
560 case 272500000:
561 case 273750000:
562 case 280750000:
563 case 281250000:
564 case 286000000:
565 case 291750000:
566 budget = 4000;
567 break;
568 case 267250000:
569 case 268500000:
570 budget = 5000;
571 break;
572 default:
573 budget = 1000;
574 break;
575 }
6441ab5f 576
1c0b85c5
DL		 577 return budget;
578}
579
580static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
581 unsigned r2, unsigned n2, unsigned p,
582 struct wrpll_rnp *best)
583{
584 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 585
1c0b85c5
DL		 586 /* No best (r,n,p) yet */
587 if (best->p == 0) {
588 best->p = p;
589 best->n2 = n2;
590 best->r2 = r2;
591 return;
592 }
6441ab5f 593
1c0b85c5
DL		 594 /*
595 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
596 * freq2k.
597 *
598 * delta = 1e6 *
599 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
600 * freq2k;
601 *
602 * and we would like delta <= budget.
603 *
604 * If the discrepancy is above the PPM-based budget, always prefer to
605 * improve upon the previous solution. However, if you're within the
606 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
607 */
608 a = freq2k * budget * p * r2;
609 b = freq2k * budget * best->p * best->r2;
27893390
DL		 610 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
611 diff_best = abs_diff(freq2k * best->p * best->r2,
612 LC_FREQ_2K * best->n2);
1c0b85c5
DL		 613 c = 1000000 * diff;
614 d = 1000000 * diff_best;
615
616 if (a < c && b < d) {
617 /* If both are above the budget, pick the closer */
618 if (best->p * best->r2 * diff < p * r2 * diff_best) {
619 best->p = p;
620 best->n2 = n2;
621 best->r2 = r2;
622 }
623 } else if (a >= c && b < d) {
624 /* If A is below the threshold but B is above it? Update. */
625 best->p = p;
626 best->n2 = n2;
627 best->r2 = r2;
628 } else if (a >= c && b >= d) {
629 /* Both are below the limit, so pick the higher n2/(r2*r2) */
630 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
631 best->p = p;
632 best->n2 = n2;
633 best->r2 = r2;
634 }
635 }
636 /* Otherwise a < c && b >= d, do nothing */
637}
638
11578553
JB		 639static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
640 int reg)
641{
642 int refclk = LC_FREQ;
643 int n, p, r;
644 u32 wrpll;
645
646 wrpll = I915_READ(reg);
114fe488
DV		 647 switch (wrpll & WRPLL_PLL_REF_MASK) {
648 case WRPLL_PLL_SSC:
649 case WRPLL_PLL_NON_SSC:
11578553
JB		 650 /*
651 * We could calculate spread here, but our checking
652 * code only cares about 5% accuracy, and spread is a max of
653 * 0.5% downspread.
654 */
655 refclk = 135;
656 break;
114fe488 657 case WRPLL_PLL_LCPLL:
11578553
JB		 658 refclk = LC_FREQ;
659 break;
660 default:
661 WARN(1, "bad wrpll refclk\n");
662 return 0;
663 }
664
665 r = wrpll & WRPLL_DIVIDER_REF_MASK;
666 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
667 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
668
20f0ec16
JB		 669 /* Convert to KHz, p & r have a fixed point portion */
670 return (refclk * n * 100) / (p * r);
11578553
JB		 671}
672
540e732c
S		 673static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
674 uint32_t dpll)
675{
676 uint32_t cfgcr1_reg, cfgcr2_reg;
677 uint32_t cfgcr1_val, cfgcr2_val;
678 uint32_t p0, p1, p2, dco_freq;
679
680 cfgcr1_reg = GET_CFG_CR1_REG(dpll);
681 cfgcr2_reg = GET_CFG_CR2_REG(dpll);
682
683 cfgcr1_val = I915_READ(cfgcr1_reg);
684 cfgcr2_val = I915_READ(cfgcr2_reg);
685
686 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
687 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
688
689 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
690 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
691 else
692 p1 = 1;
693
694
695 switch (p0) {
696 case DPLL_CFGCR2_PDIV_1:
697 p0 = 1;
698 break;
699 case DPLL_CFGCR2_PDIV_2:
700 p0 = 2;
701 break;
702 case DPLL_CFGCR2_PDIV_3:
703 p0 = 3;
704 break;
705 case DPLL_CFGCR2_PDIV_7:
706 p0 = 7;
707 break;
708 }
709
710 switch (p2) {
711 case DPLL_CFGCR2_KDIV_5:
712 p2 = 5;
713 break;
714 case DPLL_CFGCR2_KDIV_2:
715 p2 = 2;
716 break;
717 case DPLL_CFGCR2_KDIV_3:
718 p2 = 3;
719 break;
720 case DPLL_CFGCR2_KDIV_1:
721 p2 = 1;
722 break;
723 }
724
725 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
726
727 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
728 1000) / 0x8000;
729
730 return dco_freq / (p0 * p1 * p2 * 5);
731}
732
733
734static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 735 struct intel_crtc_state *pipe_config)
540e732c
S		 736{
737 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
540e732c
S		 738 int link_clock = 0;
739 uint32_t dpll_ctl1, dpll;
740
134ffa44 741 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 742
743 dpll_ctl1 = I915_READ(DPLL_CTRL1);
744
745 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
746 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
747 } else {
748 link_clock = dpll_ctl1 & DPLL_CRTL1_LINK_RATE_MASK(dpll);
749 link_clock >>= DPLL_CRTL1_LINK_RATE_SHIFT(dpll);
750
751 switch (link_clock) {
752 case DPLL_CRTL1_LINK_RATE_810:
753 link_clock = 81000;
754 break;
755 case DPLL_CRTL1_LINK_RATE_1350:
756 link_clock = 135000;
757 break;
758 case DPLL_CRTL1_LINK_RATE_2700:
759 link_clock = 270000;
760 break;
761 default:
762 WARN(1, "Unsupported link rate\n");
763 break;
764 }
765 link_clock *= 2;
766 }
767
768 pipe_config->port_clock = link_clock;
769
770 if (pipe_config->has_dp_encoder)
771 pipe_config->adjusted_mode.crtc_clock =
772 intel_dotclock_calculate(pipe_config->port_clock,
773 &pipe_config->dp_m_n);
774 else
775 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
776}
777
3d51278a 778static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 779 struct intel_crtc_state *pipe_config)
11578553
JB		 780{
781 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
11578553
JB		 782 int link_clock = 0;
783 u32 val, pll;
784
26804afd 785 val = pipe_config->ddi_pll_sel;
11578553
JB		 786 switch (val & PORT_CLK_SEL_MASK) {
787 case PORT_CLK_SEL_LCPLL_810:
788 link_clock = 81000;
789 break;
790 case PORT_CLK_SEL_LCPLL_1350:
791 link_clock = 135000;
792 break;
793 case PORT_CLK_SEL_LCPLL_2700:
794 link_clock = 270000;
795 break;
796 case PORT_CLK_SEL_WRPLL1:
797 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
798 break;
799 case PORT_CLK_SEL_WRPLL2:
800 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
801 break;
802 case PORT_CLK_SEL_SPLL:
803 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
804 if (pll == SPLL_PLL_FREQ_810MHz)
805 link_clock = 81000;
806 else if (pll == SPLL_PLL_FREQ_1350MHz)
807 link_clock = 135000;
808 else if (pll == SPLL_PLL_FREQ_2700MHz)
809 link_clock = 270000;
810 else {
811 WARN(1, "bad spll freq\n");
812 return;
813 }
814 break;
815 default:
816 WARN(1, "bad port clock sel\n");
817 return;
818 }
819
820 pipe_config->port_clock = link_clock * 2;
821
822 if (pipe_config->has_pch_encoder)
823 pipe_config->adjusted_mode.crtc_clock =
824 intel_dotclock_calculate(pipe_config->port_clock,
825 &pipe_config->fdi_m_n);
826 else if (pipe_config->has_dp_encoder)
827 pipe_config->adjusted_mode.crtc_clock =
828 intel_dotclock_calculate(pipe_config->port_clock,
829 &pipe_config->dp_m_n);
830 else
831 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
832}
833
3d51278a 834void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 835 struct intel_crtc_state *pipe_config)
3d51278a 836{
22606a18
DL		 837 struct drm_device *dev = encoder->base.dev;
838
839 if (INTEL_INFO(dev)->gen <= 8)
840 hsw_ddi_clock_get(encoder, pipe_config);
841 else
842 skl_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 843}
844
1c0b85c5 845static void
d664c0ce
DL		 846hsw_ddi_calculate_wrpll(int clock /* in Hz */,
847 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1c0b85c5
DL		 848{
849 uint64_t freq2k;
850 unsigned p, n2, r2;
851 struct wrpll_rnp best = { 0, 0, 0 };
852 unsigned budget;
853
854 freq2k = clock / 100;
855
856 budget = wrpll_get_budget_for_freq(clock);
857
858 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
859 * and directly pass the LC PLL to it. */
860 if (freq2k == 5400000) {
861 *n2_out = 2;
862 *p_out = 1;
863 *r2_out = 2;
864 return;
865 }
866
867 /*
868 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
869 * the WR PLL.
870 *
871 * We want R so that REF_MIN <= Ref <= REF_MAX.
872 * Injecting R2 = 2 * R gives:
873 * REF_MAX * r2 > LC_FREQ * 2 and
874 * REF_MIN * r2 < LC_FREQ * 2
875 *
876 * Which means the desired boundaries for r2 are:
877 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
878 *
879 */
880 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
881 r2 <= LC_FREQ * 2 / REF_MIN;
882 r2++) {
883
884 /*
885 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
886 *
887 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
888 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
889 * VCO_MAX * r2 > n2 * LC_FREQ and
890 * VCO_MIN * r2 < n2 * LC_FREQ)
891 *
892 * Which means the desired boundaries for n2 are:
893 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
894 */
895 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
896 n2 <= VCO_MAX * r2 / LC_FREQ;
897 n2++) {
898
899 for (p = P_MIN; p <= P_MAX; p += P_INC)
900 wrpll_update_rnp(freq2k, budget,
901 r2, n2, p, &best);
902 }
903 }
6441ab5f 904
1c0b85c5
DL		 905 *n2_out = best.n2;
906 *p_out = best.p;
907 *r2_out = best.r2;
6441ab5f
PZ		 908}
909
0220ab6e 910static bool
d664c0ce
DL		 911hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
912 struct intel_encoder *intel_encoder,
913 int clock)
6441ab5f 914{
d664c0ce 915 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
e0b01be4 916 struct intel_shared_dpll *pll;
716c2e55 917 uint32_t val;
1c0b85c5 918 unsigned p, n2, r2;
6441ab5f 919
d664c0ce 920 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
0694001b 921
114fe488 922 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
0694001b
PZ		 923 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
924 WRPLL_DIVIDER_POST(p);
925
d0737e1d 926 intel_crtc->new_config->dpll_hw_state.wrpll = val;
6441ab5f 927
716c2e55
DV		 928 pll = intel_get_shared_dpll(intel_crtc);
929 if (pll == NULL) {
930 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
931 pipe_name(intel_crtc->pipe));
932 return false;
0694001b 933 }
d452c5b6 934
d0737e1d 935 intel_crtc->new_config->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
6441ab5f
PZ		 936 }
937
6441ab5f
PZ		 938 return true;
939}
940
82d35437
S		 941struct skl_wrpll_params {
942 uint32_t dco_fraction;
943 uint32_t dco_integer;
944 uint32_t qdiv_ratio;
945 uint32_t qdiv_mode;
946 uint32_t kdiv;
947 uint32_t pdiv;
948 uint32_t central_freq;
949};
950
951static void
952skl_ddi_calculate_wrpll(int clock /* in Hz */,
953 struct skl_wrpll_params *wrpll_params)
954{
955 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
21318cce
DL		 956 uint64_t dco_central_freq[3] = {8400000000ULL,
957 9000000000ULL,
958 9600000000ULL};
82d35437
S		 959 uint32_t min_dco_deviation = 400;
960 uint32_t min_dco_index = 3;
961 uint32_t P0[4] = {1, 2, 3, 7};
962 uint32_t P2[4] = {1, 2, 3, 5};
963 bool found = false;
964 uint32_t candidate_p = 0;
965 uint32_t candidate_p0[3] = {0}, candidate_p1[3] = {0};
966 uint32_t candidate_p2[3] = {0};
967 uint32_t dco_central_freq_deviation[3];
968 uint32_t i, P1, k, dco_count;
969 bool retry_with_odd = false;
970 uint64_t dco_freq;
971
972 /* Determine P0, P1 or P2 */
973 for (dco_count = 0; dco_count < 3; dco_count++) {
974 found = false;
975 candidate_p =
976 div64_u64(dco_central_freq[dco_count], afe_clock);
977 if (retry_with_odd == false)
978 candidate_p = (candidate_p % 2 == 0 ?
979 candidate_p : candidate_p + 1);
980
981 for (P1 = 1; P1 < candidate_p; P1++) {
982 for (i = 0; i < 4; i++) {
983 if (!(P0[i] != 1 || P1 == 1))
984 continue;
985
986 for (k = 0; k < 4; k++) {
987 if (P1 != 1 && P2[k] != 2)
988 continue;
989
990 if (candidate_p == P0[i] * P1 * P2[k]) {
991 /* Found possible P0, P1, P2 */
992 found = true;
993 candidate_p0[dco_count] = P0[i];
994 candidate_p1[dco_count] = P1;
995 candidate_p2[dco_count] = P2[k];
996 goto found;
997 }
998
999 }
1000 }
1001 }
1002
1003found:
1004 if (found) {
1005 dco_central_freq_deviation[dco_count] =
1006 div64_u64(10000 *
1007 abs_diff((candidate_p * afe_clock),
1008 dco_central_freq[dco_count]),
1009 dco_central_freq[dco_count]);
1010
1011 if (dco_central_freq_deviation[dco_count] <
1012 min_dco_deviation) {
1013 min_dco_deviation =
1014 dco_central_freq_deviation[dco_count];
1015 min_dco_index = dco_count;
1016 }
1017 }
1018
1019 if (min_dco_index > 2 && dco_count == 2) {
1020 retry_with_odd = true;
1021 dco_count = 0;
1022 }
1023 }
1024
1025 if (min_dco_index > 2) {
1026 WARN(1, "No valid values found for the given pixel clock\n");
1027 } else {
1028 wrpll_params->central_freq = dco_central_freq[min_dco_index];
1029
1030 switch (dco_central_freq[min_dco_index]) {
21318cce 1031 case 9600000000ULL:
82d35437
S		 1032 wrpll_params->central_freq = 0;
1033 break;
21318cce 1034 case 9000000000ULL:
82d35437
S		 1035 wrpll_params->central_freq = 1;
1036 break;
21318cce 1037 case 8400000000ULL:
82d35437
S		 1038 wrpll_params->central_freq = 3;
1039 }
1040
1041 switch (candidate_p0[min_dco_index]) {
1042 case 1:
1043 wrpll_params->pdiv = 0;
1044 break;
1045 case 2:
1046 wrpll_params->pdiv = 1;
1047 break;
1048 case 3:
1049 wrpll_params->pdiv = 2;
1050 break;
1051 case 7:
1052 wrpll_params->pdiv = 4;
1053 break;
1054 default:
1055 WARN(1, "Incorrect PDiv\n");
1056 }
1057
1058 switch (candidate_p2[min_dco_index]) {
1059 case 5:
1060 wrpll_params->kdiv = 0;
1061 break;
1062 case 2:
1063 wrpll_params->kdiv = 1;
1064 break;
1065 case 3:
1066 wrpll_params->kdiv = 2;
1067 break;
1068 case 1:
1069 wrpll_params->kdiv = 3;
1070 break;
1071 default:
1072 WARN(1, "Incorrect KDiv\n");
1073 }
1074
1075 wrpll_params->qdiv_ratio = candidate_p1[min_dco_index];
1076 wrpll_params->qdiv_mode =
1077 (wrpll_params->qdiv_ratio == 1) ? 0 : 1;
1078
1079 dco_freq = candidate_p0[min_dco_index] *
1080 candidate_p1[min_dco_index] *
1081 candidate_p2[min_dco_index] * afe_clock;
1082
1083 /*
1084 * Intermediate values are in Hz.
1085 * Divide by MHz to match bsepc
1086 */
1087 wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1)));
1088 wrpll_params->dco_fraction =
1089 div_u64(((div_u64(dco_freq, 24) -
1090 wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1));
1091
1092 }
1093}
1094
1095
1096static bool
1097skl_ddi_pll_select(struct intel_crtc *intel_crtc,
1098 struct intel_encoder *intel_encoder,
1099 int clock)
1100{
1101 struct intel_shared_dpll *pll;
1102 uint32_t ctrl1, cfgcr1, cfgcr2;
1103
1104 /*
1105 * See comment in intel_dpll_hw_state to understand why we always use 0
1106 * as the DPLL id in this function.
1107 */
1108
1109 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1110
1111 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1112 struct skl_wrpll_params wrpll_params = { 0, };
1113
1114 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1115
1116 skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params);
1117
1118 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1119 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1120 wrpll_params.dco_integer;
1121
1122 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1123 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1124 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1125 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1126 wrpll_params.central_freq;
1127 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1128 struct drm_encoder *encoder = &intel_encoder->base;
1129 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1130
1131 switch (intel_dp->link_bw) {
1132 case DP_LINK_BW_1_62:
1133 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810, 0);
1134 break;
1135 case DP_LINK_BW_2_7:
1136 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350, 0);
1137 break;
1138 case DP_LINK_BW_5_4:
1139 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700, 0);
1140 break;
1141 }
1142
1143 cfgcr1 = cfgcr2 = 0;
1144 } else /* eDP */
1145 return true;
1146
1147 intel_crtc->new_config->dpll_hw_state.ctrl1 = ctrl1;
1148 intel_crtc->new_config->dpll_hw_state.cfgcr1 = cfgcr1;
1149 intel_crtc->new_config->dpll_hw_state.cfgcr2 = cfgcr2;
1150
1151 pll = intel_get_shared_dpll(intel_crtc);
1152 if (pll == NULL) {
1153 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1154 pipe_name(intel_crtc->pipe));
1155 return false;
1156 }
1157
1158 /* shared DPLL id 0 is DPLL 1 */
1159 intel_crtc->new_config->ddi_pll_sel = pll->id + 1;
1160
1161 return true;
1162}
0220ab6e
DL		 1163
1164/*
1165 * Tries to find a *shared* PLL for the CRTC and store it in
1166 * intel_crtc->ddi_pll_sel.
1167 *
1168 * For private DPLLs, compute_config() should do the selection for us. This
1169 * function should be folded into compute_config() eventually.
1170 */
1171bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
1172{
82d35437 1173 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d
ACO		 1174 struct intel_encoder *intel_encoder =
1175 intel_ddi_get_crtc_new_encoder(intel_crtc);
1176 int clock = intel_crtc->new_config->port_clock;
0220ab6e 1177
82d35437
S		 1178 if (IS_SKYLAKE(dev))
1179 return skl_ddi_pll_select(intel_crtc, intel_encoder, clock);
1180 else
1181 return hsw_ddi_pll_select(intel_crtc, intel_encoder, clock);
0220ab6e
DL		 1182}
1183
dae84799
PZ		 1184void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1185{
1186 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1188 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
3b117c8f 1189 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
dae84799
PZ		 1190 int type = intel_encoder->type;
1191 uint32_t temp;
1192
0e32b39c 1193 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
c9809791 1194 temp = TRANS_MSA_SYNC_CLK;
965e0c48 1195 switch (intel_crtc->config.pipe_bpp) {
dae84799 1196 case 18:
c9809791 1197 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1198 break;
1199 case 24:
c9809791 1200 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1201 break;
1202 case 30:
c9809791 1203 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1204 break;
1205 case 36:
c9809791 1206 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1207 break;
1208 default:
4e53c2e0 1209 BUG();
dae84799 1210 }
c9809791 1211 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1212 }
1213}
1214
0e32b39c
DA		 1215void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1216{
1217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1218 struct drm_device *dev = crtc->dev;
1219 struct drm_i915_private *dev_priv = dev->dev_private;
1220 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1221 uint32_t temp;
1222 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1223 if (state == true)
1224 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1225 else
1226 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1227 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1228}
1229
8228c251 1230void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1231{
1232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1233 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1234 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 1235 struct drm_device *dev = crtc->dev;
1236 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 1237 enum pipe pipe = intel_crtc->pipe;
3b117c8f 1238 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
174edf1f 1239 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1240 int type = intel_encoder->type;
8d9ddbcb
PZ		 1241 uint32_t temp;
1242
ad80a810
PZ		 1243 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1244 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1245 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1246
965e0c48 1247 switch (intel_crtc->config.pipe_bpp) {
dfcef252 1248 case 18:
ad80a810 1249 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1250 break;
1251 case 24:
ad80a810 1252 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1253 break;
1254 case 30:
ad80a810 1255 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1256 break;
1257 case 36:
ad80a810 1258 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1259 break;
1260 default:
4e53c2e0 1261 BUG();
dfcef252 1262 }
72662e10 1263
a666283e 1264 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1265 temp |= TRANS_DDI_PVSYNC;
a666283e 1266 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1267 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1268
e6f0bfc4
PZ		 1269 if (cpu_transcoder == TRANSCODER_EDP) {
1270 switch (pipe) {
1271 case PIPE_A:
c7670b10
PZ		 1272 /* On Haswell, can only use the always-on power well for
1273 * eDP when not using the panel fitter, and when not
1274 * using motion blur mitigation (which we don't
1275 * support). */
fabf6e51
DV		 1276 if (IS_HASWELL(dev) &&
1277 (intel_crtc->config.pch_pfit.enabled ||
1278 intel_crtc->config.pch_pfit.force_thru))
d6dd9eb1
DV		 1279 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1280 else
1281 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1282 break;
1283 case PIPE_B:
1284 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1285 break;
1286 case PIPE_C:
1287 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1288 break;
1289 default:
1290 BUG();
1291 break;
1292 }
1293 }
1294
7739c33b 1295 if (type == INTEL_OUTPUT_HDMI) {
6897b4b5 1296 if (intel_crtc->config.has_hdmi_sink)
ad80a810 1297 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1298 else
ad80a810 1299 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1300
7739c33b 1301 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1302 temp |= TRANS_DDI_MODE_SELECT_FDI;
33d29b14 1303 temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
7739c33b
PZ		 1304
1305 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1306 type == INTEL_OUTPUT_EDP) {
1307 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1308
0e32b39c
DA		 1309 if (intel_dp->is_mst) {
1310 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1311 } else
1312 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1313
1314 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1315 } else if (type == INTEL_OUTPUT_DP_MST) {
1316 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1317
1318 if (intel_dp->is_mst) {
1319 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1320 } else
1321 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1322
17aa6be9 1323 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
8d9ddbcb 1324 } else {
84f44ce7
VS		 1325 WARN(1, "Invalid encoder type %d for pipe %c\n",
1326 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1327 }
1328
ad80a810 1329 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1330}
72662e10 1331
ad80a810
PZ		 1332void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1333 enum transcoder cpu_transcoder)
8d9ddbcb 1334{
ad80a810 1335 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1336 uint32_t val = I915_READ(reg);
1337
0e32b39c 1338 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1339 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1340 I915_WRITE(reg, val);
72662e10
ED		 1341}
1342
bcbc889b
PZ		 1343bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1344{
1345 struct drm_device *dev = intel_connector->base.dev;
1346 struct drm_i915_private *dev_priv = dev->dev_private;
1347 struct intel_encoder *intel_encoder = intel_connector->encoder;
1348 int type = intel_connector->base.connector_type;
1349 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1350 enum pipe pipe = 0;
1351 enum transcoder cpu_transcoder;
882244a3 1352 enum intel_display_power_domain power_domain;
bcbc889b
PZ		 1353 uint32_t tmp;
1354
882244a3 1355 power_domain = intel_display_port_power_domain(intel_encoder);
f458ebbc 1356 if (!intel_display_power_is_enabled(dev_priv, power_domain))
882244a3
PZ		 1357 return false;
1358
bcbc889b
PZ		 1359 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1360 return false;
1361
1362 if (port == PORT_A)
1363 cpu_transcoder = TRANSCODER_EDP;
1364 else
1a240d4d 1365 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1366
1367 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1368
1369 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1370 case TRANS_DDI_MODE_SELECT_HDMI:
1371 case TRANS_DDI_MODE_SELECT_DVI:
1372 return (type == DRM_MODE_CONNECTOR_HDMIA);
1373
1374 case TRANS_DDI_MODE_SELECT_DP_SST:
1375 if (type == DRM_MODE_CONNECTOR_eDP)
1376 return true;
bcbc889b 1377 return (type == DRM_MODE_CONNECTOR_DisplayPort);
0e32b39c
DA		 1378 case TRANS_DDI_MODE_SELECT_DP_MST:
1379 /* if the transcoder is in MST state then
1380 * connector isn't connected */
1381 return false;
bcbc889b
PZ		 1382
1383 case TRANS_DDI_MODE_SELECT_FDI:
1384 return (type == DRM_MODE_CONNECTOR_VGA);
1385
1386 default:
1387 return false;
1388 }
1389}
1390
85234cdc
DV		 1391bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1392 enum pipe *pipe)
1393{
1394 struct drm_device *dev = encoder->base.dev;
1395 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 1396 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 1397 enum intel_display_power_domain power_domain;
85234cdc
DV		 1398 u32 tmp;
1399 int i;
1400
6d129bea 1401 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1402 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1403 return false;
1404
fe43d3f5 1405 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1406
1407 if (!(tmp & DDI_BUF_CTL_ENABLE))
1408 return false;
1409
ad80a810
PZ		 1410 if (port == PORT_A) {
1411 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1412
ad80a810
PZ		 1413 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1414 case TRANS_DDI_EDP_INPUT_A_ON:
1415 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1416 *pipe = PIPE_A;
1417 break;
1418 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1419 *pipe = PIPE_B;
1420 break;
1421 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1422 *pipe = PIPE_C;
1423 break;
1424 }
1425
1426 return true;
1427 } else {
1428 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1429 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1430
1431 if ((tmp & TRANS_DDI_PORT_MASK)
1432 == TRANS_DDI_SELECT_PORT(port)) {
0e32b39c
DA		 1433 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1434 return false;
1435
ad80a810
PZ		 1436 *pipe = i;
1437 return true;
1438 }
85234cdc
DV		 1439 }
1440 }
1441
84f44ce7 1442 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 1443
22f9fe50 1444 return false;
85234cdc
DV		 1445}
1446
fc914639
PZ		 1447void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1448{
1449 struct drm_crtc *crtc = &intel_crtc->base;
1450 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1451 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1452 enum port port = intel_ddi_get_encoder_port(intel_encoder);
3b117c8f 1453 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
fc914639 1454
bb523fc0
PZ		 1455 if (cpu_transcoder != TRANSCODER_EDP)
1456 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1457 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1458}
1459
1460void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1461{
1462 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3b117c8f 1463 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
fc914639 1464
bb523fc0
PZ		 1465 if (cpu_transcoder != TRANSCODER_EDP)
1466 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1467 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1468}
1469
00c09d70 1470static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
6441ab5f 1471{
c19b0669 1472 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 1473 struct drm_device *dev = encoder->dev;
1474 struct drm_i915_private *dev_priv = dev->dev_private;
30cf6db8 1475 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
6441ab5f 1476 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1477 int type = intel_encoder->type;
6441ab5f 1478
82a4d9c0
PZ		 1479 if (type == INTEL_OUTPUT_EDP) {
1480 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4be73780 1481 intel_edp_panel_on(intel_dp);
82a4d9c0 1482 }
6441ab5f 1483
efa80add
S		 1484 if (IS_SKYLAKE(dev)) {
1485 uint32_t dpll = crtc->config.ddi_pll_sel;
1486 uint32_t val;
1487
5416d871
DL		 1488 /*
1489 * DPLL0 is used for eDP and is the only "private" DPLL (as
1490 * opposed to shared) on SKL
1491 */
1492 if (type == INTEL_OUTPUT_EDP) {
1493 WARN_ON(dpll != SKL_DPLL0);
1494
1495 val = I915_READ(DPLL_CTRL1);
1496
1497 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
1498 DPLL_CTRL1_SSC(dpll) |
1499 DPLL_CRTL1_LINK_RATE_MASK(dpll));
1500 val |= crtc->config.dpll_hw_state.ctrl1 << (dpll * 6);
1501
1502 I915_WRITE(DPLL_CTRL1, val);
1503 POSTING_READ(DPLL_CTRL1);
1504 }
1505
1506 /* DDI -> PLL mapping */
efa80add
S		 1507 val = I915_READ(DPLL_CTRL2);
1508
1509 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1510 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1511 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1512 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1513
1514 I915_WRITE(DPLL_CTRL2, val);
5416d871 1515
efa80add
S		 1516 } else {
1517 WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE);
1518 I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel);
1519 }
c19b0669 1520
82a4d9c0 1521 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669 1522 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 1523
44905a27 1524 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 1525
1526 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1527 intel_dp_start_link_train(intel_dp);
1528 intel_dp_complete_link_train(intel_dp);
23f08d83 1529 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
3ab9c637 1530 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 1531 } else if (type == INTEL_OUTPUT_HDMI) {
1532 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1533
1534 intel_hdmi->set_infoframes(encoder,
1535 crtc->config.has_hdmi_sink,
1536 &crtc->config.adjusted_mode);
c19b0669 1537 }
6441ab5f
PZ		 1538}
1539
00c09d70 1540static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 1541{
1542 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 1543 struct drm_device *dev = encoder->dev;
1544 struct drm_i915_private *dev_priv = dev->dev_private;
6441ab5f 1545 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1546 int type = intel_encoder->type;
2886e93f 1547 uint32_t val;
a836bdf9 1548 bool wait = false;
2886e93f
PZ		 1549
1550 val = I915_READ(DDI_BUF_CTL(port));
1551 if (val & DDI_BUF_CTL_ENABLE) {
1552 val &= ~DDI_BUF_CTL_ENABLE;
1553 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 1554 wait = true;
2886e93f 1555 }
6441ab5f 1556
a836bdf9
PZ		 1557 val = I915_READ(DP_TP_CTL(port));
1558 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1559 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1560 I915_WRITE(DP_TP_CTL(port), val);
1561
1562 if (wait)
1563 intel_wait_ddi_buf_idle(dev_priv, port);
1564
76bb80ed 1565 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 1566 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 1567 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 1568 intel_edp_panel_vdd_on(intel_dp);
4be73780 1569 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 1570 }
1571
efa80add
S		 1572 if (IS_SKYLAKE(dev))
1573 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1574 DPLL_CTRL2_DDI_CLK_OFF(port)));
1575 else
1576 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
6441ab5f
PZ		 1577}
1578
00c09d70 1579static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 1580{
6547fef8 1581 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1582 struct drm_crtc *crtc = encoder->crtc;
1583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 1584 struct drm_device *dev = encoder->dev;
72662e10 1585 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 1586 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1587 int type = intel_encoder->type;
72662e10 1588
6547fef8 1589 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 1590 struct intel_digital_port *intel_dig_port =
1591 enc_to_dig_port(encoder);
1592
6547fef8
PZ		 1593 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1594 * are ignored so nothing special needs to be done besides
1595 * enabling the port.
1596 */
876a8cdf 1597 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 1598 intel_dig_port->saved_port_bits |
1599 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 1600 } else if (type == INTEL_OUTPUT_EDP) {
1601 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1602
23f08d83 1603 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 1604 intel_dp_stop_link_train(intel_dp);
1605
4be73780 1606 intel_edp_backlight_on(intel_dp);
0bc12bcb 1607 intel_psr_enable(intel_dp);
6547fef8 1608 }
7b9f35a6 1609
9ed109a7 1610 if (intel_crtc->config.has_audio) {
d45a0bf5 1611 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 1612 intel_audio_codec_enable(intel_encoder);
7b9f35a6 1613 }
5ab432ef
DV		 1614}
1615
00c09d70 1616static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 1617{
d6c50ff8 1618 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1619 struct drm_crtc *crtc = encoder->crtc;
1620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 1621 int type = intel_encoder->type;
7b9f35a6
WX		 1622 struct drm_device *dev = encoder->dev;
1623 struct drm_i915_private *dev_priv = dev->dev_private;
d6c50ff8 1624
d45a0bf5 1625 if (intel_crtc->config.has_audio) {
69bfe1a9 1626 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 1627 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1628 }
2831d842 1629
d6c50ff8
PZ		 1630 if (type == INTEL_OUTPUT_EDP) {
1631 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1632
0bc12bcb 1633 intel_psr_disable(intel_dp);
4be73780 1634 intel_edp_backlight_off(intel_dp);
d6c50ff8 1635 }
72662e10 1636}
79f689aa 1637
121643c2
S		 1638static int skl_get_cdclk_freq(struct drm_i915_private *dev_priv)
1639{
1640 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
1641 uint32_t cdctl = I915_READ(CDCLK_CTL);
1642 uint32_t linkrate;
1643
1644 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
1645 WARN(1, "LCPLL1 not enabled\n");
1646 return 24000; /* 24MHz is the cd freq with NSSC ref */
1647 }
1648
1649 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
1650 return 540000;
1651
1652 linkrate = (I915_READ(DPLL_CTRL1) &
1653 DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1654
1655 if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
1656 linkrate == DPLL_CRTL1_LINK_RATE_1080) {
1657 /* vco 8640 */
1658 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
1659 case CDCLK_FREQ_450_432:
1660 return 432000;
1661 case CDCLK_FREQ_337_308:
1662 return 308570;
1663 case CDCLK_FREQ_675_617:
1664 return 617140;
1665 default:
1666 WARN(1, "Unknown cd freq selection\n");
1667 }
1668 } else {
1669 /* vco 8100 */
1670 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
1671 case CDCLK_FREQ_450_432:
1672 return 450000;
1673 case CDCLK_FREQ_337_308:
1674 return 337500;
1675 case CDCLK_FREQ_675_617:
1676 return 675000;
1677 default:
1678 WARN(1, "Unknown cd freq selection\n");
1679 }
1680 }
1681
1682 /* error case, do as if DPLL0 isn't enabled */
1683 return 24000;
1684}
1685
ad13d604
DL		 1686static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv)
1687{
1688 uint32_t lcpll = I915_READ(LCPLL_CTL);
1689 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1690
1691 if (lcpll & LCPLL_CD_SOURCE_FCLK)
1692 return 800000;
1693 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1694 return 450000;
1695 else if (freq == LCPLL_CLK_FREQ_450)
1696 return 450000;
1697 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
1698 return 540000;
1699 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
1700 return 337500;
1701 else
1702 return 675000;
1703}
1704
1705static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv)
79f689aa 1706{
e39bf98a 1707 struct drm_device *dev = dev_priv->dev;
a4006641 1708 uint32_t lcpll = I915_READ(LCPLL_CTL);
e39bf98a 1709 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
a4006641 1710
ad13d604 1711 if (lcpll & LCPLL_CD_SOURCE_FCLK)
a4006641 1712 return 800000;
ad13d604 1713 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
b2b877ff 1714 return 450000;
ad13d604 1715 else if (freq == LCPLL_CLK_FREQ_450)
b2b877ff 1716 return 450000;
95626e7c 1717 else if (IS_HSW_ULT(dev))
ad13d604
DL		 1718 return 337500;
1719 else
1720 return 540000;
1721}
1722
1723int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1724{
1725 struct drm_device *dev = dev_priv->dev;
1726
121643c2
S		 1727 if (IS_SKYLAKE(dev))
1728 return skl_get_cdclk_freq(dev_priv);
1729
ad13d604
DL		 1730 if (IS_BROADWELL(dev))
1731 return bdw_get_cdclk_freq(dev_priv);
1732
1733 /* Haswell */
1734 return hsw_get_cdclk_freq(dev_priv);
79f689aa
PZ		 1735}
1736
e0b01be4
DV		 1737static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
1738 struct intel_shared_dpll *pll)
1739{
3e369b76 1740 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
e0b01be4
DV		 1741 POSTING_READ(WRPLL_CTL(pll->id));
1742 udelay(20);
1743}
1744
12030431
DV		 1745static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
1746 struct intel_shared_dpll *pll)
1747{
1748 uint32_t val;
1749
1750 val = I915_READ(WRPLL_CTL(pll->id));
12030431
DV		 1751 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
1752 POSTING_READ(WRPLL_CTL(pll->id));
1753}
1754
d452c5b6
DV		 1755static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1756 struct intel_shared_dpll *pll,
1757 struct intel_dpll_hw_state *hw_state)
1758{
1759 uint32_t val;
1760
f458ebbc 1761 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
d452c5b6
DV		 1762 return false;
1763
1764 val = I915_READ(WRPLL_CTL(pll->id));
1765 hw_state->wrpll = val;
1766
1767 return val & WRPLL_PLL_ENABLE;
1768}
1769
ca1381b5 1770static const char * const hsw_ddi_pll_names[] = {
9cd86933
DV		 1771 "WRPLL 1",
1772 "WRPLL 2",
1773};
1774
143b307c 1775static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
79f689aa 1776{
9cd86933
DV		 1777 int i;
1778
716c2e55 1779 dev_priv->num_shared_dpll = 2;
9cd86933 1780
716c2e55 1781 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9cd86933
DV		 1782 dev_priv->shared_dplls[i].id = i;
1783 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
12030431 1784 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
e0b01be4 1785 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
d452c5b6
DV		 1786 dev_priv->shared_dplls[i].get_hw_state =
1787 hsw_ddi_pll_get_hw_state;
9cd86933 1788 }
143b307c
DL		 1789}
1790
d1a2dc78
S		 1791static const char * const skl_ddi_pll_names[] = {
1792 "DPLL 1",
1793 "DPLL 2",
1794 "DPLL 3",
1795};
1796
1797struct skl_dpll_regs {
1798 u32 ctl, cfgcr1, cfgcr2;
1799};
1800
1801/* this array is indexed by the *shared* pll id */
1802static const struct skl_dpll_regs skl_dpll_regs[3] = {
1803 {
1804 /* DPLL 1 */
1805 .ctl = LCPLL2_CTL,
1806 .cfgcr1 = DPLL1_CFGCR1,
1807 .cfgcr2 = DPLL1_CFGCR2,
1808 },
1809 {
1810 /* DPLL 2 */
1811 .ctl = WRPLL_CTL1,
1812 .cfgcr1 = DPLL2_CFGCR1,
1813 .cfgcr2 = DPLL2_CFGCR2,
1814 },
1815 {
1816 /* DPLL 3 */
1817 .ctl = WRPLL_CTL2,
1818 .cfgcr1 = DPLL3_CFGCR1,
1819 .cfgcr2 = DPLL3_CFGCR2,
1820 },
1821};
1822
1823static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
1824 struct intel_shared_dpll *pll)
1825{
1826 uint32_t val;
1827 unsigned int dpll;
1828 const struct skl_dpll_regs *regs = skl_dpll_regs;
1829
1830 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
1831 dpll = pll->id + 1;
1832
1833 val = I915_READ(DPLL_CTRL1);
1834
1835 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
1836 DPLL_CRTL1_LINK_RATE_MASK(dpll));
1837 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
1838
1839 I915_WRITE(DPLL_CTRL1, val);
1840 POSTING_READ(DPLL_CTRL1);
1841
1842 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
1843 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
1844 POSTING_READ(regs[pll->id].cfgcr1);
1845 POSTING_READ(regs[pll->id].cfgcr2);
1846
1847 /* the enable bit is always bit 31 */
1848 I915_WRITE(regs[pll->id].ctl,
1849 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
1850
1851 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
1852 DRM_ERROR("DPLL %d not locked\n", dpll);
1853}
1854
1855static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
1856 struct intel_shared_dpll *pll)
1857{
1858 const struct skl_dpll_regs *regs = skl_dpll_regs;
1859
1860 /* the enable bit is always bit 31 */
1861 I915_WRITE(regs[pll->id].ctl,
1862 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
1863 POSTING_READ(regs[pll->id].ctl);
1864}
1865
1866static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1867 struct intel_shared_dpll *pll,
1868 struct intel_dpll_hw_state *hw_state)
1869{
1870 uint32_t val;
1871 unsigned int dpll;
1872 const struct skl_dpll_regs *regs = skl_dpll_regs;
1873
1874 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
1875 return false;
1876
1877 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
1878 dpll = pll->id + 1;
1879
1880 val = I915_READ(regs[pll->id].ctl);
1881 if (!(val & LCPLL_PLL_ENABLE))
1882 return false;
1883
1884 val = I915_READ(DPLL_CTRL1);
1885 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
1886
1887 /* avoid reading back stale values if HDMI mode is not enabled */
1888 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
1889 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
1890 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
1891 }
1892
1893 return true;
1894}
1895
1896static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
1897{
1898 int i;
1899
1900 dev_priv->num_shared_dpll = 3;
1901
1902 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
1903 dev_priv->shared_dplls[i].id = i;
1904 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
1905 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
1906 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
1907 dev_priv->shared_dplls[i].get_hw_state =
1908 skl_ddi_pll_get_hw_state;
1909 }
1910}
1911
143b307c
DL		 1912void intel_ddi_pll_init(struct drm_device *dev)
1913{
1914 struct drm_i915_private *dev_priv = dev->dev_private;
1915 uint32_t val = I915_READ(LCPLL_CTL);
1916
d1a2dc78
S		 1917 if (IS_SKYLAKE(dev))
1918 skl_shared_dplls_init(dev_priv);
1919 else
1920 hsw_shared_dplls_init(dev_priv);
79f689aa 1921
b2b877ff 1922 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
79f689aa
PZ		 1923 intel_ddi_get_cdclk_freq(dev_priv));
1924
121643c2
S		 1925 if (IS_SKYLAKE(dev)) {
1926 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
1927 DRM_ERROR("LCPLL1 is disabled\n");
1928 } else {
1929 /*
1930 * The LCPLL register should be turned on by the BIOS. For now
1931 * let's just check its state and print errors in case
1932 * something is wrong. Don't even try to turn it on.
1933 */
1934
1935 if (val & LCPLL_CD_SOURCE_FCLK)
1936 DRM_ERROR("CDCLK source is not LCPLL\n");
79f689aa 1937
121643c2
S		 1938 if (val & LCPLL_PLL_DISABLE)
1939 DRM_ERROR("LCPLL is disabled\n");
1940 }
79f689aa 1941}
c19b0669
PZ		 1942
1943void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1944{
174edf1f
PZ		 1945 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1946 struct intel_dp *intel_dp = &intel_dig_port->dp;
c19b0669 1947 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
174edf1f 1948 enum port port = intel_dig_port->port;
c19b0669 1949 uint32_t val;
f3e227df 1950 bool wait = false;
c19b0669
PZ		 1951
1952 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1953 val = I915_READ(DDI_BUF_CTL(port));
1954 if (val & DDI_BUF_CTL_ENABLE) {
1955 val &= ~DDI_BUF_CTL_ENABLE;
1956 I915_WRITE(DDI_BUF_CTL(port), val);
1957 wait = true;
1958 }
1959
1960 val = I915_READ(DP_TP_CTL(port));
1961 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1962 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1963 I915_WRITE(DP_TP_CTL(port), val);
1964 POSTING_READ(DP_TP_CTL(port));
1965
1966 if (wait)
1967 intel_wait_ddi_buf_idle(dev_priv, port);
1968 }
1969
0e32b39c 1970 val = DP_TP_CTL_ENABLE |
c19b0669 1971 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 1972 if (intel_dp->is_mst)
1973 val |= DP_TP_CTL_MODE_MST;
1974 else {
1975 val |= DP_TP_CTL_MODE_SST;
1976 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1977 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1978 }
c19b0669
PZ		 1979 I915_WRITE(DP_TP_CTL(port), val);
1980 POSTING_READ(DP_TP_CTL(port));
1981
1982 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1983 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1984 POSTING_READ(DDI_BUF_CTL(port));
1985
1986 udelay(600);
1987}
00c09d70 1988
1ad960f2
PZ		 1989void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1990{
1991 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1992 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1993 uint32_t val;
1994
1995 intel_ddi_post_disable(intel_encoder);
1996
1997 val = I915_READ(_FDI_RXA_CTL);
1998 val &= ~FDI_RX_ENABLE;
1999 I915_WRITE(_FDI_RXA_CTL, val);
2000
2001 val = I915_READ(_FDI_RXA_MISC);
2002 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2003 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2004 I915_WRITE(_FDI_RXA_MISC, val);
2005
2006 val = I915_READ(_FDI_RXA_CTL);
2007 val &= ~FDI_PCDCLK;
2008 I915_WRITE(_FDI_RXA_CTL, val);
2009
2010 val = I915_READ(_FDI_RXA_CTL);
2011 val &= ~FDI_RX_PLL_ENABLE;
2012 I915_WRITE(_FDI_RXA_CTL, val);
2013}
2014
00c09d70
PZ		 2015static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
2016{
0e32b39c
DA		 2017 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base);
2018 int type = intel_dig_port->base.type;
2019
2020 if (type != INTEL_OUTPUT_DISPLAYPORT &&
2021 type != INTEL_OUTPUT_EDP &&
2022 type != INTEL_OUTPUT_UNKNOWN) {
2023 return;
2024 }
00c09d70 2025
0e32b39c 2026 intel_dp_hot_plug(intel_encoder);
00c09d70
PZ		 2027}
2028
6801c18c 2029void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 2030 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2031{
2032 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
2033 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2034 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
bbd440fb 2035 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 2036 u32 temp, flags = 0;
2037
2038 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2039 if (temp & TRANS_DDI_PHSYNC)
2040 flags |= DRM_MODE_FLAG_PHSYNC;
2041 else
2042 flags |= DRM_MODE_FLAG_NHSYNC;
2043 if (temp & TRANS_DDI_PVSYNC)
2044 flags |= DRM_MODE_FLAG_PVSYNC;
2045 else
2046 flags |= DRM_MODE_FLAG_NVSYNC;
2047
2048 pipe_config->adjusted_mode.flags |= flags;
42571aef
VS		 2049
2050 switch (temp & TRANS_DDI_BPC_MASK) {
2051 case TRANS_DDI_BPC_6:
2052 pipe_config->pipe_bpp = 18;
2053 break;
2054 case TRANS_DDI_BPC_8:
2055 pipe_config->pipe_bpp = 24;
2056 break;
2057 case TRANS_DDI_BPC_10:
2058 pipe_config->pipe_bpp = 30;
2059 break;
2060 case TRANS_DDI_BPC_12:
2061 pipe_config->pipe_bpp = 36;
2062 break;
2063 default:
2064 break;
2065 }
eb14cb74
VS		 2066
2067 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2068 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 2069 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 2070 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2071
2072 if (intel_hdmi->infoframe_enabled(&encoder->base))
2073 pipe_config->has_infoframe = true;
cbc572a9 2074 break;
eb14cb74
VS		 2075 case TRANS_DDI_MODE_SELECT_DVI:
2076 case TRANS_DDI_MODE_SELECT_FDI:
2077 break;
2078 case TRANS_DDI_MODE_SELECT_DP_SST:
2079 case TRANS_DDI_MODE_SELECT_DP_MST:
2080 pipe_config->has_dp_encoder = true;
2081 intel_dp_get_m_n(intel_crtc, pipe_config);
2082 break;
2083 default:
2084 break;
2085 }
10214420 2086
f458ebbc 2087 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
a60551b1 2088 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
82910ac6 2089 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
a60551b1
PZ		 2090 pipe_config->has_audio = true;
2091 }
9ed109a7 2092
10214420
DV		 2093 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
2094 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2095 /*
2096 * This is a big fat ugly hack.
2097 *
2098 * Some machines in UEFI boot mode provide us a VBT that has 18
2099 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2100 * unknown we fail to light up. Yet the same BIOS boots up with
2101 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2102 * max, not what it tells us to use.
2103 *
2104 * Note: This will still be broken if the eDP panel is not lit
2105 * up by the BIOS, and thus we can't get the mode at module
2106 * load.
2107 */
2108 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2109 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2110 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2111 }
11578553 2112
22606a18 2113 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 2114}
2115
00c09d70
PZ		 2116static void intel_ddi_destroy(struct drm_encoder *encoder)
2117{
2118 /* HDMI has nothing special to destroy, so we can go with this. */
2119 intel_dp_encoder_destroy(encoder);
2120}
2121
5bfe2ac0 2122static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 2123 struct intel_crtc_state *pipe_config)
00c09d70 2124{
5bfe2ac0 2125 int type = encoder->type;
eccb140b 2126 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 2127
5bfe2ac0 2128 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 2129
eccb140b
DV		 2130 if (port == PORT_A)
2131 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2132
00c09d70 2133 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 2134 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 2135 else
5bfe2ac0 2136 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 2137}
2138
2139static const struct drm_encoder_funcs intel_ddi_funcs = {
2140 .destroy = intel_ddi_destroy,
2141};
2142
4a28ae58
PZ		 2143static struct intel_connector *
2144intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2145{
2146 struct intel_connector *connector;
2147 enum port port = intel_dig_port->port;
2148
2149 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
2150 if (!connector)
2151 return NULL;
2152
2153 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2154 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2155 kfree(connector);
2156 return NULL;
2157 }
2158
2159 return connector;
2160}
2161
2162static struct intel_connector *
2163intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2164{
2165 struct intel_connector *connector;
2166 enum port port = intel_dig_port->port;
2167
2168 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
2169 if (!connector)
2170 return NULL;
2171
2172 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2173 intel_hdmi_init_connector(intel_dig_port, connector);
2174
2175 return connector;
2176}
2177
00c09d70
PZ		 2178void intel_ddi_init(struct drm_device *dev, enum port port)
2179{
876a8cdf 2180 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 2181 struct intel_digital_port *intel_dig_port;
2182 struct intel_encoder *intel_encoder;
2183 struct drm_encoder *encoder;
311a2094
PZ		 2184 bool init_hdmi, init_dp;
2185
2186 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2187 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2188 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2189 if (!init_dp && !init_hdmi) {
f68d697e 2190 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
311a2094
PZ		 2191 port_name(port));
2192 init_hdmi = true;
2193 init_dp = true;
2194 }
00c09d70 2195
b14c5679 2196 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 2197 if (!intel_dig_port)
2198 return;
2199
00c09d70
PZ		 2200 intel_encoder = &intel_dig_port->base;
2201 encoder = &intel_encoder->base;
2202
2203 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
2204 DRM_MODE_ENCODER_TMDS);
00c09d70 2205
5bfe2ac0 2206 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 2207 intel_encoder->enable = intel_enable_ddi;
2208 intel_encoder->pre_enable = intel_ddi_pre_enable;
2209 intel_encoder->disable = intel_disable_ddi;
2210 intel_encoder->post_disable = intel_ddi_post_disable;
2211 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 2212 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 2213
2214 intel_dig_port->port = port;
bcf53de4
SM		 2215 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2216 (DDI_BUF_PORT_REVERSAL |
2217 DDI_A_4_LANES);
00c09d70
PZ		 2218
2219 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 2220 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 2221 intel_encoder->cloneable = 0;
00c09d70
PZ		 2222 intel_encoder->hot_plug = intel_ddi_hot_plug;
2223
f68d697e
CW		 2224 if (init_dp) {
2225 if (!intel_ddi_init_dp_connector(intel_dig_port))
2226 goto err;
13cf5504 2227
f68d697e
CW		 2228 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2229 dev_priv->hpd_irq_port[port] = intel_dig_port;
2230 }
21a8e6a4 2231
311a2094
PZ		 2232 /* In theory we don't need the encoder->type check, but leave it just in
2233 * case we have some really bad VBTs... */
f68d697e
CW		 2234 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2235 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2236 goto err;
21a8e6a4 2237 }
f68d697e
CW		 2238
2239 return;
2240
2241err:
2242 drm_encoder_cleanup(encoder);
2243 kfree(intel_dig_port);
00c09d70 2244}
Linux kernel - Deliverables
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