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drm/i915: Fix race condition in accessing GMBUS
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
23b2f8bb 27#include <linux/cpufreq.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
7662c8bd 47static void intel_update_watermarks(struct drm_device *dev);
3dec0095 48static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 49static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 50
51typedef struct {
0206e353
AJ		 52 /* given values */
53 int n;
54 int m1, m2;
55 int p1, p2;
56 /* derived values */
57 int dot;
58 int vco;
59 int m;
60 int p;
79e53945
JB		 61} intel_clock_t;
62
63typedef struct {
0206e353 64 int min, max;
79e53945
JB		 65} intel_range_t;
66
67typedef struct {
0206e353
AJ		 68 int dot_limit;
69 int p2_slow, p2_fast;
79e53945
JB		 70} intel_p2_t;
71
72#define INTEL_P2_NUM 2
d4906093
ML		 73typedef struct intel_limit intel_limit_t;
74struct intel_limit {
0206e353
AJ		 75 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 intel_p2_t p2;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 78 int, int, intel_clock_t *, intel_clock_t *);
d4906093 79};
79e53945 80
2377b741
JB		 81/* FDI */
82#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
83
d4906093
ML		 84static bool
85intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 86 int target, int refclk, intel_clock_t *match_clock,
87 intel_clock_t *best_clock);
d4906093
ML		 88static bool
89intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 90 int target, int refclk, intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
79e53945 92
a4fc5ed6
KP		 93static bool
94intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
5eb08b69 97static bool
f2b115e6 98intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
a4fc5ed6 101
021357ac
CW		 102static inline u32 /* units of 100MHz */
103intel_fdi_link_freq(struct drm_device *dev)
104{
8b99e68c
CW		 105 if (IS_GEN5(dev)) {
106 struct drm_i915_private *dev_priv = dev->dev_private;
107 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
108 } else
109 return 27;
021357ac
CW		 110}
111
e4b36699 112static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 113 .dot = { .min = 25000, .max = 350000 },
114 .vco = { .min = 930000, .max = 1400000 },
115 .n = { .min = 3, .max = 16 },
116 .m = { .min = 96, .max = 140 },
117 .m1 = { .min = 18, .max = 26 },
118 .m2 = { .min = 6, .max = 16 },
119 .p = { .min = 4, .max = 128 },
120 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 121 .p2 = { .dot_limit = 165000,
122 .p2_slow = 4, .p2_fast = 2 },
d4906093 123 .find_pll = intel_find_best_PLL,
e4b36699
KP		 124};
125
126static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 14, .p2_fast = 7 },
d4906093 137 .find_pll = intel_find_best_PLL,
e4b36699 138};
273e27ca 139
e4b36699 140static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 141 .dot = { .min = 20000, .max = 400000 },
142 .vco = { .min = 1400000, .max = 2800000 },
143 .n = { .min = 1, .max = 6 },
144 .m = { .min = 70, .max = 120 },
145 .m1 = { .min = 10, .max = 22 },
146 .m2 = { .min = 5, .max = 9 },
147 .p = { .min = 5, .max = 80 },
148 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 149 .p2 = { .dot_limit = 200000,
150 .p2_slow = 10, .p2_fast = 5 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699
KP		 152};
153
154static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 7, .max = 98 },
162 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 163 .p2 = { .dot_limit = 112000,
164 .p2_slow = 14, .p2_fast = 7 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699
KP		 166};
167
273e27ca 168
e4b36699 169static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 170 .dot = { .min = 25000, .max = 270000 },
171 .vco = { .min = 1750000, .max = 3500000},
172 .n = { .min = 1, .max = 4 },
173 .m = { .min = 104, .max = 138 },
174 .m1 = { .min = 17, .max = 23 },
175 .m2 = { .min = 5, .max = 11 },
176 .p = { .min = 10, .max = 30 },
177 .p1 = { .min = 1, .max = 3},
178 .p2 = { .dot_limit = 270000,
179 .p2_slow = 10,
180 .p2_fast = 10
044c7c41 181 },
d4906093 182 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 183};
184
185static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 186 .dot = { .min = 22000, .max = 400000 },
187 .vco = { .min = 1750000, .max = 3500000},
188 .n = { .min = 1, .max = 4 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 16, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 5, .max = 80 },
193 .p1 = { .min = 1, .max = 8},
194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 10, .p2_fast = 5 },
d4906093 196 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 200 .dot = { .min = 20000, .max = 115000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 28, .max = 112 },
207 .p1 = { .min = 2, .max = 8 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 14, .p2_fast = 14
044c7c41 210 },
d4906093 211 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 212};
213
214static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 215 .dot = { .min = 80000, .max = 224000 },
216 .vco = { .min = 1750000, .max = 3500000 },
217 .n = { .min = 1, .max = 3 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 14, .max = 42 },
222 .p1 = { .min = 2, .max = 6 },
223 .p2 = { .dot_limit = 0,
224 .p2_slow = 7, .p2_fast = 7
044c7c41 225 },
d4906093 226 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 227};
228
229static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 230 .dot = { .min = 161670, .max = 227000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 2 },
233 .m = { .min = 97, .max = 108 },
234 .m1 = { .min = 0x10, .max = 0x12 },
235 .m2 = { .min = 0x05, .max = 0x06 },
236 .p = { .min = 10, .max = 20 },
237 .p1 = { .min = 1, .max = 2},
238 .p2 = { .dot_limit = 0,
273e27ca 239 .p2_slow = 10, .p2_fast = 10 },
0206e353 240 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 241};
242
f2b115e6 243static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 244 .dot = { .min = 20000, .max = 400000},
245 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 246 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 247 .n = { .min = 3, .max = 6 },
248 .m = { .min = 2, .max = 256 },
273e27ca 249 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 250 .m1 = { .min = 0, .max = 0 },
251 .m2 = { .min = 0, .max = 254 },
252 .p = { .min = 5, .max = 80 },
253 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 254 .p2 = { .dot_limit = 200000,
255 .p2_slow = 10, .p2_fast = 5 },
6115707b 256 .find_pll = intel_find_best_PLL,
e4b36699
KP		 257};
258
f2b115e6 259static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 260 .dot = { .min = 20000, .max = 400000 },
261 .vco = { .min = 1700000, .max = 3500000 },
262 .n = { .min = 3, .max = 6 },
263 .m = { .min = 2, .max = 256 },
264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 7, .max = 112 },
267 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 268 .p2 = { .dot_limit = 112000,
269 .p2_slow = 14, .p2_fast = 14 },
6115707b 270 .find_pll = intel_find_best_PLL,
e4b36699
KP		 271};
272
273e27ca
EA		 273/* Ironlake / Sandybridge
274 *
275 * We calculate clock using (register_value + 2) for N/M1/M2, so here
276 * the range value for them is (actual_value - 2).
277 */
b91ad0ec 278static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 279 .dot = { .min = 25000, .max = 350000 },
280 .vco = { .min = 1760000, .max = 3510000 },
281 .n = { .min = 1, .max = 5 },
282 .m = { .min = 79, .max = 127 },
283 .m1 = { .min = 12, .max = 22 },
284 .m2 = { .min = 5, .max = 9 },
285 .p = { .min = 5, .max = 80 },
286 .p1 = { .min = 1, .max = 8 },
287 .p2 = { .dot_limit = 225000,
288 .p2_slow = 10, .p2_fast = 5 },
4547668a 289 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 290};
291
b91ad0ec 292static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 3 },
296 .m = { .min = 79, .max = 118 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 28, .max = 112 },
300 .p1 = { .min = 2, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 303 .find_pll = intel_g4x_find_best_PLL,
304};
305
306static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 14, .max = 56 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 317 .find_pll = intel_g4x_find_best_PLL,
318};
319
273e27ca 320/* LVDS 100mhz refclk limits. */
b91ad0ec 321static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 322 .dot = { .min = 25000, .max = 350000 },
323 .vco = { .min = 1760000, .max = 3510000 },
324 .n = { .min = 1, .max = 2 },
325 .m = { .min = 79, .max = 126 },
326 .m1 = { .min = 12, .max = 22 },
327 .m2 = { .min = 5, .max = 9 },
328 .p = { .min = 28, .max = 112 },
0206e353 329 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 330 .p2 = { .dot_limit = 225000,
331 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 332 .find_pll = intel_g4x_find_best_PLL,
333};
334
335static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 3 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 14, .max = 42 },
0206e353 343 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 346 .find_pll = intel_g4x_find_best_PLL,
347};
348
349static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000},
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 81, .max = 90 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 10, .max = 20 },
357 .p1 = { .min = 1, .max = 2},
358 .p2 = { .dot_limit = 0,
273e27ca 359 .p2_slow = 10, .p2_fast = 10 },
0206e353 360 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 361};
362
1b894b59
CW		 363static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
364 int refclk)
2c07245f 365{
b91ad0ec
ZW		 366 struct drm_device *dev = crtc->dev;
367 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 368 const intel_limit_t *limit;
b91ad0ec
ZW		 369
370 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b91ad0ec
ZW		 371 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
372 LVDS_CLKB_POWER_UP) {
373 /* LVDS dual channel */
1b894b59 374 if (refclk == 100000)
b91ad0ec
ZW		 375 limit = &intel_limits_ironlake_dual_lvds_100m;
376 else
377 limit = &intel_limits_ironlake_dual_lvds;
378 } else {
1b894b59 379 if (refclk == 100000)
b91ad0ec
ZW		 380 limit = &intel_limits_ironlake_single_lvds_100m;
381 else
382 limit = &intel_limits_ironlake_single_lvds;
383 }
384 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 385 HAS_eDP)
386 limit = &intel_limits_ironlake_display_port;
2c07245f 387 else
b91ad0ec 388 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 389
390 return limit;
391}
392
044c7c41
ML		 393static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
394{
395 struct drm_device *dev = crtc->dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 const intel_limit_t *limit;
398
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
400 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
401 LVDS_CLKB_POWER_UP)
402 /* LVDS with dual channel */
e4b36699 403 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 404 else
405 /* LVDS with dual channel */
e4b36699 406 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 407 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
408 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 409 limit = &intel_limits_g4x_hdmi;
044c7c41 410 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 411 limit = &intel_limits_g4x_sdvo;
0206e353 412 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 413 limit = &intel_limits_g4x_display_port;
044c7c41 414 } else /* The option is for other outputs */
e4b36699 415 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 416
417 return limit;
418}
419
1b894b59 420static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 421{
422 struct drm_device *dev = crtc->dev;
423 const intel_limit_t *limit;
424
bad720ff 425 if (HAS_PCH_SPLIT(dev))
1b894b59 426 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 427 else if (IS_G4X(dev)) {
044c7c41 428 limit = intel_g4x_limit(crtc);
f2b115e6 429 } else if (IS_PINEVIEW(dev)) {
2177832f 430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 431 limit = &intel_limits_pineview_lvds;
2177832f 432 else
f2b115e6 433 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 434 } else if (!IS_GEN2(dev)) {
435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
436 limit = &intel_limits_i9xx_lvds;
437 else
438 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 439 } else {
440 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 441 limit = &intel_limits_i8xx_lvds;
79e53945 442 else
e4b36699 443 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 444 }
445 return limit;
446}
447
f2b115e6
AJ		 448/* m1 is reserved as 0 in Pineview, n is a ring counter */
449static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 450{
2177832f
SL		 451 clock->m = clock->m2 + 2;
452 clock->p = clock->p1 * clock->p2;
453 clock->vco = refclk * clock->m / clock->n;
454 clock->dot = clock->vco / clock->p;
455}
456
457static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
458{
f2b115e6
AJ		 459 if (IS_PINEVIEW(dev)) {
460 pineview_clock(refclk, clock);
2177832f
SL		 461 return;
462 }
79e53945
JB		 463 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
464 clock->p = clock->p1 * clock->p2;
465 clock->vco = refclk * clock->m / (clock->n + 2);
466 clock->dot = clock->vco / clock->p;
467}
468
79e53945
JB		 469/**
470 * Returns whether any output on the specified pipe is of the specified type
471 */
4ef69c7a 472bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 473{
4ef69c7a
CW		 474 struct drm_device *dev = crtc->dev;
475 struct drm_mode_config *mode_config = &dev->mode_config;
476 struct intel_encoder *encoder;
477
478 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
479 if (encoder->base.crtc == crtc && encoder->type == type)
480 return true;
481
482 return false;
79e53945
JB		 483}
484
7c04d1d9 485#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 486/**
487 * Returns whether the given set of divisors are valid for a given refclk with
488 * the given connectors.
489 */
490
1b894b59
CW		 491static bool intel_PLL_is_valid(struct drm_device *dev,
492 const intel_limit_t *limit,
493 const intel_clock_t *clock)
79e53945 494{
79e53945 495 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 496 INTELPllInvalid("p1 out of range\n");
79e53945 497 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 498 INTELPllInvalid("p out of range\n");
79e53945 499 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 500 INTELPllInvalid("m2 out of range\n");
79e53945 501 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 502 INTELPllInvalid("m1 out of range\n");
f2b115e6 503 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 504 INTELPllInvalid("m1 <= m2\n");
79e53945 505 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 506 INTELPllInvalid("m out of range\n");
79e53945 507 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 508 INTELPllInvalid("n out of range\n");
79e53945 509 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 510 INTELPllInvalid("vco out of range\n");
79e53945
JB		 511 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
512 * connector, etc., rather than just a single range.
513 */
514 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 515 INTELPllInvalid("dot out of range\n");
79e53945
JB		 516
517 return true;
518}
519
d4906093
ML		 520static bool
521intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 522 int target, int refclk, intel_clock_t *match_clock,
523 intel_clock_t *best_clock)
d4906093 524
79e53945
JB		 525{
526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
528 intel_clock_t clock;
79e53945
JB		 529 int err = target;
530
bc5e5718 531 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 532 (I915_READ(LVDS)) != 0) {
79e53945
JB		 533 /*
534 * For LVDS, if the panel is on, just rely on its current
535 * settings for dual-channel. We haven't figured out how to
536 * reliably set up different single/dual channel state, if we
537 * even can.
538 */
539 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
540 LVDS_CLKB_POWER_UP)
541 clock.p2 = limit->p2.p2_fast;
542 else
543 clock.p2 = limit->p2.p2_slow;
544 } else {
545 if (target < limit->p2.dot_limit)
546 clock.p2 = limit->p2.p2_slow;
547 else
548 clock.p2 = limit->p2.p2_fast;
549 }
550
0206e353 551 memset(best_clock, 0, sizeof(*best_clock));
79e53945 552
42158660
ZY		 553 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
554 clock.m1++) {
555 for (clock.m2 = limit->m2.min;
556 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 557 /* m1 is always 0 in Pineview */
558 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 559 break;
560 for (clock.n = limit->n.min;
561 clock.n <= limit->n.max; clock.n++) {
562 for (clock.p1 = limit->p1.min;
563 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 564 int this_err;
565
2177832f 566 intel_clock(dev, refclk, &clock);
1b894b59
CW		 567 if (!intel_PLL_is_valid(dev, limit,
568 &clock))
79e53945 569 continue;
cec2f356
SP		 570 if (match_clock &&
571 clock.p != match_clock->p)
572 continue;
79e53945
JB		 573
574 this_err = abs(clock.dot - target);
575 if (this_err < err) {
576 *best_clock = clock;
577 err = this_err;
578 }
579 }
580 }
581 }
582 }
583
584 return (err != target);
585}
586
d4906093
ML		 587static bool
588intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 589 int target, int refclk, intel_clock_t *match_clock,
590 intel_clock_t *best_clock)
d4906093
ML		 591{
592 struct drm_device *dev = crtc->dev;
593 struct drm_i915_private *dev_priv = dev->dev_private;
594 intel_clock_t clock;
595 int max_n;
596 bool found;
6ba770dc
AJ		 597 /* approximately equals target * 0.00585 */
598 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 599 found = false;
600
601 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 602 int lvds_reg;
603
c619eed4 604 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 605 lvds_reg = PCH_LVDS;
606 else
607 lvds_reg = LVDS;
608 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 609 LVDS_CLKB_POWER_UP)
610 clock.p2 = limit->p2.p2_fast;
611 else
612 clock.p2 = limit->p2.p2_slow;
613 } else {
614 if (target < limit->p2.dot_limit)
615 clock.p2 = limit->p2.p2_slow;
616 else
617 clock.p2 = limit->p2.p2_fast;
618 }
619
620 memset(best_clock, 0, sizeof(*best_clock));
621 max_n = limit->n.max;
f77f13e2 622 /* based on hardware requirement, prefer smaller n to precision */
d4906093 623 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 624 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 625 for (clock.m1 = limit->m1.max;
626 clock.m1 >= limit->m1.min; clock.m1--) {
627 for (clock.m2 = limit->m2.max;
628 clock.m2 >= limit->m2.min; clock.m2--) {
629 for (clock.p1 = limit->p1.max;
630 clock.p1 >= limit->p1.min; clock.p1--) {
631 int this_err;
632
2177832f 633 intel_clock(dev, refclk, &clock);
1b894b59
CW		 634 if (!intel_PLL_is_valid(dev, limit,
635 &clock))
d4906093 636 continue;
cec2f356
SP		 637 if (match_clock &&
638 clock.p != match_clock->p)
639 continue;
1b894b59
CW		 640
641 this_err = abs(clock.dot - target);
d4906093
ML		 642 if (this_err < err_most) {
643 *best_clock = clock;
644 err_most = this_err;
645 max_n = clock.n;
646 found = true;
647 }
648 }
649 }
650 }
651 }
2c07245f
ZW		 652 return found;
653}
654
5eb08b69 655static bool
f2b115e6 656intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 657 int target, int refclk, intel_clock_t *match_clock,
658 intel_clock_t *best_clock)
5eb08b69
ZW		 659{
660 struct drm_device *dev = crtc->dev;
661 intel_clock_t clock;
4547668a 662
5eb08b69
ZW		 663 if (target < 200000) {
664 clock.n = 1;
665 clock.p1 = 2;
666 clock.p2 = 10;
667 clock.m1 = 12;
668 clock.m2 = 9;
669 } else {
670 clock.n = 2;
671 clock.p1 = 1;
672 clock.p2 = 10;
673 clock.m1 = 14;
674 clock.m2 = 8;
675 }
676 intel_clock(dev, refclk, &clock);
677 memcpy(best_clock, &clock, sizeof(intel_clock_t));
678 return true;
679}
680
a4fc5ed6
KP		 681/* DisplayPort has only two frequencies, 162MHz and 270MHz */
682static bool
683intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
a4fc5ed6 686{
5eddb70b
CW		 687 intel_clock_t clock;
688 if (target < 200000) {
689 clock.p1 = 2;
690 clock.p2 = 10;
691 clock.n = 2;
692 clock.m1 = 23;
693 clock.m2 = 8;
694 } else {
695 clock.p1 = 1;
696 clock.p2 = 10;
697 clock.n = 1;
698 clock.m1 = 14;
699 clock.m2 = 2;
700 }
701 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
702 clock.p = (clock.p1 * clock.p2);
703 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
704 clock.vco = 0;
705 memcpy(best_clock, &clock, sizeof(intel_clock_t));
706 return true;
a4fc5ed6
KP		 707}
708
9d0498a2
JB		 709/**
710 * intel_wait_for_vblank - wait for vblank on a given pipe
711 * @dev: drm device
712 * @pipe: pipe to wait for
713 *
714 * Wait for vblank to occur on a given pipe. Needed for various bits of
715 * mode setting code.
716 */
717void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 718{
9d0498a2 719 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 720 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 721
300387c0
CW		 722 /* Clear existing vblank status. Note this will clear any other
723 * sticky status fields as well.
724 *
725 * This races with i915_driver_irq_handler() with the result
726 * that either function could miss a vblank event. Here it is not
727 * fatal, as we will either wait upon the next vblank interrupt or
728 * timeout. Generally speaking intel_wait_for_vblank() is only
729 * called during modeset at which time the GPU should be idle and
730 * should *not* be performing page flips and thus not waiting on
731 * vblanks...
732 * Currently, the result of us stealing a vblank from the irq
733 * handler is that a single frame will be skipped during swapbuffers.
734 */
735 I915_WRITE(pipestat_reg,
736 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
737
9d0498a2 738 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 739 if (wait_for(I915_READ(pipestat_reg) &
740 PIPE_VBLANK_INTERRUPT_STATUS,
741 50))
9d0498a2
JB		 742 DRM_DEBUG_KMS("vblank wait timed out\n");
743}
744
ab7ad7f6
KP		 745/*
746 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 747 * @dev: drm device
748 * @pipe: pipe to wait for
749 *
750 * After disabling a pipe, we can't wait for vblank in the usual way,
751 * spinning on the vblank interrupt status bit, since we won't actually
752 * see an interrupt when the pipe is disabled.
753 *
ab7ad7f6
KP		 754 * On Gen4 and above:
755 * wait for the pipe register state bit to turn off
756 *
757 * Otherwise:
758 * wait for the display line value to settle (it usually
759 * ends up stopping at the start of the next frame).
58e10eb9 760 *
9d0498a2 761 */
58e10eb9 762void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 763{
764 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 765
766 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 767 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 768
769 /* Wait for the Pipe State to go off */
58e10eb9
CW		 770 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
771 100))
ab7ad7f6
KP		 772 DRM_DEBUG_KMS("pipe_off wait timed out\n");
773 } else {
774 u32 last_line;
58e10eb9 775 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 776 unsigned long timeout = jiffies + msecs_to_jiffies(100);
777
778 /* Wait for the display line to settle */
779 do {
58e10eb9 780 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 781 mdelay(5);
58e10eb9 782 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 783 time_after(timeout, jiffies));
784 if (time_after(jiffies, timeout))
785 DRM_DEBUG_KMS("pipe_off wait timed out\n");
786 }
79e53945
JB		 787}
788
b24e7179
JB		 789static const char *state_string(bool enabled)
790{
791 return enabled ? "on" : "off";
792}
793
794/* Only for pre-ILK configs */
795static void assert_pll(struct drm_i915_private *dev_priv,
796 enum pipe pipe, bool state)
797{
798 int reg;
799 u32 val;
800 bool cur_state;
801
802 reg = DPLL(pipe);
803 val = I915_READ(reg);
804 cur_state = !!(val & DPLL_VCO_ENABLE);
805 WARN(cur_state != state,
806 "PLL state assertion failure (expected %s, current %s)\n",
807 state_string(state), state_string(cur_state));
808}
809#define assert_pll_enabled(d, p) assert_pll(d, p, true)
810#define assert_pll_disabled(d, p) assert_pll(d, p, false)
811
040484af
JB		 812/* For ILK+ */
813static void assert_pch_pll(struct drm_i915_private *dev_priv,
814 enum pipe pipe, bool state)
815{
816 int reg;
817 u32 val;
818 bool cur_state;
819
d3ccbe86
JB		 820 if (HAS_PCH_CPT(dev_priv->dev)) {
821 u32 pch_dpll;
822
823 pch_dpll = I915_READ(PCH_DPLL_SEL);
824
825 /* Make sure the selected PLL is enabled to the transcoder */
826 WARN(!((pch_dpll >> (4 * pipe)) & 8),
827 "transcoder %d PLL not enabled\n", pipe);
828
829 /* Convert the transcoder pipe number to a pll pipe number */
830 pipe = (pch_dpll >> (4 * pipe)) & 1;
831 }
832
040484af
JB		 833 reg = PCH_DPLL(pipe);
834 val = I915_READ(reg);
835 cur_state = !!(val & DPLL_VCO_ENABLE);
836 WARN(cur_state != state,
837 "PCH PLL state assertion failure (expected %s, current %s)\n",
838 state_string(state), state_string(cur_state));
839}
840#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
841#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
842
843static void assert_fdi_tx(struct drm_i915_private *dev_priv,
844 enum pipe pipe, bool state)
845{
846 int reg;
847 u32 val;
848 bool cur_state;
849
850 reg = FDI_TX_CTL(pipe);
851 val = I915_READ(reg);
852 cur_state = !!(val & FDI_TX_ENABLE);
853 WARN(cur_state != state,
854 "FDI TX state assertion failure (expected %s, current %s)\n",
855 state_string(state), state_string(cur_state));
856}
857#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
858#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
859
860static void assert_fdi_rx(struct drm_i915_private *dev_priv,
861 enum pipe pipe, bool state)
862{
863 int reg;
864 u32 val;
865 bool cur_state;
866
867 reg = FDI_RX_CTL(pipe);
868 val = I915_READ(reg);
869 cur_state = !!(val & FDI_RX_ENABLE);
870 WARN(cur_state != state,
871 "FDI RX state assertion failure (expected %s, current %s)\n",
872 state_string(state), state_string(cur_state));
873}
874#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
875#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
876
877static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
878 enum pipe pipe)
879{
880 int reg;
881 u32 val;
882
883 /* ILK FDI PLL is always enabled */
884 if (dev_priv->info->gen == 5)
885 return;
886
887 reg = FDI_TX_CTL(pipe);
888 val = I915_READ(reg);
889 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
890}
891
892static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
893 enum pipe pipe)
894{
895 int reg;
896 u32 val;
897
898 reg = FDI_RX_CTL(pipe);
899 val = I915_READ(reg);
900 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
901}
902
ea0760cf
JB		 903static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
904 enum pipe pipe)
905{
906 int pp_reg, lvds_reg;
907 u32 val;
908 enum pipe panel_pipe = PIPE_A;
0de3b485 909 bool locked = true;
ea0760cf
JB		 910
911 if (HAS_PCH_SPLIT(dev_priv->dev)) {
912 pp_reg = PCH_PP_CONTROL;
913 lvds_reg = PCH_LVDS;
914 } else {
915 pp_reg = PP_CONTROL;
916 lvds_reg = LVDS;
917 }
918
919 val = I915_READ(pp_reg);
920 if (!(val & PANEL_POWER_ON) ||
921 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
922 locked = false;
923
924 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
925 panel_pipe = PIPE_B;
926
927 WARN(panel_pipe == pipe && locked,
928 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 929 pipe_name(pipe));
ea0760cf
JB		 930}
931
b840d907
JB		 932void assert_pipe(struct drm_i915_private *dev_priv,
933 enum pipe pipe, bool state)
b24e7179
JB		 934{
935 int reg;
936 u32 val;
63d7bbe9 937 bool cur_state;
b24e7179 938
8e636784
DV		 939 /* if we need the pipe A quirk it must be always on */
940 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
941 state = true;
942
b24e7179
JB		 943 reg = PIPECONF(pipe);
944 val = I915_READ(reg);
63d7bbe9
JB		 945 cur_state = !!(val & PIPECONF_ENABLE);
946 WARN(cur_state != state,
947 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 948 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 949}
950
931872fc
CW		 951static void assert_plane(struct drm_i915_private *dev_priv,
952 enum plane plane, bool state)
b24e7179
JB		 953{
954 int reg;
955 u32 val;
931872fc 956 bool cur_state;
b24e7179
JB		 957
958 reg = DSPCNTR(plane);
959 val = I915_READ(reg);
931872fc
CW		 960 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
961 WARN(cur_state != state,
962 "plane %c assertion failure (expected %s, current %s)\n",
963 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 964}
965
931872fc
CW		 966#define assert_plane_enabled(d, p) assert_plane(d, p, true)
967#define assert_plane_disabled(d, p) assert_plane(d, p, false)
968
b24e7179
JB		 969static void assert_planes_disabled(struct drm_i915_private *dev_priv,
970 enum pipe pipe)
971{
972 int reg, i;
973 u32 val;
974 int cur_pipe;
975
19ec1358 976 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 977 if (HAS_PCH_SPLIT(dev_priv->dev)) {
978 reg = DSPCNTR(pipe);
979 val = I915_READ(reg);
980 WARN((val & DISPLAY_PLANE_ENABLE),
981 "plane %c assertion failure, should be disabled but not\n",
982 plane_name(pipe));
19ec1358 983 return;
28c05794 984 }
19ec1358 985
b24e7179
JB		 986 /* Need to check both planes against the pipe */
987 for (i = 0; i < 2; i++) {
988 reg = DSPCNTR(i);
989 val = I915_READ(reg);
990 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
991 DISPPLANE_SEL_PIPE_SHIFT;
992 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 993 "plane %c assertion failure, should be off on pipe %c but is still active\n",
994 plane_name(i), pipe_name(pipe));
b24e7179
JB		 995 }
996}
997
92f2584a
JB		 998static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
999{
1000 u32 val;
1001 bool enabled;
1002
1003 val = I915_READ(PCH_DREF_CONTROL);
1004 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1005 DREF_SUPERSPREAD_SOURCE_MASK));
1006 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1007}
1008
1009static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1010 enum pipe pipe)
1011{
1012 int reg;
1013 u32 val;
1014 bool enabled;
1015
1016 reg = TRANSCONF(pipe);
1017 val = I915_READ(reg);
1018 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1019 WARN(enabled,
1020 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1021 pipe_name(pipe));
92f2584a
JB		 1022}
1023
4e634389
KP		 1024static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1025 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1026{
1027 if ((val & DP_PORT_EN) == 0)
1028 return false;
1029
1030 if (HAS_PCH_CPT(dev_priv->dev)) {
1031 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1032 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1033 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1034 return false;
1035 } else {
1036 if ((val & DP_PIPE_MASK) != (pipe << 30))
1037 return false;
1038 }
1039 return true;
1040}
1041
1519b995
KP		 1042static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1043 enum pipe pipe, u32 val)
1044{
1045 if ((val & PORT_ENABLE) == 0)
1046 return false;
1047
1048 if (HAS_PCH_CPT(dev_priv->dev)) {
1049 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1050 return false;
1051 } else {
1052 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1053 return false;
1054 }
1055 return true;
1056}
1057
1058static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, u32 val)
1060{
1061 if ((val & LVDS_PORT_EN) == 0)
1062 return false;
1063
1064 if (HAS_PCH_CPT(dev_priv->dev)) {
1065 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1066 return false;
1067 } else {
1068 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1069 return false;
1070 }
1071 return true;
1072}
1073
1074static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1075 enum pipe pipe, u32 val)
1076{
1077 if ((val & ADPA_DAC_ENABLE) == 0)
1078 return false;
1079 if (HAS_PCH_CPT(dev_priv->dev)) {
1080 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1081 return false;
1082 } else {
1083 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1084 return false;
1085 }
1086 return true;
1087}
1088
291906f1 1089static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1090 enum pipe pipe, int reg, u32 port_sel)
291906f1 1091{
47a05eca 1092 u32 val = I915_READ(reg);
4e634389 1093 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1094 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1095 reg, pipe_name(pipe));
291906f1
JB		 1096}
1097
1098static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1099 enum pipe pipe, int reg)
1100{
47a05eca 1101 u32 val = I915_READ(reg);
1519b995 1102 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
23c99e77 1103 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1104 reg, pipe_name(pipe));
291906f1
JB		 1105}
1106
1107static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1108 enum pipe pipe)
1109{
1110 int reg;
1111 u32 val;
291906f1 1112
f0575e92
KP		 1113 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1114 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1115 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1116
1117 reg = PCH_ADPA;
1118 val = I915_READ(reg);
1519b995 1119 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1120 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1121 pipe_name(pipe));
291906f1
JB		 1122
1123 reg = PCH_LVDS;
1124 val = I915_READ(reg);
1519b995 1125 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1126 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1127 pipe_name(pipe));
291906f1
JB		 1128
1129 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1130 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1131 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1132}
1133
63d7bbe9
JB		 1134/**
1135 * intel_enable_pll - enable a PLL
1136 * @dev_priv: i915 private structure
1137 * @pipe: pipe PLL to enable
1138 *
1139 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1140 * make sure the PLL reg is writable first though, since the panel write
1141 * protect mechanism may be enabled.
1142 *
1143 * Note! This is for pre-ILK only.
1144 */
1145static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1146{
1147 int reg;
1148 u32 val;
1149
1150 /* No really, not for ILK+ */
1151 BUG_ON(dev_priv->info->gen >= 5);
1152
1153 /* PLL is protected by panel, make sure we can write it */
1154 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1155 assert_panel_unlocked(dev_priv, pipe);
1156
1157 reg = DPLL(pipe);
1158 val = I915_READ(reg);
1159 val |= DPLL_VCO_ENABLE;
1160
1161 /* We do this three times for luck */
1162 I915_WRITE(reg, val);
1163 POSTING_READ(reg);
1164 udelay(150); /* wait for warmup */
1165 I915_WRITE(reg, val);
1166 POSTING_READ(reg);
1167 udelay(150); /* wait for warmup */
1168 I915_WRITE(reg, val);
1169 POSTING_READ(reg);
1170 udelay(150); /* wait for warmup */
1171}
1172
1173/**
1174 * intel_disable_pll - disable a PLL
1175 * @dev_priv: i915 private structure
1176 * @pipe: pipe PLL to disable
1177 *
1178 * Disable the PLL for @pipe, making sure the pipe is off first.
1179 *
1180 * Note! This is for pre-ILK only.
1181 */
1182static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1183{
1184 int reg;
1185 u32 val;
1186
1187 /* Don't disable pipe A or pipe A PLLs if needed */
1188 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1189 return;
1190
1191 /* Make sure the pipe isn't still relying on us */
1192 assert_pipe_disabled(dev_priv, pipe);
1193
1194 reg = DPLL(pipe);
1195 val = I915_READ(reg);
1196 val &= ~DPLL_VCO_ENABLE;
1197 I915_WRITE(reg, val);
1198 POSTING_READ(reg);
1199}
1200
92f2584a
JB		 1201/**
1202 * intel_enable_pch_pll - enable PCH PLL
1203 * @dev_priv: i915 private structure
1204 * @pipe: pipe PLL to enable
1205 *
1206 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1207 * drives the transcoder clock.
1208 */
1209static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1210 enum pipe pipe)
1211{
1212 int reg;
1213 u32 val;
1214
4c609cb8
JB		 1215 if (pipe > 1)
1216 return;
1217
92f2584a
JB		 1218 /* PCH only available on ILK+ */
1219 BUG_ON(dev_priv->info->gen < 5);
1220
1221 /* PCH refclock must be enabled first */
1222 assert_pch_refclk_enabled(dev_priv);
1223
1224 reg = PCH_DPLL(pipe);
1225 val = I915_READ(reg);
1226 val |= DPLL_VCO_ENABLE;
1227 I915_WRITE(reg, val);
1228 POSTING_READ(reg);
1229 udelay(200);
1230}
1231
1232static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1233 enum pipe pipe)
1234{
1235 int reg;
7a419866
JB		 1236 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1237 pll_sel = TRANSC_DPLL_ENABLE;
92f2584a 1238
4c609cb8
JB		 1239 if (pipe > 1)
1240 return;
1241
92f2584a
JB		 1242 /* PCH only available on ILK+ */
1243 BUG_ON(dev_priv->info->gen < 5);
1244
1245 /* Make sure transcoder isn't still depending on us */
1246 assert_transcoder_disabled(dev_priv, pipe);
1247
7a419866
JB		 1248 if (pipe == 0)
1249 pll_sel |= TRANSC_DPLLA_SEL;
1250 else if (pipe == 1)
1251 pll_sel |= TRANSC_DPLLB_SEL;
1252
1253
1254 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1255 return;
1256
92f2584a
JB		 1257 reg = PCH_DPLL(pipe);
1258 val = I915_READ(reg);
1259 val &= ~DPLL_VCO_ENABLE;
1260 I915_WRITE(reg, val);
1261 POSTING_READ(reg);
1262 udelay(200);
1263}
1264
040484af
JB		 1265static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1266 enum pipe pipe)
1267{
1268 int reg;
5f7f726d 1269 u32 val, pipeconf_val;
040484af
JB		 1270
1271 /* PCH only available on ILK+ */
1272 BUG_ON(dev_priv->info->gen < 5);
1273
1274 /* Make sure PCH DPLL is enabled */
1275 assert_pch_pll_enabled(dev_priv, pipe);
1276
1277 /* FDI must be feeding us bits for PCH ports */
1278 assert_fdi_tx_enabled(dev_priv, pipe);
1279 assert_fdi_rx_enabled(dev_priv, pipe);
1280
1281 reg = TRANSCONF(pipe);
1282 val = I915_READ(reg);
5f7f726d 1283 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1284
1285 if (HAS_PCH_IBX(dev_priv->dev)) {
1286 /*
1287 * make the BPC in transcoder be consistent with
1288 * that in pipeconf reg.
1289 */
1290 val &= ~PIPE_BPC_MASK;
5f7f726d 1291 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1292 }
5f7f726d
PZ		 1293
1294 val &= ~TRANS_INTERLACE_MASK;
1295 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1296 val |= TRANS_INTERLACED;
1297 else
1298 val |= TRANS_PROGRESSIVE;
1299
040484af
JB		 1300 I915_WRITE(reg, val | TRANS_ENABLE);
1301 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1302 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1303}
1304
1305static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1306 enum pipe pipe)
1307{
1308 int reg;
1309 u32 val;
1310
1311 /* FDI relies on the transcoder */
1312 assert_fdi_tx_disabled(dev_priv, pipe);
1313 assert_fdi_rx_disabled(dev_priv, pipe);
1314
291906f1
JB		 1315 /* Ports must be off as well */
1316 assert_pch_ports_disabled(dev_priv, pipe);
1317
040484af
JB		 1318 reg = TRANSCONF(pipe);
1319 val = I915_READ(reg);
1320 val &= ~TRANS_ENABLE;
1321 I915_WRITE(reg, val);
1322 /* wait for PCH transcoder off, transcoder state */
1323 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1324 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1325}
1326
b24e7179 1327/**
309cfea8 1328 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1329 * @dev_priv: i915 private structure
1330 * @pipe: pipe to enable
040484af 1331 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1332 *
1333 * Enable @pipe, making sure that various hardware specific requirements
1334 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1335 *
1336 * @pipe should be %PIPE_A or %PIPE_B.
1337 *
1338 * Will wait until the pipe is actually running (i.e. first vblank) before
1339 * returning.
1340 */
040484af
JB		 1341static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1342 bool pch_port)
b24e7179
JB		 1343{
1344 int reg;
1345 u32 val;
1346
1347 /*
1348 * A pipe without a PLL won't actually be able to drive bits from
1349 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1350 * need the check.
1351 */
1352 if (!HAS_PCH_SPLIT(dev_priv->dev))
1353 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1354 else {
1355 if (pch_port) {
1356 /* if driving the PCH, we need FDI enabled */
1357 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1358 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1359 }
1360 /* FIXME: assert CPU port conditions for SNB+ */
1361 }
b24e7179
JB		 1362
1363 reg = PIPECONF(pipe);
1364 val = I915_READ(reg);
00d70b15
CW		 1365 if (val & PIPECONF_ENABLE)
1366 return;
1367
1368 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1369 intel_wait_for_vblank(dev_priv->dev, pipe);
1370}
1371
1372/**
309cfea8 1373 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1374 * @dev_priv: i915 private structure
1375 * @pipe: pipe to disable
1376 *
1377 * Disable @pipe, making sure that various hardware specific requirements
1378 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1379 *
1380 * @pipe should be %PIPE_A or %PIPE_B.
1381 *
1382 * Will wait until the pipe has shut down before returning.
1383 */
1384static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1385 enum pipe pipe)
1386{
1387 int reg;
1388 u32 val;
1389
1390 /*
1391 * Make sure planes won't keep trying to pump pixels to us,
1392 * or we might hang the display.
1393 */
1394 assert_planes_disabled(dev_priv, pipe);
1395
1396 /* Don't disable pipe A or pipe A PLLs if needed */
1397 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1398 return;
1399
1400 reg = PIPECONF(pipe);
1401 val = I915_READ(reg);
00d70b15
CW		 1402 if ((val & PIPECONF_ENABLE) == 0)
1403 return;
1404
1405 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1406 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1407}
1408
d74362c9
KP		 1409/*
1410 * Plane regs are double buffered, going from enabled->disabled needs a
1411 * trigger in order to latch. The display address reg provides this.
1412 */
1413static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1414 enum plane plane)
1415{
1416 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1417 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1418}
1419
b24e7179
JB		 1420/**
1421 * intel_enable_plane - enable a display plane on a given pipe
1422 * @dev_priv: i915 private structure
1423 * @plane: plane to enable
1424 * @pipe: pipe being fed
1425 *
1426 * Enable @plane on @pipe, making sure that @pipe is running first.
1427 */
1428static void intel_enable_plane(struct drm_i915_private *dev_priv,
1429 enum plane plane, enum pipe pipe)
1430{
1431 int reg;
1432 u32 val;
1433
1434 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1435 assert_pipe_enabled(dev_priv, pipe);
1436
1437 reg = DSPCNTR(plane);
1438 val = I915_READ(reg);
00d70b15
CW		 1439 if (val & DISPLAY_PLANE_ENABLE)
1440 return;
1441
1442 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1443 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1444 intel_wait_for_vblank(dev_priv->dev, pipe);
1445}
1446
b24e7179
JB		 1447/**
1448 * intel_disable_plane - disable a display plane
1449 * @dev_priv: i915 private structure
1450 * @plane: plane to disable
1451 * @pipe: pipe consuming the data
1452 *
1453 * Disable @plane; should be an independent operation.
1454 */
1455static void intel_disable_plane(struct drm_i915_private *dev_priv,
1456 enum plane plane, enum pipe pipe)
1457{
1458 int reg;
1459 u32 val;
1460
1461 reg = DSPCNTR(plane);
1462 val = I915_READ(reg);
00d70b15
CW		 1463 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1464 return;
1465
1466 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1467 intel_flush_display_plane(dev_priv, plane);
1468 intel_wait_for_vblank(dev_priv->dev, pipe);
1469}
1470
47a05eca 1471static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1472 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1473{
1474 u32 val = I915_READ(reg);
4e634389 1475 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1476 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1477 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1478 }
47a05eca
JB		 1479}
1480
1481static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1482 enum pipe pipe, int reg)
1483{
1484 u32 val = I915_READ(reg);
1519b995 1485 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1486 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1487 reg, pipe);
47a05eca 1488 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1489 }
47a05eca
JB		 1490}
1491
1492/* Disable any ports connected to this transcoder */
1493static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1494 enum pipe pipe)
1495{
1496 u32 reg, val;
1497
1498 val = I915_READ(PCH_PP_CONTROL);
1499 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1500
f0575e92
KP		 1501 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1502 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1503 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1504
1505 reg = PCH_ADPA;
1506 val = I915_READ(reg);
1519b995 1507 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1508 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1509
1510 reg = PCH_LVDS;
1511 val = I915_READ(reg);
1519b995
KP		 1512 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1513 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1514 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1515 POSTING_READ(reg);
1516 udelay(100);
1517 }
1518
1519 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1520 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1521 disable_pch_hdmi(dev_priv, pipe, HDMID);
1522}
1523
43a9539f
CW		 1524static void i8xx_disable_fbc(struct drm_device *dev)
1525{
1526 struct drm_i915_private *dev_priv = dev->dev_private;
1527 u32 fbc_ctl;
1528
1529 /* Disable compression */
1530 fbc_ctl = I915_READ(FBC_CONTROL);
1531 if ((fbc_ctl & FBC_CTL_EN) == 0)
1532 return;
1533
1534 fbc_ctl &= ~FBC_CTL_EN;
1535 I915_WRITE(FBC_CONTROL, fbc_ctl);
1536
1537 /* Wait for compressing bit to clear */
1538 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1539 DRM_DEBUG_KMS("FBC idle timed out\n");
1540 return;
1541 }
1542
1543 DRM_DEBUG_KMS("disabled FBC\n");
1544}
1545
80824003
JB		 1546static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1547{
1548 struct drm_device *dev = crtc->dev;
1549 struct drm_i915_private *dev_priv = dev->dev_private;
1550 struct drm_framebuffer *fb = crtc->fb;
1551 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1552 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003 1553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
016b9b61 1554 int cfb_pitch;
80824003
JB		 1555 int plane, i;
1556 u32 fbc_ctl, fbc_ctl2;
1557
016b9b61 1558 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
01f2c773
VS		 1559 if (fb->pitches[0] < cfb_pitch)
1560 cfb_pitch = fb->pitches[0];
80824003
JB		 1561
1562 /* FBC_CTL wants 64B units */
016b9b61
CW		 1563 cfb_pitch = (cfb_pitch / 64) - 1;
1564 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
80824003
JB		 1565
1566 /* Clear old tags */
1567 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1568 I915_WRITE(FBC_TAG + (i * 4), 0);
1569
1570 /* Set it up... */
de568510
CW		 1571 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1572 fbc_ctl2 |= plane;
80824003
JB		 1573 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1574 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1575
1576 /* enable it... */
1577 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1578 if (IS_I945GM(dev))
49677901 1579 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
016b9b61 1580 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
80824003 1581 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
016b9b61 1582 fbc_ctl |= obj->fence_reg;
80824003
JB		 1583 I915_WRITE(FBC_CONTROL, fbc_ctl);
1584
016b9b61
CW		 1585 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1586 cfb_pitch, crtc->y, intel_crtc->plane);
80824003
JB		 1587}
1588
ee5382ae 1589static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1590{
80824003
JB		 1591 struct drm_i915_private *dev_priv = dev->dev_private;
1592
1593 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1594}
1595
74dff282
JB		 1596static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1597{
1598 struct drm_device *dev = crtc->dev;
1599 struct drm_i915_private *dev_priv = dev->dev_private;
1600 struct drm_framebuffer *fb = crtc->fb;
1601 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1602 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1604 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB		 1605 unsigned long stall_watermark = 200;
1606 u32 dpfc_ctl;
1607
74dff282 1608 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
016b9b61 1609 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
de568510 1610 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
74dff282 1611
74dff282
JB		 1612 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1613 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1614 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1615 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1616
1617 /* enable it... */
1618 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1619
28c97730 1620 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB		 1621}
1622
43a9539f 1623static void g4x_disable_fbc(struct drm_device *dev)
74dff282
JB		 1624{
1625 struct drm_i915_private *dev_priv = dev->dev_private;
1626 u32 dpfc_ctl;
1627
1628 /* Disable compression */
1629 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW		 1630 if (dpfc_ctl & DPFC_CTL_EN) {
1631 dpfc_ctl &= ~DPFC_CTL_EN;
1632 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1633
bed4a673
CW		 1634 DRM_DEBUG_KMS("disabled FBC\n");
1635 }
74dff282
JB		 1636}
1637
ee5382ae 1638static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1639{
74dff282
JB		 1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641
1642 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1643}
1644
4efe0708
JB		 1645static void sandybridge_blit_fbc_update(struct drm_device *dev)
1646{
1647 struct drm_i915_private *dev_priv = dev->dev_private;
1648 u32 blt_ecoskpd;
1649
1650 /* Make sure blitter notifies FBC of writes */
fcca7926 1651 gen6_gt_force_wake_get(dev_priv);
4efe0708
JB		 1652 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1653 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1654 GEN6_BLITTER_LOCK_SHIFT;
1655 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1656 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1657 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1658 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1659 GEN6_BLITTER_LOCK_SHIFT);
1660 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1661 POSTING_READ(GEN6_BLITTER_ECOSKPD);
fcca7926 1662 gen6_gt_force_wake_put(dev_priv);
4efe0708
JB		 1663}
1664
b52eb4dc
ZY		 1665static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1666{
1667 struct drm_device *dev = crtc->dev;
1668 struct drm_i915_private *dev_priv = dev->dev_private;
1669 struct drm_framebuffer *fb = crtc->fb;
1670 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1671 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1673 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY		 1674 unsigned long stall_watermark = 200;
1675 u32 dpfc_ctl;
1676
bed4a673 1677 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
b52eb4dc
ZY		 1678 dpfc_ctl &= DPFC_RESERVED;
1679 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
9ce9d069
CW		 1680 /* Set persistent mode for front-buffer rendering, ala X. */
1681 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
016b9b61 1682 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
de568510 1683 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
b52eb4dc 1684
b52eb4dc
ZY		 1685 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1686 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1687 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1688 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1689 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1690 /* enable it... */
bed4a673 1691 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc 1692
9c04f015
YL		 1693 if (IS_GEN6(dev)) {
1694 I915_WRITE(SNB_DPFC_CTL_SA,
016b9b61 1695 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
9c04f015 1696 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
4efe0708 1697 sandybridge_blit_fbc_update(dev);
9c04f015
YL		 1698 }
1699
b52eb4dc
ZY		 1700 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1701}
1702
43a9539f 1703static void ironlake_disable_fbc(struct drm_device *dev)
b52eb4dc
ZY		 1704{
1705 struct drm_i915_private *dev_priv = dev->dev_private;
1706 u32 dpfc_ctl;
1707
1708 /* Disable compression */
1709 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW		 1710 if (dpfc_ctl & DPFC_CTL_EN) {
1711 dpfc_ctl &= ~DPFC_CTL_EN;
1712 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1713
bed4a673
CW		 1714 DRM_DEBUG_KMS("disabled FBC\n");
1715 }
b52eb4dc
ZY		 1716}
1717
1718static bool ironlake_fbc_enabled(struct drm_device *dev)
1719{
1720 struct drm_i915_private *dev_priv = dev->dev_private;
1721
1722 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1723}
1724
ee5382ae
AJ		 1725bool intel_fbc_enabled(struct drm_device *dev)
1726{
1727 struct drm_i915_private *dev_priv = dev->dev_private;
1728
1729 if (!dev_priv->display.fbc_enabled)
1730 return false;
1731
1732 return dev_priv->display.fbc_enabled(dev);
1733}
1734
1630fe75
CW		 1735static void intel_fbc_work_fn(struct work_struct *__work)
1736{
1737 struct intel_fbc_work *work =
1738 container_of(to_delayed_work(__work),
1739 struct intel_fbc_work, work);
1740 struct drm_device *dev = work->crtc->dev;
1741 struct drm_i915_private *dev_priv = dev->dev_private;
1742
1743 mutex_lock(&dev->struct_mutex);
1744 if (work == dev_priv->fbc_work) {
1745 /* Double check that we haven't switched fb without cancelling
1746 * the prior work.
1747 */
016b9b61 1748 if (work->crtc->fb == work->fb) {
1630fe75
CW		 1749 dev_priv->display.enable_fbc(work->crtc,
1750 work->interval);
1751
016b9b61
CW		 1752 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1753 dev_priv->cfb_fb = work->crtc->fb->base.id;
1754 dev_priv->cfb_y = work->crtc->y;
1755 }
1756
1630fe75
CW		 1757 dev_priv->fbc_work = NULL;
1758 }
1759 mutex_unlock(&dev->struct_mutex);
1760
1761 kfree(work);
1762}
1763
1764static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1765{
1766 if (dev_priv->fbc_work == NULL)
1767 return;
1768
1769 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1770
1771 /* Synchronisation is provided by struct_mutex and checking of
1772 * dev_priv->fbc_work, so we can perform the cancellation
1773 * entirely asynchronously.
1774 */
1775 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1776 /* tasklet was killed before being run, clean up */
1777 kfree(dev_priv->fbc_work);
1778
1779 /* Mark the work as no longer wanted so that if it does
1780 * wake-up (because the work was already running and waiting
1781 * for our mutex), it will discover that is no longer
1782 * necessary to run.
1783 */
1784 dev_priv->fbc_work = NULL;
1785}
1786
43a9539f 1787static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
ee5382ae 1788{
1630fe75
CW		 1789 struct intel_fbc_work *work;
1790 struct drm_device *dev = crtc->dev;
1791 struct drm_i915_private *dev_priv = dev->dev_private;
ee5382ae
AJ		 1792
1793 if (!dev_priv->display.enable_fbc)
1794 return;
1795
1630fe75
CW		 1796 intel_cancel_fbc_work(dev_priv);
1797
1798 work = kzalloc(sizeof *work, GFP_KERNEL);
1799 if (work == NULL) {
1800 dev_priv->display.enable_fbc(crtc, interval);
1801 return;
1802 }
1803
1804 work->crtc = crtc;
1805 work->fb = crtc->fb;
1806 work->interval = interval;
1807 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1808
1809 dev_priv->fbc_work = work;
1810
1811 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1812
1813 /* Delay the actual enabling to let pageflipping cease and the
016b9b61
CW		 1814 * display to settle before starting the compression. Note that
1815 * this delay also serves a second purpose: it allows for a
1816 * vblank to pass after disabling the FBC before we attempt
1817 * to modify the control registers.
1630fe75
CW		 1818 *
1819 * A more complicated solution would involve tracking vblanks
1820 * following the termination of the page-flipping sequence
1821 * and indeed performing the enable as a co-routine and not
1822 * waiting synchronously upon the vblank.
1823 */
1824 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
ee5382ae
AJ		 1825}
1826
1827void intel_disable_fbc(struct drm_device *dev)
1828{
1829 struct drm_i915_private *dev_priv = dev->dev_private;
1830
1630fe75
CW		 1831 intel_cancel_fbc_work(dev_priv);
1832
ee5382ae
AJ		 1833 if (!dev_priv->display.disable_fbc)
1834 return;
1835
1836 dev_priv->display.disable_fbc(dev);
016b9b61 1837 dev_priv->cfb_plane = -1;
ee5382ae
AJ		 1838}
1839
80824003
JB		 1840/**
1841 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1842 * @dev: the drm_device
80824003
JB		 1843 *
1844 * Set up the framebuffer compression hardware at mode set time. We
1845 * enable it if possible:
1846 * - plane A only (on pre-965)
1847 * - no pixel mulitply/line duplication
1848 * - no alpha buffer discard
1849 * - no dual wide
1850 * - framebuffer <= 2048 in width, 1536 in height
1851 *
1852 * We can't assume that any compression will take place (worst case),
1853 * so the compressed buffer has to be the same size as the uncompressed
1854 * one. It also must reside (along with the line length buffer) in
1855 * stolen memory.
1856 *
1857 * We need to enable/disable FBC on a global basis.
1858 */
bed4a673 1859static void intel_update_fbc(struct drm_device *dev)
80824003 1860{
80824003 1861 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW		 1862 struct drm_crtc *crtc = NULL, *tmp_crtc;
1863 struct intel_crtc *intel_crtc;
1864 struct drm_framebuffer *fb;
80824003 1865 struct intel_framebuffer *intel_fb;
05394f39 1866 struct drm_i915_gem_object *obj;
cd0de039 1867 int enable_fbc;
9c928d16
JB		 1868
1869 DRM_DEBUG_KMS("\n");
80824003
JB		 1870
1871 if (!i915_powersave)
1872 return;
1873
ee5382ae 1874 if (!I915_HAS_FBC(dev))
e70236a8
JB		 1875 return;
1876
80824003
JB		 1877 /*
1878 * If FBC is already on, we just have to verify that we can
1879 * keep it that way...
1880 * Need to disable if:
9c928d16 1881 * - more than one pipe is active
80824003
JB		 1882 * - changing FBC params (stride, fence, mode)
1883 * - new fb is too large to fit in compressed buffer
1884 * - going to an unsupported config (interlace, pixel multiply, etc.)
1885 */
9c928d16 1886 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
d210246a 1887 if (tmp_crtc->enabled && tmp_crtc->fb) {
bed4a673
CW		 1888 if (crtc) {
1889 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1890 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1891 goto out_disable;
1892 }
1893 crtc = tmp_crtc;
1894 }
9c928d16 1895 }
bed4a673
CW		 1896
1897 if (!crtc || crtc->fb == NULL) {
1898 DRM_DEBUG_KMS("no output, disabling\n");
1899 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB		 1900 goto out_disable;
1901 }
bed4a673
CW		 1902
1903 intel_crtc = to_intel_crtc(crtc);
1904 fb = crtc->fb;
1905 intel_fb = to_intel_framebuffer(fb);
05394f39 1906 obj = intel_fb->obj;
bed4a673 1907
cd0de039
KP		 1908 enable_fbc = i915_enable_fbc;
1909 if (enable_fbc < 0) {
1910 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1911 enable_fbc = 1;
d56d8b28 1912 if (INTEL_INFO(dev)->gen <= 6)
cd0de039
KP		 1913 enable_fbc = 0;
1914 }
1915 if (!enable_fbc) {
1916 DRM_DEBUG_KMS("fbc disabled per module param\n");
c1a9f047
JB		 1917 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1918 goto out_disable;
1919 }
05394f39 1920 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 1921 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 1922 "compression\n");
b5e50c3f 1923 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1924 goto out_disable;
1925 }
bed4a673
CW		 1926 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1927 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 1928 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 1929 "disabling\n");
b5e50c3f 1930 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB		 1931 goto out_disable;
1932 }
bed4a673
CW		 1933 if ((crtc->mode.hdisplay > 2048) ||
1934 (crtc->mode.vdisplay > 1536)) {
28c97730 1935 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 1936 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB		 1937 goto out_disable;
1938 }
bed4a673 1939 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 1940 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 1941 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB		 1942 goto out_disable;
1943 }
de568510
CW		 1944
1945 /* The use of a CPU fence is mandatory in order to detect writes
1946 * by the CPU to the scanout and trigger updates to the FBC.
1947 */
1948 if (obj->tiling_mode != I915_TILING_X ||
1949 obj->fence_reg == I915_FENCE_REG_NONE) {
1950 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
b5e50c3f 1951 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB		 1952 goto out_disable;
1953 }
1954
c924b934
JW		 1955 /* If the kernel debugger is active, always disable compression */
1956 if (in_dbg_master())
1957 goto out_disable;
1958
016b9b61
CW		 1959 /* If the scanout has not changed, don't modify the FBC settings.
1960 * Note that we make the fundamental assumption that the fb->obj
1961 * cannot be unpinned (and have its GTT offset and fence revoked)
1962 * without first being decoupled from the scanout and FBC disabled.
1963 */
1964 if (dev_priv->cfb_plane == intel_crtc->plane &&
1965 dev_priv->cfb_fb == fb->base.id &&
1966 dev_priv->cfb_y == crtc->y)
1967 return;
1968
1969 if (intel_fbc_enabled(dev)) {
1970 /* We update FBC along two paths, after changing fb/crtc
1971 * configuration (modeswitching) and after page-flipping
1972 * finishes. For the latter, we know that not only did
1973 * we disable the FBC at the start of the page-flip
1974 * sequence, but also more than one vblank has passed.
1975 *
1976 * For the former case of modeswitching, it is possible
1977 * to switch between two FBC valid configurations
1978 * instantaneously so we do need to disable the FBC
1979 * before we can modify its control registers. We also
1980 * have to wait for the next vblank for that to take
1981 * effect. However, since we delay enabling FBC we can
1982 * assume that a vblank has passed since disabling and
1983 * that we can safely alter the registers in the deferred
1984 * callback.
1985 *
1986 * In the scenario that we go from a valid to invalid
1987 * and then back to valid FBC configuration we have
1988 * no strict enforcement that a vblank occurred since
1989 * disabling the FBC. However, along all current pipe
1990 * disabling paths we do need to wait for a vblank at
1991 * some point. And we wait before enabling FBC anyway.
1992 */
1993 DRM_DEBUG_KMS("disabling active FBC for update\n");
1994 intel_disable_fbc(dev);
1995 }
1996
bed4a673 1997 intel_enable_fbc(crtc, 500);
80824003
JB		 1998 return;
1999
2000out_disable:
80824003 2001 /* Multiple disables should be harmless */
a939406f
CW		 2002 if (intel_fbc_enabled(dev)) {
2003 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 2004 intel_disable_fbc(dev);
a939406f 2005 }
80824003
JB		 2006}
2007
127bd2ac 2008int
48b956c5 2009intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 2010 struct drm_i915_gem_object *obj,
919926ae 2011 struct intel_ring_buffer *pipelined)
6b95a207 2012{
ce453d81 2013 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 2014 u32 alignment;
2015 int ret;
2016
05394f39 2017 switch (obj->tiling_mode) {
6b95a207 2018 case I915_TILING_NONE:
534843da
CW		 2019 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2020 alignment = 128 * 1024;
a6c45cf0 2021 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2022 alignment = 4 * 1024;
2023 else
2024 alignment = 64 * 1024;
6b95a207
KH		 2025 break;
2026 case I915_TILING_X:
2027 /* pin() will align the object as required by fence */
2028 alignment = 0;
2029 break;
2030 case I915_TILING_Y:
2031 /* FIXME: Is this true? */
2032 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2033 return -EINVAL;
2034 default:
2035 BUG();
2036 }
2037
ce453d81 2038 dev_priv->mm.interruptible = false;
2da3b9b9 2039 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 2040 if (ret)
ce453d81 2041 goto err_interruptible;
6b95a207
KH		 2042
2043 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2044 * fence, whereas 965+ only requires a fence if using
2045 * framebuffer compression. For simplicity, we always install
2046 * a fence as the cost is not that onerous.
2047 */
05394f39 2048 if (obj->tiling_mode != I915_TILING_NONE) {
ce453d81 2049 ret = i915_gem_object_get_fence(obj, pipelined);
48b956c5
CW		 2050 if (ret)
2051 goto err_unpin;
1690e1eb
CW		 2052
2053 i915_gem_object_pin_fence(obj);
6b95a207
KH		 2054 }
2055
ce453d81 2056 dev_priv->mm.interruptible = true;
6b95a207 2057 return 0;
48b956c5
CW		 2058
2059err_unpin:
2060 i915_gem_object_unpin(obj);
ce453d81
CW		 2061err_interruptible:
2062 dev_priv->mm.interruptible = true;
48b956c5 2063 return ret;
6b95a207
KH		 2064}
2065
1690e1eb
CW		 2066void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2067{
2068 i915_gem_object_unpin_fence(obj);
2069 i915_gem_object_unpin(obj);
2070}
2071
17638cd6
JB		 2072static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2073 int x, int y)
81255565
JB		 2074{
2075 struct drm_device *dev = crtc->dev;
2076 struct drm_i915_private *dev_priv = dev->dev_private;
2077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2078 struct intel_framebuffer *intel_fb;
05394f39 2079 struct drm_i915_gem_object *obj;
81255565
JB		 2080 int plane = intel_crtc->plane;
2081 unsigned long Start, Offset;
81255565 2082 u32 dspcntr;
5eddb70b 2083 u32 reg;
81255565
JB		 2084
2085 switch (plane) {
2086 case 0:
2087 case 1:
2088 break;
2089 default:
2090 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2091 return -EINVAL;
2092 }
2093
2094 intel_fb = to_intel_framebuffer(fb);
2095 obj = intel_fb->obj;
81255565 2096
5eddb70b
CW		 2097 reg = DSPCNTR(plane);
2098 dspcntr = I915_READ(reg);
81255565
JB		 2099 /* Mask out pixel format bits in case we change it */
2100 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2101 switch (fb->bits_per_pixel) {
2102 case 8:
2103 dspcntr |= DISPPLANE_8BPP;
2104 break;
2105 case 16:
2106 if (fb->depth == 15)
2107 dspcntr |= DISPPLANE_15_16BPP;
2108 else
2109 dspcntr |= DISPPLANE_16BPP;
2110 break;
2111 case 24:
2112 case 32:
2113 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2114 break;
2115 default:
17638cd6 2116 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2117 return -EINVAL;
2118 }
a6c45cf0 2119 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2120 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2121 dspcntr |= DISPPLANE_TILED;
2122 else
2123 dspcntr &= ~DISPPLANE_TILED;
2124 }
2125
5eddb70b 2126 I915_WRITE(reg, dspcntr);
81255565 2127
05394f39 2128 Start = obj->gtt_offset;
01f2c773 2129 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2130
4e6cfefc 2131 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 2132 Start, Offset, x, y, fb->pitches[0]);
2133 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2134 if (INTEL_INFO(dev)->gen >= 4) {
5eddb70b
CW		 2135 I915_WRITE(DSPSURF(plane), Start);
2136 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2137 I915_WRITE(DSPADDR(plane), Offset);
2138 } else
2139 I915_WRITE(DSPADDR(plane), Start + Offset);
2140 POSTING_READ(reg);
81255565 2141
17638cd6
JB		 2142 return 0;
2143}
2144
2145static int ironlake_update_plane(struct drm_crtc *crtc,
2146 struct drm_framebuffer *fb, int x, int y)
2147{
2148 struct drm_device *dev = crtc->dev;
2149 struct drm_i915_private *dev_priv = dev->dev_private;
2150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2151 struct intel_framebuffer *intel_fb;
2152 struct drm_i915_gem_object *obj;
2153 int plane = intel_crtc->plane;
2154 unsigned long Start, Offset;
2155 u32 dspcntr;
2156 u32 reg;
2157
2158 switch (plane) {
2159 case 0:
2160 case 1:
27f8227b 2161 case 2:
17638cd6
JB		 2162 break;
2163 default:
2164 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2165 return -EINVAL;
2166 }
2167
2168 intel_fb = to_intel_framebuffer(fb);
2169 obj = intel_fb->obj;
2170
2171 reg = DSPCNTR(plane);
2172 dspcntr = I915_READ(reg);
2173 /* Mask out pixel format bits in case we change it */
2174 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2175 switch (fb->bits_per_pixel) {
2176 case 8:
2177 dspcntr |= DISPPLANE_8BPP;
2178 break;
2179 case 16:
2180 if (fb->depth != 16)
2181 return -EINVAL;
2182
2183 dspcntr |= DISPPLANE_16BPP;
2184 break;
2185 case 24:
2186 case 32:
2187 if (fb->depth == 24)
2188 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2189 else if (fb->depth == 30)
2190 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2191 else
2192 return -EINVAL;
2193 break;
2194 default:
2195 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2196 return -EINVAL;
2197 }
2198
2199 if (obj->tiling_mode != I915_TILING_NONE)
2200 dspcntr |= DISPPLANE_TILED;
2201 else
2202 dspcntr &= ~DISPPLANE_TILED;
2203
2204 /* must disable */
2205 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2206
2207 I915_WRITE(reg, dspcntr);
2208
2209 Start = obj->gtt_offset;
01f2c773 2210 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
17638cd6
JB		 2211
2212 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 2213 Start, Offset, x, y, fb->pitches[0]);
2214 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
17638cd6
JB		 2215 I915_WRITE(DSPSURF(plane), Start);
2216 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2217 I915_WRITE(DSPADDR(plane), Offset);
2218 POSTING_READ(reg);
2219
2220 return 0;
2221}
2222
2223/* Assume fb object is pinned & idle & fenced and just update base pointers */
2224static int
2225intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2226 int x, int y, enum mode_set_atomic state)
2227{
2228 struct drm_device *dev = crtc->dev;
2229 struct drm_i915_private *dev_priv = dev->dev_private;
2230 int ret;
2231
2232 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2233 if (ret)
2234 return ret;
2235
bed4a673 2236 intel_update_fbc(dev);
3dec0095 2237 intel_increase_pllclock(crtc);
81255565
JB		 2238
2239 return 0;
2240}
2241
5c3b82e2 2242static int
3c4fdcfb
KH		 2243intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2244 struct drm_framebuffer *old_fb)
79e53945
JB		 2245{
2246 struct drm_device *dev = crtc->dev;
79e53945
JB		 2247 struct drm_i915_master_private *master_priv;
2248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2249 int ret;
79e53945
JB		 2250
2251 /* no fb bound */
2252 if (!crtc->fb) {
a5071c2f 2253 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2254 return 0;
2255 }
2256
265db958 2257 switch (intel_crtc->plane) {
5c3b82e2
CW		 2258 case 0:
2259 case 1:
2260 break;
27f8227b
JB		 2261 case 2:
2262 if (IS_IVYBRIDGE(dev))
2263 break;
2264 /* fall through otherwise */
5c3b82e2 2265 default:
a5071c2f 2266 DRM_ERROR("no plane for crtc\n");
5c3b82e2 2267 return -EINVAL;
79e53945
JB		 2268 }
2269
5c3b82e2 2270 mutex_lock(&dev->struct_mutex);
265db958
CW		 2271 ret = intel_pin_and_fence_fb_obj(dev,
2272 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2273 NULL);
5c3b82e2
CW		 2274 if (ret != 0) {
2275 mutex_unlock(&dev->struct_mutex);
a5071c2f 2276 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2277 return ret;
2278 }
79e53945 2279
265db958 2280 if (old_fb) {
e6c3a2a6 2281 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 2282 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
265db958 2283
e6c3a2a6 2284 wait_event(dev_priv->pending_flip_queue,
01eec727 2285 atomic_read(&dev_priv->mm.wedged) ||
05394f39 2286 atomic_read(&obj->pending_flip) == 0);
85345517
CW		 2287
2288 /* Big Hammer, we also need to ensure that any pending
2289 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2290 * current scanout is retired before unpinning the old
2291 * framebuffer.
01eec727
CW		 2292 *
2293 * This should only fail upon a hung GPU, in which case we
2294 * can safely continue.
85345517 2295 */
a8198eea 2296 ret = i915_gem_object_finish_gpu(obj);
01eec727 2297 (void) ret;
265db958
CW		 2298 }
2299
21c74a8e
JW		 2300 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2301 LEAVE_ATOMIC_MODE_SET);
4e6cfefc 2302 if (ret) {
1690e1eb 2303 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2304 mutex_unlock(&dev->struct_mutex);
a5071c2f 2305 DRM_ERROR("failed to update base address\n");
4e6cfefc 2306 return ret;
79e53945 2307 }
3c4fdcfb 2308
b7f1de28
CW		 2309 if (old_fb) {
2310 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2311 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2312 }
652c393a 2313
5c3b82e2 2314 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2315
2316 if (!dev->primary->master)
5c3b82e2 2317 return 0;
79e53945
JB		 2318
2319 master_priv = dev->primary->master->driver_priv;
2320 if (!master_priv->sarea_priv)
5c3b82e2 2321 return 0;
79e53945 2322
265db958 2323 if (intel_crtc->pipe) {
79e53945
JB		 2324 master_priv->sarea_priv->pipeB_x = x;
2325 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2326 } else {
2327 master_priv->sarea_priv->pipeA_x = x;
2328 master_priv->sarea_priv->pipeA_y = y;
79e53945 2329 }
5c3b82e2
CW		 2330
2331 return 0;
79e53945
JB		 2332}
2333
5eddb70b 2334static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2335{
2336 struct drm_device *dev = crtc->dev;
2337 struct drm_i915_private *dev_priv = dev->dev_private;
2338 u32 dpa_ctl;
2339
28c97730 2340 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2341 dpa_ctl = I915_READ(DP_A);
2342 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2343
2344 if (clock < 200000) {
2345 u32 temp;
2346 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2347 /* workaround for 160Mhz:
2348 1) program 0x4600c bits 15:0 = 0x8124
2349 2) program 0x46010 bit 0 = 1
2350 3) program 0x46034 bit 24 = 1
2351 4) program 0x64000 bit 14 = 1
2352 */
2353 temp = I915_READ(0x4600c);
2354 temp &= 0xffff0000;
2355 I915_WRITE(0x4600c, temp | 0x8124);
2356
2357 temp = I915_READ(0x46010);
2358 I915_WRITE(0x46010, temp | 1);
2359
2360 temp = I915_READ(0x46034);
2361 I915_WRITE(0x46034, temp | (1 << 24));
2362 } else {
2363 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2364 }
2365 I915_WRITE(DP_A, dpa_ctl);
2366
5eddb70b 2367 POSTING_READ(DP_A);
32f9d658
ZW		 2368 udelay(500);
2369}
2370
5e84e1a4
ZW		 2371static void intel_fdi_normal_train(struct drm_crtc *crtc)
2372{
2373 struct drm_device *dev = crtc->dev;
2374 struct drm_i915_private *dev_priv = dev->dev_private;
2375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2376 int pipe = intel_crtc->pipe;
2377 u32 reg, temp;
2378
2379 /* enable normal train */
2380 reg = FDI_TX_CTL(pipe);
2381 temp = I915_READ(reg);
61e499bf 2382 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2383 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2384 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2385 } else {
2386 temp &= ~FDI_LINK_TRAIN_NONE;
2387 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2388 }
5e84e1a4
ZW		 2389 I915_WRITE(reg, temp);
2390
2391 reg = FDI_RX_CTL(pipe);
2392 temp = I915_READ(reg);
2393 if (HAS_PCH_CPT(dev)) {
2394 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2395 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2396 } else {
2397 temp &= ~FDI_LINK_TRAIN_NONE;
2398 temp |= FDI_LINK_TRAIN_NONE;
2399 }
2400 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2401
2402 /* wait one idle pattern time */
2403 POSTING_READ(reg);
2404 udelay(1000);
357555c0
JB		 2405
2406 /* IVB wants error correction enabled */
2407 if (IS_IVYBRIDGE(dev))
2408 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2409 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2410}
2411
291427f5
JB		 2412static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2413{
2414 struct drm_i915_private *dev_priv = dev->dev_private;
2415 u32 flags = I915_READ(SOUTH_CHICKEN1);
2416
2417 flags |= FDI_PHASE_SYNC_OVR(pipe);
2418 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2419 flags |= FDI_PHASE_SYNC_EN(pipe);
2420 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2421 POSTING_READ(SOUTH_CHICKEN1);
2422}
2423
8db9d77b
ZW		 2424/* The FDI link training functions for ILK/Ibexpeak. */
2425static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2426{
2427 struct drm_device *dev = crtc->dev;
2428 struct drm_i915_private *dev_priv = dev->dev_private;
2429 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2430 int pipe = intel_crtc->pipe;
0fc932b8 2431 int plane = intel_crtc->plane;
5eddb70b 2432 u32 reg, temp, tries;
8db9d77b 2433
0fc932b8
JB		 2434 /* FDI needs bits from pipe & plane first */
2435 assert_pipe_enabled(dev_priv, pipe);
2436 assert_plane_enabled(dev_priv, plane);
2437
e1a44743
AJ		 2438 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2439 for train result */
5eddb70b
CW		 2440 reg = FDI_RX_IMR(pipe);
2441 temp = I915_READ(reg);
e1a44743
AJ		 2442 temp &= ~FDI_RX_SYMBOL_LOCK;
2443 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2444 I915_WRITE(reg, temp);
2445 I915_READ(reg);
e1a44743
AJ		 2446 udelay(150);
2447
8db9d77b 2448 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2449 reg = FDI_TX_CTL(pipe);
2450 temp = I915_READ(reg);
77ffb597
AJ		 2451 temp &= ~(7 << 19);
2452 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2453 temp &= ~FDI_LINK_TRAIN_NONE;
2454 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2455 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2456
5eddb70b
CW		 2457 reg = FDI_RX_CTL(pipe);
2458 temp = I915_READ(reg);
8db9d77b
ZW		 2459 temp &= ~FDI_LINK_TRAIN_NONE;
2460 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2461 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2462
2463 POSTING_READ(reg);
8db9d77b
ZW		 2464 udelay(150);
2465
5b2adf89 2466 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2467 if (HAS_PCH_IBX(dev)) {
2468 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2469 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2470 FDI_RX_PHASE_SYNC_POINTER_EN);
2471 }
5b2adf89 2472
5eddb70b 2473 reg = FDI_RX_IIR(pipe);
e1a44743 2474 for (tries = 0; tries < 5; tries++) {
5eddb70b 2475 temp = I915_READ(reg);
8db9d77b
ZW		 2476 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2477
2478 if ((temp & FDI_RX_BIT_LOCK)) {
2479 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2480 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2481 break;
2482 }
8db9d77b 2483 }
e1a44743 2484 if (tries == 5)
5eddb70b 2485 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2486
2487 /* Train 2 */
5eddb70b
CW		 2488 reg = FDI_TX_CTL(pipe);
2489 temp = I915_READ(reg);
8db9d77b
ZW		 2490 temp &= ~FDI_LINK_TRAIN_NONE;
2491 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2492 I915_WRITE(reg, temp);
8db9d77b 2493
5eddb70b
CW		 2494 reg = FDI_RX_CTL(pipe);
2495 temp = I915_READ(reg);
8db9d77b
ZW		 2496 temp &= ~FDI_LINK_TRAIN_NONE;
2497 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2498 I915_WRITE(reg, temp);
8db9d77b 2499
5eddb70b
CW		 2500 POSTING_READ(reg);
2501 udelay(150);
8db9d77b 2502
5eddb70b 2503 reg = FDI_RX_IIR(pipe);
e1a44743 2504 for (tries = 0; tries < 5; tries++) {
5eddb70b 2505 temp = I915_READ(reg);
8db9d77b
ZW		 2506 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2507
2508 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2509 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2510 DRM_DEBUG_KMS("FDI train 2 done.\n");
2511 break;
2512 }
8db9d77b 2513 }
e1a44743 2514 if (tries == 5)
5eddb70b 2515 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2516
2517 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2518
8db9d77b
ZW		 2519}
2520
0206e353 2521static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2522 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2523 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2524 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2525 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2526};
2527
2528/* The FDI link training functions for SNB/Cougarpoint. */
2529static void gen6_fdi_link_train(struct drm_crtc *crtc)
2530{
2531 struct drm_device *dev = crtc->dev;
2532 struct drm_i915_private *dev_priv = dev->dev_private;
2533 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2534 int pipe = intel_crtc->pipe;
5eddb70b 2535 u32 reg, temp, i;
8db9d77b 2536
e1a44743
AJ		 2537 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2538 for train result */
5eddb70b
CW		 2539 reg = FDI_RX_IMR(pipe);
2540 temp = I915_READ(reg);
e1a44743
AJ		 2541 temp &= ~FDI_RX_SYMBOL_LOCK;
2542 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2543 I915_WRITE(reg, temp);
2544
2545 POSTING_READ(reg);
e1a44743
AJ		 2546 udelay(150);
2547
8db9d77b 2548 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2549 reg = FDI_TX_CTL(pipe);
2550 temp = I915_READ(reg);
77ffb597
AJ		 2551 temp &= ~(7 << 19);
2552 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2553 temp &= ~FDI_LINK_TRAIN_NONE;
2554 temp |= FDI_LINK_TRAIN_PATTERN_1;
2555 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2556 /* SNB-B */
2557 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2558 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2559
5eddb70b
CW		 2560 reg = FDI_RX_CTL(pipe);
2561 temp = I915_READ(reg);
8db9d77b
ZW		 2562 if (HAS_PCH_CPT(dev)) {
2563 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2564 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2565 } else {
2566 temp &= ~FDI_LINK_TRAIN_NONE;
2567 temp |= FDI_LINK_TRAIN_PATTERN_1;
2568 }
5eddb70b
CW		 2569 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2570
2571 POSTING_READ(reg);
8db9d77b
ZW		 2572 udelay(150);
2573
291427f5
JB		 2574 if (HAS_PCH_CPT(dev))
2575 cpt_phase_pointer_enable(dev, pipe);
2576
0206e353 2577 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2578 reg = FDI_TX_CTL(pipe);
2579 temp = I915_READ(reg);
8db9d77b
ZW		 2580 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2581 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2582 I915_WRITE(reg, temp);
2583
2584 POSTING_READ(reg);
8db9d77b
ZW		 2585 udelay(500);
2586
5eddb70b
CW		 2587 reg = FDI_RX_IIR(pipe);
2588 temp = I915_READ(reg);
8db9d77b
ZW		 2589 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2590
2591 if (temp & FDI_RX_BIT_LOCK) {
5eddb70b 2592 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2593 DRM_DEBUG_KMS("FDI train 1 done.\n");
2594 break;
2595 }
2596 }
2597 if (i == 4)
5eddb70b 2598 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2599
2600 /* Train 2 */
5eddb70b
CW		 2601 reg = FDI_TX_CTL(pipe);
2602 temp = I915_READ(reg);
8db9d77b
ZW		 2603 temp &= ~FDI_LINK_TRAIN_NONE;
2604 temp |= FDI_LINK_TRAIN_PATTERN_2;
2605 if (IS_GEN6(dev)) {
2606 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2607 /* SNB-B */
2608 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2609 }
5eddb70b 2610 I915_WRITE(reg, temp);
8db9d77b 2611
5eddb70b
CW		 2612 reg = FDI_RX_CTL(pipe);
2613 temp = I915_READ(reg);
8db9d77b
ZW		 2614 if (HAS_PCH_CPT(dev)) {
2615 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2616 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2617 } else {
2618 temp &= ~FDI_LINK_TRAIN_NONE;
2619 temp |= FDI_LINK_TRAIN_PATTERN_2;
2620 }
5eddb70b
CW		 2621 I915_WRITE(reg, temp);
2622
2623 POSTING_READ(reg);
8db9d77b
ZW		 2624 udelay(150);
2625
0206e353 2626 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2627 reg = FDI_TX_CTL(pipe);
2628 temp = I915_READ(reg);
8db9d77b
ZW		 2629 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2630 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2631 I915_WRITE(reg, temp);
2632
2633 POSTING_READ(reg);
8db9d77b
ZW		 2634 udelay(500);
2635
5eddb70b
CW		 2636 reg = FDI_RX_IIR(pipe);
2637 temp = I915_READ(reg);
8db9d77b
ZW		 2638 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2639
2640 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2641 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2642 DRM_DEBUG_KMS("FDI train 2 done.\n");
2643 break;
2644 }
2645 }
2646 if (i == 4)
5eddb70b 2647 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2648
2649 DRM_DEBUG_KMS("FDI train done.\n");
2650}
2651
357555c0
JB		 2652/* Manual link training for Ivy Bridge A0 parts */
2653static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2654{
2655 struct drm_device *dev = crtc->dev;
2656 struct drm_i915_private *dev_priv = dev->dev_private;
2657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2658 int pipe = intel_crtc->pipe;
2659 u32 reg, temp, i;
2660
2661 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2662 for train result */
2663 reg = FDI_RX_IMR(pipe);
2664 temp = I915_READ(reg);
2665 temp &= ~FDI_RX_SYMBOL_LOCK;
2666 temp &= ~FDI_RX_BIT_LOCK;
2667 I915_WRITE(reg, temp);
2668
2669 POSTING_READ(reg);
2670 udelay(150);
2671
2672 /* enable CPU FDI TX and PCH FDI RX */
2673 reg = FDI_TX_CTL(pipe);
2674 temp = I915_READ(reg);
2675 temp &= ~(7 << 19);
2676 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2677 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2678 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2679 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2680 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2681 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2682 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2683
2684 reg = FDI_RX_CTL(pipe);
2685 temp = I915_READ(reg);
2686 temp &= ~FDI_LINK_TRAIN_AUTO;
2687 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2688 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2689 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2690 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2691
2692 POSTING_READ(reg);
2693 udelay(150);
2694
291427f5
JB		 2695 if (HAS_PCH_CPT(dev))
2696 cpt_phase_pointer_enable(dev, pipe);
2697
0206e353 2698 for (i = 0; i < 4; i++) {
357555c0
JB		 2699 reg = FDI_TX_CTL(pipe);
2700 temp = I915_READ(reg);
2701 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2702 temp |= snb_b_fdi_train_param[i];
2703 I915_WRITE(reg, temp);
2704
2705 POSTING_READ(reg);
2706 udelay(500);
2707
2708 reg = FDI_RX_IIR(pipe);
2709 temp = I915_READ(reg);
2710 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2711
2712 if (temp & FDI_RX_BIT_LOCK ||
2713 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2714 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2715 DRM_DEBUG_KMS("FDI train 1 done.\n");
2716 break;
2717 }
2718 }
2719 if (i == 4)
2720 DRM_ERROR("FDI train 1 fail!\n");
2721
2722 /* Train 2 */
2723 reg = FDI_TX_CTL(pipe);
2724 temp = I915_READ(reg);
2725 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2726 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2727 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2728 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2729 I915_WRITE(reg, temp);
2730
2731 reg = FDI_RX_CTL(pipe);
2732 temp = I915_READ(reg);
2733 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2734 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2735 I915_WRITE(reg, temp);
2736
2737 POSTING_READ(reg);
2738 udelay(150);
2739
0206e353 2740 for (i = 0; i < 4; i++) {
357555c0
JB		 2741 reg = FDI_TX_CTL(pipe);
2742 temp = I915_READ(reg);
2743 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2744 temp |= snb_b_fdi_train_param[i];
2745 I915_WRITE(reg, temp);
2746
2747 POSTING_READ(reg);
2748 udelay(500);
2749
2750 reg = FDI_RX_IIR(pipe);
2751 temp = I915_READ(reg);
2752 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2753
2754 if (temp & FDI_RX_SYMBOL_LOCK) {
2755 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2756 DRM_DEBUG_KMS("FDI train 2 done.\n");
2757 break;
2758 }
2759 }
2760 if (i == 4)
2761 DRM_ERROR("FDI train 2 fail!\n");
2762
2763 DRM_DEBUG_KMS("FDI train done.\n");
2764}
2765
2766static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2767{
2768 struct drm_device *dev = crtc->dev;
2769 struct drm_i915_private *dev_priv = dev->dev_private;
2770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2771 int pipe = intel_crtc->pipe;
5eddb70b 2772 u32 reg, temp;
79e53945 2773
c64e311e 2774 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2775 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2776 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2777
c98e9dcf 2778 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2779 reg = FDI_RX_CTL(pipe);
2780 temp = I915_READ(reg);
2781 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2782 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2783 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2784 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2785
2786 POSTING_READ(reg);
c98e9dcf
JB		 2787 udelay(200);
2788
2789 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2790 temp = I915_READ(reg);
2791 I915_WRITE(reg, temp | FDI_PCDCLK);
2792
2793 POSTING_READ(reg);
c98e9dcf
JB		 2794 udelay(200);
2795
2796 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2797 reg = FDI_TX_CTL(pipe);
2798 temp = I915_READ(reg);
c98e9dcf 2799 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2800 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2801
2802 POSTING_READ(reg);
c98e9dcf 2803 udelay(100);
6be4a607 2804 }
0e23b99d
JB		 2805}
2806
291427f5
JB		 2807static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2808{
2809 struct drm_i915_private *dev_priv = dev->dev_private;
2810 u32 flags = I915_READ(SOUTH_CHICKEN1);
2811
2812 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2813 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2814 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2815 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2816 POSTING_READ(SOUTH_CHICKEN1);
2817}
0fc932b8
JB		 2818static void ironlake_fdi_disable(struct drm_crtc *crtc)
2819{
2820 struct drm_device *dev = crtc->dev;
2821 struct drm_i915_private *dev_priv = dev->dev_private;
2822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2823 int pipe = intel_crtc->pipe;
2824 u32 reg, temp;
2825
2826 /* disable CPU FDI tx and PCH FDI rx */
2827 reg = FDI_TX_CTL(pipe);
2828 temp = I915_READ(reg);
2829 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2830 POSTING_READ(reg);
2831
2832 reg = FDI_RX_CTL(pipe);
2833 temp = I915_READ(reg);
2834 temp &= ~(0x7 << 16);
2835 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2836 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2837
2838 POSTING_READ(reg);
2839 udelay(100);
2840
2841 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2842 if (HAS_PCH_IBX(dev)) {
2843 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2844 I915_WRITE(FDI_RX_CHICKEN(pipe),
2845 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2846 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2847 } else if (HAS_PCH_CPT(dev)) {
2848 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2849 }
0fc932b8
JB		 2850
2851 /* still set train pattern 1 */
2852 reg = FDI_TX_CTL(pipe);
2853 temp = I915_READ(reg);
2854 temp &= ~FDI_LINK_TRAIN_NONE;
2855 temp |= FDI_LINK_TRAIN_PATTERN_1;
2856 I915_WRITE(reg, temp);
2857
2858 reg = FDI_RX_CTL(pipe);
2859 temp = I915_READ(reg);
2860 if (HAS_PCH_CPT(dev)) {
2861 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2862 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2863 } else {
2864 temp &= ~FDI_LINK_TRAIN_NONE;
2865 temp |= FDI_LINK_TRAIN_PATTERN_1;
2866 }
2867 /* BPC in FDI rx is consistent with that in PIPECONF */
2868 temp &= ~(0x07 << 16);
2869 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2870 I915_WRITE(reg, temp);
2871
2872 POSTING_READ(reg);
2873 udelay(100);
2874}
2875
6b383a7f
CW		 2876/*
2877 * When we disable a pipe, we need to clear any pending scanline wait events
2878 * to avoid hanging the ring, which we assume we are waiting on.
2879 */
2880static void intel_clear_scanline_wait(struct drm_device *dev)
2881{
2882 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 2883 struct intel_ring_buffer *ring;
6b383a7f
CW		 2884 u32 tmp;
2885
2886 if (IS_GEN2(dev))
2887 /* Can't break the hang on i8xx */
2888 return;
2889
1ec14ad3 2890 ring = LP_RING(dev_priv);
8168bd48
CW		 2891 tmp = I915_READ_CTL(ring);
2892 if (tmp & RING_WAIT)
2893 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 2894}
2895
e6c3a2a6
CW		 2896static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2897{
05394f39 2898 struct drm_i915_gem_object *obj;
e6c3a2a6
CW		 2899 struct drm_i915_private *dev_priv;
2900
2901 if (crtc->fb == NULL)
2902 return;
2903
05394f39 2904 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW		 2905 dev_priv = crtc->dev->dev_private;
2906 wait_event(dev_priv->pending_flip_queue,
05394f39 2907 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW		 2908}
2909
040484af
JB		 2910static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2911{
2912 struct drm_device *dev = crtc->dev;
2913 struct drm_mode_config *mode_config = &dev->mode_config;
2914 struct intel_encoder *encoder;
2915
2916 /*
2917 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2918 * must be driven by its own crtc; no sharing is possible.
2919 */
2920 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2921 if (encoder->base.crtc != crtc)
2922 continue;
2923
2924 switch (encoder->type) {
2925 case INTEL_OUTPUT_EDP:
2926 if (!intel_encoder_is_pch_edp(&encoder->base))
2927 return false;
2928 continue;
2929 }
2930 }
2931
2932 return true;
2933}
2934
f67a559d
JB		 2935/*
2936 * Enable PCH resources required for PCH ports:
2937 * - PCH PLLs
2938 * - FDI training & RX/TX
2939 * - update transcoder timings
2940 * - DP transcoding bits
2941 * - transcoder
2942 */
2943static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2944{
2945 struct drm_device *dev = crtc->dev;
2946 struct drm_i915_private *dev_priv = dev->dev_private;
2947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2948 int pipe = intel_crtc->pipe;
4b645f14 2949 u32 reg, temp, transc_sel;
2c07245f 2950
c98e9dcf 2951 /* For PCH output, training FDI link */
674cf967 2952 dev_priv->display.fdi_link_train(crtc);
2c07245f 2953
92f2584a 2954 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 2955
c98e9dcf 2956 if (HAS_PCH_CPT(dev)) {
4b645f14
JB		 2957 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2958 TRANSC_DPLLB_SEL;
2959
c98e9dcf
JB		 2960 /* Be sure PCH DPLL SEL is set */
2961 temp = I915_READ(PCH_DPLL_SEL);
d64311ab
JB		 2962 if (pipe == 0) {
2963 temp &= ~(TRANSA_DPLLB_SEL);
c98e9dcf 2964 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
d64311ab
JB		 2965 } else if (pipe == 1) {
2966 temp &= ~(TRANSB_DPLLB_SEL);
c98e9dcf 2967 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
d64311ab
JB		 2968 } else if (pipe == 2) {
2969 temp &= ~(TRANSC_DPLLB_SEL);
4b645f14 2970 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
d64311ab 2971 }
c98e9dcf 2972 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2973 }
5eddb70b 2974
d9b6cb56
JB		 2975 /* set transcoder timing, panel must allow it */
2976 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2977 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2978 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2979 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2980
5eddb70b
CW		 2981 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2982 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2983 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 2984 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 2985
5e84e1a4
ZW		 2986 intel_fdi_normal_train(crtc);
2987
c98e9dcf
JB		 2988 /* For PCH DP, enable TRANS_DP_CTL */
2989 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2990 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2991 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 2992 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 2993 reg = TRANS_DP_CTL(pipe);
2994 temp = I915_READ(reg);
2995 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2996 TRANS_DP_SYNC_MASK |
2997 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2998 temp |= (TRANS_DP_OUTPUT_ENABLE |
2999 TRANS_DP_ENH_FRAMING);
9325c9f0 3000 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3001
3002 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3003 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3004 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3005 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3006
3007 switch (intel_trans_dp_port_sel(crtc)) {
3008 case PCH_DP_B:
5eddb70b 3009 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3010 break;
3011 case PCH_DP_C:
5eddb70b 3012 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3013 break;
3014 case PCH_DP_D:
5eddb70b 3015 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3016 break;
3017 default:
3018 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 3019 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 3020 break;
32f9d658 3021 }
2c07245f 3022
5eddb70b 3023 I915_WRITE(reg, temp);
6be4a607 3024 }
b52eb4dc 3025
040484af 3026 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3027}
3028
d4270e57
JB		 3029void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3030{
3031 struct drm_i915_private *dev_priv = dev->dev_private;
3032 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3033 u32 temp;
3034
3035 temp = I915_READ(dslreg);
3036 udelay(500);
3037 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3038 /* Without this, mode sets may fail silently on FDI */
3039 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3040 udelay(250);
3041 I915_WRITE(tc2reg, 0);
3042 if (wait_for(I915_READ(dslreg) != temp, 5))
3043 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3044 }
3045}
3046
f67a559d
JB		 3047static void ironlake_crtc_enable(struct drm_crtc *crtc)
3048{
3049 struct drm_device *dev = crtc->dev;
3050 struct drm_i915_private *dev_priv = dev->dev_private;
3051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3052 int pipe = intel_crtc->pipe;
3053 int plane = intel_crtc->plane;
3054 u32 temp;
3055 bool is_pch_port;
3056
3057 if (intel_crtc->active)
3058 return;
3059
3060 intel_crtc->active = true;
3061 intel_update_watermarks(dev);
3062
3063 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3064 temp = I915_READ(PCH_LVDS);
3065 if ((temp & LVDS_PORT_EN) == 0)
3066 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3067 }
3068
3069 is_pch_port = intel_crtc_driving_pch(crtc);
3070
3071 if (is_pch_port)
357555c0 3072 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 3073 else
3074 ironlake_fdi_disable(crtc);
3075
3076 /* Enable panel fitting for LVDS */
3077 if (dev_priv->pch_pf_size &&
3078 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3079 /* Force use of hard-coded filter coefficients
3080 * as some pre-programmed values are broken,
3081 * e.g. x201.
3082 */
9db4a9c7
JB		 3083 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3084 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3085 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3086 }
3087
9c54c0dd
JB		 3088 /*
3089 * On ILK+ LUT must be loaded before the pipe is running but with
3090 * clocks enabled
3091 */
3092 intel_crtc_load_lut(crtc);
3093
f67a559d
JB		 3094 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3095 intel_enable_plane(dev_priv, plane, pipe);
3096
3097 if (is_pch_port)
3098 ironlake_pch_enable(crtc);
c98e9dcf 3099
d1ebd816 3100 mutex_lock(&dev->struct_mutex);
bed4a673 3101 intel_update_fbc(dev);
d1ebd816
BW		 3102 mutex_unlock(&dev->struct_mutex);
3103
6b383a7f 3104 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 3105}
3106
3107static void ironlake_crtc_disable(struct drm_crtc *crtc)
3108{
3109 struct drm_device *dev = crtc->dev;
3110 struct drm_i915_private *dev_priv = dev->dev_private;
3111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3112 int pipe = intel_crtc->pipe;
3113 int plane = intel_crtc->plane;
5eddb70b 3114 u32 reg, temp;
b52eb4dc 3115
f7abfe8b
CW		 3116 if (!intel_crtc->active)
3117 return;
3118
e6c3a2a6 3119 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3120 drm_vblank_off(dev, pipe);
6b383a7f 3121 intel_crtc_update_cursor(crtc, false);
5eddb70b 3122
b24e7179 3123 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3124
973d04f9
CW		 3125 if (dev_priv->cfb_plane == plane)
3126 intel_disable_fbc(dev);
2c07245f 3127
b24e7179 3128 intel_disable_pipe(dev_priv, pipe);
32f9d658 3129
6be4a607 3130 /* Disable PF */
9db4a9c7
JB		 3131 I915_WRITE(PF_CTL(pipe), 0);
3132 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3133
0fc932b8 3134 ironlake_fdi_disable(crtc);
2c07245f 3135
47a05eca
JB		 3136 /* This is a horrible layering violation; we should be doing this in
3137 * the connector/encoder ->prepare instead, but we don't always have
3138 * enough information there about the config to know whether it will
3139 * actually be necessary or just cause undesired flicker.
3140 */
3141 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 3142
040484af 3143 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3144
6be4a607
JB		 3145 if (HAS_PCH_CPT(dev)) {
3146 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3147 reg = TRANS_DP_CTL(pipe);
3148 temp = I915_READ(reg);
3149 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3150 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3151 I915_WRITE(reg, temp);
6be4a607
JB		 3152
3153 /* disable DPLL_SEL */
3154 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3155 switch (pipe) {
3156 case 0:
d64311ab 3157 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3158 break;
3159 case 1:
6be4a607 3160 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3161 break;
3162 case 2:
4b645f14 3163 /* C shares PLL A or B */
d64311ab 3164 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3165 break;
3166 default:
3167 BUG(); /* wtf */
3168 }
6be4a607 3169 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3170 }
e3421a18 3171
6be4a607 3172 /* disable PCH DPLL */
4b645f14
JB		 3173 if (!intel_crtc->no_pll)
3174 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 3175
6be4a607 3176 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 3177 reg = FDI_RX_CTL(pipe);
3178 temp = I915_READ(reg);
3179 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 3180
6be4a607 3181 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 3182 reg = FDI_TX_CTL(pipe);
3183 temp = I915_READ(reg);
3184 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3185
3186 POSTING_READ(reg);
6be4a607 3187 udelay(100);
8db9d77b 3188
5eddb70b
CW		 3189 reg = FDI_RX_CTL(pipe);
3190 temp = I915_READ(reg);
3191 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 3192
6be4a607 3193 /* Wait for the clocks to turn off. */
5eddb70b 3194 POSTING_READ(reg);
6be4a607 3195 udelay(100);
6b383a7f 3196
f7abfe8b 3197 intel_crtc->active = false;
6b383a7f 3198 intel_update_watermarks(dev);
d1ebd816
BW		 3199
3200 mutex_lock(&dev->struct_mutex);
6b383a7f
CW		 3201 intel_update_fbc(dev);
3202 intel_clear_scanline_wait(dev);
d1ebd816 3203 mutex_unlock(&dev->struct_mutex);
6be4a607 3204}
1b3c7a47 3205
6be4a607
JB		 3206static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3207{
3208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3209 int pipe = intel_crtc->pipe;
3210 int plane = intel_crtc->plane;
8db9d77b 3211
6be4a607
JB		 3212 /* XXX: When our outputs are all unaware of DPMS modes other than off
3213 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3214 */
3215 switch (mode) {
3216 case DRM_MODE_DPMS_ON:
3217 case DRM_MODE_DPMS_STANDBY:
3218 case DRM_MODE_DPMS_SUSPEND:
3219 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3220 ironlake_crtc_enable(crtc);
3221 break;
1b3c7a47 3222
6be4a607
JB		 3223 case DRM_MODE_DPMS_OFF:
3224 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3225 ironlake_crtc_disable(crtc);
2c07245f
ZW		 3226 break;
3227 }
3228}
3229
02e792fb
DV		 3230static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3231{
02e792fb 3232 if (!enable && intel_crtc->overlay) {
23f09ce3 3233 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3234 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3235
23f09ce3 3236 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3237 dev_priv->mm.interruptible = false;
3238 (void) intel_overlay_switch_off(intel_crtc->overlay);
3239 dev_priv->mm.interruptible = true;
23f09ce3 3240 mutex_unlock(&dev->struct_mutex);
02e792fb 3241 }
02e792fb 3242
5dcdbcb0
CW		 3243 /* Let userspace switch the overlay on again. In most cases userspace
3244 * has to recompute where to put it anyway.
3245 */
02e792fb
DV		 3246}
3247
0b8765c6 3248static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3249{
3250 struct drm_device *dev = crtc->dev;
79e53945
JB		 3251 struct drm_i915_private *dev_priv = dev->dev_private;
3252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3253 int pipe = intel_crtc->pipe;
80824003 3254 int plane = intel_crtc->plane;
79e53945 3255
f7abfe8b
CW		 3256 if (intel_crtc->active)
3257 return;
3258
3259 intel_crtc->active = true;
6b383a7f
CW		 3260 intel_update_watermarks(dev);
3261
63d7bbe9 3262 intel_enable_pll(dev_priv, pipe);
040484af 3263 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3264 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3265
0b8765c6 3266 intel_crtc_load_lut(crtc);
bed4a673 3267 intel_update_fbc(dev);
79e53945 3268
0b8765c6
JB		 3269 /* Give the overlay scaler a chance to enable if it's on this pipe */
3270 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3271 intel_crtc_update_cursor(crtc, true);
0b8765c6 3272}
79e53945 3273
0b8765c6
JB		 3274static void i9xx_crtc_disable(struct drm_crtc *crtc)
3275{
3276 struct drm_device *dev = crtc->dev;
3277 struct drm_i915_private *dev_priv = dev->dev_private;
3278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3279 int pipe = intel_crtc->pipe;
3280 int plane = intel_crtc->plane;
b690e96c 3281
f7abfe8b
CW		 3282 if (!intel_crtc->active)
3283 return;
3284
0b8765c6 3285 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3286 intel_crtc_wait_for_pending_flips(crtc);
3287 drm_vblank_off(dev, pipe);
0b8765c6 3288 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3289 intel_crtc_update_cursor(crtc, false);
0b8765c6 3290
973d04f9
CW		 3291 if (dev_priv->cfb_plane == plane)
3292 intel_disable_fbc(dev);
79e53945 3293
b24e7179 3294 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3295 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3296 intel_disable_pll(dev_priv, pipe);
0b8765c6 3297
f7abfe8b 3298 intel_crtc->active = false;
6b383a7f
CW		 3299 intel_update_fbc(dev);
3300 intel_update_watermarks(dev);
3301 intel_clear_scanline_wait(dev);
0b8765c6
JB		 3302}
3303
3304static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3305{
3306 /* XXX: When our outputs are all unaware of DPMS modes other than off
3307 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3308 */
3309 switch (mode) {
3310 case DRM_MODE_DPMS_ON:
3311 case DRM_MODE_DPMS_STANDBY:
3312 case DRM_MODE_DPMS_SUSPEND:
3313 i9xx_crtc_enable(crtc);
3314 break;
3315 case DRM_MODE_DPMS_OFF:
3316 i9xx_crtc_disable(crtc);
79e53945
JB		 3317 break;
3318 }
2c07245f
ZW		 3319}
3320
3321/**
3322 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3323 */
3324static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3325{
3326 struct drm_device *dev = crtc->dev;
e70236a8 3327 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3328 struct drm_i915_master_private *master_priv;
3329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3330 int pipe = intel_crtc->pipe;
3331 bool enabled;
3332
032d2a0d
CW		 3333 if (intel_crtc->dpms_mode == mode)
3334 return;
3335
65655d4a 3336 intel_crtc->dpms_mode = mode;
debcaddc 3337
e70236a8 3338 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3339
3340 if (!dev->primary->master)
3341 return;
3342
3343 master_priv = dev->primary->master->driver_priv;
3344 if (!master_priv->sarea_priv)
3345 return;
3346
3347 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3348
3349 switch (pipe) {
3350 case 0:
3351 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3352 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3353 break;
3354 case 1:
3355 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3356 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3357 break;
3358 default:
9db4a9c7 3359 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3360 break;
3361 }
79e53945
JB		 3362}
3363
cdd59983
CW		 3364static void intel_crtc_disable(struct drm_crtc *crtc)
3365{
3366 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3367 struct drm_device *dev = crtc->dev;
3368
3369 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
931872fc
CW		 3370 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3371 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3372
3373 if (crtc->fb) {
3374 mutex_lock(&dev->struct_mutex);
1690e1eb 3375 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983
CW		 3376 mutex_unlock(&dev->struct_mutex);
3377 }
3378}
3379
7e7d76c3
JB		 3380/* Prepare for a mode set.
3381 *
3382 * Note we could be a lot smarter here. We need to figure out which outputs
3383 * will be enabled, which disabled (in short, how the config will changes)
3384 * and perform the minimum necessary steps to accomplish that, e.g. updating
3385 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3386 * panel fitting is in the proper state, etc.
3387 */
3388static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3389{
7e7d76c3 3390 i9xx_crtc_disable(crtc);
79e53945
JB		 3391}
3392
7e7d76c3 3393static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3394{
7e7d76c3 3395 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3396}
3397
3398static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3399{
7e7d76c3 3400 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3401}
3402
3403static void ironlake_crtc_commit(struct drm_crtc *crtc)
3404{
7e7d76c3 3405 ironlake_crtc_enable(crtc);
79e53945
JB		 3406}
3407
0206e353 3408void intel_encoder_prepare(struct drm_encoder *encoder)
79e53945
JB		 3409{
3410 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3411 /* lvds has its own version of prepare see intel_lvds_prepare */
3412 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3413}
3414
0206e353 3415void intel_encoder_commit(struct drm_encoder *encoder)
79e53945
JB		 3416{
3417 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
d4270e57
JB		 3418 struct drm_device *dev = encoder->dev;
3419 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3420 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3421
79e53945
JB		 3422 /* lvds has its own version of commit see intel_lvds_commit */
3423 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
d4270e57
JB		 3424
3425 if (HAS_PCH_CPT(dev))
3426 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
79e53945
JB		 3427}
3428
ea5b213a
CW		 3429void intel_encoder_destroy(struct drm_encoder *encoder)
3430{
4ef69c7a 3431 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3432
ea5b213a
CW		 3433 drm_encoder_cleanup(encoder);
3434 kfree(intel_encoder);
3435}
3436
79e53945
JB		 3437static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3438 struct drm_display_mode *mode,
3439 struct drm_display_mode *adjusted_mode)
3440{
2c07245f 3441 struct drm_device *dev = crtc->dev;
89749350 3442
bad720ff 3443 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3444 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3445 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3446 return false;
2c07245f 3447 }
89749350 3448
ca9bfa7e
DV		 3449 /* All interlaced capable intel hw wants timings in frames. */
3450 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3451
79e53945
JB		 3452 return true;
3453}
3454
e70236a8
JB		 3455static int i945_get_display_clock_speed(struct drm_device *dev)
3456{
3457 return 400000;
3458}
79e53945 3459
e70236a8 3460static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3461{
e70236a8
JB		 3462 return 333000;
3463}
79e53945 3464
e70236a8
JB		 3465static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3466{
3467 return 200000;
3468}
79e53945 3469
e70236a8
JB		 3470static int i915gm_get_display_clock_speed(struct drm_device *dev)
3471{
3472 u16 gcfgc = 0;
79e53945 3473
e70236a8
JB		 3474 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3475
3476 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3477 return 133000;
3478 else {
3479 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3480 case GC_DISPLAY_CLOCK_333_MHZ:
3481 return 333000;
3482 default:
3483 case GC_DISPLAY_CLOCK_190_200_MHZ:
3484 return 190000;
79e53945 3485 }
e70236a8
JB		 3486 }
3487}
3488
3489static int i865_get_display_clock_speed(struct drm_device *dev)
3490{
3491 return 266000;
3492}
3493
3494static int i855_get_display_clock_speed(struct drm_device *dev)
3495{
3496 u16 hpllcc = 0;
3497 /* Assume that the hardware is in the high speed state. This
3498 * should be the default.
3499 */
3500 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3501 case GC_CLOCK_133_200:
3502 case GC_CLOCK_100_200:
3503 return 200000;
3504 case GC_CLOCK_166_250:
3505 return 250000;
3506 case GC_CLOCK_100_133:
79e53945 3507 return 133000;
e70236a8 3508 }
79e53945 3509
e70236a8
JB		 3510 /* Shouldn't happen */
3511 return 0;
3512}
79e53945 3513
e70236a8
JB		 3514static int i830_get_display_clock_speed(struct drm_device *dev)
3515{
3516 return 133000;
79e53945
JB		 3517}
3518
2c07245f
ZW		 3519struct fdi_m_n {
3520 u32 tu;
3521 u32 gmch_m;
3522 u32 gmch_n;
3523 u32 link_m;
3524 u32 link_n;
3525};
3526
3527static void
3528fdi_reduce_ratio(u32 *num, u32 *den)
3529{
3530 while (*num > 0xffffff || *den > 0xffffff) {
3531 *num >>= 1;
3532 *den >>= 1;
3533 }
3534}
3535
2c07245f 3536static void
f2b115e6
AJ		 3537ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3538 int link_clock, struct fdi_m_n *m_n)
2c07245f 3539{
2c07245f
ZW		 3540 m_n->tu = 64; /* default size */
3541
22ed1113
CW		 3542 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3543 m_n->gmch_m = bits_per_pixel * pixel_clock;
3544 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3545 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3546
22ed1113
CW		 3547 m_n->link_m = pixel_clock;
3548 m_n->link_n = link_clock;
2c07245f
ZW		 3549 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3550}
3551
3552
7662c8bd
SL		 3553struct intel_watermark_params {
3554 unsigned long fifo_size;
3555 unsigned long max_wm;
3556 unsigned long default_wm;
3557 unsigned long guard_size;
3558 unsigned long cacheline_size;
3559};
3560
f2b115e6 3561/* Pineview has different values for various configs */
d210246a 3562static const struct intel_watermark_params pineview_display_wm = {
f2b115e6
AJ		 3563 PINEVIEW_DISPLAY_FIFO,
3564 PINEVIEW_MAX_WM,
3565 PINEVIEW_DFT_WM,
3566 PINEVIEW_GUARD_WM,
3567 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3568};
d210246a 3569static const struct intel_watermark_params pineview_display_hplloff_wm = {
f2b115e6
AJ		 3570 PINEVIEW_DISPLAY_FIFO,
3571 PINEVIEW_MAX_WM,
3572 PINEVIEW_DFT_HPLLOFF_WM,
3573 PINEVIEW_GUARD_WM,
3574 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3575};
d210246a 3576static const struct intel_watermark_params pineview_cursor_wm = {
f2b115e6
AJ		 3577 PINEVIEW_CURSOR_FIFO,
3578 PINEVIEW_CURSOR_MAX_WM,
3579 PINEVIEW_CURSOR_DFT_WM,
3580 PINEVIEW_CURSOR_GUARD_WM,
3581 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 3582};
d210246a 3583static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
f2b115e6
AJ		 3584 PINEVIEW_CURSOR_FIFO,
3585 PINEVIEW_CURSOR_MAX_WM,
3586 PINEVIEW_CURSOR_DFT_WM,
3587 PINEVIEW_CURSOR_GUARD_WM,
3588 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3589};
d210246a 3590static const struct intel_watermark_params g4x_wm_info = {
0e442c60
JB		 3591 G4X_FIFO_SIZE,
3592 G4X_MAX_WM,
3593 G4X_MAX_WM,
3594 2,
3595 G4X_FIFO_LINE_SIZE,
3596};
d210246a 3597static const struct intel_watermark_params g4x_cursor_wm_info = {
4fe5e611
ZY		 3598 I965_CURSOR_FIFO,
3599 I965_CURSOR_MAX_WM,
3600 I965_CURSOR_DFT_WM,
3601 2,
3602 G4X_FIFO_LINE_SIZE,
3603};
d210246a 3604static const struct intel_watermark_params i965_cursor_wm_info = {
4fe5e611
ZY		 3605 I965_CURSOR_FIFO,
3606 I965_CURSOR_MAX_WM,
3607 I965_CURSOR_DFT_WM,
3608 2,
3609 I915_FIFO_LINE_SIZE,
3610};
d210246a 3611static const struct intel_watermark_params i945_wm_info = {
dff33cfc 3612 I945_FIFO_SIZE,
7662c8bd
SL		 3613 I915_MAX_WM,
3614 1,
dff33cfc
JB		 3615 2,
3616 I915_FIFO_LINE_SIZE
7662c8bd 3617};
d210246a 3618static const struct intel_watermark_params i915_wm_info = {
dff33cfc 3619 I915_FIFO_SIZE,
7662c8bd
SL		 3620 I915_MAX_WM,
3621 1,
dff33cfc 3622 2,
7662c8bd
SL		 3623 I915_FIFO_LINE_SIZE
3624};
d210246a 3625static const struct intel_watermark_params i855_wm_info = {
7662c8bd
SL		 3626 I855GM_FIFO_SIZE,
3627 I915_MAX_WM,
3628 1,
dff33cfc 3629 2,
7662c8bd
SL		 3630 I830_FIFO_LINE_SIZE
3631};
d210246a 3632static const struct intel_watermark_params i830_wm_info = {
7662c8bd
SL		 3633 I830_FIFO_SIZE,
3634 I915_MAX_WM,
3635 1,
dff33cfc 3636 2,
7662c8bd
SL		 3637 I830_FIFO_LINE_SIZE
3638};
3639
d210246a 3640static const struct intel_watermark_params ironlake_display_wm_info = {
7f8a8569
ZW		 3641 ILK_DISPLAY_FIFO,
3642 ILK_DISPLAY_MAXWM,
3643 ILK_DISPLAY_DFTWM,
3644 2,
3645 ILK_FIFO_LINE_SIZE
3646};
d210246a 3647static const struct intel_watermark_params ironlake_cursor_wm_info = {
c936f44d
ZY		 3648 ILK_CURSOR_FIFO,
3649 ILK_CURSOR_MAXWM,
3650 ILK_CURSOR_DFTWM,
3651 2,
3652 ILK_FIFO_LINE_SIZE
3653};
d210246a 3654static const struct intel_watermark_params ironlake_display_srwm_info = {
7f8a8569
ZW		 3655 ILK_DISPLAY_SR_FIFO,
3656 ILK_DISPLAY_MAX_SRWM,
3657 ILK_DISPLAY_DFT_SRWM,
3658 2,
3659 ILK_FIFO_LINE_SIZE
3660};
d210246a 3661static const struct intel_watermark_params ironlake_cursor_srwm_info = {
7f8a8569
ZW		 3662 ILK_CURSOR_SR_FIFO,
3663 ILK_CURSOR_MAX_SRWM,
3664 ILK_CURSOR_DFT_SRWM,
3665 2,
3666 ILK_FIFO_LINE_SIZE
3667};
3668
d210246a 3669static const struct intel_watermark_params sandybridge_display_wm_info = {
1398261a
YL		 3670 SNB_DISPLAY_FIFO,
3671 SNB_DISPLAY_MAXWM,
3672 SNB_DISPLAY_DFTWM,
3673 2,
3674 SNB_FIFO_LINE_SIZE
3675};
d210246a 3676static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1398261a
YL		 3677 SNB_CURSOR_FIFO,
3678 SNB_CURSOR_MAXWM,
3679 SNB_CURSOR_DFTWM,
3680 2,
3681 SNB_FIFO_LINE_SIZE
3682};
d210246a 3683static const struct intel_watermark_params sandybridge_display_srwm_info = {
1398261a
YL		 3684 SNB_DISPLAY_SR_FIFO,
3685 SNB_DISPLAY_MAX_SRWM,
3686 SNB_DISPLAY_DFT_SRWM,
3687 2,
3688 SNB_FIFO_LINE_SIZE
3689};
d210246a 3690static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1398261a
YL		 3691 SNB_CURSOR_SR_FIFO,
3692 SNB_CURSOR_MAX_SRWM,
3693 SNB_CURSOR_DFT_SRWM,
3694 2,
3695 SNB_FIFO_LINE_SIZE
3696};
3697
3698
dff33cfc
JB		 3699/**
3700 * intel_calculate_wm - calculate watermark level
3701 * @clock_in_khz: pixel clock
3702 * @wm: chip FIFO params
3703 * @pixel_size: display pixel size
3704 * @latency_ns: memory latency for the platform
3705 *
3706 * Calculate the watermark level (the level at which the display plane will
3707 * start fetching from memory again). Each chip has a different display
3708 * FIFO size and allocation, so the caller needs to figure that out and pass
3709 * in the correct intel_watermark_params structure.
3710 *
3711 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3712 * on the pixel size. When it reaches the watermark level, it'll start
3713 * fetching FIFO line sized based chunks from memory until the FIFO fills
3714 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3715 * will occur, and a display engine hang could result.
3716 */
7662c8bd 3717static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
d210246a
CW		 3718 const struct intel_watermark_params *wm,
3719 int fifo_size,
7662c8bd
SL		 3720 int pixel_size,
3721 unsigned long latency_ns)
3722{
390c4dd4 3723 long entries_required, wm_size;
dff33cfc 3724
d660467c
JB		 3725 /*
3726 * Note: we need to make sure we don't overflow for various clock &
3727 * latency values.
3728 * clocks go from a few thousand to several hundred thousand.
3729 * latency is usually a few thousand
3730 */
3731 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3732 1000;
8de9b311 3733 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 3734
bbb0aef5 3735 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
dff33cfc 3736
d210246a 3737 wm_size = fifo_size - (entries_required + wm->guard_size);
dff33cfc 3738
bbb0aef5 3739 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
7662c8bd 3740
390c4dd4
JB		 3741 /* Don't promote wm_size to unsigned... */
3742 if (wm_size > (long)wm->max_wm)
7662c8bd 3743 wm_size = wm->max_wm;
c3add4b6 3744 if (wm_size <= 0)
7662c8bd
SL		 3745 wm_size = wm->default_wm;
3746 return wm_size;
3747}
3748
3749struct cxsr_latency {
3750 int is_desktop;
95534263 3751 int is_ddr3;
7662c8bd
SL		 3752 unsigned long fsb_freq;
3753 unsigned long mem_freq;
3754 unsigned long display_sr;
3755 unsigned long display_hpll_disable;
3756 unsigned long cursor_sr;
3757 unsigned long cursor_hpll_disable;
3758};
3759
403c89ff 3760static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP		 3761 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3762 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3763 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3764 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3765 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3766
3767 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3768 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3769 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3770 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3771 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3772
3773 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3774 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3775 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3776 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3777 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3778
3779 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3780 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3781 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3782 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3783 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3784
3785 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3786 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3787 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3788 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3789 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3790
3791 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3792 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3793 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3794 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3795 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL		 3796};
3797
403c89ff
CW		 3798static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3799 int is_ddr3,
3800 int fsb,
3801 int mem)
7662c8bd 3802{
403c89ff 3803 const struct cxsr_latency *latency;
7662c8bd 3804 int i;
7662c8bd
SL		 3805
3806 if (fsb == 0 || mem == 0)
3807 return NULL;
3808
3809 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3810 latency = &cxsr_latency_table[i];
3811 if (is_desktop == latency->is_desktop &&
95534263 3812 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR		 3813 fsb == latency->fsb_freq && mem == latency->mem_freq)
3814 return latency;
7662c8bd 3815 }
decbbcda 3816
28c97730 3817 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR		 3818
3819 return NULL;
7662c8bd
SL		 3820}
3821
f2b115e6 3822static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL		 3823{
3824 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL		 3825
3826 /* deactivate cxsr */
3e33d94d 3827 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL		 3828}
3829
bcc24fb4
JB		 3830/*
3831 * Latency for FIFO fetches is dependent on several factors:
3832 * - memory configuration (speed, channels)
3833 * - chipset
3834 * - current MCH state
3835 * It can be fairly high in some situations, so here we assume a fairly
3836 * pessimal value. It's a tradeoff between extra memory fetches (if we
3837 * set this value too high, the FIFO will fetch frequently to stay full)
3838 * and power consumption (set it too low to save power and we might see
3839 * FIFO underruns and display "flicker").
3840 *
3841 * A value of 5us seems to be a good balance; safe for very low end
3842 * platforms but not overly aggressive on lower latency configs.
3843 */
69e302a9 3844static const int latency_ns = 5000;
7662c8bd 3845
e70236a8 3846static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB		 3847{
3848 struct drm_i915_private *dev_priv = dev->dev_private;
3849 uint32_t dsparb = I915_READ(DSPARB);
3850 int size;
3851
8de9b311
CW		 3852 size = dsparb & 0x7f;
3853 if (plane)
3854 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 3855
28c97730 3856 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3857 plane ? "B" : "A", size);
dff33cfc
JB		 3858
3859 return size;
3860}
7662c8bd 3861
e70236a8
JB		 3862static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3863{
3864 struct drm_i915_private *dev_priv = dev->dev_private;
3865 uint32_t dsparb = I915_READ(DSPARB);
3866 int size;
3867
8de9b311
CW		 3868 size = dsparb & 0x1ff;
3869 if (plane)
3870 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 3871 size >>= 1; /* Convert to cachelines */
dff33cfc 3872
28c97730 3873 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3874 plane ? "B" : "A", size);
dff33cfc
JB		 3875
3876 return size;
3877}
7662c8bd 3878
e70236a8
JB		 3879static int i845_get_fifo_size(struct drm_device *dev, int plane)
3880{
3881 struct drm_i915_private *dev_priv = dev->dev_private;
3882 uint32_t dsparb = I915_READ(DSPARB);
3883 int size;
3884
3885 size = dsparb & 0x7f;
3886 size >>= 2; /* Convert to cachelines */
3887
28c97730 3888 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW		 3889 plane ? "B" : "A",
3890 size);
e70236a8
JB		 3891
3892 return size;
3893}
3894
3895static int i830_get_fifo_size(struct drm_device *dev, int plane)
3896{
3897 struct drm_i915_private *dev_priv = dev->dev_private;
3898 uint32_t dsparb = I915_READ(DSPARB);
3899 int size;
3900
3901 size = dsparb & 0x7f;
3902 size >>= 1; /* Convert to cachelines */
3903
28c97730 3904 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3905 plane ? "B" : "A", size);
e70236a8
JB		 3906
3907 return size;
3908}
3909
d210246a
CW		 3910static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3911{
3912 struct drm_crtc *crtc, *enabled = NULL;
3913
3914 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3915 if (crtc->enabled && crtc->fb) {
3916 if (enabled)
3917 return NULL;
3918 enabled = crtc;
3919 }
3920 }
3921
3922 return enabled;
3923}
3924
3925static void pineview_update_wm(struct drm_device *dev)
d4294342
ZY		 3926{
3927 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3928 struct drm_crtc *crtc;
403c89ff 3929 const struct cxsr_latency *latency;
d4294342
ZY		 3930 u32 reg;
3931 unsigned long wm;
d4294342 3932
403c89ff 3933 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 3934 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY		 3935 if (!latency) {
3936 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3937 pineview_disable_cxsr(dev);
3938 return;
3939 }
3940
d210246a
CW		 3941 crtc = single_enabled_crtc(dev);
3942 if (crtc) {
3943 int clock = crtc->mode.clock;
3944 int pixel_size = crtc->fb->bits_per_pixel / 8;
d4294342
ZY		 3945
3946 /* Display SR */
d210246a
CW		 3947 wm = intel_calculate_wm(clock, &pineview_display_wm,
3948 pineview_display_wm.fifo_size,
d4294342
ZY		 3949 pixel_size, latency->display_sr);
3950 reg = I915_READ(DSPFW1);
3951 reg &= ~DSPFW_SR_MASK;
3952 reg |= wm << DSPFW_SR_SHIFT;
3953 I915_WRITE(DSPFW1, reg);
3954 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3955
3956 /* cursor SR */
d210246a
CW		 3957 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3958 pineview_display_wm.fifo_size,
d4294342
ZY		 3959 pixel_size, latency->cursor_sr);
3960 reg = I915_READ(DSPFW3);
3961 reg &= ~DSPFW_CURSOR_SR_MASK;
3962 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3963 I915_WRITE(DSPFW3, reg);
3964
3965 /* Display HPLL off SR */
d210246a
CW		 3966 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3967 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3968 pixel_size, latency->display_hpll_disable);
3969 reg = I915_READ(DSPFW3);
3970 reg &= ~DSPFW_HPLL_SR_MASK;
3971 reg |= wm & DSPFW_HPLL_SR_MASK;
3972 I915_WRITE(DSPFW3, reg);
3973
3974 /* cursor HPLL off SR */
d210246a
CW		 3975 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3976 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3977 pixel_size, latency->cursor_hpll_disable);
3978 reg = I915_READ(DSPFW3);
3979 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3980 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3981 I915_WRITE(DSPFW3, reg);
3982 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3983
3984 /* activate cxsr */
3e33d94d
CW		 3985 I915_WRITE(DSPFW3,
3986 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY		 3987 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3988 } else {
3989 pineview_disable_cxsr(dev);
3990 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3991 }
3992}
3993
417ae147
CW		 3994static bool g4x_compute_wm0(struct drm_device *dev,
3995 int plane,
3996 const struct intel_watermark_params *display,
3997 int display_latency_ns,
3998 const struct intel_watermark_params *cursor,
3999 int cursor_latency_ns,
4000 int *plane_wm,
4001 int *cursor_wm)
4002{
4003 struct drm_crtc *crtc;
4004 int htotal, hdisplay, clock, pixel_size;
4005 int line_time_us, line_count;
4006 int entries, tlb_miss;
4007
4008 crtc = intel_get_crtc_for_plane(dev, plane);
5c72d064
CW		 4009 if (crtc->fb == NULL || !crtc->enabled) {
4010 *cursor_wm = cursor->guard_size;
4011 *plane_wm = display->guard_size;
417ae147 4012 return false;
5c72d064 4013 }
417ae147
CW		 4014
4015 htotal = crtc->mode.htotal;
4016 hdisplay = crtc->mode.hdisplay;
4017 clock = crtc->mode.clock;
4018 pixel_size = crtc->fb->bits_per_pixel / 8;
4019
4020 /* Use the small buffer method to calculate plane watermark */
4021 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4022 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4023 if (tlb_miss > 0)
4024 entries += tlb_miss;
4025 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4026 *plane_wm = entries + display->guard_size;
4027 if (*plane_wm > (int)display->max_wm)
4028 *plane_wm = display->max_wm;
4029
4030 /* Use the large buffer method to calculate cursor watermark */
4031 line_time_us = ((htotal * 1000) / clock);
4032 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4033 entries = line_count * 64 * pixel_size;
4034 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4035 if (tlb_miss > 0)
4036 entries += tlb_miss;
4037 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4038 *cursor_wm = entries + cursor->guard_size;
4039 if (*cursor_wm > (int)cursor->max_wm)
4040 *cursor_wm = (int)cursor->max_wm;
4041
4042 return true;
4043}
4044
4045/*
4046 * Check the wm result.
4047 *
4048 * If any calculated watermark values is larger than the maximum value that
4049 * can be programmed into the associated watermark register, that watermark
4050 * must be disabled.
4051 */
4052static bool g4x_check_srwm(struct drm_device *dev,
4053 int display_wm, int cursor_wm,
4054 const struct intel_watermark_params *display,
4055 const struct intel_watermark_params *cursor)
652c393a 4056{
417ae147
CW		 4057 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4058 display_wm, cursor_wm);
652c393a 4059
417ae147 4060 if (display_wm > display->max_wm) {
bbb0aef5 4061 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 4062 display_wm, display->max_wm);
4063 return false;
4064 }
0e442c60 4065
417ae147 4066 if (cursor_wm > cursor->max_wm) {
bbb0aef5 4067 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 4068 cursor_wm, cursor->max_wm);
4069 return false;
4070 }
0e442c60 4071
417ae147
CW		 4072 if (!(display_wm || cursor_wm)) {
4073 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4074 return false;
4075 }
0e442c60 4076
417ae147
CW		 4077 return true;
4078}
0e442c60 4079
417ae147 4080static bool g4x_compute_srwm(struct drm_device *dev,
d210246a
CW		 4081 int plane,
4082 int latency_ns,
417ae147
CW		 4083 const struct intel_watermark_params *display,
4084 const struct intel_watermark_params *cursor,
4085 int *display_wm, int *cursor_wm)
4086{
d210246a
CW		 4087 struct drm_crtc *crtc;
4088 int hdisplay, htotal, pixel_size, clock;
417ae147
CW		 4089 unsigned long line_time_us;
4090 int line_count, line_size;
4091 int small, large;
4092 int entries;
0e442c60 4093
417ae147
CW		 4094 if (!latency_ns) {
4095 *display_wm = *cursor_wm = 0;
4096 return false;
4097 }
0e442c60 4098
d210246a
CW		 4099 crtc = intel_get_crtc_for_plane(dev, plane);
4100 hdisplay = crtc->mode.hdisplay;
4101 htotal = crtc->mode.htotal;
4102 clock = crtc->mode.clock;
4103 pixel_size = crtc->fb->bits_per_pixel / 8;
4104
417ae147
CW		 4105 line_time_us = (htotal * 1000) / clock;
4106 line_count = (latency_ns / line_time_us + 1000) / 1000;
4107 line_size = hdisplay * pixel_size;
0e442c60 4108
417ae147
CW		 4109 /* Use the minimum of the small and large buffer method for primary */
4110 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4111 large = line_count * line_size;
0e442c60 4112
417ae147
CW		 4113 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4114 *display_wm = entries + display->guard_size;
4fe5e611 4115
417ae147
CW		 4116 /* calculate the self-refresh watermark for display cursor */
4117 entries = line_count * pixel_size * 64;
4118 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4119 *cursor_wm = entries + cursor->guard_size;
4fe5e611 4120
417ae147
CW		 4121 return g4x_check_srwm(dev,
4122 *display_wm, *cursor_wm,
4123 display, cursor);
4124}
4fe5e611 4125
7ccb4a53 4126#define single_plane_enabled(mask) is_power_of_2(mask)
d210246a
CW		 4127
4128static void g4x_update_wm(struct drm_device *dev)
417ae147
CW		 4129{
4130 static const int sr_latency_ns = 12000;
4131 struct drm_i915_private *dev_priv = dev->dev_private;
4132 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
d210246a
CW		 4133 int plane_sr, cursor_sr;
4134 unsigned int enabled = 0;
417ae147
CW		 4135
4136 if (g4x_compute_wm0(dev, 0,
4137 &g4x_wm_info, latency_ns,
4138 &g4x_cursor_wm_info, latency_ns,
4139 &planea_wm, &cursora_wm))
d210246a 4140 enabled |= 1;
417ae147
CW		 4141
4142 if (g4x_compute_wm0(dev, 1,
4143 &g4x_wm_info, latency_ns,
4144 &g4x_cursor_wm_info, latency_ns,
4145 &planeb_wm, &cursorb_wm))
d210246a 4146 enabled |= 2;
417ae147
CW		 4147
4148 plane_sr = cursor_sr = 0;
d210246a
CW		 4149 if (single_plane_enabled(enabled) &&
4150 g4x_compute_srwm(dev, ffs(enabled) - 1,
4151 sr_latency_ns,
417ae147
CW		 4152 &g4x_wm_info,
4153 &g4x_cursor_wm_info,
4154 &plane_sr, &cursor_sr))
0e442c60 4155 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
417ae147
CW		 4156 else
4157 I915_WRITE(FW_BLC_SELF,
4158 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
0e442c60 4159
308977ac
CW		 4160 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4161 planea_wm, cursora_wm,
4162 planeb_wm, cursorb_wm,
4163 plane_sr, cursor_sr);
0e442c60 4164
417ae147
CW		 4165 I915_WRITE(DSPFW1,
4166 (plane_sr << DSPFW_SR_SHIFT) |
0e442c60 4167 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
417ae147
CW		 4168 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4169 planea_wm);
4170 I915_WRITE(DSPFW2,
4171 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
0e442c60
JB		 4172 (cursora_wm << DSPFW_CURSORA_SHIFT));
4173 /* HPLL off in SR has some issues on G4x... disable it */
417ae147
CW		 4174 I915_WRITE(DSPFW3,
4175 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
0e442c60 4176 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB		 4177}
4178
d210246a 4179static void i965_update_wm(struct drm_device *dev)
7662c8bd
SL		 4180{
4181 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4182 struct drm_crtc *crtc;
4183 int srwm = 1;
4fe5e611 4184 int cursor_sr = 16;
1dc7546d
JB		 4185
4186 /* Calc sr entries for one plane configs */
d210246a
CW		 4187 crtc = single_enabled_crtc(dev);
4188 if (crtc) {
1dc7546d 4189 /* self-refresh has much higher latency */
69e302a9 4190 static const int sr_latency_ns = 12000;
d210246a
CW		 4191 int clock = crtc->mode.clock;
4192 int htotal = crtc->mode.htotal;
4193 int hdisplay = crtc->mode.hdisplay;
4194 int pixel_size = crtc->fb->bits_per_pixel / 8;
4195 unsigned long line_time_us;
4196 int entries;
1dc7546d 4197
d210246a 4198 line_time_us = ((htotal * 1000) / clock);
1dc7546d
JB		 4199
4200 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4201 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4202 pixel_size * hdisplay;
4203 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
d210246a 4204 srwm = I965_FIFO_SIZE - entries;
1dc7546d
JB		 4205 if (srwm < 0)
4206 srwm = 1;
1b07e04e 4207 srwm &= 0x1ff;
308977ac
CW		 4208 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4209 entries, srwm);
4fe5e611 4210
d210246a 4211 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 4212 pixel_size * 64;
d210246a 4213 entries = DIV_ROUND_UP(entries,
8de9b311 4214 i965_cursor_wm_info.cacheline_size);
4fe5e611 4215 cursor_sr = i965_cursor_wm_info.fifo_size -
d210246a 4216 (entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY		 4217
4218 if (cursor_sr > i965_cursor_wm_info.max_wm)
4219 cursor_sr = i965_cursor_wm_info.max_wm;
4220
4221 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4222 "cursor %d\n", srwm, cursor_sr);
4223
a6c45cf0 4224 if (IS_CRESTLINE(dev))
adcdbc66 4225 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ		 4226 } else {
4227 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 4228 if (IS_CRESTLINE(dev))
adcdbc66
JB		 4229 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4230 & ~FW_BLC_SELF_EN);
1dc7546d 4231 }
7662c8bd 4232
1dc7546d
JB		 4233 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4234 srwm);
7662c8bd
SL		 4235
4236 /* 965 has limitations... */
417ae147
CW		 4237 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4238 (8 << 16) | (8 << 8) | (8 << 0));
7662c8bd 4239 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY		 4240 /* update cursor SR watermark */
4241 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL		 4242}
4243
d210246a 4244static void i9xx_update_wm(struct drm_device *dev)
7662c8bd
SL		 4245{
4246 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 4247 const struct intel_watermark_params *wm_info;
dff33cfc
JB		 4248 uint32_t fwater_lo;
4249 uint32_t fwater_hi;
d210246a
CW		 4250 int cwm, srwm = 1;
4251 int fifo_size;
dff33cfc 4252 int planea_wm, planeb_wm;
d210246a 4253 struct drm_crtc *crtc, *enabled = NULL;
7662c8bd 4254
72557b4f 4255 if (IS_I945GM(dev))
d210246a 4256 wm_info = &i945_wm_info;
a6c45cf0 4257 else if (!IS_GEN2(dev))
d210246a 4258 wm_info = &i915_wm_info;
7662c8bd 4259 else
d210246a
CW		 4260 wm_info = &i855_wm_info;
4261
4262 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4263 crtc = intel_get_crtc_for_plane(dev, 0);
4264 if (crtc->enabled && crtc->fb) {
4265 planea_wm = intel_calculate_wm(crtc->mode.clock,
4266 wm_info, fifo_size,
4267 crtc->fb->bits_per_pixel / 8,
4268 latency_ns);
4269 enabled = crtc;
4270 } else
4271 planea_wm = fifo_size - wm_info->guard_size;
4272
4273 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4274 crtc = intel_get_crtc_for_plane(dev, 1);
4275 if (crtc->enabled && crtc->fb) {
4276 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4277 wm_info, fifo_size,
4278 crtc->fb->bits_per_pixel / 8,
4279 latency_ns);
4280 if (enabled == NULL)
4281 enabled = crtc;
4282 else
4283 enabled = NULL;
4284 } else
4285 planeb_wm = fifo_size - wm_info->guard_size;
7662c8bd 4286
28c97730 4287 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL		 4288
4289 /*
4290 * Overlay gets an aggressive default since video jitter is bad.
4291 */
4292 cwm = 2;
4293
18b2190c
AL		 4294 /* Play safe and disable self-refresh before adjusting watermarks. */
4295 if (IS_I945G(dev) || IS_I945GM(dev))
4296 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4297 else if (IS_I915GM(dev))
4298 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4299
dff33cfc 4300 /* Calc sr entries for one plane configs */
d210246a 4301 if (HAS_FW_BLC(dev) && enabled) {
dff33cfc 4302 /* self-refresh has much higher latency */
69e302a9 4303 static const int sr_latency_ns = 6000;
d210246a
CW		 4304 int clock = enabled->mode.clock;
4305 int htotal = enabled->mode.htotal;
4306 int hdisplay = enabled->mode.hdisplay;
4307 int pixel_size = enabled->fb->bits_per_pixel / 8;
4308 unsigned long line_time_us;
4309 int entries;
dff33cfc 4310
d210246a 4311 line_time_us = (htotal * 1000) / clock;
dff33cfc
JB		 4312
4313 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4314 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4315 pixel_size * hdisplay;
4316 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4317 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4318 srwm = wm_info->fifo_size - entries;
dff33cfc
JB		 4319 if (srwm < 0)
4320 srwm = 1;
ee980b80
LP		 4321
4322 if (IS_I945G(dev) || IS_I945GM(dev))
18b2190c
AL		 4323 I915_WRITE(FW_BLC_SELF,
4324 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4325 else if (IS_I915GM(dev))
ee980b80 4326 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
7662c8bd
SL		 4327 }
4328
28c97730 4329 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 4330 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 4331
dff33cfc
JB		 4332 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4333 fwater_hi = (cwm & 0x1f);
4334
4335 /* Set request length to 8 cachelines per fetch */
4336 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4337 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL		 4338
4339 I915_WRITE(FW_BLC, fwater_lo);
4340 I915_WRITE(FW_BLC2, fwater_hi);
18b2190c 4341
d210246a
CW		 4342 if (HAS_FW_BLC(dev)) {
4343 if (enabled) {
4344 if (IS_I945G(dev) || IS_I945GM(dev))
4345 I915_WRITE(FW_BLC_SELF,
4346 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4347 else if (IS_I915GM(dev))
4348 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4349 DRM_DEBUG_KMS("memory self refresh enabled\n");
4350 } else
4351 DRM_DEBUG_KMS("memory self refresh disabled\n");
4352 }
7662c8bd
SL		 4353}
4354
d210246a 4355static void i830_update_wm(struct drm_device *dev)
7662c8bd
SL		 4356{
4357 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4358 struct drm_crtc *crtc;
4359 uint32_t fwater_lo;
dff33cfc 4360 int planea_wm;
7662c8bd 4361
d210246a
CW		 4362 crtc = single_enabled_crtc(dev);
4363 if (crtc == NULL)
4364 return;
7662c8bd 4365
d210246a
CW		 4366 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4367 dev_priv->display.get_fifo_size(dev, 0),
4368 crtc->fb->bits_per_pixel / 8,
4369 latency_ns);
4370 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
f3601326
JB		 4371 fwater_lo |= (3<<8) | planea_wm;
4372
28c97730 4373 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL		 4374
4375 I915_WRITE(FW_BLC, fwater_lo);
4376}
4377
7f8a8569 4378#define ILK_LP0_PLANE_LATENCY 700
c936f44d 4379#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 4380
1398261a
YL		 4381/*
4382 * Check the wm result.
4383 *
4384 * If any calculated watermark values is larger than the maximum value that
4385 * can be programmed into the associated watermark register, that watermark
4386 * must be disabled.
1398261a 4387 */
b79d4990
JB		 4388static bool ironlake_check_srwm(struct drm_device *dev, int level,
4389 int fbc_wm, int display_wm, int cursor_wm,
4390 const struct intel_watermark_params *display,
4391 const struct intel_watermark_params *cursor)
1398261a
YL		 4392{
4393 struct drm_i915_private *dev_priv = dev->dev_private;
4394
4395 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4396 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4397
4398 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4399 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4400 fbc_wm, SNB_FBC_MAX_SRWM, level);
1398261a
YL		 4401
4402 /* fbc has it's own way to disable FBC WM */
4403 I915_WRITE(DISP_ARB_CTL,
4404 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4405 return false;
4406 }
4407
b79d4990 4408 if (display_wm > display->max_wm) {
1398261a 4409 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4410 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1398261a
YL		 4411 return false;
4412 }
4413
b79d4990 4414 if (cursor_wm > cursor->max_wm) {
1398261a 4415 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4416 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1398261a
YL		 4417 return false;
4418 }
4419
4420 if (!(fbc_wm || display_wm || cursor_wm)) {
4421 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4422 return false;
4423 }
4424
4425 return true;
4426}
4427
4428/*
4429 * Compute watermark values of WM[1-3],
4430 */
d210246a
CW		 4431static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4432 int latency_ns,
b79d4990
JB		 4433 const struct intel_watermark_params *display,
4434 const struct intel_watermark_params *cursor,
4435 int *fbc_wm, int *display_wm, int *cursor_wm)
1398261a 4436{
d210246a 4437 struct drm_crtc *crtc;
1398261a 4438 unsigned long line_time_us;
d210246a 4439 int hdisplay, htotal, pixel_size, clock;
b79d4990 4440 int line_count, line_size;
1398261a
YL		 4441 int small, large;
4442 int entries;
1398261a
YL		 4443
4444 if (!latency_ns) {
4445 *fbc_wm = *display_wm = *cursor_wm = 0;
4446 return false;
4447 }
4448
d210246a
CW		 4449 crtc = intel_get_crtc_for_plane(dev, plane);
4450 hdisplay = crtc->mode.hdisplay;
4451 htotal = crtc->mode.htotal;
4452 clock = crtc->mode.clock;
4453 pixel_size = crtc->fb->bits_per_pixel / 8;
4454
1398261a
YL		 4455 line_time_us = (htotal * 1000) / clock;
4456 line_count = (latency_ns / line_time_us + 1000) / 1000;
4457 line_size = hdisplay * pixel_size;
4458
4459 /* Use the minimum of the small and large buffer method for primary */
4460 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4461 large = line_count * line_size;
4462
b79d4990
JB		 4463 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4464 *display_wm = entries + display->guard_size;
1398261a
YL		 4465
4466 /*
b79d4990 4467 * Spec says:
1398261a
YL		 4468 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4469 */
4470 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4471
4472 /* calculate the self-refresh watermark for display cursor */
4473 entries = line_count * pixel_size * 64;
b79d4990
JB		 4474 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4475 *cursor_wm = entries + cursor->guard_size;
1398261a 4476
b79d4990
JB		 4477 return ironlake_check_srwm(dev, level,
4478 *fbc_wm, *display_wm, *cursor_wm,
4479 display, cursor);
4480}
4481
d210246a 4482static void ironlake_update_wm(struct drm_device *dev)
b79d4990
JB		 4483{
4484 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4485 int fbc_wm, plane_wm, cursor_wm;
4486 unsigned int enabled;
b79d4990
JB		 4487
4488 enabled = 0;
9f405100
CW		 4489 if (g4x_compute_wm0(dev, 0,
4490 &ironlake_display_wm_info,
4491 ILK_LP0_PLANE_LATENCY,
4492 &ironlake_cursor_wm_info,
4493 ILK_LP0_CURSOR_LATENCY,
4494 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4495 I915_WRITE(WM0_PIPEA_ILK,
4496 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4497 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4498 " plane %d, " "cursor: %d\n",
4499 plane_wm, cursor_wm);
d210246a 4500 enabled |= 1;
b79d4990
JB		 4501 }
4502
9f405100
CW		 4503 if (g4x_compute_wm0(dev, 1,
4504 &ironlake_display_wm_info,
4505 ILK_LP0_PLANE_LATENCY,
4506 &ironlake_cursor_wm_info,
4507 ILK_LP0_CURSOR_LATENCY,
4508 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4509 I915_WRITE(WM0_PIPEB_ILK,
4510 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4511 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4512 " plane %d, cursor: %d\n",
4513 plane_wm, cursor_wm);
d210246a 4514 enabled |= 2;
b79d4990
JB		 4515 }
4516
4517 /*
4518 * Calculate and update the self-refresh watermark only when one
4519 * display plane is used.
4520 */
4521 I915_WRITE(WM3_LP_ILK, 0);
4522 I915_WRITE(WM2_LP_ILK, 0);
4523 I915_WRITE(WM1_LP_ILK, 0);
4524
d210246a 4525 if (!single_plane_enabled(enabled))
b79d4990 4526 return;
d210246a 4527 enabled = ffs(enabled) - 1;
b79d4990
JB		 4528
4529 /* WM1 */
d210246a
CW		 4530 if (!ironlake_compute_srwm(dev, 1, enabled,
4531 ILK_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4532 &ironlake_display_srwm_info,
4533 &ironlake_cursor_srwm_info,
4534 &fbc_wm, &plane_wm, &cursor_wm))
4535 return;
4536
4537 I915_WRITE(WM1_LP_ILK,
4538 WM1_LP_SR_EN |
4539 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4540 (fbc_wm << WM1_LP_FBC_SHIFT) |
4541 (plane_wm << WM1_LP_SR_SHIFT) |
4542 cursor_wm);
4543
4544 /* WM2 */
d210246a
CW		 4545 if (!ironlake_compute_srwm(dev, 2, enabled,
4546 ILK_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4547 &ironlake_display_srwm_info,
4548 &ironlake_cursor_srwm_info,
4549 &fbc_wm, &plane_wm, &cursor_wm))
4550 return;
4551
4552 I915_WRITE(WM2_LP_ILK,
4553 WM2_LP_EN |
4554 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4555 (fbc_wm << WM1_LP_FBC_SHIFT) |
4556 (plane_wm << WM1_LP_SR_SHIFT) |
4557 cursor_wm);
4558
4559 /*
4560 * WM3 is unsupported on ILK, probably because we don't have latency
4561 * data for that power state
4562 */
1398261a
YL		 4563}
4564
b840d907 4565void sandybridge_update_wm(struct drm_device *dev)
1398261a
YL		 4566{
4567 struct drm_i915_private *dev_priv = dev->dev_private;
a0fa62d3 4568 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
47842649 4569 u32 val;
d210246a
CW		 4570 int fbc_wm, plane_wm, cursor_wm;
4571 unsigned int enabled;
1398261a
YL		 4572
4573 enabled = 0;
9f405100
CW		 4574 if (g4x_compute_wm0(dev, 0,
4575 &sandybridge_display_wm_info, latency,
4576 &sandybridge_cursor_wm_info, latency,
4577 &plane_wm, &cursor_wm)) {
47842649
JB		 4578 val = I915_READ(WM0_PIPEA_ILK);
4579 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4580 I915_WRITE(WM0_PIPEA_ILK, val |
4581 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1398261a
YL		 4582 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4583 " plane %d, " "cursor: %d\n",
4584 plane_wm, cursor_wm);
d210246a 4585 enabled |= 1;
1398261a
YL		 4586 }
4587
9f405100
CW		 4588 if (g4x_compute_wm0(dev, 1,
4589 &sandybridge_display_wm_info, latency,
4590 &sandybridge_cursor_wm_info, latency,
4591 &plane_wm, &cursor_wm)) {
47842649
JB		 4592 val = I915_READ(WM0_PIPEB_ILK);
4593 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4594 I915_WRITE(WM0_PIPEB_ILK, val |
4595 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1398261a
YL		 4596 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4597 " plane %d, cursor: %d\n",
4598 plane_wm, cursor_wm);
d210246a 4599 enabled |= 2;
1398261a
YL		 4600 }
4601
d6c892df
JB		 4602 /* IVB has 3 pipes */
4603 if (IS_IVYBRIDGE(dev) &&
4604 g4x_compute_wm0(dev, 2,
4605 &sandybridge_display_wm_info, latency,
4606 &sandybridge_cursor_wm_info, latency,
4607 &plane_wm, &cursor_wm)) {
47842649
JB		 4608 val = I915_READ(WM0_PIPEC_IVB);
4609 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4610 I915_WRITE(WM0_PIPEC_IVB, val |
4611 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
d6c892df
JB		 4612 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4613 " plane %d, cursor: %d\n",
4614 plane_wm, cursor_wm);
4615 enabled |= 3;
4616 }
4617
1398261a
YL		 4618 /*
4619 * Calculate and update the self-refresh watermark only when one
4620 * display plane is used.
4621 *
4622 * SNB support 3 levels of watermark.
4623 *
4624 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4625 * and disabled in the descending order
4626 *
4627 */
4628 I915_WRITE(WM3_LP_ILK, 0);
4629 I915_WRITE(WM2_LP_ILK, 0);
4630 I915_WRITE(WM1_LP_ILK, 0);
4631
b840d907
JB		 4632 if (!single_plane_enabled(enabled) ||
4633 dev_priv->sprite_scaling_enabled)
1398261a 4634 return;
d210246a 4635 enabled = ffs(enabled) - 1;
1398261a
YL		 4636
4637 /* WM1 */
d210246a
CW		 4638 if (!ironlake_compute_srwm(dev, 1, enabled,
4639 SNB_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4640 &sandybridge_display_srwm_info,
4641 &sandybridge_cursor_srwm_info,
4642 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4643 return;
4644
4645 I915_WRITE(WM1_LP_ILK,
4646 WM1_LP_SR_EN |
4647 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4648 (fbc_wm << WM1_LP_FBC_SHIFT) |
4649 (plane_wm << WM1_LP_SR_SHIFT) |
4650 cursor_wm);
4651
4652 /* WM2 */
d210246a
CW		 4653 if (!ironlake_compute_srwm(dev, 2, enabled,
4654 SNB_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4655 &sandybridge_display_srwm_info,
4656 &sandybridge_cursor_srwm_info,
4657 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4658 return;
4659
4660 I915_WRITE(WM2_LP_ILK,
4661 WM2_LP_EN |
4662 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4663 (fbc_wm << WM1_LP_FBC_SHIFT) |
4664 (plane_wm << WM1_LP_SR_SHIFT) |
4665 cursor_wm);
4666
4667 /* WM3 */
d210246a
CW		 4668 if (!ironlake_compute_srwm(dev, 3, enabled,
4669 SNB_READ_WM3_LATENCY() * 500,
b79d4990
JB		 4670 &sandybridge_display_srwm_info,
4671 &sandybridge_cursor_srwm_info,
4672 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4673 return;
4674
4675 I915_WRITE(WM3_LP_ILK,
4676 WM3_LP_EN |
4677 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4678 (fbc_wm << WM1_LP_FBC_SHIFT) |
4679 (plane_wm << WM1_LP_SR_SHIFT) |
4680 cursor_wm);
4681}
4682
b840d907
JB		 4683static bool
4684sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4685 uint32_t sprite_width, int pixel_size,
4686 const struct intel_watermark_params *display,
4687 int display_latency_ns, int *sprite_wm)
4688{
4689 struct drm_crtc *crtc;
4690 int clock;
4691 int entries, tlb_miss;
4692
4693 crtc = intel_get_crtc_for_plane(dev, plane);
4694 if (crtc->fb == NULL || !crtc->enabled) {
4695 *sprite_wm = display->guard_size;
4696 return false;
4697 }
4698
4699 clock = crtc->mode.clock;
4700
4701 /* Use the small buffer method to calculate the sprite watermark */
4702 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4703 tlb_miss = display->fifo_size*display->cacheline_size -
4704 sprite_width * 8;
4705 if (tlb_miss > 0)
4706 entries += tlb_miss;
4707 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4708 *sprite_wm = entries + display->guard_size;
4709 if (*sprite_wm > (int)display->max_wm)
4710 *sprite_wm = display->max_wm;
4711
4712 return true;
4713}
4714
4715static bool
4716sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4717 uint32_t sprite_width, int pixel_size,
4718 const struct intel_watermark_params *display,
4719 int latency_ns, int *sprite_wm)
4720{
4721 struct drm_crtc *crtc;
4722 unsigned long line_time_us;
4723 int clock;
4724 int line_count, line_size;
4725 int small, large;
4726 int entries;
4727
4728 if (!latency_ns) {
4729 *sprite_wm = 0;
4730 return false;
4731 }
4732
4733 crtc = intel_get_crtc_for_plane(dev, plane);
4734 clock = crtc->mode.clock;
4735
4736 line_time_us = (sprite_width * 1000) / clock;
4737 line_count = (latency_ns / line_time_us + 1000) / 1000;
4738 line_size = sprite_width * pixel_size;
4739
4740 /* Use the minimum of the small and large buffer method for primary */
4741 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4742 large = line_count * line_size;
4743
4744 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4745 *sprite_wm = entries + display->guard_size;
4746
4747 return *sprite_wm > 0x3ff ? false : true;
4748}
4749
4750static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4751 uint32_t sprite_width, int pixel_size)
4752{
4753 struct drm_i915_private *dev_priv = dev->dev_private;
4754 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
47842649 4755 u32 val;
b840d907
JB		 4756 int sprite_wm, reg;
4757 int ret;
4758
4759 switch (pipe) {
4760 case 0:
4761 reg = WM0_PIPEA_ILK;
4762 break;
4763 case 1:
4764 reg = WM0_PIPEB_ILK;
4765 break;
4766 case 2:
4767 reg = WM0_PIPEC_IVB;
4768 break;
4769 default:
4770 return; /* bad pipe */
4771 }
4772
4773 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4774 &sandybridge_display_wm_info,
4775 latency, &sprite_wm);
4776 if (!ret) {
4777 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4778 pipe);
4779 return;
4780 }
4781
47842649
JB		 4782 val = I915_READ(reg);
4783 val &= ~WM0_PIPE_SPRITE_MASK;
4784 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
b840d907
JB		 4785 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4786
4787
4788 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4789 pixel_size,
4790 &sandybridge_display_srwm_info,
4791 SNB_READ_WM1_LATENCY() * 500,
4792 &sprite_wm);
4793 if (!ret) {
4794 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4795 pipe);
4796 return;
4797 }
4798 I915_WRITE(WM1S_LP_ILK, sprite_wm);
4799
4800 /* Only IVB has two more LP watermarks for sprite */
4801 if (!IS_IVYBRIDGE(dev))
4802 return;
4803
4804 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4805 pixel_size,
4806 &sandybridge_display_srwm_info,
4807 SNB_READ_WM2_LATENCY() * 500,
4808 &sprite_wm);
4809 if (!ret) {
4810 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4811 pipe);
4812 return;
4813 }
4814 I915_WRITE(WM2S_LP_IVB, sprite_wm);
4815
4816 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4817 pixel_size,
4818 &sandybridge_display_srwm_info,
4819 SNB_READ_WM3_LATENCY() * 500,
4820 &sprite_wm);
4821 if (!ret) {
4822 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4823 pipe);
4824 return;
4825 }
4826 I915_WRITE(WM3S_LP_IVB, sprite_wm);
4827}
4828
7662c8bd
SL		 4829/**
4830 * intel_update_watermarks - update FIFO watermark values based on current modes
4831 *
4832 * Calculate watermark values for the various WM regs based on current mode
4833 * and plane configuration.
4834 *
4835 * There are several cases to deal with here:
4836 * - normal (i.e. non-self-refresh)
4837 * - self-refresh (SR) mode
4838 * - lines are large relative to FIFO size (buffer can hold up to 2)
4839 * - lines are small relative to FIFO size (buffer can hold more than 2
4840 * lines), so need to account for TLB latency
4841 *
4842 * The normal calculation is:
4843 * watermark = dotclock * bytes per pixel * latency
4844 * where latency is platform & configuration dependent (we assume pessimal
4845 * values here).
4846 *
4847 * The SR calculation is:
4848 * watermark = (trunc(latency/line time)+1) * surface width *
4849 * bytes per pixel
4850 * where
4851 * line time = htotal / dotclock
fa143215 4852 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL		 4853 * and latency is assumed to be high, as above.
4854 *
4855 * The final value programmed to the register should always be rounded up,
4856 * and include an extra 2 entries to account for clock crossings.
4857 *
4858 * We don't use the sprite, so we can ignore that. And on Crestline we have
4859 * to set the non-SR watermarks to 8.
5eddb70b 4860 */
7662c8bd
SL		 4861static void intel_update_watermarks(struct drm_device *dev)
4862{
e70236a8 4863 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 4864
d210246a
CW		 4865 if (dev_priv->display.update_wm)
4866 dev_priv->display.update_wm(dev);
7662c8bd
SL		 4867}
4868
b840d907
JB		 4869void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4870 uint32_t sprite_width, int pixel_size)
4871{
4872 struct drm_i915_private *dev_priv = dev->dev_private;
4873
4874 if (dev_priv->display.update_sprite_wm)
4875 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4876 pixel_size);
4877}
4878
a7615030
CW		 4879static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4880{
72bbe58c
KP		 4881 if (i915_panel_use_ssc >= 0)
4882 return i915_panel_use_ssc != 0;
4883 return dev_priv->lvds_use_ssc
435793df 4884 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4885}
4886
5a354204
JB		 4887/**
4888 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4889 * @crtc: CRTC structure
3b5c78a3 4890 * @mode: requested mode
5a354204
JB		 4891 *
4892 * A pipe may be connected to one or more outputs. Based on the depth of the
4893 * attached framebuffer, choose a good color depth to use on the pipe.
4894 *
4895 * If possible, match the pipe depth to the fb depth. In some cases, this
4896 * isn't ideal, because the connected output supports a lesser or restricted
4897 * set of depths. Resolve that here:
4898 * LVDS typically supports only 6bpc, so clamp down in that case
4899 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4900 * Displays may support a restricted set as well, check EDID and clamp as
4901 * appropriate.
3b5c78a3 4902 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4903 *
4904 * RETURNS:
4905 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4906 * true if they don't match).
4907 */
4908static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3b5c78a3
AJ		 4909 unsigned int *pipe_bpp,
4910 struct drm_display_mode *mode)
5a354204
JB		 4911{
4912 struct drm_device *dev = crtc->dev;
4913 struct drm_i915_private *dev_priv = dev->dev_private;
4914 struct drm_encoder *encoder;
4915 struct drm_connector *connector;
4916 unsigned int display_bpc = UINT_MAX, bpc;
4917
4918 /* Walk the encoders & connectors on this crtc, get min bpc */
4919 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4920 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4921
4922 if (encoder->crtc != crtc)
4923 continue;
4924
4925 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4926 unsigned int lvds_bpc;
4927
4928 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4929 LVDS_A3_POWER_UP)
4930 lvds_bpc = 8;
4931 else
4932 lvds_bpc = 6;
4933
4934 if (lvds_bpc < display_bpc) {
82820490 4935 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4936 display_bpc = lvds_bpc;
4937 }
4938 continue;
4939 }
4940
4941 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4942 /* Use VBT settings if we have an eDP panel */
4943 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4944
4945 if (edp_bpc < display_bpc) {
82820490 4946 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5a354204
JB		 4947 display_bpc = edp_bpc;
4948 }
4949 continue;
4950 }
4951
4952 /* Not one of the known troublemakers, check the EDID */
4953 list_for_each_entry(connector, &dev->mode_config.connector_list,
4954 head) {
4955 if (connector->encoder != encoder)
4956 continue;
4957
62ac41a6
JB		 4958 /* Don't use an invalid EDID bpc value */
4959 if (connector->display_info.bpc &&
4960 connector->display_info.bpc < display_bpc) {
82820490 4961 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4962 display_bpc = connector->display_info.bpc;
4963 }
4964 }
4965
4966 /*
4967 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4968 * through, clamp it down. (Note: >12bpc will be caught below.)
4969 */
4970 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4971 if (display_bpc > 8 && display_bpc < 12) {
82820490 4972 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4973 display_bpc = 12;
4974 } else {
82820490 4975 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4976 display_bpc = 8;
4977 }
4978 }
4979 }
4980
3b5c78a3
AJ		 4981 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4982 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4983 display_bpc = 6;
4984 }
4985
5a354204
JB		 4986 /*
4987 * We could just drive the pipe at the highest bpc all the time and
4988 * enable dithering as needed, but that costs bandwidth. So choose
4989 * the minimum value that expresses the full color range of the fb but
4990 * also stays within the max display bpc discovered above.
4991 */
4992
4993 switch (crtc->fb->depth) {
4994 case 8:
4995 bpc = 8; /* since we go through a colormap */
4996 break;
4997 case 15:
4998 case 16:
4999 bpc = 6; /* min is 18bpp */
5000 break;
5001 case 24:
578393cd 5002 bpc = 8;
5a354204
JB		 5003 break;
5004 case 30:
578393cd 5005 bpc = 10;
5a354204
JB		 5006 break;
5007 case 48:
578393cd 5008 bpc = 12;
5a354204
JB		 5009 break;
5010 default:
5011 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
5012 bpc = min((unsigned int)8, display_bpc);
5013 break;
5014 }
5015
578393cd
KP		 5016 display_bpc = min(display_bpc, bpc);
5017
82820490
AJ		 5018 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5019 bpc, display_bpc);
5a354204 5020
578393cd 5021 *pipe_bpp = display_bpc * 3;
5a354204
JB		 5022
5023 return display_bpc != bpc;
5024}
5025
c65d77d8
JB		 5026static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5027{
5028 struct drm_device *dev = crtc->dev;
5029 struct drm_i915_private *dev_priv = dev->dev_private;
5030 int refclk;
5031
5032 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5033 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5034 refclk = dev_priv->lvds_ssc_freq * 1000;
5035 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5036 refclk / 1000);
5037 } else if (!IS_GEN2(dev)) {
5038 refclk = 96000;
5039 } else {
5040 refclk = 48000;
5041 }
5042
5043 return refclk;
5044}
5045
5046static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5047 intel_clock_t *clock)
5048{
5049 /* SDVO TV has fixed PLL values depend on its clock range,
5050 this mirrors vbios setting. */
5051 if (adjusted_mode->clock >= 100000
5052 && adjusted_mode->clock < 140500) {
5053 clock->p1 = 2;
5054 clock->p2 = 10;
5055 clock->n = 3;
5056 clock->m1 = 16;
5057 clock->m2 = 8;
5058 } else if (adjusted_mode->clock >= 140500
5059 && adjusted_mode->clock <= 200000) {
5060 clock->p1 = 1;
5061 clock->p2 = 10;
5062 clock->n = 6;
5063 clock->m1 = 12;
5064 clock->m2 = 8;
5065 }
5066}
5067
a7516a05
JB		 5068static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5069 intel_clock_t *clock,
5070 intel_clock_t *reduced_clock)
5071{
5072 struct drm_device *dev = crtc->dev;
5073 struct drm_i915_private *dev_priv = dev->dev_private;
5074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5075 int pipe = intel_crtc->pipe;
5076 u32 fp, fp2 = 0;
5077
5078 if (IS_PINEVIEW(dev)) {
5079 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5080 if (reduced_clock)
5081 fp2 = (1 << reduced_clock->n) << 16 |
5082 reduced_clock->m1 << 8 | reduced_clock->m2;
5083 } else {
5084 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5085 if (reduced_clock)
5086 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5087 reduced_clock->m2;
5088 }
5089
5090 I915_WRITE(FP0(pipe), fp);
5091
5092 intel_crtc->lowfreq_avail = false;
5093 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5094 reduced_clock && i915_powersave) {
5095 I915_WRITE(FP1(pipe), fp2);
5096 intel_crtc->lowfreq_avail = true;
5097 } else {
5098 I915_WRITE(FP1(pipe), fp);
5099 }
5100}
5101
f564048e
EA		 5102static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5103 struct drm_display_mode *mode,
5104 struct drm_display_mode *adjusted_mode,
5105 int x, int y,
5106 struct drm_framebuffer *old_fb)
79e53945
JB		 5107{
5108 struct drm_device *dev = crtc->dev;
5109 struct drm_i915_private *dev_priv = dev->dev_private;
5110 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5111 int pipe = intel_crtc->pipe;
80824003 5112 int plane = intel_crtc->plane;
c751ce4f 5113 int refclk, num_connectors = 0;
652c393a 5114 intel_clock_t clock, reduced_clock;
0529a0d9 5115 u32 dpll, dspcntr, pipeconf, vsyncshift;
652c393a 5116 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
a4fc5ed6 5117 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 5118 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 5119 struct intel_encoder *encoder;
d4906093 5120 const intel_limit_t *limit;
5c3b82e2 5121 int ret;
fae14981 5122 u32 temp;
aa9b500d 5123 u32 lvds_sync = 0;
79e53945 5124
5eddb70b
CW		 5125 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5126 if (encoder->base.crtc != crtc)
79e53945
JB		 5127 continue;
5128
5eddb70b 5129 switch (encoder->type) {
79e53945
JB		 5130 case INTEL_OUTPUT_LVDS:
5131 is_lvds = true;
5132 break;
5133 case INTEL_OUTPUT_SDVO:
7d57382e 5134 case INTEL_OUTPUT_HDMI:
79e53945 5135 is_sdvo = true;
5eddb70b 5136 if (encoder->needs_tv_clock)
e2f0ba97 5137 is_tv = true;
79e53945
JB		 5138 break;
5139 case INTEL_OUTPUT_DVO:
5140 is_dvo = true;
5141 break;
5142 case INTEL_OUTPUT_TVOUT:
5143 is_tv = true;
5144 break;
5145 case INTEL_OUTPUT_ANALOG:
5146 is_crt = true;
5147 break;
a4fc5ed6
KP		 5148 case INTEL_OUTPUT_DISPLAYPORT:
5149 is_dp = true;
5150 break;
79e53945 5151 }
43565a06 5152
c751ce4f 5153 num_connectors++;
79e53945
JB		 5154 }
5155
c65d77d8 5156 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 5157
d4906093
ML		 5158 /*
5159 * Returns a set of divisors for the desired target clock with the given
5160 * refclk, or FALSE. The returned values represent the clock equation:
5161 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5162 */
1b894b59 5163 limit = intel_limit(crtc, refclk);
cec2f356
SP		 5164 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5165 &clock);
79e53945
JB		 5166 if (!ok) {
5167 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 5168 return -EINVAL;
79e53945
JB		 5169 }
5170
cda4b7d3 5171 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 5172 intel_crtc_update_cursor(crtc, true);
cda4b7d3 5173
ddc9003c 5174 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5175 /*
5176 * Ensure we match the reduced clock's P to the target clock.
5177 * If the clocks don't match, we can't switch the display clock
5178 * by using the FP0/FP1. In such case we will disable the LVDS
5179 * downclock feature.
5180 */
ddc9003c 5181 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 5182 dev_priv->lvds_downclock,
5183 refclk,
cec2f356 5184 &clock,
5eddb70b 5185 &reduced_clock);
652c393a 5186 }
c65d77d8
JB		 5187
5188 if (is_sdvo && is_tv)
5189 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 5190
a7516a05
JB		 5191 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5192 &reduced_clock : NULL);
79e53945 5193
929c77fb 5194 dpll = DPLL_VGA_MODE_DIS;
2c07245f 5195
a6c45cf0 5196 if (!IS_GEN2(dev)) {
79e53945
JB		 5197 if (is_lvds)
5198 dpll |= DPLLB_MODE_LVDS;
5199 else
5200 dpll |= DPLLB_MODE_DAC_SERIAL;
5201 if (is_sdvo) {
6c9547ff
CW		 5202 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5203 if (pixel_multiplier > 1) {
5204 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5205 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
6c9547ff 5206 }
79e53945 5207 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5208 }
929c77fb 5209 if (is_dp)
a4fc5ed6 5210 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945
JB		 5211
5212 /* compute bitmask from p1 value */
f2b115e6
AJ		 5213 if (IS_PINEVIEW(dev))
5214 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
2c07245f 5215 else {
2177832f 5216 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
652c393a
JB		 5217 if (IS_G4X(dev) && has_reduced_clock)
5218 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2c07245f 5219 }
79e53945
JB		 5220 switch (clock.p2) {
5221 case 5:
5222 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5223 break;
5224 case 7:
5225 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5226 break;
5227 case 10:
5228 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5229 break;
5230 case 14:
5231 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5232 break;
5233 }
929c77fb 5234 if (INTEL_INFO(dev)->gen >= 4)
79e53945
JB		 5235 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5236 } else {
5237 if (is_lvds) {
5238 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5239 } else {
5240 if (clock.p1 == 2)
5241 dpll |= PLL_P1_DIVIDE_BY_TWO;
5242 else
5243 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5244 if (clock.p2 == 4)
5245 dpll |= PLL_P2_DIVIDE_BY_4;
5246 }
5247 }
5248
43565a06
KH		 5249 if (is_sdvo && is_tv)
5250 dpll |= PLL_REF_INPUT_TVCLKINBC;
5251 else if (is_tv)
79e53945 5252 /* XXX: just matching BIOS for now */
43565a06 5253 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5254 dpll |= 3;
a7615030 5255 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5256 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5257 else
5258 dpll |= PLL_REF_INPUT_DREFCLK;
5259
5260 /* setup pipeconf */
5eddb70b 5261 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5262
5263 /* Set up the display plane register */
5264 dspcntr = DISPPLANE_GAMMA_ENABLE;
5265
929c77fb
EA		 5266 if (pipe == 0)
5267 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5268 else
5269 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 5270
a6c45cf0 5271 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 5272 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5273 * core speed.
5274 *
5275 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5276 * pipe == 0 check?
5277 */
e70236a8
JB		 5278 if (mode->clock >
5279 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 5280 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 5281 else
5eddb70b 5282 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 5283 }
5284
3b5c78a3
AJ		 5285 /* default to 8bpc */
5286 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5287 if (is_dp) {
5288 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5289 pipeconf |= PIPECONF_BPP_6 |
5290 PIPECONF_DITHER_EN |
5291 PIPECONF_DITHER_TYPE_SP;
5292 }
5293 }
5294
929c77fb 5295 dpll |= DPLL_VCO_ENABLE;
8d86dc6a 5296
28c97730 5297 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 5298 drm_mode_debug_printmodeline(mode);
5299
fae14981 5300 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 5301
fae14981 5302 POSTING_READ(DPLL(pipe));
c713bb08 5303 udelay(150);
8db9d77b 5304
79e53945
JB		 5305 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5306 * This is an exception to the general rule that mode_set doesn't turn
5307 * things on.
5308 */
5309 if (is_lvds) {
fae14981 5310 temp = I915_READ(LVDS);
5eddb70b 5311 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3 5312 if (pipe == 1) {
929c77fb 5313 temp |= LVDS_PIPEB_SELECT;
b3b095b3 5314 } else {
929c77fb 5315 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 5316 }
a3e17eb8 5317 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5318 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5319 /* Set the B0-B3 data pairs corresponding to whether we're going to
5320 * set the DPLLs for dual-channel mode or not.
5321 */
5322 if (clock.p2 == 7)
5eddb70b 5323 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5324 else
5eddb70b 5325 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5326
5327 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5328 * appropriately here, but we need to look more thoroughly into how
5329 * panels behave in the two modes.
5330 */
929c77fb
EA		 5331 /* set the dithering flag on LVDS as needed */
5332 if (INTEL_INFO(dev)->gen >= 4) {
434ed097 5333 if (dev_priv->lvds_dither)
5eddb70b 5334 temp |= LVDS_ENABLE_DITHER;
434ed097 5335 else
5eddb70b 5336 temp &= ~LVDS_ENABLE_DITHER;
898822ce 5337 }
aa9b500d
BF		 5338 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5339 lvds_sync |= LVDS_HSYNC_POLARITY;
5340 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5341 lvds_sync |= LVDS_VSYNC_POLARITY;
5342 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5343 != lvds_sync) {
5344 char flags[2] = "-+";
5345 DRM_INFO("Changing LVDS panel from "
5346 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5347 flags[!(temp & LVDS_HSYNC_POLARITY)],
5348 flags[!(temp & LVDS_VSYNC_POLARITY)],
5349 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5350 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5351 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5352 temp |= lvds_sync;
5353 }
fae14981 5354 I915_WRITE(LVDS, temp);
79e53945 5355 }
434ed097 5356
929c77fb 5357 if (is_dp) {
a4fc5ed6 5358 intel_dp_set_m_n(crtc, mode, adjusted_mode);
434ed097
JB		 5359 }
5360
fae14981 5361 I915_WRITE(DPLL(pipe), dpll);
5eddb70b 5362
c713bb08 5363 /* Wait for the clocks to stabilize. */
fae14981 5364 POSTING_READ(DPLL(pipe));
c713bb08 5365 udelay(150);
32f9d658 5366
c713bb08
EA		 5367 if (INTEL_INFO(dev)->gen >= 4) {
5368 temp = 0;
5369 if (is_sdvo) {
5370 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5371 if (temp > 1)
5372 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5373 else
5374 temp = 0;
32f9d658 5375 }
c713bb08
EA		 5376 I915_WRITE(DPLL_MD(pipe), temp);
5377 } else {
5378 /* The pixel multiplier can only be updated once the
5379 * DPLL is enabled and the clocks are stable.
5380 *
5381 * So write it again.
5382 */
fae14981 5383 I915_WRITE(DPLL(pipe), dpll);
79e53945 5384 }
79e53945 5385
a7516a05
JB		 5386 if (HAS_PIPE_CXSR(dev)) {
5387 if (intel_crtc->lowfreq_avail) {
28c97730 5388 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 5389 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 5390 } else {
28c97730 5391 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5392 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5393 }
5394 }
5395
617cf884 5396 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575
DV		 5397 if (!IS_GEN2(dev) &&
5398 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157
KH		 5399 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5400 /* the chip adds 2 halflines automatically */
734b4157 5401 adjusted_mode->crtc_vtotal -= 1;
734b4157 5402 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 5403 vsyncshift = adjusted_mode->crtc_hsync_start
5404 - adjusted_mode->crtc_htotal/2;
5405 } else {
617cf884 5406 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 5407 vsyncshift = 0;
5408 }
5409
5410 if (!IS_GEN3(dev))
5411 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
734b4157 5412
5eddb70b
CW		 5413 I915_WRITE(HTOTAL(pipe),
5414 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5415 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5416 I915_WRITE(HBLANK(pipe),
5417 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5418 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5419 I915_WRITE(HSYNC(pipe),
5420 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5421 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5422
5423 I915_WRITE(VTOTAL(pipe),
5424 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5425 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5426 I915_WRITE(VBLANK(pipe),
5427 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5428 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5429 I915_WRITE(VSYNC(pipe),
5430 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5431 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 5432
5433 /* pipesrc and dspsize control the size that is scaled from,
5434 * which should always be the user's requested size.
79e53945 5435 */
929c77fb
EA		 5436 I915_WRITE(DSPSIZE(plane),
5437 ((mode->vdisplay - 1) << 16) |
5438 (mode->hdisplay - 1));
5439 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 5440 I915_WRITE(PIPESRC(pipe),
5441 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5442
f564048e
EA		 5443 I915_WRITE(PIPECONF(pipe), pipeconf);
5444 POSTING_READ(PIPECONF(pipe));
929c77fb 5445 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 5446
5447 intel_wait_for_vblank(dev, pipe);
5448
f564048e
EA		 5449 I915_WRITE(DSPCNTR(plane), dspcntr);
5450 POSTING_READ(DSPCNTR(plane));
284d9529 5451 intel_enable_plane(dev_priv, plane, pipe);
f564048e
EA		 5452
5453 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5454
5455 intel_update_watermarks(dev);
5456
f564048e
EA		 5457 return ret;
5458}
5459
9fb526db
KP		 5460/*
5461 * Initialize reference clocks when the driver loads
5462 */
5463void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5464{
5465 struct drm_i915_private *dev_priv = dev->dev_private;
5466 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5467 struct intel_encoder *encoder;
13d83a67
JB		 5468 u32 temp;
5469 bool has_lvds = false;
199e5d79
KP		 5470 bool has_cpu_edp = false;
5471 bool has_pch_edp = false;
5472 bool has_panel = false;
99eb6a01
KP		 5473 bool has_ck505 = false;
5474 bool can_ssc = false;
13d83a67
JB		 5475
5476 /* We need to take the global config into account */
199e5d79
KP		 5477 list_for_each_entry(encoder, &mode_config->encoder_list,
5478 base.head) {
5479 switch (encoder->type) {
5480 case INTEL_OUTPUT_LVDS:
5481 has_panel = true;
5482 has_lvds = true;
5483 break;
5484 case INTEL_OUTPUT_EDP:
5485 has_panel = true;
5486 if (intel_encoder_is_pch_edp(&encoder->base))
5487 has_pch_edp = true;
5488 else
5489 has_cpu_edp = true;
5490 break;
13d83a67
JB		 5491 }
5492 }
5493
99eb6a01
KP		 5494 if (HAS_PCH_IBX(dev)) {
5495 has_ck505 = dev_priv->display_clock_mode;
5496 can_ssc = has_ck505;
5497 } else {
5498 has_ck505 = false;
5499 can_ssc = true;
5500 }
5501
5502 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5503 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5504 has_ck505);
13d83a67
JB		 5505
5506 /* Ironlake: try to setup display ref clock before DPLL
5507 * enabling. This is only under driver's control after
5508 * PCH B stepping, previous chipset stepping should be
5509 * ignoring this setting.
5510 */
5511 temp = I915_READ(PCH_DREF_CONTROL);
5512 /* Always enable nonspread source */
5513 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5514
99eb6a01
KP		 5515 if (has_ck505)
5516 temp |= DREF_NONSPREAD_CK505_ENABLE;
5517 else
5518 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5519
199e5d79
KP		 5520 if (has_panel) {
5521 temp &= ~DREF_SSC_SOURCE_MASK;
5522 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5523
199e5d79 5524 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5525 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5526 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 5527 temp |= DREF_SSC1_ENABLE;
13d83a67 5528 }
199e5d79
KP		 5529
5530 /* Get SSC going before enabling the outputs */
5531 I915_WRITE(PCH_DREF_CONTROL, temp);
5532 POSTING_READ(PCH_DREF_CONTROL);
5533 udelay(200);
5534
13d83a67
JB		 5535 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5536
5537 /* Enable CPU source on CPU attached eDP */
199e5d79 5538 if (has_cpu_edp) {
99eb6a01 5539 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5540 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 5541 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5542 }
13d83a67
JB		 5543 else
5544 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 5545 } else
5546 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5547
5548 I915_WRITE(PCH_DREF_CONTROL, temp);
5549 POSTING_READ(PCH_DREF_CONTROL);
5550 udelay(200);
5551 } else {
5552 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5553
5554 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5555
5556 /* Turn off CPU output */
5557 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5558
5559 I915_WRITE(PCH_DREF_CONTROL, temp);
5560 POSTING_READ(PCH_DREF_CONTROL);
5561 udelay(200);
5562
5563 /* Turn off the SSC source */
5564 temp &= ~DREF_SSC_SOURCE_MASK;
5565 temp |= DREF_SSC_SOURCE_DISABLE;
5566
5567 /* Turn off SSC1 */
5568 temp &= ~ DREF_SSC1_ENABLE;
5569
13d83a67
JB		 5570 I915_WRITE(PCH_DREF_CONTROL, temp);
5571 POSTING_READ(PCH_DREF_CONTROL);
5572 udelay(200);
5573 }
5574}
5575
d9d444cb
JB		 5576static int ironlake_get_refclk(struct drm_crtc *crtc)
5577{
5578 struct drm_device *dev = crtc->dev;
5579 struct drm_i915_private *dev_priv = dev->dev_private;
5580 struct intel_encoder *encoder;
5581 struct drm_mode_config *mode_config = &dev->mode_config;
5582 struct intel_encoder *edp_encoder = NULL;
5583 int num_connectors = 0;
5584 bool is_lvds = false;
5585
5586 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5587 if (encoder->base.crtc != crtc)
5588 continue;
5589
5590 switch (encoder->type) {
5591 case INTEL_OUTPUT_LVDS:
5592 is_lvds = true;
5593 break;
5594 case INTEL_OUTPUT_EDP:
5595 edp_encoder = encoder;
5596 break;
5597 }
5598 num_connectors++;
5599 }
5600
5601 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5602 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5603 dev_priv->lvds_ssc_freq);
5604 return dev_priv->lvds_ssc_freq * 1000;
5605 }
5606
5607 return 120000;
5608}
5609
f564048e
EA		 5610static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5611 struct drm_display_mode *mode,
5612 struct drm_display_mode *adjusted_mode,
5613 int x, int y,
5614 struct drm_framebuffer *old_fb)
79e53945
JB		 5615{
5616 struct drm_device *dev = crtc->dev;
5617 struct drm_i915_private *dev_priv = dev->dev_private;
5618 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5619 int pipe = intel_crtc->pipe;
80824003 5620 int plane = intel_crtc->plane;
c751ce4f 5621 int refclk, num_connectors = 0;
652c393a 5622 intel_clock_t clock, reduced_clock;
5eddb70b 5623 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 5624 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 5625 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
8e647a27 5626 struct intel_encoder *has_edp_encoder = NULL;
79e53945 5627 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 5628 struct intel_encoder *encoder;
d4906093 5629 const intel_limit_t *limit;
5c3b82e2 5630 int ret;
2c07245f 5631 struct fdi_m_n m_n = {0};
fae14981 5632 u32 temp;
aa9b500d 5633 u32 lvds_sync = 0;
5a354204
JB		 5634 int target_clock, pixel_multiplier, lane, link_bw, factor;
5635 unsigned int pipe_bpp;
5636 bool dither;
79e53945 5637
5eddb70b
CW		 5638 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5639 if (encoder->base.crtc != crtc)
79e53945
JB		 5640 continue;
5641
5eddb70b 5642 switch (encoder->type) {
79e53945
JB		 5643 case INTEL_OUTPUT_LVDS:
5644 is_lvds = true;
5645 break;
5646 case INTEL_OUTPUT_SDVO:
7d57382e 5647 case INTEL_OUTPUT_HDMI:
79e53945 5648 is_sdvo = true;
5eddb70b 5649 if (encoder->needs_tv_clock)
e2f0ba97 5650 is_tv = true;
79e53945 5651 break;
79e53945
JB		 5652 case INTEL_OUTPUT_TVOUT:
5653 is_tv = true;
5654 break;
5655 case INTEL_OUTPUT_ANALOG:
5656 is_crt = true;
5657 break;
a4fc5ed6
KP		 5658 case INTEL_OUTPUT_DISPLAYPORT:
5659 is_dp = true;
5660 break;
32f9d658 5661 case INTEL_OUTPUT_EDP:
5eddb70b 5662 has_edp_encoder = encoder;
32f9d658 5663 break;
79e53945 5664 }
43565a06 5665
c751ce4f 5666 num_connectors++;
79e53945
JB		 5667 }
5668
d9d444cb 5669 refclk = ironlake_get_refclk(crtc);
79e53945 5670
d4906093
ML		 5671 /*
5672 * Returns a set of divisors for the desired target clock with the given
5673 * refclk, or FALSE. The returned values represent the clock equation:
5674 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5675 */
1b894b59 5676 limit = intel_limit(crtc, refclk);
cec2f356
SP		 5677 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5678 &clock);
79e53945
JB		 5679 if (!ok) {
5680 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 5681 return -EINVAL;
79e53945
JB		 5682 }
5683
cda4b7d3 5684 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 5685 intel_crtc_update_cursor(crtc, true);
cda4b7d3 5686
ddc9003c 5687 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5688 /*
5689 * Ensure we match the reduced clock's P to the target clock.
5690 * If the clocks don't match, we can't switch the display clock
5691 * by using the FP0/FP1. In such case we will disable the LVDS
5692 * downclock feature.
5693 */
ddc9003c 5694 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 5695 dev_priv->lvds_downclock,
5696 refclk,
cec2f356 5697 &clock,
5eddb70b 5698 &reduced_clock);
652c393a 5699 }
7026d4ac
ZW		 5700 /* SDVO TV has fixed PLL values depend on its clock range,
5701 this mirrors vbios setting. */
5702 if (is_sdvo && is_tv) {
5703 if (adjusted_mode->clock >= 100000
5eddb70b 5704 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 5705 clock.p1 = 2;
5706 clock.p2 = 10;
5707 clock.n = 3;
5708 clock.m1 = 16;
5709 clock.m2 = 8;
5710 } else if (adjusted_mode->clock >= 140500
5eddb70b 5711 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 5712 clock.p1 = 1;
5713 clock.p2 = 10;
5714 clock.n = 6;
5715 clock.m1 = 12;
5716 clock.m2 = 8;
5717 }
5718 }
5719
2c07245f 5720 /* FDI link */
8febb297
EA		 5721 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5722 lane = 0;
5723 /* CPU eDP doesn't require FDI link, so just set DP M/N
5724 according to current link config */
5725 if (has_edp_encoder &&
5726 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5727 target_clock = mode->clock;
5728 intel_edp_link_config(has_edp_encoder,
5729 &lane, &link_bw);
5730 } else {
5731 /* [e]DP over FDI requires target mode clock
5732 instead of link clock */
5733 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5eb08b69 5734 target_clock = mode->clock;
8febb297
EA		 5735 else
5736 target_clock = adjusted_mode->clock;
5737
5738 /* FDI is a binary signal running at ~2.7GHz, encoding
5739 * each output octet as 10 bits. The actual frequency
5740 * is stored as a divider into a 100MHz clock, and the
5741 * mode pixel clock is stored in units of 1KHz.
5742 * Hence the bw of each lane in terms of the mode signal
5743 * is:
5744 */
5745 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5746 }
58a27471 5747
8febb297
EA		 5748 /* determine panel color depth */
5749 temp = I915_READ(PIPECONF(pipe));
5750 temp &= ~PIPE_BPC_MASK;
3b5c78a3 5751 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5a354204
JB		 5752 switch (pipe_bpp) {
5753 case 18:
5754 temp |= PIPE_6BPC;
8febb297 5755 break;
5a354204
JB		 5756 case 24:
5757 temp |= PIPE_8BPC;
8febb297 5758 break;
5a354204
JB		 5759 case 30:
5760 temp |= PIPE_10BPC;
8febb297 5761 break;
5a354204
JB		 5762 case 36:
5763 temp |= PIPE_12BPC;
8febb297
EA		 5764 break;
5765 default:
62ac41a6
JB		 5766 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5767 pipe_bpp);
5a354204
JB		 5768 temp |= PIPE_8BPC;
5769 pipe_bpp = 24;
5770 break;
8febb297 5771 }
77ffb597 5772
5a354204
JB		 5773 intel_crtc->bpp = pipe_bpp;
5774 I915_WRITE(PIPECONF(pipe), temp);
5775
8febb297
EA		 5776 if (!lane) {
5777 /*
5778 * Account for spread spectrum to avoid
5779 * oversubscribing the link. Max center spread
5780 * is 2.5%; use 5% for safety's sake.
5781 */
5a354204 5782 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 5783 lane = bps / (link_bw * 8) + 1;
5eb08b69 5784 }
2c07245f 5785
8febb297
EA		 5786 intel_crtc->fdi_lanes = lane;
5787
5788 if (pixel_multiplier > 1)
5789 link_bw *= pixel_multiplier;
5a354204
JB		 5790 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5791 &m_n);
8febb297 5792
a07d6787
EA		 5793 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5794 if (has_reduced_clock)
5795 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5796 reduced_clock.m2;
79e53945 5797
c1858123 5798 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5799 factor = 21;
5800 if (is_lvds) {
5801 if ((intel_panel_use_ssc(dev_priv) &&
5802 dev_priv->lvds_ssc_freq == 100) ||
5803 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5804 factor = 25;
5805 } else if (is_sdvo && is_tv)
5806 factor = 20;
c1858123 5807
cb0e0931 5808 if (clock.m < factor * clock.n)
8febb297 5809 fp |= FP_CB_TUNE;
2c07245f 5810
5eddb70b 5811 dpll = 0;
2c07245f 5812
a07d6787
EA		 5813 if (is_lvds)
5814 dpll |= DPLLB_MODE_LVDS;
5815 else
5816 dpll |= DPLLB_MODE_DAC_SERIAL;
5817 if (is_sdvo) {
5818 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5819 if (pixel_multiplier > 1) {
5820 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5821 }
a07d6787
EA		 5822 dpll |= DPLL_DVO_HIGH_SPEED;
5823 }
5824 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5825 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5826
a07d6787
EA		 5827 /* compute bitmask from p1 value */
5828 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5829 /* also FPA1 */
5830 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5831
5832 switch (clock.p2) {
5833 case 5:
5834 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5835 break;
5836 case 7:
5837 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5838 break;
5839 case 10:
5840 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5841 break;
5842 case 14:
5843 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5844 break;
79e53945
JB		 5845 }
5846
43565a06
KH		 5847 if (is_sdvo && is_tv)
5848 dpll |= PLL_REF_INPUT_TVCLKINBC;
5849 else if (is_tv)
79e53945 5850 /* XXX: just matching BIOS for now */
43565a06 5851 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5852 dpll |= 3;
a7615030 5853 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5854 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5855 else
5856 dpll |= PLL_REF_INPUT_DREFCLK;
5857
5858 /* setup pipeconf */
5eddb70b 5859 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5860
5861 /* Set up the display plane register */
5862 dspcntr = DISPPLANE_GAMMA_ENABLE;
5863
f7cb34d4 5864 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5865 drm_mode_debug_printmodeline(mode);
5866
5c5313c8 5867 /* PCH eDP needs FDI, but CPU eDP does not */
4b645f14
JB		 5868 if (!intel_crtc->no_pll) {
5869 if (!has_edp_encoder ||
5870 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5871 I915_WRITE(PCH_FP0(pipe), fp);
5872 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5873
5874 POSTING_READ(PCH_DPLL(pipe));
5875 udelay(150);
5876 }
5877 } else {
5878 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5879 fp == I915_READ(PCH_FP0(0))) {
5880 intel_crtc->use_pll_a = true;
5881 DRM_DEBUG_KMS("using pipe a dpll\n");
5882 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5883 fp == I915_READ(PCH_FP0(1))) {
5884 intel_crtc->use_pll_a = false;
5885 DRM_DEBUG_KMS("using pipe b dpll\n");
5886 } else {
5887 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5888 return -EINVAL;
5889 }
79e53945
JB		 5890 }
5891
5892 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5893 * This is an exception to the general rule that mode_set doesn't turn
5894 * things on.
5895 */
5896 if (is_lvds) {
fae14981 5897 temp = I915_READ(PCH_LVDS);
5eddb70b 5898 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 5899 if (HAS_PCH_CPT(dev)) {
5900 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 5901 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 5902 } else {
5903 if (pipe == 1)
5904 temp |= LVDS_PIPEB_SELECT;
5905 else
5906 temp &= ~LVDS_PIPEB_SELECT;
5907 }
4b645f14 5908
a3e17eb8 5909 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5910 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5911 /* Set the B0-B3 data pairs corresponding to whether we're going to
5912 * set the DPLLs for dual-channel mode or not.
5913 */
5914 if (clock.p2 == 7)
5eddb70b 5915 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5916 else
5eddb70b 5917 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5918
5919 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5920 * appropriately here, but we need to look more thoroughly into how
5921 * panels behave in the two modes.
5922 */
aa9b500d
BF		 5923 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5924 lvds_sync |= LVDS_HSYNC_POLARITY;
5925 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5926 lvds_sync |= LVDS_VSYNC_POLARITY;
5927 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5928 != lvds_sync) {
5929 char flags[2] = "-+";
5930 DRM_INFO("Changing LVDS panel from "
5931 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5932 flags[!(temp & LVDS_HSYNC_POLARITY)],
5933 flags[!(temp & LVDS_VSYNC_POLARITY)],
5934 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5935 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5936 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5937 temp |= lvds_sync;
5938 }
fae14981 5939 I915_WRITE(PCH_LVDS, temp);
79e53945 5940 }
434ed097 5941
8febb297
EA		 5942 pipeconf &= ~PIPECONF_DITHER_EN;
5943 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 5944 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 5945 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 5946 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 5947 }
5c5313c8 5948 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
a4fc5ed6 5949 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5950 } else {
8db9d77b 5951 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5952 I915_WRITE(TRANSDATA_M1(pipe), 0);
5953 I915_WRITE(TRANSDATA_N1(pipe), 0);
5954 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5955 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5956 }
79e53945 5957
4b645f14
JB		 5958 if (!intel_crtc->no_pll &&
5959 (!has_edp_encoder ||
5960 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
fae14981 5961 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 5962
32f9d658 5963 /* Wait for the clocks to stabilize. */
fae14981 5964 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 5965 udelay(150);
5966
8febb297
EA		 5967 /* The pixel multiplier can only be updated once the
5968 * DPLL is enabled and the clocks are stable.
5969 *
5970 * So write it again.
5971 */
fae14981 5972 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 5973 }
79e53945 5974
5eddb70b 5975 intel_crtc->lowfreq_avail = false;
4b645f14
JB		 5976 if (!intel_crtc->no_pll) {
5977 if (is_lvds && has_reduced_clock && i915_powersave) {
5978 I915_WRITE(PCH_FP1(pipe), fp2);
5979 intel_crtc->lowfreq_avail = true;
5980 if (HAS_PIPE_CXSR(dev)) {
5981 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5982 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5983 }
5984 } else {
5985 I915_WRITE(PCH_FP1(pipe), fp);
5986 if (HAS_PIPE_CXSR(dev)) {
5987 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5988 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5989 }
652c393a
JB		 5990 }
5991 }
5992
617cf884 5993 pipeconf &= ~PIPECONF_INTERLACE_MASK;
734b4157 5994 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5def474e 5995 pipeconf |= PIPECONF_INTERLACED_ILK;
734b4157 5996 /* the chip adds 2 halflines automatically */
734b4157 5997 adjusted_mode->crtc_vtotal -= 1;
734b4157 5998 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 5999 I915_WRITE(VSYNCSHIFT(pipe),
6000 adjusted_mode->crtc_hsync_start
6001 - adjusted_mode->crtc_htotal/2);
6002 } else {
617cf884 6003 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 6004 I915_WRITE(VSYNCSHIFT(pipe), 0);
6005 }
734b4157 6006
5eddb70b
CW		 6007 I915_WRITE(HTOTAL(pipe),
6008 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 6009 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 6010 I915_WRITE(HBLANK(pipe),
6011 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 6012 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 6013 I915_WRITE(HSYNC(pipe),
6014 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 6015 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 6016
6017 I915_WRITE(VTOTAL(pipe),
6018 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 6019 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 6020 I915_WRITE(VBLANK(pipe),
6021 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 6022 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 6023 I915_WRITE(VSYNC(pipe),
6024 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 6025 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 6026
8febb297
EA		 6027 /* pipesrc controls the size that is scaled from, which should
6028 * always be the user's requested size.
79e53945 6029 */
5eddb70b
CW		 6030 I915_WRITE(PIPESRC(pipe),
6031 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 6032
8febb297
EA		 6033 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
6034 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
6035 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
6036 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 6037
8febb297
EA		 6038 if (has_edp_encoder &&
6039 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6040 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f
ZW		 6041 }
6042
5eddb70b
CW		 6043 I915_WRITE(PIPECONF(pipe), pipeconf);
6044 POSTING_READ(PIPECONF(pipe));
79e53945 6045
9d0498a2 6046 intel_wait_for_vblank(dev, pipe);
79e53945 6047
5eddb70b 6048 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 6049 POSTING_READ(DSPCNTR(plane));
79e53945 6050
5c3b82e2 6051 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 6052
6053 intel_update_watermarks(dev);
6054
1f803ee5 6055 return ret;
79e53945
JB		 6056}
6057
f564048e
EA		 6058static int intel_crtc_mode_set(struct drm_crtc *crtc,
6059 struct drm_display_mode *mode,
6060 struct drm_display_mode *adjusted_mode,
6061 int x, int y,
6062 struct drm_framebuffer *old_fb)
6063{
6064 struct drm_device *dev = crtc->dev;
6065 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 6066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6067 int pipe = intel_crtc->pipe;
f564048e
EA		 6068 int ret;
6069
0b701d27 6070 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6071
f564048e
EA		 6072 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6073 x, y, old_fb);
79e53945 6074 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6075
d8e70a25
JB		 6076 if (ret)
6077 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6078 else
6079 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
120eced9 6080
1f803ee5 6081 return ret;
79e53945
JB		 6082}
6083
3a9627f4
WF		 6084static bool intel_eld_uptodate(struct drm_connector *connector,
6085 int reg_eldv, uint32_t bits_eldv,
6086 int reg_elda, uint32_t bits_elda,
6087 int reg_edid)
6088{
6089 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6090 uint8_t *eld = connector->eld;
6091 uint32_t i;
6092
6093 i = I915_READ(reg_eldv);
6094 i &= bits_eldv;
6095
6096 if (!eld[0])
6097 return !i;
6098
6099 if (!i)
6100 return false;
6101
6102 i = I915_READ(reg_elda);
6103 i &= ~bits_elda;
6104 I915_WRITE(reg_elda, i);
6105
6106 for (i = 0; i < eld[2]; i++)
6107 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6108 return false;
6109
6110 return true;
6111}
6112
e0dac65e
WF		 6113static void g4x_write_eld(struct drm_connector *connector,
6114 struct drm_crtc *crtc)
6115{
6116 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6117 uint8_t *eld = connector->eld;
6118 uint32_t eldv;
6119 uint32_t len;
6120 uint32_t i;
6121
6122 i = I915_READ(G4X_AUD_VID_DID);
6123
6124 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6125 eldv = G4X_ELDV_DEVCL_DEVBLC;
6126 else
6127 eldv = G4X_ELDV_DEVCTG;
6128
3a9627f4
WF		 6129 if (intel_eld_uptodate(connector,
6130 G4X_AUD_CNTL_ST, eldv,
6131 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6132 G4X_HDMIW_HDMIEDID))
6133 return;
6134
e0dac65e
WF		 6135 i = I915_READ(G4X_AUD_CNTL_ST);
6136 i &= ~(eldv | G4X_ELD_ADDR);
6137 len = (i >> 9) & 0x1f; /* ELD buffer size */
6138 I915_WRITE(G4X_AUD_CNTL_ST, i);
6139
6140 if (!eld[0])
6141 return;
6142
6143 len = min_t(uint8_t, eld[2], len);
6144 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6145 for (i = 0; i < len; i++)
6146 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6147
6148 i = I915_READ(G4X_AUD_CNTL_ST);
6149 i |= eldv;
6150 I915_WRITE(G4X_AUD_CNTL_ST, i);
6151}
6152
6153static void ironlake_write_eld(struct drm_connector *connector,
6154 struct drm_crtc *crtc)
6155{
6156 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6157 uint8_t *eld = connector->eld;
6158 uint32_t eldv;
6159 uint32_t i;
6160 int len;
6161 int hdmiw_hdmiedid;
b6daa025 6162 int aud_config;
e0dac65e
WF		 6163 int aud_cntl_st;
6164 int aud_cntrl_st2;
6165
b3f33cbf 6166 if (HAS_PCH_IBX(connector->dev)) {
1202b4c6 6167 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
b6daa025 6168 aud_config = IBX_AUD_CONFIG_A;
1202b4c6
WF		 6169 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6170 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6171 } else {
1202b4c6 6172 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
b6daa025 6173 aud_config = CPT_AUD_CONFIG_A;
1202b4c6
WF		 6174 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6175 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6176 }
6177
6178 i = to_intel_crtc(crtc)->pipe;
6179 hdmiw_hdmiedid += i * 0x100;
6180 aud_cntl_st += i * 0x100;
b6daa025 6181 aud_config += i * 0x100;
e0dac65e
WF		 6182
6183 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6184
6185 i = I915_READ(aud_cntl_st);
6186 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
6187 if (!i) {
6188 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6189 /* operate blindly on all ports */
1202b4c6
WF		 6190 eldv = IBX_ELD_VALIDB;
6191 eldv |= IBX_ELD_VALIDB << 4;
6192 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6193 } else {
6194 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6195 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6196 }
6197
3a9627f4
WF		 6198 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6199 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6200 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6201 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6202 } else
6203 I915_WRITE(aud_config, 0);
e0dac65e 6204
3a9627f4
WF		 6205 if (intel_eld_uptodate(connector,
6206 aud_cntrl_st2, eldv,
6207 aud_cntl_st, IBX_ELD_ADDRESS,
6208 hdmiw_hdmiedid))
6209 return;
6210
e0dac65e
WF		 6211 i = I915_READ(aud_cntrl_st2);
6212 i &= ~eldv;
6213 I915_WRITE(aud_cntrl_st2, i);
6214
6215 if (!eld[0])
6216 return;
6217
e0dac65e 6218 i = I915_READ(aud_cntl_st);
1202b4c6 6219 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6220 I915_WRITE(aud_cntl_st, i);
6221
6222 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6223 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6224 for (i = 0; i < len; i++)
6225 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6226
6227 i = I915_READ(aud_cntrl_st2);
6228 i |= eldv;
6229 I915_WRITE(aud_cntrl_st2, i);
6230}
6231
6232void intel_write_eld(struct drm_encoder *encoder,
6233 struct drm_display_mode *mode)
6234{
6235 struct drm_crtc *crtc = encoder->crtc;
6236 struct drm_connector *connector;
6237 struct drm_device *dev = encoder->dev;
6238 struct drm_i915_private *dev_priv = dev->dev_private;
6239
6240 connector = drm_select_eld(encoder, mode);
6241 if (!connector)
6242 return;
6243
6244 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6245 connector->base.id,
6246 drm_get_connector_name(connector),
6247 connector->encoder->base.id,
6248 drm_get_encoder_name(connector->encoder));
6249
6250 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6251
6252 if (dev_priv->display.write_eld)
6253 dev_priv->display.write_eld(connector, crtc);
6254}
6255
79e53945
JB		 6256/** Loads the palette/gamma unit for the CRTC with the prepared values */
6257void intel_crtc_load_lut(struct drm_crtc *crtc)
6258{
6259 struct drm_device *dev = crtc->dev;
6260 struct drm_i915_private *dev_priv = dev->dev_private;
6261 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6262 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6263 int i;
6264
6265 /* The clocks have to be on to load the palette. */
6266 if (!crtc->enabled)
6267 return;
6268
f2b115e6 6269 /* use legacy palette for Ironlake */
bad720ff 6270 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6271 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6272
79e53945
JB		 6273 for (i = 0; i < 256; i++) {
6274 I915_WRITE(palreg + 4 * i,
6275 (intel_crtc->lut_r[i] << 16) |
6276 (intel_crtc->lut_g[i] << 8) |
6277 intel_crtc->lut_b[i]);
6278 }
6279}
6280
560b85bb
CW		 6281static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6282{
6283 struct drm_device *dev = crtc->dev;
6284 struct drm_i915_private *dev_priv = dev->dev_private;
6285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6286 bool visible = base != 0;
6287 u32 cntl;
6288
6289 if (intel_crtc->cursor_visible == visible)
6290 return;
6291
9db4a9c7 6292 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6293 if (visible) {
6294 /* On these chipsets we can only modify the base whilst
6295 * the cursor is disabled.
6296 */
9db4a9c7 6297 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6298
6299 cntl &= ~(CURSOR_FORMAT_MASK);
6300 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6301 cntl |= CURSOR_ENABLE |
6302 CURSOR_GAMMA_ENABLE |
6303 CURSOR_FORMAT_ARGB;
6304 } else
6305 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6306 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6307
6308 intel_crtc->cursor_visible = visible;
6309}
6310
6311static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6312{
6313 struct drm_device *dev = crtc->dev;
6314 struct drm_i915_private *dev_priv = dev->dev_private;
6315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6316 int pipe = intel_crtc->pipe;
6317 bool visible = base != 0;
6318
6319 if (intel_crtc->cursor_visible != visible) {
548f245b 6320 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6321 if (base) {
6322 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6323 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6324 cntl |= pipe << 28; /* Connect to correct pipe */
6325 } else {
6326 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6327 cntl |= CURSOR_MODE_DISABLE;
6328 }
9db4a9c7 6329 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6330
6331 intel_crtc->cursor_visible = visible;
6332 }
6333 /* and commit changes on next vblank */
9db4a9c7 6334 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6335}
6336
65a21cd6
JB		 6337static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6338{
6339 struct drm_device *dev = crtc->dev;
6340 struct drm_i915_private *dev_priv = dev->dev_private;
6341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6342 int pipe = intel_crtc->pipe;
6343 bool visible = base != 0;
6344
6345 if (intel_crtc->cursor_visible != visible) {
6346 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6347 if (base) {
6348 cntl &= ~CURSOR_MODE;
6349 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6350 } else {
6351 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6352 cntl |= CURSOR_MODE_DISABLE;
6353 }
6354 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6355
6356 intel_crtc->cursor_visible = visible;
6357 }
6358 /* and commit changes on next vblank */
6359 I915_WRITE(CURBASE_IVB(pipe), base);
6360}
6361
cda4b7d3 6362/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6363static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6364 bool on)
cda4b7d3
CW		 6365{
6366 struct drm_device *dev = crtc->dev;
6367 struct drm_i915_private *dev_priv = dev->dev_private;
6368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6369 int pipe = intel_crtc->pipe;
6370 int x = intel_crtc->cursor_x;
6371 int y = intel_crtc->cursor_y;
560b85bb 6372 u32 base, pos;
cda4b7d3
CW		 6373 bool visible;
6374
6375 pos = 0;
6376
6b383a7f 6377 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6378 base = intel_crtc->cursor_addr;
6379 if (x > (int) crtc->fb->width)
6380 base = 0;
6381
6382 if (y > (int) crtc->fb->height)
6383 base = 0;
6384 } else
6385 base = 0;
6386
6387 if (x < 0) {
6388 if (x + intel_crtc->cursor_width < 0)
6389 base = 0;
6390
6391 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6392 x = -x;
6393 }
6394 pos |= x << CURSOR_X_SHIFT;
6395
6396 if (y < 0) {
6397 if (y + intel_crtc->cursor_height < 0)
6398 base = 0;
6399
6400 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6401 y = -y;
6402 }
6403 pos |= y << CURSOR_Y_SHIFT;
6404
6405 visible = base != 0;
560b85bb 6406 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6407 return;
6408
65a21cd6
JB		 6409 if (IS_IVYBRIDGE(dev)) {
6410 I915_WRITE(CURPOS_IVB(pipe), pos);
6411 ivb_update_cursor(crtc, base);
6412 } else {
6413 I915_WRITE(CURPOS(pipe), pos);
6414 if (IS_845G(dev) || IS_I865G(dev))
6415 i845_update_cursor(crtc, base);
6416 else
6417 i9xx_update_cursor(crtc, base);
6418 }
cda4b7d3
CW		 6419
6420 if (visible)
6421 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6422}
6423
79e53945 6424static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6425 struct drm_file *file,
79e53945
JB		 6426 uint32_t handle,
6427 uint32_t width, uint32_t height)
6428{
6429 struct drm_device *dev = crtc->dev;
6430 struct drm_i915_private *dev_priv = dev->dev_private;
6431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6432 struct drm_i915_gem_object *obj;
cda4b7d3 6433 uint32_t addr;
3f8bc370 6434 int ret;
79e53945 6435
28c97730 6436 DRM_DEBUG_KMS("\n");
79e53945
JB		 6437
6438 /* if we want to turn off the cursor ignore width and height */
6439 if (!handle) {
28c97730 6440 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6441 addr = 0;
05394f39 6442 obj = NULL;
5004417d 6443 mutex_lock(&dev->struct_mutex);
3f8bc370 6444 goto finish;
79e53945
JB		 6445 }
6446
6447 /* Currently we only support 64x64 cursors */
6448 if (width != 64 || height != 64) {
6449 DRM_ERROR("we currently only support 64x64 cursors\n");
6450 return -EINVAL;
6451 }
6452
05394f39 6453 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6454 if (&obj->base == NULL)
79e53945
JB		 6455 return -ENOENT;
6456
05394f39 6457 if (obj->base.size < width * height * 4) {
79e53945 6458 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6459 ret = -ENOMEM;
6460 goto fail;
79e53945
JB		 6461 }
6462
71acb5eb 6463 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6464 mutex_lock(&dev->struct_mutex);
b295d1b6 6465 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6466 if (obj->tiling_mode) {
6467 DRM_ERROR("cursor cannot be tiled\n");
6468 ret = -EINVAL;
6469 goto fail_locked;
6470 }
6471
2da3b9b9 6472 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6473 if (ret) {
6474 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6475 goto fail_locked;
e7b526bb
CW		 6476 }
6477
d9e86c0e
CW		 6478 ret = i915_gem_object_put_fence(obj);
6479 if (ret) {
2da3b9b9 6480 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6481 goto fail_unpin;
6482 }
6483
05394f39 6484 addr = obj->gtt_offset;
71acb5eb 6485 } else {
6eeefaf3 6486 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6487 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6488 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6489 align);
71acb5eb
DA		 6490 if (ret) {
6491 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6492 goto fail_locked;
71acb5eb 6493 }
05394f39 6494 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6495 }
6496
a6c45cf0 6497 if (IS_GEN2(dev))
14b60391
JB		 6498 I915_WRITE(CURSIZE, (height << 12) | width);
6499
3f8bc370 6500 finish:
3f8bc370 6501 if (intel_crtc->cursor_bo) {
b295d1b6 6502 if (dev_priv->info->cursor_needs_physical) {
05394f39 6503 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6504 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6505 } else
6506 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6507 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6508 }
80824003 6509
7f9872e0 6510 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6511
6512 intel_crtc->cursor_addr = addr;
05394f39 6513 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6514 intel_crtc->cursor_width = width;
6515 intel_crtc->cursor_height = height;
6516
6b383a7f 6517 intel_crtc_update_cursor(crtc, true);
3f8bc370 6518
79e53945 6519 return 0;
e7b526bb 6520fail_unpin:
05394f39 6521 i915_gem_object_unpin(obj);
7f9872e0 6522fail_locked:
34b8686e 6523 mutex_unlock(&dev->struct_mutex);
bc9025bd 6524fail:
05394f39 6525 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6526 return ret;
79e53945
JB		 6527}
6528
6529static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6530{
79e53945 6531 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6532
cda4b7d3
CW		 6533 intel_crtc->cursor_x = x;
6534 intel_crtc->cursor_y = y;
652c393a 6535
6b383a7f 6536 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6537
6538 return 0;
6539}
6540
6541/** Sets the color ramps on behalf of RandR */
6542void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6543 u16 blue, int regno)
6544{
6545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6546
6547 intel_crtc->lut_r[regno] = red >> 8;
6548 intel_crtc->lut_g[regno] = green >> 8;
6549 intel_crtc->lut_b[regno] = blue >> 8;
6550}
6551
b8c00ac5
DA		 6552void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6553 u16 *blue, int regno)
6554{
6555 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6556
6557 *red = intel_crtc->lut_r[regno] << 8;
6558 *green = intel_crtc->lut_g[regno] << 8;
6559 *blue = intel_crtc->lut_b[regno] << 8;
6560}
6561
79e53945 6562static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6563 u16 *blue, uint32_t start, uint32_t size)
79e53945 6564{
7203425a 6565 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6566 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6567
7203425a 6568 for (i = start; i < end; i++) {
79e53945
JB		 6569 intel_crtc->lut_r[i] = red[i] >> 8;
6570 intel_crtc->lut_g[i] = green[i] >> 8;
6571 intel_crtc->lut_b[i] = blue[i] >> 8;
6572 }
6573
6574 intel_crtc_load_lut(crtc);
6575}
6576
6577/**
6578 * Get a pipe with a simple mode set on it for doing load-based monitor
6579 * detection.
6580 *
6581 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6582 * its requirements. The pipe will be connected to no other encoders.
79e53945 6583 *
c751ce4f 6584 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6585 * configured for it. In the future, it could choose to temporarily disable
6586 * some outputs to free up a pipe for its use.
6587 *
6588 * \return crtc, or NULL if no pipes are available.
6589 */
6590
6591/* VESA 640x480x72Hz mode to set on the pipe */
6592static struct drm_display_mode load_detect_mode = {
6593 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6594 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6595};
6596
d2dff872
CW		 6597static struct drm_framebuffer *
6598intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6599 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6600 struct drm_i915_gem_object *obj)
6601{
6602 struct intel_framebuffer *intel_fb;
6603 int ret;
6604
6605 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6606 if (!intel_fb) {
6607 drm_gem_object_unreference_unlocked(&obj->base);
6608 return ERR_PTR(-ENOMEM);
6609 }
6610
6611 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6612 if (ret) {
6613 drm_gem_object_unreference_unlocked(&obj->base);
6614 kfree(intel_fb);
6615 return ERR_PTR(ret);
6616 }
6617
6618 return &intel_fb->base;
6619}
6620
6621static u32
6622intel_framebuffer_pitch_for_width(int width, int bpp)
6623{
6624 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6625 return ALIGN(pitch, 64);
6626}
6627
6628static u32
6629intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6630{
6631 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6632 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6633}
6634
6635static struct drm_framebuffer *
6636intel_framebuffer_create_for_mode(struct drm_device *dev,
6637 struct drm_display_mode *mode,
6638 int depth, int bpp)
6639{
6640 struct drm_i915_gem_object *obj;
308e5bcb 6641 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 6642
6643 obj = i915_gem_alloc_object(dev,
6644 intel_framebuffer_size_for_mode(mode, bpp));
6645 if (obj == NULL)
6646 return ERR_PTR(-ENOMEM);
6647
6648 mode_cmd.width = mode->hdisplay;
6649 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6650 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6651 bpp);
6652 mode_cmd.pixel_format = 0;
d2dff872
CW		 6653
6654 return intel_framebuffer_create(dev, &mode_cmd, obj);
6655}
6656
6657static struct drm_framebuffer *
6658mode_fits_in_fbdev(struct drm_device *dev,
6659 struct drm_display_mode *mode)
6660{
6661 struct drm_i915_private *dev_priv = dev->dev_private;
6662 struct drm_i915_gem_object *obj;
6663 struct drm_framebuffer *fb;
6664
6665 if (dev_priv->fbdev == NULL)
6666 return NULL;
6667
6668 obj = dev_priv->fbdev->ifb.obj;
6669 if (obj == NULL)
6670 return NULL;
6671
6672 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6673 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6674 fb->bits_per_pixel))
d2dff872
CW		 6675 return NULL;
6676
01f2c773 6677 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6678 return NULL;
6679
6680 return fb;
6681}
6682
7173188d
CW		 6683bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6684 struct drm_connector *connector,
6685 struct drm_display_mode *mode,
8261b191 6686 struct intel_load_detect_pipe *old)
79e53945
JB		 6687{
6688 struct intel_crtc *intel_crtc;
6689 struct drm_crtc *possible_crtc;
4ef69c7a 6690 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6691 struct drm_crtc *crtc = NULL;
6692 struct drm_device *dev = encoder->dev;
d2dff872 6693 struct drm_framebuffer *old_fb;
79e53945
JB		 6694 int i = -1;
6695
d2dff872
CW		 6696 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6697 connector->base.id, drm_get_connector_name(connector),
6698 encoder->base.id, drm_get_encoder_name(encoder));
6699
79e53945
JB		 6700 /*
6701 * Algorithm gets a little messy:
7a5e4805 6702 *
79e53945
JB		 6703 * - if the connector already has an assigned crtc, use it (but make
6704 * sure it's on first)
7a5e4805 6705 *
79e53945
JB		 6706 * - try to find the first unused crtc that can drive this connector,
6707 * and use that if we find one
79e53945
JB		 6708 */
6709
6710 /* See if we already have a CRTC for this connector */
6711 if (encoder->crtc) {
6712 crtc = encoder->crtc;
8261b191 6713
79e53945 6714 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6715 old->dpms_mode = intel_crtc->dpms_mode;
6716 old->load_detect_temp = false;
6717
6718 /* Make sure the crtc and connector are running */
79e53945 6719 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 6720 struct drm_encoder_helper_funcs *encoder_funcs;
6721 struct drm_crtc_helper_funcs *crtc_funcs;
6722
79e53945
JB		 6723 crtc_funcs = crtc->helper_private;
6724 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 6725
6726 encoder_funcs = encoder->helper_private;
79e53945
JB		 6727 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6728 }
8261b191 6729
7173188d 6730 return true;
79e53945
JB		 6731 }
6732
6733 /* Find an unused one (if possible) */
6734 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6735 i++;
6736 if (!(encoder->possible_crtcs & (1 << i)))
6737 continue;
6738 if (!possible_crtc->enabled) {
6739 crtc = possible_crtc;
6740 break;
6741 }
79e53945
JB		 6742 }
6743
6744 /*
6745 * If we didn't find an unused CRTC, don't use any.
6746 */
6747 if (!crtc) {
7173188d
CW		 6748 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6749 return false;
79e53945
JB		 6750 }
6751
6752 encoder->crtc = crtc;
c1c43977 6753 connector->encoder = encoder;
79e53945
JB		 6754
6755 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6756 old->dpms_mode = intel_crtc->dpms_mode;
6757 old->load_detect_temp = true;
d2dff872 6758 old->release_fb = NULL;
79e53945 6759
6492711d
CW		 6760 if (!mode)
6761 mode = &load_detect_mode;
79e53945 6762
d2dff872
CW		 6763 old_fb = crtc->fb;
6764
6765 /* We need a framebuffer large enough to accommodate all accesses
6766 * that the plane may generate whilst we perform load detection.
6767 * We can not rely on the fbcon either being present (we get called
6768 * during its initialisation to detect all boot displays, or it may
6769 * not even exist) or that it is large enough to satisfy the
6770 * requested mode.
6771 */
6772 crtc->fb = mode_fits_in_fbdev(dev, mode);
6773 if (crtc->fb == NULL) {
6774 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6775 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6776 old->release_fb = crtc->fb;
6777 } else
6778 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6779 if (IS_ERR(crtc->fb)) {
6780 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6781 crtc->fb = old_fb;
6782 return false;
79e53945 6783 }
79e53945 6784
d2dff872 6785 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 6786 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6787 if (old->release_fb)
6788 old->release_fb->funcs->destroy(old->release_fb);
6789 crtc->fb = old_fb;
6492711d 6790 return false;
79e53945 6791 }
7173188d 6792
79e53945 6793 /* let the connector get through one full cycle before testing */
9d0498a2 6794 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6795
7173188d 6796 return true;
79e53945
JB		 6797}
6798
c1c43977 6799void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 6800 struct drm_connector *connector,
6801 struct intel_load_detect_pipe *old)
79e53945 6802{
4ef69c7a 6803 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6804 struct drm_device *dev = encoder->dev;
6805 struct drm_crtc *crtc = encoder->crtc;
6806 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6807 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6808
d2dff872
CW		 6809 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6810 connector->base.id, drm_get_connector_name(connector),
6811 encoder->base.id, drm_get_encoder_name(encoder));
6812
8261b191 6813 if (old->load_detect_temp) {
c1c43977 6814 connector->encoder = NULL;
79e53945 6815 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 6816
6817 if (old->release_fb)
6818 old->release_fb->funcs->destroy(old->release_fb);
6819
0622a53c 6820 return;
79e53945
JB		 6821 }
6822
c751ce4f 6823 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 6824 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6825 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 6826 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 6827 }
6828}
6829
6830/* Returns the clock of the currently programmed mode of the given pipe. */
6831static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6832{
6833 struct drm_i915_private *dev_priv = dev->dev_private;
6834 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6835 int pipe = intel_crtc->pipe;
548f245b 6836 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6837 u32 fp;
6838 intel_clock_t clock;
6839
6840 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6841 fp = I915_READ(FP0(pipe));
79e53945 6842 else
39adb7a5 6843 fp = I915_READ(FP1(pipe));
79e53945
JB		 6844
6845 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6846 if (IS_PINEVIEW(dev)) {
6847 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6848 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6849 } else {
6850 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6851 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6852 }
6853
a6c45cf0 6854 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6855 if (IS_PINEVIEW(dev))
6856 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6857 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6858 else
6859 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6860 DPLL_FPA01_P1_POST_DIV_SHIFT);
6861
6862 switch (dpll & DPLL_MODE_MASK) {
6863 case DPLLB_MODE_DAC_SERIAL:
6864 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6865 5 : 10;
6866 break;
6867 case DPLLB_MODE_LVDS:
6868 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6869 7 : 14;
6870 break;
6871 default:
28c97730 6872 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6873 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6874 return 0;
6875 }
6876
6877 /* XXX: Handle the 100Mhz refclk */
2177832f 6878 intel_clock(dev, 96000, &clock);
79e53945
JB		 6879 } else {
6880 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6881
6882 if (is_lvds) {
6883 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6884 DPLL_FPA01_P1_POST_DIV_SHIFT);
6885 clock.p2 = 14;
6886
6887 if ((dpll & PLL_REF_INPUT_MASK) ==
6888 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6889 /* XXX: might not be 66MHz */
2177832f 6890 intel_clock(dev, 66000, &clock);
79e53945 6891 } else
2177832f 6892 intel_clock(dev, 48000, &clock);
79e53945
JB		 6893 } else {
6894 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6895 clock.p1 = 2;
6896 else {
6897 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6898 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6899 }
6900 if (dpll & PLL_P2_DIVIDE_BY_4)
6901 clock.p2 = 4;
6902 else
6903 clock.p2 = 2;
6904
2177832f 6905 intel_clock(dev, 48000, &clock);
79e53945
JB		 6906 }
6907 }
6908
6909 /* XXX: It would be nice to validate the clocks, but we can't reuse
6910 * i830PllIsValid() because it relies on the xf86_config connector
6911 * configuration being accurate, which it isn't necessarily.
6912 */
6913
6914 return clock.dot;
6915}
6916
6917/** Returns the currently programmed mode of the given pipe. */
6918struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6919 struct drm_crtc *crtc)
6920{
548f245b 6921 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 6922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6923 int pipe = intel_crtc->pipe;
6924 struct drm_display_mode *mode;
548f245b
JB		 6925 int htot = I915_READ(HTOTAL(pipe));
6926 int hsync = I915_READ(HSYNC(pipe));
6927 int vtot = I915_READ(VTOTAL(pipe));
6928 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 6929
6930 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6931 if (!mode)
6932 return NULL;
6933
6934 mode->clock = intel_crtc_clock_get(dev, crtc);
6935 mode->hdisplay = (htot & 0xffff) + 1;
6936 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6937 mode->hsync_start = (hsync & 0xffff) + 1;
6938 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6939 mode->vdisplay = (vtot & 0xffff) + 1;
6940 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6941 mode->vsync_start = (vsync & 0xffff) + 1;
6942 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6943
6944 drm_mode_set_name(mode);
6945 drm_mode_set_crtcinfo(mode, 0);
6946
6947 return mode;
6948}
6949
652c393a
JB		 6950#define GPU_IDLE_TIMEOUT 500 /* ms */
6951
6952/* When this timer fires, we've been idle for awhile */
6953static void intel_gpu_idle_timer(unsigned long arg)
6954{
6955 struct drm_device *dev = (struct drm_device *)arg;
6956 drm_i915_private_t *dev_priv = dev->dev_private;
6957
ff7ea4c0
CW		 6958 if (!list_empty(&dev_priv->mm.active_list)) {
6959 /* Still processing requests, so just re-arm the timer. */
6960 mod_timer(&dev_priv->idle_timer, jiffies +
6961 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6962 return;
6963 }
652c393a 6964
ff7ea4c0 6965 dev_priv->busy = false;
01dfba93 6966 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6967}
6968
652c393a
JB		 6969#define CRTC_IDLE_TIMEOUT 1000 /* ms */
6970
6971static void intel_crtc_idle_timer(unsigned long arg)
6972{
6973 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6974 struct drm_crtc *crtc = &intel_crtc->base;
6975 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 6976 struct intel_framebuffer *intel_fb;
652c393a 6977
ff7ea4c0
CW		 6978 intel_fb = to_intel_framebuffer(crtc->fb);
6979 if (intel_fb && intel_fb->obj->active) {
6980 /* The framebuffer is still being accessed by the GPU. */
6981 mod_timer(&intel_crtc->idle_timer, jiffies +
6982 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6983 return;
6984 }
652c393a 6985
ff7ea4c0 6986 intel_crtc->busy = false;
01dfba93 6987 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6988}
6989
3dec0095 6990static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6991{
6992 struct drm_device *dev = crtc->dev;
6993 drm_i915_private_t *dev_priv = dev->dev_private;
6994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6995 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6996 int dpll_reg = DPLL(pipe);
6997 int dpll;
652c393a 6998
bad720ff 6999 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7000 return;
7001
7002 if (!dev_priv->lvds_downclock_avail)
7003 return;
7004
dbdc6479 7005 dpll = I915_READ(dpll_reg);
652c393a 7006 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7007 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7008
8ac5a6d5 7009 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7010
7011 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7012 I915_WRITE(dpll_reg, dpll);
9d0498a2 7013 intel_wait_for_vblank(dev, pipe);
dbdc6479 7014
652c393a
JB		 7015 dpll = I915_READ(dpll_reg);
7016 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7017 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 7018 }
7019
7020 /* Schedule downclock */
3dec0095
DV		 7021 mod_timer(&intel_crtc->idle_timer, jiffies +
7022 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 7023}
7024
7025static void intel_decrease_pllclock(struct drm_crtc *crtc)
7026{
7027 struct drm_device *dev = crtc->dev;
7028 drm_i915_private_t *dev_priv = dev->dev_private;
7029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7030 int pipe = intel_crtc->pipe;
9db4a9c7 7031 int dpll_reg = DPLL(pipe);
652c393a
JB		 7032 int dpll = I915_READ(dpll_reg);
7033
bad720ff 7034 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7035 return;
7036
7037 if (!dev_priv->lvds_downclock_avail)
7038 return;
7039
7040 /*
7041 * Since this is called by a timer, we should never get here in
7042 * the manual case.
7043 */
7044 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 7045 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7046
8ac5a6d5 7047 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7048
7049 dpll |= DISPLAY_RATE_SELECT_FPA1;
7050 I915_WRITE(dpll_reg, dpll);
9d0498a2 7051 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7052 dpll = I915_READ(dpll_reg);
7053 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7054 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7055 }
7056
7057}
7058
7059/**
7060 * intel_idle_update - adjust clocks for idleness
7061 * @work: work struct
7062 *
7063 * Either the GPU or display (or both) went idle. Check the busy status
7064 * here and adjust the CRTC and GPU clocks as necessary.
7065 */
7066static void intel_idle_update(struct work_struct *work)
7067{
7068 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
7069 idle_work);
7070 struct drm_device *dev = dev_priv->dev;
7071 struct drm_crtc *crtc;
7072 struct intel_crtc *intel_crtc;
7073
7074 if (!i915_powersave)
7075 return;
7076
7077 mutex_lock(&dev->struct_mutex);
7078
7648fa99
JB		 7079 i915_update_gfx_val(dev_priv);
7080
652c393a
JB		 7081 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7082 /* Skip inactive CRTCs */
7083 if (!crtc->fb)
7084 continue;
7085
7086 intel_crtc = to_intel_crtc(crtc);
7087 if (!intel_crtc->busy)
7088 intel_decrease_pllclock(crtc);
7089 }
7090
45ac22c8 7091
652c393a
JB		 7092 mutex_unlock(&dev->struct_mutex);
7093}
7094
7095/**
7096 * intel_mark_busy - mark the GPU and possibly the display busy
7097 * @dev: drm device
7098 * @obj: object we're operating on
7099 *
7100 * Callers can use this function to indicate that the GPU is busy processing
7101 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
7102 * buffer), we'll also mark the display as busy, so we know to increase its
7103 * clock frequency.
7104 */
05394f39 7105void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 7106{
7107 drm_i915_private_t *dev_priv = dev->dev_private;
7108 struct drm_crtc *crtc = NULL;
7109 struct intel_framebuffer *intel_fb;
7110 struct intel_crtc *intel_crtc;
7111
5e17ee74
ZW		 7112 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7113 return;
7114
18b2190c 7115 if (!dev_priv->busy)
28cf798f 7116 dev_priv->busy = true;
18b2190c 7117 else
28cf798f
CW		 7118 mod_timer(&dev_priv->idle_timer, jiffies +
7119 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 7120
7121 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7122 if (!crtc->fb)
7123 continue;
7124
7125 intel_crtc = to_intel_crtc(crtc);
7126 intel_fb = to_intel_framebuffer(crtc->fb);
7127 if (intel_fb->obj == obj) {
7128 if (!intel_crtc->busy) {
7129 /* Non-busy -> busy, upclock */
3dec0095 7130 intel_increase_pllclock(crtc);
652c393a
JB		 7131 intel_crtc->busy = true;
7132 } else {
7133 /* Busy -> busy, put off timer */
7134 mod_timer(&intel_crtc->idle_timer, jiffies +
7135 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7136 }
7137 }
7138 }
7139}
7140
79e53945
JB		 7141static void intel_crtc_destroy(struct drm_crtc *crtc)
7142{
7143 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7144 struct drm_device *dev = crtc->dev;
7145 struct intel_unpin_work *work;
7146 unsigned long flags;
7147
7148 spin_lock_irqsave(&dev->event_lock, flags);
7149 work = intel_crtc->unpin_work;
7150 intel_crtc->unpin_work = NULL;
7151 spin_unlock_irqrestore(&dev->event_lock, flags);
7152
7153 if (work) {
7154 cancel_work_sync(&work->work);
7155 kfree(work);
7156 }
79e53945
JB		 7157
7158 drm_crtc_cleanup(crtc);
67e77c5a 7159
79e53945
JB		 7160 kfree(intel_crtc);
7161}
7162
6b95a207
KH		 7163static void intel_unpin_work_fn(struct work_struct *__work)
7164{
7165 struct intel_unpin_work *work =
7166 container_of(__work, struct intel_unpin_work, work);
7167
7168 mutex_lock(&work->dev->struct_mutex);
1690e1eb 7169 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7170 drm_gem_object_unreference(&work->pending_flip_obj->base);
7171 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7172
7782de3b 7173 intel_update_fbc(work->dev);
6b95a207
KH		 7174 mutex_unlock(&work->dev->struct_mutex);
7175 kfree(work);
7176}
7177
1afe3e9d 7178static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7179 struct drm_crtc *crtc)
6b95a207
KH		 7180{
7181 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7183 struct intel_unpin_work *work;
05394f39 7184 struct drm_i915_gem_object *obj;
6b95a207 7185 struct drm_pending_vblank_event *e;
49b14a5c 7186 struct timeval tnow, tvbl;
6b95a207
KH		 7187 unsigned long flags;
7188
7189 /* Ignore early vblank irqs */
7190 if (intel_crtc == NULL)
7191 return;
7192
49b14a5c
MK		 7193 do_gettimeofday(&tnow);
7194
6b95a207
KH		 7195 spin_lock_irqsave(&dev->event_lock, flags);
7196 work = intel_crtc->unpin_work;
7197 if (work == NULL || !work->pending) {
7198 spin_unlock_irqrestore(&dev->event_lock, flags);
7199 return;
7200 }
7201
7202 intel_crtc->unpin_work = NULL;
6b95a207
KH		 7203
7204 if (work->event) {
7205 e = work->event;
49b14a5c 7206 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 7207
7208 /* Called before vblank count and timestamps have
7209 * been updated for the vblank interval of flip
7210 * completion? Need to increment vblank count and
7211 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 7212 * to account for this. We assume this happened if we
7213 * get called over 0.9 frame durations after the last
7214 * timestamped vblank.
7215 *
7216 * This calculation can not be used with vrefresh rates
7217 * below 5Hz (10Hz to be on the safe side) without
7218 * promoting to 64 integers.
0af7e4df 7219 */
49b14a5c
MK		 7220 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7221 9 * crtc->framedur_ns) {
0af7e4df 7222 e->event.sequence++;
49b14a5c
MK		 7223 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7224 crtc->framedur_ns);
0af7e4df
MK		 7225 }
7226
49b14a5c
MK		 7227 e->event.tv_sec = tvbl.tv_sec;
7228 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 7229
6b95a207
KH		 7230 list_add_tail(&e->base.link,
7231 &e->base.file_priv->event_list);
7232 wake_up_interruptible(&e->base.file_priv->event_wait);
7233 }
7234
0af7e4df
MK		 7235 drm_vblank_put(dev, intel_crtc->pipe);
7236
6b95a207
KH		 7237 spin_unlock_irqrestore(&dev->event_lock, flags);
7238
05394f39 7239 obj = work->old_fb_obj;
d9e86c0e 7240
e59f2bac 7241 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 7242 &obj->pending_flip.counter);
7243 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 7244 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 7245
6b95a207 7246 schedule_work(&work->work);
e5510fac
JB		 7247
7248 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7249}
7250
1afe3e9d
JB		 7251void intel_finish_page_flip(struct drm_device *dev, int pipe)
7252{
7253 drm_i915_private_t *dev_priv = dev->dev_private;
7254 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7255
49b14a5c 7256 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7257}
7258
7259void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7260{
7261 drm_i915_private_t *dev_priv = dev->dev_private;
7262 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7263
49b14a5c 7264 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7265}
7266
6b95a207
KH		 7267void intel_prepare_page_flip(struct drm_device *dev, int plane)
7268{
7269 drm_i915_private_t *dev_priv = dev->dev_private;
7270 struct intel_crtc *intel_crtc =
7271 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7272 unsigned long flags;
7273
7274 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 7275 if (intel_crtc->unpin_work) {
4e5359cd
SF		 7276 if ((++intel_crtc->unpin_work->pending) > 1)
7277 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 7278 } else {
7279 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7280 }
6b95a207
KH		 7281 spin_unlock_irqrestore(&dev->event_lock, flags);
7282}
7283
8c9f3aaf
JB		 7284static int intel_gen2_queue_flip(struct drm_device *dev,
7285 struct drm_crtc *crtc,
7286 struct drm_framebuffer *fb,
7287 struct drm_i915_gem_object *obj)
7288{
7289 struct drm_i915_private *dev_priv = dev->dev_private;
7290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7291 unsigned long offset;
7292 u32 flip_mask;
7293 int ret;
7294
7295 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7296 if (ret)
7297 goto out;
7298
7299 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 7300 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf
JB		 7301
7302 ret = BEGIN_LP_RING(6);
7303 if (ret)
7304 goto out;
7305
7306 /* Can't queue multiple flips, so wait for the previous
7307 * one to finish before executing the next.
7308 */
7309 if (intel_crtc->plane)
7310 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7311 else
7312 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7313 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7314 OUT_RING(MI_NOOP);
7315 OUT_RING(MI_DISPLAY_FLIP |
7316 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7317 OUT_RING(fb->pitches[0]);
8c9f3aaf 7318 OUT_RING(obj->gtt_offset + offset);
c6a32fcb 7319 OUT_RING(0); /* aux display base address, unused */
8c9f3aaf
JB		 7320 ADVANCE_LP_RING();
7321out:
7322 return ret;
7323}
7324
7325static int intel_gen3_queue_flip(struct drm_device *dev,
7326 struct drm_crtc *crtc,
7327 struct drm_framebuffer *fb,
7328 struct drm_i915_gem_object *obj)
7329{
7330 struct drm_i915_private *dev_priv = dev->dev_private;
7331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7332 unsigned long offset;
7333 u32 flip_mask;
7334 int ret;
7335
7336 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7337 if (ret)
7338 goto out;
7339
7340 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 7341 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf
JB		 7342
7343 ret = BEGIN_LP_RING(6);
7344 if (ret)
7345 goto out;
7346
7347 if (intel_crtc->plane)
7348 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7349 else
7350 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7351 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7352 OUT_RING(MI_NOOP);
7353 OUT_RING(MI_DISPLAY_FLIP_I915 |
7354 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7355 OUT_RING(fb->pitches[0]);
8c9f3aaf
JB		 7356 OUT_RING(obj->gtt_offset + offset);
7357 OUT_RING(MI_NOOP);
7358
7359 ADVANCE_LP_RING();
7360out:
7361 return ret;
7362}
7363
7364static int intel_gen4_queue_flip(struct drm_device *dev,
7365 struct drm_crtc *crtc,
7366 struct drm_framebuffer *fb,
7367 struct drm_i915_gem_object *obj)
7368{
7369 struct drm_i915_private *dev_priv = dev->dev_private;
7370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7371 uint32_t pf, pipesrc;
7372 int ret;
7373
7374 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7375 if (ret)
7376 goto out;
7377
7378 ret = BEGIN_LP_RING(4);
7379 if (ret)
7380 goto out;
7381
7382 /* i965+ uses the linear or tiled offsets from the
7383 * Display Registers (which do not change across a page-flip)
7384 * so we need only reprogram the base address.
7385 */
7386 OUT_RING(MI_DISPLAY_FLIP |
7387 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7388 OUT_RING(fb->pitches[0]);
8c9f3aaf
JB		 7389 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7390
7391 /* XXX Enabling the panel-fitter across page-flip is so far
7392 * untested on non-native modes, so ignore it for now.
7393 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7394 */
7395 pf = 0;
7396 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7397 OUT_RING(pf | pipesrc);
7398 ADVANCE_LP_RING();
7399out:
7400 return ret;
7401}
7402
7403static int intel_gen6_queue_flip(struct drm_device *dev,
7404 struct drm_crtc *crtc,
7405 struct drm_framebuffer *fb,
7406 struct drm_i915_gem_object *obj)
7407{
7408 struct drm_i915_private *dev_priv = dev->dev_private;
7409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7410 uint32_t pf, pipesrc;
7411 int ret;
7412
7413 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7414 if (ret)
7415 goto out;
7416
7417 ret = BEGIN_LP_RING(4);
7418 if (ret)
7419 goto out;
7420
7421 OUT_RING(MI_DISPLAY_FLIP |
7422 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7423 OUT_RING(fb->pitches[0] | obj->tiling_mode);
8c9f3aaf
JB		 7424 OUT_RING(obj->gtt_offset);
7425
7426 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7427 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7428 OUT_RING(pf | pipesrc);
7429 ADVANCE_LP_RING();
7430out:
7431 return ret;
7432}
7433
7c9017e5
JB		 7434/*
7435 * On gen7 we currently use the blit ring because (in early silicon at least)
7436 * the render ring doesn't give us interrpts for page flip completion, which
7437 * means clients will hang after the first flip is queued. Fortunately the
7438 * blit ring generates interrupts properly, so use it instead.
7439 */
7440static int intel_gen7_queue_flip(struct drm_device *dev,
7441 struct drm_crtc *crtc,
7442 struct drm_framebuffer *fb,
7443 struct drm_i915_gem_object *obj)
7444{
7445 struct drm_i915_private *dev_priv = dev->dev_private;
7446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7447 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7448 int ret;
7449
7450 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7451 if (ret)
7452 goto out;
7453
7454 ret = intel_ring_begin(ring, 4);
7455 if (ret)
7456 goto out;
7457
7458 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
01f2c773 7459 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7c9017e5
JB		 7460 intel_ring_emit(ring, (obj->gtt_offset));
7461 intel_ring_emit(ring, (MI_NOOP));
7462 intel_ring_advance(ring);
7463out:
7464 return ret;
7465}
7466
8c9f3aaf
JB		 7467static int intel_default_queue_flip(struct drm_device *dev,
7468 struct drm_crtc *crtc,
7469 struct drm_framebuffer *fb,
7470 struct drm_i915_gem_object *obj)
7471{
7472 return -ENODEV;
7473}
7474
6b95a207
KH		 7475static int intel_crtc_page_flip(struct drm_crtc *crtc,
7476 struct drm_framebuffer *fb,
7477 struct drm_pending_vblank_event *event)
7478{
7479 struct drm_device *dev = crtc->dev;
7480 struct drm_i915_private *dev_priv = dev->dev_private;
7481 struct intel_framebuffer *intel_fb;
05394f39 7482 struct drm_i915_gem_object *obj;
6b95a207
KH		 7483 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7484 struct intel_unpin_work *work;
8c9f3aaf 7485 unsigned long flags;
52e68630 7486 int ret;
6b95a207
KH		 7487
7488 work = kzalloc(sizeof *work, GFP_KERNEL);
7489 if (work == NULL)
7490 return -ENOMEM;
7491
6b95a207
KH		 7492 work->event = event;
7493 work->dev = crtc->dev;
7494 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7495 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7496 INIT_WORK(&work->work, intel_unpin_work_fn);
7497
7317c75e
JB		 7498 ret = drm_vblank_get(dev, intel_crtc->pipe);
7499 if (ret)
7500 goto free_work;
7501
6b95a207
KH		 7502 /* We borrow the event spin lock for protecting unpin_work */
7503 spin_lock_irqsave(&dev->event_lock, flags);
7504 if (intel_crtc->unpin_work) {
7505 spin_unlock_irqrestore(&dev->event_lock, flags);
7506 kfree(work);
7317c75e 7507 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7508
7509 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7510 return -EBUSY;
7511 }
7512 intel_crtc->unpin_work = work;
7513 spin_unlock_irqrestore(&dev->event_lock, flags);
7514
7515 intel_fb = to_intel_framebuffer(fb);
7516 obj = intel_fb->obj;
7517
468f0b44 7518 mutex_lock(&dev->struct_mutex);
6b95a207 7519
75dfca80 7520 /* Reference the objects for the scheduled work. */
05394f39
CW		 7521 drm_gem_object_reference(&work->old_fb_obj->base);
7522 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7523
7524 crtc->fb = fb;
96b099fd 7525
e1f99ce6 7526 work->pending_flip_obj = obj;
e1f99ce6 7527
4e5359cd
SF		 7528 work->enable_stall_check = true;
7529
e1f99ce6
CW		 7530 /* Block clients from rendering to the new back buffer until
7531 * the flip occurs and the object is no longer visible.
7532 */
05394f39 7533 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 7534
8c9f3aaf
JB		 7535 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7536 if (ret)
7537 goto cleanup_pending;
6b95a207 7538
7782de3b 7539 intel_disable_fbc(dev);
6b95a207
KH		 7540 mutex_unlock(&dev->struct_mutex);
7541
e5510fac
JB		 7542 trace_i915_flip_request(intel_crtc->plane, obj);
7543
6b95a207 7544 return 0;
96b099fd 7545
8c9f3aaf
JB		 7546cleanup_pending:
7547 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 7548 drm_gem_object_unreference(&work->old_fb_obj->base);
7549 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7550 mutex_unlock(&dev->struct_mutex);
7551
7552 spin_lock_irqsave(&dev->event_lock, flags);
7553 intel_crtc->unpin_work = NULL;
7554 spin_unlock_irqrestore(&dev->event_lock, flags);
7555
7317c75e
JB		 7556 drm_vblank_put(dev, intel_crtc->pipe);
7557free_work:
96b099fd
CW		 7558 kfree(work);
7559
7560 return ret;
6b95a207
KH		 7561}
7562
47f1c6c9
CW		 7563static void intel_sanitize_modesetting(struct drm_device *dev,
7564 int pipe, int plane)
7565{
7566 struct drm_i915_private *dev_priv = dev->dev_private;
7567 u32 reg, val;
7568
7569 if (HAS_PCH_SPLIT(dev))
7570 return;
7571
7572 /* Who knows what state these registers were left in by the BIOS or
7573 * grub?
7574 *
7575 * If we leave the registers in a conflicting state (e.g. with the
7576 * display plane reading from the other pipe than the one we intend
7577 * to use) then when we attempt to teardown the active mode, we will
7578 * not disable the pipes and planes in the correct order -- leaving
7579 * a plane reading from a disabled pipe and possibly leading to
7580 * undefined behaviour.
7581 */
7582
7583 reg = DSPCNTR(plane);
7584 val = I915_READ(reg);
7585
7586 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7587 return;
7588 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7589 return;
7590
7591 /* This display plane is active and attached to the other CPU pipe. */
7592 pipe = !pipe;
7593
7594 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 7595 intel_disable_plane(dev_priv, plane, pipe);
7596 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 7597}
79e53945 7598
f6e5b160
CW		 7599static void intel_crtc_reset(struct drm_crtc *crtc)
7600{
7601 struct drm_device *dev = crtc->dev;
7602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7603
7604 /* Reset flags back to the 'unknown' status so that they
7605 * will be correctly set on the initial modeset.
7606 */
7607 intel_crtc->dpms_mode = -1;
7608
7609 /* We need to fix up any BIOS configuration that conflicts with
7610 * our expectations.
7611 */
7612 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7613}
7614
7615static struct drm_crtc_helper_funcs intel_helper_funcs = {
7616 .dpms = intel_crtc_dpms,
7617 .mode_fixup = intel_crtc_mode_fixup,
7618 .mode_set = intel_crtc_mode_set,
7619 .mode_set_base = intel_pipe_set_base,
7620 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7621 .load_lut = intel_crtc_load_lut,
7622 .disable = intel_crtc_disable,
7623};
7624
7625static const struct drm_crtc_funcs intel_crtc_funcs = {
7626 .reset = intel_crtc_reset,
7627 .cursor_set = intel_crtc_cursor_set,
7628 .cursor_move = intel_crtc_cursor_move,
7629 .gamma_set = intel_crtc_gamma_set,
7630 .set_config = drm_crtc_helper_set_config,
7631 .destroy = intel_crtc_destroy,
7632 .page_flip = intel_crtc_page_flip,
7633};
7634
b358d0a6 7635static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 7636{
22fd0fab 7637 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 7638 struct intel_crtc *intel_crtc;
7639 int i;
7640
7641 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7642 if (intel_crtc == NULL)
7643 return;
7644
7645 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7646
7647 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7648 for (i = 0; i < 256; i++) {
7649 intel_crtc->lut_r[i] = i;
7650 intel_crtc->lut_g[i] = i;
7651 intel_crtc->lut_b[i] = i;
7652 }
7653
80824003
JB		 7654 /* Swap pipes & planes for FBC on pre-965 */
7655 intel_crtc->pipe = pipe;
7656 intel_crtc->plane = pipe;
e2e767ab 7657 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7658 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7659 intel_crtc->plane = !pipe;
80824003
JB		 7660 }
7661
22fd0fab
JB		 7662 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7663 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7664 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7665 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7666
5d1d0cc8 7667 intel_crtc_reset(&intel_crtc->base);
04dbff52 7668 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 7669 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 7670
7671 if (HAS_PCH_SPLIT(dev)) {
4b645f14
JB		 7672 if (pipe == 2 && IS_IVYBRIDGE(dev))
7673 intel_crtc->no_pll = true;
7e7d76c3
JB		 7674 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7675 intel_helper_funcs.commit = ironlake_crtc_commit;
7676 } else {
7677 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7678 intel_helper_funcs.commit = i9xx_crtc_commit;
7679 }
7680
79e53945
JB		 7681 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7682
652c393a
JB		 7683 intel_crtc->busy = false;
7684
7685 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7686 (unsigned long)intel_crtc);
79e53945
JB		 7687}
7688
08d7b3d1 7689int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7690 struct drm_file *file)
08d7b3d1
CW		 7691{
7692 drm_i915_private_t *dev_priv = dev->dev_private;
7693 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 7694 struct drm_mode_object *drmmode_obj;
7695 struct intel_crtc *crtc;
08d7b3d1
CW		 7696
7697 if (!dev_priv) {
7698 DRM_ERROR("called with no initialization\n");
7699 return -EINVAL;
7700 }
7701
c05422d5
DV		 7702 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7703 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7704
c05422d5 7705 if (!drmmode_obj) {
08d7b3d1
CW		 7706 DRM_ERROR("no such CRTC id\n");
7707 return -EINVAL;
7708 }
7709
c05422d5
DV		 7710 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7711 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7712
c05422d5 7713 return 0;
08d7b3d1
CW		 7714}
7715
c5e4df33 7716static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 7717{
4ef69c7a 7718 struct intel_encoder *encoder;
79e53945 7719 int index_mask = 0;
79e53945
JB		 7720 int entry = 0;
7721
4ef69c7a
CW		 7722 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7723 if (type_mask & encoder->clone_mask)
79e53945
JB		 7724 index_mask |= (1 << entry);
7725 entry++;
7726 }
4ef69c7a 7727
79e53945
JB		 7728 return index_mask;
7729}
7730
4d302442
CW		 7731static bool has_edp_a(struct drm_device *dev)
7732{
7733 struct drm_i915_private *dev_priv = dev->dev_private;
7734
7735 if (!IS_MOBILE(dev))
7736 return false;
7737
7738 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7739 return false;
7740
7741 if (IS_GEN5(dev) &&
7742 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7743 return false;
7744
7745 return true;
7746}
7747
79e53945
JB		 7748static void intel_setup_outputs(struct drm_device *dev)
7749{
725e30ad 7750 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 7751 struct intel_encoder *encoder;
cb0953d7 7752 bool dpd_is_edp = false;
c5d1b51d 7753 bool has_lvds = false;
79e53945 7754
541998a1 7755 if (IS_MOBILE(dev) && !IS_I830(dev))
c5d1b51d
CW		 7756 has_lvds = intel_lvds_init(dev);
7757 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7758 /* disable the panel fitter on everything but LVDS */
7759 I915_WRITE(PFIT_CONTROL, 0);
7760 }
79e53945 7761
bad720ff 7762 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 7763 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 7764
4d302442 7765 if (has_edp_a(dev))
32f9d658
ZW		 7766 intel_dp_init(dev, DP_A);
7767
cb0953d7
AJ		 7768 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7769 intel_dp_init(dev, PCH_DP_D);
7770 }
7771
7772 intel_crt_init(dev);
7773
7774 if (HAS_PCH_SPLIT(dev)) {
7775 int found;
7776
30ad48b7 7777 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca
ZY		 7778 /* PCH SDVOB multiplex with HDMIB */
7779 found = intel_sdvo_init(dev, PCH_SDVOB);
30ad48b7
ZW		 7780 if (!found)
7781 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 7782 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7783 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 7784 }
7785
7786 if (I915_READ(HDMIC) & PORT_DETECTED)
7787 intel_hdmi_init(dev, HDMIC);
7788
7789 if (I915_READ(HDMID) & PORT_DETECTED)
7790 intel_hdmi_init(dev, HDMID);
7791
5eb08b69
ZW		 7792 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7793 intel_dp_init(dev, PCH_DP_C);
7794
cb0953d7 7795 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 7796 intel_dp_init(dev, PCH_DP_D);
7797
103a196f 7798 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 7799 bool found = false;
7d57382e 7800
725e30ad 7801 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 7802 DRM_DEBUG_KMS("probing SDVOB\n");
725e30ad 7803 found = intel_sdvo_init(dev, SDVOB);
b01f2c3a
JB		 7804 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7805 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 7806 intel_hdmi_init(dev, SDVOB);
b01f2c3a 7807 }
27185ae1 7808
b01f2c3a
JB		 7809 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7810 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 7811 intel_dp_init(dev, DP_B);
b01f2c3a 7812 }
725e30ad 7813 }
13520b05
KH		 7814
7815 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 7816
b01f2c3a
JB		 7817 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7818 DRM_DEBUG_KMS("probing SDVOC\n");
725e30ad 7819 found = intel_sdvo_init(dev, SDVOC);
b01f2c3a 7820 }
27185ae1
ML		 7821
7822 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7823
b01f2c3a
JB		 7824 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7825 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 7826 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 7827 }
7828 if (SUPPORTS_INTEGRATED_DP(dev)) {
7829 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 7830 intel_dp_init(dev, DP_C);
b01f2c3a 7831 }
725e30ad 7832 }
27185ae1 7833
b01f2c3a
JB		 7834 if (SUPPORTS_INTEGRATED_DP(dev) &&
7835 (I915_READ(DP_D) & DP_DETECTED)) {
7836 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 7837 intel_dp_init(dev, DP_D);
b01f2c3a 7838 }
bad720ff 7839 } else if (IS_GEN2(dev))
79e53945
JB		 7840 intel_dvo_init(dev);
7841
103a196f 7842 if (SUPPORTS_TV(dev))
79e53945
JB		 7843 intel_tv_init(dev);
7844
4ef69c7a
CW		 7845 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7846 encoder->base.possible_crtcs = encoder->crtc_mask;
7847 encoder->base.possible_clones =
7848 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 7849 }
47356eb6 7850
2c7111db
CW		 7851 /* disable all the possible outputs/crtcs before entering KMS mode */
7852 drm_helper_disable_unused_functions(dev);
9fb526db
KP		 7853
7854 if (HAS_PCH_SPLIT(dev))
7855 ironlake_init_pch_refclk(dev);
79e53945
JB		 7856}
7857
7858static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7859{
7860 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 7861
7862 drm_framebuffer_cleanup(fb);
05394f39 7863 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 7864
7865 kfree(intel_fb);
7866}
7867
7868static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 7869 struct drm_file *file,
79e53945
JB		 7870 unsigned int *handle)
7871{
7872 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 7873 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 7874
05394f39 7875 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 7876}
7877
7878static const struct drm_framebuffer_funcs intel_fb_funcs = {
7879 .destroy = intel_user_framebuffer_destroy,
7880 .create_handle = intel_user_framebuffer_create_handle,
7881};
7882
38651674
DA		 7883int intel_framebuffer_init(struct drm_device *dev,
7884 struct intel_framebuffer *intel_fb,
308e5bcb 7885 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 7886 struct drm_i915_gem_object *obj)
79e53945 7887{
79e53945
JB		 7888 int ret;
7889
05394f39 7890 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 7891 return -EINVAL;
7892
308e5bcb 7893 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 7894 return -EINVAL;
7895
308e5bcb 7896 switch (mode_cmd->pixel_format) {
04b3924d
VS		 7897 case DRM_FORMAT_RGB332:
7898 case DRM_FORMAT_RGB565:
7899 case DRM_FORMAT_XRGB8888:
7900 case DRM_FORMAT_ARGB8888:
7901 case DRM_FORMAT_XRGB2101010:
7902 case DRM_FORMAT_ARGB2101010:
308e5bcb 7903 /* RGB formats are common across chipsets */
b5626747 7904 break;
04b3924d
VS		 7905 case DRM_FORMAT_YUYV:
7906 case DRM_FORMAT_UYVY:
7907 case DRM_FORMAT_YVYU:
7908 case DRM_FORMAT_VYUY:
57cd6508
CW		 7909 break;
7910 default:
aca25848
ED		 7911 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7912 mode_cmd->pixel_format);
57cd6508
CW		 7913 return -EINVAL;
7914 }
7915
79e53945
JB		 7916 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7917 if (ret) {
7918 DRM_ERROR("framebuffer init failed %d\n", ret);
7919 return ret;
7920 }
7921
7922 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 7923 intel_fb->obj = obj;
79e53945
JB		 7924 return 0;
7925}
7926
79e53945
JB		 7927static struct drm_framebuffer *
7928intel_user_framebuffer_create(struct drm_device *dev,
7929 struct drm_file *filp,
308e5bcb 7930 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 7931{
05394f39 7932 struct drm_i915_gem_object *obj;
79e53945 7933
308e5bcb
JB		 7934 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7935 mode_cmd->handles[0]));
c8725226 7936 if (&obj->base == NULL)
cce13ff7 7937 return ERR_PTR(-ENOENT);
79e53945 7938
d2dff872 7939 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 7940}
7941
79e53945 7942static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 7943 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 7944 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 7945};
7946
05394f39 7947static struct drm_i915_gem_object *
aa40d6bb 7948intel_alloc_context_page(struct drm_device *dev)
9ea8d059 7949{
05394f39 7950 struct drm_i915_gem_object *ctx;
9ea8d059
CW		 7951 int ret;
7952
2c34b850
BW		 7953 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7954
aa40d6bb
ZN		 7955 ctx = i915_gem_alloc_object(dev, 4096);
7956 if (!ctx) {
9ea8d059
CW		 7957 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7958 return NULL;
7959 }
7960
75e9e915 7961 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW		 7962 if (ret) {
7963 DRM_ERROR("failed to pin power context: %d\n", ret);
7964 goto err_unref;
7965 }
7966
aa40d6bb 7967 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW		 7968 if (ret) {
7969 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7970 goto err_unpin;
7971 }
9ea8d059 7972
aa40d6bb 7973 return ctx;
9ea8d059
CW		 7974
7975err_unpin:
aa40d6bb 7976 i915_gem_object_unpin(ctx);
9ea8d059 7977err_unref:
05394f39 7978 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW		 7979 mutex_unlock(&dev->struct_mutex);
7980 return NULL;
7981}
7982
7648fa99
JB		 7983bool ironlake_set_drps(struct drm_device *dev, u8 val)
7984{
7985 struct drm_i915_private *dev_priv = dev->dev_private;
7986 u16 rgvswctl;
7987
7988 rgvswctl = I915_READ16(MEMSWCTL);
7989 if (rgvswctl & MEMCTL_CMD_STS) {
7990 DRM_DEBUG("gpu busy, RCS change rejected\n");
7991 return false; /* still busy with another command */
7992 }
7993
7994 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7995 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7996 I915_WRITE16(MEMSWCTL, rgvswctl);
7997 POSTING_READ16(MEMSWCTL);
7998
7999 rgvswctl |= MEMCTL_CMD_STS;
8000 I915_WRITE16(MEMSWCTL, rgvswctl);
8001
8002 return true;
8003}
8004
f97108d1
JB		 8005void ironlake_enable_drps(struct drm_device *dev)
8006{
8007 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 8008 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 8009 u8 fmax, fmin, fstart, vstart;
f97108d1 8010
ea056c14
JB		 8011 /* Enable temp reporting */
8012 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
8013 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
8014
f97108d1
JB		 8015 /* 100ms RC evaluation intervals */
8016 I915_WRITE(RCUPEI, 100000);
8017 I915_WRITE(RCDNEI, 100000);
8018
8019 /* Set max/min thresholds to 90ms and 80ms respectively */
8020 I915_WRITE(RCBMAXAVG, 90000);
8021 I915_WRITE(RCBMINAVG, 80000);
8022
8023 I915_WRITE(MEMIHYST, 1);
8024
8025 /* Set up min, max, and cur for interrupt handling */
8026 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
8027 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
8028 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
8029 MEMMODE_FSTART_SHIFT;
7648fa99 8030
f97108d1
JB		 8031 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
8032 PXVFREQ_PX_SHIFT;
8033
80dbf4b7 8034 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB		 8035 dev_priv->fstart = fstart;
8036
80dbf4b7 8037 dev_priv->max_delay = fstart;
f97108d1
JB		 8038 dev_priv->min_delay = fmin;
8039 dev_priv->cur_delay = fstart;
8040
80dbf4b7
JB		 8041 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8042 fmax, fmin, fstart);
7648fa99 8043
f97108d1
JB		 8044 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8045
8046 /*
8047 * Interrupts will be enabled in ironlake_irq_postinstall
8048 */
8049
8050 I915_WRITE(VIDSTART, vstart);
8051 POSTING_READ(VIDSTART);
8052
8053 rgvmodectl |= MEMMODE_SWMODE_EN;
8054 I915_WRITE(MEMMODECTL, rgvmodectl);
8055
481b6af3 8056 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 8057 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB		 8058 msleep(1);
8059
7648fa99 8060 ironlake_set_drps(dev, fstart);
f97108d1 8061
7648fa99
JB		 8062 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8063 I915_READ(0x112e0);
8064 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8065 dev_priv->last_count2 = I915_READ(0x112f4);
8066 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB		 8067}
8068
8069void ironlake_disable_drps(struct drm_device *dev)
8070{
8071 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 8072 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB		 8073
8074 /* Ack interrupts, disable EFC interrupt */
8075 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8076 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8077 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8078 I915_WRITE(DEIIR, DE_PCU_EVENT);
8079 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8080
8081 /* Go back to the starting frequency */
7648fa99 8082 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB		 8083 msleep(1);
8084 rgvswctl |= MEMCTL_CMD_STS;
8085 I915_WRITE(MEMSWCTL, rgvswctl);
8086 msleep(1);
8087
8088}
8089
3b8d8d91
JB		 8090void gen6_set_rps(struct drm_device *dev, u8 val)
8091{
8092 struct drm_i915_private *dev_priv = dev->dev_private;
8093 u32 swreq;
8094
8095 swreq = (val & 0x3ff) << 25;
8096 I915_WRITE(GEN6_RPNSWREQ, swreq);
8097}
8098
8099void gen6_disable_rps(struct drm_device *dev)
8100{
8101 struct drm_i915_private *dev_priv = dev->dev_private;
8102
8103 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8104 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8105 I915_WRITE(GEN6_PMIER, 0);
6fdd4d98
DV		 8106 /* Complete PM interrupt masking here doesn't race with the rps work
8107 * item again unmasking PM interrupts because that is using a different
8108 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8109 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
4912d041
BW		 8110
8111 spin_lock_irq(&dev_priv->rps_lock);
8112 dev_priv->pm_iir = 0;
8113 spin_unlock_irq(&dev_priv->rps_lock);
8114
3b8d8d91
JB		 8115 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8116}
8117
7648fa99
JB		 8118static unsigned long intel_pxfreq(u32 vidfreq)
8119{
8120 unsigned long freq;
8121 int div = (vidfreq & 0x3f0000) >> 16;
8122 int post = (vidfreq & 0x3000) >> 12;
8123 int pre = (vidfreq & 0x7);
8124
8125 if (!pre)
8126 return 0;
8127
8128 freq = ((div * 133333) / ((1<<post) * pre));
8129
8130 return freq;
8131}
8132
8133void intel_init_emon(struct drm_device *dev)
8134{
8135 struct drm_i915_private *dev_priv = dev->dev_private;
8136 u32 lcfuse;
8137 u8 pxw[16];
8138 int i;
8139
8140 /* Disable to program */
8141 I915_WRITE(ECR, 0);
8142 POSTING_READ(ECR);
8143
8144 /* Program energy weights for various events */
8145 I915_WRITE(SDEW, 0x15040d00);
8146 I915_WRITE(CSIEW0, 0x007f0000);
8147 I915_WRITE(CSIEW1, 0x1e220004);
8148 I915_WRITE(CSIEW2, 0x04000004);
8149
8150 for (i = 0; i < 5; i++)
8151 I915_WRITE(PEW + (i * 4), 0);
8152 for (i = 0; i < 3; i++)
8153 I915_WRITE(DEW + (i * 4), 0);
8154
8155 /* Program P-state weights to account for frequency power adjustment */
8156 for (i = 0; i < 16; i++) {
8157 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8158 unsigned long freq = intel_pxfreq(pxvidfreq);
8159 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8160 PXVFREQ_PX_SHIFT;
8161 unsigned long val;
8162
8163 val = vid * vid;
8164 val *= (freq / 1000);
8165 val *= 255;
8166 val /= (127*127*900);
8167 if (val > 0xff)
8168 DRM_ERROR("bad pxval: %ld\n", val);
8169 pxw[i] = val;
8170 }
8171 /* Render standby states get 0 weight */
8172 pxw[14] = 0;
8173 pxw[15] = 0;
8174
8175 for (i = 0; i < 4; i++) {
8176 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8177 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8178 I915_WRITE(PXW + (i * 4), val);
8179 }
8180
8181 /* Adjust magic regs to magic values (more experimental results) */
8182 I915_WRITE(OGW0, 0);
8183 I915_WRITE(OGW1, 0);
8184 I915_WRITE(EG0, 0x00007f00);
8185 I915_WRITE(EG1, 0x0000000e);
8186 I915_WRITE(EG2, 0x000e0000);
8187 I915_WRITE(EG3, 0x68000300);
8188 I915_WRITE(EG4, 0x42000000);
8189 I915_WRITE(EG5, 0x00140031);
8190 I915_WRITE(EG6, 0);
8191 I915_WRITE(EG7, 0);
8192
8193 for (i = 0; i < 8; i++)
8194 I915_WRITE(PXWL + (i * 4), 0);
8195
8196 /* Enable PMON + select events */
8197 I915_WRITE(ECR, 0x80000019);
8198
8199 lcfuse = I915_READ(LCFUSE02);
8200
8201 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8202}
8203
c0f372b3
KP		 8204static bool intel_enable_rc6(struct drm_device *dev)
8205{
8206 /*
8207 * Respect the kernel parameter if it is set
8208 */
8209 if (i915_enable_rc6 >= 0)
8210 return i915_enable_rc6;
8211
8212 /*
8213 * Disable RC6 on Ironlake
8214 */
8215 if (INTEL_INFO(dev)->gen == 5)
8216 return 0;
8217
8218 /*
371de6e4 8219 * Disable rc6 on Sandybridge
c0f372b3
KP		 8220 */
8221 if (INTEL_INFO(dev)->gen == 6) {
371de6e4
KP		 8222 DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
8223 return 0;
c0f372b3
KP		 8224 }
8225 DRM_DEBUG_DRIVER("RC6 enabled\n");
8226 return 1;
8227}
8228
3b8d8d91 8229void gen6_enable_rps(struct drm_i915_private *dev_priv)
8fd26859 8230{
a6044e23
JB		 8231 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8232 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7df8721b 8233 u32 pcu_mbox, rc6_mask = 0;
dd202c6d 8234 u32 gtfifodbg;
a6044e23 8235 int cur_freq, min_freq, max_freq;
8fd26859
CW		 8236 int i;
8237
8238 /* Here begins a magic sequence of register writes to enable
8239 * auto-downclocking.
8240 *
8241 * Perhaps there might be some value in exposing these to
8242 * userspace...
8243 */
8244 I915_WRITE(GEN6_RC_STATE, 0);
d1ebd816 8245 mutex_lock(&dev_priv->dev->struct_mutex);
dd202c6d
BW		 8246
8247 /* Clear the DBG now so we don't confuse earlier errors */
8248 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
8249 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
8250 I915_WRITE(GTFIFODBG, gtfifodbg);
8251 }
8252
fcca7926 8253 gen6_gt_force_wake_get(dev_priv);
8fd26859 8254
3b8d8d91 8255 /* disable the counters and set deterministic thresholds */
8fd26859
CW		 8256 I915_WRITE(GEN6_RC_CONTROL, 0);
8257
8258 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8259 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8260 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8261 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8262 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8263
8264 for (i = 0; i < I915_NUM_RINGS; i++)
8265 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8266
8267 I915_WRITE(GEN6_RC_SLEEP, 0);
8268 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8269 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8270 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8271 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8272
c0f372b3 8273 if (intel_enable_rc6(dev_priv->dev))
7df8721b
JB		 8274 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
8275 GEN6_RC_CTL_RC6_ENABLE;
8276
8fd26859 8277 I915_WRITE(GEN6_RC_CONTROL,
7df8721b 8278 rc6_mask |
9c3d2f7f 8279 GEN6_RC_CTL_EI_MODE(1) |
8fd26859
CW		 8280 GEN6_RC_CTL_HW_ENABLE);
8281
3b8d8d91 8282 I915_WRITE(GEN6_RPNSWREQ,
8fd26859
CW		 8283 GEN6_FREQUENCY(10) |
8284 GEN6_OFFSET(0) |
8285 GEN6_AGGRESSIVE_TURBO);
8286 I915_WRITE(GEN6_RC_VIDEO_FREQ,
8287 GEN6_FREQUENCY(12));
8288
8289 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8290 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8291 18 << 24 |
8292 6 << 16);
ccab5c82
JB		 8293 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8294 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8fd26859 8295 I915_WRITE(GEN6_RP_UP_EI, 100000);
ccab5c82 8296 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8fd26859
CW		 8297 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8298 I915_WRITE(GEN6_RP_CONTROL,
8299 GEN6_RP_MEDIA_TURBO |
6ed55ee7 8300 GEN6_RP_MEDIA_HW_MODE |
8fd26859
CW		 8301 GEN6_RP_MEDIA_IS_GFX |
8302 GEN6_RP_ENABLE |
ccab5c82
JB		 8303 GEN6_RP_UP_BUSY_AVG |
8304 GEN6_RP_DOWN_IDLE_CONT);
8fd26859
CW		 8305
8306 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8307 500))
8308 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8309
8310 I915_WRITE(GEN6_PCODE_DATA, 0);
8311 I915_WRITE(GEN6_PCODE_MAILBOX,
8312 GEN6_PCODE_READY |
8313 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8314 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8315 500))
8316 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8317
a6044e23
JB		 8318 min_freq = (rp_state_cap & 0xff0000) >> 16;
8319 max_freq = rp_state_cap & 0xff;
8320 cur_freq = (gt_perf_status & 0xff00) >> 8;
8321
8322 /* Check for overclock support */
8323 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8324 500))
8325 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8326 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8327 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8328 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8329 500))
8330 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8331 if (pcu_mbox & (1<<31)) { /* OC supported */
8332 max_freq = pcu_mbox & 0xff;
e281fcaa 8333 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
a6044e23
JB		 8334 }
8335
8336 /* In units of 100MHz */
8337 dev_priv->max_delay = max_freq;
8338 dev_priv->min_delay = min_freq;
8339 dev_priv->cur_delay = cur_freq;
8340
8fd26859
CW		 8341 /* requires MSI enabled */
8342 I915_WRITE(GEN6_PMIER,
8343 GEN6_PM_MBOX_EVENT |
8344 GEN6_PM_THERMAL_EVENT |
8345 GEN6_PM_RP_DOWN_TIMEOUT |
8346 GEN6_PM_RP_UP_THRESHOLD |
8347 GEN6_PM_RP_DOWN_THRESHOLD |
8348 GEN6_PM_RP_UP_EI_EXPIRED |
8349 GEN6_PM_RP_DOWN_EI_EXPIRED);
4912d041
BW		 8350 spin_lock_irq(&dev_priv->rps_lock);
8351 WARN_ON(dev_priv->pm_iir != 0);
3b8d8d91 8352 I915_WRITE(GEN6_PMIMR, 0);
4912d041 8353 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91
JB		 8354 /* enable all PM interrupts */
8355 I915_WRITE(GEN6_PMINTRMSK, 0);
8fd26859 8356
fcca7926 8357 gen6_gt_force_wake_put(dev_priv);
d1ebd816 8358 mutex_unlock(&dev_priv->dev->struct_mutex);
8fd26859
CW		 8359}
8360
23b2f8bb
JB		 8361void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8362{
8363 int min_freq = 15;
8364 int gpu_freq, ia_freq, max_ia_freq;
8365 int scaling_factor = 180;
8366
8367 max_ia_freq = cpufreq_quick_get_max(0);
8368 /*
8369 * Default to measured freq if none found, PCU will ensure we don't go
8370 * over
8371 */
8372 if (!max_ia_freq)
8373 max_ia_freq = tsc_khz;
8374
8375 /* Convert from kHz to MHz */
8376 max_ia_freq /= 1000;
8377
8378 mutex_lock(&dev_priv->dev->struct_mutex);
8379
8380 /*
8381 * For each potential GPU frequency, load a ring frequency we'd like
8382 * to use for memory access. We do this by specifying the IA frequency
8383 * the PCU should use as a reference to determine the ring frequency.
8384 */
8385 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8386 gpu_freq--) {
8387 int diff = dev_priv->max_delay - gpu_freq;
8388
8389 /*
8390 * For GPU frequencies less than 750MHz, just use the lowest
8391 * ring freq.
8392 */
8393 if (gpu_freq < min_freq)
8394 ia_freq = 800;
8395 else
8396 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8397 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8398
8399 I915_WRITE(GEN6_PCODE_DATA,
8400 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8401 gpu_freq);
8402 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8403 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8404 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8405 GEN6_PCODE_READY) == 0, 10)) {
8406 DRM_ERROR("pcode write of freq table timed out\n");
8407 continue;
8408 }
8409 }
8410
8411 mutex_unlock(&dev_priv->dev->struct_mutex);
8412}
8413
6067aaea
JB		 8414static void ironlake_init_clock_gating(struct drm_device *dev)
8415{
8416 struct drm_i915_private *dev_priv = dev->dev_private;
8417 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8418
8419 /* Required for FBC */
8420 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8421 DPFCRUNIT_CLOCK_GATE_DISABLE |
8422 DPFDUNIT_CLOCK_GATE_DISABLE;
8423 /* Required for CxSR */
8424 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8425
8426 I915_WRITE(PCH_3DCGDIS0,
8427 MARIUNIT_CLOCK_GATE_DISABLE |
8428 SVSMUNIT_CLOCK_GATE_DISABLE);
8429 I915_WRITE(PCH_3DCGDIS1,
8430 VFMUNIT_CLOCK_GATE_DISABLE);
8431
8432 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8433
6067aaea
JB		 8434 /*
8435 * According to the spec the following bits should be set in
8436 * order to enable memory self-refresh
8437 * The bit 22/21 of 0x42004
8438 * The bit 5 of 0x42020
8439 * The bit 15 of 0x45000
8440 */
8441 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8442 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8443 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8444 I915_WRITE(ILK_DSPCLK_GATE,
8445 (I915_READ(ILK_DSPCLK_GATE) |
8446 ILK_DPARB_CLK_GATE));
8447 I915_WRITE(DISP_ARB_CTL,
8448 (I915_READ(DISP_ARB_CTL) |
8449 DISP_FBC_WM_DIS));
8450 I915_WRITE(WM3_LP_ILK, 0);
8451 I915_WRITE(WM2_LP_ILK, 0);
8452 I915_WRITE(WM1_LP_ILK, 0);
8453
8454 /*
8455 * Based on the document from hardware guys the following bits
8456 * should be set unconditionally in order to enable FBC.
8457 * The bit 22 of 0x42000
8458 * The bit 22 of 0x42004
8459 * The bit 7,8,9 of 0x42020.
8460 */
8461 if (IS_IRONLAKE_M(dev)) {
8462 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8463 I915_READ(ILK_DISPLAY_CHICKEN1) |
8464 ILK_FBCQ_DIS);
8465 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8466 I915_READ(ILK_DISPLAY_CHICKEN2) |
8467 ILK_DPARB_GATE);
8468 I915_WRITE(ILK_DSPCLK_GATE,
8469 I915_READ(ILK_DSPCLK_GATE) |
8470 ILK_DPFC_DIS1 |
8471 ILK_DPFC_DIS2 |
8472 ILK_CLK_FBC);
8473 }
8474
8475 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8476 I915_READ(ILK_DISPLAY_CHICKEN2) |
8477 ILK_ELPIN_409_SELECT);
8478 I915_WRITE(_3D_CHICKEN2,
8479 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8480 _3D_CHICKEN2_WM_READ_PIPELINED);
8fd26859
CW		 8481}
8482
6067aaea 8483static void gen6_init_clock_gating(struct drm_device *dev)
652c393a
JB		 8484{
8485 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 8486 int pipe;
6067aaea
JB		 8487 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8488
8489 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
652c393a 8490
6067aaea
JB		 8491 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8492 I915_READ(ILK_DISPLAY_CHICKEN2) |
8493 ILK_ELPIN_409_SELECT);
8956c8bb 8494
6067aaea
JB		 8495 I915_WRITE(WM3_LP_ILK, 0);
8496 I915_WRITE(WM2_LP_ILK, 0);
8497 I915_WRITE(WM1_LP_ILK, 0);
652c393a 8498
406478dc
EA		 8499 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8500 * gating disable must be set. Failure to set it results in
8501 * flickering pixels due to Z write ordering failures after
8502 * some amount of runtime in the Mesa "fire" demo, and Unigine
8503 * Sanctuary and Tropics, and apparently anything else with
8504 * alpha test or pixel discard.
9ca1d10d
EA		 8505 *
8506 * According to the spec, bit 11 (RCCUNIT) must also be set,
8507 * but we didn't debug actual testcases to find it out.
406478dc 8508 */
9ca1d10d
EA		 8509 I915_WRITE(GEN6_UCGCTL2,
8510 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8511 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
406478dc 8512
652c393a 8513 /*
6067aaea
JB		 8514 * According to the spec the following bits should be
8515 * set in order to enable memory self-refresh and fbc:
8516 * The bit21 and bit22 of 0x42000
8517 * The bit21 and bit22 of 0x42004
8518 * The bit5 and bit7 of 0x42020
8519 * The bit14 of 0x70180
8520 * The bit14 of 0x71180
652c393a 8521 */
6067aaea
JB		 8522 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8523 I915_READ(ILK_DISPLAY_CHICKEN1) |
8524 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8525 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8526 I915_READ(ILK_DISPLAY_CHICKEN2) |
8527 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8528 I915_WRITE(ILK_DSPCLK_GATE,
8529 I915_READ(ILK_DSPCLK_GATE) |
8530 ILK_DPARB_CLK_GATE |
8531 ILK_DPFD_CLK_GATE);
8956c8bb 8532
d74362c9 8533 for_each_pipe(pipe) {
6067aaea
JB		 8534 I915_WRITE(DSPCNTR(pipe),
8535 I915_READ(DSPCNTR(pipe)) |
8536 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 8537 intel_flush_display_plane(dev_priv, pipe);
8538 }
6067aaea 8539}
8956c8bb 8540
28963a3e
JB		 8541static void ivybridge_init_clock_gating(struct drm_device *dev)
8542{
8543 struct drm_i915_private *dev_priv = dev->dev_private;
8544 int pipe;
8545 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7f8a8569 8546
28963a3e 8547 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
382b0936 8548
28963a3e
JB		 8549 I915_WRITE(WM3_LP_ILK, 0);
8550 I915_WRITE(WM2_LP_ILK, 0);
8551 I915_WRITE(WM1_LP_ILK, 0);
de6e2eaf 8552
28963a3e 8553 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
67e92af0 8554
116ac8d2
EA		 8555 I915_WRITE(IVB_CHICKEN3,
8556 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8557 CHICKEN3_DGMG_DONE_FIX_DISABLE);
8558
d74362c9 8559 for_each_pipe(pipe) {
28963a3e
JB		 8560 I915_WRITE(DSPCNTR(pipe),
8561 I915_READ(DSPCNTR(pipe)) |
8562 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 8563 intel_flush_display_plane(dev_priv, pipe);
8564 }
28963a3e
JB		 8565}
8566
6067aaea
JB		 8567static void g4x_init_clock_gating(struct drm_device *dev)
8568{
8569 struct drm_i915_private *dev_priv = dev->dev_private;
8570 uint32_t dspclk_gate;
8fd26859 8571
6067aaea
JB		 8572 I915_WRITE(RENCLK_GATE_D1, 0);
8573 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8574 GS_UNIT_CLOCK_GATE_DISABLE |
8575 CL_UNIT_CLOCK_GATE_DISABLE);
8576 I915_WRITE(RAMCLK_GATE_D, 0);
8577 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8578 OVRUNIT_CLOCK_GATE_DISABLE |
8579 OVCUNIT_CLOCK_GATE_DISABLE;
8580 if (IS_GM45(dev))
8581 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8582 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8583}
1398261a 8584
6067aaea
JB		 8585static void crestline_init_clock_gating(struct drm_device *dev)
8586{
8587 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 8588
6067aaea
JB		 8589 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8590 I915_WRITE(RENCLK_GATE_D2, 0);
8591 I915_WRITE(DSPCLK_GATE_D, 0);
8592 I915_WRITE(RAMCLK_GATE_D, 0);
8593 I915_WRITE16(DEUC, 0);
8594}
652c393a 8595
6067aaea
JB		 8596static void broadwater_init_clock_gating(struct drm_device *dev)
8597{
8598 struct drm_i915_private *dev_priv = dev->dev_private;
8599
8600 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8601 I965_RCC_CLOCK_GATE_DISABLE |
8602 I965_RCPB_CLOCK_GATE_DISABLE |
8603 I965_ISC_CLOCK_GATE_DISABLE |
8604 I965_FBC_CLOCK_GATE_DISABLE);
8605 I915_WRITE(RENCLK_GATE_D2, 0);
8606}
8607
8608static void gen3_init_clock_gating(struct drm_device *dev)
8609{
8610 struct drm_i915_private *dev_priv = dev->dev_private;
8611 u32 dstate = I915_READ(D_STATE);
8612
8613 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8614 DSTATE_DOT_CLOCK_GATING;
8615 I915_WRITE(D_STATE, dstate);
8616}
8617
8618static void i85x_init_clock_gating(struct drm_device *dev)
8619{
8620 struct drm_i915_private *dev_priv = dev->dev_private;
8621
8622 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8623}
8624
8625static void i830_init_clock_gating(struct drm_device *dev)
8626{
8627 struct drm_i915_private *dev_priv = dev->dev_private;
8628
8629 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
652c393a
JB		 8630}
8631
645c62a5
JB		 8632static void ibx_init_clock_gating(struct drm_device *dev)
8633{
8634 struct drm_i915_private *dev_priv = dev->dev_private;
8635
8636 /*
8637 * On Ibex Peak and Cougar Point, we need to disable clock
8638 * gating for the panel power sequencer or it will fail to
8639 * start up when no ports are active.
8640 */
8641 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8642}
8643
8644static void cpt_init_clock_gating(struct drm_device *dev)
8645{
8646 struct drm_i915_private *dev_priv = dev->dev_private;
3bcf603f 8647 int pipe;
645c62a5
JB		 8648
8649 /*
8650 * On Ibex Peak and Cougar Point, we need to disable clock
8651 * gating for the panel power sequencer or it will fail to
8652 * start up when no ports are active.
8653 */
8654 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8655 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8656 DPLS_EDP_PPS_FIX_DIS);
3bcf603f
JB		 8657 /* Without this, mode sets may fail silently on FDI */
8658 for_each_pipe(pipe)
8659 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
652c393a
JB		 8660}
8661
ac668088 8662static void ironlake_teardown_rc6(struct drm_device *dev)
0cdab21f
CW		 8663{
8664 struct drm_i915_private *dev_priv = dev->dev_private;
8665
8666 if (dev_priv->renderctx) {
ac668088
CW		 8667 i915_gem_object_unpin(dev_priv->renderctx);
8668 drm_gem_object_unreference(&dev_priv->renderctx->base);
0cdab21f
CW		 8669 dev_priv->renderctx = NULL;
8670 }
8671
8672 if (dev_priv->pwrctx) {
ac668088
CW		 8673 i915_gem_object_unpin(dev_priv->pwrctx);
8674 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8675 dev_priv->pwrctx = NULL;
8676 }
8677}
8678
8679static void ironlake_disable_rc6(struct drm_device *dev)
8680{
8681 struct drm_i915_private *dev_priv = dev->dev_private;
8682
8683 if (I915_READ(PWRCTXA)) {
8684 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8685 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8686 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8687 50);
0cdab21f
CW		 8688
8689 I915_WRITE(PWRCTXA, 0);
8690 POSTING_READ(PWRCTXA);
8691
ac668088
CW		 8692 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8693 POSTING_READ(RSTDBYCTL);
0cdab21f 8694 }
ac668088 8695
99507307 8696 ironlake_teardown_rc6(dev);
0cdab21f
CW		 8697}
8698
ac668088 8699static int ironlake_setup_rc6(struct drm_device *dev)
d5bb081b
JB		 8700{
8701 struct drm_i915_private *dev_priv = dev->dev_private;
8702
ac668088
CW		 8703 if (dev_priv->renderctx == NULL)
8704 dev_priv->renderctx = intel_alloc_context_page(dev);
8705 if (!dev_priv->renderctx)
8706 return -ENOMEM;
8707
8708 if (dev_priv->pwrctx == NULL)
8709 dev_priv->pwrctx = intel_alloc_context_page(dev);
8710 if (!dev_priv->pwrctx) {
8711 ironlake_teardown_rc6(dev);
8712 return -ENOMEM;
8713 }
8714
8715 return 0;
d5bb081b
JB		 8716}
8717
8718void ironlake_enable_rc6(struct drm_device *dev)
8719{
8720 struct drm_i915_private *dev_priv = dev->dev_private;
8721 int ret;
8722
ac668088
CW		 8723 /* rc6 disabled by default due to repeated reports of hanging during
8724 * boot and resume.
8725 */
c0f372b3 8726 if (!intel_enable_rc6(dev))
ac668088
CW		 8727 return;
8728
2c34b850 8729 mutex_lock(&dev->struct_mutex);
ac668088 8730 ret = ironlake_setup_rc6(dev);
2c34b850
BW		 8731 if (ret) {
8732 mutex_unlock(&dev->struct_mutex);
ac668088 8733 return;
2c34b850 8734 }
ac668088 8735
d5bb081b
JB		 8736 /*
8737 * GPU can automatically power down the render unit if given a page
8738 * to save state.
8739 */
8740 ret = BEGIN_LP_RING(6);
8741 if (ret) {
ac668088 8742 ironlake_teardown_rc6(dev);
2c34b850 8743 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8744 return;
8745 }
ac668088 8746
d5bb081b
JB		 8747 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8748 OUT_RING(MI_SET_CONTEXT);
8749 OUT_RING(dev_priv->renderctx->gtt_offset |
8750 MI_MM_SPACE_GTT |
8751 MI_SAVE_EXT_STATE_EN |
8752 MI_RESTORE_EXT_STATE_EN |
8753 MI_RESTORE_INHIBIT);
8754 OUT_RING(MI_SUSPEND_FLUSH);
8755 OUT_RING(MI_NOOP);
8756 OUT_RING(MI_FLUSH);
8757 ADVANCE_LP_RING();
8758
4a246cfc
BW		 8759 /*
8760 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8761 * does an implicit flush, combined with MI_FLUSH above, it should be
8762 * safe to assume that renderctx is valid
8763 */
8764 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8765 if (ret) {
8766 DRM_ERROR("failed to enable ironlake power power savings\n");
8767 ironlake_teardown_rc6(dev);
8768 mutex_unlock(&dev->struct_mutex);
8769 return;
8770 }
8771
d5bb081b
JB		 8772 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8773 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2c34b850 8774 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8775}
8776
645c62a5
JB		 8777void intel_init_clock_gating(struct drm_device *dev)
8778{
8779 struct drm_i915_private *dev_priv = dev->dev_private;
8780
8781 dev_priv->display.init_clock_gating(dev);
8782
8783 if (dev_priv->display.init_pch_clock_gating)
8784 dev_priv->display.init_pch_clock_gating(dev);
8785}
ac668088 8786
e70236a8
JB		 8787/* Set up chip specific display functions */
8788static void intel_init_display(struct drm_device *dev)
8789{
8790 struct drm_i915_private *dev_priv = dev->dev_private;
8791
8792 /* We always want a DPMS function */
f564048e 8793 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 8794 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 8795 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
17638cd6 8796 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8797 } else {
e70236a8 8798 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 8799 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
17638cd6 8800 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8801 }
e70236a8 8802
ee5382ae 8803 if (I915_HAS_FBC(dev)) {
9c04f015 8804 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 8805 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8806 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8807 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8808 } else if (IS_GM45(dev)) {
74dff282
JB		 8809 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8810 dev_priv->display.enable_fbc = g4x_enable_fbc;
8811 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 8812 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 8813 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8814 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8815 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8816 }
74dff282 8817 /* 855GM needs testing */
e70236a8
JB		 8818 }
8819
8820 /* Returns the core display clock speed */
0206e353 8821 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8822 dev_priv->display.get_display_clock_speed =
8823 i945_get_display_clock_speed;
8824 else if (IS_I915G(dev))
8825 dev_priv->display.get_display_clock_speed =
8826 i915_get_display_clock_speed;
f2b115e6 8827 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8828 dev_priv->display.get_display_clock_speed =
8829 i9xx_misc_get_display_clock_speed;
8830 else if (IS_I915GM(dev))
8831 dev_priv->display.get_display_clock_speed =
8832 i915gm_get_display_clock_speed;
8833 else if (IS_I865G(dev))
8834 dev_priv->display.get_display_clock_speed =
8835 i865_get_display_clock_speed;
f0f8a9ce 8836 else if (IS_I85X(dev))
e70236a8
JB		 8837 dev_priv->display.get_display_clock_speed =
8838 i855_get_display_clock_speed;
8839 else /* 852, 830 */
8840 dev_priv->display.get_display_clock_speed =
8841 i830_get_display_clock_speed;
8842
8843 /* For FIFO watermark updates */
7f8a8569 8844 if (HAS_PCH_SPLIT(dev)) {
8d715f00
KP		 8845 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8846 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8847
8848 /* IVB configs may use multi-threaded forcewake */
8849 if (IS_IVYBRIDGE(dev)) {
8850 u32 ecobus;
8851
c7dffff7
KP		 8852 /* A small trick here - if the bios hasn't configured MT forcewake,
8853 * and if the device is in RC6, then force_wake_mt_get will not wake
8854 * the device and the ECOBUS read will return zero. Which will be
8855 * (correctly) interpreted by the test below as MT forcewake being
8856 * disabled.
8857 */
8d715f00
KP		 8858 mutex_lock(&dev->struct_mutex);
8859 __gen6_gt_force_wake_mt_get(dev_priv);
c7dffff7 8860 ecobus = I915_READ_NOTRACE(ECOBUS);
8d715f00
KP		 8861 __gen6_gt_force_wake_mt_put(dev_priv);
8862 mutex_unlock(&dev->struct_mutex);
8863
8864 if (ecobus & FORCEWAKE_MT_ENABLE) {
8865 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8866 dev_priv->display.force_wake_get =
8867 __gen6_gt_force_wake_mt_get;
8868 dev_priv->display.force_wake_put =
8869 __gen6_gt_force_wake_mt_put;
8870 }
8871 }
8872
645c62a5
JB		 8873 if (HAS_PCH_IBX(dev))
8874 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8875 else if (HAS_PCH_CPT(dev))
8876 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8877
f00a3ddf 8878 if (IS_GEN5(dev)) {
7f8a8569
ZW		 8879 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8880 dev_priv->display.update_wm = ironlake_update_wm;
8881 else {
8882 DRM_DEBUG_KMS("Failed to get proper latency. "
8883 "Disable CxSR\n");
8884 dev_priv->display.update_wm = NULL;
1398261a 8885 }
674cf967 8886 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6067aaea 8887 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
e0dac65e 8888 dev_priv->display.write_eld = ironlake_write_eld;
1398261a
YL		 8889 } else if (IS_GEN6(dev)) {
8890 if (SNB_READ_WM0_LATENCY()) {
8891 dev_priv->display.update_wm = sandybridge_update_wm;
b840d907 8892 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
1398261a
YL		 8893 } else {
8894 DRM_DEBUG_KMS("Failed to read display plane latency. "
8895 "Disable CxSR\n");
8896 dev_priv->display.update_wm = NULL;
7f8a8569 8897 }
674cf967 8898 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6067aaea 8899 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
e0dac65e 8900 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8901 } else if (IS_IVYBRIDGE(dev)) {
8902 /* FIXME: detect B0+ stepping and use auto training */
8903 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
fe100d4d
JB		 8904 if (SNB_READ_WM0_LATENCY()) {
8905 dev_priv->display.update_wm = sandybridge_update_wm;
b840d907 8906 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
fe100d4d
JB		 8907 } else {
8908 DRM_DEBUG_KMS("Failed to read display plane latency. "
8909 "Disable CxSR\n");
8910 dev_priv->display.update_wm = NULL;
8911 }
28963a3e 8912 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
e0dac65e 8913 dev_priv->display.write_eld = ironlake_write_eld;
7f8a8569
ZW		 8914 } else
8915 dev_priv->display.update_wm = NULL;
8916 } else if (IS_PINEVIEW(dev)) {
d4294342 8917 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 8918 dev_priv->is_ddr3,
d4294342
ZY		 8919 dev_priv->fsb_freq,
8920 dev_priv->mem_freq)) {
8921 DRM_INFO("failed to find known CxSR latency "
95534263 8922 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 8923 "disabling CxSR\n",
0206e353 8924 (dev_priv->is_ddr3 == 1) ? "3" : "2",
d4294342
ZY		 8925 dev_priv->fsb_freq, dev_priv->mem_freq);
8926 /* Disable CxSR and never update its watermark again */
8927 pineview_disable_cxsr(dev);
8928 dev_priv->display.update_wm = NULL;
8929 } else
8930 dev_priv->display.update_wm = pineview_update_wm;
95e0ee92 8931 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6067aaea 8932 } else if (IS_G4X(dev)) {
e0dac65e 8933 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8934 dev_priv->display.update_wm = g4x_update_wm;
6067aaea
JB		 8935 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8936 } else if (IS_GEN4(dev)) {
e70236a8 8937 dev_priv->display.update_wm = i965_update_wm;
6067aaea
JB		 8938 if (IS_CRESTLINE(dev))
8939 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8940 else if (IS_BROADWATER(dev))
8941 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8942 } else if (IS_GEN3(dev)) {
e70236a8
JB		 8943 dev_priv->display.update_wm = i9xx_update_wm;
8944 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6067aaea
JB		 8945 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8946 } else if (IS_I865G(dev)) {
8947 dev_priv->display.update_wm = i830_update_wm;
8948 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8949 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8f4695ed
AJ		 8950 } else if (IS_I85X(dev)) {
8951 dev_priv->display.update_wm = i9xx_update_wm;
8952 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6067aaea 8953 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
e70236a8 8954 } else {
8f4695ed 8955 dev_priv->display.update_wm = i830_update_wm;
6067aaea 8956 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8f4695ed 8957 if (IS_845G(dev))
e70236a8
JB		 8958 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8959 else
8960 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8 8961 }
8c9f3aaf
JB		 8962
8963 /* Default just returns -ENODEV to indicate unsupported */
8964 dev_priv->display.queue_flip = intel_default_queue_flip;
8965
8966 switch (INTEL_INFO(dev)->gen) {
8967 case 2:
8968 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8969 break;
8970
8971 case 3:
8972 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8973 break;
8974
8975 case 4:
8976 case 5:
8977 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8978 break;
8979
8980 case 6:
8981 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8982 break;
7c9017e5
JB		 8983 case 7:
8984 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8985 break;
8c9f3aaf 8986 }
e70236a8
JB		 8987}
8988
b690e96c
JB		 8989/*
8990 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8991 * resume, or other times. This quirk makes sure that's the case for
8992 * affected systems.
8993 */
0206e353 8994static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8995{
8996 struct drm_i915_private *dev_priv = dev->dev_private;
8997
8998 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8999 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
9000}
9001
435793df
KP		 9002/*
9003 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9004 */
9005static void quirk_ssc_force_disable(struct drm_device *dev)
9006{
9007 struct drm_i915_private *dev_priv = dev->dev_private;
9008 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9009}
9010
b690e96c
JB		 9011struct intel_quirk {
9012 int device;
9013 int subsystem_vendor;
9014 int subsystem_device;
9015 void (*hook)(struct drm_device *dev);
9016};
9017
9018struct intel_quirk intel_quirks[] = {
9019 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
9020 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
9021 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9022 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c
JB		 9023
9024 /* Thinkpad R31 needs pipe A force quirk */
9025 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
9026 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9027 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9028
9029 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
9030 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
9031 /* ThinkPad X40 needs pipe A force quirk */
9032
9033 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9034 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9035
9036 /* 855 & before need to leave pipe A & dpll A up */
9037 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9038 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9039
9040 /* Lenovo U160 cannot use SSC on LVDS */
9041 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9042
9043 /* Sony Vaio Y cannot use SSC on LVDS */
9044 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
b690e96c
JB		 9045};
9046
9047static void intel_init_quirks(struct drm_device *dev)
9048{
9049 struct pci_dev *d = dev->pdev;
9050 int i;
9051
9052 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9053 struct intel_quirk *q = &intel_quirks[i];
9054
9055 if (d->device == q->device &&
9056 (d->subsystem_vendor == q->subsystem_vendor ||
9057 q->subsystem_vendor == PCI_ANY_ID) &&
9058 (d->subsystem_device == q->subsystem_device ||
9059 q->subsystem_device == PCI_ANY_ID))
9060 q->hook(dev);
9061 }
9062}
9063
9cce37f4
JB		 9064/* Disable the VGA plane that we never use */
9065static void i915_disable_vga(struct drm_device *dev)
9066{
9067 struct drm_i915_private *dev_priv = dev->dev_private;
9068 u8 sr1;
9069 u32 vga_reg;
9070
9071 if (HAS_PCH_SPLIT(dev))
9072 vga_reg = CPU_VGACNTRL;
9073 else
9074 vga_reg = VGACNTRL;
9075
9076 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9077 outb(1, VGA_SR_INDEX);
9078 sr1 = inb(VGA_SR_DATA);
9079 outb(sr1 | 1<<5, VGA_SR_DATA);
9080 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9081 udelay(300);
9082
9083 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9084 POSTING_READ(vga_reg);
9085}
9086
79e53945
JB		 9087void intel_modeset_init(struct drm_device *dev)
9088{
652c393a 9089 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 9090 int i, ret;
79e53945
JB		 9091
9092 drm_mode_config_init(dev);
9093
9094 dev->mode_config.min_width = 0;
9095 dev->mode_config.min_height = 0;
9096
9097 dev->mode_config.funcs = (void *)&intel_mode_funcs;
9098
b690e96c
JB		 9099 intel_init_quirks(dev);
9100
e70236a8
JB		 9101 intel_init_display(dev);
9102
a6c45cf0
CW		 9103 if (IS_GEN2(dev)) {
9104 dev->mode_config.max_width = 2048;
9105 dev->mode_config.max_height = 2048;
9106 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9107 dev->mode_config.max_width = 4096;
9108 dev->mode_config.max_height = 4096;
79e53945 9109 } else {
a6c45cf0
CW		 9110 dev->mode_config.max_width = 8192;
9111 dev->mode_config.max_height = 8192;
79e53945 9112 }
35c3047a 9113 dev->mode_config.fb_base = dev->agp->base;
79e53945 9114
28c97730 9115 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 9116 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 9117
a3524f1b 9118 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 9119 intel_crtc_init(dev, i);
00c2064b
JB		 9120 ret = intel_plane_init(dev, i);
9121 if (ret)
9122 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 9123 }
9124
9cce37f4
JB		 9125 /* Just disable it once at startup */
9126 i915_disable_vga(dev);
79e53945 9127 intel_setup_outputs(dev);
652c393a 9128
645c62a5 9129 intel_init_clock_gating(dev);
9cce37f4 9130
7648fa99 9131 if (IS_IRONLAKE_M(dev)) {
f97108d1 9132 ironlake_enable_drps(dev);
7648fa99
JB		 9133 intel_init_emon(dev);
9134 }
f97108d1 9135
1c70c0ce 9136 if (IS_GEN6(dev) || IS_GEN7(dev)) {
3b8d8d91 9137 gen6_enable_rps(dev_priv);
23b2f8bb
JB		 9138 gen6_update_ring_freq(dev_priv);
9139 }
3b8d8d91 9140
652c393a
JB		 9141 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9142 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9143 (unsigned long)dev);
2c7111db
CW		 9144}
9145
9146void intel_modeset_gem_init(struct drm_device *dev)
9147{
9148 if (IS_IRONLAKE_M(dev))
9149 ironlake_enable_rc6(dev);
02e792fb
DV		 9150
9151 intel_setup_overlay(dev);
79e53945
JB		 9152}
9153
9154void intel_modeset_cleanup(struct drm_device *dev)
9155{
652c393a
JB		 9156 struct drm_i915_private *dev_priv = dev->dev_private;
9157 struct drm_crtc *crtc;
9158 struct intel_crtc *intel_crtc;
9159
f87ea761 9160 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9161 mutex_lock(&dev->struct_mutex);
9162
723bfd70
JB		 9163 intel_unregister_dsm_handler();
9164
9165
652c393a
JB		 9166 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9167 /* Skip inactive CRTCs */
9168 if (!crtc->fb)
9169 continue;
9170
9171 intel_crtc = to_intel_crtc(crtc);
3dec0095 9172 intel_increase_pllclock(crtc);
652c393a
JB		 9173 }
9174
973d04f9 9175 intel_disable_fbc(dev);
e70236a8 9176
f97108d1
JB		 9177 if (IS_IRONLAKE_M(dev))
9178 ironlake_disable_drps(dev);
1c70c0ce 9179 if (IS_GEN6(dev) || IS_GEN7(dev))
3b8d8d91 9180 gen6_disable_rps(dev);
f97108d1 9181
d5bb081b
JB		 9182 if (IS_IRONLAKE_M(dev))
9183 ironlake_disable_rc6(dev);
0cdab21f 9184
69341a5e
KH		 9185 mutex_unlock(&dev->struct_mutex);
9186
6c0d9350
DV		 9187 /* Disable the irq before mode object teardown, for the irq might
9188 * enqueue unpin/hotplug work. */
9189 drm_irq_uninstall(dev);
9190 cancel_work_sync(&dev_priv->hotplug_work);
6fdd4d98 9191 cancel_work_sync(&dev_priv->rps_work);
6c0d9350 9192
1630fe75
CW		 9193 /* flush any delayed tasks or pending work */
9194 flush_scheduled_work();
9195
3dec0095
DV		 9196 /* Shut off idle work before the crtcs get freed. */
9197 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9198 intel_crtc = to_intel_crtc(crtc);
9199 del_timer_sync(&intel_crtc->idle_timer);
9200 }
9201 del_timer_sync(&dev_priv->idle_timer);
9202 cancel_work_sync(&dev_priv->idle_work);
9203
79e53945
JB		 9204 drm_mode_config_cleanup(dev);
9205}
9206
f1c79df3
ZW		 9207/*
9208 * Return which encoder is currently attached for connector.
9209 */
df0e9248 9210struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9211{
df0e9248
CW		 9212 return &intel_attached_encoder(connector)->base;
9213}
f1c79df3 9214
df0e9248
CW		 9215void intel_connector_attach_encoder(struct intel_connector *connector,
9216 struct intel_encoder *encoder)
9217{
9218 connector->encoder = encoder;
9219 drm_mode_connector_attach_encoder(&connector->base,
9220 &encoder->base);
79e53945 9221}
28d52043
DA		 9222
9223/*
9224 * set vga decode state - true == enable VGA decode
9225 */
9226int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9227{
9228 struct drm_i915_private *dev_priv = dev->dev_private;
9229 u16 gmch_ctrl;
9230
9231 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9232 if (state)
9233 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9234 else
9235 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9236 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9237 return 0;
9238}
c4a1d9e4
CW		 9239
9240#ifdef CONFIG_DEBUG_FS
9241#include <linux/seq_file.h>
9242
9243struct intel_display_error_state {
9244 struct intel_cursor_error_state {
9245 u32 control;
9246 u32 position;
9247 u32 base;
9248 u32 size;
9249 } cursor[2];
9250
9251 struct intel_pipe_error_state {
9252 u32 conf;
9253 u32 source;
9254
9255 u32 htotal;
9256 u32 hblank;
9257 u32 hsync;
9258 u32 vtotal;
9259 u32 vblank;
9260 u32 vsync;
9261 } pipe[2];
9262
9263 struct intel_plane_error_state {
9264 u32 control;
9265 u32 stride;
9266 u32 size;
9267 u32 pos;
9268 u32 addr;
9269 u32 surface;
9270 u32 tile_offset;
9271 } plane[2];
9272};
9273
9274struct intel_display_error_state *
9275intel_display_capture_error_state(struct drm_device *dev)
9276{
0206e353 9277 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9278 struct intel_display_error_state *error;
9279 int i;
9280
9281 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9282 if (error == NULL)
9283 return NULL;
9284
9285 for (i = 0; i < 2; i++) {
9286 error->cursor[i].control = I915_READ(CURCNTR(i));
9287 error->cursor[i].position = I915_READ(CURPOS(i));
9288 error->cursor[i].base = I915_READ(CURBASE(i));
9289
9290 error->plane[i].control = I915_READ(DSPCNTR(i));
9291 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9292 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9293 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9294 error->plane[i].addr = I915_READ(DSPADDR(i));
9295 if (INTEL_INFO(dev)->gen >= 4) {
9296 error->plane[i].surface = I915_READ(DSPSURF(i));
9297 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9298 }
9299
9300 error->pipe[i].conf = I915_READ(PIPECONF(i));
9301 error->pipe[i].source = I915_READ(PIPESRC(i));
9302 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9303 error->pipe[i].hblank = I915_READ(HBLANK(i));
9304 error->pipe[i].hsync = I915_READ(HSYNC(i));
9305 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9306 error->pipe[i].vblank = I915_READ(VBLANK(i));
9307 error->pipe[i].vsync = I915_READ(VSYNC(i));
9308 }
9309
9310 return error;
9311}
9312
9313void
9314intel_display_print_error_state(struct seq_file *m,
9315 struct drm_device *dev,
9316 struct intel_display_error_state *error)
9317{
9318 int i;
9319
9320 for (i = 0; i < 2; i++) {
9321 seq_printf(m, "Pipe [%d]:\n", i);
9322 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9323 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9324 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9325 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9326 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9327 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9328 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9329 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9330
9331 seq_printf(m, "Plane [%d]:\n", i);
9332 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9333 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9334 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9335 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9336 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9337 if (INTEL_INFO(dev)->gen >= 4) {
9338 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9339 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9340 }
9341
9342 seq_printf(m, "Cursor [%d]:\n", i);
9343 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9344 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9345 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9346 }
9347}
9348#endif
Linux kernel - Deliverables
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