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* elf-m10300.c (mn10300_elf_relax_section): Use _bfd_merged_section_offset
[deliverable/binutils-gdb.git] / opcodes / i386-dis.c
CommitLineData
252b5132 1/* Print i386 instructions for GDB, the GNU debugger.
060d22b0 2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
9b201bb5 3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
252b5132 4
9b201bb5 5 This file is part of the GNU opcodes library.
20f0a1fc 6
9b201bb5 7 This library is free software; you can redistribute it and/or modify
20f0a1fc 8 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
20f0a1fc 11
9b201bb5
NC		 12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
20f0a1fc
NC		 16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
9b201bb5
NC		 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
20f0a1fc
NC		 22
23/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 July 1988
25 modified by John Hassey (hassey@dg-rtp.dg.com)
26 x86-64 support added by Jan Hubicka (jh@suse.cz)
27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28
29/* The main tables describing the instructions is essentially a copy
30 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
31 Programmers Manual. Usually, there is a capital letter, followed
32 by a small letter. The capital letter tell the addressing mode,
33 and the small letter tells about the operand size. Refer to
34 the Intel manual for details. */
252b5132 35
252b5132 36#include "sysdep.h"
dabbade6 37#include "dis-asm.h"
252b5132 38#include "opintl.h"
0b1cf022 39#include "opcode/i386.h"
85f10a01 40#include "libiberty.h"
252b5132
RH		 41
42#include <setjmp.h>
43
26ca5450
AJ		 44static int fetch_data (struct disassemble_info *, bfd_byte *);
45static void ckprefix (void);
46static const char *prefix_name (int, int);
47static int print_insn (bfd_vma, disassemble_info *);
48static void dofloat (int);
49static void OP_ST (int, int);
50static void OP_STi (int, int);
51static int putop (const char *, int);
52static void oappend (const char *);
53static void append_seg (void);
54static void OP_indirE (int, int);
55static void print_operand_value (char *, int, bfd_vma);
85f10a01 56static void OP_E_extended (int, int, int);
5d669648 57static void print_displacement (char *, bfd_vma);
26ca5450
AJ		 58static void OP_E (int, int);
59static void OP_G (int, int);
60static bfd_vma get64 (void);
61static bfd_signed_vma get32 (void);
62static bfd_signed_vma get32s (void);
63static int get16 (void);
64static void set_op (bfd_vma, int);
b844680a 65static void OP_Skip_MODRM (int, int);
26ca5450
AJ		 66static void OP_REG (int, int);
67static void OP_IMREG (int, int);
68static void OP_I (int, int);
69static void OP_I64 (int, int);
70static void OP_sI (int, int);
71static void OP_J (int, int);
72static void OP_SEG (int, int);
73static void OP_DIR (int, int);
74static void OP_OFF (int, int);
75static void OP_OFF64 (int, int);
76static void ptr_reg (int, int);
77static void OP_ESreg (int, int);
78static void OP_DSreg (int, int);
79static void OP_C (int, int);
80static void OP_D (int, int);
81static void OP_T (int, int);
6f74c397 82static void OP_R (int, int);
26ca5450
AJ		 83static void OP_MMX (int, int);
84static void OP_XMM (int, int);
85static void OP_EM (int, int);
86static void OP_EX (int, int);
4d9567e0
MM		 87static void OP_EMC (int,int);
88static void OP_MXC (int,int);
26ca5450
AJ		 89static void OP_MS (int, int);
90static void OP_XS (int, int);
cc0ec051 91static void OP_M (int, int);
cc0ec051 92static void OP_0f07 (int, int);
b844680a
L		 93static void OP_Monitor (int, int);
94static void OP_Mwait (int, int);
46e883c5
L		 95static void NOP_Fixup1 (int, int);
96static void NOP_Fixup2 (int, int);
26ca5450 97static void OP_3DNowSuffix (int, int);
ad19981d 98static void CMP_Fixup (int, int);
26ca5450 99static void BadOp (void);
35c52694 100static void REP_Fixup (int, int);
f5804c90 101static void CMPXCHG8B_Fixup (int, int);
42903f7f 102static void XMM_Fixup (int, int);
381d071f 103static void CRC32_Fixup (int, int);
85f10a01
MM		 104static void print_drex_arg (unsigned int, int, int);
105static void OP_DREX4 (int, int);
106static void OP_DREX3 (int, int);
107static void OP_DREX_ICMP (int, int);
108static void OP_DREX_FCMP (int, int);
252b5132 109
6608db57 110struct dis_private {
252b5132
RH		 111 /* Points to first byte not fetched. */
112 bfd_byte *max_fetched;
0b1cf022 113 bfd_byte the_buffer[MAX_MNEM_SIZE];
252b5132 114 bfd_vma insn_start;
e396998b 115 int orig_sizeflag;
252b5132
RH		 116 jmp_buf bailout;
117};
118
cb712a9e
L		 119enum address_mode
120{
121 mode_16bit,
122 mode_32bit,
123 mode_64bit
124};
125
126enum address_mode address_mode;
52b15da3 127
5076851f
ILT		 128/* Flags for the prefixes for the current instruction. See below. */
129static int prefixes;
130
52b15da3
JH		 131/* REX prefix the current instruction. See below. */
132static int rex;
133/* Bits of REX we've already used. */
134static int rex_used;
52b15da3
JH		 135/* Mark parts used in the REX prefix. When we are testing for
136 empty prefix (for 8bit register REX extension), just mask it
137 out. Otherwise test for REX bit is excuse for existence of REX
138 only in case value is nonzero. */
139#define USED_REX(value) \
140 { \
141 if (value) \
161a04f6
L		 142 { \
143 if ((rex & value)) \
144 rex_used |= (value) | REX_OPCODE; \
145 } \
52b15da3 146 else \
161a04f6 147 rex_used |= REX_OPCODE; \
52b15da3
JH		 148 }
149
85f10a01
MM		 150/* Special 'registers' for DREX handling */
151#define DREX_REG_UNKNOWN 1000 /* not initialized */
152#define DREX_REG_MEMORY 1001 /* use MODRM/SIB/OFFSET memory */
153
154/* The DREX byte has the following fields:
155 Bits 7-4 -- DREX.Dest, xmm destination register
156 Bit 3 -- DREX.OC0, operand config bit defines operand order
157 Bit 2 -- DREX.R, equivalent to REX_R bit, to extend ModRM register
158 Bit 1 -- DREX.X, equivalent to REX_X bit, to extend SIB index field
159 Bit 0 -- DREX.W, equivalent to REX_B bit, to extend ModRM r/m field,
160 SIB base field, or opcode reg field. */
161#define DREX_XMM(drex) ((drex >> 4) & 0xf)
162#define DREX_OC0(drex) ((drex >> 3) & 0x1)
163
7d421014
ILT		 164/* Flags for prefixes which we somehow handled when printing the
165 current instruction. */
166static int used_prefixes;
167
5076851f
ILT		 168/* Flags stored in PREFIXES. */
169#define PREFIX_REPZ 1
170#define PREFIX_REPNZ 2
171#define PREFIX_LOCK 4
172#define PREFIX_CS 8
173#define PREFIX_SS 0x10
174#define PREFIX_DS 0x20
175#define PREFIX_ES 0x40
176#define PREFIX_FS 0x80
177#define PREFIX_GS 0x100
178#define PREFIX_DATA 0x200
179#define PREFIX_ADDR 0x400
180#define PREFIX_FWAIT 0x800
181
252b5132
RH		 182/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
183 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
184 on error. */
185#define FETCH_DATA(info, addr) \
6608db57 186 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
252b5132
RH		 187 ? 1 : fetch_data ((info), (addr)))
188
189static int
26ca5450 190fetch_data (struct disassemble_info *info, bfd_byte *addr)
252b5132
RH		 191{
192 int status;
6608db57 193 struct dis_private *priv = (struct dis_private *) info->private_data;
252b5132
RH		 194 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
195
0b1cf022 196 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
272c9217
JB		 197 status = (*info->read_memory_func) (start,
198 priv->max_fetched,
199 addr - priv->max_fetched,
200 info);
201 else
202 status = -1;
252b5132
RH		 203 if (status != 0)
204 {
7d421014 205 /* If we did manage to read at least one byte, then
db6eb5be
AM		 206 print_insn_i386 will do something sensible. Otherwise, print
207 an error. We do that here because this is where we know
208 STATUS. */
7d421014 209 if (priv->max_fetched == priv->the_buffer)
5076851f 210 (*info->memory_error_func) (status, start, info);
252b5132
RH		 211 longjmp (priv->bailout, 1);
212 }
213 else
214 priv->max_fetched = addr;
215 return 1;
216}
217
ce518a5f
L		 218#define XX { NULL, 0 }
219
220#define Eb { OP_E, b_mode }
221#define Ev { OP_E, v_mode }
222#define Ed { OP_E, d_mode }
223#define Edq { OP_E, dq_mode }
224#define Edqw { OP_E, dqw_mode }
42903f7f
L		 225#define Edqb { OP_E, dqb_mode }
226#define Edqd { OP_E, dqd_mode }
09335d05 227#define Eq { OP_E, q_mode }
ce518a5f
L		 228#define indirEv { OP_indirE, stack_v_mode }
229#define indirEp { OP_indirE, f_mode }
230#define stackEv { OP_E, stack_v_mode }
231#define Em { OP_E, m_mode }
232#define Ew { OP_E, w_mode }
233#define M { OP_M, 0 } /* lea, lgdt, etc. */
234#define Ma { OP_M, v_mode }
b844680a 235#define Mb { OP_M, b_mode }
d9a5e5e5 236#define Md { OP_M, d_mode }
ce518a5f
L		 237#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
238#define Mq { OP_M, q_mode }
239#define Gb { OP_G, b_mode }
240#define Gv { OP_G, v_mode }
241#define Gd { OP_G, d_mode }
242#define Gdq { OP_G, dq_mode }
243#define Gm { OP_G, m_mode }
244#define Gw { OP_G, w_mode }
6f74c397
L		 245#define Rd { OP_R, d_mode }
246#define Rm { OP_R, m_mode }
ce518a5f
L		 247#define Ib { OP_I, b_mode }
248#define sIb { OP_sI, b_mode } /* sign extened byte */
249#define Iv { OP_I, v_mode }
250#define Iq { OP_I, q_mode }
251#define Iv64 { OP_I64, v_mode }
252#define Iw { OP_I, w_mode }
253#define I1 { OP_I, const_1_mode }
254#define Jb { OP_J, b_mode }
255#define Jv { OP_J, v_mode }
256#define Cm { OP_C, m_mode }
257#define Dm { OP_D, m_mode }
258#define Td { OP_T, d_mode }
b844680a 259#define Skip_MODRM { OP_Skip_MODRM, 0 }
ce518a5f
L		 260
261#define RMeAX { OP_REG, eAX_reg }
262#define RMeBX { OP_REG, eBX_reg }
263#define RMeCX { OP_REG, eCX_reg }
264#define RMeDX { OP_REG, eDX_reg }
265#define RMeSP { OP_REG, eSP_reg }
266#define RMeBP { OP_REG, eBP_reg }
267#define RMeSI { OP_REG, eSI_reg }
268#define RMeDI { OP_REG, eDI_reg }
269#define RMrAX { OP_REG, rAX_reg }
270#define RMrBX { OP_REG, rBX_reg }
271#define RMrCX { OP_REG, rCX_reg }
272#define RMrDX { OP_REG, rDX_reg }
273#define RMrSP { OP_REG, rSP_reg }
274#define RMrBP { OP_REG, rBP_reg }
275#define RMrSI { OP_REG, rSI_reg }
276#define RMrDI { OP_REG, rDI_reg }
277#define RMAL { OP_REG, al_reg }
278#define RMAL { OP_REG, al_reg }
279#define RMCL { OP_REG, cl_reg }
280#define RMDL { OP_REG, dl_reg }
281#define RMBL { OP_REG, bl_reg }
282#define RMAH { OP_REG, ah_reg }
283#define RMCH { OP_REG, ch_reg }
284#define RMDH { OP_REG, dh_reg }
285#define RMBH { OP_REG, bh_reg }
286#define RMAX { OP_REG, ax_reg }
287#define RMDX { OP_REG, dx_reg }
288
289#define eAX { OP_IMREG, eAX_reg }
290#define eBX { OP_IMREG, eBX_reg }
291#define eCX { OP_IMREG, eCX_reg }
292#define eDX { OP_IMREG, eDX_reg }
293#define eSP { OP_IMREG, eSP_reg }
294#define eBP { OP_IMREG, eBP_reg }
295#define eSI { OP_IMREG, eSI_reg }
296#define eDI { OP_IMREG, eDI_reg }
297#define AL { OP_IMREG, al_reg }
298#define CL { OP_IMREG, cl_reg }
299#define DL { OP_IMREG, dl_reg }
300#define BL { OP_IMREG, bl_reg }
301#define AH { OP_IMREG, ah_reg }
302#define CH { OP_IMREG, ch_reg }
303#define DH { OP_IMREG, dh_reg }
304#define BH { OP_IMREG, bh_reg }
305#define AX { OP_IMREG, ax_reg }
306#define DX { OP_IMREG, dx_reg }
307#define zAX { OP_IMREG, z_mode_ax_reg }
308#define indirDX { OP_IMREG, indir_dx_reg }
309
310#define Sw { OP_SEG, w_mode }
311#define Sv { OP_SEG, v_mode }
312#define Ap { OP_DIR, 0 }
313#define Ob { OP_OFF64, b_mode }
314#define Ov { OP_OFF64, v_mode }
315#define Xb { OP_DSreg, eSI_reg }
316#define Xv { OP_DSreg, eSI_reg }
317#define Xz { OP_DSreg, eSI_reg }
318#define Yb { OP_ESreg, eDI_reg }
319#define Yv { OP_ESreg, eDI_reg }
320#define DSBX { OP_DSreg, eBX_reg }
321
322#define es { OP_REG, es_reg }
323#define ss { OP_REG, ss_reg }
324#define cs { OP_REG, cs_reg }
325#define ds { OP_REG, ds_reg }
326#define fs { OP_REG, fs_reg }
327#define gs { OP_REG, gs_reg }
328
329#define MX { OP_MMX, 0 }
330#define XM { OP_XMM, 0 }
331#define EM { OP_EM, v_mode }
09a2c6cf 332#define EMd { OP_EM, d_mode }
14051056 333#define EMx { OP_EM, x_mode }
8976381e 334#define EXw { OP_EX, w_mode }
09a2c6cf
L		 335#define EXd { OP_EX, d_mode }
336#define EXq { OP_EX, q_mode }
337#define EXx { OP_EX, x_mode }
ce518a5f
L		 338#define MS { OP_MS, v_mode }
339#define XS { OP_XS, v_mode }
09335d05 340#define EMCq { OP_EMC, q_mode }
ce518a5f 341#define MXC { OP_MXC, 0 }
ce518a5f 342#define OPSUF { OP_3DNowSuffix, 0 }
ad19981d 343#define CMP { CMP_Fixup, 0 }
42903f7f 344#define XMM0 { XMM_Fixup, 0 }
252b5132 345
35c52694 346/* Used handle "rep" prefix for string instructions. */
ce518a5f
L		 347#define Xbr { REP_Fixup, eSI_reg }
348#define Xvr { REP_Fixup, eSI_reg }
349#define Ybr { REP_Fixup, eDI_reg }
350#define Yvr { REP_Fixup, eDI_reg }
351#define Yzr { REP_Fixup, eDI_reg }
352#define indirDXr { REP_Fixup, indir_dx_reg }
353#define ALr { REP_Fixup, al_reg }
354#define eAXr { REP_Fixup, eAX_reg }
355
356#define cond_jump_flag { NULL, cond_jump_mode }
357#define loop_jcxz_flag { NULL, loop_jcxz_mode }
3ffd33cf 358
252b5132 359/* bits in sizeflag */
252b5132 360#define SUFFIX_ALWAYS 4
252b5132
RH		 361#define AFLAG 2
362#define DFLAG 1
363
d55ee72f
L		 364/* byte operand */
365#define b_mode 1
366/* operand size depends on prefixes */
630c2cc5 367#define v_mode (b_mode + 1)
d55ee72f
L		 368/* word operand */
369#define w_mode (v_mode + 1)
370/* double word operand */
371#define d_mode (w_mode + 1)
372/* quad word operand */
373#define q_mode (d_mode + 1)
374/* ten-byte operand */
375#define t_mode (q_mode + 1)
376/* 16-byte XMM operand */
377#define x_mode (t_mode + 1)
378/* d_mode in 32bit, q_mode in 64bit mode. */
379#define m_mode (x_mode + 1)
380#define cond_jump_mode (m_mode + 1)
381#define loop_jcxz_mode (cond_jump_mode + 1)
382/* operand size depends on REX prefixes. */
383#define dq_mode (loop_jcxz_mode + 1)
384/* registers like dq_mode, memory like w_mode. */
385#define dqw_mode (dq_mode + 1)
386/* 4- or 6-byte pointer operand */
387#define f_mode (dqw_mode + 1)
388#define const_1_mode (f_mode + 1)
389/* v_mode for stack-related opcodes. */
390#define stack_v_mode (const_1_mode + 1)
391/* non-quad operand size depends on prefixes */
392#define z_mode (stack_v_mode + 1)
393/* 16-byte operand */
394#define o_mode (z_mode + 1)
395/* registers like dq_mode, memory like b_mode. */
396#define dqb_mode (o_mode + 1)
397/* registers like dq_mode, memory like d_mode. */
398#define dqd_mode (dqb_mode + 1)
399
400#define es_reg (dqd_mode + 1)
401#define cs_reg (es_reg + 1)
402#define ss_reg (cs_reg + 1)
403#define ds_reg (ss_reg + 1)
404#define fs_reg (ds_reg + 1)
405#define gs_reg (fs_reg + 1)
406
407#define eAX_reg (gs_reg + 1)
408#define eCX_reg (eAX_reg + 1)
409#define eDX_reg (eCX_reg + 1)
410#define eBX_reg (eDX_reg + 1)
411#define eSP_reg (eBX_reg + 1)
412#define eBP_reg (eSP_reg + 1)
413#define eSI_reg (eBP_reg + 1)
414#define eDI_reg (eSI_reg + 1)
415
416#define al_reg (eDI_reg + 1)
417#define cl_reg (al_reg + 1)
418#define dl_reg (cl_reg + 1)
419#define bl_reg (dl_reg + 1)
420#define ah_reg (bl_reg + 1)
421#define ch_reg (ah_reg + 1)
422#define dh_reg (ch_reg + 1)
423#define bh_reg (dh_reg + 1)
424
425#define ax_reg (bh_reg + 1)
426#define cx_reg (ax_reg + 1)
427#define dx_reg (cx_reg + 1)
428#define bx_reg (dx_reg + 1)
429#define sp_reg (bx_reg + 1)
430#define bp_reg (sp_reg + 1)
431#define si_reg (bp_reg + 1)
432#define di_reg (si_reg + 1)
433
434#define rAX_reg (di_reg + 1)
435#define rCX_reg (rAX_reg + 1)
436#define rDX_reg (rCX_reg + 1)
437#define rBX_reg (rDX_reg + 1)
438#define rSP_reg (rBX_reg + 1)
439#define rBP_reg (rSP_reg + 1)
440#define rSI_reg (rBP_reg + 1)
441#define rDI_reg (rSI_reg + 1)
442
443#define z_mode_ax_reg (rDI_reg + 1)
444#define indir_dx_reg (z_mode_ax_reg + 1)
445
446#define MAX_BYTEMODE indir_dx_reg
447
448/* Flags that are OR'ed into the bytemode field to pass extra
449 information. */
450#define DREX_OC1 0x10000 /* OC1 bit set */
451#define DREX_NO_OC0 0x20000 /* OC0 bit not used */
452#define DREX_MASK 0x40000 /* mask to delete */
453
454#if MAX_BYTEMODE >= DREX_OC1
455#error MAX_BYTEMODE must be less than DREX_OC1
456#endif
252b5132 457
1b0d430b
L		 458#define FLOATCODE 1
459#define USE_REG_TABLE (FLOATCODE + 1)
460#define USE_MOD_TABLE (USE_REG_TABLE + 1)
461#define USE_RM_TABLE (USE_MOD_TABLE + 1)
462#define USE_PREFIX_TABLE (USE_RM_TABLE + 1)
463#define USE_X86_64_TABLE (USE_PREFIX_TABLE + 1)
464#define USE_3BYTE_TABLE (USE_X86_64_TABLE + 1)
6439fc28 465
1ceb70f8 466#define FLOAT NULL, { { NULL, FLOATCODE } }
4efba78c 467
4e7d34a6 468#define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
1ceb70f8
L		 469#define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
470#define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
471#define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
472#define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
4e7d34a6
L		 473#define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
474#define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
1ceb70f8
L		 475
476#define REG_80 0
477#define REG_81 (REG_80 + 1)
478#define REG_82 (REG_81 + 1)
479#define REG_8F (REG_82 + 1)
480#define REG_C0 (REG_8F + 1)
481#define REG_C1 (REG_C0 + 1)
482#define REG_C6 (REG_C1 + 1)
483#define REG_C7 (REG_C6 + 1)
484#define REG_D0 (REG_C7 + 1)
485#define REG_D1 (REG_D0 + 1)
486#define REG_D2 (REG_D1 + 1)
487#define REG_D3 (REG_D2 + 1)
488#define REG_F6 (REG_D3 + 1)
489#define REG_F7 (REG_F6 + 1)
490#define REG_FE (REG_F7 + 1)
491#define REG_FF (REG_FE + 1)
492#define REG_0F00 (REG_FF + 1)
493#define REG_0F01 (REG_0F00 + 1)
494#define REG_0F0E (REG_0F01 + 1)
495#define REG_0F18 (REG_0F0E + 1)
496#define REG_0F71 (REG_0F18 + 1)
497#define REG_0F72 (REG_0F71 + 1)
498#define REG_0F73 (REG_0F72 + 1)
499#define REG_0FA6 (REG_0F73 + 1)
500#define REG_0FA7 (REG_0FA6 + 1)
501#define REG_0FAE (REG_0FA7 + 1)
502#define REG_0FBA (REG_0FAE + 1)
503#define REG_0FC7 (REG_0FBA + 1)
504
505#define MOD_8D 0
92fddf8e 506#define MOD_0F01_REG_0 (MOD_8D + 1)
1ceb70f8
L		 507#define MOD_0F01_REG_1 (MOD_0F01_REG_0 + 1)
508#define MOD_0F01_REG_2 (MOD_0F01_REG_1 + 1)
509#define MOD_0F01_REG_3 (MOD_0F01_REG_2 + 1)
510#define MOD_0F01_REG_7 (MOD_0F01_REG_3 + 1)
92fddf8e
L		 511#define MOD_0F12_PREFIX_0 (MOD_0F01_REG_7 + 1)
512#define MOD_0F13 (MOD_0F12_PREFIX_0 + 1)
513#define MOD_0F16_PREFIX_0 (MOD_0F13 + 1)
514#define MOD_0F17 (MOD_0F16_PREFIX_0 + 1)
515#define MOD_0F18_REG_0 (MOD_0F17 + 1)
1ceb70f8
L		 516#define MOD_0F18_REG_1 (MOD_0F18_REG_0 + 1)
517#define MOD_0F18_REG_2 (MOD_0F18_REG_1 + 1)
518#define MOD_0F18_REG_3 (MOD_0F18_REG_2 + 1)
92fddf8e
L		 519#define MOD_0F20 (MOD_0F18_REG_3 + 1)
520#define MOD_0F21 (MOD_0F20 + 1)
521#define MOD_0F22 (MOD_0F21 + 1)
522#define MOD_0F23 (MOD_0F22 + 1)
523#define MOD_0F24 (MOD_0F23 + 1)
524#define MOD_0F26 (MOD_0F24 + 1)
75c135a8
L		 525#define MOD_0F2B_PREFIX_0 (MOD_0F26 + 1)
526#define MOD_0F2B_PREFIX_1 (MOD_0F2B_PREFIX_0 + 1)
527#define MOD_0F2B_PREFIX_2 (MOD_0F2B_PREFIX_1 + 1)
528#define MOD_0F2B_PREFIX_3 (MOD_0F2B_PREFIX_2 + 1)
529#define MOD_0F51 (MOD_0F2B_PREFIX_3 + 1)
530#define MOD_0F71_REG_2 (MOD_0F51 + 1)
1ceb70f8
L		 531#define MOD_0F71_REG_4 (MOD_0F71_REG_2 + 1)
532#define MOD_0F71_REG_6 (MOD_0F71_REG_4 + 1)
533#define MOD_0F72_REG_2 (MOD_0F71_REG_6 + 1)
534#define MOD_0F72_REG_4 (MOD_0F72_REG_2 + 1)
535#define MOD_0F72_REG_6 (MOD_0F72_REG_4 + 1)
536#define MOD_0F73_REG_2 (MOD_0F72_REG_6 + 1)
537#define MOD_0F73_REG_3 (MOD_0F73_REG_2 + 1)
538#define MOD_0F73_REG_6 (MOD_0F73_REG_3 + 1)
539#define MOD_0F73_REG_7 (MOD_0F73_REG_6 + 1)
540#define MOD_0FAE_REG_0 (MOD_0F73_REG_7 + 1)
541#define MOD_0FAE_REG_1 (MOD_0FAE_REG_0 + 1)
542#define MOD_0FAE_REG_2 (MOD_0FAE_REG_1 + 1)
543#define MOD_0FAE_REG_3 (MOD_0FAE_REG_2 + 1)
544#define MOD_0FAE_REG_5 (MOD_0FAE_REG_3 + 1)
545#define MOD_0FAE_REG_6 (MOD_0FAE_REG_5 + 1)
546#define MOD_0FAE_REG_7 (MOD_0FAE_REG_6 + 1)
92fddf8e
L		 547#define MOD_0FB2 (MOD_0FAE_REG_7 + 1)
548#define MOD_0FB4 (MOD_0FB2 + 1)
549#define MOD_0FB5 (MOD_0FB4 + 1)
550#define MOD_0FC7_REG_6 (MOD_0FB5 + 1)
1ceb70f8 551#define MOD_0FC7_REG_7 (MOD_0FC7_REG_6 + 1)
75c135a8
L		 552#define MOD_0FD7 (MOD_0FC7_REG_7 + 1)
553#define MOD_0FE7_PREFIX_2 (MOD_0FD7 + 1)
554#define MOD_0FF0_PREFIX_3 (MOD_0FE7_PREFIX_2 + 1)
555#define MOD_0F382A_PREFIX_2 (MOD_0FF0_PREFIX_3 + 1)
556#define MOD_62_32BIT (MOD_0F382A_PREFIX_2 + 1)
1ceb70f8
L		 557#define MOD_C4_32BIT (MOD_62_32BIT + 1)
558#define MOD_C5_32BIT (MOD_C4_32BIT + 1)
559
560#define RM_0F01_REG_0 0
561#define RM_0F01_REG_1 (RM_0F01_REG_0 + 1)
562#define RM_0F01_REG_3 (RM_0F01_REG_1 + 1)
563#define RM_0F01_REG_7 (RM_0F01_REG_3 + 1)
564#define RM_0FAE_REG_5 (RM_0F01_REG_7 + 1)
565#define RM_0FAE_REG_6 (RM_0FAE_REG_5 + 1)
566#define RM_0FAE_REG_7 (RM_0FAE_REG_6 + 1)
567
568#define PREFIX_90 0
569#define PREFIX_0F10 (PREFIX_90 + 1)
570#define PREFIX_0F11 (PREFIX_0F10 + 1)
571#define PREFIX_0F12 (PREFIX_0F11 + 1)
572#define PREFIX_0F16 (PREFIX_0F12 + 1)
573#define PREFIX_0F2A (PREFIX_0F16 + 1)
574#define PREFIX_0F2B (PREFIX_0F2A + 1)
575#define PREFIX_0F2C (PREFIX_0F2B + 1)
576#define PREFIX_0F2D (PREFIX_0F2C + 1)
577#define PREFIX_0F2E (PREFIX_0F2D + 1)
578#define PREFIX_0F2F (PREFIX_0F2E + 1)
579#define PREFIX_0F51 (PREFIX_0F2F + 1)
580#define PREFIX_0F52 (PREFIX_0F51 + 1)
581#define PREFIX_0F53 (PREFIX_0F52 + 1)
582#define PREFIX_0F58 (PREFIX_0F53 + 1)
583#define PREFIX_0F59 (PREFIX_0F58 + 1)
584#define PREFIX_0F5A (PREFIX_0F59 + 1)
585#define PREFIX_0F5B (PREFIX_0F5A + 1)
586#define PREFIX_0F5C (PREFIX_0F5B + 1)
587#define PREFIX_0F5D (PREFIX_0F5C + 1)
588#define PREFIX_0F5E (PREFIX_0F5D + 1)
589#define PREFIX_0F5F (PREFIX_0F5E + 1)
590#define PREFIX_0F60 (PREFIX_0F5F + 1)
591#define PREFIX_0F61 (PREFIX_0F60 + 1)
592#define PREFIX_0F62 (PREFIX_0F61 + 1)
593#define PREFIX_0F6C (PREFIX_0F62 + 1)
594#define PREFIX_0F6D (PREFIX_0F6C + 1)
595#define PREFIX_0F6F (PREFIX_0F6D + 1)
596#define PREFIX_0F70 (PREFIX_0F6F + 1)
92fddf8e
L		 597#define PREFIX_0F73_REG_3 (PREFIX_0F70 + 1)
598#define PREFIX_0F73_REG_7 (PREFIX_0F73_REG_3 + 1)
599#define PREFIX_0F78 (PREFIX_0F73_REG_7 + 1)
1ceb70f8
L		 600#define PREFIX_0F79 (PREFIX_0F78 + 1)
601#define PREFIX_0F7C (PREFIX_0F79 + 1)
602#define PREFIX_0F7D (PREFIX_0F7C + 1)
603#define PREFIX_0F7E (PREFIX_0F7D + 1)
604#define PREFIX_0F7F (PREFIX_0F7E + 1)
605#define PREFIX_0FB8 (PREFIX_0F7F + 1)
606#define PREFIX_0FBD (PREFIX_0FB8 + 1)
607#define PREFIX_0FC2 (PREFIX_0FBD + 1)
92fddf8e
L		 608#define PREFIX_0FC7_REG_6 (PREFIX_0FC2 + 1)
609#define PREFIX_0FD0 (PREFIX_0FC7_REG_6 + 1)
1ceb70f8
L		 610#define PREFIX_0FD6 (PREFIX_0FD0 + 1)
611#define PREFIX_0FE6 (PREFIX_0FD6 + 1)
612#define PREFIX_0FE7 (PREFIX_0FE6 + 1)
613#define PREFIX_0FF0 (PREFIX_0FE7 + 1)
614#define PREFIX_0FF7 (PREFIX_0FF0 + 1)
615#define PREFIX_0F3810 (PREFIX_0FF7 + 1)
616#define PREFIX_0F3814 (PREFIX_0F3810 + 1)
617#define PREFIX_0F3815 (PREFIX_0F3814 + 1)
618#define PREFIX_0F3817 (PREFIX_0F3815 + 1)
619#define PREFIX_0F3820 (PREFIX_0F3817 + 1)
620#define PREFIX_0F3821 (PREFIX_0F3820 + 1)
621#define PREFIX_0F3822 (PREFIX_0F3821 + 1)
622#define PREFIX_0F3823 (PREFIX_0F3822 + 1)
623#define PREFIX_0F3824 (PREFIX_0F3823 + 1)
624#define PREFIX_0F3825 (PREFIX_0F3824 + 1)
625#define PREFIX_0F3828 (PREFIX_0F3825 + 1)
626#define PREFIX_0F3829 (PREFIX_0F3828 + 1)
627#define PREFIX_0F382A (PREFIX_0F3829 + 1)
628#define PREFIX_0F382B (PREFIX_0F382A + 1)
629#define PREFIX_0F3830 (PREFIX_0F382B + 1)
630#define PREFIX_0F3831 (PREFIX_0F3830 + 1)
631#define PREFIX_0F3832 (PREFIX_0F3831 + 1)
632#define PREFIX_0F3833 (PREFIX_0F3832 + 1)
633#define PREFIX_0F3834 (PREFIX_0F3833 + 1)
634#define PREFIX_0F3835 (PREFIX_0F3834 + 1)
635#define PREFIX_0F3837 (PREFIX_0F3835 + 1)
636#define PREFIX_0F3838 (PREFIX_0F3837 + 1)
637#define PREFIX_0F3839 (PREFIX_0F3838 + 1)
638#define PREFIX_0F383A (PREFIX_0F3839 + 1)
639#define PREFIX_0F383B (PREFIX_0F383A + 1)
640#define PREFIX_0F383C (PREFIX_0F383B + 1)
641#define PREFIX_0F383D (PREFIX_0F383C + 1)
642#define PREFIX_0F383E (PREFIX_0F383D + 1)
643#define PREFIX_0F383F (PREFIX_0F383E + 1)
644#define PREFIX_0F3840 (PREFIX_0F383F + 1)
645#define PREFIX_0F3841 (PREFIX_0F3840 + 1)
646#define PREFIX_0F38F0 (PREFIX_0F3841 + 1)
647#define PREFIX_0F38F1 (PREFIX_0F38F0 + 1)
648#define PREFIX_0F3A08 (PREFIX_0F38F1 + 1)
649#define PREFIX_0F3A09 (PREFIX_0F3A08 + 1)
650#define PREFIX_0F3A0A (PREFIX_0F3A09 + 1)
651#define PREFIX_0F3A0B (PREFIX_0F3A0A + 1)
652#define PREFIX_0F3A0C (PREFIX_0F3A0B + 1)
653#define PREFIX_0F3A0D (PREFIX_0F3A0C + 1)
654#define PREFIX_0F3A0E (PREFIX_0F3A0D + 1)
655#define PREFIX_0F3A14 (PREFIX_0F3A0E + 1)
656#define PREFIX_0F3A15 (PREFIX_0F3A14 + 1)
657#define PREFIX_0F3A16 (PREFIX_0F3A15 + 1)
658#define PREFIX_0F3A17 (PREFIX_0F3A16 + 1)
659#define PREFIX_0F3A20 (PREFIX_0F3A17 + 1)
660#define PREFIX_0F3A21 (PREFIX_0F3A20 + 1)
661#define PREFIX_0F3A22 (PREFIX_0F3A21 + 1)
662#define PREFIX_0F3A40 (PREFIX_0F3A22 + 1)
663#define PREFIX_0F3A41 (PREFIX_0F3A40 + 1)
664#define PREFIX_0F3A42 (PREFIX_0F3A41 + 1)
665#define PREFIX_0F3A60 (PREFIX_0F3A42 + 1)
666#define PREFIX_0F3A61 (PREFIX_0F3A60 + 1)
667#define PREFIX_0F3A62 (PREFIX_0F3A61 + 1)
668#define PREFIX_0F3A63 (PREFIX_0F3A62 + 1)
4e7d34a6
L		 669
670#define X86_64_06 0
671#define X86_64_07 (X86_64_06 + 1)
672#define X86_64_0D (X86_64_07 + 1)
673#define X86_64_16 (X86_64_0D + 1)
674#define X86_64_17 (X86_64_16 + 1)
675#define X86_64_1E (X86_64_17 + 1)
676#define X86_64_1F (X86_64_1E + 1)
677#define X86_64_27 (X86_64_1F + 1)
678#define X86_64_2F (X86_64_27 + 1)
679#define X86_64_37 (X86_64_2F + 1)
680#define X86_64_3F (X86_64_37 + 1)
681#define X86_64_60 (X86_64_3F + 1)
682#define X86_64_61 (X86_64_60 + 1)
683#define X86_64_62 (X86_64_61 + 1)
684#define X86_64_63 (X86_64_62 + 1)
685#define X86_64_6D (X86_64_63 + 1)
686#define X86_64_6F (X86_64_6D + 1)
687#define X86_64_9A (X86_64_6F + 1)
688#define X86_64_C4 (X86_64_9A + 1)
689#define X86_64_C5 (X86_64_C4 + 1)
690#define X86_64_CE (X86_64_C5 + 1)
691#define X86_64_D4 (X86_64_CE + 1)
692#define X86_64_D5 (X86_64_D4 + 1)
693#define X86_64_EA (X86_64_D5 + 1)
694#define X86_64_0F01_REG_0 (X86_64_EA + 1)
695#define X86_64_0F01_REG_1 (X86_64_0F01_REG_0 + 1)
696#define X86_64_0F01_REG_2 (X86_64_0F01_REG_1 + 1)
697#define X86_64_0F01_REG_3 (X86_64_0F01_REG_2 + 1)
698
699#define THREE_BYTE_0F24 0
700#define THREE_BYTE_0F25 (THREE_BYTE_0F24 + 1)
701#define THREE_BYTE_0F38 (THREE_BYTE_0F25 + 1)
702#define THREE_BYTE_0F3A (THREE_BYTE_0F38 + 1)
703#define THREE_BYTE_0F7A (THREE_BYTE_0F3A + 1)
89b66d55 704#define THREE_BYTE_0F7B (THREE_BYTE_0F7A + 1)
4e7d34a6 705
26ca5450 706typedef void (*op_rtn) (int bytemode, int sizeflag);
252b5132
RH		 707
708struct dis386 {
2da11e11 709 const char *name;
ce518a5f
L		 710 struct
711 {
712 op_rtn rtn;
713 int bytemode;
714 } op[MAX_OPERANDS];
252b5132
RH		 715};
716
717/* Upper case letters in the instruction names here are macros.
718 'A' => print 'b' if no register operands or suffix_always is true
719 'B' => print 'b' if suffix_always is true
9306ca4a
JB		 720 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
721 . size prefix
ed7841b3
JB		 722 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
723 . suffix_always is true
252b5132 724 'E' => print 'e' if 32-bit form of jcxz
3ffd33cf 725 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
52fd6d94 726 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
5dd0794d 727 'H' => print ",pt" or ",pn" branch hint
9306ca4a
JB		 728 'I' => honor following macro letter even in Intel mode (implemented only
729 . for some of the macro letters)
730 'J' => print 'l'
42903f7f 731 'K' => print 'd' or 'q' if rex prefix is present.
252b5132 732 'L' => print 'l' if suffix_always is true
9d141669 733 'M' => print 'r' if intel_mnemonic is false.
252b5132 734 'N' => print 'n' if instruction has no wait "prefix"
a35ca55a 735 'O' => print 'd' or 'o' (or 'q' in Intel mode)
52b15da3 736 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
e396998b
AM		 737 . or suffix_always is true. print 'q' if rex prefix is present.
738 'Q' => print 'w', 'l' or 'q' if no register operands or suffix_always
739 . is true
a35ca55a 740 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
52b15da3 741 'S' => print 'w', 'l' or 'q' if suffix_always is true
6439fc28
AM		 742 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
743 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1a114b12 744 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
a35ca55a 745 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
9306ca4a 746 'X' => print 's', 'd' depending on data16 prefix (for XMM)
8a72226a
L		 747 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
748 suffix_always is true.
6dd5059a 749 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
9d141669 750 '!' => change condition from true to false or from false to true.
52b15da3 751
6439fc28
AM		 752 Many of the above letters print nothing in Intel mode. See "putop"
753 for the details.
52b15da3 754
6439fc28 755 Braces '{' and '}', and vertical bars '|', indicate alternative
7c52e0e8 756 mnemonic strings for AT&T and Intel. */
252b5132 757
6439fc28 758static const struct dis386 dis386[] = {
252b5132 759 /* 00 */
ce518a5f
L		 760 { "addB", { Eb, Gb } },
761 { "addS", { Ev, Gv } },
762 { "addB", { Gb, Eb } },
763 { "addS", { Gv, Ev } },
764 { "addB", { AL, Ib } },
765 { "addS", { eAX, Iv } },
4e7d34a6
L		 766 { X86_64_TABLE (X86_64_06) },
767 { X86_64_TABLE (X86_64_07) },
252b5132 768 /* 08 */
ce518a5f
L		 769 { "orB", { Eb, Gb } },
770 { "orS", { Ev, Gv } },
771 { "orB", { Gb, Eb } },
772 { "orS", { Gv, Ev } },
773 { "orB", { AL, Ib } },
774 { "orS", { eAX, Iv } },
4e7d34a6 775 { X86_64_TABLE (X86_64_0D) },
ce518a5f 776 { "(bad)", { XX } }, /* 0x0f extended opcode escape */
252b5132 777 /* 10 */
ce518a5f
L		 778 { "adcB", { Eb, Gb } },
779 { "adcS", { Ev, Gv } },
780 { "adcB", { Gb, Eb } },
781 { "adcS", { Gv, Ev } },
782 { "adcB", { AL, Ib } },
783 { "adcS", { eAX, Iv } },
4e7d34a6
L		 784 { X86_64_TABLE (X86_64_16) },
785 { X86_64_TABLE (X86_64_17) },
252b5132 786 /* 18 */
ce518a5f
L		 787 { "sbbB", { Eb, Gb } },
788 { "sbbS", { Ev, Gv } },
789 { "sbbB", { Gb, Eb } },
790 { "sbbS", { Gv, Ev } },
791 { "sbbB", { AL, Ib } },
792 { "sbbS", { eAX, Iv } },
4e7d34a6
L		 793 { X86_64_TABLE (X86_64_1E) },
794 { X86_64_TABLE (X86_64_1F) },
252b5132 795 /* 20 */
ce518a5f
L		 796 { "andB", { Eb, Gb } },
797 { "andS", { Ev, Gv } },
798 { "andB", { Gb, Eb } },
799 { "andS", { Gv, Ev } },
800 { "andB", { AL, Ib } },
801 { "andS", { eAX, Iv } },
802 { "(bad)", { XX } }, /* SEG ES prefix */
4e7d34a6 803 { X86_64_TABLE (X86_64_27) },
252b5132 804 /* 28 */
ce518a5f
L		 805 { "subB", { Eb, Gb } },
806 { "subS", { Ev, Gv } },
807 { "subB", { Gb, Eb } },
808 { "subS", { Gv, Ev } },
809 { "subB", { AL, Ib } },
810 { "subS", { eAX, Iv } },
811 { "(bad)", { XX } }, /* SEG CS prefix */
4e7d34a6 812 { X86_64_TABLE (X86_64_2F) },
252b5132 813 /* 30 */
ce518a5f
L		 814 { "xorB", { Eb, Gb } },
815 { "xorS", { Ev, Gv } },
816 { "xorB", { Gb, Eb } },
817 { "xorS", { Gv, Ev } },
818 { "xorB", { AL, Ib } },
819 { "xorS", { eAX, Iv } },
820 { "(bad)", { XX } }, /* SEG SS prefix */
4e7d34a6 821 { X86_64_TABLE (X86_64_37) },
252b5132 822 /* 38 */
ce518a5f
L		 823 { "cmpB", { Eb, Gb } },
824 { "cmpS", { Ev, Gv } },
825 { "cmpB", { Gb, Eb } },
826 { "cmpS", { Gv, Ev } },
827 { "cmpB", { AL, Ib } },
828 { "cmpS", { eAX, Iv } },
829 { "(bad)", { XX } }, /* SEG DS prefix */
4e7d34a6 830 { X86_64_TABLE (X86_64_3F) },
252b5132 831 /* 40 */
ce518a5f
L		 832 { "inc{S|}", { RMeAX } },
833 { "inc{S|}", { RMeCX } },
834 { "inc{S|}", { RMeDX } },
835 { "inc{S|}", { RMeBX } },
836 { "inc{S|}", { RMeSP } },
837 { "inc{S|}", { RMeBP } },
838 { "inc{S|}", { RMeSI } },
839 { "inc{S|}", { RMeDI } },
252b5132 840 /* 48 */
ce518a5f
L		 841 { "dec{S|}", { RMeAX } },
842 { "dec{S|}", { RMeCX } },
843 { "dec{S|}", { RMeDX } },
844 { "dec{S|}", { RMeBX } },
845 { "dec{S|}", { RMeSP } },
846 { "dec{S|}", { RMeBP } },
847 { "dec{S|}", { RMeSI } },
848 { "dec{S|}", { RMeDI } },
252b5132 849 /* 50 */
ce518a5f
L		 850 { "pushV", { RMrAX } },
851 { "pushV", { RMrCX } },
852 { "pushV", { RMrDX } },
853 { "pushV", { RMrBX } },
854 { "pushV", { RMrSP } },
855 { "pushV", { RMrBP } },
856 { "pushV", { RMrSI } },
857 { "pushV", { RMrDI } },
252b5132 858 /* 58 */
ce518a5f
L		 859 { "popV", { RMrAX } },
860 { "popV", { RMrCX } },
861 { "popV", { RMrDX } },
862 { "popV", { RMrBX } },
863 { "popV", { RMrSP } },
864 { "popV", { RMrBP } },
865 { "popV", { RMrSI } },
866 { "popV", { RMrDI } },
252b5132 867 /* 60 */
4e7d34a6
L		 868 { X86_64_TABLE (X86_64_60) },
869 { X86_64_TABLE (X86_64_61) },
870 { X86_64_TABLE (X86_64_62) },
871 { X86_64_TABLE (X86_64_63) },
ce518a5f
L		 872 { "(bad)", { XX } }, /* seg fs */
873 { "(bad)", { XX } }, /* seg gs */
874 { "(bad)", { XX } }, /* op size prefix */
875 { "(bad)", { XX } }, /* adr size prefix */
252b5132 876 /* 68 */
ce518a5f
L		 877 { "pushT", { Iq } },
878 { "imulS", { Gv, Ev, Iv } },
879 { "pushT", { sIb } },
880 { "imulS", { Gv, Ev, sIb } },
7c52e0e8 881 { "ins{b|}", { Ybr, indirDX } },
4e7d34a6 882 { X86_64_TABLE (X86_64_6D) },
7c52e0e8 883 { "outs{b|}", { indirDXr, Xb } },
4e7d34a6 884 { X86_64_TABLE (X86_64_6F) },
252b5132 885 /* 70 */
ce518a5f
L		 886 { "joH", { Jb, XX, cond_jump_flag } },
887 { "jnoH", { Jb, XX, cond_jump_flag } },
888 { "jbH", { Jb, XX, cond_jump_flag } },
889 { "jaeH", { Jb, XX, cond_jump_flag } },
890 { "jeH", { Jb, XX, cond_jump_flag } },
891 { "jneH", { Jb, XX, cond_jump_flag } },
892 { "jbeH", { Jb, XX, cond_jump_flag } },
893 { "jaH", { Jb, XX, cond_jump_flag } },
252b5132 894 /* 78 */
ce518a5f
L		 895 { "jsH", { Jb, XX, cond_jump_flag } },
896 { "jnsH", { Jb, XX, cond_jump_flag } },
897 { "jpH", { Jb, XX, cond_jump_flag } },
898 { "jnpH", { Jb, XX, cond_jump_flag } },
899 { "jlH", { Jb, XX, cond_jump_flag } },
900 { "jgeH", { Jb, XX, cond_jump_flag } },
901 { "jleH", { Jb, XX, cond_jump_flag } },
902 { "jgH", { Jb, XX, cond_jump_flag } },
252b5132 903 /* 80 */
1ceb70f8
L		 904 { REG_TABLE (REG_80) },
905 { REG_TABLE (REG_81) },
ce518a5f 906 { "(bad)", { XX } },
1ceb70f8 907 { REG_TABLE (REG_82) },
ce518a5f
L		 908 { "testB", { Eb, Gb } },
909 { "testS", { Ev, Gv } },
910 { "xchgB", { Eb, Gb } },
911 { "xchgS", { Ev, Gv } },
252b5132 912 /* 88 */
ce518a5f
L		 913 { "movB", { Eb, Gb } },
914 { "movS", { Ev, Gv } },
915 { "movB", { Gb, Eb } },
916 { "movS", { Gv, Ev } },
917 { "movD", { Sv, Sw } },
1ceb70f8 918 { MOD_TABLE (MOD_8D) },
ce518a5f 919 { "movD", { Sw, Sv } },
1ceb70f8 920 { REG_TABLE (REG_8F) },
252b5132 921 /* 90 */
1ceb70f8 922 { PREFIX_TABLE (PREFIX_90) },
ce518a5f
L		 923 { "xchgS", { RMeCX, eAX } },
924 { "xchgS", { RMeDX, eAX } },
925 { "xchgS", { RMeBX, eAX } },
926 { "xchgS", { RMeSP, eAX } },
927 { "xchgS", { RMeBP, eAX } },
928 { "xchgS", { RMeSI, eAX } },
929 { "xchgS", { RMeDI, eAX } },
252b5132 930 /* 98 */
7c52e0e8
L		 931 { "cW{t|}R", { XX } },
932 { "cR{t|}O", { XX } },
4e7d34a6 933 { X86_64_TABLE (X86_64_9A) },
ce518a5f
L		 934 { "(bad)", { XX } }, /* fwait */
935 { "pushfT", { XX } },
936 { "popfT", { XX } },
7c52e0e8
L		 937 { "sahf", { XX } },
938 { "lahf", { XX } },
252b5132 939 /* a0 */
ce518a5f
L		 940 { "movB", { AL, Ob } },
941 { "movS", { eAX, Ov } },
942 { "movB", { Ob, AL } },
943 { "movS", { Ov, eAX } },
7c52e0e8
L		 944 { "movs{b|}", { Ybr, Xb } },
945 { "movs{R|}", { Yvr, Xv } },
946 { "cmps{b|}", { Xb, Yb } },
947 { "cmps{R|}", { Xv, Yv } },
252b5132 948 /* a8 */
ce518a5f
L		 949 { "testB", { AL, Ib } },
950 { "testS", { eAX, Iv } },
951 { "stosB", { Ybr, AL } },
952 { "stosS", { Yvr, eAX } },
953 { "lodsB", { ALr, Xb } },
954 { "lodsS", { eAXr, Xv } },
955 { "scasB", { AL, Yb } },
956 { "scasS", { eAX, Yv } },
252b5132 957 /* b0 */
ce518a5f
L		 958 { "movB", { RMAL, Ib } },
959 { "movB", { RMCL, Ib } },
960 { "movB", { RMDL, Ib } },
961 { "movB", { RMBL, Ib } },
962 { "movB", { RMAH, Ib } },
963 { "movB", { RMCH, Ib } },
964 { "movB", { RMDH, Ib } },
965 { "movB", { RMBH, Ib } },
252b5132 966 /* b8 */
ce518a5f
L		 967 { "movS", { RMeAX, Iv64 } },
968 { "movS", { RMeCX, Iv64 } },
969 { "movS", { RMeDX, Iv64 } },
970 { "movS", { RMeBX, Iv64 } },
971 { "movS", { RMeSP, Iv64 } },
972 { "movS", { RMeBP, Iv64 } },
973 { "movS", { RMeSI, Iv64 } },
974 { "movS", { RMeDI, Iv64 } },
252b5132 975 /* c0 */
1ceb70f8
L		 976 { REG_TABLE (REG_C0) },
977 { REG_TABLE (REG_C1) },
ce518a5f
L		 978 { "retT", { Iw } },
979 { "retT", { XX } },
4e7d34a6
L		 980 { X86_64_TABLE (X86_64_C4) },
981 { X86_64_TABLE (X86_64_C5) },
1ceb70f8
L		 982 { REG_TABLE (REG_C6) },
983 { REG_TABLE (REG_C7) },
252b5132 984 /* c8 */
ce518a5f
L		 985 { "enterT", { Iw, Ib } },
986 { "leaveT", { XX } },
987 { "lretP", { Iw } },
988 { "lretP", { XX } },
989 { "int3", { XX } },
990 { "int", { Ib } },
4e7d34a6 991 { X86_64_TABLE (X86_64_CE) },
ce518a5f 992 { "iretP", { XX } },
252b5132 993 /* d0 */
1ceb70f8
L		 994 { REG_TABLE (REG_D0) },
995 { REG_TABLE (REG_D1) },
996 { REG_TABLE (REG_D2) },
997 { REG_TABLE (REG_D3) },
4e7d34a6
L		 998 { X86_64_TABLE (X86_64_D4) },
999 { X86_64_TABLE (X86_64_D5) },
ce518a5f
L		 1000 { "(bad)", { XX } },
1001 { "xlat", { DSBX } },
252b5132
RH		 1002 /* d8 */
1003 { FLOAT },
1004 { FLOAT },
1005 { FLOAT },
1006 { FLOAT },
1007 { FLOAT },
1008 { FLOAT },
1009 { FLOAT },
1010 { FLOAT },
1011 /* e0 */
ce518a5f
L		 1012 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
1013 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
1014 { "loopFH", { Jb, XX, loop_jcxz_flag } },
1015 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
1016 { "inB", { AL, Ib } },
1017 { "inG", { zAX, Ib } },
1018 { "outB", { Ib, AL } },
1019 { "outG", { Ib, zAX } },
252b5132 1020 /* e8 */
ce518a5f
L		 1021 { "callT", { Jv } },
1022 { "jmpT", { Jv } },
4e7d34a6 1023 { X86_64_TABLE (X86_64_EA) },
ce518a5f
L		 1024 { "jmp", { Jb } },
1025 { "inB", { AL, indirDX } },
1026 { "inG", { zAX, indirDX } },
1027 { "outB", { indirDX, AL } },
1028 { "outG", { indirDX, zAX } },
252b5132 1029 /* f0 */
ce518a5f
L		 1030 { "(bad)", { XX } }, /* lock prefix */
1031 { "icebp", { XX } },
1032 { "(bad)", { XX } }, /* repne */
1033 { "(bad)", { XX } }, /* repz */
1034 { "hlt", { XX } },
1035 { "cmc", { XX } },
1ceb70f8
L		 1036 { REG_TABLE (REG_F6) },
1037 { REG_TABLE (REG_F7) },
252b5132 1038 /* f8 */
ce518a5f
L		 1039 { "clc", { XX } },
1040 { "stc", { XX } },
1041 { "cli", { XX } },
1042 { "sti", { XX } },
1043 { "cld", { XX } },
1044 { "std", { XX } },
1ceb70f8
L		 1045 { REG_TABLE (REG_FE) },
1046 { REG_TABLE (REG_FF) },
252b5132
RH		 1047};
1048
6439fc28 1049static const struct dis386 dis386_twobyte[] = {
252b5132 1050 /* 00 */
1ceb70f8
L		 1051 { REG_TABLE (REG_0F00 ) },
1052 { REG_TABLE (REG_0F01 ) },
ce518a5f
L		 1053 { "larS", { Gv, Ew } },
1054 { "lslS", { Gv, Ew } },
1055 { "(bad)", { XX } },
1056 { "syscall", { XX } },
1057 { "clts", { XX } },
1058 { "sysretP", { XX } },
252b5132 1059 /* 08 */
ce518a5f
L		 1060 { "invd", { XX } },
1061 { "wbinvd", { XX } },
1062 { "(bad)", { XX } },
1063 { "ud2a", { XX } },
1064 { "(bad)", { XX } },
1ceb70f8 1065 { REG_TABLE (REG_0F0E) },
ce518a5f
L		 1066 { "femms", { XX } },
1067 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
252b5132 1068 /* 10 */
1ceb70f8
L		 1069 { PREFIX_TABLE (PREFIX_0F10) },
1070 { PREFIX_TABLE (PREFIX_0F11) },
1071 { PREFIX_TABLE (PREFIX_0F12) },
1072 { MOD_TABLE (MOD_0F13) },
f2a421c4
L		 1073 { "unpcklpX", { XM, EXx } },
1074 { "unpckhpX", { XM, EXx } },
1ceb70f8
L		 1075 { PREFIX_TABLE (PREFIX_0F16) },
1076 { MOD_TABLE (MOD_0F17) },
252b5132 1077 /* 18 */
1ceb70f8 1078 { REG_TABLE (REG_0F18) },
ce518a5f
L		 1079 { "(bad)", { XX } },
1080 { "(bad)", { XX } },
1081 { "(bad)", { XX } },
1082 { "(bad)", { XX } },
1083 { "(bad)", { XX } },
1084 { "(bad)", { XX } },
1085 { "nopQ", { Ev } },
252b5132 1086 /* 20 */
1ceb70f8
L		 1087 { MOD_TABLE (MOD_0F20) },
1088 { MOD_TABLE (MOD_0F21) },
1089 { MOD_TABLE (MOD_0F22) },
1090 { MOD_TABLE (MOD_0F23) },
1091 { MOD_TABLE (MOD_0F24) },
4e7d34a6 1092 { THREE_BYTE_TABLE (THREE_BYTE_0F25) },
1ceb70f8 1093 { MOD_TABLE (MOD_0F26) },
ce518a5f 1094 { "(bad)", { XX } },
252b5132 1095 /* 28 */
09a2c6cf 1096 { "movapX", { XM, EXx } },
d5d7db8e 1097 { "movapX", { EXx, XM } },
1ceb70f8
L		 1098 { PREFIX_TABLE (PREFIX_0F2A) },
1099 { PREFIX_TABLE (PREFIX_0F2B) },
1100 { PREFIX_TABLE (PREFIX_0F2C) },
1101 { PREFIX_TABLE (PREFIX_0F2D) },
1102 { PREFIX_TABLE (PREFIX_0F2E) },
1103 { PREFIX_TABLE (PREFIX_0F2F) },
252b5132 1104 /* 30 */
ce518a5f
L		 1105 { "wrmsr", { XX } },
1106 { "rdtsc", { XX } },
1107 { "rdmsr", { XX } },
1108 { "rdpmc", { XX } },
1109 { "sysenter", { XX } },
1110 { "sysexit", { XX } },
1111 { "(bad)", { XX } },
47dd174c 1112 { "getsec", { XX } },
252b5132 1113 /* 38 */
4e7d34a6 1114 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
ce518a5f 1115 { "(bad)", { XX } },
4e7d34a6 1116 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
ce518a5f
L		 1117 { "(bad)", { XX } },
1118 { "(bad)", { XX } },
1119 { "(bad)", { XX } },
1120 { "(bad)", { XX } },
1121 { "(bad)", { XX } },
252b5132 1122 /* 40 */
ce518a5f
L		 1123 { "cmovo", { Gv, Ev } },
1124 { "cmovno", { Gv, Ev } },
1125 { "cmovb", { Gv, Ev } },
1126 { "cmovae", { Gv, Ev } },
1127 { "cmove", { Gv, Ev } },
1128 { "cmovne", { Gv, Ev } },
1129 { "cmovbe", { Gv, Ev } },
1130 { "cmova", { Gv, Ev } },
252b5132 1131 /* 48 */
ce518a5f
L		 1132 { "cmovs", { Gv, Ev } },
1133 { "cmovns", { Gv, Ev } },
1134 { "cmovp", { Gv, Ev } },
1135 { "cmovnp", { Gv, Ev } },
1136 { "cmovl", { Gv, Ev } },
1137 { "cmovge", { Gv, Ev } },
1138 { "cmovle", { Gv, Ev } },
1139 { "cmovg", { Gv, Ev } },
252b5132 1140 /* 50 */
75c135a8 1141 { MOD_TABLE (MOD_0F51) },
1ceb70f8
L		 1142 { PREFIX_TABLE (PREFIX_0F51) },
1143 { PREFIX_TABLE (PREFIX_0F52) },
1144 { PREFIX_TABLE (PREFIX_0F53) },
09a2c6cf
L		 1145 { "andpX", { XM, EXx } },
1146 { "andnpX", { XM, EXx } },
1147 { "orpX", { XM, EXx } },
1148 { "xorpX", { XM, EXx } },
252b5132 1149 /* 58 */
1ceb70f8
L		 1150 { PREFIX_TABLE (PREFIX_0F58) },
1151 { PREFIX_TABLE (PREFIX_0F59) },
1152 { PREFIX_TABLE (PREFIX_0F5A) },
1153 { PREFIX_TABLE (PREFIX_0F5B) },
1154 { PREFIX_TABLE (PREFIX_0F5C) },
1155 { PREFIX_TABLE (PREFIX_0F5D) },
1156 { PREFIX_TABLE (PREFIX_0F5E) },
1157 { PREFIX_TABLE (PREFIX_0F5F) },
252b5132 1158 /* 60 */
1ceb70f8
L		 1159 { PREFIX_TABLE (PREFIX_0F60) },
1160 { PREFIX_TABLE (PREFIX_0F61) },
1161 { PREFIX_TABLE (PREFIX_0F62) },
ce518a5f
L		 1162 { "packsswb", { MX, EM } },
1163 { "pcmpgtb", { MX, EM } },
1164 { "pcmpgtw", { MX, EM } },
1165 { "pcmpgtd", { MX, EM } },
1166 { "packuswb", { MX, EM } },
252b5132 1167 /* 68 */
ce518a5f
L		 1168 { "punpckhbw", { MX, EM } },
1169 { "punpckhwd", { MX, EM } },
1170 { "punpckhdq", { MX, EM } },
1171 { "packssdw", { MX, EM } },
1ceb70f8
L		 1172 { PREFIX_TABLE (PREFIX_0F6C) },
1173 { PREFIX_TABLE (PREFIX_0F6D) },
231af070 1174 { "movK", { MX, Edq } },
1ceb70f8 1175 { PREFIX_TABLE (PREFIX_0F6F) },
252b5132 1176 /* 70 */
1ceb70f8
L		 1177 { PREFIX_TABLE (PREFIX_0F70) },
1178 { REG_TABLE (REG_0F71) },
1179 { REG_TABLE (REG_0F72) },
1180 { REG_TABLE (REG_0F73) },
ce518a5f
L		 1181 { "pcmpeqb", { MX, EM } },
1182 { "pcmpeqw", { MX, EM } },
1183 { "pcmpeqd", { MX, EM } },
1184 { "emms", { XX } },
252b5132 1185 /* 78 */
1ceb70f8
L		 1186 { PREFIX_TABLE (PREFIX_0F78) },
1187 { PREFIX_TABLE (PREFIX_0F79) },
4e7d34a6 1188 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
89b66d55 1189 { THREE_BYTE_TABLE (THREE_BYTE_0F7B) },
1ceb70f8
L		 1190 { PREFIX_TABLE (PREFIX_0F7C) },
1191 { PREFIX_TABLE (PREFIX_0F7D) },
1192 { PREFIX_TABLE (PREFIX_0F7E) },
1193 { PREFIX_TABLE (PREFIX_0F7F) },
252b5132 1194 /* 80 */
ce518a5f
L		 1195 { "joH", { Jv, XX, cond_jump_flag } },
1196 { "jnoH", { Jv, XX, cond_jump_flag } },
1197 { "jbH", { Jv, XX, cond_jump_flag } },
1198 { "jaeH", { Jv, XX, cond_jump_flag } },
1199 { "jeH", { Jv, XX, cond_jump_flag } },
1200 { "jneH", { Jv, XX, cond_jump_flag } },
1201 { "jbeH", { Jv, XX, cond_jump_flag } },
1202 { "jaH", { Jv, XX, cond_jump_flag } },
252b5132 1203 /* 88 */
ce518a5f
L		 1204 { "jsH", { Jv, XX, cond_jump_flag } },
1205 { "jnsH", { Jv, XX, cond_jump_flag } },
1206 { "jpH", { Jv, XX, cond_jump_flag } },
1207 { "jnpH", { Jv, XX, cond_jump_flag } },
1208 { "jlH", { Jv, XX, cond_jump_flag } },
1209 { "jgeH", { Jv, XX, cond_jump_flag } },
1210 { "jleH", { Jv, XX, cond_jump_flag } },
1211 { "jgH", { Jv, XX, cond_jump_flag } },
252b5132 1212 /* 90 */
ce518a5f
L		 1213 { "seto", { Eb } },
1214 { "setno", { Eb } },
1215 { "setb", { Eb } },
1216 { "setae", { Eb } },
1217 { "sete", { Eb } },
1218 { "setne", { Eb } },
1219 { "setbe", { Eb } },
1220 { "seta", { Eb } },
252b5132 1221 /* 98 */
ce518a5f
L		 1222 { "sets", { Eb } },
1223 { "setns", { Eb } },
1224 { "setp", { Eb } },
1225 { "setnp", { Eb } },
1226 { "setl", { Eb } },
1227 { "setge", { Eb } },
1228 { "setle", { Eb } },
1229 { "setg", { Eb } },
252b5132 1230 /* a0 */
ce518a5f
L		 1231 { "pushT", { fs } },
1232 { "popT", { fs } },
1233 { "cpuid", { XX } },
1234 { "btS", { Ev, Gv } },
1235 { "shldS", { Ev, Gv, Ib } },
1236 { "shldS", { Ev, Gv, CL } },
1ceb70f8
L		 1237 { REG_TABLE (REG_0FA6) },
1238 { REG_TABLE (REG_0FA7) },
252b5132 1239 /* a8 */
ce518a5f
L		 1240 { "pushT", { gs } },
1241 { "popT", { gs } },
1242 { "rsm", { XX } },
1243 { "btsS", { Ev, Gv } },
1244 { "shrdS", { Ev, Gv, Ib } },
1245 { "shrdS", { Ev, Gv, CL } },
1ceb70f8 1246 { REG_TABLE (REG_0FAE) },
ce518a5f 1247 { "imulS", { Gv, Ev } },
252b5132 1248 /* b0 */
ce518a5f
L		 1249 { "cmpxchgB", { Eb, Gb } },
1250 { "cmpxchgS", { Ev, Gv } },
1ceb70f8 1251 { MOD_TABLE (MOD_0FB2) },
ce518a5f 1252 { "btrS", { Ev, Gv } },
1ceb70f8
L		 1253 { MOD_TABLE (MOD_0FB4) },
1254 { MOD_TABLE (MOD_0FB5) },
7c52e0e8
L		 1255 { "movz{bR|x}", { Gv, Eb } },
1256 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
252b5132 1257 /* b8 */
1ceb70f8 1258 { PREFIX_TABLE (PREFIX_0FB8) },
ce518a5f 1259 { "ud2b", { XX } },
1ceb70f8 1260 { REG_TABLE (REG_0FBA) },
ce518a5f
L		 1261 { "btcS", { Ev, Gv } },
1262 { "bsfS", { Gv, Ev } },
1ceb70f8 1263 { PREFIX_TABLE (PREFIX_0FBD) },
7c52e0e8
L		 1264 { "movs{bR|x}", { Gv, Eb } },
1265 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
252b5132 1266 /* c0 */
ce518a5f
L		 1267 { "xaddB", { Eb, Gb } },
1268 { "xaddS", { Ev, Gv } },
1ceb70f8 1269 { PREFIX_TABLE (PREFIX_0FC2) },
ce518a5f
L		 1270 { "movntiS", { Ev, Gv } },
1271 { "pinsrw", { MX, Edqw, Ib } },
1272 { "pextrw", { Gdq, MS, Ib } },
09a2c6cf 1273 { "shufpX", { XM, EXx, Ib } },
1ceb70f8 1274 { REG_TABLE (REG_0FC7) },
252b5132 1275 /* c8 */
ce518a5f
L		 1276 { "bswap", { RMeAX } },
1277 { "bswap", { RMeCX } },
1278 { "bswap", { RMeDX } },
1279 { "bswap", { RMeBX } },
1280 { "bswap", { RMeSP } },
1281 { "bswap", { RMeBP } },
1282 { "bswap", { RMeSI } },
1283 { "bswap", { RMeDI } },
252b5132 1284 /* d0 */
1ceb70f8 1285 { PREFIX_TABLE (PREFIX_0FD0) },
ce518a5f
L		 1286 { "psrlw", { MX, EM } },
1287 { "psrld", { MX, EM } },
1288 { "psrlq", { MX, EM } },
1289 { "paddq", { MX, EM } },
1290 { "pmullw", { MX, EM } },
1ceb70f8 1291 { PREFIX_TABLE (PREFIX_0FD6) },
75c135a8 1292 { MOD_TABLE (MOD_0FD7) },
252b5132 1293 /* d8 */
ce518a5f
L		 1294 { "psubusb", { MX, EM } },
1295 { "psubusw", { MX, EM } },
1296 { "pminub", { MX, EM } },
1297 { "pand", { MX, EM } },
1298 { "paddusb", { MX, EM } },
1299 { "paddusw", { MX, EM } },
1300 { "pmaxub", { MX, EM } },
1301 { "pandn", { MX, EM } },
252b5132 1302 /* e0 */
ce518a5f
L		 1303 { "pavgb", { MX, EM } },
1304 { "psraw", { MX, EM } },
1305 { "psrad", { MX, EM } },
1306 { "pavgw", { MX, EM } },
1307 { "pmulhuw", { MX, EM } },
1308 { "pmulhw", { MX, EM } },
1ceb70f8
L		 1309 { PREFIX_TABLE (PREFIX_0FE6) },
1310 { PREFIX_TABLE (PREFIX_0FE7) },
252b5132 1311 /* e8 */
ce518a5f
L		 1312 { "psubsb", { MX, EM } },
1313 { "psubsw", { MX, EM } },
1314 { "pminsw", { MX, EM } },
1315 { "por", { MX, EM } },
1316 { "paddsb", { MX, EM } },
1317 { "paddsw", { MX, EM } },
1318 { "pmaxsw", { MX, EM } },
1319 { "pxor", { MX, EM } },
252b5132 1320 /* f0 */
1ceb70f8 1321 { PREFIX_TABLE (PREFIX_0FF0) },
ce518a5f
L		 1322 { "psllw", { MX, EM } },
1323 { "pslld", { MX, EM } },
1324 { "psllq", { MX, EM } },
1325 { "pmuludq", { MX, EM } },
1326 { "pmaddwd", { MX, EM } },
1327 { "psadbw", { MX, EM } },
1ceb70f8 1328 { PREFIX_TABLE (PREFIX_0FF7) },
252b5132 1329 /* f8 */
ce518a5f
L		 1330 { "psubb", { MX, EM } },
1331 { "psubw", { MX, EM } },
1332 { "psubd", { MX, EM } },
1333 { "psubq", { MX, EM } },
1334 { "paddb", { MX, EM } },
1335 { "paddw", { MX, EM } },
1336 { "paddd", { MX, EM } },
1337 { "(bad)", { XX } },
252b5132
RH		 1338};
1339
1340static const unsigned char onebyte_has_modrm[256] = {
c608c12e
AM		 1341 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1342 /* ------------------------------- */
1343 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1344 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1345 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1346 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1347 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1348 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1349 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1350 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1351 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1352 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1353 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1354 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1355 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1356 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1357 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1358 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1359 /* ------------------------------- */
1360 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
252b5132
RH		 1361};
1362
1363static const unsigned char twobyte_has_modrm[256] = {
c608c12e
AM		 1364 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1365 /* ------------------------------- */
252b5132 1366 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
15965411 1367 /* 10 */ 1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,1, /* 1f */
85f10a01 1368 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
331d2d0d 1369 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
252b5132 1370 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
4bba6815
AM		 1371 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1372 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
85f10a01 1373 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
252b5132
RH		 1374 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1375 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
30d1c836 1376 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
050dfa73 1377 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
252b5132 1378 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
ca164297 1379 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
4bba6815 1380 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
ca164297 1381 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
c608c12e
AM		 1382 /* ------------------------------- */
1383 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1384};
1385
252b5132
RH		 1386static char obuf[100];
1387static char *obufp;
1388static char scratchbuf[100];
1389static unsigned char *start_codep;
1390static unsigned char *insn_codep;
1391static unsigned char *codep;
b844680a
L		 1392static const char *lock_prefix;
1393static const char *data_prefix;
1394static const char *addr_prefix;
1395static const char *repz_prefix;
1396static const char *repnz_prefix;
252b5132 1397static disassemble_info *the_info;
7967e09e
L		 1398static struct
1399 {
1400 int mod;
7967e09e 1401 int reg;
484c222e 1402 int rm;
7967e09e
L		 1403 }
1404modrm;
4bba6815 1405static unsigned char need_modrm;
252b5132 1406
4bba6815
AM		 1407/* If we are accessing mod/rm/reg without need_modrm set, then the
1408 values are stale. Hitting this abort likely indicates that you
1409 need to update onebyte_has_modrm or twobyte_has_modrm. */
1410#define MODRM_CHECK if (!need_modrm) abort ()
1411
d708bcba
AM		 1412static const char **names64;
1413static const char **names32;
1414static const char **names16;
1415static const char **names8;
1416static const char **names8rex;
1417static const char **names_seg;
db51cc60
L		 1418static const char *index64;
1419static const char *index32;
d708bcba
AM		 1420static const char **index16;
1421
1422static const char *intel_names64[] = {
1423 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
1424 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
1425};
1426static const char *intel_names32[] = {
1427 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
1428 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
1429};
1430static const char *intel_names16[] = {
1431 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
1432 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
1433};
1434static const char *intel_names8[] = {
1435 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
1436};
1437static const char *intel_names8rex[] = {
1438 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
1439 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
1440};
1441static const char *intel_names_seg[] = {
1442 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
1443};
db51cc60
L		 1444static const char *intel_index64 = "riz";
1445static const char *intel_index32 = "eiz";
d708bcba
AM		 1446static const char *intel_index16[] = {
1447 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
1448};
1449
1450static const char *att_names64[] = {
1451 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
52b15da3
JH		 1452 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
1453};
d708bcba
AM		 1454static const char *att_names32[] = {
1455 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
52b15da3 1456 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
252b5132 1457};
d708bcba
AM		 1458static const char *att_names16[] = {
1459 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
52b15da3 1460 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
252b5132 1461};
d708bcba
AM		 1462static const char *att_names8[] = {
1463 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
252b5132 1464};
d708bcba
AM		 1465static const char *att_names8rex[] = {
1466 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
52b15da3
JH		 1467 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
1468};
d708bcba
AM		 1469static const char *att_names_seg[] = {
1470 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
252b5132 1471};
db51cc60
L		 1472static const char *att_index64 = "%riz";
1473static const char *att_index32 = "%eiz";
d708bcba
AM		 1474static const char *att_index16[] = {
1475 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
252b5132
RH		 1476};
1477
1ceb70f8
L		 1478static const struct dis386 reg_table[][8] = {
1479 /* REG_80 */
252b5132 1480 {
ce518a5f
L		 1481 { "addA", { Eb, Ib } },
1482 { "orA", { Eb, Ib } },
1483 { "adcA", { Eb, Ib } },
1484 { "sbbA", { Eb, Ib } },
1485 { "andA", { Eb, Ib } },
1486 { "subA", { Eb, Ib } },
1487 { "xorA", { Eb, Ib } },
1488 { "cmpA", { Eb, Ib } },
252b5132 1489 },
1ceb70f8 1490 /* REG_81 */
252b5132 1491 {
ce518a5f
L		 1492 { "addQ", { Ev, Iv } },
1493 { "orQ", { Ev, Iv } },
1494 { "adcQ", { Ev, Iv } },
1495 { "sbbQ", { Ev, Iv } },
1496 { "andQ", { Ev, Iv } },
1497 { "subQ", { Ev, Iv } },
1498 { "xorQ", { Ev, Iv } },
1499 { "cmpQ", { Ev, Iv } },
252b5132 1500 },
1ceb70f8 1501 /* REG_82 */
252b5132 1502 {
ce518a5f
L		 1503 { "addQ", { Ev, sIb } },
1504 { "orQ", { Ev, sIb } },
1505 { "adcQ", { Ev, sIb } },
1506 { "sbbQ", { Ev, sIb } },
1507 { "andQ", { Ev, sIb } },
1508 { "subQ", { Ev, sIb } },
1509 { "xorQ", { Ev, sIb } },
1510 { "cmpQ", { Ev, sIb } },
252b5132 1511 },
1ceb70f8 1512 /* REG_8F */
4e7d34a6
L		 1513 {
1514 { "popU", { stackEv } },
1515 { "(bad)", { XX } },
1516 { "(bad)", { XX } },
1517 { "(bad)", { XX } },
1518 { "(bad)", { XX } },
1519 { "(bad)", { XX } },
1520 { "(bad)", { XX } },
1521 { "(bad)", { XX } },
1522 },
1ceb70f8 1523 /* REG_C0 */
252b5132 1524 {
ce518a5f
L		 1525 { "rolA", { Eb, Ib } },
1526 { "rorA", { Eb, Ib } },
1527 { "rclA", { Eb, Ib } },
1528 { "rcrA", { Eb, Ib } },
1529 { "shlA", { Eb, Ib } },
1530 { "shrA", { Eb, Ib } },
1531 { "(bad)", { XX } },
1532 { "sarA", { Eb, Ib } },
252b5132 1533 },
1ceb70f8 1534 /* REG_C1 */
252b5132 1535 {
ce518a5f
L		 1536 { "rolQ", { Ev, Ib } },
1537 { "rorQ", { Ev, Ib } },
1538 { "rclQ", { Ev, Ib } },
1539 { "rcrQ", { Ev, Ib } },
1540 { "shlQ", { Ev, Ib } },
1541 { "shrQ", { Ev, Ib } },
1542 { "(bad)", { XX } },
1543 { "sarQ", { Ev, Ib } },
252b5132 1544 },
1ceb70f8 1545 /* REG_C6 */
4e7d34a6
L		 1546 {
1547 { "movA", { Eb, Ib } },
1548 { "(bad)", { XX } },
1549 { "(bad)", { XX } },
1550 { "(bad)", { XX } },
1551 { "(bad)", { XX } },
1552 { "(bad)", { XX } },
1553 { "(bad)", { XX } },
1554 { "(bad)", { XX } },
1555 },
1ceb70f8 1556 /* REG_C7 */
4e7d34a6
L		 1557 {
1558 { "movQ", { Ev, Iv } },
1559 { "(bad)", { XX } },
1560 { "(bad)", { XX } },
1561 { "(bad)", { XX } },
1562 { "(bad)", { XX } },
1563 { "(bad)", { XX } },
1564 { "(bad)", { XX } },
1565 { "(bad)", { XX } },
1566 },
1ceb70f8 1567 /* REG_D0 */
252b5132 1568 {
ce518a5f
L		 1569 { "rolA", { Eb, I1 } },
1570 { "rorA", { Eb, I1 } },
1571 { "rclA", { Eb, I1 } },
1572 { "rcrA", { Eb, I1 } },
1573 { "shlA", { Eb, I1 } },
1574 { "shrA", { Eb, I1 } },
1575 { "(bad)", { XX } },
1576 { "sarA", { Eb, I1 } },
252b5132 1577 },
1ceb70f8 1578 /* REG_D1 */
252b5132 1579 {
ce518a5f
L		 1580 { "rolQ", { Ev, I1 } },
1581 { "rorQ", { Ev, I1 } },
1582 { "rclQ", { Ev, I1 } },
1583 { "rcrQ", { Ev, I1 } },
1584 { "shlQ", { Ev, I1 } },
1585 { "shrQ", { Ev, I1 } },
1586 { "(bad)", { XX } },
1587 { "sarQ", { Ev, I1 } },
252b5132 1588 },
1ceb70f8 1589 /* REG_D2 */
252b5132 1590 {
ce518a5f
L		 1591 { "rolA", { Eb, CL } },
1592 { "rorA", { Eb, CL } },
1593 { "rclA", { Eb, CL } },
1594 { "rcrA", { Eb, CL } },
1595 { "shlA", { Eb, CL } },
1596 { "shrA", { Eb, CL } },
1597 { "(bad)", { XX } },
1598 { "sarA", { Eb, CL } },
252b5132 1599 },
1ceb70f8 1600 /* REG_D3 */
252b5132 1601 {
ce518a5f
L		 1602 { "rolQ", { Ev, CL } },
1603 { "rorQ", { Ev, CL } },
1604 { "rclQ", { Ev, CL } },
1605 { "rcrQ", { Ev, CL } },
1606 { "shlQ", { Ev, CL } },
1607 { "shrQ", { Ev, CL } },
1608 { "(bad)", { XX } },
1609 { "sarQ", { Ev, CL } },
252b5132 1610 },
1ceb70f8 1611 /* REG_F6 */
252b5132 1612 {
ce518a5f 1613 { "testA", { Eb, Ib } },
058f233b 1614 { "(bad)", { XX } },
ce518a5f
L		 1615 { "notA", { Eb } },
1616 { "negA", { Eb } },
1617 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
1618 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
1619 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
1620 { "idivA", { Eb } }, /* and idiv for consistency. */
252b5132 1621 },
1ceb70f8 1622 /* REG_F7 */
252b5132 1623 {
ce518a5f
L		 1624 { "testQ", { Ev, Iv } },
1625 { "(bad)", { XX } },
1626 { "notQ", { Ev } },
1627 { "negQ", { Ev } },
1628 { "mulQ", { Ev } }, /* Don't print the implicit register. */
1629 { "imulQ", { Ev } },
1630 { "divQ", { Ev } },
1631 { "idivQ", { Ev } },
252b5132 1632 },
1ceb70f8 1633 /* REG_FE */
252b5132 1634 {
ce518a5f
L		 1635 { "incA", { Eb } },
1636 { "decA", { Eb } },
1637 { "(bad)", { XX } },
1638 { "(bad)", { XX } },
1639 { "(bad)", { XX } },
1640 { "(bad)", { XX } },
1641 { "(bad)", { XX } },
1642 { "(bad)", { XX } },
252b5132 1643 },
1ceb70f8 1644 /* REG_FF */
252b5132 1645 {
ce518a5f
L		 1646 { "incQ", { Ev } },
1647 { "decQ", { Ev } },
1648 { "callT", { indirEv } },
1649 { "JcallT", { indirEp } },
1650 { "jmpT", { indirEv } },
1651 { "JjmpT", { indirEp } },
1652 { "pushU", { stackEv } },
1653 { "(bad)", { XX } },
252b5132 1654 },
1ceb70f8 1655 /* REG_0F00 */
252b5132 1656 {
ce518a5f
L		 1657 { "sldtD", { Sv } },
1658 { "strD", { Sv } },
1659 { "lldt", { Ew } },
1660 { "ltr", { Ew } },
1661 { "verr", { Ew } },
1662 { "verw", { Ew } },
1663 { "(bad)", { XX } },
1664 { "(bad)", { XX } },
252b5132 1665 },
1ceb70f8 1666 /* REG_0F01 */
252b5132 1667 {
1ceb70f8
L		 1668 { MOD_TABLE (MOD_0F01_REG_0) },
1669 { MOD_TABLE (MOD_0F01_REG_1) },
1670 { MOD_TABLE (MOD_0F01_REG_2) },
1671 { MOD_TABLE (MOD_0F01_REG_3) },
ce518a5f
L		 1672 { "smswD", { Sv } },
1673 { "(bad)", { XX } },
1674 { "lmsw", { Ew } },
1ceb70f8 1675 { MOD_TABLE (MOD_0F01_REG_7) },
252b5132 1676 },
1ceb70f8 1677 /* REG_0F0E */
252b5132 1678 {
4e7d34a6
L		 1679 { "prefetch", { Eb } },
1680 { "prefetchw", { Eb } },
1681 { "(bad)", { XX } },
1682 { "(bad)", { XX } },
1683 { "(bad)", { XX } },
1684 { "(bad)", { XX } },
1685 { "(bad)", { XX } },
1686 { "(bad)", { XX } },
252b5132 1687 },
1ceb70f8 1688 /* REG_0F18 */
252b5132 1689 {
1ceb70f8
L		 1690 { MOD_TABLE (MOD_0F18_REG_0) },
1691 { MOD_TABLE (MOD_0F18_REG_1) },
1692 { MOD_TABLE (MOD_0F18_REG_2) },
1693 { MOD_TABLE (MOD_0F18_REG_3) },
ce518a5f
L		 1694 { "(bad)", { XX } },
1695 { "(bad)", { XX } },
1696 { "(bad)", { XX } },
1697 { "(bad)", { XX } },
252b5132 1698 },
1ceb70f8 1699 /* REG_0F71 */
a6bd098c 1700 {
ce518a5f
L		 1701 { "(bad)", { XX } },
1702 { "(bad)", { XX } },
1ceb70f8 1703 { MOD_TABLE (MOD_0F71_REG_2) },
ce518a5f 1704 { "(bad)", { XX } },
1ceb70f8 1705 { MOD_TABLE (MOD_0F71_REG_4) },
ce518a5f 1706 { "(bad)", { XX } },
1ceb70f8 1707 { MOD_TABLE (MOD_0F71_REG_6) },
ce518a5f 1708 { "(bad)", { XX } },
a6bd098c 1709 },
1ceb70f8 1710 /* REG_0F72 */
a6bd098c 1711 {
ce518a5f
L		 1712 { "(bad)", { XX } },
1713 { "(bad)", { XX } },
1ceb70f8 1714 { MOD_TABLE (MOD_0F72_REG_2) },
ce518a5f 1715 { "(bad)", { XX } },
1ceb70f8 1716 { MOD_TABLE (MOD_0F72_REG_4) },
ce518a5f 1717 { "(bad)", { XX } },
1ceb70f8 1718 { MOD_TABLE (MOD_0F72_REG_6) },
ce518a5f 1719 { "(bad)", { XX } },
a6bd098c 1720 },
1ceb70f8 1721 /* REG_0F73 */
252b5132 1722 {
ce518a5f
L		 1723 { "(bad)", { XX } },
1724 { "(bad)", { XX } },
1ceb70f8
L		 1725 { MOD_TABLE (MOD_0F73_REG_2) },
1726 { MOD_TABLE (MOD_0F73_REG_3) },
ce518a5f 1727 { "(bad)", { XX } },
ce518a5f 1728 { "(bad)", { XX } },
1ceb70f8
L		 1729 { MOD_TABLE (MOD_0F73_REG_6) },
1730 { MOD_TABLE (MOD_0F73_REG_7) },
252b5132 1731 },
1ceb70f8 1732 /* REG_0FA6 */
252b5132 1733 {
4e7d34a6
L		 1734 { "montmul", { { OP_0f07, 0 } } },
1735 { "xsha1", { { OP_0f07, 0 } } },
1736 { "xsha256", { { OP_0f07, 0 } } },
1737 { "(bad)", { { OP_0f07, 0 } } },
1738 { "(bad)", { { OP_0f07, 0 } } },
1739 { "(bad)", { { OP_0f07, 0 } } },
1740 { "(bad)", { { OP_0f07, 0 } } },
1741 { "(bad)", { { OP_0f07, 0 } } },
1742 },
1ceb70f8 1743 /* REG_0FA7 */
4e7d34a6
L		 1744 {
1745 { "xstore-rng", { { OP_0f07, 0 } } },
1746 { "xcrypt-ecb", { { OP_0f07, 0 } } },
1747 { "xcrypt-cbc", { { OP_0f07, 0 } } },
1748 { "xcrypt-ctr", { { OP_0f07, 0 } } },
1749 { "xcrypt-cfb", { { OP_0f07, 0 } } },
1750 { "xcrypt-ofb", { { OP_0f07, 0 } } },
1751 { "(bad)", { { OP_0f07, 0 } } },
1752 { "(bad)", { { OP_0f07, 0 } } },
1753 },
1ceb70f8 1754 /* REG_0FAE */
4e7d34a6 1755 {
1ceb70f8
L		 1756 { MOD_TABLE (MOD_0FAE_REG_0) },
1757 { MOD_TABLE (MOD_0FAE_REG_1) },
1758 { MOD_TABLE (MOD_0FAE_REG_2) },
1759 { MOD_TABLE (MOD_0FAE_REG_3) },
ce518a5f 1760 { "(bad)", { XX } },
1ceb70f8
L		 1761 { MOD_TABLE (MOD_0FAE_REG_5) },
1762 { MOD_TABLE (MOD_0FAE_REG_6) },
1763 { MOD_TABLE (MOD_0FAE_REG_7) },
252b5132 1764 },
1ceb70f8 1765 /* REG_0FBA */
252b5132 1766 {
ce518a5f
L		 1767 { "(bad)", { XX } },
1768 { "(bad)", { XX } },
d8faab4e
L		 1769 { "(bad)", { XX } },
1770 { "(bad)", { XX } },
4e7d34a6
L		 1771 { "btQ", { Ev, Ib } },
1772 { "btsQ", { Ev, Ib } },
1773 { "btrQ", { Ev, Ib } },
1774 { "btcQ", { Ev, Ib } },
c608c12e 1775 },
1ceb70f8 1776 /* REG_0FC7 */
c608c12e 1777 {
b844680a 1778 { "(bad)", { XX } },
4e7d34a6 1779 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
d8faab4e 1780 { "(bad)", { XX } },
b844680a
L		 1781 { "(bad)", { XX } },
1782 { "(bad)", { XX } },
1783 { "(bad)", { XX } },
1ceb70f8
L		 1784 { MOD_TABLE (MOD_0FC7_REG_6) },
1785 { MOD_TABLE (MOD_0FC7_REG_7) },
252b5132 1786 },
4e7d34a6
L		 1787};
1788
1ceb70f8
L		 1789static const struct dis386 prefix_table[][4] = {
1790 /* PREFIX_90 */
252b5132 1791 {
4e7d34a6
L		 1792 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
1793 { "pause", { XX } },
1794 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
1795 { "(bad)", { XX } },
0f10071e 1796 },
4e7d34a6 1797
1ceb70f8 1798 /* PREFIX_0F10 */
cc0ec051 1799 {
4e7d34a6
L		 1800 { "movups", { XM, EXx } },
1801 { "movss", { XM, EXd } },
1802 { "movupd", { XM, EXx } },
1803 { "movsd", { XM, EXq } },
30d1c836 1804 },
4e7d34a6 1805
1ceb70f8 1806 /* PREFIX_0F11 */
30d1c836 1807 {
d5d7db8e
L		 1808 { "movups", { EXx, XM } },
1809 { "movss", { EXd, XM } },
1810 { "movupd", { EXx, XM } },
1811 { "movsd", { EXq, XM } },
4e7d34a6 1812 },
252b5132 1813
1ceb70f8 1814 /* PREFIX_0F12 */
c608c12e 1815 {
1ceb70f8 1816 { MOD_TABLE (MOD_0F12_PREFIX_0) },
4e7d34a6
L		 1817 { "movsldup", { XM, EXx } },
1818 { "movlpd", { XM, EXq } },
1819 { "movddup", { XM, EXq } },
c608c12e 1820 },
4e7d34a6 1821
1ceb70f8 1822 /* PREFIX_0F16 */
c608c12e 1823 {
1ceb70f8 1824 { MOD_TABLE (MOD_0F16_PREFIX_0) },
4e7d34a6
L		 1825 { "movshdup", { XM, EXx } },
1826 { "movhpd", { XM, EXq } },
058f233b 1827 { "(bad)", { XX } },
c608c12e 1828 },
4e7d34a6 1829
1ceb70f8 1830 /* PREFIX_0F2A */
c608c12e 1831 {
09335d05 1832 { "cvtpi2ps", { XM, EMCq } },
ce518a5f 1833 { "cvtsi2ssY", { XM, Ev } },
09335d05 1834 { "cvtpi2pd", { XM, EMCq } },
ce518a5f 1835 { "cvtsi2sdY", { XM, Ev } },
c608c12e 1836 },
4e7d34a6 1837
1ceb70f8 1838 /* PREFIX_0F2B */
c608c12e 1839 {
75c135a8
L		 1840 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
1841 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
1842 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
1843 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
c608c12e 1844 },
4e7d34a6 1845
1ceb70f8 1846 /* PREFIX_0F2C */
c608c12e 1847 {
09335d05
L		 1848 { "cvttps2pi", { MXC, EXq } },
1849 { "cvttss2siY", { Gv, EXd } },
09a2c6cf 1850 { "cvttpd2pi", { MXC, EXx } },
09335d05 1851 { "cvttsd2siY", { Gv, EXq } },
c608c12e 1852 },
4e7d34a6 1853
1ceb70f8 1854 /* PREFIX_0F2D */
c608c12e 1855 {
4e7d34a6
L		 1856 { "cvtps2pi", { MXC, EXq } },
1857 { "cvtss2siY", { Gv, EXd } },
1858 { "cvtpd2pi", { MXC, EXx } },
1859 { "cvtsd2siY", { Gv, EXq } },
c608c12e 1860 },
4e7d34a6 1861
1ceb70f8 1862 /* PREFIX_0F2E */
c608c12e 1863 {
4e7d34a6
L		 1864 { "ucomiss",{ XM, EXd } },
1865 { "(bad)", { XX } },
1866 { "ucomisd",{ XM, EXq } },
1867 { "(bad)", { XX } },
c608c12e 1868 },
4e7d34a6 1869
1ceb70f8 1870 /* PREFIX_0F2F */
c608c12e 1871 {
4e7d34a6
L		 1872 { "comiss", { XM, EXd } },
1873 { "(bad)", { XX } },
1874 { "comisd", { XM, EXq } },
1875 { "(bad)", { XX } },
c608c12e 1876 },
4e7d34a6 1877
1ceb70f8 1878 /* PREFIX_0F51 */
c608c12e 1879 {
4e7d34a6
L		 1880 { "sqrtps", { XM, EXx } },
1881 { "sqrtss", { XM, EXd } },
1882 { "sqrtpd", { XM, EXx } },
1883 { "sqrtsd", { XM, EXq } },
c608c12e 1884 },
4e7d34a6 1885
1ceb70f8 1886 /* PREFIX_0F52 */
c608c12e 1887 {
4e7d34a6
L		 1888 { "rsqrtps",{ XM, EXx } },
1889 { "rsqrtss",{ XM, EXd } },
058f233b
L		 1890 { "(bad)", { XX } },
1891 { "(bad)", { XX } },
c608c12e 1892 },
4e7d34a6 1893
1ceb70f8 1894 /* PREFIX_0F53 */
c608c12e 1895 {
4e7d34a6
L		 1896 { "rcpps", { XM, EXx } },
1897 { "rcpss", { XM, EXd } },
058f233b
L		 1898 { "(bad)", { XX } },
1899 { "(bad)", { XX } },
c608c12e 1900 },
4e7d34a6 1901
1ceb70f8 1902 /* PREFIX_0F58 */
c608c12e 1903 {
4e7d34a6
L		 1904 { "addps", { XM, EXx } },
1905 { "addss", { XM, EXd } },
1906 { "addpd", { XM, EXx } },
1907 { "addsd", { XM, EXq } },
c608c12e 1908 },
4e7d34a6 1909
1ceb70f8 1910 /* PREFIX_0F59 */
c608c12e 1911 {
4e7d34a6
L		 1912 { "mulps", { XM, EXx } },
1913 { "mulss", { XM, EXd } },
1914 { "mulpd", { XM, EXx } },
1915 { "mulsd", { XM, EXq } },
041bd2e0 1916 },
4e7d34a6 1917
1ceb70f8 1918 /* PREFIX_0F5A */
041bd2e0 1919 {
4e7d34a6
L		 1920 { "cvtps2pd", { XM, EXq } },
1921 { "cvtss2sd", { XM, EXd } },
1922 { "cvtpd2ps", { XM, EXx } },
1923 { "cvtsd2ss", { XM, EXq } },
041bd2e0 1924 },
4e7d34a6 1925
1ceb70f8 1926 /* PREFIX_0F5B */
041bd2e0 1927 {
09a2c6cf
L		 1928 { "cvtdq2ps", { XM, EXx } },
1929 { "cvttps2dq", { XM, EXx } },
1930 { "cvtps2dq", { XM, EXx } },
058f233b 1931 { "(bad)", { XX } },
041bd2e0 1932 },
4e7d34a6 1933
1ceb70f8 1934 /* PREFIX_0F5C */
041bd2e0 1935 {
4e7d34a6
L		 1936 { "subps", { XM, EXx } },
1937 { "subss", { XM, EXd } },
1938 { "subpd", { XM, EXx } },
1939 { "subsd", { XM, EXq } },
041bd2e0 1940 },
4e7d34a6 1941
1ceb70f8 1942 /* PREFIX_0F5D */
041bd2e0 1943 {
4e7d34a6
L		 1944 { "minps", { XM, EXx } },
1945 { "minss", { XM, EXd } },
1946 { "minpd", { XM, EXx } },
1947 { "minsd", { XM, EXq } },
041bd2e0 1948 },
4e7d34a6 1949
1ceb70f8 1950 /* PREFIX_0F5E */
041bd2e0 1951 {
4e7d34a6
L		 1952 { "divps", { XM, EXx } },
1953 { "divss", { XM, EXd } },
1954 { "divpd", { XM, EXx } },
1955 { "divsd", { XM, EXq } },
041bd2e0 1956 },
4e7d34a6 1957
1ceb70f8 1958 /* PREFIX_0F5F */
041bd2e0 1959 {
4e7d34a6
L		 1960 { "maxps", { XM, EXx } },
1961 { "maxss", { XM, EXd } },
1962 { "maxpd", { XM, EXx } },
1963 { "maxsd", { XM, EXq } },
041bd2e0 1964 },
4e7d34a6 1965
1ceb70f8 1966 /* PREFIX_0F60 */
041bd2e0 1967 {
4e7d34a6
L		 1968 { "punpcklbw",{ MX, EMd } },
1969 { "(bad)", { XX } },
1970 { "punpcklbw",{ MX, EMx } },
1971 { "(bad)", { XX } },
041bd2e0 1972 },
4e7d34a6 1973
1ceb70f8 1974 /* PREFIX_0F61 */
041bd2e0 1975 {
4e7d34a6
L		 1976 { "punpcklwd",{ MX, EMd } },
1977 { "(bad)", { XX } },
1978 { "punpcklwd",{ MX, EMx } },
1979 { "(bad)", { XX } },
041bd2e0 1980 },
4e7d34a6 1981
1ceb70f8 1982 /* PREFIX_0F62 */
041bd2e0 1983 {
4e7d34a6
L		 1984 { "punpckldq",{ MX, EMd } },
1985 { "(bad)", { XX } },
1986 { "punpckldq",{ MX, EMx } },
1987 { "(bad)", { XX } },
041bd2e0 1988 },
4e7d34a6 1989
1ceb70f8 1990 /* PREFIX_0F6C */
041bd2e0 1991 {
058f233b
L		 1992 { "(bad)", { XX } },
1993 { "(bad)", { XX } },
4e7d34a6 1994 { "punpcklqdq", { XM, EXx } },
058f233b 1995 { "(bad)", { XX } },
0f17484f 1996 },
4e7d34a6 1997
1ceb70f8 1998 /* PREFIX_0F6D */
0f17484f 1999 {
058f233b
L		 2000 { "(bad)", { XX } },
2001 { "(bad)", { XX } },
4e7d34a6 2002 { "punpckhqdq", { XM, EXx } },
058f233b 2003 { "(bad)", { XX } },
041bd2e0 2004 },
4e7d34a6 2005
1ceb70f8 2006 /* PREFIX_0F6F */
ca164297 2007 {
4e7d34a6
L		 2008 { "movq", { MX, EM } },
2009 { "movdqu", { XM, EXx } },
2010 { "movdqa", { XM, EXx } },
058f233b 2011 { "(bad)", { XX } },
ca164297 2012 },
4e7d34a6 2013
1ceb70f8 2014 /* PREFIX_0F70 */
4e7d34a6
L		 2015 {
2016 { "pshufw", { MX, EM, Ib } },
2017 { "pshufhw",{ XM, EXx, Ib } },
2018 { "pshufd", { XM, EXx, Ib } },
2019 { "pshuflw",{ XM, EXx, Ib } },
2020 },
2021
92fddf8e
L		 2022 /* PREFIX_0F73_REG_3 */
2023 {
2024 { "(bad)", { XX } },
2025 { "(bad)", { XX } },
2026 { "psrldq", { XS, Ib } },
2027 { "(bad)", { XX } },
2028 },
2029
2030 /* PREFIX_0F73_REG_7 */
2031 {
2032 { "(bad)", { XX } },
2033 { "(bad)", { XX } },
2034 { "pslldq", { XS, Ib } },
2035 { "(bad)", { XX } },
2036 },
2037
1ceb70f8 2038 /* PREFIX_0F78 */
4e7d34a6
L		 2039 {
2040 {"vmread", { Em, Gm } },
2041 {"(bad)", { XX } },
2042 {"extrq", { XS, Ib, Ib } },
2043 {"insertq", { XM, XS, Ib, Ib } },
2044 },
2045
1ceb70f8 2046 /* PREFIX_0F79 */
4e7d34a6
L		 2047 {
2048 {"vmwrite", { Gm, Em } },
2049 {"(bad)", { XX } },
2050 {"extrq", { XM, XS } },
2051 {"insertq", { XM, XS } },
2052 },
2053
1ceb70f8 2054 /* PREFIX_0F7C */
ca164297 2055 {
058f233b
L		 2056 { "(bad)", { XX } },
2057 { "(bad)", { XX } },
09a2c6cf
L		 2058 { "haddpd", { XM, EXx } },
2059 { "haddps", { XM, EXx } },
ca164297 2060 },
4e7d34a6 2061
1ceb70f8 2062 /* PREFIX_0F7D */
ca164297 2063 {
058f233b
L		 2064 { "(bad)", { XX } },
2065 { "(bad)", { XX } },
09a2c6cf
L		 2066 { "hsubpd", { XM, EXx } },
2067 { "hsubps", { XM, EXx } },
ca164297 2068 },
4e7d34a6 2069
1ceb70f8 2070 /* PREFIX_0F7E */
ca164297 2071 {
4e7d34a6
L		 2072 { "movK", { Edq, MX } },
2073 { "movq", { XM, EXq } },
2074 { "movK", { Edq, XM } },
058f233b 2075 { "(bad)", { XX } },
ca164297 2076 },
4e7d34a6 2077
1ceb70f8 2078 /* PREFIX_0F7F */
ca164297 2079 {
4e7d34a6 2080 { "movq", { EM, MX } },
d5d7db8e
L		 2081 { "movdqu", { EXx, XM } },
2082 { "movdqa", { EXx, XM } },
058f233b 2083 { "(bad)", { XX } },
ca164297 2084 },
4e7d34a6 2085
1ceb70f8 2086 /* PREFIX_0FB8 */
ca164297 2087 {
4e7d34a6
L		 2088 { "(bad)", { XX } },
2089 { "popcntS", { Gv, Ev } },
2090 { "(bad)", { XX } },
2091 { "(bad)", { XX } },
ca164297 2092 },
4e7d34a6 2093
1ceb70f8 2094 /* PREFIX_0FBD */
050dfa73 2095 {
4e7d34a6
L		 2096 { "bsrS", { Gv, Ev } },
2097 { "lzcntS", { Gv, Ev } },
2098 { "bsrS", { Gv, Ev } },
2099 { "(bad)", { XX } },
050dfa73
MM		 2100 },
2101
1ceb70f8 2102 /* PREFIX_0FC2 */
050dfa73 2103 {
ad19981d
L		 2104 { "cmpps", { XM, EXx, CMP } },
2105 { "cmpss", { XM, EXd, CMP } },
2106 { "cmppd", { XM, EXx, CMP } },
2107 { "cmpsd", { XM, EXq, CMP } },
050dfa73 2108 },
246c51aa 2109
92fddf8e
L		 2110 /* PREFIX_0FC7_REG_6 */
2111 {
2112 { "vmptrld",{ Mq } },
2113 { "vmxon", { Mq } },
2114 { "vmclear",{ Mq } },
2115 { "(bad)", { XX } },
2116 },
2117
1ceb70f8 2118 /* PREFIX_0FD0 */
050dfa73 2119 {
058f233b
L		 2120 { "(bad)", { XX } },
2121 { "(bad)", { XX } },
4e7d34a6
L		 2122 { "addsubpd", { XM, EXx } },
2123 { "addsubps", { XM, EXx } },
246c51aa 2124 },
050dfa73 2125
1ceb70f8 2126 /* PREFIX_0FD6 */
050dfa73 2127 {
058f233b 2128 { "(bad)", { XX } },
4e7d34a6
L		 2129 { "movq2dq",{ XM, MS } },
2130 { "movq", { EXq, XM } },
2131 { "movdq2q",{ MX, XS } },
050dfa73
MM		 2132 },
2133
1ceb70f8 2134 /* PREFIX_0FE6 */
7918206c 2135 {
058f233b 2136 { "(bad)", { XX } },
4e7d34a6
L		 2137 { "cvtdq2pd", { XM, EXq } },
2138 { "cvttpd2dq", { XM, EXx } },
2139 { "cvtpd2dq", { XM, EXx } },
7918206c 2140 },
8b38ad71 2141
1ceb70f8 2142 /* PREFIX_0FE7 */
8b38ad71 2143 {
4e7d34a6 2144 { "movntq", { EM, MX } },
058f233b 2145 { "(bad)", { XX } },
75c135a8 2146 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
058f233b 2147 { "(bad)", { XX } },
4e7d34a6
L		 2148 },
2149
1ceb70f8 2150 /* PREFIX_0FF0 */
4e7d34a6 2151 {
058f233b
L		 2152 { "(bad)", { XX } },
2153 { "(bad)", { XX } },
2154 { "(bad)", { XX } },
1ceb70f8 2155 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4e7d34a6
L		 2156 },
2157
1ceb70f8 2158 /* PREFIX_0FF7 */
4e7d34a6
L		 2159 {
2160 { "maskmovq", { MX, MS } },
058f233b 2161 { "(bad)", { XX } },
4e7d34a6 2162 { "maskmovdqu", { XM, XS } },
058f233b 2163 { "(bad)", { XX } },
8b38ad71 2164 },
42903f7f 2165
1ceb70f8 2166 /* PREFIX_0F3810 */
42903f7f
L		 2167 {
2168 { "(bad)", { XX } },
2169 { "(bad)", { XX } },
88a94849 2170 { "pblendvb", { XM, EXx, XMM0 } },
42903f7f
L		 2171 { "(bad)", { XX } },
2172 },
2173
1ceb70f8 2174 /* PREFIX_0F3814 */
42903f7f
L		 2175 {
2176 { "(bad)", { XX } },
2177 { "(bad)", { XX } },
88a94849 2178 { "blendvps", { XM, EXx, XMM0 } },
42903f7f
L		 2179 { "(bad)", { XX } },
2180 },
2181
1ceb70f8 2182 /* PREFIX_0F3815 */
42903f7f
L		 2183 {
2184 { "(bad)", { XX } },
2185 { "(bad)", { XX } },
09a2c6cf 2186 { "blendvpd", { XM, EXx, XMM0 } },
42903f7f
L		 2187 { "(bad)", { XX } },
2188 },
2189
1ceb70f8 2190 /* PREFIX_0F3817 */
42903f7f
L		 2191 {
2192 { "(bad)", { XX } },
2193 { "(bad)", { XX } },
09a2c6cf 2194 { "ptest", { XM, EXx } },
42903f7f
L		 2195 { "(bad)", { XX } },
2196 },
2197
1ceb70f8 2198 /* PREFIX_0F3820 */
42903f7f
L		 2199 {
2200 { "(bad)", { XX } },
2201 { "(bad)", { XX } },
8976381e 2202 { "pmovsxbw", { XM, EXq } },
42903f7f
L		 2203 { "(bad)", { XX } },
2204 },
2205
1ceb70f8 2206 /* PREFIX_0F3821 */
42903f7f
L		 2207 {
2208 { "(bad)", { XX } },
2209 { "(bad)", { XX } },
8976381e 2210 { "pmovsxbd", { XM, EXd } },
42903f7f
L		 2211 { "(bad)", { XX } },
2212 },
2213
1ceb70f8 2214 /* PREFIX_0F3822 */
42903f7f
L		 2215 {
2216 { "(bad)", { XX } },
2217 { "(bad)", { XX } },
8976381e 2218 { "pmovsxbq", { XM, EXw } },
42903f7f
L		 2219 { "(bad)", { XX } },
2220 },
2221
1ceb70f8 2222 /* PREFIX_0F3823 */
42903f7f
L		 2223 {
2224 { "(bad)", { XX } },
2225 { "(bad)", { XX } },
8976381e 2226 { "pmovsxwd", { XM, EXq } },
42903f7f
L		 2227 { "(bad)", { XX } },
2228 },
2229
1ceb70f8 2230 /* PREFIX_0F3824 */
42903f7f
L		 2231 {
2232 { "(bad)", { XX } },
2233 { "(bad)", { XX } },
8976381e 2234 { "pmovsxwq", { XM, EXd } },
42903f7f
L		 2235 { "(bad)", { XX } },
2236 },
2237
1ceb70f8 2238 /* PREFIX_0F3825 */
42903f7f
L		 2239 {
2240 { "(bad)", { XX } },
2241 { "(bad)", { XX } },
8976381e 2242 { "pmovsxdq", { XM, EXq } },
42903f7f
L		 2243 { "(bad)", { XX } },
2244 },
2245
1ceb70f8 2246 /* PREFIX_0F3828 */
42903f7f
L		 2247 {
2248 { "(bad)", { XX } },
2249 { "(bad)", { XX } },
09a2c6cf 2250 { "pmuldq", { XM, EXx } },
42903f7f
L		 2251 { "(bad)", { XX } },
2252 },
2253
1ceb70f8 2254 /* PREFIX_0F3829 */
42903f7f
L		 2255 {
2256 { "(bad)", { XX } },
2257 { "(bad)", { XX } },
09a2c6cf 2258 { "pcmpeqq", { XM, EXx } },
42903f7f
L		 2259 { "(bad)", { XX } },
2260 },
2261
1ceb70f8 2262 /* PREFIX_0F382A */
42903f7f
L		 2263 {
2264 { "(bad)", { XX } },
2265 { "(bad)", { XX } },
75c135a8 2266 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
42903f7f
L		 2267 { "(bad)", { XX } },
2268 },
2269
1ceb70f8 2270 /* PREFIX_0F382B */
42903f7f
L		 2271 {
2272 { "(bad)", { XX } },
2273 { "(bad)", { XX } },
09a2c6cf 2274 { "packusdw", { XM, EXx } },
42903f7f
L		 2275 { "(bad)", { XX } },
2276 },
2277
1ceb70f8 2278 /* PREFIX_0F3830 */
42903f7f
L		 2279 {
2280 { "(bad)", { XX } },
2281 { "(bad)", { XX } },
8976381e 2282 { "pmovzxbw", { XM, EXq } },
42903f7f
L		 2283 { "(bad)", { XX } },
2284 },
2285
1ceb70f8 2286 /* PREFIX_0F3831 */
42903f7f
L		 2287 {
2288 { "(bad)", { XX } },
2289 { "(bad)", { XX } },
8976381e 2290 { "pmovzxbd", { XM, EXd } },
42903f7f
L		 2291 { "(bad)", { XX } },
2292 },
2293
1ceb70f8 2294 /* PREFIX_0F3832 */
42903f7f
L		 2295 {
2296 { "(bad)", { XX } },
2297 { "(bad)", { XX } },
8976381e 2298 { "pmovzxbq", { XM, EXw } },
42903f7f
L		 2299 { "(bad)", { XX } },
2300 },
2301
1ceb70f8 2302 /* PREFIX_0F3833 */
42903f7f
L		 2303 {
2304 { "(bad)", { XX } },
2305 { "(bad)", { XX } },
8976381e 2306 { "pmovzxwd", { XM, EXq } },
42903f7f
L		 2307 { "(bad)", { XX } },
2308 },
2309
1ceb70f8 2310 /* PREFIX_0F3834 */
42903f7f
L		 2311 {
2312 { "(bad)", { XX } },
2313 { "(bad)", { XX } },
8976381e 2314 { "pmovzxwq", { XM, EXd } },
42903f7f
L		 2315 { "(bad)", { XX } },
2316 },
2317
1ceb70f8 2318 /* PREFIX_0F3835 */
42903f7f
L		 2319 {
2320 { "(bad)", { XX } },
2321 { "(bad)", { XX } },
8976381e 2322 { "pmovzxdq", { XM, EXq } },
42903f7f
L		 2323 { "(bad)", { XX } },
2324 },
2325
1ceb70f8 2326 /* PREFIX_0F3837 */
4e7d34a6
L		 2327 {
2328 { "(bad)", { XX } },
2329 { "(bad)", { XX } },
2330 { "pcmpgtq", { XM, EXx } },
2331 { "(bad)", { XX } },
2332 },
2333
1ceb70f8 2334 /* PREFIX_0F3838 */
42903f7f
L		 2335 {
2336 { "(bad)", { XX } },
2337 { "(bad)", { XX } },
09a2c6cf 2338 { "pminsb", { XM, EXx } },
42903f7f
L		 2339 { "(bad)", { XX } },
2340 },
2341
1ceb70f8 2342 /* PREFIX_0F3839 */
42903f7f
L		 2343 {
2344 { "(bad)", { XX } },
2345 { "(bad)", { XX } },
09a2c6cf 2346 { "pminsd", { XM, EXx } },
42903f7f
L		 2347 { "(bad)", { XX } },
2348 },
2349
1ceb70f8 2350 /* PREFIX_0F383A */
42903f7f
L		 2351 {
2352 { "(bad)", { XX } },
2353 { "(bad)", { XX } },
09a2c6cf 2354 { "pminuw", { XM, EXx } },
42903f7f
L		 2355 { "(bad)", { XX } },
2356 },
2357
1ceb70f8 2358 /* PREFIX_0F383B */
42903f7f
L		 2359 {
2360 { "(bad)", { XX } },
2361 { "(bad)", { XX } },
09a2c6cf 2362 { "pminud", { XM, EXx } },
42903f7f
L		 2363 { "(bad)", { XX } },
2364 },
2365
1ceb70f8 2366 /* PREFIX_0F383C */
42903f7f
L		 2367 {
2368 { "(bad)", { XX } },
2369 { "(bad)", { XX } },
09a2c6cf 2370 { "pmaxsb", { XM, EXx } },
42903f7f
L		 2371 { "(bad)", { XX } },
2372 },
2373
1ceb70f8 2374 /* PREFIX_0F383D */
42903f7f
L		 2375 {
2376 { "(bad)", { XX } },
2377 { "(bad)", { XX } },
09a2c6cf 2378 { "pmaxsd", { XM, EXx } },
42903f7f
L		 2379 { "(bad)", { XX } },
2380 },
2381
1ceb70f8 2382 /* PREFIX_0F383E */
42903f7f
L		 2383 {
2384 { "(bad)", { XX } },
2385 { "(bad)", { XX } },
09a2c6cf 2386 { "pmaxuw", { XM, EXx } },
42903f7f
L		 2387 { "(bad)", { XX } },
2388 },
2389
1ceb70f8 2390 /* PREFIX_0F383F */
42903f7f
L		 2391 {
2392 { "(bad)", { XX } },
2393 { "(bad)", { XX } },
09a2c6cf 2394 { "pmaxud", { XM, EXx } },
42903f7f
L		 2395 { "(bad)", { XX } },
2396 },
2397
1ceb70f8 2398 /* PREFIX_0F3840 */
42903f7f
L		 2399 {
2400 { "(bad)", { XX } },
2401 { "(bad)", { XX } },
09a2c6cf 2402 { "pmulld", { XM, EXx } },
42903f7f
L		 2403 { "(bad)", { XX } },
2404 },
2405
1ceb70f8 2406 /* PREFIX_0F3841 */
42903f7f
L		 2407 {
2408 { "(bad)", { XX } },
2409 { "(bad)", { XX } },
09a2c6cf 2410 { "phminposuw", { XM, EXx } },
42903f7f
L		 2411 { "(bad)", { XX } },
2412 },
2413
1ceb70f8 2414 /* PREFIX_0F38F0 */
4e7d34a6
L		 2415 {
2416 { "(bad)", { XX } },
2417 { "(bad)", { XX } },
2418 { "(bad)", { XX } },
2419 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
2420 },
2421
1ceb70f8 2422 /* PREFIX_0F38F1 */
4e7d34a6
L		 2423 {
2424 { "(bad)", { XX } },
2425 { "(bad)", { XX } },
2426 { "(bad)", { XX } },
2427 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
2428 },
2429
1ceb70f8 2430 /* PREFIX_0F3A08 */
42903f7f
L		 2431 {
2432 { "(bad)", { XX } },
2433 { "(bad)", { XX } },
09a2c6cf 2434 { "roundps", { XM, EXx, Ib } },
42903f7f
L		 2435 { "(bad)", { XX } },
2436 },
2437
1ceb70f8 2438 /* PREFIX_0F3A09 */
42903f7f
L		 2439 {
2440 { "(bad)", { XX } },
2441 { "(bad)", { XX } },
09a2c6cf 2442 { "roundpd", { XM, EXx, Ib } },
42903f7f
L		 2443 { "(bad)", { XX } },
2444 },
2445
1ceb70f8 2446 /* PREFIX_0F3A0A */
42903f7f
L		 2447 {
2448 { "(bad)", { XX } },
2449 { "(bad)", { XX } },
09335d05 2450 { "roundss", { XM, EXd, Ib } },
42903f7f
L		 2451 { "(bad)", { XX } },
2452 },
2453
1ceb70f8 2454 /* PREFIX_0F3A0B */
42903f7f
L		 2455 {
2456 { "(bad)", { XX } },
2457 { "(bad)", { XX } },
09335d05 2458 { "roundsd", { XM, EXq, Ib } },
42903f7f
L		 2459 { "(bad)", { XX } },
2460 },
2461
1ceb70f8 2462 /* PREFIX_0F3A0C */
42903f7f
L		 2463 {
2464 { "(bad)", { XX } },
2465 { "(bad)", { XX } },
09a2c6cf 2466 { "blendps", { XM, EXx, Ib } },
42903f7f
L		 2467 { "(bad)", { XX } },
2468 },
2469
1ceb70f8 2470 /* PREFIX_0F3A0D */
42903f7f
L		 2471 {
2472 { "(bad)", { XX } },
2473 { "(bad)", { XX } },
09a2c6cf 2474 { "blendpd", { XM, EXx, Ib } },
42903f7f
L		 2475 { "(bad)", { XX } },
2476 },
2477
1ceb70f8 2478 /* PREFIX_0F3A0E */
42903f7f
L		 2479 {
2480 { "(bad)", { XX } },
2481 { "(bad)", { XX } },
09a2c6cf 2482 { "pblendw", { XM, EXx, Ib } },
42903f7f
L		 2483 { "(bad)", { XX } },
2484 },
2485
1ceb70f8 2486 /* PREFIX_0F3A14 */
42903f7f
L		 2487 {
2488 { "(bad)", { XX } },
2489 { "(bad)", { XX } },
2490 { "pextrb", { Edqb, XM, Ib } },
2491 { "(bad)", { XX } },
2492 },
2493
1ceb70f8 2494 /* PREFIX_0F3A15 */
42903f7f
L		 2495 {
2496 { "(bad)", { XX } },
2497 { "(bad)", { XX } },
2498 { "pextrw", { Edqw, XM, Ib } },
2499 { "(bad)", { XX } },
2500 },
2501
1ceb70f8 2502 /* PREFIX_0F3A16 */
42903f7f
L		 2503 {
2504 { "(bad)", { XX } },
2505 { "(bad)", { XX } },
2506 { "pextrK", { Edq, XM, Ib } },
2507 { "(bad)", { XX } },
2508 },
2509
1ceb70f8 2510 /* PREFIX_0F3A17 */
42903f7f
L		 2511 {
2512 { "(bad)", { XX } },
2513 { "(bad)", { XX } },
2514 { "extractps", { Edqd, XM, Ib } },
2515 { "(bad)", { XX } },
2516 },
2517
1ceb70f8 2518 /* PREFIX_0F3A20 */
42903f7f
L		 2519 {
2520 { "(bad)", { XX } },
2521 { "(bad)", { XX } },
2522 { "pinsrb", { XM, Edqb, Ib } },
2523 { "(bad)", { XX } },
2524 },
2525
1ceb70f8 2526 /* PREFIX_0F3A21 */
42903f7f
L		 2527 {
2528 { "(bad)", { XX } },
2529 { "(bad)", { XX } },
8976381e 2530 { "insertps", { XM, EXd, Ib } },
42903f7f
L		 2531 { "(bad)", { XX } },
2532 },
2533
1ceb70f8 2534 /* PREFIX_0F3A22 */
42903f7f
L		 2535 {
2536 { "(bad)", { XX } },
2537 { "(bad)", { XX } },
2538 { "pinsrK", { XM, Edq, Ib } },
2539 { "(bad)", { XX } },
2540 },
2541
1ceb70f8 2542 /* PREFIX_0F3A40 */
42903f7f
L		 2543 {
2544 { "(bad)", { XX } },
2545 { "(bad)", { XX } },
09a2c6cf 2546 { "dpps", { XM, EXx, Ib } },
42903f7f
L		 2547 { "(bad)", { XX } },
2548 },
2549
1ceb70f8 2550 /* PREFIX_0F3A41 */
42903f7f
L		 2551 {
2552 { "(bad)", { XX } },
2553 { "(bad)", { XX } },
09a2c6cf 2554 { "dppd", { XM, EXx, Ib } },
42903f7f
L		 2555 { "(bad)", { XX } },
2556 },
2557
1ceb70f8 2558 /* PREFIX_0F3A42 */
42903f7f
L		 2559 {
2560 { "(bad)", { XX } },
2561 { "(bad)", { XX } },
09a2c6cf 2562 { "mpsadbw", { XM, EXx, Ib } },
42903f7f
L		 2563 { "(bad)", { XX } },
2564 },
381d071f 2565
1ceb70f8 2566 /* PREFIX_0F3A60 */
381d071f
L		 2567 {
2568 { "(bad)", { XX } },
2569 { "(bad)", { XX } },
4e7d34a6 2570 { "pcmpestrm", { XM, EXx, Ib } },
381d071f
L		 2571 { "(bad)", { XX } },
2572 },
2573
1ceb70f8 2574 /* PREFIX_0F3A61 */
381d071f
L		 2575 {
2576 { "(bad)", { XX } },
2577 { "(bad)", { XX } },
4e7d34a6 2578 { "pcmpestri", { XM, EXx, Ib } },
381d071f 2579 { "(bad)", { XX } },
381d071f
L		 2580 },
2581
1ceb70f8 2582 /* PREFIX_0F3A62 */
381d071f
L		 2583 {
2584 { "(bad)", { XX } },
2585 { "(bad)", { XX } },
4e7d34a6 2586 { "pcmpistrm", { XM, EXx, Ib } },
381d071f 2587 { "(bad)", { XX } },
381d071f
L		 2588 },
2589
1ceb70f8 2590 /* PREFIX_0F3A63 */
381d071f
L		 2591 {
2592 { "(bad)", { XX } },
2593 { "(bad)", { XX } },
4e7d34a6 2594 { "pcmpistri", { XM, EXx, Ib } },
381d071f
L		 2595 { "(bad)", { XX } },
2596 },
4e7d34a6 2597};
09a2c6cf 2598
4e7d34a6
L		 2599static const struct dis386 x86_64_table[][2] = {
2600 /* X86_64_06 */
09a2c6cf 2601 {
4e7d34a6
L		 2602 { "push{T|}", { es } },
2603 { "(bad)", { XX } },
09a2c6cf
L		 2604 },
2605
4e7d34a6 2606 /* X86_64_07 */
09a2c6cf 2607 {
4e7d34a6
L		 2608 { "pop{T|}", { es } },
2609 { "(bad)", { XX } },
09a2c6cf
L		 2610 },
2611
4e7d34a6 2612 /* X86_64_0D */
09a2c6cf 2613 {
4e7d34a6
L		 2614 { "push{T|}", { cs } },
2615 { "(bad)", { XX } },
09a2c6cf
L		 2616 },
2617
4e7d34a6 2618 /* X86_64_16 */
09a2c6cf 2619 {
4e7d34a6
L		 2620 { "push{T|}", { ss } },
2621 { "(bad)", { XX } },
09a2c6cf
L		 2622 },
2623
4e7d34a6 2624 /* X86_64_17 */
09a2c6cf 2625 {
4e7d34a6 2626 { "pop{T|}", { ss } },
ce518a5f 2627 { "(bad)", { XX } },
5f754f58 2628 },
7c52e0e8 2629
4e7d34a6 2630 /* X86_64_1E */
5f754f58 2631 {
4e7d34a6 2632 { "push{T|}", { ds } },
ce518a5f 2633 { "(bad)", { XX } },
5f754f58 2634 },
7c52e0e8 2635
4e7d34a6 2636 /* X86_64_1F */
5f754f58 2637 {
4e7d34a6 2638 { "pop{T|}", { ds } },
ce518a5f 2639 { "(bad)", { XX } },
5f754f58 2640 },
7c52e0e8 2641
4e7d34a6 2642 /* X86_64_27 */
7c52e0e8 2643 {
4e7d34a6 2644 { "daa", { XX } },
7c52e0e8
L		 2645 { "(bad)", { XX } },
2646 },
2647
4e7d34a6 2648 /* X86_64_2F */
7c52e0e8 2649 {
4e7d34a6 2650 { "das", { XX } },
7c52e0e8
L		 2651 { "(bad)", { XX } },
2652 },
2653
4e7d34a6 2654 /* X86_64_37 */
7c52e0e8 2655 {
4e7d34a6 2656 { "aaa", { XX } },
7c52e0e8
L		 2657 { "(bad)", { XX } },
2658 },
2659
4e7d34a6 2660 /* X86_64_3F */
7c52e0e8 2661 {
4e7d34a6 2662 { "aas", { XX } },
7c52e0e8
L		 2663 { "(bad)", { XX } },
2664 },
2665
4e7d34a6 2666 /* X86_64_60 */
7c52e0e8 2667 {
4e7d34a6 2668 { "pusha{P|}", { XX } },
7c52e0e8
L		 2669 { "(bad)", { XX } },
2670 },
2671
4e7d34a6 2672 /* X86_64_61 */
7c52e0e8 2673 {
4e7d34a6 2674 { "popa{P|}", { XX } },
7c52e0e8
L		 2675 { "(bad)", { XX } },
2676 },
2677
4e7d34a6 2678 /* X86_64_62 */
7c52e0e8 2679 {
1ceb70f8 2680 { MOD_TABLE (MOD_62_32BIT) },
7c52e0e8
L		 2681 { "(bad)", { XX } },
2682 },
2683
4e7d34a6 2684 /* X86_64_63 */
7c52e0e8 2685 {
4e7d34a6
L		 2686 { "arpl", { Ew, Gw } },
2687 { "movs{lq|xd}", { Gv, Ed } },
7c52e0e8
L		 2688 },
2689
4e7d34a6 2690 /* X86_64_6D */
7c52e0e8 2691 {
4e7d34a6
L		 2692 { "ins{R|}", { Yzr, indirDX } },
2693 { "ins{G|}", { Yzr, indirDX } },
7c52e0e8
L		 2694 },
2695
4e7d34a6 2696 /* X86_64_6F */
7c52e0e8 2697 {
4e7d34a6
L		 2698 { "outs{R|}", { indirDXr, Xz } },
2699 { "outs{G|}", { indirDXr, Xz } },
7c52e0e8
L		 2700 },
2701
4e7d34a6 2702 /* X86_64_9A */
7c52e0e8 2703 {
4e7d34a6 2704 { "Jcall{T|}", { Ap } },
7c52e0e8
L		 2705 { "(bad)", { XX } },
2706 },
2707
4e7d34a6 2708 /* X86_64_C4 */
7c52e0e8 2709 {
1ceb70f8 2710 { MOD_TABLE (MOD_C4_32BIT) },
4e7d34a6 2711 { "(bad)", { XX } },
7c52e0e8
L		 2712 },
2713
4e7d34a6 2714 /* X86_64_C5 */
7c52e0e8 2715 {
1ceb70f8 2716 { MOD_TABLE (MOD_C5_32BIT) },
7c52e0e8
L		 2717 { "(bad)", { XX } },
2718 },
2719
4e7d34a6 2720 /* X86_64_CE */
7c52e0e8
L		 2721 {
2722 { "into", { XX } },
2723 { "(bad)", { XX } },
2724 },
2725
4e7d34a6 2726 /* X86_64_D4 */
7c52e0e8
L		 2727 {
2728 { "aam", { sIb } },
2729 { "(bad)", { XX } },
2730 },
2731
4e7d34a6 2732 /* X86_64_D5 */
7c52e0e8
L		 2733 {
2734 { "aad", { sIb } },
2735 { "(bad)", { XX } },
2736 },
2737
4e7d34a6 2738 /* X86_64_EA */
7c52e0e8
L		 2739 {
2740 { "Jjmp{T|}", { Ap } },
2741 { "(bad)", { XX } },
2742 },
2743
4e7d34a6 2744 /* X86_64_0F01_REG_0 */
7c52e0e8
L		 2745 {
2746 { "sgdt{Q|IQ}", { M } },
2747 { "sgdt", { M } },
2748 },
2749
4e7d34a6 2750 /* X86_64_0F01_REG_1 */
7c52e0e8
L		 2751 {
2752 { "sidt{Q|IQ}", { M } },
2753 { "sidt", { M } },
2754 },
2755
4e7d34a6 2756 /* X86_64_0F01_REG_2 */
7c52e0e8
L		 2757 {
2758 { "lgdt{Q|Q}", { M } },
2759 { "lgdt", { M } },
2760 },
2761
4e7d34a6 2762 /* X86_64_0F01_REG_3 */
7c52e0e8
L		 2763 {
2764 { "lidt{Q|Q}", { M } },
2765 { "lidt", { M } },
2766 },
6439fc28
AM		 2767};
2768
96fbad73 2769static const struct dis386 three_byte_table[][256] = {
4e7d34a6 2770 /* THREE_BYTE_0F24 */
331d2d0d 2771 {
96fbad73 2772 /* 00 */
4e7d34a6
L		 2773 { "fmaddps", { { OP_DREX4, q_mode } } },
2774 { "fmaddpd", { { OP_DREX4, q_mode } } },
2775 { "fmaddss", { { OP_DREX4, w_mode } } },
2776 { "fmaddsd", { { OP_DREX4, d_mode } } },
2777 { "fmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2778 { "fmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2779 { "fmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2780 { "fmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
96fbad73 2781 /* 08 */
4e7d34a6
L		 2782 { "fmsubps", { { OP_DREX4, q_mode } } },
2783 { "fmsubpd", { { OP_DREX4, q_mode } } },
2784 { "fmsubss", { { OP_DREX4, w_mode } } },
2785 { "fmsubsd", { { OP_DREX4, d_mode } } },
2786 { "fmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2787 { "fmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2788 { "fmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2789 { "fmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
85f10a01 2790 /* 10 */
4e7d34a6
L		 2791 { "fnmaddps", { { OP_DREX4, q_mode } } },
2792 { "fnmaddpd", { { OP_DREX4, q_mode } } },
2793 { "fnmaddss", { { OP_DREX4, w_mode } } },
2794 { "fnmaddsd", { { OP_DREX4, d_mode } } },
2795 { "fnmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2796 { "fnmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2797 { "fnmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2798 { "fnmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
85f10a01 2799 /* 18 */
4e7d34a6
L		 2800 { "fnmsubps", { { OP_DREX4, q_mode } } },
2801 { "fnmsubpd", { { OP_DREX4, q_mode } } },
2802 { "fnmsubss", { { OP_DREX4, w_mode } } },
2803 { "fnmsubsd", { { OP_DREX4, d_mode } } },
2804 { "fnmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2805 { "fnmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2806 { "fnmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2807 { "fnmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
85f10a01 2808 /* 20 */
4e7d34a6
L		 2809 { "permps", { { OP_DREX4, q_mode } } },
2810 { "permpd", { { OP_DREX4, q_mode } } },
2811 { "pcmov", { { OP_DREX4, q_mode } } },
2812 { "pperm", { { OP_DREX4, q_mode } } },
2813 { "permps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2814 { "permpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2815 { "pcmov", { { OP_DREX4, DREX_OC1 + w_mode } } },
2816 { "pperm", { { OP_DREX4, DREX_OC1 + d_mode } } },
85f10a01 2817 /* 28 */
4e7d34a6
L		 2818 { "(bad)", { XX } },
2819 { "(bad)", { XX } },
2820 { "(bad)", { XX } },
2821 { "(bad)", { XX } },
2822 { "(bad)", { XX } },
2823 { "(bad)", { XX } },
2824 { "(bad)", { XX } },
2825 { "(bad)", { XX } },
85f10a01 2826 /* 30 */
4e7d34a6
L		 2827 { "(bad)", { XX } },
2828 { "(bad)", { XX } },
2829 { "(bad)", { XX } },
2830 { "(bad)", { XX } },
2831 { "(bad)", { XX } },
2832 { "(bad)", { XX } },
2833 { "(bad)", { XX } },
2834 { "(bad)", { XX } },
85f10a01 2835 /* 38 */
4e7d34a6
L		 2836 { "(bad)", { XX } },
2837 { "(bad)", { XX } },
2838 { "(bad)", { XX } },
2839 { "(bad)", { XX } },
2840 { "(bad)", { XX } },
2841 { "(bad)", { XX } },
2842 { "(bad)", { XX } },
2843 { "(bad)", { XX } },
85f10a01 2844 /* 40 */
4e7d34a6
L		 2845 { "protb", { { OP_DREX3, q_mode } } },
2846 { "protw", { { OP_DREX3, q_mode } } },
2847 { "protd", { { OP_DREX3, q_mode } } },
2848 { "protq", { { OP_DREX3, q_mode } } },
2849 { "pshlb", { { OP_DREX3, q_mode } } },
2850 { "pshlw", { { OP_DREX3, q_mode } } },
2851 { "pshld", { { OP_DREX3, q_mode } } },
2852 { "pshlq", { { OP_DREX3, q_mode } } },
85f10a01 2853 /* 48 */
4e7d34a6
L		 2854 { "pshab", { { OP_DREX3, q_mode } } },
2855 { "pshaw", { { OP_DREX3, q_mode } } },
2856 { "pshad", { { OP_DREX3, q_mode } } },
2857 { "pshaq", { { OP_DREX3, q_mode } } },
2858 { "(bad)", { XX } },
2859 { "(bad)", { XX } },
2860 { "(bad)", { XX } },
2861 { "(bad)", { XX } },
85f10a01 2862 /* 50 */
4e7d34a6
L		 2863 { "(bad)", { XX } },
2864 { "(bad)", { XX } },
2865 { "(bad)", { XX } },
2866 { "(bad)", { XX } },
2867 { "(bad)", { XX } },
2868 { "(bad)", { XX } },
2869 { "(bad)", { XX } },
2870 { "(bad)", { XX } },
85f10a01 2871 /* 58 */
4e7d34a6
L		 2872 { "(bad)", { XX } },
2873 { "(bad)", { XX } },
2874 { "(bad)", { XX } },
2875 { "(bad)", { XX } },
2876 { "(bad)", { XX } },
2877 { "(bad)", { XX } },
2878 { "(bad)", { XX } },
2879 { "(bad)", { XX } },
85f10a01 2880 /* 60 */
4e7d34a6
L		 2881 { "(bad)", { XX } },
2882 { "(bad)", { XX } },
2883 { "(bad)", { XX } },
2884 { "(bad)", { XX } },
2885 { "(bad)", { XX } },
2886 { "(bad)", { XX } },
2887 { "(bad)", { XX } },
2888 { "(bad)", { XX } },
2889 /* 68 */
2890 { "(bad)", { XX } },
2891 { "(bad)", { XX } },
2892 { "(bad)", { XX } },
2893 { "(bad)", { XX } },
2894 { "(bad)", { XX } },
2895 { "(bad)", { XX } },
2896 { "(bad)", { XX } },
2897 { "(bad)", { XX } },
85f10a01 2898 /* 70 */
4e7d34a6
L		 2899 { "(bad)", { XX } },
2900 { "(bad)", { XX } },
2901 { "(bad)", { XX } },
2902 { "(bad)", { XX } },
2903 { "(bad)", { XX } },
2904 { "(bad)", { XX } },
2905 { "(bad)", { XX } },
2906 { "(bad)", { XX } },
85f10a01 2907 /* 78 */
4e7d34a6
L		 2908 { "(bad)", { XX } },
2909 { "(bad)", { XX } },
2910 { "(bad)", { XX } },
2911 { "(bad)", { XX } },
2912 { "(bad)", { XX } },
2913 { "(bad)", { XX } },
2914 { "(bad)", { XX } },
2915 { "(bad)", { XX } },
85f10a01 2916 /* 80 */
4e7d34a6
L		 2917 { "(bad)", { XX } },
2918 { "(bad)", { XX } },
2919 { "(bad)", { XX } },
2920 { "(bad)", { XX } },
2921 { "(bad)", { XX } },
2922 { "pmacssww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2923 { "pmacsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2924 { "pmacssdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
85f10a01 2925 /* 88 */
4e7d34a6
L		 2926 { "(bad)", { XX } },
2927 { "(bad)", { XX } },
2928 { "(bad)", { XX } },
2929 { "(bad)", { XX } },
2930 { "(bad)", { XX } },
2931 { "(bad)", { XX } },
2932 { "pmacssdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2933 { "pmacssdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
85f10a01 2934 /* 90 */
4e7d34a6
L		 2935 { "(bad)", { XX } },
2936 { "(bad)", { XX } },
2937 { "(bad)", { XX } },
2938 { "(bad)", { XX } },
2939 { "(bad)", { XX } },
2940 { "pmacsww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2941 { "pmacswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2942 { "pmacsdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
85f10a01 2943 /* 98 */
4e7d34a6
L		 2944 { "(bad)", { XX } },
2945 { "(bad)", { XX } },
2946 { "(bad)", { XX } },
2947 { "(bad)", { XX } },
2948 { "(bad)", { XX } },
2949 { "(bad)", { XX } },
2950 { "pmacsdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2951 { "pmacsdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
85f10a01 2952 /* a0 */
4e7d34a6
L		 2953 { "(bad)", { XX } },
2954 { "(bad)", { XX } },
2955 { "(bad)", { XX } },
2956 { "(bad)", { XX } },
2957 { "(bad)", { XX } },
2958 { "(bad)", { XX } },
2959 { "pmadcsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2960 { "(bad)", { XX } },
85f10a01 2961 /* a8 */
4e7d34a6
L		 2962 { "(bad)", { XX } },
2963 { "(bad)", { XX } },
2964 { "(bad)", { XX } },
2965 { "(bad)", { XX } },
2966 { "(bad)", { XX } },
2967 { "(bad)", { XX } },
2968 { "(bad)", { XX } },
2969 { "(bad)", { XX } },
85f10a01 2970 /* b0 */
4e7d34a6
L		 2971 { "(bad)", { XX } },
2972 { "(bad)", { XX } },
2973 { "(bad)", { XX } },
2974 { "(bad)", { XX } },
2975 { "(bad)", { XX } },
2976 { "(bad)", { XX } },
2977 { "pmadcswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2978 { "(bad)", { XX } },
85f10a01 2979 /* b8 */
4e7d34a6
L		 2980 { "(bad)", { XX } },
2981 { "(bad)", { XX } },
2982 { "(bad)", { XX } },
2983 { "(bad)", { XX } },
2984 { "(bad)", { XX } },
2985 { "(bad)", { XX } },
2986 { "(bad)", { XX } },
2987 { "(bad)", { XX } },
85f10a01 2988 /* c0 */
4e7d34a6
L		 2989 { "(bad)", { XX } },
2990 { "(bad)", { XX } },
2991 { "(bad)", { XX } },
2992 { "(bad)", { XX } },
2993 { "(bad)", { XX } },
2994 { "(bad)", { XX } },
2995 { "(bad)", { XX } },
2996 { "(bad)", { XX } },
85f10a01 2997 /* c8 */
4e7d34a6
L		 2998 { "(bad)", { XX } },
2999 { "(bad)", { XX } },
3000 { "(bad)", { XX } },
3001 { "(bad)", { XX } },
3002 { "(bad)", { XX } },
3003 { "(bad)", { XX } },
3004 { "(bad)", { XX } },
3005 { "(bad)", { XX } },
85f10a01 3006 /* d0 */
4e7d34a6
L		 3007 { "(bad)", { XX } },
3008 { "(bad)", { XX } },
3009 { "(bad)", { XX } },
3010 { "(bad)", { XX } },
3011 { "(bad)", { XX } },
3012 { "(bad)", { XX } },
3013 { "(bad)", { XX } },
3014 { "(bad)", { XX } },
85f10a01 3015 /* d8 */
4e7d34a6
L		 3016 { "(bad)", { XX } },
3017 { "(bad)", { XX } },
3018 { "(bad)", { XX } },
3019 { "(bad)", { XX } },
3020 { "(bad)", { XX } },
3021 { "(bad)", { XX } },
3022 { "(bad)", { XX } },
3023 { "(bad)", { XX } },
85f10a01 3024 /* e0 */
4e7d34a6
L		 3025 { "(bad)", { XX } },
3026 { "(bad)", { XX } },
3027 { "(bad)", { XX } },
3028 { "(bad)", { XX } },
3029 { "(bad)", { XX } },
3030 { "(bad)", { XX } },
3031 { "(bad)", { XX } },
3032 { "(bad)", { XX } },
85f10a01 3033 /* e8 */
4e7d34a6
L		 3034 { "(bad)", { XX } },
3035 { "(bad)", { XX } },
3036 { "(bad)", { XX } },
3037 { "(bad)", { XX } },
3038 { "(bad)", { XX } },
3039 { "(bad)", { XX } },
3040 { "(bad)", { XX } },
3041 { "(bad)", { XX } },
85f10a01 3042 /* f0 */
4e7d34a6
L		 3043 { "(bad)", { XX } },
3044 { "(bad)", { XX } },
3045 { "(bad)", { XX } },
3046 { "(bad)", { XX } },
3047 { "(bad)", { XX } },
3048 { "(bad)", { XX } },
3049 { "(bad)", { XX } },
3050 { "(bad)", { XX } },
85f10a01 3051 /* f8 */
4e7d34a6
L		 3052 { "(bad)", { XX } },
3053 { "(bad)", { XX } },
3054 { "(bad)", { XX } },
3055 { "(bad)", { XX } },
3056 { "(bad)", { XX } },
3057 { "(bad)", { XX } },
3058 { "(bad)", { XX } },
3059 { "(bad)", { XX } },
85f10a01 3060 },
4e7d34a6 3061 /* THREE_BYTE_0F25 */
85f10a01
MM		 3062 {
3063 /* 00 */
4e7d34a6
L		 3064 { "(bad)", { XX } },
3065 { "(bad)", { XX } },
3066 { "(bad)", { XX } },
3067 { "(bad)", { XX } },
3068 { "(bad)", { XX } },
3069 { "(bad)", { XX } },
3070 { "(bad)", { XX } },
3071 { "(bad)", { XX } },
85f10a01 3072 /* 08 */
4e7d34a6
L		 3073 { "(bad)", { XX } },
3074 { "(bad)", { XX } },
3075 { "(bad)", { XX } },
3076 { "(bad)", { XX } },
3077 { "(bad)", { XX } },
3078 { "(bad)", { XX } },
3079 { "(bad)", { XX } },
3080 { "(bad)", { XX } },
85f10a01 3081 /* 10 */
4e7d34a6
L		 3082 { "(bad)", { XX } },
3083 { "(bad)", { XX } },
3084 { "(bad)", { XX } },
3085 { "(bad)", { XX } },
3086 { "(bad)", { XX } },
3087 { "(bad)", { XX } },
3088 { "(bad)", { XX } },
3089 { "(bad)", { XX } },
85f10a01 3090 /* 18 */
4e7d34a6
L		 3091 { "(bad)", { XX } },
3092 { "(bad)", { XX } },
3093 { "(bad)", { XX } },
3094 { "(bad)", { XX } },
3095 { "(bad)", { XX } },
3096 { "(bad)", { XX } },
3097 { "(bad)", { XX } },
3098 { "(bad)", { XX } },
85f10a01 3099 /* 20 */
4e7d34a6
L		 3100 { "(bad)", { XX } },
3101 { "(bad)", { XX } },
3102 { "(bad)", { XX } },
3103 { "(bad)", { XX } },
3104 { "(bad)", { XX } },
3105 { "(bad)", { XX } },
3106 { "(bad)", { XX } },
3107 { "(bad)", { XX } },
85f10a01 3108 /* 28 */
4e7d34a6
L		 3109 { "(bad)", { XX } },
3110 { "(bad)", { XX } },
3111 { "(bad)", { XX } },
3112 { "(bad)", { XX } },
3113 { "comps", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
3114 { "compd", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
3115 { "comss", { { OP_DREX3, w_mode }, { OP_DREX_FCMP, b_mode } } },
3116 { "comsd", { { OP_DREX3, d_mode }, { OP_DREX_FCMP, b_mode } } },
85f10a01 3117 /* 30 */
4e7d34a6
L		 3118 { "(bad)", { XX } },
3119 { "(bad)", { XX } },
3120 { "(bad)", { XX } },
3121 { "(bad)", { XX } },
3122 { "(bad)", { XX } },
3123 { "(bad)", { XX } },
3124 { "(bad)", { XX } },
3125 { "(bad)", { XX } },
85f10a01 3126 /* 38 */
4e7d34a6
L		 3127 { "(bad)", { XX } },
3128 { "(bad)", { XX } },
3129 { "(bad)", { XX } },
3130 { "(bad)", { XX } },
3131 { "(bad)", { XX } },
3132 { "(bad)", { XX } },
3133 { "(bad)", { XX } },
3134 { "(bad)", { XX } },
85f10a01 3135 /* 40 */
4e7d34a6
L		 3136 { "(bad)", { XX } },
3137 { "(bad)", { XX } },
3138 { "(bad)", { XX } },
3139 { "(bad)", { XX } },
3140 { "(bad)", { XX } },
3141 { "(bad)", { XX } },
3142 { "(bad)", { XX } },
3143 { "(bad)", { XX } },
85f10a01 3144 /* 48 */
4e7d34a6
L		 3145 { "(bad)", { XX } },
3146 { "(bad)", { XX } },
3147 { "(bad)", { XX } },
3148 { "(bad)", { XX } },
3149 { "pcomb", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3150 { "pcomw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3151 { "pcomd", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3152 { "pcomq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
85f10a01 3153 /* 50 */
4e7d34a6
L		 3154 { "(bad)", { XX } },
3155 { "(bad)", { XX } },
3156 { "(bad)", { XX } },
3157 { "(bad)", { XX } },
3158 { "(bad)", { XX } },
3159 { "(bad)", { XX } },
3160 { "(bad)", { XX } },
3161 { "(bad)", { XX } },
85f10a01 3162 /* 58 */
4e7d34a6
L		 3163 { "(bad)", { XX } },
3164 { "(bad)", { XX } },
3165 { "(bad)", { XX } },
3166 { "(bad)", { XX } },
3167 { "(bad)", { XX } },
3168 { "(bad)", { XX } },
3169 { "(bad)", { XX } },
3170 { "(bad)", { XX } },
85f10a01 3171 /* 60 */
4e7d34a6
L		 3172 { "(bad)", { XX } },
3173 { "(bad)", { XX } },
3174 { "(bad)", { XX } },
3175 { "(bad)", { XX } },
3176 { "(bad)", { XX } },
3177 { "(bad)", { XX } },
3178 { "(bad)", { XX } },
3179 { "(bad)", { XX } },
85f10a01 3180 /* 68 */
4e7d34a6
L		 3181 { "(bad)", { XX } },
3182 { "(bad)", { XX } },
3183 { "(bad)", { XX } },
3184 { "(bad)", { XX } },
3185 { "pcomub", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3186 { "pcomuw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3187 { "pcomud", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3188 { "pcomuq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
85f10a01 3189 /* 70 */
4e7d34a6
L		 3190 { "(bad)", { XX } },
3191 { "(bad)", { XX } },
3192 { "(bad)", { XX } },
3193 { "(bad)", { XX } },
3194 { "(bad)", { XX } },
3195 { "(bad)", { XX } },
3196 { "(bad)", { XX } },
3197 { "(bad)", { XX } },
85f10a01 3198 /* 78 */
4e7d34a6
L		 3199 { "(bad)", { XX } },
3200 { "(bad)", { XX } },
3201 { "(bad)", { XX } },
3202 { "(bad)", { XX } },
3203 { "(bad)", { XX } },
3204 { "(bad)", { XX } },
3205 { "(bad)", { XX } },
3206 { "(bad)", { XX } },
85f10a01 3207 /* 80 */
4e7d34a6
L		 3208 { "(bad)", { XX } },
3209 { "(bad)", { XX } },
3210 { "(bad)", { XX } },
3211 { "(bad)", { XX } },
3212 { "(bad)", { XX } },
3213 { "(bad)", { XX } },
3214 { "(bad)", { XX } },
3215 { "(bad)", { XX } },
3216 /* 88 */
3217 { "(bad)", { XX } },
3218 { "(bad)", { XX } },
3219 { "(bad)", { XX } },
3220 { "(bad)", { XX } },
3221 { "(bad)", { XX } },
3222 { "(bad)", { XX } },
3223 { "(bad)", { XX } },
3224 { "(bad)", { XX } },
3225 /* 90 */
3226 { "(bad)", { XX } },
3227 { "(bad)", { XX } },
3228 { "(bad)", { XX } },
3229 { "(bad)", { XX } },
3230 { "(bad)", { XX } },
3231 { "(bad)", { XX } },
3232 { "(bad)", { XX } },
3233 { "(bad)", { XX } },
3234 /* 98 */
3235 { "(bad)", { XX } },
3236 { "(bad)", { XX } },
3237 { "(bad)", { XX } },
3238 { "(bad)", { XX } },
3239 { "(bad)", { XX } },
3240 { "(bad)", { XX } },
3241 { "(bad)", { XX } },
3242 { "(bad)", { XX } },
3243 /* a0 */
3244 { "(bad)", { XX } },
3245 { "(bad)", { XX } },
3246 { "(bad)", { XX } },
3247 { "(bad)", { XX } },
3248 { "(bad)", { XX } },
3249 { "(bad)", { XX } },
3250 { "(bad)", { XX } },
3251 { "(bad)", { XX } },
3252 /* a8 */
3253 { "(bad)", { XX } },
3254 { "(bad)", { XX } },
3255 { "(bad)", { XX } },
3256 { "(bad)", { XX } },
3257 { "(bad)", { XX } },
3258 { "(bad)", { XX } },
3259 { "(bad)", { XX } },
3260 { "(bad)", { XX } },
3261 /* b0 */
3262 { "(bad)", { XX } },
3263 { "(bad)", { XX } },
3264 { "(bad)", { XX } },
3265 { "(bad)", { XX } },
3266 { "(bad)", { XX } },
3267 { "(bad)", { XX } },
3268 { "(bad)", { XX } },
3269 { "(bad)", { XX } },
3270 /* b8 */
3271 { "(bad)", { XX } },
3272 { "(bad)", { XX } },
3273 { "(bad)", { XX } },
3274 { "(bad)", { XX } },
3275 { "(bad)", { XX } },
3276 { "(bad)", { XX } },
3277 { "(bad)", { XX } },
3278 { "(bad)", { XX } },
3279 /* c0 */
3280 { "(bad)", { XX } },
3281 { "(bad)", { XX } },
3282 { "(bad)", { XX } },
3283 { "(bad)", { XX } },
3284 { "(bad)", { XX } },
3285 { "(bad)", { XX } },
3286 { "(bad)", { XX } },
3287 { "(bad)", { XX } },
3288 /* c8 */
3289 { "(bad)", { XX } },
3290 { "(bad)", { XX } },
3291 { "(bad)", { XX } },
3292 { "(bad)", { XX } },
3293 { "(bad)", { XX } },
3294 { "(bad)", { XX } },
3295 { "(bad)", { XX } },
3296 { "(bad)", { XX } },
3297 /* d0 */
3298 { "(bad)", { XX } },
3299 { "(bad)", { XX } },
3300 { "(bad)", { XX } },
3301 { "(bad)", { XX } },
3302 { "(bad)", { XX } },
3303 { "(bad)", { XX } },
3304 { "(bad)", { XX } },
3305 { "(bad)", { XX } },
3306 /* d8 */
3307 { "(bad)", { XX } },
3308 { "(bad)", { XX } },
3309 { "(bad)", { XX } },
3310 { "(bad)", { XX } },
3311 { "(bad)", { XX } },
3312 { "(bad)", { XX } },
3313 { "(bad)", { XX } },
3314 { "(bad)", { XX } },
3315 /* e0 */
3316 { "(bad)", { XX } },
3317 { "(bad)", { XX } },
3318 { "(bad)", { XX } },
3319 { "(bad)", { XX } },
3320 { "(bad)", { XX } },
3321 { "(bad)", { XX } },
3322 { "(bad)", { XX } },
3323 { "(bad)", { XX } },
3324 /* e8 */
3325 { "(bad)", { XX } },
3326 { "(bad)", { XX } },
3327 { "(bad)", { XX } },
3328 { "(bad)", { XX } },
3329 { "(bad)", { XX } },
3330 { "(bad)", { XX } },
3331 { "(bad)", { XX } },
3332 { "(bad)", { XX } },
3333 /* f0 */
3334 { "(bad)", { XX } },
3335 { "(bad)", { XX } },
3336 { "(bad)", { XX } },
3337 { "(bad)", { XX } },
3338 { "(bad)", { XX } },
3339 { "(bad)", { XX } },
3340 { "(bad)", { XX } },
3341 { "(bad)", { XX } },
3342 /* f8 */
3343 { "(bad)", { XX } },
3344 { "(bad)", { XX } },
3345 { "(bad)", { XX } },
3346 { "(bad)", { XX } },
3347 { "(bad)", { XX } },
3348 { "(bad)", { XX } },
3349 { "(bad)", { XX } },
3350 { "(bad)", { XX } },
3351 },
3352 /* THREE_BYTE_0F38 */
3353 {
3354 /* 00 */
d5d7db8e
L		 3355 { "pshufb", { MX, EM } },
3356 { "phaddw", { MX, EM } },
3357 { "phaddd", { MX, EM } },
3358 { "phaddsw", { MX, EM } },
3359 { "pmaddubsw", { MX, EM } },
3360 { "phsubw", { MX, EM } },
3361 { "phsubd", { MX, EM } },
3362 { "phsubsw", { MX, EM } },
4e7d34a6 3363 /* 08 */
d5d7db8e
L		 3364 { "psignb", { MX, EM } },
3365 { "psignw", { MX, EM } },
3366 { "psignd", { MX, EM } },
3367 { "pmulhrsw", { MX, EM } },
3368 { "(bad)", { XX } },
3369 { "(bad)", { XX } },
3370 { "(bad)", { XX } },
3371 { "(bad)", { XX } },
4e7d34a6 3372 /* 10 */
1ceb70f8 3373 { PREFIX_TABLE (PREFIX_0F3810) },
d5d7db8e
L		 3374 { "(bad)", { XX } },
3375 { "(bad)", { XX } },
3376 { "(bad)", { XX } },
1ceb70f8
L		 3377 { PREFIX_TABLE (PREFIX_0F3814) },
3378 { PREFIX_TABLE (PREFIX_0F3815) },
d5d7db8e 3379 { "(bad)", { XX } },
1ceb70f8 3380 { PREFIX_TABLE (PREFIX_0F3817) },
4e7d34a6 3381 /* 18 */
d5d7db8e
L		 3382 { "(bad)", { XX } },
3383 { "(bad)", { XX } },
3384 { "(bad)", { XX } },
3385 { "(bad)", { XX } },
3386 { "pabsb", { MX, EM } },
3387 { "pabsw", { MX, EM } },
3388 { "pabsd", { MX, EM } },
3389 { "(bad)", { XX } },
4e7d34a6 3390 /* 20 */
1ceb70f8
L		 3391 { PREFIX_TABLE (PREFIX_0F3820) },
3392 { PREFIX_TABLE (PREFIX_0F3821) },
3393 { PREFIX_TABLE (PREFIX_0F3822) },
3394 { PREFIX_TABLE (PREFIX_0F3823) },
3395 { PREFIX_TABLE (PREFIX_0F3824) },
3396 { PREFIX_TABLE (PREFIX_0F3825) },
d5d7db8e
L		 3397 { "(bad)", { XX } },
3398 { "(bad)", { XX } },
4e7d34a6 3399 /* 28 */
1ceb70f8
L		 3400 { PREFIX_TABLE (PREFIX_0F3828) },
3401 { PREFIX_TABLE (PREFIX_0F3829) },
3402 { PREFIX_TABLE (PREFIX_0F382A) },
3403 { PREFIX_TABLE (PREFIX_0F382B) },
d5d7db8e
L		 3404 { "(bad)", { XX } },
3405 { "(bad)", { XX } },
3406 { "(bad)", { XX } },
3407 { "(bad)", { XX } },
4e7d34a6 3408 /* 30 */
1ceb70f8
L		 3409 { PREFIX_TABLE (PREFIX_0F3830) },
3410 { PREFIX_TABLE (PREFIX_0F3831) },
3411 { PREFIX_TABLE (PREFIX_0F3832) },
3412 { PREFIX_TABLE (PREFIX_0F3833) },
3413 { PREFIX_TABLE (PREFIX_0F3834) },
3414 { PREFIX_TABLE (PREFIX_0F3835) },
d5d7db8e 3415 { "(bad)", { XX } },
1ceb70f8 3416 { PREFIX_TABLE (PREFIX_0F3837) },
4e7d34a6 3417 /* 38 */
1ceb70f8
L		 3418 { PREFIX_TABLE (PREFIX_0F3838) },
3419 { PREFIX_TABLE (PREFIX_0F3839) },
3420 { PREFIX_TABLE (PREFIX_0F383A) },
3421 { PREFIX_TABLE (PREFIX_0F383B) },
3422 { PREFIX_TABLE (PREFIX_0F383C) },
3423 { PREFIX_TABLE (PREFIX_0F383D) },
3424 { PREFIX_TABLE (PREFIX_0F383E) },
3425 { PREFIX_TABLE (PREFIX_0F383F) },
4e7d34a6 3426 /* 40 */
1ceb70f8
L		 3427 { PREFIX_TABLE (PREFIX_0F3840) },
3428 { PREFIX_TABLE (PREFIX_0F3841) },
d5d7db8e
L		 3429 { "(bad)", { XX } },
3430 { "(bad)", { XX } },
3431 { "(bad)", { XX } },
3432 { "(bad)", { XX } },
3433 { "(bad)", { XX } },
3434 { "(bad)", { XX } },
4e7d34a6 3435 /* 48 */
d5d7db8e
L		 3436 { "(bad)", { XX } },
3437 { "(bad)", { XX } },
3438 { "(bad)", { XX } },
3439 { "(bad)", { XX } },
3440 { "(bad)", { XX } },
3441 { "(bad)", { XX } },
3442 { "(bad)", { XX } },
3443 { "(bad)", { XX } },
4e7d34a6 3444 /* 50 */
d5d7db8e
L		 3445 { "(bad)", { XX } },
3446 { "(bad)", { XX } },
3447 { "(bad)", { XX } },
3448 { "(bad)", { XX } },
3449 { "(bad)", { XX } },
3450 { "(bad)", { XX } },
3451 { "(bad)", { XX } },
3452 { "(bad)", { XX } },
4e7d34a6 3453 /* 58 */
d5d7db8e
L		 3454 { "(bad)", { XX } },
3455 { "(bad)", { XX } },
3456 { "(bad)", { XX } },
3457 { "(bad)", { XX } },
3458 { "(bad)", { XX } },
3459 { "(bad)", { XX } },
3460 { "(bad)", { XX } },
3461 { "(bad)", { XX } },
4e7d34a6 3462 /* 60 */
d5d7db8e
L		 3463 { "(bad)", { XX } },
3464 { "(bad)", { XX } },
3465 { "(bad)", { XX } },
3466 { "(bad)", { XX } },
3467 { "(bad)", { XX } },
3468 { "(bad)", { XX } },
3469 { "(bad)", { XX } },
3470 { "(bad)", { XX } },
4e7d34a6 3471 /* 68 */
d5d7db8e
L		 3472 { "(bad)", { XX } },
3473 { "(bad)", { XX } },
3474 { "(bad)", { XX } },
3475 { "(bad)", { XX } },
3476 { "(bad)", { XX } },
3477 { "(bad)", { XX } },
3478 { "(bad)", { XX } },
3479 { "(bad)", { XX } },
4e7d34a6 3480 /* 70 */
d5d7db8e
L		 3481 { "(bad)", { XX } },
3482 { "(bad)", { XX } },
3483 { "(bad)", { XX } },
3484 { "(bad)", { XX } },
3485 { "(bad)", { XX } },
3486 { "(bad)", { XX } },
3487 { "(bad)", { XX } },
3488 { "(bad)", { XX } },
4e7d34a6 3489 /* 78 */
d5d7db8e
L		 3490 { "(bad)", { XX } },
3491 { "(bad)", { XX } },
3492 { "(bad)", { XX } },
3493 { "(bad)", { XX } },
3494 { "(bad)", { XX } },
3495 { "(bad)", { XX } },
3496 { "(bad)", { XX } },
3497 { "(bad)", { XX } },
4e7d34a6 3498 /* 80 */
d5d7db8e
L		 3499 { "(bad)", { XX } },
3500 { "(bad)", { XX } },
3501 { "(bad)", { XX } },
3502 { "(bad)", { XX } },
3503 { "(bad)", { XX } },
3504 { "(bad)", { XX } },
3505 { "(bad)", { XX } },
3506 { "(bad)", { XX } },
4e7d34a6 3507 /* 88 */
d5d7db8e
L		 3508 { "(bad)", { XX } },
3509 { "(bad)", { XX } },
3510 { "(bad)", { XX } },
3511 { "(bad)", { XX } },
3512 { "(bad)", { XX } },
3513 { "(bad)", { XX } },
3514 { "(bad)", { XX } },
3515 { "(bad)", { XX } },
4e7d34a6 3516 /* 90 */
d5d7db8e
L		 3517 { "(bad)", { XX } },
3518 { "(bad)", { XX } },
3519 { "(bad)", { XX } },
3520 { "(bad)", { XX } },
3521 { "(bad)", { XX } },
3522 { "(bad)", { XX } },
3523 { "(bad)", { XX } },
3524 { "(bad)", { XX } },
4e7d34a6 3525 /* 98 */
d5d7db8e
L		 3526 { "(bad)", { XX } },
3527 { "(bad)", { XX } },
3528 { "(bad)", { XX } },
3529 { "(bad)", { XX } },
3530 { "(bad)", { XX } },
3531 { "(bad)", { XX } },
3532 { "(bad)", { XX } },
3533 { "(bad)", { XX } },
4e7d34a6 3534 /* a0 */
d5d7db8e
L		 3535 { "(bad)", { XX } },
3536 { "(bad)", { XX } },
3537 { "(bad)", { XX } },
3538 { "(bad)", { XX } },
3539 { "(bad)", { XX } },
3540 { "(bad)", { XX } },
3541 { "(bad)", { XX } },
3542 { "(bad)", { XX } },
4e7d34a6 3543 /* a8 */
d5d7db8e
L		 3544 { "(bad)", { XX } },
3545 { "(bad)", { XX } },
3546 { "(bad)", { XX } },
3547 { "(bad)", { XX } },
3548 { "(bad)", { XX } },
3549 { "(bad)", { XX } },
3550 { "(bad)", { XX } },
3551 { "(bad)", { XX } },
3552 /* b0 */
3553 { "(bad)", { XX } },
3554 { "(bad)", { XX } },
3555 { "(bad)", { XX } },
3556 { "(bad)", { XX } },
3557 { "(bad)", { XX } },
3558 { "(bad)", { XX } },
3559 { "(bad)", { XX } },
3560 { "(bad)", { XX } },
85f10a01 3561 /* b8 */
d5d7db8e
L		 3562 { "(bad)", { XX } },
3563 { "(bad)", { XX } },
3564 { "(bad)", { XX } },
3565 { "(bad)", { XX } },
3566 { "(bad)", { XX } },
3567 { "(bad)", { XX } },
3568 { "(bad)", { XX } },
3569 { "(bad)", { XX } },
85f10a01 3570 /* c0 */
d5d7db8e
L		 3571 { "(bad)", { XX } },
3572 { "(bad)", { XX } },
3573 { "(bad)", { XX } },
3574 { "(bad)", { XX } },
3575 { "(bad)", { XX } },
3576 { "(bad)", { XX } },
3577 { "(bad)", { XX } },
3578 { "(bad)", { XX } },
85f10a01 3579 /* c8 */
d5d7db8e
L		 3580 { "(bad)", { XX } },
3581 { "(bad)", { XX } },
3582 { "(bad)", { XX } },
3583 { "(bad)", { XX } },
3584 { "(bad)", { XX } },
3585 { "(bad)", { XX } },
3586 { "(bad)", { XX } },
3587 { "(bad)", { XX } },
85f10a01 3588 /* d0 */
d5d7db8e
L		 3589 { "(bad)", { XX } },
3590 { "(bad)", { XX } },
3591 { "(bad)", { XX } },
3592 { "(bad)", { XX } },
3593 { "(bad)", { XX } },
3594 { "(bad)", { XX } },
3595 { "(bad)", { XX } },
3596 { "(bad)", { XX } },
85f10a01 3597 /* d8 */
d5d7db8e
L		 3598 { "(bad)", { XX } },
3599 { "(bad)", { XX } },
3600 { "(bad)", { XX } },
3601 { "(bad)", { XX } },
3602 { "(bad)", { XX } },
3603 { "(bad)", { XX } },
3604 { "(bad)", { XX } },
3605 { "(bad)", { XX } },
85f10a01 3606 /* e0 */
d5d7db8e
L		 3607 { "(bad)", { XX } },
3608 { "(bad)", { XX } },
3609 { "(bad)", { XX } },
3610 { "(bad)", { XX } },
3611 { "(bad)", { XX } },
3612 { "(bad)", { XX } },
3613 { "(bad)", { XX } },
3614 { "(bad)", { XX } },
85f10a01 3615 /* e8 */
d5d7db8e
L		 3616 { "(bad)", { XX } },
3617 { "(bad)", { XX } },
3618 { "(bad)", { XX } },
3619 { "(bad)", { XX } },
3620 { "(bad)", { XX } },
3621 { "(bad)", { XX } },
3622 { "(bad)", { XX } },
3623 { "(bad)", { XX } },
85f10a01 3624 /* f0 */
1ceb70f8
L		 3625 { PREFIX_TABLE (PREFIX_0F38F0) },
3626 { PREFIX_TABLE (PREFIX_0F38F1) },
d5d7db8e
L		 3627 { "(bad)", { XX } },
3628 { "(bad)", { XX } },
3629 { "(bad)", { XX } },
3630 { "(bad)", { XX } },
3631 { "(bad)", { XX } },
3632 { "(bad)", { XX } },
85f10a01 3633 /* f8 */
d5d7db8e
L		 3634 { "(bad)", { XX } },
3635 { "(bad)", { XX } },
3636 { "(bad)", { XX } },
3637 { "(bad)", { XX } },
3638 { "(bad)", { XX } },
3639 { "(bad)", { XX } },
3640 { "(bad)", { XX } },
3641 { "(bad)", { XX } },
85f10a01 3642 },
4e7d34a6 3643 /* THREE_BYTE_0F3A */
85f10a01
MM		 3644 {
3645 /* 00 */
d5d7db8e
L		 3646 { "(bad)", { XX } },
3647 { "(bad)", { XX } },
3648 { "(bad)", { XX } },
3649 { "(bad)", { XX } },
3650 { "(bad)", { XX } },
3651 { "(bad)", { XX } },
3652 { "(bad)", { XX } },
3653 { "(bad)", { XX } },
85f10a01 3654 /* 08 */
1ceb70f8
L		 3655 { PREFIX_TABLE (PREFIX_0F3A08) },
3656 { PREFIX_TABLE (PREFIX_0F3A09) },
3657 { PREFIX_TABLE (PREFIX_0F3A0A) },
3658 { PREFIX_TABLE (PREFIX_0F3A0B) },
3659 { PREFIX_TABLE (PREFIX_0F3A0C) },
3660 { PREFIX_TABLE (PREFIX_0F3A0D) },
3661 { PREFIX_TABLE (PREFIX_0F3A0E) },
d5d7db8e 3662 { "palignr", { MX, EM, Ib } },
85f10a01 3663 /* 10 */
d5d7db8e
L		 3664 { "(bad)", { XX } },
3665 { "(bad)", { XX } },
3666 { "(bad)", { XX } },
3667 { "(bad)", { XX } },
1ceb70f8
L		 3668 { PREFIX_TABLE (PREFIX_0F3A14) },
3669 { PREFIX_TABLE (PREFIX_0F3A15) },
3670 { PREFIX_TABLE (PREFIX_0F3A16) },
3671 { PREFIX_TABLE (PREFIX_0F3A17) },
85f10a01 3672 /* 18 */
d5d7db8e
L		 3673 { "(bad)", { XX } },
3674 { "(bad)", { XX } },
3675 { "(bad)", { XX } },
3676 { "(bad)", { XX } },
3677 { "(bad)", { XX } },
3678 { "(bad)", { XX } },
3679 { "(bad)", { XX } },
3680 { "(bad)", { XX } },
85f10a01 3681 /* 20 */
1ceb70f8
L		 3682 { PREFIX_TABLE (PREFIX_0F3A20) },
3683 { PREFIX_TABLE (PREFIX_0F3A21) },
3684 { PREFIX_TABLE (PREFIX_0F3A22) },
d5d7db8e
L		 3685 { "(bad)", { XX } },
3686 { "(bad)", { XX } },
3687 { "(bad)", { XX } },
3688 { "(bad)", { XX } },
3689 { "(bad)", { XX } },
85f10a01 3690 /* 28 */
d5d7db8e
L		 3691 { "(bad)", { XX } },
3692 { "(bad)", { XX } },
3693 { "(bad)", { XX } },
3694 { "(bad)", { XX } },
3695 { "(bad)", { XX } },
3696 { "(bad)", { XX } },
3697 { "(bad)", { XX } },
3698 { "(bad)", { XX } },
85f10a01 3699 /* 30 */
d5d7db8e
L		 3700 { "(bad)", { XX } },
3701 { "(bad)", { XX } },
3702 { "(bad)", { XX } },
3703 { "(bad)", { XX } },
3704 { "(bad)", { XX } },
3705 { "(bad)", { XX } },
3706 { "(bad)", { XX } },
3707 { "(bad)", { XX } },
4e7d34a6 3708 /* 38 */
d5d7db8e
L		 3709 { "(bad)", { XX } },
3710 { "(bad)", { XX } },
3711 { "(bad)", { XX } },
3712 { "(bad)", { XX } },
3713 { "(bad)", { XX } },
3714 { "(bad)", { XX } },
3715 { "(bad)", { XX } },
3716 { "(bad)", { XX } },
3717 /* 40 */
3718 { PREFIX_TABLE (PREFIX_0F3A40) },
3719 { PREFIX_TABLE (PREFIX_0F3A41) },
3720 { PREFIX_TABLE (PREFIX_0F3A42) },
3721 { "(bad)", { XX } },
3722 { "(bad)", { XX } },
3723 { "(bad)", { XX } },
3724 { "(bad)", { XX } },
3725 { "(bad)", { XX } },
85f10a01 3726 /* 48 */
85f10a01
MM		 3727 { "(bad)", { XX } },
3728 { "(bad)", { XX } },
3729 { "(bad)", { XX } },
3730 { "(bad)", { XX } },
3731 { "(bad)", { XX } },
3732 { "(bad)", { XX } },
3733 { "(bad)", { XX } },
3734 { "(bad)", { XX } },
d5d7db8e 3735 /* 50 */
85f10a01
MM		 3736 { "(bad)", { XX } },
3737 { "(bad)", { XX } },
3738 { "(bad)", { XX } },
3739 { "(bad)", { XX } },
3740 { "(bad)", { XX } },
3741 { "(bad)", { XX } },
3742 { "(bad)", { XX } },
3743 { "(bad)", { XX } },
d5d7db8e 3744 /* 58 */
85f10a01
MM		 3745 { "(bad)", { XX } },
3746 { "(bad)", { XX } },
3747 { "(bad)", { XX } },
3748 { "(bad)", { XX } },
85f10a01
MM		 3749 { "(bad)", { XX } },
3750 { "(bad)", { XX } },
3751 { "(bad)", { XX } },
3752 { "(bad)", { XX } },
d5d7db8e
L		 3753 /* 60 */
3754 { PREFIX_TABLE (PREFIX_0F3A60) },
3755 { PREFIX_TABLE (PREFIX_0F3A61) },
3756 { PREFIX_TABLE (PREFIX_0F3A62) },
3757 { PREFIX_TABLE (PREFIX_0F3A63) },
85f10a01
MM		 3758 { "(bad)", { XX } },
3759 { "(bad)", { XX } },
3760 { "(bad)", { XX } },
3761 { "(bad)", { XX } },
d5d7db8e 3762 /* 68 */
85f10a01
MM		 3763 { "(bad)", { XX } },
3764 { "(bad)", { XX } },
3765 { "(bad)", { XX } },
3766 { "(bad)", { XX } },
3767 { "(bad)", { XX } },
3768 { "(bad)", { XX } },
3769 { "(bad)", { XX } },
85f10a01 3770 { "(bad)", { XX } },
d5d7db8e 3771 /* 70 */
85f10a01
MM		 3772 { "(bad)", { XX } },
3773 { "(bad)", { XX } },
3774 { "(bad)", { XX } },
d5d7db8e
L		 3775 { "(bad)", { XX } },
3776 { "(bad)", { XX } },
3777 { "(bad)", { XX } },
3778 { "(bad)", { XX } },
3779 { "(bad)", { XX } },
3780 /* 78 */
3781 { "(bad)", { XX } },
3782 { "(bad)", { XX } },
3783 { "(bad)", { XX } },
3784 { "(bad)", { XX } },
3785 { "(bad)", { XX } },
3786 { "(bad)", { XX } },
3787 { "(bad)", { XX } },
3788 { "(bad)", { XX } },
3789 /* 80 */
3790 { "(bad)", { XX } },
3791 { "(bad)", { XX } },
3792 { "(bad)", { XX } },
3793 { "(bad)", { XX } },
3794 { "(bad)", { XX } },
3795 { "(bad)", { XX } },
3796 { "(bad)", { XX } },
3797 { "(bad)", { XX } },
3798 /* 88 */
3799 { "(bad)", { XX } },
3800 { "(bad)", { XX } },
3801 { "(bad)", { XX } },
3802 { "(bad)", { XX } },
3803 { "(bad)", { XX } },
3804 { "(bad)", { XX } },
3805 { "(bad)", { XX } },
3806 { "(bad)", { XX } },
3807 /* 90 */
3808 { "(bad)", { XX } },
3809 { "(bad)", { XX } },
3810 { "(bad)", { XX } },
3811 { "(bad)", { XX } },
3812 { "(bad)", { XX } },
3813 { "(bad)", { XX } },
3814 { "(bad)", { XX } },
3815 { "(bad)", { XX } },
3816 /* 98 */
3817 { "(bad)", { XX } },
3818 { "(bad)", { XX } },
3819 { "(bad)", { XX } },
3820 { "(bad)", { XX } },
3821 { "(bad)", { XX } },
3822 { "(bad)", { XX } },
3823 { "(bad)", { XX } },
3824 { "(bad)", { XX } },
3825 /* a0 */
3826 { "(bad)", { XX } },
3827 { "(bad)", { XX } },
3828 { "(bad)", { XX } },
3829 { "(bad)", { XX } },
3830 { "(bad)", { XX } },
3831 { "(bad)", { XX } },
3832 { "(bad)", { XX } },
3833 { "(bad)", { XX } },
3834 /* a8 */
3835 { "(bad)", { XX } },
3836 { "(bad)", { XX } },
3837 { "(bad)", { XX } },
3838 { "(bad)", { XX } },
3839 { "(bad)", { XX } },
3840 { "(bad)", { XX } },
3841 { "(bad)", { XX } },
3842 { "(bad)", { XX } },
3843 /* b0 */
3844 { "(bad)", { XX } },
3845 { "(bad)", { XX } },
3846 { "(bad)", { XX } },
3847 { "(bad)", { XX } },
3848 { "(bad)", { XX } },
3849 { "(bad)", { XX } },
3850 { "(bad)", { XX } },
3851 { "(bad)", { XX } },
3852 /* b8 */
3853 { "(bad)", { XX } },
3854 { "(bad)", { XX } },
3855 { "(bad)", { XX } },
3856 { "(bad)", { XX } },
3857 { "(bad)", { XX } },
3858 { "(bad)", { XX } },
3859 { "(bad)", { XX } },
3860 { "(bad)", { XX } },
3861 /* c0 */
3862 { "(bad)", { XX } },
3863 { "(bad)", { XX } },
3864 { "(bad)", { XX } },
3865 { "(bad)", { XX } },
3866 { "(bad)", { XX } },
3867 { "(bad)", { XX } },
3868 { "(bad)", { XX } },
3869 { "(bad)", { XX } },
3870 /* c8 */
3871 { "(bad)", { XX } },
3872 { "(bad)", { XX } },
3873 { "(bad)", { XX } },
3874 { "(bad)", { XX } },
3875 { "(bad)", { XX } },
3876 { "(bad)", { XX } },
3877 { "(bad)", { XX } },
3878 { "(bad)", { XX } },
3879 /* d0 */
3880 { "(bad)", { XX } },
3881 { "(bad)", { XX } },
3882 { "(bad)", { XX } },
3883 { "(bad)", { XX } },
3884 { "(bad)", { XX } },
3885 { "(bad)", { XX } },
3886 { "(bad)", { XX } },
3887 { "(bad)", { XX } },
3888 /* d8 */
3889 { "(bad)", { XX } },
3890 { "(bad)", { XX } },
3891 { "(bad)", { XX } },
3892 { "(bad)", { XX } },
3893 { "(bad)", { XX } },
3894 { "(bad)", { XX } },
3895 { "(bad)", { XX } },
3896 { "(bad)", { XX } },
3897 /* e0 */
3898 { "(bad)", { XX } },
3899 { "(bad)", { XX } },
3900 { "(bad)", { XX } },
3901 { "(bad)", { XX } },
3902 { "(bad)", { XX } },
3903 { "(bad)", { XX } },
3904 { "(bad)", { XX } },
3905 { "(bad)", { XX } },
3906 /* e8 */
3907 { "(bad)", { XX } },
3908 { "(bad)", { XX } },
3909 { "(bad)", { XX } },
3910 { "(bad)", { XX } },
3911 { "(bad)", { XX } },
3912 { "(bad)", { XX } },
3913 { "(bad)", { XX } },
3914 { "(bad)", { XX } },
3915 /* f0 */
3916 { "(bad)", { XX } },
3917 { "(bad)", { XX } },
3918 { "(bad)", { XX } },
3919 { "(bad)", { XX } },
3920 { "(bad)", { XX } },
3921 { "(bad)", { XX } },
3922 { "(bad)", { XX } },
3923 { "(bad)", { XX } },
3924 /* f8 */
3925 { "(bad)", { XX } },
3926 { "(bad)", { XX } },
3927 { "(bad)", { XX } },
3928 { "(bad)", { XX } },
3929 { "(bad)", { XX } },
3930 { "(bad)", { XX } },
3931 { "(bad)", { XX } },
3932 { "(bad)", { XX } },
3933 },
3934 /* THREE_BYTE_0F7A */
3935 {
3936 /* 00 */
3937 { "(bad)", { XX } },
3938 { "(bad)", { XX } },
3939 { "(bad)", { XX } },
3940 { "(bad)", { XX } },
3941 { "(bad)", { XX } },
3942 { "(bad)", { XX } },
3943 { "(bad)", { XX } },
3944 { "(bad)", { XX } },
3945 /* 08 */
3946 { "(bad)", { XX } },
3947 { "(bad)", { XX } },
3948 { "(bad)", { XX } },
3949 { "(bad)", { XX } },
3950 { "(bad)", { XX } },
3951 { "(bad)", { XX } },
3952 { "(bad)", { XX } },
3953 { "(bad)", { XX } },
3954 /* 10 */
3955 { "frczps", { XM, EXq } },
3956 { "frczpd", { XM, EXq } },
3957 { "frczss", { XM, EXq } },
3958 { "frczsd", { XM, EXq } },
3959 { "(bad)", { XX } },
3960 { "(bad)", { XX } },
3961 { "(bad)", { XX } },
3962 { "(bad)", { XX } },
3963 /* 18 */
3964 { "(bad)", { XX } },
3965 { "(bad)", { XX } },
3966 { "(bad)", { XX } },
3967 { "(bad)", { XX } },
3968 { "(bad)", { XX } },
3969 { "(bad)", { XX } },
3970 { "(bad)", { XX } },
3971 { "(bad)", { XX } },
3972 /* 20 */
3973 { "ptest", { XX } },
3974 { "(bad)", { XX } },
3975 { "(bad)", { XX } },
3976 { "(bad)", { XX } },
3977 { "(bad)", { XX } },
3978 { "(bad)", { XX } },
3979 { "(bad)", { XX } },
3980 { "(bad)", { XX } },
3981 /* 28 */
3982 { "(bad)", { XX } },
3983 { "(bad)", { XX } },
3984 { "(bad)", { XX } },
3985 { "(bad)", { XX } },
3986 { "(bad)", { XX } },
3987 { "(bad)", { XX } },
3988 { "(bad)", { XX } },
3989 { "(bad)", { XX } },
3990 /* 30 */
85f10a01
MM		 3991 { "cvtph2ps", { XM, EXd } },
3992 { "cvtps2ph", { EXd, XM } },
d5d7db8e
L		 3993 { "(bad)", { XX } },
3994 { "(bad)", { XX } },
3995 { "(bad)", { XX } },
3996 { "(bad)", { XX } },
3997 { "(bad)", { XX } },
3998 { "(bad)", { XX } },
85f10a01 3999 /* 38 */
d5d7db8e
L		 4000 { "(bad)", { XX } },
4001 { "(bad)", { XX } },
4002 { "(bad)", { XX } },
4003 { "(bad)", { XX } },
4004 { "(bad)", { XX } },
4005 { "(bad)", { XX } },
4006 { "(bad)", { XX } },
4007 { "(bad)", { XX } },
96fbad73 4008 /* 40 */
d5d7db8e 4009 { "(bad)", { XX } },
85f10a01
MM		 4010 { "phaddbw", { XM, EXq } },
4011 { "phaddbd", { XM, EXq } },
4012 { "phaddbq", { XM, EXq } },
d5d7db8e
L		 4013 { "(bad)", { XX } },
4014 { "(bad)", { XX } },
85f10a01
MM		 4015 { "phaddwd", { XM, EXq } },
4016 { "phaddwq", { XM, EXq } },
96fbad73 4017 /* 48 */
d5d7db8e
L		 4018 { "(bad)", { XX } },
4019 { "(bad)", { XX } },
4020 { "(bad)", { XX } },
85f10a01 4021 { "phadddq", { XM, EXq } },
d5d7db8e
L		 4022 { "(bad)", { XX } },
4023 { "(bad)", { XX } },
4024 { "(bad)", { XX } },
4025 { "(bad)", { XX } },
96fbad73 4026 /* 50 */
d5d7db8e 4027 { "(bad)", { XX } },
85f10a01
MM		 4028 { "phaddubw", { XM, EXq } },
4029 { "phaddubd", { XM, EXq } },
4030 { "phaddubq", { XM, EXq } },
d5d7db8e
L		 4031 { "(bad)", { XX } },
4032 { "(bad)", { XX } },
85f10a01
MM		 4033 { "phadduwd", { XM, EXq } },
4034 { "phadduwq", { XM, EXq } },
96fbad73 4035 /* 58 */
d5d7db8e
L		 4036 { "(bad)", { XX } },
4037 { "(bad)", { XX } },
4038 { "(bad)", { XX } },
85f10a01 4039 { "phaddudq", { XM, EXq } },
d5d7db8e
L		 4040 { "(bad)", { XX } },
4041 { "(bad)", { XX } },
4042 { "(bad)", { XX } },
4043 { "(bad)", { XX } },
96fbad73 4044 /* 60 */
d5d7db8e 4045 { "(bad)", { XX } },
85f10a01
MM		 4046 { "phsubbw", { XM, EXq } },
4047 { "phsubbd", { XM, EXq } },
4048 { "phsubbq", { XM, EXq } },
d5d7db8e
L		 4049 { "(bad)", { XX } },
4050 { "(bad)", { XX } },
4051 { "(bad)", { XX } },
4052 { "(bad)", { XX } },
96fbad73 4053 /* 68 */
d5d7db8e
L		 4054 { "(bad)", { XX } },
4055 { "(bad)", { XX } },
4056 { "(bad)", { XX } },
4057 { "(bad)", { XX } },
4058 { "(bad)", { XX } },
4059 { "(bad)", { XX } },
4060 { "(bad)", { XX } },
4061 { "(bad)", { XX } },
96fbad73 4062 /* 70 */
d5d7db8e
L		 4063 { "(bad)", { XX } },
4064 { "(bad)", { XX } },
4065 { "(bad)", { XX } },
4066 { "(bad)", { XX } },
4067 { "(bad)", { XX } },
4068 { "(bad)", { XX } },
4069 { "(bad)", { XX } },
4070 { "(bad)", { XX } },
96fbad73 4071 /* 78 */
d5d7db8e
L		 4072 { "(bad)", { XX } },
4073 { "(bad)", { XX } },
4074 { "(bad)", { XX } },
4075 { "(bad)", { XX } },
4076 { "(bad)", { XX } },
4077 { "(bad)", { XX } },
4078 { "(bad)", { XX } },
4079 { "(bad)", { XX } },
96fbad73 4080 /* 80 */
d5d7db8e
L		 4081 { "(bad)", { XX } },
4082 { "(bad)", { XX } },
4083 { "(bad)", { XX } },
4084 { "(bad)", { XX } },
4085 { "(bad)", { XX } },
4086 { "(bad)", { XX } },
4087 { "(bad)", { XX } },
4088 { "(bad)", { XX } },
96fbad73 4089 /* 88 */
d5d7db8e
L		 4090 { "(bad)", { XX } },
4091 { "(bad)", { XX } },
4092 { "(bad)", { XX } },
4093 { "(bad)", { XX } },
4094 { "(bad)", { XX } },
4095 { "(bad)", { XX } },
4096 { "(bad)", { XX } },
4097 { "(bad)", { XX } },
96fbad73 4098 /* 90 */
d5d7db8e
L		 4099 { "(bad)", { XX } },
4100 { "(bad)", { XX } },
4101 { "(bad)", { XX } },
4102 { "(bad)", { XX } },
4103 { "(bad)", { XX } },
4104 { "(bad)", { XX } },
4105 { "(bad)", { XX } },
4106 { "(bad)", { XX } },
96fbad73 4107 /* 98 */
d5d7db8e
L		 4108 { "(bad)", { XX } },
4109 { "(bad)", { XX } },
4110 { "(bad)", { XX } },
4111 { "(bad)", { XX } },
4112 { "(bad)", { XX } },
4113 { "(bad)", { XX } },
4114 { "(bad)", { XX } },
4115 { "(bad)", { XX } },
96fbad73 4116 /* a0 */
d5d7db8e
L		 4117 { "(bad)", { XX } },
4118 { "(bad)", { XX } },
4119 { "(bad)", { XX } },
4120 { "(bad)", { XX } },
4121 { "(bad)", { XX } },
4122 { "(bad)", { XX } },
4123 { "(bad)", { XX } },
4124 { "(bad)", { XX } },
96fbad73 4125 /* a8 */
d5d7db8e
L		 4126 { "(bad)", { XX } },
4127 { "(bad)", { XX } },
4128 { "(bad)", { XX } },
4129 { "(bad)", { XX } },
4130 { "(bad)", { XX } },
4131 { "(bad)", { XX } },
4132 { "(bad)", { XX } },
4133 { "(bad)", { XX } },
96fbad73 4134 /* b0 */
d5d7db8e
L		 4135 { "(bad)", { XX } },
4136 { "(bad)", { XX } },
4137 { "(bad)", { XX } },
4138 { "(bad)", { XX } },
4139 { "(bad)", { XX } },
4140 { "(bad)", { XX } },
4141 { "(bad)", { XX } },
4142 { "(bad)", { XX } },
96fbad73 4143 /* b8 */
d5d7db8e
L		 4144 { "(bad)", { XX } },
4145 { "(bad)", { XX } },
4146 { "(bad)", { XX } },
4147 { "(bad)", { XX } },
4148 { "(bad)", { XX } },
4149 { "(bad)", { XX } },
4150 { "(bad)", { XX } },
4151 { "(bad)", { XX } },
96fbad73 4152 /* c0 */
d5d7db8e
L		 4153 { "(bad)", { XX } },
4154 { "(bad)", { XX } },
4155 { "(bad)", { XX } },
4156 { "(bad)", { XX } },
4157 { "(bad)", { XX } },
4158 { "(bad)", { XX } },
4159 { "(bad)", { XX } },
4160 { "(bad)", { XX } },
96fbad73 4161 /* c8 */
d5d7db8e
L		 4162 { "(bad)", { XX } },
4163 { "(bad)", { XX } },
4164 { "(bad)", { XX } },
4165 { "(bad)", { XX } },
4166 { "(bad)", { XX } },
4167 { "(bad)", { XX } },
4168 { "(bad)", { XX } },
4169 { "(bad)", { XX } },
96fbad73 4170 /* d0 */
d5d7db8e
L		 4171 { "(bad)", { XX } },
4172 { "(bad)", { XX } },
4173 { "(bad)", { XX } },
4174 { "(bad)", { XX } },
4175 { "(bad)", { XX } },
4176 { "(bad)", { XX } },
4177 { "(bad)", { XX } },
4178 { "(bad)", { XX } },
96fbad73 4179 /* d8 */
d5d7db8e
L		 4180 { "(bad)", { XX } },
4181 { "(bad)", { XX } },
4182 { "(bad)", { XX } },
4183 { "(bad)", { XX } },
4184 { "(bad)", { XX } },
4185 { "(bad)", { XX } },
4186 { "(bad)", { XX } },
4187 { "(bad)", { XX } },
96fbad73 4188 /* e0 */
d5d7db8e
L		 4189 { "(bad)", { XX } },
4190 { "(bad)", { XX } },
4191 { "(bad)", { XX } },
4192 { "(bad)", { XX } },
4193 { "(bad)", { XX } },
4194 { "(bad)", { XX } },
4195 { "(bad)", { XX } },
4196 { "(bad)", { XX } },
96fbad73 4197 /* e8 */
d5d7db8e
L		 4198 { "(bad)", { XX } },
4199 { "(bad)", { XX } },
4200 { "(bad)", { XX } },
4201 { "(bad)", { XX } },
4202 { "(bad)", { XX } },
4203 { "(bad)", { XX } },
4204 { "(bad)", { XX } },
4205 { "(bad)", { XX } },
96fbad73 4206 /* f0 */
85f10a01
MM		 4207 { "(bad)", { XX } },
4208 { "(bad)", { XX } },
d5d7db8e
L		 4209 { "(bad)", { XX } },
4210 { "(bad)", { XX } },
4211 { "(bad)", { XX } },
4212 { "(bad)", { XX } },
4213 { "(bad)", { XX } },
4214 { "(bad)", { XX } },
96fbad73 4215 /* f8 */
d5d7db8e
L		 4216 { "(bad)", { XX } },
4217 { "(bad)", { XX } },
4218 { "(bad)", { XX } },
4219 { "(bad)", { XX } },
4220 { "(bad)", { XX } },
4221 { "(bad)", { XX } },
4222 { "(bad)", { XX } },
4223 { "(bad)", { XX } },
331d2d0d 4224 },
89b66d55 4225 /* THREE_BYTE_0F7B */
331d2d0d 4226 {
96fbad73 4227 /* 00 */
d5d7db8e
L		 4228 { "(bad)", { XX } },
4229 { "(bad)", { XX } },
4230 { "(bad)", { XX } },
4231 { "(bad)", { XX } },
4232 { "(bad)", { XX } },
4233 { "(bad)", { XX } },
4234 { "(bad)", { XX } },
4235 { "(bad)", { XX } },
96fbad73 4236 /* 08 */
d5d7db8e
L		 4237 { "(bad)", { XX } },
4238 { "(bad)", { XX } },
4239 { "(bad)", { XX } },
4240 { "(bad)", { XX } },
4241 { "(bad)", { XX } },
4242 { "(bad)", { XX } },
4243 { "(bad)", { XX } },
4244 { "(bad)", { XX } },
85f10a01 4245 /* 10 */
d5d7db8e
L		 4246 { "(bad)", { XX } },
4247 { "(bad)", { XX } },
4248 { "(bad)", { XX } },
4249 { "(bad)", { XX } },
4250 { "(bad)", { XX } },
4251 { "(bad)", { XX } },
4252 { "(bad)", { XX } },
4253 { "(bad)", { XX } },
85f10a01 4254 /* 18 */
d5d7db8e
L		 4255 { "(bad)", { XX } },
4256 { "(bad)", { XX } },
4257 { "(bad)", { XX } },
4258 { "(bad)", { XX } },
4259 { "(bad)", { XX } },
4260 { "(bad)", { XX } },
4261 { "(bad)", { XX } },
4262 { "(bad)", { XX } },
85f10a01 4263 /* 20 */
d5d7db8e
L		 4264 { "(bad)", { XX } },
4265 { "(bad)", { XX } },
4266 { "(bad)", { XX } },
4267 { "(bad)", { XX } },
4268 { "(bad)", { XX } },
4269 { "(bad)", { XX } },
4270 { "(bad)", { XX } },
4271 { "(bad)", { XX } },
85f10a01 4272 /* 28 */
d5d7db8e
L		 4273 { "(bad)", { XX } },
4274 { "(bad)", { XX } },
4275 { "(bad)", { XX } },
4276 { "(bad)", { XX } },
4277 { "(bad)", { XX } },
4278 { "(bad)", { XX } },
4279 { "(bad)", { XX } },
4280 { "(bad)", { XX } },
85f10a01 4281 /* 30 */
d5d7db8e
L		 4282 { "(bad)", { XX } },
4283 { "(bad)", { XX } },
4284 { "(bad)", { XX } },
4285 { "(bad)", { XX } },
4286 { "(bad)", { XX } },
4287 { "(bad)", { XX } },
85f10a01
MM		 4288 { "(bad)", { XX } },
4289 { "(bad)", { XX } },
4290 /* 38 */
4291 { "(bad)", { XX } },
4292 { "(bad)", { XX } },
4293 { "(bad)", { XX } },
d5d7db8e
L		 4294 { "(bad)", { XX } },
4295 { "(bad)", { XX } },
4296 { "(bad)", { XX } },
4297 { "(bad)", { XX } },
4298 { "(bad)", { XX } },
85f10a01
MM		 4299 /* 40 */
4300 { "protb", { XM, EXq, Ib } },
4301 { "protw", { XM, EXq, Ib } },
4302 { "protd", { XM, EXq, Ib } },
4303 { "protq", { XM, EXq, Ib } },
4304 { "pshlb", { XM, EXq, Ib } },
4305 { "pshlw", { XM, EXq, Ib } },
4306 { "pshld", { XM, EXq, Ib } },
4307 { "pshlq", { XM, EXq, Ib } },
4308 /* 48 */
4309 { "pshab", { XM, EXq, Ib } },
4310 { "pshaw", { XM, EXq, Ib } },
4311 { "pshad", { XM, EXq, Ib } },
4312 { "pshaq", { XM, EXq, Ib } },
4313 { "(bad)", { XX } },
d5d7db8e
L		 4314 { "(bad)", { XX } },
4315 { "(bad)", { XX } },
4316 { "(bad)", { XX } },
96fbad73 4317 /* 50 */
d5d7db8e
L		 4318 { "(bad)", { XX } },
4319 { "(bad)", { XX } },
4320 { "(bad)", { XX } },
4321 { "(bad)", { XX } },
4322 { "(bad)", { XX } },
4323 { "(bad)", { XX } },
4324 { "(bad)", { XX } },
4325 { "(bad)", { XX } },
96fbad73 4326 /* 58 */
d5d7db8e
L		 4327 { "(bad)", { XX } },
4328 { "(bad)", { XX } },
4329 { "(bad)", { XX } },
4330 { "(bad)", { XX } },
4331 { "(bad)", { XX } },
4332 { "(bad)", { XX } },
4333 { "(bad)", { XX } },
4334 { "(bad)", { XX } },
96fbad73 4335 /* 60 */
85f10a01
MM		 4336 { "(bad)", { XX } },
4337 { "(bad)", { XX } },
4338 { "(bad)", { XX } },
4339 { "(bad)", { XX } },
d5d7db8e
L		 4340 { "(bad)", { XX } },
4341 { "(bad)", { XX } },
4342 { "(bad)", { XX } },
4343 { "(bad)", { XX } },
96fbad73 4344 /* 68 */
d5d7db8e
L		 4345 { "(bad)", { XX } },
4346 { "(bad)", { XX } },
4347 { "(bad)", { XX } },
4348 { "(bad)", { XX } },
4349 { "(bad)", { XX } },
4350 { "(bad)", { XX } },
4351 { "(bad)", { XX } },
4352 { "(bad)", { XX } },
96fbad73 4353 /* 70 */
d5d7db8e
L		 4354 { "(bad)", { XX } },
4355 { "(bad)", { XX } },
4356 { "(bad)", { XX } },
4357 { "(bad)", { XX } },
4358 { "(bad)", { XX } },
4359 { "(bad)", { XX } },
4360 { "(bad)", { XX } },
4361 { "(bad)", { XX } },
96fbad73 4362 /* 78 */
d5d7db8e
L		 4363 { "(bad)", { XX } },
4364 { "(bad)", { XX } },
4365 { "(bad)", { XX } },
4366 { "(bad)", { XX } },
4367 { "(bad)", { XX } },
4368 { "(bad)", { XX } },
4369 { "(bad)", { XX } },
4370 { "(bad)", { XX } },
96fbad73 4371 /* 80 */
d5d7db8e
L		 4372 { "(bad)", { XX } },
4373 { "(bad)", { XX } },
4374 { "(bad)", { XX } },
4375 { "(bad)", { XX } },
4376 { "(bad)", { XX } },
4377 { "(bad)", { XX } },
4378 { "(bad)", { XX } },
4379 { "(bad)", { XX } },
96fbad73 4380 /* 88 */
d5d7db8e
L		 4381 { "(bad)", { XX } },
4382 { "(bad)", { XX } },
4383 { "(bad)", { XX } },
4384 { "(bad)", { XX } },
4385 { "(bad)", { XX } },
4386 { "(bad)", { XX } },
4387 { "(bad)", { XX } },
4388 { "(bad)", { XX } },
96fbad73 4389 /* 90 */
d5d7db8e
L		 4390 { "(bad)", { XX } },
4391 { "(bad)", { XX } },
4392 { "(bad)", { XX } },
4393 { "(bad)", { XX } },
4394 { "(bad)", { XX } },
4395 { "(bad)", { XX } },
4396 { "(bad)", { XX } },
4397 { "(bad)", { XX } },
96fbad73 4398 /* 98 */
d5d7db8e
L		 4399 { "(bad)", { XX } },
4400 { "(bad)", { XX } },
4401 { "(bad)", { XX } },
4402 { "(bad)", { XX } },
4403 { "(bad)", { XX } },
4404 { "(bad)", { XX } },
4405 { "(bad)", { XX } },
4406 { "(bad)", { XX } },
96fbad73 4407 /* a0 */
d5d7db8e
L		 4408 { "(bad)", { XX } },
4409 { "(bad)", { XX } },
4410 { "(bad)", { XX } },
4411 { "(bad)", { XX } },
4412 { "(bad)", { XX } },
4413 { "(bad)", { XX } },
4414 { "(bad)", { XX } },
4415 { "(bad)", { XX } },
96fbad73 4416 /* a8 */
d5d7db8e
L		 4417 { "(bad)", { XX } },
4418 { "(bad)", { XX } },
4419 { "(bad)", { XX } },
4420 { "(bad)", { XX } },
4421 { "(bad)", { XX } },
4422 { "(bad)", { XX } },
4423 { "(bad)", { XX } },
4424 { "(bad)", { XX } },
96fbad73 4425 /* b0 */
d5d7db8e
L		 4426 { "(bad)", { XX } },
4427 { "(bad)", { XX } },
4428 { "(bad)", { XX } },
4429 { "(bad)", { XX } },
4430 { "(bad)", { XX } },
4431 { "(bad)", { XX } },
4432 { "(bad)", { XX } },
4433 { "(bad)", { XX } },
96fbad73 4434 /* b8 */
d5d7db8e
L		 4435 { "(bad)", { XX } },
4436 { "(bad)", { XX } },
4437 { "(bad)", { XX } },
4438 { "(bad)", { XX } },
4439 { "(bad)", { XX } },
4440 { "(bad)", { XX } },
4441 { "(bad)", { XX } },
4442 { "(bad)", { XX } },
96fbad73 4443 /* c0 */
d5d7db8e
L		 4444 { "(bad)", { XX } },
4445 { "(bad)", { XX } },
4446 { "(bad)", { XX } },
4447 { "(bad)", { XX } },
4448 { "(bad)", { XX } },
4449 { "(bad)", { XX } },
4450 { "(bad)", { XX } },
4451 { "(bad)", { XX } },
96fbad73 4452 /* c8 */
d5d7db8e
L		 4453 { "(bad)", { XX } },
4454 { "(bad)", { XX } },
4455 { "(bad)", { XX } },
4456 { "(bad)", { XX } },
4457 { "(bad)", { XX } },
4458 { "(bad)", { XX } },
4459 { "(bad)", { XX } },
4460 { "(bad)", { XX } },
96fbad73 4461 /* d0 */
d5d7db8e
L		 4462 { "(bad)", { XX } },
4463 { "(bad)", { XX } },
4464 { "(bad)", { XX } },
4465 { "(bad)", { XX } },
4466 { "(bad)", { XX } },
4467 { "(bad)", { XX } },
4468 { "(bad)", { XX } },
4469 { "(bad)", { XX } },
96fbad73 4470 /* d8 */
d5d7db8e
L		 4471 { "(bad)", { XX } },
4472 { "(bad)", { XX } },
4473 { "(bad)", { XX } },
4474 { "(bad)", { XX } },
4475 { "(bad)", { XX } },
4476 { "(bad)", { XX } },
4477 { "(bad)", { XX } },
4478 { "(bad)", { XX } },
96fbad73 4479 /* e0 */
d5d7db8e
L		 4480 { "(bad)", { XX } },
4481 { "(bad)", { XX } },
4482 { "(bad)", { XX } },
4483 { "(bad)", { XX } },
4484 { "(bad)", { XX } },
4485 { "(bad)", { XX } },
4486 { "(bad)", { XX } },
4487 { "(bad)", { XX } },
96fbad73 4488 /* e8 */
d5d7db8e
L		 4489 { "(bad)", { XX } },
4490 { "(bad)", { XX } },
4491 { "(bad)", { XX } },
4492 { "(bad)", { XX } },
4493 { "(bad)", { XX } },
4494 { "(bad)", { XX } },
4495 { "(bad)", { XX } },
4496 { "(bad)", { XX } },
96fbad73 4497 /* f0 */
d5d7db8e
L		 4498 { "(bad)", { XX } },
4499 { "(bad)", { XX } },
4500 { "(bad)", { XX } },
4501 { "(bad)", { XX } },
4502 { "(bad)", { XX } },
4503 { "(bad)", { XX } },
4504 { "(bad)", { XX } },
4505 { "(bad)", { XX } },
96fbad73 4506 /* f8 */
d5d7db8e
L		 4507 { "(bad)", { XX } },
4508 { "(bad)", { XX } },
4509 { "(bad)", { XX } },
4510 { "(bad)", { XX } },
4511 { "(bad)", { XX } },
4512 { "(bad)", { XX } },
4513 { "(bad)", { XX } },
4514 { "(bad)", { XX } },
ce518a5f 4515 }
331d2d0d
L		 4516};
4517
1ceb70f8 4518static const struct dis386 mod_table[][2] = {
b844680a 4519 {
1ceb70f8 4520 /* MOD_8D */
d8faab4e
L		 4521 { "leaS", { Gv, M } },
4522 { "(bad)", { XX } },
4523 },
4524 {
92fddf8e
L		 4525 /* MOD_0F01_REG_0 */
4526 { X86_64_TABLE (X86_64_0F01_REG_0) },
4527 { RM_TABLE (RM_0F01_REG_0) },
d8faab4e
L		 4528 },
4529 {
92fddf8e
L		 4530 /* MOD_0F01_REG_1 */
4531 { X86_64_TABLE (X86_64_0F01_REG_1) },
4532 { RM_TABLE (RM_0F01_REG_1) },
d8faab4e
L		 4533 },
4534 {
92fddf8e
L		 4535 /* MOD_0F01_REG_2 */
4536 { X86_64_TABLE (X86_64_0F01_REG_2) },
d8faab4e
L		 4537 { "(bad)", { XX } },
4538 },
4539 {
92fddf8e
L		 4540 /* MOD_0F01_REG_3 */
4541 { X86_64_TABLE (X86_64_0F01_REG_3) },
4542 { RM_TABLE (RM_0F01_REG_3) },
d8faab4e
L		 4543 },
4544 {
92fddf8e
L		 4545 /* MOD_0F01_REG_7 */
4546 { "invlpg", { Mb } },
4547 { RM_TABLE (RM_0F01_REG_7) },
b844680a
L		 4548 },
4549 {
92fddf8e
L		 4550 /* MOD_0F12_PREFIX_0 */
4551 { "movlps", { XM, EXq } },
4552 { "movhlps", { XM, EXq } },
b844680a
L		 4553 },
4554 {
92fddf8e
L		 4555 /* MOD_0F13 */
4556 { "movlpX", { EXq, XM } },
d8faab4e
L		 4557 { "(bad)", { XX } },
4558 },
4559 {
92fddf8e
L		 4560 /* MOD_0F16_PREFIX_0 */
4561 { "movhps", { XM, EXq } },
4562 { "movlhps", { XM, EXq } },
b844680a
L		 4563 },
4564 {
92fddf8e
L		 4565 /* MOD_0F17 */
4566 { "movhpX", { EXq, XM } },
b844680a
L		 4567 { "(bad)", { XX } },
4568 },
4569 {
92fddf8e
L		 4570 /* MOD_0F18_REG_0 */
4571 { "prefetchnta", { Mb } },
b844680a 4572 { "(bad)", { XX } },
b844680a
L		 4573 },
4574 {
92fddf8e
L		 4575 /* MOD_0F18_REG_1 */
4576 { "prefetcht0", { Mb } },
4577 { "(bad)", { XX } },
b844680a
L		 4578 },
4579 {
92fddf8e
L		 4580 /* MOD_0F18_REG_2 */
4581 { "prefetcht1", { Mb } },
4582 { "(bad)", { XX } },
b844680a
L		 4583 },
4584 {
92fddf8e
L		 4585 /* MOD_0F18_REG_3 */
4586 { "prefetcht2", { Mb } },
b844680a 4587 { "(bad)", { XX } },
b844680a
L		 4588 },
4589 {
92fddf8e
L		 4590 /* MOD_0F20 */
4591 { "(bad)", { XX } },
4592 { "movZ", { Rm, Cm } },
b844680a
L		 4593 },
4594 {
92fddf8e
L		 4595 /* MOD_0F21 */
4596 { "(bad)", { XX } },
4597 { "movZ", { Rm, Dm } },
b844680a
L		 4598 },
4599 {
92fddf8e 4600 /* MOD_0F22 */
b844680a 4601 { "(bad)", { XX } },
92fddf8e 4602 { "movZ", { Cm, Rm } },
b844680a
L		 4603 },
4604 {
92fddf8e 4605 /* MOD_0F23 */
b844680a 4606 { "(bad)", { XX } },
92fddf8e 4607 { "movZ", { Dm, Rm } },
b844680a
L		 4608 },
4609 {
92fddf8e
L		 4610 /* MOD_0F24 */
4611 { THREE_BYTE_TABLE (THREE_BYTE_0F24) },
4612 { "movL", { Rd, Td } },
b844680a
L		 4613 },
4614 {
92fddf8e 4615 /* MOD_0F26 */
b844680a 4616 { "(bad)", { XX } },
92fddf8e 4617 { "movL", { Td, Rd } },
b844680a 4618 },
75c135a8
L		 4619 {
4620 /* MOD_0F2B_PREFIX_0 */
4621 {"movntps", { Ev, XM } },
4622 { "(bad)", { XX } },
4623 },
4624 {
4625 /* MOD_0F2B_PREFIX_1 */
4626 {"movntss", { Ed, XM } },
4627 { "(bad)", { XX } },
4628 },
4629 {
4630 /* MOD_0F2B_PREFIX_2 */
4631 {"movntpd", { Ev, XM } },
4632 { "(bad)", { XX } },
4633 },
4634 {
4635 /* MOD_0F2B_PREFIX_3 */
4636 {"movntsd", { Eq, XM } },
4637 { "(bad)", { XX } },
4638 },
4639 {
4640 /* MOD_0F51 */
4641 { "(bad)", { XX } },
4642 { "movmskpX", { Gdq, XS } },
4643 },
b844680a 4644 {
1ceb70f8 4645 /* MOD_0F71_REG_2 */
b844680a 4646 { "(bad)", { XX } },
4e7d34a6 4647 { "psrlw", { MS, Ib } },
b844680a
L		 4648 },
4649 {
1ceb70f8 4650 /* MOD_0F71_REG_4 */
b844680a 4651 { "(bad)", { XX } },
4e7d34a6 4652 { "psraw", { MS, Ib } },
b844680a
L		 4653 },
4654 {
1ceb70f8 4655 /* MOD_0F71_REG_6 */
b844680a 4656 { "(bad)", { XX } },
4e7d34a6 4657 { "psllw", { MS, Ib } },
b844680a
L		 4658 },
4659 {
1ceb70f8 4660 /* MOD_0F72_REG_2 */
b844680a 4661 { "(bad)", { XX } },
4e7d34a6 4662 { "psrld", { MS, Ib } },
b844680a
L		 4663 },
4664 {
1ceb70f8 4665 /* MOD_0F72_REG_4 */
b844680a 4666 { "(bad)", { XX } },
4e7d34a6 4667 { "psrad", { MS, Ib } },
b844680a
L		 4668 },
4669 {
1ceb70f8 4670 /* MOD_0F72_REG_6 */
b844680a 4671 { "(bad)", { XX } },
4e7d34a6 4672 { "pslld", { MS, Ib } },
b844680a
L		 4673 },
4674 {
1ceb70f8 4675 /* MOD_0F73_REG_2 */
4e7d34a6
L		 4676 { "(bad)", { XX } },
4677 { "psrlq", { MS, Ib } },
b844680a
L		 4678 },
4679 {
1ceb70f8 4680 /* MOD_0F73_REG_3 */
b844680a 4681 { "(bad)", { XX } },
1ceb70f8 4682 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
b844680a
L		 4683 },
4684 {
1ceb70f8 4685 /* MOD_0F73_REG_6 */
b844680a 4686 { "(bad)", { XX } },
4e7d34a6 4687 { "psllq", { MS, Ib } },
b844680a
L		 4688 },
4689 {
1ceb70f8 4690 /* MOD_0F73_REG_7 */
b844680a 4691 { "(bad)", { XX } },
1ceb70f8 4692 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
b844680a
L		 4693 },
4694 {
1ceb70f8 4695 /* MOD_0FAE_REG_0 */
4e7d34a6 4696 { "fxsave", { M } },
b844680a
L		 4697 { "(bad)", { XX } },
4698 },
d8faab4e 4699 {
1ceb70f8 4700 /* MOD_0FAE_REG_1 */
4e7d34a6 4701 { "fxrstor", { M } },
d8faab4e
L		 4702 { "(bad)", { XX } },
4703 },
4704 {
1ceb70f8 4705 /* MOD_0FAE_REG_2 */
4e7d34a6 4706 { "ldmxcsr", { Md } },
d8faab4e
L		 4707 { "(bad)", { XX } },
4708 },
876d4bfa 4709 {
1ceb70f8 4710 /* MOD_0FAE_REG_3 */
4e7d34a6 4711 { "stmxcsr", { Md } },
876d4bfa
L		 4712 { "(bad)", { XX } },
4713 },
4714 {
1ceb70f8 4715 /* MOD_0FAE_REG_5 */
876d4bfa 4716 { "(bad)", { XX } },
1ceb70f8 4717 { RM_TABLE (RM_0FAE_REG_5) },
876d4bfa
L		 4718 },
4719 {
1ceb70f8 4720 /* MOD_0FAE_REG_6 */
4e7d34a6 4721 { "(bad)", { XX } },
1ceb70f8 4722 { RM_TABLE (RM_0FAE_REG_6) },
876d4bfa
L		 4723 },
4724 {
1ceb70f8 4725 /* MOD_0FAE_REG_7 */
4e7d34a6 4726 { "clflush", { Mb } },
1ceb70f8 4727 { RM_TABLE (RM_0FAE_REG_7) },
876d4bfa 4728 },
bbedc832 4729 {
92fddf8e
L		 4730 /* MOD_0FB2 */
4731 { "lssS", { Gv, Mp } },
4e7d34a6 4732 { "(bad)", { XX } },
bbedc832 4733 },
144c41d9 4734 {
92fddf8e
L		 4735 /* MOD_0FB4 */
4736 { "lfsS", { Gv, Mp } },
4e7d34a6 4737 { "(bad)", { XX } },
144c41d9 4738 },
1afd85e3 4739 {
92fddf8e
L		 4740 /* MOD_0FB5 */
4741 { "lgsS", { Gv, Mp } },
4742 { "(bad)", { XX } },
1afd85e3
L		 4743 },
4744 {
92fddf8e
L		 4745 /* MOD_0FC7_REG_6 */
4746 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
4747 { "(bad)", { XX } },
4748 },
4749 {
4750 /* MOD_0FC7_REG_7 */
4751 { "vmptrst", { Mq } },
4752 { "(bad)", { XX } },
1afd85e3 4753 },
75c135a8
L		 4754 {
4755 /* MOD_0FD7 */
4756 { "(bad)", { XX } },
4757 { "pmovmskb", { Gdq, MS } },
4758 },
4759 {
4760 /* MOD_0FE7_PREFIX_2 */
4761 { "movntdq", { EM, XM } },
4762 { "(bad)", { XX } },
4763 },
1afd85e3 4764 {
1ceb70f8 4765 /* MOD_0FF0_PREFIX_3 */
4e7d34a6 4766 { "lddqu", { XM, M } },
1afd85e3 4767 { "(bad)", { XX } },
1afd85e3 4768 },
75c135a8
L		 4769 {
4770 /* MOD_0F382A_PREFIX_2 */
4771 { "movntdqa", { XM, EM } },
4772 { "(bad)", { XX } },
4773 },
1afd85e3 4774 {
1ceb70f8 4775 /* MOD_62_32BIT */
4e7d34a6 4776 { "bound{S|}", { Gv, Ma } },
1afd85e3 4777 { "(bad)", { XX } },
1afd85e3
L		 4778 },
4779 {
1ceb70f8 4780 /* MOD_C4_32BIT */
4e7d34a6
L		 4781 { "lesS", { Gv, Mp } },
4782 { "(bad)", { XX } },
1afd85e3
L		 4783 },
4784 {
1ceb70f8 4785 /* MOD_C5_32BIT */
4e7d34a6 4786 { "ldsS", { Gv, Mp } },
1afd85e3 4787 { "(bad)", { XX } },
1afd85e3 4788 },
b844680a
L		 4789};
4790
1ceb70f8 4791static const struct dis386 rm_table[][8] = {
b844680a 4792 {
1ceb70f8 4793 /* RM_0F01_REG_0 */
b844680a
L		 4794 { "(bad)", { XX } },
4795 { "vmcall", { Skip_MODRM } },
4796 { "vmlaunch", { Skip_MODRM } },
4797 { "vmresume", { Skip_MODRM } },
4798 { "vmxoff", { Skip_MODRM } },
4799 { "(bad)", { XX } },
4800 { "(bad)", { XX } },
4801 { "(bad)", { XX } },
4802 },
4803 {
1ceb70f8 4804 /* RM_0F01_REG_1 */
b844680a
L		 4805 { "monitor", { { OP_Monitor, 0 } } },
4806 { "mwait", { { OP_Mwait, 0 } } },
4807 { "(bad)", { XX } },
4808 { "(bad)", { XX } },
4809 { "(bad)", { XX } },
4810 { "(bad)", { XX } },
4811 { "(bad)", { XX } },
4812 { "(bad)", { XX } },
4813 },
4814 {
1ceb70f8 4815 /* RM_0F01_REG_3 */
4e7d34a6
L		 4816 { "vmrun", { Skip_MODRM } },
4817 { "vmmcall", { Skip_MODRM } },
4818 { "vmload", { Skip_MODRM } },
4819 { "vmsave", { Skip_MODRM } },
4820 { "stgi", { Skip_MODRM } },
4821 { "clgi", { Skip_MODRM } },
4822 { "skinit", { Skip_MODRM } },
4823 { "invlpga", { Skip_MODRM } },
4824 },
4825 {
1ceb70f8 4826 /* RM_0F01_REG_7 */
4e7d34a6
L		 4827 { "swapgs", { Skip_MODRM } },
4828 { "rdtscp", { Skip_MODRM } },
b844680a
L		 4829 { "(bad)", { XX } },
4830 { "(bad)", { XX } },
4831 { "(bad)", { XX } },
4832 { "(bad)", { XX } },
4833 { "(bad)", { XX } },
4834 { "(bad)", { XX } },
4835 },
4836 {
1ceb70f8 4837 /* RM_0FAE_REG_5 */
4e7d34a6 4838 { "lfence", { Skip_MODRM } },
b844680a
L		 4839 { "(bad)", { XX } },
4840 { "(bad)", { XX } },
4841 { "(bad)", { XX } },
4842 { "(bad)", { XX } },
4843 { "(bad)", { XX } },
4844 { "(bad)", { XX } },
4845 { "(bad)", { XX } },
4846 },
4847 {
1ceb70f8 4848 /* RM_0FAE_REG_6 */
4e7d34a6 4849 { "mfence", { Skip_MODRM } },
b844680a
L		 4850 { "(bad)", { XX } },
4851 { "(bad)", { XX } },
4852 { "(bad)", { XX } },
4853 { "(bad)", { XX } },
4854 { "(bad)", { XX } },
4855 { "(bad)", { XX } },
4856 { "(bad)", { XX } },
4857 },
bbedc832 4858 {
1ceb70f8 4859 /* RM_0FAE_REG_7 */
4e7d34a6
L		 4860 { "sfence", { Skip_MODRM } },
4861 { "(bad)", { XX } },
bbedc832
L		 4862 { "(bad)", { XX } },
4863 { "(bad)", { XX } },
4864 { "(bad)", { XX } },
4865 { "(bad)", { XX } },
4866 { "(bad)", { XX } },
4867 { "(bad)", { XX } },
144c41d9 4868 },
b844680a
L		 4869};
4870
c608c12e
AM		 4871#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
4872
252b5132 4873static void
26ca5450 4874ckprefix (void)
252b5132 4875{
52b15da3
JH		 4876 int newrex;
4877 rex = 0;
252b5132 4878 prefixes = 0;
7d421014 4879 used_prefixes = 0;
52b15da3 4880 rex_used = 0;
252b5132
RH		 4881 while (1)
4882 {
4883 FETCH_DATA (the_info, codep + 1);
52b15da3 4884 newrex = 0;
252b5132
RH		 4885 switch (*codep)
4886 {
52b15da3
JH		 4887 /* REX prefixes family. */
4888 case 0x40:
4889 case 0x41:
4890 case 0x42:
4891 case 0x43:
4892 case 0x44:
4893 case 0x45:
4894 case 0x46:
4895 case 0x47:
4896 case 0x48:
4897 case 0x49:
4898 case 0x4a:
4899 case 0x4b:
4900 case 0x4c:
4901 case 0x4d:
4902 case 0x4e:
4903 case 0x4f:
cb712a9e 4904 if (address_mode == mode_64bit)
52b15da3
JH		 4905 newrex = *codep;
4906 else
4907 return;
4908 break;
252b5132
RH		 4909 case 0xf3:
4910 prefixes |= PREFIX_REPZ;
4911 break;
4912 case 0xf2:
4913 prefixes |= PREFIX_REPNZ;
4914 break;
4915 case 0xf0:
4916 prefixes |= PREFIX_LOCK;
4917 break;
4918 case 0x2e:
4919 prefixes |= PREFIX_CS;
4920 break;
4921 case 0x36:
4922 prefixes |= PREFIX_SS;
4923 break;
4924 case 0x3e:
4925 prefixes |= PREFIX_DS;
4926 break;
4927 case 0x26:
4928 prefixes |= PREFIX_ES;
4929 break;
4930 case 0x64:
4931 prefixes |= PREFIX_FS;
4932 break;
4933 case 0x65:
4934 prefixes |= PREFIX_GS;
4935 break;
4936 case 0x66:
4937 prefixes |= PREFIX_DATA;
4938 break;
4939 case 0x67:
4940 prefixes |= PREFIX_ADDR;
4941 break;
5076851f 4942 case FWAIT_OPCODE:
252b5132
RH		 4943 /* fwait is really an instruction. If there are prefixes
4944 before the fwait, they belong to the fwait, *not* to the
4945 following instruction. */
3e7d61b2 4946 if (prefixes || rex)
252b5132
RH		 4947 {
4948 prefixes |= PREFIX_FWAIT;
4949 codep++;
4950 return;
4951 }
4952 prefixes = PREFIX_FWAIT;
4953 break;
4954 default:
4955 return;
4956 }
52b15da3
JH		 4957 /* Rex is ignored when followed by another prefix. */
4958 if (rex)
4959 {
3e7d61b2
AM		 4960 rex_used = rex;
4961 return;
52b15da3
JH		 4962 }
4963 rex = newrex;
252b5132
RH		 4964 codep++;
4965 }
4966}
4967
7d421014
ILT		 4968/* Return the name of the prefix byte PREF, or NULL if PREF is not a
4969 prefix byte. */
4970
4971static const char *
26ca5450 4972prefix_name (int pref, int sizeflag)
7d421014 4973{
0003779b
L		 4974 static const char *rexes [16] =
4975 {
4976 "rex", /* 0x40 */
4977 "rex.B", /* 0x41 */
4978 "rex.X", /* 0x42 */
4979 "rex.XB", /* 0x43 */
4980 "rex.R", /* 0x44 */
4981 "rex.RB", /* 0x45 */
4982 "rex.RX", /* 0x46 */
4983 "rex.RXB", /* 0x47 */
4984 "rex.W", /* 0x48 */
4985 "rex.WB", /* 0x49 */
4986 "rex.WX", /* 0x4a */
4987 "rex.WXB", /* 0x4b */
4988 "rex.WR", /* 0x4c */
4989 "rex.WRB", /* 0x4d */
4990 "rex.WRX", /* 0x4e */
4991 "rex.WRXB", /* 0x4f */
4992 };
4993
7d421014
ILT		 4994 switch (pref)
4995 {
52b15da3
JH		 4996 /* REX prefixes family. */
4997 case 0x40:
52b15da3 4998 case 0x41:
52b15da3 4999 case 0x42:
52b15da3 5000 case 0x43:
52b15da3 5001 case 0x44:
52b15da3 5002 case 0x45:
52b15da3 5003 case 0x46:
52b15da3 5004 case 0x47:
52b15da3 5005 case 0x48:
52b15da3 5006 case 0x49:
52b15da3 5007 case 0x4a:
52b15da3 5008 case 0x4b:
52b15da3 5009 case 0x4c:
52b15da3 5010 case 0x4d:
52b15da3 5011 case 0x4e:
52b15da3 5012 case 0x4f:
0003779b 5013 return rexes [pref - 0x40];
7d421014
ILT		 5014 case 0xf3:
5015 return "repz";
5016 case 0xf2:
5017 return "repnz";
5018 case 0xf0:
5019 return "lock";
5020 case 0x2e:
5021 return "cs";
5022 case 0x36:
5023 return "ss";
5024 case 0x3e:
5025 return "ds";
5026 case 0x26:
5027 return "es";
5028 case 0x64:
5029 return "fs";
5030 case 0x65:
5031 return "gs";
5032 case 0x66:
5033 return (sizeflag & DFLAG) ? "data16" : "data32";
5034 case 0x67:
cb712a9e 5035 if (address_mode == mode_64bit)
db6eb5be 5036 return (sizeflag & AFLAG) ? "addr32" : "addr64";
c1a64871 5037 else
2888cb7a 5038 return (sizeflag & AFLAG) ? "addr16" : "addr32";
7d421014
ILT		 5039 case FWAIT_OPCODE:
5040 return "fwait";
5041 default:
5042 return NULL;
5043 }
5044}
5045
ce518a5f
L		 5046static char op_out[MAX_OPERANDS][100];
5047static int op_ad, op_index[MAX_OPERANDS];
1d9f512f 5048static int two_source_ops;
ce518a5f
L		 5049static bfd_vma op_address[MAX_OPERANDS];
5050static bfd_vma op_riprel[MAX_OPERANDS];
52b15da3 5051static bfd_vma start_pc;
ce518a5f 5052
252b5132
RH		 5053/*
5054 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
5055 * (see topic "Redundant prefixes" in the "Differences from 8086"
5056 * section of the "Virtual 8086 Mode" chapter.)
5057 * 'pc' should be the address of this instruction, it will
5058 * be used to print the target address if this is a relative jump or call
5059 * The function returns the length of this instruction in bytes.
5060 */
5061
252b5132 5062static char intel_syntax;
9d141669 5063static char intel_mnemonic = !SYSV386_COMPAT;
252b5132
RH		 5064static char open_char;
5065static char close_char;
5066static char separator_char;
5067static char scale_char;
5068
e396998b
AM		 5069/* Here for backwards compatibility. When gdb stops using
5070 print_insn_i386_att and print_insn_i386_intel these functions can
5071 disappear, and print_insn_i386 be merged into print_insn. */
252b5132 5072int
26ca5450 5073print_insn_i386_att (bfd_vma pc, disassemble_info *info)
252b5132
RH		 5074{
5075 intel_syntax = 0;
e396998b
AM		 5076
5077 return print_insn (pc, info);
252b5132
RH		 5078}
5079
5080int
26ca5450 5081print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
252b5132
RH		 5082{
5083 intel_syntax = 1;
e396998b
AM		 5084
5085 return print_insn (pc, info);
252b5132
RH		 5086}
5087
e396998b 5088int
26ca5450 5089print_insn_i386 (bfd_vma pc, disassemble_info *info)
e396998b
AM		 5090{
5091 intel_syntax = -1;
5092
5093 return print_insn (pc, info);
5094}
5095
f59a29b9
L		 5096void
5097print_i386_disassembler_options (FILE *stream)
5098{
5099 fprintf (stream, _("\n\
5100The following i386/x86-64 specific disassembler options are supported for use\n\
5101with the -M switch (multiple options should be separated by commas):\n"));
5102
5103 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
5104 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
5105 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
5106 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
5107 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
9d141669
L		 5108 fprintf (stream, _(" att-mnemonic\n"
5109 " Display instruction in AT&T mnemonic\n"));
5110 fprintf (stream, _(" intel-mnemonic\n"
5111 " Display instruction in Intel mnemonic\n"));
f59a29b9
L		 5112 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
5113 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
5114 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
5115 fprintf (stream, _(" data32 Assume 32bit data size\n"));
5116 fprintf (stream, _(" data16 Assume 16bit data size\n"));
5117 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
5118}
5119
b844680a
L		 5120/* Get a pointer to struct dis386 with a valid name. */
5121
5122static const struct dis386 *
8bb15339 5123get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
b844680a
L		 5124{
5125 int index;
5126
5127 if (dp->name != NULL)
5128 return dp;
5129
5130 switch (dp->op[0].bytemode)
5131 {
1ceb70f8
L		 5132 case USE_REG_TABLE:
5133 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
5134 break;
5135
5136 case USE_MOD_TABLE:
5137 index = modrm.mod == 0x3 ? 1 : 0;
5138 dp = &mod_table[dp->op[1].bytemode][index];
5139 break;
5140
5141 case USE_RM_TABLE:
5142 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
b844680a
L		 5143 break;
5144
4e7d34a6 5145 case USE_PREFIX_TABLE:
b844680a
L		 5146 index = 0;
5147 used_prefixes |= (prefixes & PREFIX_REPZ);
5148 if (prefixes & PREFIX_REPZ)
5149 {
5150 index = 1;
5151 repz_prefix = NULL;
5152 }
5153 else
5154 {
5155 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
5156 PREFIX_DATA. */
5157 used_prefixes |= (prefixes & PREFIX_REPNZ);
5158 if (prefixes & PREFIX_REPNZ)
5159 {
5160 index = 3;
5161 repnz_prefix = NULL;
5162 }
5163 else
5164 {
5165 used_prefixes |= (prefixes & PREFIX_DATA);
5166 if (prefixes & PREFIX_DATA)
5167 {
5168 index = 2;
5169 data_prefix = NULL;
5170 }
5171 }
5172 }
1ceb70f8 5173 dp = &prefix_table[dp->op[1].bytemode][index];
b844680a
L		 5174 break;
5175
4e7d34a6 5176 case USE_X86_64_TABLE:
b844680a
L		 5177 index = address_mode == mode_64bit ? 1 : 0;
5178 dp = &x86_64_table[dp->op[1].bytemode][index];
5179 break;
5180
4e7d34a6 5181 case USE_3BYTE_TABLE:
8bb15339
L		 5182 FETCH_DATA (info, codep + 2);
5183 index = *codep++;
5184 dp = &three_byte_table[dp->op[1].bytemode][index];
5185 modrm.mod = (*codep >> 6) & 3;
5186 modrm.reg = (*codep >> 3) & 7;
5187 modrm.rm = *codep & 7;
5188 break;
5189
b844680a
L		 5190 default:
5191 oappend (INTERNAL_DISASSEMBLER_ERROR);
5192 return NULL;
5193 }
5194
5195 if (dp->name != NULL)
5196 return dp;
5197 else
8bb15339 5198 return get_valid_dis386 (dp, info);
b844680a
L		 5199}
5200
e396998b 5201static int
26ca5450 5202print_insn (bfd_vma pc, disassemble_info *info)
252b5132 5203{
2da11e11 5204 const struct dis386 *dp;
252b5132 5205 int i;
ce518a5f 5206 char *op_txt[MAX_OPERANDS];
252b5132 5207 int needcomma;
e396998b
AM		 5208 int sizeflag;
5209 const char *p;
252b5132 5210 struct dis_private priv;
eec0f4ca 5211 unsigned char op;
b844680a
L		 5212 char prefix_obuf[32];
5213 char *prefix_obufp;
252b5132 5214
cb712a9e
L		 5215 if (info->mach == bfd_mach_x86_64_intel_syntax
5216 || info->mach == bfd_mach_x86_64)
5217 address_mode = mode_64bit;
5218 else
5219 address_mode = mode_32bit;
52b15da3 5220
8373f971 5221 if (intel_syntax == (char) -1)
e396998b
AM		 5222 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
5223 || info->mach == bfd_mach_x86_64_intel_syntax);
5224
2da11e11 5225 if (info->mach == bfd_mach_i386_i386
52b15da3
JH		 5226 || info->mach == bfd_mach_x86_64
5227 || info->mach == bfd_mach_i386_i386_intel_syntax
5228 || info->mach == bfd_mach_x86_64_intel_syntax)
e396998b 5229 priv.orig_sizeflag = AFLAG | DFLAG;
2da11e11 5230 else if (info->mach == bfd_mach_i386_i8086)
e396998b 5231 priv.orig_sizeflag = 0;
2da11e11
AM		 5232 else
5233 abort ();
e396998b
AM		 5234
5235 for (p = info->disassembler_options; p != NULL; )
5236 {
0112cd26 5237 if (CONST_STRNEQ (p, "x86-64"))
e396998b 5238 {
cb712a9e 5239 address_mode = mode_64bit;
e396998b
AM		 5240 priv.orig_sizeflag = AFLAG | DFLAG;
5241 }
0112cd26 5242 else if (CONST_STRNEQ (p, "i386"))
e396998b 5243 {
cb712a9e 5244 address_mode = mode_32bit;
e396998b
AM		 5245 priv.orig_sizeflag = AFLAG | DFLAG;
5246 }
0112cd26 5247 else if (CONST_STRNEQ (p, "i8086"))
e396998b 5248 {
cb712a9e 5249 address_mode = mode_16bit;
e396998b
AM		 5250 priv.orig_sizeflag = 0;
5251 }
0112cd26 5252 else if (CONST_STRNEQ (p, "intel"))
e396998b
AM		 5253 {
5254 intel_syntax = 1;
9d141669
L		 5255 if (CONST_STRNEQ (p + 5, "-mnemonic"))
5256 intel_mnemonic = 1;
e396998b 5257 }
0112cd26 5258 else if (CONST_STRNEQ (p, "att"))
e396998b
AM		 5259 {
5260 intel_syntax = 0;
9d141669
L		 5261 if (CONST_STRNEQ (p + 3, "-mnemonic"))
5262 intel_mnemonic = 0;
e396998b 5263 }
0112cd26 5264 else if (CONST_STRNEQ (p, "addr"))
e396998b 5265 {
f59a29b9
L		 5266 if (address_mode == mode_64bit)
5267 {
5268 if (p[4] == '3' && p[5] == '2')
5269 priv.orig_sizeflag &= ~AFLAG;
5270 else if (p[4] == '6' && p[5] == '4')
5271 priv.orig_sizeflag |= AFLAG;
5272 }
5273 else
5274 {
5275 if (p[4] == '1' && p[5] == '6')
5276 priv.orig_sizeflag &= ~AFLAG;
5277 else if (p[4] == '3' && p[5] == '2')
5278 priv.orig_sizeflag |= AFLAG;
5279 }
e396998b 5280 }
0112cd26 5281 else if (CONST_STRNEQ (p, "data"))
e396998b
AM		 5282 {
5283 if (p[4] == '1' && p[5] == '6')
5284 priv.orig_sizeflag &= ~DFLAG;
5285 else if (p[4] == '3' && p[5] == '2')
5286 priv.orig_sizeflag |= DFLAG;
5287 }
0112cd26 5288 else if (CONST_STRNEQ (p, "suffix"))
e396998b
AM		 5289 priv.orig_sizeflag |= SUFFIX_ALWAYS;
5290
5291 p = strchr (p, ',');
5292 if (p != NULL)
5293 p++;
5294 }
5295
5296 if (intel_syntax)
5297 {
5298 names64 = intel_names64;
5299 names32 = intel_names32;
5300 names16 = intel_names16;
5301 names8 = intel_names8;
5302 names8rex = intel_names8rex;
5303 names_seg = intel_names_seg;
db51cc60
L		 5304 index64 = intel_index64;
5305 index32 = intel_index32;
e396998b
AM		 5306 index16 = intel_index16;
5307 open_char = '[';
5308 close_char = ']';
5309 separator_char = '+';
5310 scale_char = '*';
5311 }
5312 else
5313 {
5314 names64 = att_names64;
5315 names32 = att_names32;
5316 names16 = att_names16;
5317 names8 = att_names8;
5318 names8rex = att_names8rex;
5319 names_seg = att_names_seg;
db51cc60
L		 5320 index64 = att_index64;
5321 index32 = att_index32;
e396998b
AM		 5322 index16 = att_index16;
5323 open_char = '(';
5324 close_char = ')';
5325 separator_char = ',';
5326 scale_char = ',';
5327 }
2da11e11 5328
4fe53c98 5329 /* The output looks better if we put 7 bytes on a line, since that
c608c12e 5330 puts most long word instructions on a single line. */
4fe53c98 5331 info->bytes_per_line = 7;
252b5132 5332
26ca5450 5333 info->private_data = &priv;
252b5132
RH		 5334 priv.max_fetched = priv.the_buffer;
5335 priv.insn_start = pc;
252b5132
RH		 5336
5337 obuf[0] = 0;
ce518a5f
L		 5338 for (i = 0; i < MAX_OPERANDS; ++i)
5339 {
5340 op_out[i][0] = 0;
5341 op_index[i] = -1;
5342 }
252b5132
RH		 5343
5344 the_info = info;
5345 start_pc = pc;
e396998b
AM		 5346 start_codep = priv.the_buffer;
5347 codep = priv.the_buffer;
252b5132 5348
5076851f
ILT		 5349 if (setjmp (priv.bailout) != 0)
5350 {
7d421014
ILT		 5351 const char *name;
5352
5076851f 5353 /* Getting here means we tried for data but didn't get it. That
e396998b
AM		 5354 means we have an incomplete instruction of some sort. Just
5355 print the first byte as a prefix or a .byte pseudo-op. */
5356 if (codep > priv.the_buffer)
5076851f 5357 {
e396998b 5358 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 5359 if (name != NULL)
5360 (*info->fprintf_func) (info->stream, "%s", name);
5361 else
5076851f 5362 {
7d421014
ILT		 5363 /* Just print the first byte as a .byte instruction. */
5364 (*info->fprintf_func) (info->stream, ".byte 0x%x",
e396998b 5365 (unsigned int) priv.the_buffer[0]);
5076851f 5366 }
5076851f 5367
7d421014 5368 return 1;
5076851f
ILT		 5369 }
5370
5371 return -1;
5372 }
5373
52b15da3 5374 obufp = obuf;
252b5132
RH		 5375 ckprefix ();
5376
5377 insn_codep = codep;
e396998b 5378 sizeflag = priv.orig_sizeflag;
252b5132
RH		 5379
5380 FETCH_DATA (info, codep + 1);
5381 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
5382
3e7d61b2
AM		 5383 if (((prefixes & PREFIX_FWAIT)
5384 && ((*codep < 0xd8) || (*codep > 0xdf)))
5385 || (rex && rex_used))
252b5132 5386 {
7d421014
ILT		 5387 const char *name;
5388
3e7d61b2
AM		 5389 /* fwait not followed by floating point instruction, or rex followed
5390 by other prefixes. Print the first prefix. */
e396998b 5391 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 5392 if (name == NULL)
5393 name = INTERNAL_DISASSEMBLER_ERROR;
5394 (*info->fprintf_func) (info->stream, "%s", name);
5395 return 1;
252b5132
RH		 5396 }
5397
eec0f4ca 5398 op = 0;
252b5132
RH		 5399 if (*codep == 0x0f)
5400 {
eec0f4ca 5401 unsigned char threebyte;
252b5132 5402 FETCH_DATA (info, codep + 2);
eec0f4ca
L		 5403 threebyte = *++codep;
5404 dp = &dis386_twobyte[threebyte];
252b5132 5405 need_modrm = twobyte_has_modrm[*codep];
eec0f4ca 5406 codep++;
252b5132
RH		 5407 }
5408 else
5409 {
6439fc28 5410 dp = &dis386[*codep];
252b5132 5411 need_modrm = onebyte_has_modrm[*codep];
eec0f4ca 5412 codep++;
252b5132 5413 }
246c51aa 5414
b844680a 5415 if ((prefixes & PREFIX_REPZ))
7d421014 5416 {
b844680a 5417 repz_prefix = "repz ";
7d421014
ILT		 5418 used_prefixes |= PREFIX_REPZ;
5419 }
b844680a
L		 5420 else
5421 repz_prefix = NULL;
5422
5423 if ((prefixes & PREFIX_REPNZ))
7d421014 5424 {
b844680a 5425 repnz_prefix = "repnz ";
7d421014
ILT		 5426 used_prefixes |= PREFIX_REPNZ;
5427 }
b844680a
L		 5428 else
5429 repnz_prefix = NULL;
050dfa73 5430
b844680a 5431 if ((prefixes & PREFIX_LOCK))
7d421014 5432 {
b844680a 5433 lock_prefix = "lock ";
7d421014
ILT		 5434 used_prefixes |= PREFIX_LOCK;
5435 }
b844680a
L		 5436 else
5437 lock_prefix = NULL;
c608c12e 5438
b844680a 5439 addr_prefix = NULL;
c608c12e
AM		 5440 if (prefixes & PREFIX_ADDR)
5441 {
5442 sizeflag ^= AFLAG;
ce518a5f 5443 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
3ffd33cf 5444 {
cb712a9e 5445 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
b844680a 5446 addr_prefix = "addr32 ";
3ffd33cf 5447 else
b844680a 5448 addr_prefix = "addr16 ";
3ffd33cf
AM		 5449 used_prefixes |= PREFIX_ADDR;
5450 }
5451 }
5452
b844680a
L		 5453 data_prefix = NULL;
5454 if ((prefixes & PREFIX_DATA))
3ffd33cf
AM		 5455 {
5456 sizeflag ^= DFLAG;
ce518a5f
L		 5457 if (dp->op[2].bytemode == cond_jump_mode
5458 && dp->op[0].bytemode == v_mode
6439fc28 5459 && !intel_syntax)
3ffd33cf
AM		 5460 {
5461 if (sizeflag & DFLAG)
b844680a 5462 data_prefix = "data32 ";
3ffd33cf 5463 else
b844680a 5464 data_prefix = "data16 ";
3ffd33cf
AM		 5465 used_prefixes |= PREFIX_DATA;
5466 }
5467 }
5468
8bb15339 5469 if (need_modrm)
252b5132
RH		 5470 {
5471 FETCH_DATA (info, codep + 1);
7967e09e
L		 5472 modrm.mod = (*codep >> 6) & 3;
5473 modrm.reg = (*codep >> 3) & 7;
5474 modrm.rm = *codep & 7;
252b5132
RH		 5475 }
5476
ce518a5f 5477 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
252b5132
RH		 5478 {
5479 dofloat (sizeflag);
5480 }
5481 else
5482 {
8bb15339 5483 dp = get_valid_dis386 (dp, info);
b844680a 5484 if (dp != NULL && putop (dp->name, sizeflag) == 0)
ce518a5f
L		 5485 {
5486 for (i = 0; i < MAX_OPERANDS; ++i)
5487 {
246c51aa 5488 obufp = op_out[i];
ce518a5f
L		 5489 op_ad = MAX_OPERANDS - 1 - i;
5490 if (dp->op[i].rtn)
5491 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
5492 }
6439fc28 5493 }
252b5132
RH		 5494 }
5495
7d421014
ILT		 5496 /* See if any prefixes were not used. If so, print the first one
5497 separately. If we don't do this, we'll wind up printing an
5498 instruction stream which does not precisely correspond to the
5499 bytes we are disassembling. */
5500 if ((prefixes & ~used_prefixes) != 0)
5501 {
5502 const char *name;
5503
e396998b 5504 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 5505 if (name == NULL)
5506 name = INTERNAL_DISASSEMBLER_ERROR;
5507 (*info->fprintf_func) (info->stream, "%s", name);
5508 return 1;
5509 }
52b15da3
JH		 5510 if (rex & ~rex_used)
5511 {
5512 const char *name;
e396998b 5513 name = prefix_name (rex | 0x40, priv.orig_sizeflag);
52b15da3
JH		 5514 if (name == NULL)
5515 name = INTERNAL_DISASSEMBLER_ERROR;
5516 (*info->fprintf_func) (info->stream, "%s ", name);
5517 }
7d421014 5518
b844680a
L		 5519 prefix_obuf[0] = 0;
5520 prefix_obufp = prefix_obuf;
5521 if (lock_prefix)
5522 prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
5523 if (repz_prefix)
5524 prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
5525 if (repnz_prefix)
5526 prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
5527 if (addr_prefix)
5528 prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
5529 if (data_prefix)
5530 prefix_obufp = stpcpy (prefix_obufp, data_prefix);
5531
5532 if (prefix_obuf[0] != 0)
5533 (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
5534
252b5132 5535 obufp = obuf + strlen (obuf);
b844680a 5536 for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
252b5132
RH		 5537 oappend (" ");
5538 oappend (" ");
5539 (*info->fprintf_func) (info->stream, "%s", obuf);
5540
5541 /* The enter and bound instructions are printed with operands in the same
5542 order as the intel book; everything else is printed in reverse order. */
2da11e11 5543 if (intel_syntax || two_source_ops)
252b5132 5544 {
185b1163
L		 5545 bfd_vma riprel;
5546
ce518a5f
L		 5547 for (i = 0; i < MAX_OPERANDS; ++i)
5548 op_txt[i] = op_out[i];
246c51aa 5549
ce518a5f
L		 5550 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
5551 {
5552 op_ad = op_index[i];
5553 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
5554 op_index[MAX_OPERANDS - 1 - i] = op_ad;
185b1163
L		 5555 riprel = op_riprel[i];
5556 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
5557 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
ce518a5f 5558 }
252b5132
RH		 5559 }
5560 else
5561 {
ce518a5f
L		 5562 for (i = 0; i < MAX_OPERANDS; ++i)
5563 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
050dfa73
MM		 5564 }
5565
ce518a5f
L		 5566 needcomma = 0;
5567 for (i = 0; i < MAX_OPERANDS; ++i)
5568 if (*op_txt[i])
5569 {
5570 if (needcomma)
5571 (*info->fprintf_func) (info->stream, ",");
5572 if (op_index[i] != -1 && !op_riprel[i])
5573 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
5574 else
5575 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
5576 needcomma = 1;
5577 }
050dfa73 5578
ce518a5f 5579 for (i = 0; i < MAX_OPERANDS; i++)
52b15da3
JH		 5580 if (op_index[i] != -1 && op_riprel[i])
5581 {
5582 (*info->fprintf_func) (info->stream, " # ");
5583 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
5584 + op_address[op_index[i]]), info);
185b1163 5585 break;
52b15da3 5586 }
e396998b 5587 return codep - priv.the_buffer;
252b5132
RH		 5588}
5589
6439fc28 5590static const char *float_mem[] = {
252b5132 5591 /* d8 */
7c52e0e8
L		 5592 "fadd{s|}",
5593 "fmul{s|}",
5594 "fcom{s|}",
5595 "fcomp{s|}",
5596 "fsub{s|}",
5597 "fsubr{s|}",
5598 "fdiv{s|}",
5599 "fdivr{s|}",
db6eb5be 5600 /* d9 */
7c52e0e8 5601 "fld{s|}",
252b5132 5602 "(bad)",
7c52e0e8
L		 5603 "fst{s|}",
5604 "fstp{s|}",
9306ca4a 5605 "fldenvIC",
252b5132 5606 "fldcw",
9306ca4a 5607 "fNstenvIC",
252b5132
RH		 5608 "fNstcw",
5609 /* da */
7c52e0e8
L		 5610 "fiadd{l|}",
5611 "fimul{l|}",
5612 "ficom{l|}",
5613 "ficomp{l|}",
5614 "fisub{l|}",
5615 "fisubr{l|}",
5616 "fidiv{l|}",
5617 "fidivr{l|}",
252b5132 5618 /* db */
7c52e0e8
L		 5619 "fild{l|}",
5620 "fisttp{l|}",
5621 "fist{l|}",
5622 "fistp{l|}",
252b5132 5623 "(bad)",
6439fc28 5624 "fld{t||t|}",
252b5132 5625 "(bad)",
6439fc28 5626 "fstp{t||t|}",
252b5132 5627 /* dc */
7c52e0e8
L		 5628 "fadd{l|}",
5629 "fmul{l|}",
5630 "fcom{l|}",
5631 "fcomp{l|}",
5632 "fsub{l|}",
5633 "fsubr{l|}",
5634 "fdiv{l|}",
5635 "fdivr{l|}",
252b5132 5636 /* dd */
7c52e0e8
L		 5637 "fld{l|}",
5638 "fisttp{ll|}",
5639 "fst{l||}",
5640 "fstp{l|}",
9306ca4a 5641 "frstorIC",
252b5132 5642 "(bad)",
9306ca4a 5643 "fNsaveIC",
252b5132
RH		 5644 "fNstsw",
5645 /* de */
5646 "fiadd",
5647 "fimul",
5648 "ficom",
5649 "ficomp",
5650 "fisub",
5651 "fisubr",
5652 "fidiv",
5653 "fidivr",
5654 /* df */
5655 "fild",
ca164297 5656 "fisttp",
252b5132
RH		 5657 "fist",
5658 "fistp",
5659 "fbld",
7c52e0e8 5660 "fild{ll|}",
252b5132 5661 "fbstp",
7c52e0e8 5662 "fistp{ll|}",
1d9f512f
AM		 5663};
5664
5665static const unsigned char float_mem_mode[] = {
5666 /* d8 */
5667 d_mode,
5668 d_mode,
5669 d_mode,
5670 d_mode,
5671 d_mode,
5672 d_mode,
5673 d_mode,
5674 d_mode,
5675 /* d9 */
5676 d_mode,
5677 0,
5678 d_mode,
5679 d_mode,
5680 0,
5681 w_mode,
5682 0,
5683 w_mode,
5684 /* da */
5685 d_mode,
5686 d_mode,
5687 d_mode,
5688 d_mode,
5689 d_mode,
5690 d_mode,
5691 d_mode,
5692 d_mode,
5693 /* db */
5694 d_mode,
5695 d_mode,
5696 d_mode,
5697 d_mode,
5698 0,
9306ca4a 5699 t_mode,
1d9f512f 5700 0,
9306ca4a 5701 t_mode,
1d9f512f
AM		 5702 /* dc */
5703 q_mode,
5704 q_mode,
5705 q_mode,
5706 q_mode,
5707 q_mode,
5708 q_mode,
5709 q_mode,
5710 q_mode,
5711 /* dd */
5712 q_mode,
5713 q_mode,
5714 q_mode,
5715 q_mode,
5716 0,
5717 0,
5718 0,
5719 w_mode,
5720 /* de */
5721 w_mode,
5722 w_mode,
5723 w_mode,
5724 w_mode,
5725 w_mode,
5726 w_mode,
5727 w_mode,
5728 w_mode,
5729 /* df */
5730 w_mode,
5731 w_mode,
5732 w_mode,
5733 w_mode,
9306ca4a 5734 t_mode,
1d9f512f 5735 q_mode,
9306ca4a 5736 t_mode,
1d9f512f 5737 q_mode
252b5132
RH		 5738};
5739
ce518a5f
L		 5740#define ST { OP_ST, 0 }
5741#define STi { OP_STi, 0 }
252b5132 5742
4efba78c
L		 5743#define FGRPd9_2 NULL, { { NULL, 0 } }
5744#define FGRPd9_4 NULL, { { NULL, 1 } }
5745#define FGRPd9_5 NULL, { { NULL, 2 } }
5746#define FGRPd9_6 NULL, { { NULL, 3 } }
5747#define FGRPd9_7 NULL, { { NULL, 4 } }
5748#define FGRPda_5 NULL, { { NULL, 5 } }
5749#define FGRPdb_4 NULL, { { NULL, 6 } }
5750#define FGRPde_3 NULL, { { NULL, 7 } }
5751#define FGRPdf_4 NULL, { { NULL, 8 } }
252b5132 5752
2da11e11 5753static const struct dis386 float_reg[][8] = {
252b5132
RH		 5754 /* d8 */
5755 {
ce518a5f
L		 5756 { "fadd", { ST, STi } },
5757 { "fmul", { ST, STi } },
5758 { "fcom", { STi } },
5759 { "fcomp", { STi } },
5760 { "fsub", { ST, STi } },
5761 { "fsubr", { ST, STi } },
5762 { "fdiv", { ST, STi } },
5763 { "fdivr", { ST, STi } },
252b5132
RH		 5764 },
5765 /* d9 */
5766 {
ce518a5f
L		 5767 { "fld", { STi } },
5768 { "fxch", { STi } },
252b5132 5769 { FGRPd9_2 },
ce518a5f 5770 { "(bad)", { XX } },
252b5132
RH		 5771 { FGRPd9_4 },
5772 { FGRPd9_5 },
5773 { FGRPd9_6 },
5774 { FGRPd9_7 },
5775 },
5776 /* da */
5777 {
ce518a5f
L		 5778 { "fcmovb", { ST, STi } },
5779 { "fcmove", { ST, STi } },
5780 { "fcmovbe",{ ST, STi } },
5781 { "fcmovu", { ST, STi } },
5782 { "(bad)", { XX } },
252b5132 5783 { FGRPda_5 },
ce518a5f
L		 5784 { "(bad)", { XX } },
5785 { "(bad)", { XX } },
252b5132
RH		 5786 },
5787 /* db */
5788 {
ce518a5f
L		 5789 { "fcmovnb",{ ST, STi } },
5790 { "fcmovne",{ ST, STi } },
5791 { "fcmovnbe",{ ST, STi } },
5792 { "fcmovnu",{ ST, STi } },
252b5132 5793 { FGRPdb_4 },
ce518a5f
L		 5794 { "fucomi", { ST, STi } },
5795 { "fcomi", { ST, STi } },
5796 { "(bad)", { XX } },
252b5132
RH		 5797 },
5798 /* dc */
5799 {
ce518a5f
L		 5800 { "fadd", { STi, ST } },
5801 { "fmul", { STi, ST } },
5802 { "(bad)", { XX } },
5803 { "(bad)", { XX } },
9d141669
L		 5804 { "fsub!M", { STi, ST } },
5805 { "fsubM", { STi, ST } },
5806 { "fdiv!M", { STi, ST } },
5807 { "fdivM", { STi, ST } },
252b5132
RH		 5808 },
5809 /* dd */
5810 {
ce518a5f
L		 5811 { "ffree", { STi } },
5812 { "(bad)", { XX } },
5813 { "fst", { STi } },
5814 { "fstp", { STi } },
5815 { "fucom", { STi } },
5816 { "fucomp", { STi } },
5817 { "(bad)", { XX } },
5818 { "(bad)", { XX } },
252b5132
RH		 5819 },
5820 /* de */
5821 {
ce518a5f
L		 5822 { "faddp", { STi, ST } },
5823 { "fmulp", { STi, ST } },
5824 { "(bad)", { XX } },
252b5132 5825 { FGRPde_3 },
9d141669
L		 5826 { "fsub!Mp", { STi, ST } },
5827 { "fsubMp", { STi, ST } },
5828 { "fdiv!Mp", { STi, ST } },
5829 { "fdivMp", { STi, ST } },
252b5132
RH		 5830 },
5831 /* df */
5832 {
ce518a5f
L		 5833 { "ffreep", { STi } },
5834 { "(bad)", { XX } },
5835 { "(bad)", { XX } },
5836 { "(bad)", { XX } },
252b5132 5837 { FGRPdf_4 },
ce518a5f
L		 5838 { "fucomip", { ST, STi } },
5839 { "fcomip", { ST, STi } },
5840 { "(bad)", { XX } },
252b5132
RH		 5841 },
5842};
5843
252b5132
RH		 5844static char *fgrps[][8] = {
5845 /* d9_2 0 */
5846 {
5847 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5848 },
5849
5850 /* d9_4 1 */
5851 {
5852 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
5853 },
5854
5855 /* d9_5 2 */
5856 {
5857 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
5858 },
5859
5860 /* d9_6 3 */
5861 {
5862 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
5863 },
5864
5865 /* d9_7 4 */
5866 {
5867 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
5868 },
5869
5870 /* da_5 5 */
5871 {
5872 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5873 },
5874
5875 /* db_4 6 */
5876 {
5877 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
5878 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
5879 },
5880
5881 /* de_3 7 */
5882 {
5883 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5884 },
5885
5886 /* df_4 8 */
5887 {
5888 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5889 },
5890};
5891
b844680a
L		 5892static void
5893OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
5894 int sizeflag ATTRIBUTE_UNUSED)
5895{
5896 /* Skip mod/rm byte. */
5897 MODRM_CHECK;
5898 codep++;
5899}
5900
252b5132 5901static void
26ca5450 5902dofloat (int sizeflag)
252b5132 5903{
2da11e11 5904 const struct dis386 *dp;
252b5132
RH		 5905 unsigned char floatop;
5906
5907 floatop = codep[-1];
5908
7967e09e 5909 if (modrm.mod != 3)
252b5132 5910 {
7967e09e 5911 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
1d9f512f
AM		 5912
5913 putop (float_mem[fp_indx], sizeflag);
ce518a5f 5914 obufp = op_out[0];
6e50d963 5915 op_ad = 2;
1d9f512f 5916 OP_E (float_mem_mode[fp_indx], sizeflag);
252b5132
RH		 5917 return;
5918 }
6608db57 5919 /* Skip mod/rm byte. */
4bba6815 5920 MODRM_CHECK;
252b5132
RH		 5921 codep++;
5922
7967e09e 5923 dp = &float_reg[floatop - 0xd8][modrm.reg];
252b5132
RH		 5924 if (dp->name == NULL)
5925 {
7967e09e 5926 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
252b5132 5927
6608db57 5928 /* Instruction fnstsw is only one with strange arg. */
252b5132 5929 if (floatop == 0xdf && codep[-1] == 0xe0)
ce518a5f 5930 strcpy (op_out[0], names16[0]);
252b5132
RH		 5931 }
5932 else
5933 {
5934 putop (dp->name, sizeflag);
5935
ce518a5f 5936 obufp = op_out[0];
6e50d963 5937 op_ad = 2;
ce518a5f
L		 5938 if (dp->op[0].rtn)
5939 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
6e50d963 5940
ce518a5f 5941 obufp = op_out[1];
6e50d963 5942 op_ad = 1;
ce518a5f
L		 5943 if (dp->op[1].rtn)
5944 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
252b5132
RH		 5945 }
5946}
5947
252b5132 5948static void
26ca5450 5949OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 5950{
422673a9 5951 oappend ("%st" + intel_syntax);
252b5132
RH		 5952}
5953
252b5132 5954static void
26ca5450 5955OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 5956{
7967e09e 5957 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
d708bcba 5958 oappend (scratchbuf + intel_syntax);
252b5132
RH		 5959}
5960
6608db57 5961/* Capital letters in template are macros. */
6439fc28 5962static int
26ca5450 5963putop (const char *template, int sizeflag)
252b5132 5964{
2da11e11 5965 const char *p;
9306ca4a 5966 int alt = 0;
9d141669 5967 int cond = 1;
252b5132
RH		 5968
5969 for (p = template; *p; p++)
5970 {
5971 switch (*p)
5972 {
5973 default:
5974 *obufp++ = *p;
5975 break;
9d141669
L		 5976 case '!':
5977 cond = 0;
5978 break;
6439fc28
AM		 5979 case '{':
5980 alt = 0;
5981 if (intel_syntax)
6439fc28
AM		 5982 {
5983 while (*++p != '|')
7c52e0e8
L		 5984 if (*p == '}' || *p == '\0')
5985 abort ();
6439fc28 5986 }
9306ca4a
JB		 5987 /* Fall through. */
5988 case 'I':
5989 alt = 1;
5990 continue;
6439fc28
AM		 5991 case '|':
5992 while (*++p != '}')
5993 {
5994 if (*p == '\0')
5995 abort ();
5996 }
5997 break;
5998 case '}':
5999 break;
252b5132 6000 case 'A':
db6eb5be
AM		 6001 if (intel_syntax)
6002 break;
7967e09e 6003 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
252b5132
RH		 6004 *obufp++ = 'b';
6005 break;
6006 case 'B':
db6eb5be
AM		 6007 if (intel_syntax)
6008 break;
252b5132
RH		 6009 if (sizeflag & SUFFIX_ALWAYS)
6010 *obufp++ = 'b';
252b5132 6011 break;
9306ca4a
JB		 6012 case 'C':
6013 if (intel_syntax && !alt)
6014 break;
6015 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
6016 {
6017 if (sizeflag & DFLAG)
6018 *obufp++ = intel_syntax ? 'd' : 'l';
6019 else
6020 *obufp++ = intel_syntax ? 'w' : 's';
6021 used_prefixes |= (prefixes & PREFIX_DATA);
6022 }
6023 break;
ed7841b3
JB		 6024 case 'D':
6025 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
6026 break;
161a04f6 6027 USED_REX (REX_W);
7967e09e 6028 if (modrm.mod == 3)
ed7841b3 6029 {
161a04f6 6030 if (rex & REX_W)
ed7841b3
JB		 6031 *obufp++ = 'q';
6032 else if (sizeflag & DFLAG)
6033 *obufp++ = intel_syntax ? 'd' : 'l';
6034 else
6035 *obufp++ = 'w';
6036 used_prefixes |= (prefixes & PREFIX_DATA);
6037 }
6038 else
6039 *obufp++ = 'w';
6040 break;
252b5132 6041 case 'E': /* For jcxz/jecxz */
cb712a9e 6042 if (address_mode == mode_64bit)
c1a64871
JH		 6043 {
6044 if (sizeflag & AFLAG)
6045 *obufp++ = 'r';
6046 else
6047 *obufp++ = 'e';
6048 }
6049 else
6050 if (sizeflag & AFLAG)
6051 *obufp++ = 'e';
3ffd33cf
AM		 6052 used_prefixes |= (prefixes & PREFIX_ADDR);
6053 break;
6054 case 'F':
db6eb5be
AM		 6055 if (intel_syntax)
6056 break;
e396998b 6057 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
3ffd33cf
AM		 6058 {
6059 if (sizeflag & AFLAG)
cb712a9e 6060 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
3ffd33cf 6061 else
cb712a9e 6062 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
3ffd33cf
AM		 6063 used_prefixes |= (prefixes & PREFIX_ADDR);
6064 }
252b5132 6065 break;
52fd6d94
JB		 6066 case 'G':
6067 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
6068 break;
161a04f6 6069 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 6070 *obufp++ = 'l';
6071 else
6072 *obufp++ = 'w';
161a04f6 6073 if (!(rex & REX_W))
52fd6d94
JB		 6074 used_prefixes |= (prefixes & PREFIX_DATA);
6075 break;
5dd0794d 6076 case 'H':
db6eb5be
AM		 6077 if (intel_syntax)
6078 break;
5dd0794d
AM		 6079 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
6080 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
6081 {
6082 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
6083 *obufp++ = ',';
6084 *obufp++ = 'p';
6085 if (prefixes & PREFIX_DS)
6086 *obufp++ = 't';
6087 else
6088 *obufp++ = 'n';
6089 }
6090 break;
9306ca4a
JB		 6091 case 'J':
6092 if (intel_syntax)
6093 break;
6094 *obufp++ = 'l';
6095 break;
42903f7f
L		 6096 case 'K':
6097 USED_REX (REX_W);
6098 if (rex & REX_W)
6099 *obufp++ = 'q';
6100 else
6101 *obufp++ = 'd';
6102 break;
6dd5059a
L		 6103 case 'Z':
6104 if (intel_syntax)
6105 break;
6106 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
6107 {
6108 *obufp++ = 'q';
6109 break;
6110 }
6111 /* Fall through. */
252b5132 6112 case 'L':
db6eb5be
AM		 6113 if (intel_syntax)
6114 break;
252b5132
RH		 6115 if (sizeflag & SUFFIX_ALWAYS)
6116 *obufp++ = 'l';
252b5132 6117 break;
9d141669
L		 6118 case 'M':
6119 if (intel_mnemonic != cond)
6120 *obufp++ = 'r';
6121 break;
252b5132
RH		 6122 case 'N':
6123 if ((prefixes & PREFIX_FWAIT) == 0)
6124 *obufp++ = 'n';
7d421014
ILT		 6125 else
6126 used_prefixes |= PREFIX_FWAIT;
252b5132 6127 break;
52b15da3 6128 case 'O':
161a04f6
L		 6129 USED_REX (REX_W);
6130 if (rex & REX_W)
6439fc28 6131 *obufp++ = 'o';
a35ca55a
JB		 6132 else if (intel_syntax && (sizeflag & DFLAG))
6133 *obufp++ = 'q';
52b15da3
JH		 6134 else
6135 *obufp++ = 'd';
161a04f6 6136 if (!(rex & REX_W))
a35ca55a 6137 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 6138 break;
6439fc28 6139 case 'T':
db6eb5be
AM		 6140 if (intel_syntax)
6141 break;
cb712a9e 6142 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 6143 {
6144 *obufp++ = 'q';
6145 break;
6146 }
6608db57 6147 /* Fall through. */
252b5132 6148 case 'P':
db6eb5be
AM		 6149 if (intel_syntax)
6150 break;
252b5132 6151 if ((prefixes & PREFIX_DATA)
161a04f6 6152 || (rex & REX_W)
e396998b 6153 || (sizeflag & SUFFIX_ALWAYS))
252b5132 6154 {
161a04f6
L		 6155 USED_REX (REX_W);
6156 if (rex & REX_W)
52b15da3 6157 *obufp++ = 'q';
c2419411 6158 else
52b15da3
JH		 6159 {
6160 if (sizeflag & DFLAG)
6161 *obufp++ = 'l';
6162 else
6163 *obufp++ = 'w';
52b15da3 6164 }
1a114b12 6165 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 6166 }
6167 break;
6439fc28 6168 case 'U':
db6eb5be
AM		 6169 if (intel_syntax)
6170 break;
cb712a9e 6171 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28 6172 {
7967e09e 6173 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
1a114b12 6174 *obufp++ = 'q';
6439fc28
AM		 6175 break;
6176 }
6608db57 6177 /* Fall through. */
252b5132 6178 case 'Q':
9306ca4a 6179 if (intel_syntax && !alt)
db6eb5be 6180 break;
161a04f6 6181 USED_REX (REX_W);
7967e09e 6182 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
252b5132 6183 {
161a04f6 6184 if (rex & REX_W)
52b15da3 6185 *obufp++ = 'q';
252b5132 6186 else
52b15da3
JH		 6187 {
6188 if (sizeflag & DFLAG)
9306ca4a 6189 *obufp++ = intel_syntax ? 'd' : 'l';
52b15da3
JH		 6190 else
6191 *obufp++ = 'w';
52b15da3 6192 }
1a114b12 6193 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 6194 }
6195 break;
6196 case 'R':
161a04f6
L		 6197 USED_REX (REX_W);
6198 if (rex & REX_W)
a35ca55a
JB		 6199 *obufp++ = 'q';
6200 else if (sizeflag & DFLAG)
c608c12e 6201 {
a35ca55a 6202 if (intel_syntax)
c608c12e 6203 *obufp++ = 'd';
c608c12e 6204 else
a35ca55a 6205 *obufp++ = 'l';
c608c12e 6206 }
252b5132 6207 else
a35ca55a
JB		 6208 *obufp++ = 'w';
6209 if (intel_syntax && !p[1]
161a04f6 6210 && ((rex & REX_W) || (sizeflag & DFLAG)))
a35ca55a 6211 *obufp++ = 'e';
161a04f6 6212 if (!(rex & REX_W))
52b15da3 6213 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6214 break;
1a114b12
JB		 6215 case 'V':
6216 if (intel_syntax)
6217 break;
cb712a9e 6218 if (address_mode == mode_64bit && (sizeflag & DFLAG))
1a114b12
JB		 6219 {
6220 if (sizeflag & SUFFIX_ALWAYS)
6221 *obufp++ = 'q';
6222 break;
6223 }
6224 /* Fall through. */
252b5132 6225 case 'S':
db6eb5be
AM		 6226 if (intel_syntax)
6227 break;
252b5132
RH		 6228 if (sizeflag & SUFFIX_ALWAYS)
6229 {
161a04f6 6230 if (rex & REX_W)
52b15da3 6231 *obufp++ = 'q';
252b5132 6232 else
52b15da3
JH		 6233 {
6234 if (sizeflag & DFLAG)
6235 *obufp++ = 'l';
6236 else
6237 *obufp++ = 'w';
6238 used_prefixes |= (prefixes & PREFIX_DATA);
6239 }
252b5132 6240 }
252b5132 6241 break;
041bd2e0
JH		 6242 case 'X':
6243 if (prefixes & PREFIX_DATA)
6244 *obufp++ = 'd';
6245 else
6246 *obufp++ = 's';
db6eb5be 6247 used_prefixes |= (prefixes & PREFIX_DATA);
041bd2e0 6248 break;
76f227a5 6249 case 'Y':
8a72226a 6250 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
db6eb5be 6251 break;
161a04f6 6252 if (rex & REX_W)
76f227a5 6253 {
161a04f6 6254 USED_REX (REX_W);
76f227a5
JH		 6255 *obufp++ = 'q';
6256 }
6257 break;
52b15da3 6258 /* implicit operand size 'l' for i386 or 'q' for x86-64 */
252b5132 6259 case 'W':
252b5132 6260 /* operand size flag for cwtl, cbtw */
161a04f6
L		 6261 USED_REX (REX_W);
6262 if (rex & REX_W)
a35ca55a
JB		 6263 {
6264 if (intel_syntax)
6265 *obufp++ = 'd';
6266 else
6267 *obufp++ = 'l';
6268 }
52b15da3 6269 else if (sizeflag & DFLAG)
252b5132
RH		 6270 *obufp++ = 'w';
6271 else
6272 *obufp++ = 'b';
161a04f6 6273 if (!(rex & REX_W))
52b15da3 6274 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 6275 break;
6276 }
9306ca4a 6277 alt = 0;
252b5132
RH		 6278 }
6279 *obufp = 0;
6439fc28 6280 return 0;
252b5132
RH		 6281}
6282
6283static void
26ca5450 6284oappend (const char *s)
252b5132
RH		 6285{
6286 strcpy (obufp, s);
6287 obufp += strlen (s);
6288}
6289
6290static void
26ca5450 6291append_seg (void)
252b5132
RH		 6292{
6293 if (prefixes & PREFIX_CS)
7d421014 6294 {
7d421014 6295 used_prefixes |= PREFIX_CS;
d708bcba 6296 oappend ("%cs:" + intel_syntax);
7d421014 6297 }
252b5132 6298 if (prefixes & PREFIX_DS)
7d421014 6299 {
7d421014 6300 used_prefixes |= PREFIX_DS;
d708bcba 6301 oappend ("%ds:" + intel_syntax);
7d421014 6302 }
252b5132 6303 if (prefixes & PREFIX_SS)
7d421014 6304 {
7d421014 6305 used_prefixes |= PREFIX_SS;
d708bcba 6306 oappend ("%ss:" + intel_syntax);
7d421014 6307 }
252b5132 6308 if (prefixes & PREFIX_ES)
7d421014 6309 {
7d421014 6310 used_prefixes |= PREFIX_ES;
d708bcba 6311 oappend ("%es:" + intel_syntax);
7d421014 6312 }
252b5132 6313 if (prefixes & PREFIX_FS)
7d421014 6314 {
7d421014 6315 used_prefixes |= PREFIX_FS;
d708bcba 6316 oappend ("%fs:" + intel_syntax);
7d421014 6317 }
252b5132 6318 if (prefixes & PREFIX_GS)
7d421014 6319 {
7d421014 6320 used_prefixes |= PREFIX_GS;
d708bcba 6321 oappend ("%gs:" + intel_syntax);
7d421014 6322 }
252b5132
RH		 6323}
6324
6325static void
26ca5450 6326OP_indirE (int bytemode, int sizeflag)
252b5132
RH		 6327{
6328 if (!intel_syntax)
6329 oappend ("*");
6330 OP_E (bytemode, sizeflag);
6331}
6332
52b15da3 6333static void
26ca5450 6334print_operand_value (char *buf, int hex, bfd_vma disp)
52b15da3 6335{
cb712a9e 6336 if (address_mode == mode_64bit)
52b15da3
JH		 6337 {
6338 if (hex)
6339 {
6340 char tmp[30];
6341 int i;
6342 buf[0] = '0';
6343 buf[1] = 'x';
6344 sprintf_vma (tmp, disp);
6608db57 6345 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
52b15da3
JH		 6346 strcpy (buf + 2, tmp + i);
6347 }
6348 else
6349 {
6350 bfd_signed_vma v = disp;
6351 char tmp[30];
6352 int i;
6353 if (v < 0)
6354 {
6355 *(buf++) = '-';
6356 v = -disp;
6608db57 6357 /* Check for possible overflow on 0x8000000000000000. */
52b15da3
JH		 6358 if (v < 0)
6359 {
6360 strcpy (buf, "9223372036854775808");
6361 return;
6362 }
6363 }
6364 if (!v)
6365 {
6366 strcpy (buf, "0");
6367 return;
6368 }
6369
6370 i = 0;
6371 tmp[29] = 0;
6372 while (v)
6373 {
6608db57 6374 tmp[28 - i] = (v % 10) + '0';
52b15da3
JH		 6375 v /= 10;
6376 i++;
6377 }
6378 strcpy (buf, tmp + 29 - i);
6379 }
6380 }
6381 else
6382 {
6383 if (hex)
6384 sprintf (buf, "0x%x", (unsigned int) disp);
6385 else
6386 sprintf (buf, "%d", (int) disp);
6387 }
6388}
6389
5d669648
L		 6390/* Put DISP in BUF as signed hex number. */
6391
6392static void
6393print_displacement (char *buf, bfd_vma disp)
6394{
6395 bfd_signed_vma val = disp;
6396 char tmp[30];
6397 int i, j = 0;
6398
6399 if (val < 0)
6400 {
6401 buf[j++] = '-';
6402 val = -disp;
6403
6404 /* Check for possible overflow. */
6405 if (val < 0)
6406 {
6407 switch (address_mode)
6408 {
6409 case mode_64bit:
6410 strcpy (buf + j, "0x8000000000000000");
6411 break;
6412 case mode_32bit:
6413 strcpy (buf + j, "0x80000000");
6414 break;
6415 case mode_16bit:
6416 strcpy (buf + j, "0x8000");
6417 break;
6418 }
6419 return;
6420 }
6421 }
6422
6423 buf[j++] = '0';
6424 buf[j++] = 'x';
6425
6426 sprintf_vma (tmp, val);
6427 for (i = 0; tmp[i] == '0'; i++)
6428 continue;
6429 if (tmp[i] == '\0')
6430 i--;
6431 strcpy (buf + j, tmp + i);
6432}
6433
3f31e633
JB		 6434static void
6435intel_operand_size (int bytemode, int sizeflag)
6436{
6437 switch (bytemode)
6438 {
6439 case b_mode:
42903f7f 6440 case dqb_mode:
3f31e633
JB		 6441 oappend ("BYTE PTR ");
6442 break;
6443 case w_mode:
6444 case dqw_mode:
6445 oappend ("WORD PTR ");
6446 break;
1a114b12 6447 case stack_v_mode:
cb712a9e 6448 if (address_mode == mode_64bit && (sizeflag & DFLAG))
3f31e633
JB		 6449 {
6450 oappend ("QWORD PTR ");
6451 used_prefixes |= (prefixes & PREFIX_DATA);
6452 break;
6453 }
6454 /* FALLTHRU */
6455 case v_mode:
6456 case dq_mode:
161a04f6
L		 6457 USED_REX (REX_W);
6458 if (rex & REX_W)
3f31e633
JB		 6459 oappend ("QWORD PTR ");
6460 else if ((sizeflag & DFLAG) || bytemode == dq_mode)
6461 oappend ("DWORD PTR ");
6462 else
6463 oappend ("WORD PTR ");
6464 used_prefixes |= (prefixes & PREFIX_DATA);
6465 break;
52fd6d94 6466 case z_mode:
161a04f6 6467 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 6468 *obufp++ = 'D';
6469 oappend ("WORD PTR ");
161a04f6 6470 if (!(rex & REX_W))
52fd6d94
JB		 6471 used_prefixes |= (prefixes & PREFIX_DATA);
6472 break;
3f31e633 6473 case d_mode:
42903f7f 6474 case dqd_mode:
3f31e633
JB		 6475 oappend ("DWORD PTR ");
6476 break;
6477 case q_mode:
6478 oappend ("QWORD PTR ");
6479 break;
6480 case m_mode:
cb712a9e 6481 if (address_mode == mode_64bit)
3f31e633
JB		 6482 oappend ("QWORD PTR ");
6483 else
6484 oappend ("DWORD PTR ");
6485 break;
6486 case f_mode:
6487 if (sizeflag & DFLAG)
6488 oappend ("FWORD PTR ");
6489 else
6490 oappend ("DWORD PTR ");
6491 used_prefixes |= (prefixes & PREFIX_DATA);
6492 break;
6493 case t_mode:
6494 oappend ("TBYTE PTR ");
6495 break;
6496 case x_mode:
6497 oappend ("XMMWORD PTR ");
6498 break;
fb9c77c7
L		 6499 case o_mode:
6500 oappend ("OWORD PTR ");
6501 break;
3f31e633
JB		 6502 default:
6503 break;
6504 }
6505}
6506
252b5132 6507static void
85f10a01 6508OP_E_extended (int bytemode, int sizeflag, int has_drex)
252b5132 6509{
52b15da3
JH		 6510 bfd_vma disp;
6511 int add = 0;
6512 int riprel = 0;
161a04f6
L		 6513 USED_REX (REX_B);
6514 if (rex & REX_B)
52b15da3 6515 add += 8;
252b5132 6516
6608db57 6517 /* Skip mod/rm byte. */
4bba6815 6518 MODRM_CHECK;
252b5132
RH		 6519 codep++;
6520
7967e09e 6521 if (modrm.mod == 3)
252b5132
RH		 6522 {
6523 switch (bytemode)
6524 {
6525 case b_mode:
52b15da3
JH		 6526 USED_REX (0);
6527 if (rex)
7967e09e 6528 oappend (names8rex[modrm.rm + add]);
52b15da3 6529 else
7967e09e 6530 oappend (names8[modrm.rm + add]);
252b5132
RH		 6531 break;
6532 case w_mode:
7967e09e 6533 oappend (names16[modrm.rm + add]);
252b5132 6534 break;
2da11e11 6535 case d_mode:
7967e09e 6536 oappend (names32[modrm.rm + add]);
52b15da3
JH		 6537 break;
6538 case q_mode:
7967e09e 6539 oappend (names64[modrm.rm + add]);
52b15da3
JH		 6540 break;
6541 case m_mode:
cb712a9e 6542 if (address_mode == mode_64bit)
7967e09e 6543 oappend (names64[modrm.rm + add]);
52b15da3 6544 else
7967e09e 6545 oappend (names32[modrm.rm + add]);
2da11e11 6546 break;
1a114b12 6547 case stack_v_mode:
cb712a9e 6548 if (address_mode == mode_64bit && (sizeflag & DFLAG))
003519a7 6549 {
7967e09e 6550 oappend (names64[modrm.rm + add]);
003519a7 6551 used_prefixes |= (prefixes & PREFIX_DATA);
1a114b12 6552 break;
003519a7 6553 }
1a114b12
JB		 6554 bytemode = v_mode;
6555 /* FALLTHRU */
252b5132 6556 case v_mode:
db6eb5be 6557 case dq_mode:
42903f7f
L		 6558 case dqb_mode:
6559 case dqd_mode:
9306ca4a 6560 case dqw_mode:
161a04f6
L		 6561 USED_REX (REX_W);
6562 if (rex & REX_W)
7967e09e 6563 oappend (names64[modrm.rm + add]);
9306ca4a 6564 else if ((sizeflag & DFLAG) || bytemode != v_mode)
7967e09e 6565 oappend (names32[modrm.rm + add]);
252b5132 6566 else
7967e09e 6567 oappend (names16[modrm.rm + add]);
7d421014 6568 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6569 break;
2da11e11 6570 case 0:
c608c12e 6571 break;
252b5132 6572 default:
c608c12e 6573 oappend (INTERNAL_DISASSEMBLER_ERROR);
252b5132
RH		 6574 break;
6575 }
6576 return;
6577 }
6578
6579 disp = 0;
3f31e633
JB		 6580 if (intel_syntax)
6581 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 6582 append_seg ();
6583
5d669648 6584 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132 6585 {
5d669648
L		 6586 /* 32/64 bit address mode */
6587 int havedisp;
252b5132
RH		 6588 int havesib;
6589 int havebase;
0f7da397 6590 int haveindex;
20afcfb7 6591 int needindex;
252b5132
RH		 6592 int base;
6593 int index = 0;
6594 int scale = 0;
6595
6596 havesib = 0;
6597 havebase = 1;
0f7da397 6598 haveindex = 0;
7967e09e 6599 base = modrm.rm;
252b5132
RH		 6600
6601 if (base == 4)
6602 {
6603 havesib = 1;
6604 FETCH_DATA (the_info, codep + 1);
252b5132 6605 index = (*codep >> 3) & 7;
db51cc60 6606 scale = (*codep >> 6) & 3;
252b5132 6607 base = *codep & 7;
161a04f6
L		 6608 USED_REX (REX_X);
6609 if (rex & REX_X)
52b15da3 6610 index += 8;
0f7da397 6611 haveindex = index != 4;
252b5132
RH		 6612 codep++;
6613 }
2888cb7a 6614 base += add;
252b5132 6615
85f10a01
MM		 6616 /* If we have a DREX byte, skip it now
6617 (it has already been handled) */
6618 if (has_drex)
6619 {
6620 FETCH_DATA (the_info, codep + 1);
6621 codep++;
6622 }
6623
7967e09e 6624 switch (modrm.mod)
252b5132
RH		 6625 {
6626 case 0:
52b15da3 6627 if ((base & 7) == 5)
252b5132
RH		 6628 {
6629 havebase = 0;
cb712a9e 6630 if (address_mode == mode_64bit && !havesib)
52b15da3
JH		 6631 riprel = 1;
6632 disp = get32s ();
252b5132
RH		 6633 }
6634 break;
6635 case 1:
6636 FETCH_DATA (the_info, codep + 1);
6637 disp = *codep++;
6638 if ((disp & 0x80) != 0)
6639 disp -= 0x100;
6640 break;
6641 case 2:
52b15da3 6642 disp = get32s ();
252b5132
RH		 6643 break;
6644 }
6645
20afcfb7
L		 6646 /* In 32bit mode, we need index register to tell [offset] from
6647 [eiz*1 + offset]. */
6648 needindex = (havesib
6649 && !havebase
6650 && !haveindex
6651 && address_mode == mode_32bit);
6652 havedisp = (havebase
6653 || needindex
6654 || (havesib && (haveindex || scale != 0)));
5d669648 6655
252b5132 6656 if (!intel_syntax)
7967e09e 6657 if (modrm.mod != 0 || (base & 7) == 5)
db6eb5be 6658 {
5d669648
L		 6659 if (havedisp || riprel)
6660 print_displacement (scratchbuf, disp);
6661 else
6662 print_operand_value (scratchbuf, 1, disp);
db6eb5be 6663 oappend (scratchbuf);
52b15da3
JH		 6664 if (riprel)
6665 {
6666 set_op (disp, 1);
87767711 6667 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
52b15da3 6668 }
db6eb5be 6669 }
2da11e11 6670
87767711
JB		 6671 if (havebase || haveindex || riprel)
6672 used_prefixes |= PREFIX_ADDR;
6673
5d669648 6674 if (havedisp || (intel_syntax && riprel))
252b5132 6675 {
252b5132 6676 *obufp++ = open_char;
52b15da3 6677 if (intel_syntax && riprel)
185b1163
L		 6678 {
6679 set_op (disp, 1);
87767711 6680 oappend (sizeflag & AFLAG ? "rip" : "eip");
185b1163 6681 }
db6eb5be 6682 *obufp = '\0';
252b5132 6683 if (havebase)
cb712a9e 6684 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
c1a64871 6685 ? names64[base] : names32[base]);
252b5132
RH		 6686 if (havesib)
6687 {
db51cc60
L		 6688 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
6689 print index to tell base + index from base. */
6690 if (scale != 0
20afcfb7 6691 || needindex
db51cc60
L		 6692 || haveindex
6693 || (havebase && base != ESP_REG_NUM))
252b5132 6694 {
9306ca4a 6695 if (!intel_syntax || havebase)
db6eb5be 6696 {
9306ca4a
JB		 6697 *obufp++ = separator_char;
6698 *obufp = '\0';
db6eb5be 6699 }
db51cc60
L		 6700 if (haveindex)
6701 oappend (address_mode == mode_64bit
6702 && (sizeflag & AFLAG)
6703 ? names64[index] : names32[index]);
6704 else
6705 oappend (address_mode == mode_64bit
6706 && (sizeflag & AFLAG)
6707 ? index64 : index32);
6708
db6eb5be
AM		 6709 *obufp++ = scale_char;
6710 *obufp = '\0';
6711 sprintf (scratchbuf, "%d", 1 << scale);
6712 oappend (scratchbuf);
6713 }
252b5132 6714 }
185b1163
L		 6715 if (intel_syntax
6716 && (disp || modrm.mod != 0 || (base & 7) == 5))
3d456fa1 6717 {
db51cc60 6718 if (!havedisp || (bfd_signed_vma) disp >= 0)
3d456fa1
JB		 6719 {
6720 *obufp++ = '+';
6721 *obufp = '\0';
6722 }
7967e09e 6723 else if (modrm.mod != 1)
3d456fa1
JB		 6724 {
6725 *obufp++ = '-';
6726 *obufp = '\0';
6727 disp = - (bfd_signed_vma) disp;
6728 }
6729
db51cc60
L		 6730 if (havedisp)
6731 print_displacement (scratchbuf, disp);
6732 else
6733 print_operand_value (scratchbuf, 1, disp);
3d456fa1
JB		 6734 oappend (scratchbuf);
6735 }
252b5132
RH		 6736
6737 *obufp++ = close_char;
db6eb5be 6738 *obufp = '\0';
252b5132
RH		 6739 }
6740 else if (intel_syntax)
db6eb5be 6741 {
7967e09e 6742 if (modrm.mod != 0 || (base & 7) == 5)
db6eb5be 6743 {
252b5132
RH		 6744 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
6745 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
6746 ;
6747 else
6748 {
d708bcba 6749 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 6750 oappend (":");
6751 }
52b15da3 6752 print_operand_value (scratchbuf, 1, disp);
db6eb5be
AM		 6753 oappend (scratchbuf);
6754 }
6755 }
252b5132
RH		 6756 }
6757 else
6758 { /* 16 bit address mode */
7967e09e 6759 switch (modrm.mod)
252b5132
RH		 6760 {
6761 case 0:
7967e09e 6762 if (modrm.rm == 6)
252b5132
RH		 6763 {
6764 disp = get16 ();
6765 if ((disp & 0x8000) != 0)
6766 disp -= 0x10000;
6767 }
6768 break;
6769 case 1:
6770 FETCH_DATA (the_info, codep + 1);
6771 disp = *codep++;
6772 if ((disp & 0x80) != 0)
6773 disp -= 0x100;
6774 break;
6775 case 2:
6776 disp = get16 ();
6777 if ((disp & 0x8000) != 0)
6778 disp -= 0x10000;
6779 break;
6780 }
6781
6782 if (!intel_syntax)
7967e09e 6783 if (modrm.mod != 0 || modrm.rm == 6)
db6eb5be 6784 {
5d669648 6785 print_displacement (scratchbuf, disp);
db6eb5be
AM		 6786 oappend (scratchbuf);
6787 }
252b5132 6788
7967e09e 6789 if (modrm.mod != 0 || modrm.rm != 6)
252b5132
RH		 6790 {
6791 *obufp++ = open_char;
db6eb5be 6792 *obufp = '\0';
7967e09e 6793 oappend (index16[modrm.rm]);
5d669648
L		 6794 if (intel_syntax
6795 && (disp || modrm.mod != 0 || modrm.rm == 6))
3d456fa1 6796 {
5d669648 6797 if ((bfd_signed_vma) disp >= 0)
3d456fa1
JB		 6798 {
6799 *obufp++ = '+';
6800 *obufp = '\0';
6801 }
7967e09e 6802 else if (modrm.mod != 1)
3d456fa1
JB		 6803 {
6804 *obufp++ = '-';
6805 *obufp = '\0';
6806 disp = - (bfd_signed_vma) disp;
6807 }
6808
5d669648 6809 print_displacement (scratchbuf, disp);
3d456fa1
JB		 6810 oappend (scratchbuf);
6811 }
6812
db6eb5be
AM		 6813 *obufp++ = close_char;
6814 *obufp = '\0';
252b5132 6815 }
3d456fa1
JB		 6816 else if (intel_syntax)
6817 {
6818 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
6819 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
6820 ;
6821 else
6822 {
6823 oappend (names_seg[ds_reg - es_reg]);
6824 oappend (":");
6825 }
6826 print_operand_value (scratchbuf, 1, disp & 0xffff);
6827 oappend (scratchbuf);
6828 }
252b5132
RH		 6829 }
6830}
6831
85f10a01
MM		 6832static void
6833OP_E (int bytemode, int sizeflag)
6834{
6835 OP_E_extended (bytemode, sizeflag, 0);
6836}
6837
6838
252b5132 6839static void
26ca5450 6840OP_G (int bytemode, int sizeflag)
252b5132 6841{
52b15da3 6842 int add = 0;
161a04f6
L		 6843 USED_REX (REX_R);
6844 if (rex & REX_R)
52b15da3 6845 add += 8;
252b5132
RH		 6846 switch (bytemode)
6847 {
6848 case b_mode:
52b15da3
JH		 6849 USED_REX (0);
6850 if (rex)
7967e09e 6851 oappend (names8rex[modrm.reg + add]);
52b15da3 6852 else
7967e09e 6853 oappend (names8[modrm.reg + add]);
252b5132
RH		 6854 break;
6855 case w_mode:
7967e09e 6856 oappend (names16[modrm.reg + add]);
252b5132
RH		 6857 break;
6858 case d_mode:
7967e09e 6859 oappend (names32[modrm.reg + add]);
52b15da3
JH		 6860 break;
6861 case q_mode:
7967e09e 6862 oappend (names64[modrm.reg + add]);
252b5132
RH		 6863 break;
6864 case v_mode:
9306ca4a 6865 case dq_mode:
42903f7f
L		 6866 case dqb_mode:
6867 case dqd_mode:
9306ca4a 6868 case dqw_mode:
161a04f6
L		 6869 USED_REX (REX_W);
6870 if (rex & REX_W)
7967e09e 6871 oappend (names64[modrm.reg + add]);
9306ca4a 6872 else if ((sizeflag & DFLAG) || bytemode != v_mode)
7967e09e 6873 oappend (names32[modrm.reg + add]);
252b5132 6874 else
7967e09e 6875 oappend (names16[modrm.reg + add]);
7d421014 6876 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6877 break;
90700ea2 6878 case m_mode:
cb712a9e 6879 if (address_mode == mode_64bit)
7967e09e 6880 oappend (names64[modrm.reg + add]);
90700ea2 6881 else
7967e09e 6882 oappend (names32[modrm.reg + add]);
90700ea2 6883 break;
252b5132
RH		 6884 default:
6885 oappend (INTERNAL_DISASSEMBLER_ERROR);
6886 break;
6887 }
6888}
6889
52b15da3 6890static bfd_vma
26ca5450 6891get64 (void)
52b15da3 6892{
5dd0794d 6893 bfd_vma x;
52b15da3 6894#ifdef BFD64
5dd0794d
AM		 6895 unsigned int a;
6896 unsigned int b;
6897
52b15da3
JH		 6898 FETCH_DATA (the_info, codep + 8);
6899 a = *codep++ & 0xff;
6900 a |= (*codep++ & 0xff) << 8;
6901 a |= (*codep++ & 0xff) << 16;
6902 a |= (*codep++ & 0xff) << 24;
5dd0794d 6903 b = *codep++ & 0xff;
52b15da3
JH		 6904 b |= (*codep++ & 0xff) << 8;
6905 b |= (*codep++ & 0xff) << 16;
6906 b |= (*codep++ & 0xff) << 24;
6907 x = a + ((bfd_vma) b << 32);
6908#else
6608db57 6909 abort ();
5dd0794d 6910 x = 0;
52b15da3
JH		 6911#endif
6912 return x;
6913}
6914
6915static bfd_signed_vma
26ca5450 6916get32 (void)
252b5132 6917{
52b15da3 6918 bfd_signed_vma x = 0;
252b5132
RH		 6919
6920 FETCH_DATA (the_info, codep + 4);
52b15da3
JH		 6921 x = *codep++ & (bfd_signed_vma) 0xff;
6922 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
6923 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
6924 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
6925 return x;
6926}
6927
6928static bfd_signed_vma
26ca5450 6929get32s (void)
52b15da3
JH		 6930{
6931 bfd_signed_vma x = 0;
6932
6933 FETCH_DATA (the_info, codep + 4);
6934 x = *codep++ & (bfd_signed_vma) 0xff;
6935 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
6936 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
6937 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
6938
6939 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
6940
252b5132
RH		 6941 return x;
6942}
6943
6944static int
26ca5450 6945get16 (void)
252b5132
RH		 6946{
6947 int x = 0;
6948
6949 FETCH_DATA (the_info, codep + 2);
6950 x = *codep++ & 0xff;
6951 x |= (*codep++ & 0xff) << 8;
6952 return x;
6953}
6954
6955static void
26ca5450 6956set_op (bfd_vma op, int riprel)
252b5132
RH		 6957{
6958 op_index[op_ad] = op_ad;
cb712a9e 6959 if (address_mode == mode_64bit)
7081ff04
AJ		 6960 {
6961 op_address[op_ad] = op;
6962 op_riprel[op_ad] = riprel;
6963 }
6964 else
6965 {
6966 /* Mask to get a 32-bit address. */
6967 op_address[op_ad] = op & 0xffffffff;
6968 op_riprel[op_ad] = riprel & 0xffffffff;
6969 }
252b5132
RH		 6970}
6971
6972static void
26ca5450 6973OP_REG (int code, int sizeflag)
252b5132 6974{
2da11e11 6975 const char *s;
9b60702d 6976 int add;
161a04f6
L		 6977 USED_REX (REX_B);
6978 if (rex & REX_B)
52b15da3 6979 add = 8;
9b60702d
L		 6980 else
6981 add = 0;
52b15da3
JH		 6982
6983 switch (code)
6984 {
52b15da3
JH		 6985 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
6986 case sp_reg: case bp_reg: case si_reg: case di_reg:
6987 s = names16[code - ax_reg + add];
6988 break;
6989 case es_reg: case ss_reg: case cs_reg:
6990 case ds_reg: case fs_reg: case gs_reg:
6991 s = names_seg[code - es_reg + add];
6992 break;
6993 case al_reg: case ah_reg: case cl_reg: case ch_reg:
6994 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
6995 USED_REX (0);
6996 if (rex)
6997 s = names8rex[code - al_reg + add];
6998 else
6999 s = names8[code - al_reg];
7000 break;
6439fc28
AM		 7001 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
7002 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
cb712a9e 7003 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 7004 {
7005 s = names64[code - rAX_reg + add];
7006 break;
7007 }
7008 code += eAX_reg - rAX_reg;
6608db57 7009 /* Fall through. */
52b15da3
JH		 7010 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
7011 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 7012 USED_REX (REX_W);
7013 if (rex & REX_W)
52b15da3
JH		 7014 s = names64[code - eAX_reg + add];
7015 else if (sizeflag & DFLAG)
7016 s = names32[code - eAX_reg + add];
7017 else
7018 s = names16[code - eAX_reg + add];
7019 used_prefixes |= (prefixes & PREFIX_DATA);
7020 break;
52b15da3
JH		 7021 default:
7022 s = INTERNAL_DISASSEMBLER_ERROR;
7023 break;
7024 }
7025 oappend (s);
7026}
7027
7028static void
26ca5450 7029OP_IMREG (int code, int sizeflag)
52b15da3
JH		 7030{
7031 const char *s;
252b5132
RH		 7032
7033 switch (code)
7034 {
7035 case indir_dx_reg:
d708bcba 7036 if (intel_syntax)
52fd6d94 7037 s = "dx";
d708bcba 7038 else
db6eb5be 7039 s = "(%dx)";
252b5132
RH		 7040 break;
7041 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
7042 case sp_reg: case bp_reg: case si_reg: case di_reg:
7043 s = names16[code - ax_reg];
7044 break;
7045 case es_reg: case ss_reg: case cs_reg:
7046 case ds_reg: case fs_reg: case gs_reg:
7047 s = names_seg[code - es_reg];
7048 break;
7049 case al_reg: case ah_reg: case cl_reg: case ch_reg:
7050 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
52b15da3
JH		 7051 USED_REX (0);
7052 if (rex)
7053 s = names8rex[code - al_reg];
7054 else
7055 s = names8[code - al_reg];
252b5132
RH		 7056 break;
7057 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
7058 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 7059 USED_REX (REX_W);
7060 if (rex & REX_W)
52b15da3
JH		 7061 s = names64[code - eAX_reg];
7062 else if (sizeflag & DFLAG)
252b5132
RH		 7063 s = names32[code - eAX_reg];
7064 else
7065 s = names16[code - eAX_reg];
7d421014 7066 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 7067 break;
52fd6d94 7068 case z_mode_ax_reg:
161a04f6 7069 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 7070 s = *names32;
7071 else
7072 s = *names16;
161a04f6 7073 if (!(rex & REX_W))
52fd6d94
JB		 7074 used_prefixes |= (prefixes & PREFIX_DATA);
7075 break;
252b5132
RH		 7076 default:
7077 s = INTERNAL_DISASSEMBLER_ERROR;
7078 break;
7079 }
7080 oappend (s);
7081}
7082
7083static void
26ca5450 7084OP_I (int bytemode, int sizeflag)
252b5132 7085{
52b15da3
JH		 7086 bfd_signed_vma op;
7087 bfd_signed_vma mask = -1;
252b5132
RH		 7088
7089 switch (bytemode)
7090 {
7091 case b_mode:
7092 FETCH_DATA (the_info, codep + 1);
52b15da3
JH		 7093 op = *codep++;
7094 mask = 0xff;
7095 break;
7096 case q_mode:
cb712a9e 7097 if (address_mode == mode_64bit)
6439fc28
AM		 7098 {
7099 op = get32s ();
7100 break;
7101 }
6608db57 7102 /* Fall through. */
252b5132 7103 case v_mode:
161a04f6
L		 7104 USED_REX (REX_W);
7105 if (rex & REX_W)
52b15da3
JH		 7106 op = get32s ();
7107 else if (sizeflag & DFLAG)
7108 {
7109 op = get32 ();
7110 mask = 0xffffffff;
7111 }
252b5132 7112 else
52b15da3
JH		 7113 {
7114 op = get16 ();
7115 mask = 0xfffff;
7116 }
7d421014 7117 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 7118 break;
7119 case w_mode:
52b15da3 7120 mask = 0xfffff;
252b5132
RH		 7121 op = get16 ();
7122 break;
9306ca4a
JB		 7123 case const_1_mode:
7124 if (intel_syntax)
7125 oappend ("1");
7126 return;
252b5132
RH		 7127 default:
7128 oappend (INTERNAL_DISASSEMBLER_ERROR);
7129 return;
7130 }
7131
52b15da3
JH		 7132 op &= mask;
7133 scratchbuf[0] = '$';
d708bcba
AM		 7134 print_operand_value (scratchbuf + 1, 1, op);
7135 oappend (scratchbuf + intel_syntax);
52b15da3
JH		 7136 scratchbuf[0] = '\0';
7137}
7138
7139static void
26ca5450 7140OP_I64 (int bytemode, int sizeflag)
52b15da3
JH		 7141{
7142 bfd_signed_vma op;
7143 bfd_signed_vma mask = -1;
7144
cb712a9e 7145 if (address_mode != mode_64bit)
6439fc28
AM		 7146 {
7147 OP_I (bytemode, sizeflag);
7148 return;
7149 }
7150
52b15da3
JH		 7151 switch (bytemode)
7152 {
7153 case b_mode:
7154 FETCH_DATA (the_info, codep + 1);
7155 op = *codep++;
7156 mask = 0xff;
7157 break;
7158 case v_mode:
161a04f6
L		 7159 USED_REX (REX_W);
7160 if (rex & REX_W)
52b15da3
JH		 7161 op = get64 ();
7162 else if (sizeflag & DFLAG)
7163 {
7164 op = get32 ();
7165 mask = 0xffffffff;
7166 }
7167 else
7168 {
7169 op = get16 ();
7170 mask = 0xfffff;
7171 }
7172 used_prefixes |= (prefixes & PREFIX_DATA);
7173 break;
7174 case w_mode:
7175 mask = 0xfffff;
7176 op = get16 ();
7177 break;
7178 default:
7179 oappend (INTERNAL_DISASSEMBLER_ERROR);
7180 return;
7181 }
7182
7183 op &= mask;
7184 scratchbuf[0] = '$';
d708bcba
AM		 7185 print_operand_value (scratchbuf + 1, 1, op);
7186 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7187 scratchbuf[0] = '\0';
7188}
7189
7190static void
26ca5450 7191OP_sI (int bytemode, int sizeflag)
252b5132 7192{
52b15da3
JH		 7193 bfd_signed_vma op;
7194 bfd_signed_vma mask = -1;
252b5132
RH		 7195
7196 switch (bytemode)
7197 {
7198 case b_mode:
7199 FETCH_DATA (the_info, codep + 1);
7200 op = *codep++;
7201 if ((op & 0x80) != 0)
7202 op -= 0x100;
52b15da3 7203 mask = 0xffffffff;
252b5132
RH		 7204 break;
7205 case v_mode:
161a04f6
L		 7206 USED_REX (REX_W);
7207 if (rex & REX_W)
52b15da3
JH		 7208 op = get32s ();
7209 else if (sizeflag & DFLAG)
7210 {
7211 op = get32s ();
7212 mask = 0xffffffff;
7213 }
252b5132
RH		 7214 else
7215 {
52b15da3 7216 mask = 0xffffffff;
6608db57 7217 op = get16 ();
252b5132
RH		 7218 if ((op & 0x8000) != 0)
7219 op -= 0x10000;
7220 }
7d421014 7221 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 7222 break;
7223 case w_mode:
7224 op = get16 ();
52b15da3 7225 mask = 0xffffffff;
252b5132
RH		 7226 if ((op & 0x8000) != 0)
7227 op -= 0x10000;
7228 break;
7229 default:
7230 oappend (INTERNAL_DISASSEMBLER_ERROR);
7231 return;
7232 }
52b15da3
JH		 7233
7234 scratchbuf[0] = '$';
7235 print_operand_value (scratchbuf + 1, 1, op);
d708bcba 7236 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7237}
7238
7239static void
26ca5450 7240OP_J (int bytemode, int sizeflag)
252b5132 7241{
52b15da3 7242 bfd_vma disp;
7081ff04 7243 bfd_vma mask = -1;
65ca155d 7244 bfd_vma segment = 0;
252b5132
RH		 7245
7246 switch (bytemode)
7247 {
7248 case b_mode:
7249 FETCH_DATA (the_info, codep + 1);
7250 disp = *codep++;
7251 if ((disp & 0x80) != 0)
7252 disp -= 0x100;
7253 break;
7254 case v_mode:
161a04f6 7255 if ((sizeflag & DFLAG) || (rex & REX_W))
52b15da3 7256 disp = get32s ();
252b5132
RH		 7257 else
7258 {
7259 disp = get16 ();
206717e8
L		 7260 if ((disp & 0x8000) != 0)
7261 disp -= 0x10000;
65ca155d
L		 7262 /* In 16bit mode, address is wrapped around at 64k within
7263 the same segment. Otherwise, a data16 prefix on a jump
7264 instruction means that the pc is masked to 16 bits after
7265 the displacement is added! */
7266 mask = 0xffff;
7267 if ((prefixes & PREFIX_DATA) == 0)
7268 segment = ((start_pc + codep - start_codep)
7269 & ~((bfd_vma) 0xffff));
252b5132 7270 }
d807a492 7271 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 7272 break;
7273 default:
7274 oappend (INTERNAL_DISASSEMBLER_ERROR);
7275 return;
7276 }
65ca155d 7277 disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
52b15da3
JH		 7278 set_op (disp, 0);
7279 print_operand_value (scratchbuf, 1, disp);
252b5132
RH		 7280 oappend (scratchbuf);
7281}
7282
252b5132 7283static void
ed7841b3 7284OP_SEG (int bytemode, int sizeflag)
252b5132 7285{
ed7841b3 7286 if (bytemode == w_mode)
7967e09e 7287 oappend (names_seg[modrm.reg]);
ed7841b3 7288 else
7967e09e 7289 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
252b5132
RH		 7290}
7291
7292static void
26ca5450 7293OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
252b5132
RH		 7294{
7295 int seg, offset;
7296
c608c12e 7297 if (sizeflag & DFLAG)
252b5132 7298 {
c608c12e
AM		 7299 offset = get32 ();
7300 seg = get16 ();
252b5132 7301 }
c608c12e
AM		 7302 else
7303 {
7304 offset = get16 ();
7305 seg = get16 ();
7306 }
7d421014 7307 used_prefixes |= (prefixes & PREFIX_DATA);
d708bcba 7308 if (intel_syntax)
3f31e633 7309 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
d708bcba
AM		 7310 else
7311 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
c608c12e 7312 oappend (scratchbuf);
252b5132
RH		 7313}
7314
252b5132 7315static void
3f31e633 7316OP_OFF (int bytemode, int sizeflag)
252b5132 7317{
52b15da3 7318 bfd_vma off;
252b5132 7319
3f31e633
JB		 7320 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
7321 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 7322 append_seg ();
7323
cb712a9e 7324 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132
RH		 7325 off = get32 ();
7326 else
7327 off = get16 ();
7328
7329 if (intel_syntax)
7330 {
7331 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 7332 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
252b5132 7333 {
d708bcba 7334 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 7335 oappend (":");
7336 }
7337 }
52b15da3
JH		 7338 print_operand_value (scratchbuf, 1, off);
7339 oappend (scratchbuf);
7340}
6439fc28 7341
52b15da3 7342static void
3f31e633 7343OP_OFF64 (int bytemode, int sizeflag)
52b15da3
JH		 7344{
7345 bfd_vma off;
7346
539e75ad
L		 7347 if (address_mode != mode_64bit
7348 || (prefixes & PREFIX_ADDR))
6439fc28
AM		 7349 {
7350 OP_OFF (bytemode, sizeflag);
7351 return;
7352 }
7353
3f31e633
JB		 7354 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
7355 intel_operand_size (bytemode, sizeflag);
52b15da3
JH		 7356 append_seg ();
7357
6608db57 7358 off = get64 ();
52b15da3
JH		 7359
7360 if (intel_syntax)
7361 {
7362 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 7363 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
52b15da3 7364 {
d708bcba 7365 oappend (names_seg[ds_reg - es_reg]);
52b15da3
JH		 7366 oappend (":");
7367 }
7368 }
7369 print_operand_value (scratchbuf, 1, off);
252b5132
RH		 7370 oappend (scratchbuf);
7371}
7372
7373static void
26ca5450 7374ptr_reg (int code, int sizeflag)
252b5132 7375{
2da11e11 7376 const char *s;
d708bcba 7377
1d9f512f 7378 *obufp++ = open_char;
20f0a1fc 7379 used_prefixes |= (prefixes & PREFIX_ADDR);
cb712a9e 7380 if (address_mode == mode_64bit)
c1a64871
JH		 7381 {
7382 if (!(sizeflag & AFLAG))
db6eb5be 7383 s = names32[code - eAX_reg];
c1a64871 7384 else
db6eb5be 7385 s = names64[code - eAX_reg];
c1a64871 7386 }
52b15da3 7387 else if (sizeflag & AFLAG)
252b5132
RH		 7388 s = names32[code - eAX_reg];
7389 else
7390 s = names16[code - eAX_reg];
7391 oappend (s);
1d9f512f
AM		 7392 *obufp++ = close_char;
7393 *obufp = 0;
252b5132
RH		 7394}
7395
7396static void
26ca5450 7397OP_ESreg (int code, int sizeflag)
252b5132 7398{
9306ca4a 7399 if (intel_syntax)
52fd6d94
JB		 7400 {
7401 switch (codep[-1])
7402 {
7403 case 0x6d: /* insw/insl */
7404 intel_operand_size (z_mode, sizeflag);
7405 break;
7406 case 0xa5: /* movsw/movsl/movsq */
7407 case 0xa7: /* cmpsw/cmpsl/cmpsq */
7408 case 0xab: /* stosw/stosl */
7409 case 0xaf: /* scasw/scasl */
7410 intel_operand_size (v_mode, sizeflag);
7411 break;
7412 default:
7413 intel_operand_size (b_mode, sizeflag);
7414 }
7415 }
d708bcba 7416 oappend ("%es:" + intel_syntax);
252b5132
RH		 7417 ptr_reg (code, sizeflag);
7418}
7419
7420static void
26ca5450 7421OP_DSreg (int code, int sizeflag)
252b5132 7422{
9306ca4a 7423 if (intel_syntax)
52fd6d94
JB		 7424 {
7425 switch (codep[-1])
7426 {
7427 case 0x6f: /* outsw/outsl */
7428 intel_operand_size (z_mode, sizeflag);
7429 break;
7430 case 0xa5: /* movsw/movsl/movsq */
7431 case 0xa7: /* cmpsw/cmpsl/cmpsq */
7432 case 0xad: /* lodsw/lodsl/lodsq */
7433 intel_operand_size (v_mode, sizeflag);
7434 break;
7435 default:
7436 intel_operand_size (b_mode, sizeflag);
7437 }
7438 }
252b5132
RH		 7439 if ((prefixes
7440 & (PREFIX_CS
7441 | PREFIX_DS
7442 | PREFIX_SS
7443 | PREFIX_ES
7444 | PREFIX_FS
7445 | PREFIX_GS)) == 0)
7446 prefixes |= PREFIX_DS;
6608db57 7447 append_seg ();
252b5132
RH		 7448 ptr_reg (code, sizeflag);
7449}
7450
252b5132 7451static void
26ca5450 7452OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7453{
9b60702d 7454 int add;
161a04f6 7455 if (rex & REX_R)
c4a530c5 7456 {
161a04f6 7457 USED_REX (REX_R);
c4a530c5
JB		 7458 add = 8;
7459 }
cb712a9e 7460 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
c4a530c5 7461 {
b844680a 7462 lock_prefix = NULL;
c4a530c5
JB		 7463 used_prefixes |= PREFIX_LOCK;
7464 add = 8;
7465 }
9b60702d
L		 7466 else
7467 add = 0;
7967e09e 7468 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
d708bcba 7469 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7470}
7471
252b5132 7472static void
26ca5450 7473OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7474{
9b60702d 7475 int add;
161a04f6
L		 7476 USED_REX (REX_R);
7477 if (rex & REX_R)
52b15da3 7478 add = 8;
9b60702d
L		 7479 else
7480 add = 0;
d708bcba 7481 if (intel_syntax)
7967e09e 7482 sprintf (scratchbuf, "db%d", modrm.reg + add);
d708bcba 7483 else
7967e09e 7484 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
252b5132
RH		 7485 oappend (scratchbuf);
7486}
7487
252b5132 7488static void
26ca5450 7489OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7490{
7967e09e 7491 sprintf (scratchbuf, "%%tr%d", modrm.reg);
d708bcba 7492 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7493}
7494
7495static void
6f74c397 7496OP_R (int bytemode, int sizeflag)
252b5132 7497{
7967e09e 7498 if (modrm.mod == 3)
2da11e11
AM		 7499 OP_E (bytemode, sizeflag);
7500 else
6608db57 7501 BadOp ();
252b5132
RH		 7502}
7503
7504static void
26ca5450 7505OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7506{
041bd2e0
JH		 7507 used_prefixes |= (prefixes & PREFIX_DATA);
7508 if (prefixes & PREFIX_DATA)
20f0a1fc 7509 {
9b60702d 7510 int add;
161a04f6
L		 7511 USED_REX (REX_R);
7512 if (rex & REX_R)
20f0a1fc 7513 add = 8;
9b60702d
L		 7514 else
7515 add = 0;
7967e09e 7516 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
20f0a1fc 7517 }
041bd2e0 7518 else
7967e09e 7519 sprintf (scratchbuf, "%%mm%d", modrm.reg);
d708bcba 7520 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7521}
7522
c608c12e 7523static void
26ca5450 7524OP_XMM (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e 7525{
9b60702d 7526 int add;
161a04f6
L		 7527 USED_REX (REX_R);
7528 if (rex & REX_R)
041bd2e0 7529 add = 8;
9b60702d
L		 7530 else
7531 add = 0;
7967e09e 7532 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
d708bcba 7533 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 7534}
7535
252b5132 7536static void
26ca5450 7537OP_EM (int bytemode, int sizeflag)
252b5132 7538{
7967e09e 7539 if (modrm.mod != 3)
252b5132 7540 {
9306ca4a
JB		 7541 if (intel_syntax && bytemode == v_mode)
7542 {
7543 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
7544 used_prefixes |= (prefixes & PREFIX_DATA);
7545 }
252b5132
RH		 7546 OP_E (bytemode, sizeflag);
7547 return;
7548 }
7549
6608db57 7550 /* Skip mod/rm byte. */
4bba6815 7551 MODRM_CHECK;
252b5132 7552 codep++;
041bd2e0
JH		 7553 used_prefixes |= (prefixes & PREFIX_DATA);
7554 if (prefixes & PREFIX_DATA)
20f0a1fc 7555 {
9b60702d 7556 int add;
20f0a1fc 7557
161a04f6
L		 7558 USED_REX (REX_B);
7559 if (rex & REX_B)
20f0a1fc 7560 add = 8;
9b60702d
L		 7561 else
7562 add = 0;
7967e09e 7563 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
20f0a1fc 7564 }
041bd2e0 7565 else
7967e09e 7566 sprintf (scratchbuf, "%%mm%d", modrm.rm);
d708bcba 7567 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7568}
7569
246c51aa
L		 7570/* cvt* are the only instructions in sse2 which have
7571 both SSE and MMX operands and also have 0x66 prefix
7572 in their opcode. 0x66 was originally used to differentiate
7573 between SSE and MMX instruction(operands). So we have to handle the
4d9567e0
MM		 7574 cvt* separately using OP_EMC and OP_MXC */
7575static void
7576OP_EMC (int bytemode, int sizeflag)
7577{
7967e09e 7578 if (modrm.mod != 3)
4d9567e0
MM		 7579 {
7580 if (intel_syntax && bytemode == v_mode)
7581 {
7582 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
7583 used_prefixes |= (prefixes & PREFIX_DATA);
7584 }
7585 OP_E (bytemode, sizeflag);
7586 return;
7587 }
246c51aa 7588
4d9567e0
MM		 7589 /* Skip mod/rm byte. */
7590 MODRM_CHECK;
7591 codep++;
7592 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 7593 sprintf (scratchbuf, "%%mm%d", modrm.rm);
4d9567e0
MM		 7594 oappend (scratchbuf + intel_syntax);
7595}
7596
7597static void
7598OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
7599{
7600 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 7601 sprintf (scratchbuf, "%%mm%d", modrm.reg);
4d9567e0
MM		 7602 oappend (scratchbuf + intel_syntax);
7603}
7604
c608c12e 7605static void
26ca5450 7606OP_EX (int bytemode, int sizeflag)
c608c12e 7607{
9b60702d 7608 int add;
7967e09e 7609 if (modrm.mod != 3)
c608c12e
AM		 7610 {
7611 OP_E (bytemode, sizeflag);
7612 return;
7613 }
161a04f6
L		 7614 USED_REX (REX_B);
7615 if (rex & REX_B)
041bd2e0 7616 add = 8;
9b60702d
L		 7617 else
7618 add = 0;
c608c12e 7619
6608db57 7620 /* Skip mod/rm byte. */
4bba6815 7621 MODRM_CHECK;
c608c12e 7622 codep++;
7967e09e 7623 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
d708bcba 7624 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 7625}
7626
252b5132 7627static void
26ca5450 7628OP_MS (int bytemode, int sizeflag)
252b5132 7629{
7967e09e 7630 if (modrm.mod == 3)
2da11e11
AM		 7631 OP_EM (bytemode, sizeflag);
7632 else
6608db57 7633 BadOp ();
252b5132
RH		 7634}
7635
992aaec9 7636static void
26ca5450 7637OP_XS (int bytemode, int sizeflag)
992aaec9 7638{
7967e09e 7639 if (modrm.mod == 3)
992aaec9
AM		 7640 OP_EX (bytemode, sizeflag);
7641 else
6608db57 7642 BadOp ();
992aaec9
AM		 7643}
7644
cc0ec051
AM		 7645static void
7646OP_M (int bytemode, int sizeflag)
7647{
7967e09e 7648 if (modrm.mod == 3)
75413a22
L		 7649 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
7650 BadOp ();
cc0ec051
AM		 7651 else
7652 OP_E (bytemode, sizeflag);
7653}
7654
7655static void
7656OP_0f07 (int bytemode, int sizeflag)
7657{
7967e09e 7658 if (modrm.mod != 3 || modrm.rm != 0)
cc0ec051
AM		 7659 BadOp ();
7660 else
7661 OP_E (bytemode, sizeflag);
7662}
7663
46e883c5 7664/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
246c51aa 7665 32bit mode and "xchg %rax,%rax" in 64bit mode. */
46e883c5 7666
cc0ec051 7667static void
46e883c5 7668NOP_Fixup1 (int bytemode, int sizeflag)
cc0ec051 7669{
8b38ad71
L		 7670 if ((prefixes & PREFIX_DATA) != 0
7671 || (rex != 0
7672 && rex != 0x48
7673 && address_mode == mode_64bit))
46e883c5
L		 7674 OP_REG (bytemode, sizeflag);
7675 else
7676 strcpy (obuf, "nop");
7677}
7678
7679static void
7680NOP_Fixup2 (int bytemode, int sizeflag)
7681{
8b38ad71
L		 7682 if ((prefixes & PREFIX_DATA) != 0
7683 || (rex != 0
7684 && rex != 0x48
7685 && address_mode == mode_64bit))
46e883c5 7686 OP_IMREG (bytemode, sizeflag);
cc0ec051
AM		 7687}
7688
84037f8c 7689static const char *const Suffix3DNow[] = {
252b5132
RH		 7690/* 00 */ NULL, NULL, NULL, NULL,
7691/* 04 */ NULL, NULL, NULL, NULL,
7692/* 08 */ NULL, NULL, NULL, NULL,
9e525108 7693/* 0C */ "pi2fw", "pi2fd", NULL, NULL,
252b5132
RH		 7694/* 10 */ NULL, NULL, NULL, NULL,
7695/* 14 */ NULL, NULL, NULL, NULL,
7696/* 18 */ NULL, NULL, NULL, NULL,
9e525108 7697/* 1C */ "pf2iw", "pf2id", NULL, NULL,
252b5132
RH		 7698/* 20 */ NULL, NULL, NULL, NULL,
7699/* 24 */ NULL, NULL, NULL, NULL,
7700/* 28 */ NULL, NULL, NULL, NULL,
7701/* 2C */ NULL, NULL, NULL, NULL,
7702/* 30 */ NULL, NULL, NULL, NULL,
7703/* 34 */ NULL, NULL, NULL, NULL,
7704/* 38 */ NULL, NULL, NULL, NULL,
7705/* 3C */ NULL, NULL, NULL, NULL,
7706/* 40 */ NULL, NULL, NULL, NULL,
7707/* 44 */ NULL, NULL, NULL, NULL,
7708/* 48 */ NULL, NULL, NULL, NULL,
7709/* 4C */ NULL, NULL, NULL, NULL,
7710/* 50 */ NULL, NULL, NULL, NULL,
7711/* 54 */ NULL, NULL, NULL, NULL,
7712/* 58 */ NULL, NULL, NULL, NULL,
7713/* 5C */ NULL, NULL, NULL, NULL,
7714/* 60 */ NULL, NULL, NULL, NULL,
7715/* 64 */ NULL, NULL, NULL, NULL,
7716/* 68 */ NULL, NULL, NULL, NULL,
7717/* 6C */ NULL, NULL, NULL, NULL,
7718/* 70 */ NULL, NULL, NULL, NULL,
7719/* 74 */ NULL, NULL, NULL, NULL,
7720/* 78 */ NULL, NULL, NULL, NULL,
7721/* 7C */ NULL, NULL, NULL, NULL,
7722/* 80 */ NULL, NULL, NULL, NULL,
7723/* 84 */ NULL, NULL, NULL, NULL,
9e525108
AM		 7724/* 88 */ NULL, NULL, "pfnacc", NULL,
7725/* 8C */ NULL, NULL, "pfpnacc", NULL,
252b5132
RH		 7726/* 90 */ "pfcmpge", NULL, NULL, NULL,
7727/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
7728/* 98 */ NULL, NULL, "pfsub", NULL,
7729/* 9C */ NULL, NULL, "pfadd", NULL,
7730/* A0 */ "pfcmpgt", NULL, NULL, NULL,
7731/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
7732/* A8 */ NULL, NULL, "pfsubr", NULL,
7733/* AC */ NULL, NULL, "pfacc", NULL,
7734/* B0 */ "pfcmpeq", NULL, NULL, NULL,
9beff690 7735/* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
9e525108 7736/* B8 */ NULL, NULL, NULL, "pswapd",
252b5132
RH		 7737/* BC */ NULL, NULL, NULL, "pavgusb",
7738/* C0 */ NULL, NULL, NULL, NULL,
7739/* C4 */ NULL, NULL, NULL, NULL,
7740/* C8 */ NULL, NULL, NULL, NULL,
7741/* CC */ NULL, NULL, NULL, NULL,
7742/* D0 */ NULL, NULL, NULL, NULL,
7743/* D4 */ NULL, NULL, NULL, NULL,
7744/* D8 */ NULL, NULL, NULL, NULL,
7745/* DC */ NULL, NULL, NULL, NULL,
7746/* E0 */ NULL, NULL, NULL, NULL,
7747/* E4 */ NULL, NULL, NULL, NULL,
7748/* E8 */ NULL, NULL, NULL, NULL,
7749/* EC */ NULL, NULL, NULL, NULL,
7750/* F0 */ NULL, NULL, NULL, NULL,
7751/* F4 */ NULL, NULL, NULL, NULL,
7752/* F8 */ NULL, NULL, NULL, NULL,
7753/* FC */ NULL, NULL, NULL, NULL,
7754};
7755
7756static void
26ca5450 7757OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132
RH		 7758{
7759 const char *mnemonic;
7760
7761 FETCH_DATA (the_info, codep + 1);
7762 /* AMD 3DNow! instructions are specified by an opcode suffix in the
7763 place where an 8-bit immediate would normally go. ie. the last
7764 byte of the instruction. */
6608db57 7765 obufp = obuf + strlen (obuf);
c608c12e 7766 mnemonic = Suffix3DNow[*codep++ & 0xff];
252b5132 7767 if (mnemonic)
2da11e11 7768 oappend (mnemonic);
252b5132
RH		 7769 else
7770 {
7771 /* Since a variable sized modrm/sib chunk is between the start
7772 of the opcode (0x0f0f) and the opcode suffix, we need to do
7773 all the modrm processing first, and don't know until now that
7774 we have a bad opcode. This necessitates some cleaning up. */
ce518a5f
L		 7775 op_out[0][0] = '\0';
7776 op_out[1][0] = '\0';
6608db57 7777 BadOp ();
252b5132
RH		 7778 }
7779}
c608c12e 7780
6608db57 7781static const char *simd_cmp_op[] = {
c608c12e
AM		 7782 "eq",
7783 "lt",
7784 "le",
7785 "unord",
7786 "neq",
7787 "nlt",
7788 "nle",
7789 "ord"
7790};
7791
7792static void
ad19981d 7793CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e
AM		 7794{
7795 unsigned int cmp_type;
7796
7797 FETCH_DATA (the_info, codep + 1);
7798 cmp_type = *codep++ & 0xff;
7799 if (cmp_type < 8)
7800 {
ad19981d
L		 7801 char suffix [3];
7802 char *p = obuf + strlen (obuf) - 2;
7803 suffix[0] = p[0];
7804 suffix[1] = p[1];
7805 suffix[2] = '\0';
7806 sprintf (p, "%s%s", simd_cmp_op[cmp_type], suffix);
c608c12e
AM		 7807 }
7808 else
7809 {
ad19981d
L		 7810 /* We have a reserved extension byte. Output it directly. */
7811 scratchbuf[0] = '$';
7812 print_operand_value (scratchbuf + 1, 1, cmp_type);
7813 oappend (scratchbuf + intel_syntax);
7814 scratchbuf[0] = '\0';
c608c12e
AM		 7815 }
7816}
7817
ca164297 7818static void
b844680a
L		 7819OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
7820 int sizeflag ATTRIBUTE_UNUSED)
7821{
7822 /* mwait %eax,%ecx */
7823 if (!intel_syntax)
7824 {
7825 const char **names = (address_mode == mode_64bit
7826 ? names64 : names32);
7827 strcpy (op_out[0], names[0]);
7828 strcpy (op_out[1], names[1]);
7829 two_source_ops = 1;
7830 }
7831 /* Skip mod/rm byte. */
7832 MODRM_CHECK;
7833 codep++;
7834}
7835
7836static void
7837OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
7838 int sizeflag ATTRIBUTE_UNUSED)
ca164297 7839{
b844680a
L		 7840 /* monitor %eax,%ecx,%edx" */
7841 if (!intel_syntax)
ca164297 7842 {
b844680a 7843 const char **op1_names;
cb712a9e
L		 7844 const char **names = (address_mode == mode_64bit
7845 ? names64 : names32);
1d9f512f 7846
b844680a
L		 7847 if (!(prefixes & PREFIX_ADDR))
7848 op1_names = (address_mode == mode_16bit
7849 ? names16 : names);
ca164297
L		 7850 else
7851 {
b844680a
L		 7852 /* Remove "addr16/addr32". */
7853 addr_prefix = NULL;
7854 op1_names = (address_mode != mode_32bit
7855 ? names32 : names16);
7856 used_prefixes |= PREFIX_ADDR;
ca164297 7857 }
b844680a
L		 7858 strcpy (op_out[0], op1_names[0]);
7859 strcpy (op_out[1], names[1]);
7860 strcpy (op_out[2], names[2]);
7861 two_source_ops = 1;
ca164297 7862 }
b844680a
L		 7863 /* Skip mod/rm byte. */
7864 MODRM_CHECK;
7865 codep++;
30123838
JB		 7866}
7867
6608db57
KH		 7868static void
7869BadOp (void)
2da11e11 7870{
6608db57
KH		 7871 /* Throw away prefixes and 1st. opcode byte. */
7872 codep = insn_codep + 1;
2da11e11
AM		 7873 oappend ("(bad)");
7874}
4cc91dba 7875
35c52694
L		 7876static void
7877REP_Fixup (int bytemode, int sizeflag)
7878{
7879 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
7880 lods and stos. */
35c52694 7881 if (prefixes & PREFIX_REPZ)
b844680a 7882 repz_prefix = "rep ";
35c52694
L		 7883
7884 switch (bytemode)
7885 {
7886 case al_reg:
7887 case eAX_reg:
7888 case indir_dx_reg:
7889 OP_IMREG (bytemode, sizeflag);
7890 break;
7891 case eDI_reg:
7892 OP_ESreg (bytemode, sizeflag);
7893 break;
7894 case eSI_reg:
7895 OP_DSreg (bytemode, sizeflag);
7896 break;
7897 default:
7898 abort ();
7899 break;
7900 }
7901}
f5804c90
L		 7902
7903static void
7904CMPXCHG8B_Fixup (int bytemode, int sizeflag)
7905{
161a04f6
L		 7906 USED_REX (REX_W);
7907 if (rex & REX_W)
f5804c90
L		 7908 {
7909 /* Change cmpxchg8b to cmpxchg16b. */
7910 char *p = obuf + strlen (obuf) - 2;
7911 strcpy (p, "16b");
fb9c77c7 7912 bytemode = o_mode;
f5804c90
L		 7913 }
7914 OP_M (bytemode, sizeflag);
7915}
42903f7f
L		 7916
7917static void
7918XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
7919{
7920 sprintf (scratchbuf, "%%xmm%d", reg);
7921 oappend (scratchbuf + intel_syntax);
7922}
381d071f
L		 7923
7924static void
7925CRC32_Fixup (int bytemode, int sizeflag)
7926{
7927 /* Add proper suffix to "crc32". */
7928 char *p = obuf + strlen (obuf);
7929
7930 switch (bytemode)
7931 {
7932 case b_mode:
20592a94
L		 7933 if (intel_syntax)
7934 break;
7935
381d071f
L		 7936 *p++ = 'b';
7937 break;
7938 case v_mode:
20592a94
L		 7939 if (intel_syntax)
7940 break;
7941
381d071f
L		 7942 USED_REX (REX_W);
7943 if (rex & REX_W)
7944 *p++ = 'q';
9344ff29 7945 else if (sizeflag & DFLAG)
20592a94 7946 *p++ = 'l';
381d071f 7947 else
9344ff29
L		 7948 *p++ = 'w';
7949 used_prefixes |= (prefixes & PREFIX_DATA);
381d071f
L		 7950 break;
7951 default:
7952 oappend (INTERNAL_DISASSEMBLER_ERROR);
7953 break;
7954 }
7955 *p = '\0';
7956
7957 if (modrm.mod == 3)
7958 {
7959 int add;
7960
7961 /* Skip mod/rm byte. */
7962 MODRM_CHECK;
7963 codep++;
7964
7965 USED_REX (REX_B);
7966 add = (rex & REX_B) ? 8 : 0;
7967 if (bytemode == b_mode)
7968 {
7969 USED_REX (0);
7970 if (rex)
7971 oappend (names8rex[modrm.rm + add]);
7972 else
7973 oappend (names8[modrm.rm + add]);
7974 }
7975 else
7976 {
7977 USED_REX (REX_W);
7978 if (rex & REX_W)
7979 oappend (names64[modrm.rm + add]);
7980 else if ((prefixes & PREFIX_DATA))
7981 oappend (names16[modrm.rm + add]);
7982 else
7983 oappend (names32[modrm.rm + add]);
7984 }
7985 }
7986 else
9344ff29 7987 OP_E (bytemode, sizeflag);
381d071f 7988}
85f10a01
MM		 7989
7990/* Print a DREX argument as either a register or memory operation. */
7991static void
7992print_drex_arg (unsigned int reg, int bytemode, int sizeflag)
7993{
7994 if (reg == DREX_REG_UNKNOWN)
7995 BadOp ();
7996
7997 else if (reg != DREX_REG_MEMORY)
7998 {
7999 sprintf (scratchbuf, "%%xmm%d", reg);
8000 oappend (scratchbuf + intel_syntax);
8001 }
8002
8003 else
8004 OP_E_extended (bytemode, sizeflag, 1);
8005}
8006
8007/* SSE5 instructions that have 4 arguments are encoded as:
8008 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>.
8009
8010 The <sub-opcode> byte has 1 bit (0x4) that is combined with 1 bit in
8011 the DREX field (0x8) to determine how the arguments are laid out.
8012 The destination register must be the same register as one of the
8013 inputs, and it is encoded in the DREX byte. No REX prefix is used
8014 for these instructions, since the DREX field contains the 3 extension
8015 bits provided by the REX prefix.
8016
8017 The bytemode argument adds 2 extra bits for passing extra information:
8018 DREX_OC1 -- Set the OC1 bit to indicate dest == 1st arg
8019 DREX_NO_OC0 -- OC0 in DREX is invalid
8020 (but pretend it is set). */
8021
8022static void
8023OP_DREX4 (int flag_bytemode, int sizeflag)
8024{
8025 unsigned int drex_byte;
8026 unsigned int regs[4];
8027 unsigned int modrm_regmem;
8028 unsigned int modrm_reg;
8029 unsigned int drex_reg;
8030 int bytemode;
8031 int rex_save = rex;
8032 int rex_used_save = rex_used;
8033 int has_sib = 0;
8034 int oc1 = (flag_bytemode & DREX_OC1) ? 2 : 0;
8035 int oc0;
8036 int i;
8037
8038 bytemode = flag_bytemode & ~ DREX_MASK;
8039
8040 for (i = 0; i < 4; i++)
8041 regs[i] = DREX_REG_UNKNOWN;
8042
8043 /* Determine if we have a SIB byte in addition to MODRM before the
8044 DREX byte. */
8045 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
8046 && (modrm.mod != 3)
8047 && (modrm.rm == 4))
8048 has_sib = 1;
8049
8050 /* Get the DREX byte. */
8051 FETCH_DATA (the_info, codep + 2 + has_sib);
8052 drex_byte = codep[has_sib+1];
8053 drex_reg = DREX_XMM (drex_byte);
8054 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
8055
8056 /* Is OC0 legal? If not, hardwire oc0 == 1. */
8057 if (flag_bytemode & DREX_NO_OC0)
8058 {
8059 oc0 = 1;
8060 if (DREX_OC0 (drex_byte))
8061 BadOp ();
8062 }
8063 else
8064 oc0 = DREX_OC0 (drex_byte);
8065
8066 if (modrm.mod == 3)
8067 {
8068 /* regmem == register */
8069 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
8070 rex = rex_used = 0;
8071 /* skip modrm/drex since we don't call OP_E_extended */
8072 codep += 2;
8073 }
8074 else
8075 {
8076 /* regmem == memory, fill in appropriate REX bits */
8077 modrm_regmem = DREX_REG_MEMORY;
8078 rex = drex_byte & (REX_B | REX_X | REX_R);
8079 if (rex)
8080 rex |= REX_OPCODE;
8081 rex_used = rex;
8082 }
8083
8084 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
8085 order. */
8086 switch (oc0 + oc1)
8087 {
8088 default:
8089 BadOp ();
8090 return;
8091
8092 case 0:
8093 regs[0] = modrm_regmem;
8094 regs[1] = modrm_reg;
8095 regs[2] = drex_reg;
8096 regs[3] = drex_reg;
8097 break;
8098
8099 case 1:
8100 regs[0] = modrm_reg;
8101 regs[1] = modrm_regmem;
8102 regs[2] = drex_reg;
8103 regs[3] = drex_reg;
8104 break;
8105
8106 case 2:
8107 regs[0] = drex_reg;
8108 regs[1] = modrm_regmem;
8109 regs[2] = modrm_reg;
8110 regs[3] = drex_reg;
8111 break;
8112
8113 case 3:
8114 regs[0] = drex_reg;
8115 regs[1] = modrm_reg;
8116 regs[2] = modrm_regmem;
8117 regs[3] = drex_reg;
8118 break;
8119 }
8120
8121 /* Print out the arguments. */
8122 for (i = 0; i < 4; i++)
8123 {
8124 int j = (intel_syntax) ? 3 - i : i;
8125 if (i > 0)
8126 {
8127 *obufp++ = ',';
8128 *obufp = '\0';
8129 }
8130
8131 print_drex_arg (regs[j], bytemode, sizeflag);
8132 }
8133
8134 rex = rex_save;
8135 rex_used = rex_used_save;
8136}
8137
8138/* SSE5 instructions that have 3 arguments, and are encoded as:
8139 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset> (or)
8140 0f 25 <sub-opcode> <modrm> <optional-sib> <drex> <offset> <cmp-byte>
8141
8142 The DREX field has 1 bit (0x8) to determine how the arguments are
8143 laid out. The destination register is encoded in the DREX byte.
8144 No REX prefix is used for these instructions, since the DREX field
8145 contains the 3 extension bits provided by the REX prefix. */
8146
8147static void
8148OP_DREX3 (int flag_bytemode, int sizeflag)
8149{
8150 unsigned int drex_byte;
8151 unsigned int regs[3];
8152 unsigned int modrm_regmem;
8153 unsigned int modrm_reg;
8154 unsigned int drex_reg;
8155 int bytemode;
8156 int rex_save = rex;
8157 int rex_used_save = rex_used;
8158 int has_sib = 0;
8159 int oc0;
8160 int i;
8161
8162 bytemode = flag_bytemode & ~ DREX_MASK;
8163
8164 for (i = 0; i < 3; i++)
8165 regs[i] = DREX_REG_UNKNOWN;
8166
8167 /* Determine if we have a SIB byte in addition to MODRM before the
8168 DREX byte. */
8169 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
8170 && (modrm.mod != 3)
8171 && (modrm.rm == 4))
8172 has_sib = 1;
8173
8174 /* Get the DREX byte. */
8175 FETCH_DATA (the_info, codep + 2 + has_sib);
8176 drex_byte = codep[has_sib+1];
8177 drex_reg = DREX_XMM (drex_byte);
8178 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
8179
8180 /* Is OC0 legal? If not, hardwire oc0 == 0 */
8181 oc0 = DREX_OC0 (drex_byte);
8182 if ((flag_bytemode & DREX_NO_OC0) && oc0)
8183 BadOp ();
8184
8185 if (modrm.mod == 3)
8186 {
8187 /* regmem == register */
8188 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
8189 rex = rex_used = 0;
8190 /* skip modrm/drex since we don't call OP_E_extended. */
8191 codep += 2;
8192 }
8193 else
8194 {
8195 /* regmem == memory, fill in appropriate REX bits. */
8196 modrm_regmem = DREX_REG_MEMORY;
8197 rex = drex_byte & (REX_B | REX_X | REX_R);
8198 if (rex)
8199 rex |= REX_OPCODE;
8200 rex_used = rex;
8201 }
8202
8203 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
8204 order. */
8205 switch (oc0)
8206 {
8207 default:
8208 BadOp ();
8209 return;
8210
8211 case 0:
8212 regs[0] = modrm_regmem;
8213 regs[1] = modrm_reg;
8214 regs[2] = drex_reg;
8215 break;
8216
8217 case 1:
8218 regs[0] = modrm_reg;
8219 regs[1] = modrm_regmem;
8220 regs[2] = drex_reg;
8221 break;
8222 }
8223
8224 /* Print out the arguments. */
8225 for (i = 0; i < 3; i++)
8226 {
8227 int j = (intel_syntax) ? 2 - i : i;
8228 if (i > 0)
8229 {
8230 *obufp++ = ',';
8231 *obufp = '\0';
8232 }
8233
8234 print_drex_arg (regs[j], bytemode, sizeflag);
8235 }
8236
8237 rex = rex_save;
8238 rex_used = rex_used_save;
8239}
8240
8241/* Emit a floating point comparison for comp<xx> instructions. */
8242
8243static void
8244OP_DREX_FCMP (int bytemode ATTRIBUTE_UNUSED,
8245 int sizeflag ATTRIBUTE_UNUSED)
8246{
8247 unsigned char byte;
8248
8249 static const char *const cmp_test[] = {
8250 "eq",
8251 "lt",
8252 "le",
8253 "unord",
8254 "ne",
8255 "nlt",
8256 "nle",
8257 "ord",
8258 "ueq",
8259 "ult",
8260 "ule",
8261 "false",
8262 "une",
8263 "unlt",
8264 "unle",
8265 "true"
8266 };
8267
8268 FETCH_DATA (the_info, codep + 1);
8269 byte = *codep & 0xff;
8270
8271 if (byte >= ARRAY_SIZE (cmp_test)
8272 || obuf[0] != 'c'
8273 || obuf[1] != 'o'
8274 || obuf[2] != 'm')
8275 {
8276 /* The instruction isn't one we know about, so just append the
8277 extension byte as a numeric value. */
8278 OP_I (b_mode, 0);
8279 }
8280
8281 else
8282 {
8283 sprintf (scratchbuf, "com%s%s", cmp_test[byte], obuf+3);
8284 strcpy (obuf, scratchbuf);
8285 codep++;
8286 }
8287}
8288
8289/* Emit an integer point comparison for pcom<xx> instructions,
8290 rewriting the instruction to have the test inside of it. */
8291
8292static void
8293OP_DREX_ICMP (int bytemode ATTRIBUTE_UNUSED,
8294 int sizeflag ATTRIBUTE_UNUSED)
8295{
8296 unsigned char byte;
8297
8298 static const char *const cmp_test[] = {
8299 "lt",
8300 "le",
8301 "gt",
8302 "ge",
8303 "eq",
8304 "ne",
8305 "false",
8306 "true"
8307 };
8308
8309 FETCH_DATA (the_info, codep + 1);
8310 byte = *codep & 0xff;
8311
8312 if (byte >= ARRAY_SIZE (cmp_test)
8313 || obuf[0] != 'p'
8314 || obuf[1] != 'c'
8315 || obuf[2] != 'o'
8316 || obuf[3] != 'm')
8317 {
8318 /* The instruction isn't one we know about, so just print the
8319 comparison test byte as a numeric value. */
8320 OP_I (b_mode, 0);
8321 }
8322
8323 else
8324 {
8325 sprintf (scratchbuf, "pcom%s%s", cmp_test[byte], obuf+4);
8326 strcpy (obuf, scratchbuf);
8327 codep++;
8328 }
8329}
GDB Binutils - Deliverables
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