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[deliverable/binutils-gdb.git] / opcodes / i386-dis.c
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252b5132 1/* Print i386 instructions for GDB, the GNU debugger.
060d22b0 2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
9b201bb5 3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
252b5132 4
9b201bb5 5 This file is part of the GNU opcodes library.
20f0a1fc 6
9b201bb5 7 This library is free software; you can redistribute it and/or modify
20f0a1fc 8 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
20f0a1fc 11
9b201bb5
NC		 12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
20f0a1fc
NC		 16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
9b201bb5
NC		 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
20f0a1fc
NC		 22
23/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 July 1988
25 modified by John Hassey (hassey@dg-rtp.dg.com)
26 x86-64 support added by Jan Hubicka (jh@suse.cz)
27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28
29/* The main tables describing the instructions is essentially a copy
30 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
31 Programmers Manual. Usually, there is a capital letter, followed
32 by a small letter. The capital letter tell the addressing mode,
33 and the small letter tells about the operand size. Refer to
34 the Intel manual for details. */
252b5132 35
252b5132 36#include "sysdep.h"
dabbade6 37#include "dis-asm.h"
252b5132 38#include "opintl.h"
0b1cf022 39#include "opcode/i386.h"
85f10a01 40#include "libiberty.h"
252b5132
RH		 41
42#include <setjmp.h>
43
26ca5450
AJ		 44static int fetch_data (struct disassemble_info *, bfd_byte *);
45static void ckprefix (void);
46static const char *prefix_name (int, int);
47static int print_insn (bfd_vma, disassemble_info *);
48static void dofloat (int);
49static void OP_ST (int, int);
50static void OP_STi (int, int);
51static int putop (const char *, int);
52static void oappend (const char *);
53static void append_seg (void);
54static void OP_indirE (int, int);
55static void print_operand_value (char *, int, bfd_vma);
85f10a01 56static void OP_E_extended (int, int, int);
5d669648 57static void print_displacement (char *, bfd_vma);
26ca5450
AJ		 58static void OP_E (int, int);
59static void OP_G (int, int);
60static bfd_vma get64 (void);
61static bfd_signed_vma get32 (void);
62static bfd_signed_vma get32s (void);
63static int get16 (void);
64static void set_op (bfd_vma, int);
b844680a 65static void OP_Skip_MODRM (int, int);
26ca5450
AJ		 66static void OP_REG (int, int);
67static void OP_IMREG (int, int);
68static void OP_I (int, int);
69static void OP_I64 (int, int);
70static void OP_sI (int, int);
71static void OP_J (int, int);
72static void OP_SEG (int, int);
73static void OP_DIR (int, int);
74static void OP_OFF (int, int);
75static void OP_OFF64 (int, int);
76static void ptr_reg (int, int);
77static void OP_ESreg (int, int);
78static void OP_DSreg (int, int);
79static void OP_C (int, int);
80static void OP_D (int, int);
81static void OP_T (int, int);
6f74c397 82static void OP_R (int, int);
26ca5450
AJ		 83static void OP_MMX (int, int);
84static void OP_XMM (int, int);
85static void OP_EM (int, int);
86static void OP_EX (int, int);
4d9567e0
MM		 87static void OP_EMC (int,int);
88static void OP_MXC (int,int);
26ca5450
AJ		 89static void OP_MS (int, int);
90static void OP_XS (int, int);
cc0ec051 91static void OP_M (int, int);
cc0ec051 92static void OP_0f07 (int, int);
b844680a
L		 93static void OP_Monitor (int, int);
94static void OP_Mwait (int, int);
46e883c5
L		 95static void NOP_Fixup1 (int, int);
96static void NOP_Fixup2 (int, int);
26ca5450 97static void OP_3DNowSuffix (int, int);
ad19981d 98static void CMP_Fixup (int, int);
26ca5450 99static void BadOp (void);
35c52694 100static void REP_Fixup (int, int);
f5804c90 101static void CMPXCHG8B_Fixup (int, int);
42903f7f 102static void XMM_Fixup (int, int);
381d071f 103static void CRC32_Fixup (int, int);
85f10a01
MM		 104static void print_drex_arg (unsigned int, int, int);
105static void OP_DREX4 (int, int);
106static void OP_DREX3 (int, int);
107static void OP_DREX_ICMP (int, int);
108static void OP_DREX_FCMP (int, int);
252b5132 109
6608db57 110struct dis_private {
252b5132
RH		 111 /* Points to first byte not fetched. */
112 bfd_byte *max_fetched;
0b1cf022 113 bfd_byte the_buffer[MAX_MNEM_SIZE];
252b5132 114 bfd_vma insn_start;
e396998b 115 int orig_sizeflag;
252b5132
RH		 116 jmp_buf bailout;
117};
118
cb712a9e
L		 119enum address_mode
120{
121 mode_16bit,
122 mode_32bit,
123 mode_64bit
124};
125
126enum address_mode address_mode;
52b15da3 127
5076851f
ILT		 128/* Flags for the prefixes for the current instruction. See below. */
129static int prefixes;
130
52b15da3
JH		 131/* REX prefix the current instruction. See below. */
132static int rex;
133/* Bits of REX we've already used. */
134static int rex_used;
52b15da3
JH		 135/* Mark parts used in the REX prefix. When we are testing for
136 empty prefix (for 8bit register REX extension), just mask it
137 out. Otherwise test for REX bit is excuse for existence of REX
138 only in case value is nonzero. */
139#define USED_REX(value) \
140 { \
141 if (value) \
161a04f6
L		 142 { \
143 if ((rex & value)) \
144 rex_used |= (value) | REX_OPCODE; \
145 } \
52b15da3 146 else \
161a04f6 147 rex_used |= REX_OPCODE; \
52b15da3
JH		 148 }
149
85f10a01
MM		 150/* Special 'registers' for DREX handling */
151#define DREX_REG_UNKNOWN 1000 /* not initialized */
152#define DREX_REG_MEMORY 1001 /* use MODRM/SIB/OFFSET memory */
153
154/* The DREX byte has the following fields:
155 Bits 7-4 -- DREX.Dest, xmm destination register
156 Bit 3 -- DREX.OC0, operand config bit defines operand order
157 Bit 2 -- DREX.R, equivalent to REX_R bit, to extend ModRM register
158 Bit 1 -- DREX.X, equivalent to REX_X bit, to extend SIB index field
159 Bit 0 -- DREX.W, equivalent to REX_B bit, to extend ModRM r/m field,
160 SIB base field, or opcode reg field. */
161#define DREX_XMM(drex) ((drex >> 4) & 0xf)
162#define DREX_OC0(drex) ((drex >> 3) & 0x1)
163
7d421014
ILT		 164/* Flags for prefixes which we somehow handled when printing the
165 current instruction. */
166static int used_prefixes;
167
5076851f
ILT		 168/* Flags stored in PREFIXES. */
169#define PREFIX_REPZ 1
170#define PREFIX_REPNZ 2
171#define PREFIX_LOCK 4
172#define PREFIX_CS 8
173#define PREFIX_SS 0x10
174#define PREFIX_DS 0x20
175#define PREFIX_ES 0x40
176#define PREFIX_FS 0x80
177#define PREFIX_GS 0x100
178#define PREFIX_DATA 0x200
179#define PREFIX_ADDR 0x400
180#define PREFIX_FWAIT 0x800
181
252b5132
RH		 182/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
183 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
184 on error. */
185#define FETCH_DATA(info, addr) \
6608db57 186 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
252b5132
RH		 187 ? 1 : fetch_data ((info), (addr)))
188
189static int
26ca5450 190fetch_data (struct disassemble_info *info, bfd_byte *addr)
252b5132
RH		 191{
192 int status;
6608db57 193 struct dis_private *priv = (struct dis_private *) info->private_data;
252b5132
RH		 194 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
195
0b1cf022 196 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
272c9217
JB		 197 status = (*info->read_memory_func) (start,
198 priv->max_fetched,
199 addr - priv->max_fetched,
200 info);
201 else
202 status = -1;
252b5132
RH		 203 if (status != 0)
204 {
7d421014 205 /* If we did manage to read at least one byte, then
db6eb5be
AM		 206 print_insn_i386 will do something sensible. Otherwise, print
207 an error. We do that here because this is where we know
208 STATUS. */
7d421014 209 if (priv->max_fetched == priv->the_buffer)
5076851f 210 (*info->memory_error_func) (status, start, info);
252b5132
RH		 211 longjmp (priv->bailout, 1);
212 }
213 else
214 priv->max_fetched = addr;
215 return 1;
216}
217
ce518a5f
L		 218#define XX { NULL, 0 }
219
220#define Eb { OP_E, b_mode }
221#define Ev { OP_E, v_mode }
222#define Ed { OP_E, d_mode }
223#define Edq { OP_E, dq_mode }
224#define Edqw { OP_E, dqw_mode }
42903f7f
L		 225#define Edqb { OP_E, dqb_mode }
226#define Edqd { OP_E, dqd_mode }
09335d05 227#define Eq { OP_E, q_mode }
ce518a5f
L		 228#define indirEv { OP_indirE, stack_v_mode }
229#define indirEp { OP_indirE, f_mode }
230#define stackEv { OP_E, stack_v_mode }
231#define Em { OP_E, m_mode }
232#define Ew { OP_E, w_mode }
233#define M { OP_M, 0 } /* lea, lgdt, etc. */
234#define Ma { OP_M, v_mode }
b844680a 235#define Mb { OP_M, b_mode }
d9a5e5e5 236#define Md { OP_M, d_mode }
ce518a5f
L		 237#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
238#define Mq { OP_M, q_mode }
239#define Gb { OP_G, b_mode }
240#define Gv { OP_G, v_mode }
241#define Gd { OP_G, d_mode }
242#define Gdq { OP_G, dq_mode }
243#define Gm { OP_G, m_mode }
244#define Gw { OP_G, w_mode }
6f74c397
L		 245#define Rd { OP_R, d_mode }
246#define Rm { OP_R, m_mode }
ce518a5f
L		 247#define Ib { OP_I, b_mode }
248#define sIb { OP_sI, b_mode } /* sign extened byte */
249#define Iv { OP_I, v_mode }
250#define Iq { OP_I, q_mode }
251#define Iv64 { OP_I64, v_mode }
252#define Iw { OP_I, w_mode }
253#define I1 { OP_I, const_1_mode }
254#define Jb { OP_J, b_mode }
255#define Jv { OP_J, v_mode }
256#define Cm { OP_C, m_mode }
257#define Dm { OP_D, m_mode }
258#define Td { OP_T, d_mode }
b844680a 259#define Skip_MODRM { OP_Skip_MODRM, 0 }
ce518a5f
L		 260
261#define RMeAX { OP_REG, eAX_reg }
262#define RMeBX { OP_REG, eBX_reg }
263#define RMeCX { OP_REG, eCX_reg }
264#define RMeDX { OP_REG, eDX_reg }
265#define RMeSP { OP_REG, eSP_reg }
266#define RMeBP { OP_REG, eBP_reg }
267#define RMeSI { OP_REG, eSI_reg }
268#define RMeDI { OP_REG, eDI_reg }
269#define RMrAX { OP_REG, rAX_reg }
270#define RMrBX { OP_REG, rBX_reg }
271#define RMrCX { OP_REG, rCX_reg }
272#define RMrDX { OP_REG, rDX_reg }
273#define RMrSP { OP_REG, rSP_reg }
274#define RMrBP { OP_REG, rBP_reg }
275#define RMrSI { OP_REG, rSI_reg }
276#define RMrDI { OP_REG, rDI_reg }
277#define RMAL { OP_REG, al_reg }
278#define RMAL { OP_REG, al_reg }
279#define RMCL { OP_REG, cl_reg }
280#define RMDL { OP_REG, dl_reg }
281#define RMBL { OP_REG, bl_reg }
282#define RMAH { OP_REG, ah_reg }
283#define RMCH { OP_REG, ch_reg }
284#define RMDH { OP_REG, dh_reg }
285#define RMBH { OP_REG, bh_reg }
286#define RMAX { OP_REG, ax_reg }
287#define RMDX { OP_REG, dx_reg }
288
289#define eAX { OP_IMREG, eAX_reg }
290#define eBX { OP_IMREG, eBX_reg }
291#define eCX { OP_IMREG, eCX_reg }
292#define eDX { OP_IMREG, eDX_reg }
293#define eSP { OP_IMREG, eSP_reg }
294#define eBP { OP_IMREG, eBP_reg }
295#define eSI { OP_IMREG, eSI_reg }
296#define eDI { OP_IMREG, eDI_reg }
297#define AL { OP_IMREG, al_reg }
298#define CL { OP_IMREG, cl_reg }
299#define DL { OP_IMREG, dl_reg }
300#define BL { OP_IMREG, bl_reg }
301#define AH { OP_IMREG, ah_reg }
302#define CH { OP_IMREG, ch_reg }
303#define DH { OP_IMREG, dh_reg }
304#define BH { OP_IMREG, bh_reg }
305#define AX { OP_IMREG, ax_reg }
306#define DX { OP_IMREG, dx_reg }
307#define zAX { OP_IMREG, z_mode_ax_reg }
308#define indirDX { OP_IMREG, indir_dx_reg }
309
310#define Sw { OP_SEG, w_mode }
311#define Sv { OP_SEG, v_mode }
312#define Ap { OP_DIR, 0 }
313#define Ob { OP_OFF64, b_mode }
314#define Ov { OP_OFF64, v_mode }
315#define Xb { OP_DSreg, eSI_reg }
316#define Xv { OP_DSreg, eSI_reg }
317#define Xz { OP_DSreg, eSI_reg }
318#define Yb { OP_ESreg, eDI_reg }
319#define Yv { OP_ESreg, eDI_reg }
320#define DSBX { OP_DSreg, eBX_reg }
321
322#define es { OP_REG, es_reg }
323#define ss { OP_REG, ss_reg }
324#define cs { OP_REG, cs_reg }
325#define ds { OP_REG, ds_reg }
326#define fs { OP_REG, fs_reg }
327#define gs { OP_REG, gs_reg }
328
329#define MX { OP_MMX, 0 }
330#define XM { OP_XMM, 0 }
331#define EM { OP_EM, v_mode }
09a2c6cf 332#define EMd { OP_EM, d_mode }
14051056 333#define EMx { OP_EM, x_mode }
8976381e 334#define EXw { OP_EX, w_mode }
09a2c6cf
L		 335#define EXd { OP_EX, d_mode }
336#define EXq { OP_EX, q_mode }
337#define EXx { OP_EX, x_mode }
ce518a5f
L		 338#define MS { OP_MS, v_mode }
339#define XS { OP_XS, v_mode }
09335d05 340#define EMCq { OP_EMC, q_mode }
ce518a5f 341#define MXC { OP_MXC, 0 }
ce518a5f 342#define OPSUF { OP_3DNowSuffix, 0 }
ad19981d 343#define CMP { CMP_Fixup, 0 }
42903f7f 344#define XMM0 { XMM_Fixup, 0 }
252b5132 345
35c52694 346/* Used handle "rep" prefix for string instructions. */
ce518a5f
L		 347#define Xbr { REP_Fixup, eSI_reg }
348#define Xvr { REP_Fixup, eSI_reg }
349#define Ybr { REP_Fixup, eDI_reg }
350#define Yvr { REP_Fixup, eDI_reg }
351#define Yzr { REP_Fixup, eDI_reg }
352#define indirDXr { REP_Fixup, indir_dx_reg }
353#define ALr { REP_Fixup, al_reg }
354#define eAXr { REP_Fixup, eAX_reg }
355
356#define cond_jump_flag { NULL, cond_jump_mode }
357#define loop_jcxz_flag { NULL, loop_jcxz_mode }
3ffd33cf 358
252b5132 359/* bits in sizeflag */
252b5132 360#define SUFFIX_ALWAYS 4
252b5132
RH		 361#define AFLAG 2
362#define DFLAG 1
363
d55ee72f
L		 364/* byte operand */
365#define b_mode 1
366/* operand size depends on prefixes */
630c2cc5 367#define v_mode (b_mode + 1)
d55ee72f
L		 368/* word operand */
369#define w_mode (v_mode + 1)
370/* double word operand */
371#define d_mode (w_mode + 1)
372/* quad word operand */
373#define q_mode (d_mode + 1)
374/* ten-byte operand */
375#define t_mode (q_mode + 1)
376/* 16-byte XMM operand */
377#define x_mode (t_mode + 1)
378/* d_mode in 32bit, q_mode in 64bit mode. */
379#define m_mode (x_mode + 1)
380#define cond_jump_mode (m_mode + 1)
381#define loop_jcxz_mode (cond_jump_mode + 1)
382/* operand size depends on REX prefixes. */
383#define dq_mode (loop_jcxz_mode + 1)
384/* registers like dq_mode, memory like w_mode. */
385#define dqw_mode (dq_mode + 1)
386/* 4- or 6-byte pointer operand */
387#define f_mode (dqw_mode + 1)
388#define const_1_mode (f_mode + 1)
389/* v_mode for stack-related opcodes. */
390#define stack_v_mode (const_1_mode + 1)
391/* non-quad operand size depends on prefixes */
392#define z_mode (stack_v_mode + 1)
393/* 16-byte operand */
394#define o_mode (z_mode + 1)
395/* registers like dq_mode, memory like b_mode. */
396#define dqb_mode (o_mode + 1)
397/* registers like dq_mode, memory like d_mode. */
398#define dqd_mode (dqb_mode + 1)
399
400#define es_reg (dqd_mode + 1)
401#define cs_reg (es_reg + 1)
402#define ss_reg (cs_reg + 1)
403#define ds_reg (ss_reg + 1)
404#define fs_reg (ds_reg + 1)
405#define gs_reg (fs_reg + 1)
406
407#define eAX_reg (gs_reg + 1)
408#define eCX_reg (eAX_reg + 1)
409#define eDX_reg (eCX_reg + 1)
410#define eBX_reg (eDX_reg + 1)
411#define eSP_reg (eBX_reg + 1)
412#define eBP_reg (eSP_reg + 1)
413#define eSI_reg (eBP_reg + 1)
414#define eDI_reg (eSI_reg + 1)
415
416#define al_reg (eDI_reg + 1)
417#define cl_reg (al_reg + 1)
418#define dl_reg (cl_reg + 1)
419#define bl_reg (dl_reg + 1)
420#define ah_reg (bl_reg + 1)
421#define ch_reg (ah_reg + 1)
422#define dh_reg (ch_reg + 1)
423#define bh_reg (dh_reg + 1)
424
425#define ax_reg (bh_reg + 1)
426#define cx_reg (ax_reg + 1)
427#define dx_reg (cx_reg + 1)
428#define bx_reg (dx_reg + 1)
429#define sp_reg (bx_reg + 1)
430#define bp_reg (sp_reg + 1)
431#define si_reg (bp_reg + 1)
432#define di_reg (si_reg + 1)
433
434#define rAX_reg (di_reg + 1)
435#define rCX_reg (rAX_reg + 1)
436#define rDX_reg (rCX_reg + 1)
437#define rBX_reg (rDX_reg + 1)
438#define rSP_reg (rBX_reg + 1)
439#define rBP_reg (rSP_reg + 1)
440#define rSI_reg (rBP_reg + 1)
441#define rDI_reg (rSI_reg + 1)
442
443#define z_mode_ax_reg (rDI_reg + 1)
444#define indir_dx_reg (z_mode_ax_reg + 1)
445
446#define MAX_BYTEMODE indir_dx_reg
447
448/* Flags that are OR'ed into the bytemode field to pass extra
449 information. */
450#define DREX_OC1 0x10000 /* OC1 bit set */
451#define DREX_NO_OC0 0x20000 /* OC0 bit not used */
452#define DREX_MASK 0x40000 /* mask to delete */
453
454#if MAX_BYTEMODE >= DREX_OC1
455#error MAX_BYTEMODE must be less than DREX_OC1
456#endif
252b5132 457
1b0d430b
L		 458#define FLOATCODE 1
459#define USE_REG_TABLE (FLOATCODE + 1)
460#define USE_MOD_TABLE (USE_REG_TABLE + 1)
461#define USE_RM_TABLE (USE_MOD_TABLE + 1)
462#define USE_PREFIX_TABLE (USE_RM_TABLE + 1)
463#define USE_X86_64_TABLE (USE_PREFIX_TABLE + 1)
464#define USE_3BYTE_TABLE (USE_X86_64_TABLE + 1)
6439fc28 465
1ceb70f8 466#define FLOAT NULL, { { NULL, FLOATCODE } }
4efba78c 467
4e7d34a6 468#define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
1ceb70f8
L		 469#define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
470#define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
471#define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
472#define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
4e7d34a6
L		 473#define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
474#define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
1ceb70f8
L		 475
476#define REG_80 0
477#define REG_81 (REG_80 + 1)
478#define REG_82 (REG_81 + 1)
479#define REG_8F (REG_82 + 1)
480#define REG_C0 (REG_8F + 1)
481#define REG_C1 (REG_C0 + 1)
482#define REG_C6 (REG_C1 + 1)
483#define REG_C7 (REG_C6 + 1)
484#define REG_D0 (REG_C7 + 1)
485#define REG_D1 (REG_D0 + 1)
486#define REG_D2 (REG_D1 + 1)
487#define REG_D3 (REG_D2 + 1)
488#define REG_F6 (REG_D3 + 1)
489#define REG_F7 (REG_F6 + 1)
490#define REG_FE (REG_F7 + 1)
491#define REG_FF (REG_FE + 1)
492#define REG_0F00 (REG_FF + 1)
493#define REG_0F01 (REG_0F00 + 1)
b5b1fc4f
L		 494#define REG_0F0D (REG_0F01 + 1)
495#define REG_0F18 (REG_0F0D + 1)
1ceb70f8
L		 496#define REG_0F71 (REG_0F18 + 1)
497#define REG_0F72 (REG_0F71 + 1)
498#define REG_0F73 (REG_0F72 + 1)
499#define REG_0FA6 (REG_0F73 + 1)
500#define REG_0FA7 (REG_0FA6 + 1)
501#define REG_0FAE (REG_0FA7 + 1)
502#define REG_0FBA (REG_0FAE + 1)
503#define REG_0FC7 (REG_0FBA + 1)
504
505#define MOD_8D 0
92fddf8e 506#define MOD_0F01_REG_0 (MOD_8D + 1)
1ceb70f8
L		 507#define MOD_0F01_REG_1 (MOD_0F01_REG_0 + 1)
508#define MOD_0F01_REG_2 (MOD_0F01_REG_1 + 1)
509#define MOD_0F01_REG_3 (MOD_0F01_REG_2 + 1)
510#define MOD_0F01_REG_7 (MOD_0F01_REG_3 + 1)
92fddf8e
L		 511#define MOD_0F12_PREFIX_0 (MOD_0F01_REG_7 + 1)
512#define MOD_0F13 (MOD_0F12_PREFIX_0 + 1)
513#define MOD_0F16_PREFIX_0 (MOD_0F13 + 1)
514#define MOD_0F17 (MOD_0F16_PREFIX_0 + 1)
515#define MOD_0F18_REG_0 (MOD_0F17 + 1)
1ceb70f8
L		 516#define MOD_0F18_REG_1 (MOD_0F18_REG_0 + 1)
517#define MOD_0F18_REG_2 (MOD_0F18_REG_1 + 1)
518#define MOD_0F18_REG_3 (MOD_0F18_REG_2 + 1)
92fddf8e
L		 519#define MOD_0F20 (MOD_0F18_REG_3 + 1)
520#define MOD_0F21 (MOD_0F20 + 1)
521#define MOD_0F22 (MOD_0F21 + 1)
522#define MOD_0F23 (MOD_0F22 + 1)
523#define MOD_0F24 (MOD_0F23 + 1)
524#define MOD_0F26 (MOD_0F24 + 1)
75c135a8
L		 525#define MOD_0F2B_PREFIX_0 (MOD_0F26 + 1)
526#define MOD_0F2B_PREFIX_1 (MOD_0F2B_PREFIX_0 + 1)
527#define MOD_0F2B_PREFIX_2 (MOD_0F2B_PREFIX_1 + 1)
528#define MOD_0F2B_PREFIX_3 (MOD_0F2B_PREFIX_2 + 1)
529#define MOD_0F51 (MOD_0F2B_PREFIX_3 + 1)
530#define MOD_0F71_REG_2 (MOD_0F51 + 1)
1ceb70f8
L		 531#define MOD_0F71_REG_4 (MOD_0F71_REG_2 + 1)
532#define MOD_0F71_REG_6 (MOD_0F71_REG_4 + 1)
533#define MOD_0F72_REG_2 (MOD_0F71_REG_6 + 1)
534#define MOD_0F72_REG_4 (MOD_0F72_REG_2 + 1)
535#define MOD_0F72_REG_6 (MOD_0F72_REG_4 + 1)
536#define MOD_0F73_REG_2 (MOD_0F72_REG_6 + 1)
537#define MOD_0F73_REG_3 (MOD_0F73_REG_2 + 1)
538#define MOD_0F73_REG_6 (MOD_0F73_REG_3 + 1)
539#define MOD_0F73_REG_7 (MOD_0F73_REG_6 + 1)
540#define MOD_0FAE_REG_0 (MOD_0F73_REG_7 + 1)
541#define MOD_0FAE_REG_1 (MOD_0FAE_REG_0 + 1)
542#define MOD_0FAE_REG_2 (MOD_0FAE_REG_1 + 1)
543#define MOD_0FAE_REG_3 (MOD_0FAE_REG_2 + 1)
544#define MOD_0FAE_REG_5 (MOD_0FAE_REG_3 + 1)
545#define MOD_0FAE_REG_6 (MOD_0FAE_REG_5 + 1)
546#define MOD_0FAE_REG_7 (MOD_0FAE_REG_6 + 1)
92fddf8e
L		 547#define MOD_0FB2 (MOD_0FAE_REG_7 + 1)
548#define MOD_0FB4 (MOD_0FB2 + 1)
549#define MOD_0FB5 (MOD_0FB4 + 1)
550#define MOD_0FC7_REG_6 (MOD_0FB5 + 1)
1ceb70f8 551#define MOD_0FC7_REG_7 (MOD_0FC7_REG_6 + 1)
75c135a8
L		 552#define MOD_0FD7 (MOD_0FC7_REG_7 + 1)
553#define MOD_0FE7_PREFIX_2 (MOD_0FD7 + 1)
554#define MOD_0FF0_PREFIX_3 (MOD_0FE7_PREFIX_2 + 1)
555#define MOD_0F382A_PREFIX_2 (MOD_0FF0_PREFIX_3 + 1)
556#define MOD_62_32BIT (MOD_0F382A_PREFIX_2 + 1)
1ceb70f8
L		 557#define MOD_C4_32BIT (MOD_62_32BIT + 1)
558#define MOD_C5_32BIT (MOD_C4_32BIT + 1)
559
560#define RM_0F01_REG_0 0
561#define RM_0F01_REG_1 (RM_0F01_REG_0 + 1)
562#define RM_0F01_REG_3 (RM_0F01_REG_1 + 1)
563#define RM_0F01_REG_7 (RM_0F01_REG_3 + 1)
564#define RM_0FAE_REG_5 (RM_0F01_REG_7 + 1)
565#define RM_0FAE_REG_6 (RM_0FAE_REG_5 + 1)
566#define RM_0FAE_REG_7 (RM_0FAE_REG_6 + 1)
567
568#define PREFIX_90 0
569#define PREFIX_0F10 (PREFIX_90 + 1)
570#define PREFIX_0F11 (PREFIX_0F10 + 1)
571#define PREFIX_0F12 (PREFIX_0F11 + 1)
572#define PREFIX_0F16 (PREFIX_0F12 + 1)
573#define PREFIX_0F2A (PREFIX_0F16 + 1)
574#define PREFIX_0F2B (PREFIX_0F2A + 1)
575#define PREFIX_0F2C (PREFIX_0F2B + 1)
576#define PREFIX_0F2D (PREFIX_0F2C + 1)
577#define PREFIX_0F2E (PREFIX_0F2D + 1)
578#define PREFIX_0F2F (PREFIX_0F2E + 1)
579#define PREFIX_0F51 (PREFIX_0F2F + 1)
580#define PREFIX_0F52 (PREFIX_0F51 + 1)
581#define PREFIX_0F53 (PREFIX_0F52 + 1)
582#define PREFIX_0F58 (PREFIX_0F53 + 1)
583#define PREFIX_0F59 (PREFIX_0F58 + 1)
584#define PREFIX_0F5A (PREFIX_0F59 + 1)
585#define PREFIX_0F5B (PREFIX_0F5A + 1)
586#define PREFIX_0F5C (PREFIX_0F5B + 1)
587#define PREFIX_0F5D (PREFIX_0F5C + 1)
588#define PREFIX_0F5E (PREFIX_0F5D + 1)
589#define PREFIX_0F5F (PREFIX_0F5E + 1)
590#define PREFIX_0F60 (PREFIX_0F5F + 1)
591#define PREFIX_0F61 (PREFIX_0F60 + 1)
592#define PREFIX_0F62 (PREFIX_0F61 + 1)
593#define PREFIX_0F6C (PREFIX_0F62 + 1)
594#define PREFIX_0F6D (PREFIX_0F6C + 1)
595#define PREFIX_0F6F (PREFIX_0F6D + 1)
596#define PREFIX_0F70 (PREFIX_0F6F + 1)
92fddf8e
L		 597#define PREFIX_0F73_REG_3 (PREFIX_0F70 + 1)
598#define PREFIX_0F73_REG_7 (PREFIX_0F73_REG_3 + 1)
599#define PREFIX_0F78 (PREFIX_0F73_REG_7 + 1)
1ceb70f8
L		 600#define PREFIX_0F79 (PREFIX_0F78 + 1)
601#define PREFIX_0F7C (PREFIX_0F79 + 1)
602#define PREFIX_0F7D (PREFIX_0F7C + 1)
603#define PREFIX_0F7E (PREFIX_0F7D + 1)
604#define PREFIX_0F7F (PREFIX_0F7E + 1)
605#define PREFIX_0FB8 (PREFIX_0F7F + 1)
606#define PREFIX_0FBD (PREFIX_0FB8 + 1)
607#define PREFIX_0FC2 (PREFIX_0FBD + 1)
92fddf8e
L		 608#define PREFIX_0FC7_REG_6 (PREFIX_0FC2 + 1)
609#define PREFIX_0FD0 (PREFIX_0FC7_REG_6 + 1)
1ceb70f8
L		 610#define PREFIX_0FD6 (PREFIX_0FD0 + 1)
611#define PREFIX_0FE6 (PREFIX_0FD6 + 1)
612#define PREFIX_0FE7 (PREFIX_0FE6 + 1)
613#define PREFIX_0FF0 (PREFIX_0FE7 + 1)
614#define PREFIX_0FF7 (PREFIX_0FF0 + 1)
615#define PREFIX_0F3810 (PREFIX_0FF7 + 1)
616#define PREFIX_0F3814 (PREFIX_0F3810 + 1)
617#define PREFIX_0F3815 (PREFIX_0F3814 + 1)
618#define PREFIX_0F3817 (PREFIX_0F3815 + 1)
619#define PREFIX_0F3820 (PREFIX_0F3817 + 1)
620#define PREFIX_0F3821 (PREFIX_0F3820 + 1)
621#define PREFIX_0F3822 (PREFIX_0F3821 + 1)
622#define PREFIX_0F3823 (PREFIX_0F3822 + 1)
623#define PREFIX_0F3824 (PREFIX_0F3823 + 1)
624#define PREFIX_0F3825 (PREFIX_0F3824 + 1)
625#define PREFIX_0F3828 (PREFIX_0F3825 + 1)
626#define PREFIX_0F3829 (PREFIX_0F3828 + 1)
627#define PREFIX_0F382A (PREFIX_0F3829 + 1)
628#define PREFIX_0F382B (PREFIX_0F382A + 1)
629#define PREFIX_0F3830 (PREFIX_0F382B + 1)
630#define PREFIX_0F3831 (PREFIX_0F3830 + 1)
631#define PREFIX_0F3832 (PREFIX_0F3831 + 1)
632#define PREFIX_0F3833 (PREFIX_0F3832 + 1)
633#define PREFIX_0F3834 (PREFIX_0F3833 + 1)
634#define PREFIX_0F3835 (PREFIX_0F3834 + 1)
635#define PREFIX_0F3837 (PREFIX_0F3835 + 1)
636#define PREFIX_0F3838 (PREFIX_0F3837 + 1)
637#define PREFIX_0F3839 (PREFIX_0F3838 + 1)
638#define PREFIX_0F383A (PREFIX_0F3839 + 1)
639#define PREFIX_0F383B (PREFIX_0F383A + 1)
640#define PREFIX_0F383C (PREFIX_0F383B + 1)
641#define PREFIX_0F383D (PREFIX_0F383C + 1)
642#define PREFIX_0F383E (PREFIX_0F383D + 1)
643#define PREFIX_0F383F (PREFIX_0F383E + 1)
644#define PREFIX_0F3840 (PREFIX_0F383F + 1)
645#define PREFIX_0F3841 (PREFIX_0F3840 + 1)
646#define PREFIX_0F38F0 (PREFIX_0F3841 + 1)
647#define PREFIX_0F38F1 (PREFIX_0F38F0 + 1)
648#define PREFIX_0F3A08 (PREFIX_0F38F1 + 1)
649#define PREFIX_0F3A09 (PREFIX_0F3A08 + 1)
650#define PREFIX_0F3A0A (PREFIX_0F3A09 + 1)
651#define PREFIX_0F3A0B (PREFIX_0F3A0A + 1)
652#define PREFIX_0F3A0C (PREFIX_0F3A0B + 1)
653#define PREFIX_0F3A0D (PREFIX_0F3A0C + 1)
654#define PREFIX_0F3A0E (PREFIX_0F3A0D + 1)
655#define PREFIX_0F3A14 (PREFIX_0F3A0E + 1)
656#define PREFIX_0F3A15 (PREFIX_0F3A14 + 1)
657#define PREFIX_0F3A16 (PREFIX_0F3A15 + 1)
658#define PREFIX_0F3A17 (PREFIX_0F3A16 + 1)
659#define PREFIX_0F3A20 (PREFIX_0F3A17 + 1)
660#define PREFIX_0F3A21 (PREFIX_0F3A20 + 1)
661#define PREFIX_0F3A22 (PREFIX_0F3A21 + 1)
662#define PREFIX_0F3A40 (PREFIX_0F3A22 + 1)
663#define PREFIX_0F3A41 (PREFIX_0F3A40 + 1)
664#define PREFIX_0F3A42 (PREFIX_0F3A41 + 1)
665#define PREFIX_0F3A60 (PREFIX_0F3A42 + 1)
666#define PREFIX_0F3A61 (PREFIX_0F3A60 + 1)
667#define PREFIX_0F3A62 (PREFIX_0F3A61 + 1)
668#define PREFIX_0F3A63 (PREFIX_0F3A62 + 1)
4e7d34a6
L		 669
670#define X86_64_06 0
671#define X86_64_07 (X86_64_06 + 1)
672#define X86_64_0D (X86_64_07 + 1)
673#define X86_64_16 (X86_64_0D + 1)
674#define X86_64_17 (X86_64_16 + 1)
675#define X86_64_1E (X86_64_17 + 1)
676#define X86_64_1F (X86_64_1E + 1)
677#define X86_64_27 (X86_64_1F + 1)
678#define X86_64_2F (X86_64_27 + 1)
679#define X86_64_37 (X86_64_2F + 1)
680#define X86_64_3F (X86_64_37 + 1)
681#define X86_64_60 (X86_64_3F + 1)
682#define X86_64_61 (X86_64_60 + 1)
683#define X86_64_62 (X86_64_61 + 1)
684#define X86_64_63 (X86_64_62 + 1)
685#define X86_64_6D (X86_64_63 + 1)
686#define X86_64_6F (X86_64_6D + 1)
687#define X86_64_9A (X86_64_6F + 1)
688#define X86_64_C4 (X86_64_9A + 1)
689#define X86_64_C5 (X86_64_C4 + 1)
690#define X86_64_CE (X86_64_C5 + 1)
691#define X86_64_D4 (X86_64_CE + 1)
692#define X86_64_D5 (X86_64_D4 + 1)
693#define X86_64_EA (X86_64_D5 + 1)
694#define X86_64_0F01_REG_0 (X86_64_EA + 1)
695#define X86_64_0F01_REG_1 (X86_64_0F01_REG_0 + 1)
696#define X86_64_0F01_REG_2 (X86_64_0F01_REG_1 + 1)
697#define X86_64_0F01_REG_3 (X86_64_0F01_REG_2 + 1)
698
699#define THREE_BYTE_0F24 0
700#define THREE_BYTE_0F25 (THREE_BYTE_0F24 + 1)
701#define THREE_BYTE_0F38 (THREE_BYTE_0F25 + 1)
702#define THREE_BYTE_0F3A (THREE_BYTE_0F38 + 1)
703#define THREE_BYTE_0F7A (THREE_BYTE_0F3A + 1)
89b66d55 704#define THREE_BYTE_0F7B (THREE_BYTE_0F7A + 1)
4e7d34a6 705
26ca5450 706typedef void (*op_rtn) (int bytemode, int sizeflag);
252b5132
RH		 707
708struct dis386 {
2da11e11 709 const char *name;
ce518a5f
L		 710 struct
711 {
712 op_rtn rtn;
713 int bytemode;
714 } op[MAX_OPERANDS];
252b5132
RH		 715};
716
717/* Upper case letters in the instruction names here are macros.
718 'A' => print 'b' if no register operands or suffix_always is true
719 'B' => print 'b' if suffix_always is true
9306ca4a 720 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
98b528ac 721 size prefix
ed7841b3 722 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
98b528ac 723 suffix_always is true
252b5132 724 'E' => print 'e' if 32-bit form of jcxz
3ffd33cf 725 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
52fd6d94 726 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
5dd0794d 727 'H' => print ",pt" or ",pn" branch hint
9306ca4a 728 'I' => honor following macro letter even in Intel mode (implemented only
98b528ac 729 for some of the macro letters)
9306ca4a 730 'J' => print 'l'
42903f7f 731 'K' => print 'd' or 'q' if rex prefix is present.
252b5132 732 'L' => print 'l' if suffix_always is true
9d141669 733 'M' => print 'r' if intel_mnemonic is false.
252b5132 734 'N' => print 'n' if instruction has no wait "prefix"
a35ca55a 735 'O' => print 'd' or 'o' (or 'q' in Intel mode)
52b15da3 736 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
98b528ac
L		 737 or suffix_always is true. print 'q' if rex prefix is present.
738 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
739 is true
a35ca55a 740 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
52b15da3 741 'S' => print 'w', 'l' or 'q' if suffix_always is true
6439fc28
AM		 742 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
743 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1a114b12 744 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
a35ca55a 745 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
9306ca4a 746 'X' => print 's', 'd' depending on data16 prefix (for XMM)
8a72226a
L		 747 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
748 suffix_always is true.
6dd5059a 749 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
9d141669 750 '!' => change condition from true to false or from false to true.
98b528ac
L		 751 '%' => add 1 upper case letter to the macro.
752
753 2 upper case letter macros:
754 'LQ' => print 'l' ('d' in Intel mode) or 'q' for memory operand
755 or suffix_always is true
52b15da3 756
6439fc28
AM		 757 Many of the above letters print nothing in Intel mode. See "putop"
758 for the details.
52b15da3 759
6439fc28 760 Braces '{' and '}', and vertical bars '|', indicate alternative
7c52e0e8 761 mnemonic strings for AT&T and Intel. */
252b5132 762
6439fc28 763static const struct dis386 dis386[] = {
252b5132 764 /* 00 */
ce518a5f
L		 765 { "addB", { Eb, Gb } },
766 { "addS", { Ev, Gv } },
767 { "addB", { Gb, Eb } },
768 { "addS", { Gv, Ev } },
769 { "addB", { AL, Ib } },
770 { "addS", { eAX, Iv } },
4e7d34a6
L		 771 { X86_64_TABLE (X86_64_06) },
772 { X86_64_TABLE (X86_64_07) },
252b5132 773 /* 08 */
ce518a5f
L		 774 { "orB", { Eb, Gb } },
775 { "orS", { Ev, Gv } },
776 { "orB", { Gb, Eb } },
777 { "orS", { Gv, Ev } },
778 { "orB", { AL, Ib } },
779 { "orS", { eAX, Iv } },
4e7d34a6 780 { X86_64_TABLE (X86_64_0D) },
ce518a5f 781 { "(bad)", { XX } }, /* 0x0f extended opcode escape */
252b5132 782 /* 10 */
ce518a5f
L		 783 { "adcB", { Eb, Gb } },
784 { "adcS", { Ev, Gv } },
785 { "adcB", { Gb, Eb } },
786 { "adcS", { Gv, Ev } },
787 { "adcB", { AL, Ib } },
788 { "adcS", { eAX, Iv } },
4e7d34a6
L		 789 { X86_64_TABLE (X86_64_16) },
790 { X86_64_TABLE (X86_64_17) },
252b5132 791 /* 18 */
ce518a5f
L		 792 { "sbbB", { Eb, Gb } },
793 { "sbbS", { Ev, Gv } },
794 { "sbbB", { Gb, Eb } },
795 { "sbbS", { Gv, Ev } },
796 { "sbbB", { AL, Ib } },
797 { "sbbS", { eAX, Iv } },
4e7d34a6
L		 798 { X86_64_TABLE (X86_64_1E) },
799 { X86_64_TABLE (X86_64_1F) },
252b5132 800 /* 20 */
ce518a5f
L		 801 { "andB", { Eb, Gb } },
802 { "andS", { Ev, Gv } },
803 { "andB", { Gb, Eb } },
804 { "andS", { Gv, Ev } },
805 { "andB", { AL, Ib } },
806 { "andS", { eAX, Iv } },
807 { "(bad)", { XX } }, /* SEG ES prefix */
4e7d34a6 808 { X86_64_TABLE (X86_64_27) },
252b5132 809 /* 28 */
ce518a5f
L		 810 { "subB", { Eb, Gb } },
811 { "subS", { Ev, Gv } },
812 { "subB", { Gb, Eb } },
813 { "subS", { Gv, Ev } },
814 { "subB", { AL, Ib } },
815 { "subS", { eAX, Iv } },
816 { "(bad)", { XX } }, /* SEG CS prefix */
4e7d34a6 817 { X86_64_TABLE (X86_64_2F) },
252b5132 818 /* 30 */
ce518a5f
L		 819 { "xorB", { Eb, Gb } },
820 { "xorS", { Ev, Gv } },
821 { "xorB", { Gb, Eb } },
822 { "xorS", { Gv, Ev } },
823 { "xorB", { AL, Ib } },
824 { "xorS", { eAX, Iv } },
825 { "(bad)", { XX } }, /* SEG SS prefix */
4e7d34a6 826 { X86_64_TABLE (X86_64_37) },
252b5132 827 /* 38 */
ce518a5f
L		 828 { "cmpB", { Eb, Gb } },
829 { "cmpS", { Ev, Gv } },
830 { "cmpB", { Gb, Eb } },
831 { "cmpS", { Gv, Ev } },
832 { "cmpB", { AL, Ib } },
833 { "cmpS", { eAX, Iv } },
834 { "(bad)", { XX } }, /* SEG DS prefix */
4e7d34a6 835 { X86_64_TABLE (X86_64_3F) },
252b5132 836 /* 40 */
ce518a5f
L		 837 { "inc{S|}", { RMeAX } },
838 { "inc{S|}", { RMeCX } },
839 { "inc{S|}", { RMeDX } },
840 { "inc{S|}", { RMeBX } },
841 { "inc{S|}", { RMeSP } },
842 { "inc{S|}", { RMeBP } },
843 { "inc{S|}", { RMeSI } },
844 { "inc{S|}", { RMeDI } },
252b5132 845 /* 48 */
ce518a5f
L		 846 { "dec{S|}", { RMeAX } },
847 { "dec{S|}", { RMeCX } },
848 { "dec{S|}", { RMeDX } },
849 { "dec{S|}", { RMeBX } },
850 { "dec{S|}", { RMeSP } },
851 { "dec{S|}", { RMeBP } },
852 { "dec{S|}", { RMeSI } },
853 { "dec{S|}", { RMeDI } },
252b5132 854 /* 50 */
ce518a5f
L		 855 { "pushV", { RMrAX } },
856 { "pushV", { RMrCX } },
857 { "pushV", { RMrDX } },
858 { "pushV", { RMrBX } },
859 { "pushV", { RMrSP } },
860 { "pushV", { RMrBP } },
861 { "pushV", { RMrSI } },
862 { "pushV", { RMrDI } },
252b5132 863 /* 58 */
ce518a5f
L		 864 { "popV", { RMrAX } },
865 { "popV", { RMrCX } },
866 { "popV", { RMrDX } },
867 { "popV", { RMrBX } },
868 { "popV", { RMrSP } },
869 { "popV", { RMrBP } },
870 { "popV", { RMrSI } },
871 { "popV", { RMrDI } },
252b5132 872 /* 60 */
4e7d34a6
L		 873 { X86_64_TABLE (X86_64_60) },
874 { X86_64_TABLE (X86_64_61) },
875 { X86_64_TABLE (X86_64_62) },
876 { X86_64_TABLE (X86_64_63) },
ce518a5f
L		 877 { "(bad)", { XX } }, /* seg fs */
878 { "(bad)", { XX } }, /* seg gs */
879 { "(bad)", { XX } }, /* op size prefix */
880 { "(bad)", { XX } }, /* adr size prefix */
252b5132 881 /* 68 */
ce518a5f
L		 882 { "pushT", { Iq } },
883 { "imulS", { Gv, Ev, Iv } },
884 { "pushT", { sIb } },
885 { "imulS", { Gv, Ev, sIb } },
7c52e0e8 886 { "ins{b|}", { Ybr, indirDX } },
4e7d34a6 887 { X86_64_TABLE (X86_64_6D) },
7c52e0e8 888 { "outs{b|}", { indirDXr, Xb } },
4e7d34a6 889 { X86_64_TABLE (X86_64_6F) },
252b5132 890 /* 70 */
ce518a5f
L		 891 { "joH", { Jb, XX, cond_jump_flag } },
892 { "jnoH", { Jb, XX, cond_jump_flag } },
893 { "jbH", { Jb, XX, cond_jump_flag } },
894 { "jaeH", { Jb, XX, cond_jump_flag } },
895 { "jeH", { Jb, XX, cond_jump_flag } },
896 { "jneH", { Jb, XX, cond_jump_flag } },
897 { "jbeH", { Jb, XX, cond_jump_flag } },
898 { "jaH", { Jb, XX, cond_jump_flag } },
252b5132 899 /* 78 */
ce518a5f
L		 900 { "jsH", { Jb, XX, cond_jump_flag } },
901 { "jnsH", { Jb, XX, cond_jump_flag } },
902 { "jpH", { Jb, XX, cond_jump_flag } },
903 { "jnpH", { Jb, XX, cond_jump_flag } },
904 { "jlH", { Jb, XX, cond_jump_flag } },
905 { "jgeH", { Jb, XX, cond_jump_flag } },
906 { "jleH", { Jb, XX, cond_jump_flag } },
907 { "jgH", { Jb, XX, cond_jump_flag } },
252b5132 908 /* 80 */
1ceb70f8
L		 909 { REG_TABLE (REG_80) },
910 { REG_TABLE (REG_81) },
ce518a5f 911 { "(bad)", { XX } },
1ceb70f8 912 { REG_TABLE (REG_82) },
ce518a5f
L		 913 { "testB", { Eb, Gb } },
914 { "testS", { Ev, Gv } },
915 { "xchgB", { Eb, Gb } },
916 { "xchgS", { Ev, Gv } },
252b5132 917 /* 88 */
ce518a5f
L		 918 { "movB", { Eb, Gb } },
919 { "movS", { Ev, Gv } },
920 { "movB", { Gb, Eb } },
921 { "movS", { Gv, Ev } },
922 { "movD", { Sv, Sw } },
1ceb70f8 923 { MOD_TABLE (MOD_8D) },
ce518a5f 924 { "movD", { Sw, Sv } },
1ceb70f8 925 { REG_TABLE (REG_8F) },
252b5132 926 /* 90 */
1ceb70f8 927 { PREFIX_TABLE (PREFIX_90) },
ce518a5f
L		 928 { "xchgS", { RMeCX, eAX } },
929 { "xchgS", { RMeDX, eAX } },
930 { "xchgS", { RMeBX, eAX } },
931 { "xchgS", { RMeSP, eAX } },
932 { "xchgS", { RMeBP, eAX } },
933 { "xchgS", { RMeSI, eAX } },
934 { "xchgS", { RMeDI, eAX } },
252b5132 935 /* 98 */
7c52e0e8
L		 936 { "cW{t|}R", { XX } },
937 { "cR{t|}O", { XX } },
4e7d34a6 938 { X86_64_TABLE (X86_64_9A) },
ce518a5f
L		 939 { "(bad)", { XX } }, /* fwait */
940 { "pushfT", { XX } },
941 { "popfT", { XX } },
7c52e0e8
L		 942 { "sahf", { XX } },
943 { "lahf", { XX } },
252b5132 944 /* a0 */
ce518a5f
L		 945 { "movB", { AL, Ob } },
946 { "movS", { eAX, Ov } },
947 { "movB", { Ob, AL } },
948 { "movS", { Ov, eAX } },
7c52e0e8
L		 949 { "movs{b|}", { Ybr, Xb } },
950 { "movs{R|}", { Yvr, Xv } },
951 { "cmps{b|}", { Xb, Yb } },
952 { "cmps{R|}", { Xv, Yv } },
252b5132 953 /* a8 */
ce518a5f
L		 954 { "testB", { AL, Ib } },
955 { "testS", { eAX, Iv } },
956 { "stosB", { Ybr, AL } },
957 { "stosS", { Yvr, eAX } },
958 { "lodsB", { ALr, Xb } },
959 { "lodsS", { eAXr, Xv } },
960 { "scasB", { AL, Yb } },
961 { "scasS", { eAX, Yv } },
252b5132 962 /* b0 */
ce518a5f
L		 963 { "movB", { RMAL, Ib } },
964 { "movB", { RMCL, Ib } },
965 { "movB", { RMDL, Ib } },
966 { "movB", { RMBL, Ib } },
967 { "movB", { RMAH, Ib } },
968 { "movB", { RMCH, Ib } },
969 { "movB", { RMDH, Ib } },
970 { "movB", { RMBH, Ib } },
252b5132 971 /* b8 */
ce518a5f
L		 972 { "movS", { RMeAX, Iv64 } },
973 { "movS", { RMeCX, Iv64 } },
974 { "movS", { RMeDX, Iv64 } },
975 { "movS", { RMeBX, Iv64 } },
976 { "movS", { RMeSP, Iv64 } },
977 { "movS", { RMeBP, Iv64 } },
978 { "movS", { RMeSI, Iv64 } },
979 { "movS", { RMeDI, Iv64 } },
252b5132 980 /* c0 */
1ceb70f8
L		 981 { REG_TABLE (REG_C0) },
982 { REG_TABLE (REG_C1) },
ce518a5f
L		 983 { "retT", { Iw } },
984 { "retT", { XX } },
4e7d34a6
L		 985 { X86_64_TABLE (X86_64_C4) },
986 { X86_64_TABLE (X86_64_C5) },
1ceb70f8
L		 987 { REG_TABLE (REG_C6) },
988 { REG_TABLE (REG_C7) },
252b5132 989 /* c8 */
ce518a5f
L		 990 { "enterT", { Iw, Ib } },
991 { "leaveT", { XX } },
992 { "lretP", { Iw } },
993 { "lretP", { XX } },
994 { "int3", { XX } },
995 { "int", { Ib } },
4e7d34a6 996 { X86_64_TABLE (X86_64_CE) },
ce518a5f 997 { "iretP", { XX } },
252b5132 998 /* d0 */
1ceb70f8
L		 999 { REG_TABLE (REG_D0) },
1000 { REG_TABLE (REG_D1) },
1001 { REG_TABLE (REG_D2) },
1002 { REG_TABLE (REG_D3) },
4e7d34a6
L		 1003 { X86_64_TABLE (X86_64_D4) },
1004 { X86_64_TABLE (X86_64_D5) },
ce518a5f
L		 1005 { "(bad)", { XX } },
1006 { "xlat", { DSBX } },
252b5132
RH		 1007 /* d8 */
1008 { FLOAT },
1009 { FLOAT },
1010 { FLOAT },
1011 { FLOAT },
1012 { FLOAT },
1013 { FLOAT },
1014 { FLOAT },
1015 { FLOAT },
1016 /* e0 */
ce518a5f
L		 1017 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
1018 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
1019 { "loopFH", { Jb, XX, loop_jcxz_flag } },
1020 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
1021 { "inB", { AL, Ib } },
1022 { "inG", { zAX, Ib } },
1023 { "outB", { Ib, AL } },
1024 { "outG", { Ib, zAX } },
252b5132 1025 /* e8 */
ce518a5f
L		 1026 { "callT", { Jv } },
1027 { "jmpT", { Jv } },
4e7d34a6 1028 { X86_64_TABLE (X86_64_EA) },
ce518a5f
L		 1029 { "jmp", { Jb } },
1030 { "inB", { AL, indirDX } },
1031 { "inG", { zAX, indirDX } },
1032 { "outB", { indirDX, AL } },
1033 { "outG", { indirDX, zAX } },
252b5132 1034 /* f0 */
ce518a5f
L		 1035 { "(bad)", { XX } }, /* lock prefix */
1036 { "icebp", { XX } },
1037 { "(bad)", { XX } }, /* repne */
1038 { "(bad)", { XX } }, /* repz */
1039 { "hlt", { XX } },
1040 { "cmc", { XX } },
1ceb70f8
L		 1041 { REG_TABLE (REG_F6) },
1042 { REG_TABLE (REG_F7) },
252b5132 1043 /* f8 */
ce518a5f
L		 1044 { "clc", { XX } },
1045 { "stc", { XX } },
1046 { "cli", { XX } },
1047 { "sti", { XX } },
1048 { "cld", { XX } },
1049 { "std", { XX } },
1ceb70f8
L		 1050 { REG_TABLE (REG_FE) },
1051 { REG_TABLE (REG_FF) },
252b5132
RH		 1052};
1053
6439fc28 1054static const struct dis386 dis386_twobyte[] = {
252b5132 1055 /* 00 */
1ceb70f8
L		 1056 { REG_TABLE (REG_0F00 ) },
1057 { REG_TABLE (REG_0F01 ) },
ce518a5f
L		 1058 { "larS", { Gv, Ew } },
1059 { "lslS", { Gv, Ew } },
1060 { "(bad)", { XX } },
1061 { "syscall", { XX } },
1062 { "clts", { XX } },
1063 { "sysretP", { XX } },
252b5132 1064 /* 08 */
ce518a5f
L		 1065 { "invd", { XX } },
1066 { "wbinvd", { XX } },
1067 { "(bad)", { XX } },
1068 { "ud2a", { XX } },
1069 { "(bad)", { XX } },
b5b1fc4f 1070 { REG_TABLE (REG_0F0D) },
ce518a5f
L		 1071 { "femms", { XX } },
1072 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
252b5132 1073 /* 10 */
1ceb70f8
L		 1074 { PREFIX_TABLE (PREFIX_0F10) },
1075 { PREFIX_TABLE (PREFIX_0F11) },
1076 { PREFIX_TABLE (PREFIX_0F12) },
1077 { MOD_TABLE (MOD_0F13) },
f2a421c4
L		 1078 { "unpcklpX", { XM, EXx } },
1079 { "unpckhpX", { XM, EXx } },
1ceb70f8
L		 1080 { PREFIX_TABLE (PREFIX_0F16) },
1081 { MOD_TABLE (MOD_0F17) },
252b5132 1082 /* 18 */
1ceb70f8 1083 { REG_TABLE (REG_0F18) },
b5b1fc4f
L		 1084 { "nopQ", { Ev } },
1085 { "nopQ", { Ev } },
1086 { "nopQ", { Ev } },
1087 { "nopQ", { Ev } },
1088 { "nopQ", { Ev } },
1089 { "nopQ", { Ev } },
ce518a5f 1090 { "nopQ", { Ev } },
252b5132 1091 /* 20 */
1ceb70f8
L		 1092 { MOD_TABLE (MOD_0F20) },
1093 { MOD_TABLE (MOD_0F21) },
1094 { MOD_TABLE (MOD_0F22) },
1095 { MOD_TABLE (MOD_0F23) },
1096 { MOD_TABLE (MOD_0F24) },
4e7d34a6 1097 { THREE_BYTE_TABLE (THREE_BYTE_0F25) },
1ceb70f8 1098 { MOD_TABLE (MOD_0F26) },
ce518a5f 1099 { "(bad)", { XX } },
252b5132 1100 /* 28 */
09a2c6cf 1101 { "movapX", { XM, EXx } },
d5d7db8e 1102 { "movapX", { EXx, XM } },
1ceb70f8
L		 1103 { PREFIX_TABLE (PREFIX_0F2A) },
1104 { PREFIX_TABLE (PREFIX_0F2B) },
1105 { PREFIX_TABLE (PREFIX_0F2C) },
1106 { PREFIX_TABLE (PREFIX_0F2D) },
1107 { PREFIX_TABLE (PREFIX_0F2E) },
1108 { PREFIX_TABLE (PREFIX_0F2F) },
252b5132 1109 /* 30 */
ce518a5f
L		 1110 { "wrmsr", { XX } },
1111 { "rdtsc", { XX } },
1112 { "rdmsr", { XX } },
1113 { "rdpmc", { XX } },
1114 { "sysenter", { XX } },
1115 { "sysexit", { XX } },
1116 { "(bad)", { XX } },
47dd174c 1117 { "getsec", { XX } },
252b5132 1118 /* 38 */
4e7d34a6 1119 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
ce518a5f 1120 { "(bad)", { XX } },
4e7d34a6 1121 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
ce518a5f
L		 1122 { "(bad)", { XX } },
1123 { "(bad)", { XX } },
1124 { "(bad)", { XX } },
1125 { "(bad)", { XX } },
1126 { "(bad)", { XX } },
252b5132 1127 /* 40 */
ce518a5f
L		 1128 { "cmovo", { Gv, Ev } },
1129 { "cmovno", { Gv, Ev } },
1130 { "cmovb", { Gv, Ev } },
1131 { "cmovae", { Gv, Ev } },
1132 { "cmove", { Gv, Ev } },
1133 { "cmovne", { Gv, Ev } },
1134 { "cmovbe", { Gv, Ev } },
1135 { "cmova", { Gv, Ev } },
252b5132 1136 /* 48 */
ce518a5f
L		 1137 { "cmovs", { Gv, Ev } },
1138 { "cmovns", { Gv, Ev } },
1139 { "cmovp", { Gv, Ev } },
1140 { "cmovnp", { Gv, Ev } },
1141 { "cmovl", { Gv, Ev } },
1142 { "cmovge", { Gv, Ev } },
1143 { "cmovle", { Gv, Ev } },
1144 { "cmovg", { Gv, Ev } },
252b5132 1145 /* 50 */
75c135a8 1146 { MOD_TABLE (MOD_0F51) },
1ceb70f8
L		 1147 { PREFIX_TABLE (PREFIX_0F51) },
1148 { PREFIX_TABLE (PREFIX_0F52) },
1149 { PREFIX_TABLE (PREFIX_0F53) },
09a2c6cf
L		 1150 { "andpX", { XM, EXx } },
1151 { "andnpX", { XM, EXx } },
1152 { "orpX", { XM, EXx } },
1153 { "xorpX", { XM, EXx } },
252b5132 1154 /* 58 */
1ceb70f8
L		 1155 { PREFIX_TABLE (PREFIX_0F58) },
1156 { PREFIX_TABLE (PREFIX_0F59) },
1157 { PREFIX_TABLE (PREFIX_0F5A) },
1158 { PREFIX_TABLE (PREFIX_0F5B) },
1159 { PREFIX_TABLE (PREFIX_0F5C) },
1160 { PREFIX_TABLE (PREFIX_0F5D) },
1161 { PREFIX_TABLE (PREFIX_0F5E) },
1162 { PREFIX_TABLE (PREFIX_0F5F) },
252b5132 1163 /* 60 */
1ceb70f8
L		 1164 { PREFIX_TABLE (PREFIX_0F60) },
1165 { PREFIX_TABLE (PREFIX_0F61) },
1166 { PREFIX_TABLE (PREFIX_0F62) },
ce518a5f
L		 1167 { "packsswb", { MX, EM } },
1168 { "pcmpgtb", { MX, EM } },
1169 { "pcmpgtw", { MX, EM } },
1170 { "pcmpgtd", { MX, EM } },
1171 { "packuswb", { MX, EM } },
252b5132 1172 /* 68 */
ce518a5f
L		 1173 { "punpckhbw", { MX, EM } },
1174 { "punpckhwd", { MX, EM } },
1175 { "punpckhdq", { MX, EM } },
1176 { "packssdw", { MX, EM } },
1ceb70f8
L		 1177 { PREFIX_TABLE (PREFIX_0F6C) },
1178 { PREFIX_TABLE (PREFIX_0F6D) },
231af070 1179 { "movK", { MX, Edq } },
1ceb70f8 1180 { PREFIX_TABLE (PREFIX_0F6F) },
252b5132 1181 /* 70 */
1ceb70f8
L		 1182 { PREFIX_TABLE (PREFIX_0F70) },
1183 { REG_TABLE (REG_0F71) },
1184 { REG_TABLE (REG_0F72) },
1185 { REG_TABLE (REG_0F73) },
ce518a5f
L		 1186 { "pcmpeqb", { MX, EM } },
1187 { "pcmpeqw", { MX, EM } },
1188 { "pcmpeqd", { MX, EM } },
1189 { "emms", { XX } },
252b5132 1190 /* 78 */
1ceb70f8
L		 1191 { PREFIX_TABLE (PREFIX_0F78) },
1192 { PREFIX_TABLE (PREFIX_0F79) },
4e7d34a6 1193 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
89b66d55 1194 { THREE_BYTE_TABLE (THREE_BYTE_0F7B) },
1ceb70f8
L		 1195 { PREFIX_TABLE (PREFIX_0F7C) },
1196 { PREFIX_TABLE (PREFIX_0F7D) },
1197 { PREFIX_TABLE (PREFIX_0F7E) },
1198 { PREFIX_TABLE (PREFIX_0F7F) },
252b5132 1199 /* 80 */
ce518a5f
L		 1200 { "joH", { Jv, XX, cond_jump_flag } },
1201 { "jnoH", { Jv, XX, cond_jump_flag } },
1202 { "jbH", { Jv, XX, cond_jump_flag } },
1203 { "jaeH", { Jv, XX, cond_jump_flag } },
1204 { "jeH", { Jv, XX, cond_jump_flag } },
1205 { "jneH", { Jv, XX, cond_jump_flag } },
1206 { "jbeH", { Jv, XX, cond_jump_flag } },
1207 { "jaH", { Jv, XX, cond_jump_flag } },
252b5132 1208 /* 88 */
ce518a5f
L		 1209 { "jsH", { Jv, XX, cond_jump_flag } },
1210 { "jnsH", { Jv, XX, cond_jump_flag } },
1211 { "jpH", { Jv, XX, cond_jump_flag } },
1212 { "jnpH", { Jv, XX, cond_jump_flag } },
1213 { "jlH", { Jv, XX, cond_jump_flag } },
1214 { "jgeH", { Jv, XX, cond_jump_flag } },
1215 { "jleH", { Jv, XX, cond_jump_flag } },
1216 { "jgH", { Jv, XX, cond_jump_flag } },
252b5132 1217 /* 90 */
ce518a5f
L		 1218 { "seto", { Eb } },
1219 { "setno", { Eb } },
1220 { "setb", { Eb } },
1221 { "setae", { Eb } },
1222 { "sete", { Eb } },
1223 { "setne", { Eb } },
1224 { "setbe", { Eb } },
1225 { "seta", { Eb } },
252b5132 1226 /* 98 */
ce518a5f
L		 1227 { "sets", { Eb } },
1228 { "setns", { Eb } },
1229 { "setp", { Eb } },
1230 { "setnp", { Eb } },
1231 { "setl", { Eb } },
1232 { "setge", { Eb } },
1233 { "setle", { Eb } },
1234 { "setg", { Eb } },
252b5132 1235 /* a0 */
ce518a5f
L		 1236 { "pushT", { fs } },
1237 { "popT", { fs } },
1238 { "cpuid", { XX } },
1239 { "btS", { Ev, Gv } },
1240 { "shldS", { Ev, Gv, Ib } },
1241 { "shldS", { Ev, Gv, CL } },
1ceb70f8
L		 1242 { REG_TABLE (REG_0FA6) },
1243 { REG_TABLE (REG_0FA7) },
252b5132 1244 /* a8 */
ce518a5f
L		 1245 { "pushT", { gs } },
1246 { "popT", { gs } },
1247 { "rsm", { XX } },
1248 { "btsS", { Ev, Gv } },
1249 { "shrdS", { Ev, Gv, Ib } },
1250 { "shrdS", { Ev, Gv, CL } },
1ceb70f8 1251 { REG_TABLE (REG_0FAE) },
ce518a5f 1252 { "imulS", { Gv, Ev } },
252b5132 1253 /* b0 */
ce518a5f
L		 1254 { "cmpxchgB", { Eb, Gb } },
1255 { "cmpxchgS", { Ev, Gv } },
1ceb70f8 1256 { MOD_TABLE (MOD_0FB2) },
ce518a5f 1257 { "btrS", { Ev, Gv } },
1ceb70f8
L		 1258 { MOD_TABLE (MOD_0FB4) },
1259 { MOD_TABLE (MOD_0FB5) },
7c52e0e8
L		 1260 { "movz{bR|x}", { Gv, Eb } },
1261 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
252b5132 1262 /* b8 */
1ceb70f8 1263 { PREFIX_TABLE (PREFIX_0FB8) },
ce518a5f 1264 { "ud2b", { XX } },
1ceb70f8 1265 { REG_TABLE (REG_0FBA) },
ce518a5f
L		 1266 { "btcS", { Ev, Gv } },
1267 { "bsfS", { Gv, Ev } },
1ceb70f8 1268 { PREFIX_TABLE (PREFIX_0FBD) },
7c52e0e8
L		 1269 { "movs{bR|x}", { Gv, Eb } },
1270 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
252b5132 1271 /* c0 */
ce518a5f
L		 1272 { "xaddB", { Eb, Gb } },
1273 { "xaddS", { Ev, Gv } },
1ceb70f8 1274 { PREFIX_TABLE (PREFIX_0FC2) },
ce518a5f
L		 1275 { "movntiS", { Ev, Gv } },
1276 { "pinsrw", { MX, Edqw, Ib } },
1277 { "pextrw", { Gdq, MS, Ib } },
09a2c6cf 1278 { "shufpX", { XM, EXx, Ib } },
1ceb70f8 1279 { REG_TABLE (REG_0FC7) },
252b5132 1280 /* c8 */
ce518a5f
L		 1281 { "bswap", { RMeAX } },
1282 { "bswap", { RMeCX } },
1283 { "bswap", { RMeDX } },
1284 { "bswap", { RMeBX } },
1285 { "bswap", { RMeSP } },
1286 { "bswap", { RMeBP } },
1287 { "bswap", { RMeSI } },
1288 { "bswap", { RMeDI } },
252b5132 1289 /* d0 */
1ceb70f8 1290 { PREFIX_TABLE (PREFIX_0FD0) },
ce518a5f
L		 1291 { "psrlw", { MX, EM } },
1292 { "psrld", { MX, EM } },
1293 { "psrlq", { MX, EM } },
1294 { "paddq", { MX, EM } },
1295 { "pmullw", { MX, EM } },
1ceb70f8 1296 { PREFIX_TABLE (PREFIX_0FD6) },
75c135a8 1297 { MOD_TABLE (MOD_0FD7) },
252b5132 1298 /* d8 */
ce518a5f
L		 1299 { "psubusb", { MX, EM } },
1300 { "psubusw", { MX, EM } },
1301 { "pminub", { MX, EM } },
1302 { "pand", { MX, EM } },
1303 { "paddusb", { MX, EM } },
1304 { "paddusw", { MX, EM } },
1305 { "pmaxub", { MX, EM } },
1306 { "pandn", { MX, EM } },
252b5132 1307 /* e0 */
ce518a5f
L		 1308 { "pavgb", { MX, EM } },
1309 { "psraw", { MX, EM } },
1310 { "psrad", { MX, EM } },
1311 { "pavgw", { MX, EM } },
1312 { "pmulhuw", { MX, EM } },
1313 { "pmulhw", { MX, EM } },
1ceb70f8
L		 1314 { PREFIX_TABLE (PREFIX_0FE6) },
1315 { PREFIX_TABLE (PREFIX_0FE7) },
252b5132 1316 /* e8 */
ce518a5f
L		 1317 { "psubsb", { MX, EM } },
1318 { "psubsw", { MX, EM } },
1319 { "pminsw", { MX, EM } },
1320 { "por", { MX, EM } },
1321 { "paddsb", { MX, EM } },
1322 { "paddsw", { MX, EM } },
1323 { "pmaxsw", { MX, EM } },
1324 { "pxor", { MX, EM } },
252b5132 1325 /* f0 */
1ceb70f8 1326 { PREFIX_TABLE (PREFIX_0FF0) },
ce518a5f
L		 1327 { "psllw", { MX, EM } },
1328 { "pslld", { MX, EM } },
1329 { "psllq", { MX, EM } },
1330 { "pmuludq", { MX, EM } },
1331 { "pmaddwd", { MX, EM } },
1332 { "psadbw", { MX, EM } },
1ceb70f8 1333 { PREFIX_TABLE (PREFIX_0FF7) },
252b5132 1334 /* f8 */
ce518a5f
L		 1335 { "psubb", { MX, EM } },
1336 { "psubw", { MX, EM } },
1337 { "psubd", { MX, EM } },
1338 { "psubq", { MX, EM } },
1339 { "paddb", { MX, EM } },
1340 { "paddw", { MX, EM } },
1341 { "paddd", { MX, EM } },
1342 { "(bad)", { XX } },
252b5132
RH		 1343};
1344
1345static const unsigned char onebyte_has_modrm[256] = {
c608c12e
AM		 1346 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1347 /* ------------------------------- */
1348 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1349 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1350 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1351 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1352 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1353 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1354 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1355 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1356 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1357 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1358 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1359 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1360 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1361 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1362 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1363 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1364 /* ------------------------------- */
1365 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
252b5132
RH		 1366};
1367
1368static const unsigned char twobyte_has_modrm[256] = {
c608c12e
AM		 1369 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1370 /* ------------------------------- */
252b5132 1371 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
b5b1fc4f 1372 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
85f10a01 1373 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
331d2d0d 1374 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
252b5132 1375 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
4bba6815
AM		 1376 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1377 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
85f10a01 1378 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
252b5132
RH		 1379 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1380 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
30d1c836 1381 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
050dfa73 1382 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
252b5132 1383 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
ca164297 1384 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
4bba6815 1385 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
ca164297 1386 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
c608c12e
AM		 1387 /* ------------------------------- */
1388 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1389};
1390
252b5132
RH		 1391static char obuf[100];
1392static char *obufp;
1393static char scratchbuf[100];
1394static unsigned char *start_codep;
1395static unsigned char *insn_codep;
1396static unsigned char *codep;
b844680a
L		 1397static const char *lock_prefix;
1398static const char *data_prefix;
1399static const char *addr_prefix;
1400static const char *repz_prefix;
1401static const char *repnz_prefix;
252b5132 1402static disassemble_info *the_info;
7967e09e
L		 1403static struct
1404 {
1405 int mod;
7967e09e 1406 int reg;
484c222e 1407 int rm;
7967e09e
L		 1408 }
1409modrm;
4bba6815 1410static unsigned char need_modrm;
252b5132 1411
4bba6815
AM		 1412/* If we are accessing mod/rm/reg without need_modrm set, then the
1413 values are stale. Hitting this abort likely indicates that you
1414 need to update onebyte_has_modrm or twobyte_has_modrm. */
1415#define MODRM_CHECK if (!need_modrm) abort ()
1416
d708bcba
AM		 1417static const char **names64;
1418static const char **names32;
1419static const char **names16;
1420static const char **names8;
1421static const char **names8rex;
1422static const char **names_seg;
db51cc60
L		 1423static const char *index64;
1424static const char *index32;
d708bcba
AM		 1425static const char **index16;
1426
1427static const char *intel_names64[] = {
1428 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
1429 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
1430};
1431static const char *intel_names32[] = {
1432 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
1433 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
1434};
1435static const char *intel_names16[] = {
1436 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
1437 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
1438};
1439static const char *intel_names8[] = {
1440 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
1441};
1442static const char *intel_names8rex[] = {
1443 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
1444 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
1445};
1446static const char *intel_names_seg[] = {
1447 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
1448};
db51cc60
L		 1449static const char *intel_index64 = "riz";
1450static const char *intel_index32 = "eiz";
d708bcba
AM		 1451static const char *intel_index16[] = {
1452 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
1453};
1454
1455static const char *att_names64[] = {
1456 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
52b15da3
JH		 1457 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
1458};
d708bcba
AM		 1459static const char *att_names32[] = {
1460 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
52b15da3 1461 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
252b5132 1462};
d708bcba
AM		 1463static const char *att_names16[] = {
1464 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
52b15da3 1465 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
252b5132 1466};
d708bcba
AM		 1467static const char *att_names8[] = {
1468 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
252b5132 1469};
d708bcba
AM		 1470static const char *att_names8rex[] = {
1471 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
52b15da3
JH		 1472 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
1473};
d708bcba
AM		 1474static const char *att_names_seg[] = {
1475 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
252b5132 1476};
db51cc60
L		 1477static const char *att_index64 = "%riz";
1478static const char *att_index32 = "%eiz";
d708bcba
AM		 1479static const char *att_index16[] = {
1480 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
252b5132
RH		 1481};
1482
1ceb70f8
L		 1483static const struct dis386 reg_table[][8] = {
1484 /* REG_80 */
252b5132 1485 {
ce518a5f
L		 1486 { "addA", { Eb, Ib } },
1487 { "orA", { Eb, Ib } },
1488 { "adcA", { Eb, Ib } },
1489 { "sbbA", { Eb, Ib } },
1490 { "andA", { Eb, Ib } },
1491 { "subA", { Eb, Ib } },
1492 { "xorA", { Eb, Ib } },
1493 { "cmpA", { Eb, Ib } },
252b5132 1494 },
1ceb70f8 1495 /* REG_81 */
252b5132 1496 {
ce518a5f
L		 1497 { "addQ", { Ev, Iv } },
1498 { "orQ", { Ev, Iv } },
1499 { "adcQ", { Ev, Iv } },
1500 { "sbbQ", { Ev, Iv } },
1501 { "andQ", { Ev, Iv } },
1502 { "subQ", { Ev, Iv } },
1503 { "xorQ", { Ev, Iv } },
1504 { "cmpQ", { Ev, Iv } },
252b5132 1505 },
1ceb70f8 1506 /* REG_82 */
252b5132 1507 {
ce518a5f
L		 1508 { "addQ", { Ev, sIb } },
1509 { "orQ", { Ev, sIb } },
1510 { "adcQ", { Ev, sIb } },
1511 { "sbbQ", { Ev, sIb } },
1512 { "andQ", { Ev, sIb } },
1513 { "subQ", { Ev, sIb } },
1514 { "xorQ", { Ev, sIb } },
1515 { "cmpQ", { Ev, sIb } },
252b5132 1516 },
1ceb70f8 1517 /* REG_8F */
4e7d34a6
L		 1518 {
1519 { "popU", { stackEv } },
1520 { "(bad)", { XX } },
1521 { "(bad)", { XX } },
1522 { "(bad)", { XX } },
1523 { "(bad)", { XX } },
1524 { "(bad)", { XX } },
1525 { "(bad)", { XX } },
1526 { "(bad)", { XX } },
1527 },
1ceb70f8 1528 /* REG_C0 */
252b5132 1529 {
ce518a5f
L		 1530 { "rolA", { Eb, Ib } },
1531 { "rorA", { Eb, Ib } },
1532 { "rclA", { Eb, Ib } },
1533 { "rcrA", { Eb, Ib } },
1534 { "shlA", { Eb, Ib } },
1535 { "shrA", { Eb, Ib } },
1536 { "(bad)", { XX } },
1537 { "sarA", { Eb, Ib } },
252b5132 1538 },
1ceb70f8 1539 /* REG_C1 */
252b5132 1540 {
ce518a5f
L		 1541 { "rolQ", { Ev, Ib } },
1542 { "rorQ", { Ev, Ib } },
1543 { "rclQ", { Ev, Ib } },
1544 { "rcrQ", { Ev, Ib } },
1545 { "shlQ", { Ev, Ib } },
1546 { "shrQ", { Ev, Ib } },
1547 { "(bad)", { XX } },
1548 { "sarQ", { Ev, Ib } },
252b5132 1549 },
1ceb70f8 1550 /* REG_C6 */
4e7d34a6
L		 1551 {
1552 { "movA", { Eb, Ib } },
1553 { "(bad)", { XX } },
1554 { "(bad)", { XX } },
1555 { "(bad)", { XX } },
1556 { "(bad)", { XX } },
1557 { "(bad)", { XX } },
1558 { "(bad)", { XX } },
1559 { "(bad)", { XX } },
1560 },
1ceb70f8 1561 /* REG_C7 */
4e7d34a6
L		 1562 {
1563 { "movQ", { Ev, Iv } },
1564 { "(bad)", { XX } },
1565 { "(bad)", { XX } },
1566 { "(bad)", { XX } },
1567 { "(bad)", { XX } },
1568 { "(bad)", { XX } },
1569 { "(bad)", { XX } },
1570 { "(bad)", { XX } },
1571 },
1ceb70f8 1572 /* REG_D0 */
252b5132 1573 {
ce518a5f
L		 1574 { "rolA", { Eb, I1 } },
1575 { "rorA", { Eb, I1 } },
1576 { "rclA", { Eb, I1 } },
1577 { "rcrA", { Eb, I1 } },
1578 { "shlA", { Eb, I1 } },
1579 { "shrA", { Eb, I1 } },
1580 { "(bad)", { XX } },
1581 { "sarA", { Eb, I1 } },
252b5132 1582 },
1ceb70f8 1583 /* REG_D1 */
252b5132 1584 {
ce518a5f
L		 1585 { "rolQ", { Ev, I1 } },
1586 { "rorQ", { Ev, I1 } },
1587 { "rclQ", { Ev, I1 } },
1588 { "rcrQ", { Ev, I1 } },
1589 { "shlQ", { Ev, I1 } },
1590 { "shrQ", { Ev, I1 } },
1591 { "(bad)", { XX } },
1592 { "sarQ", { Ev, I1 } },
252b5132 1593 },
1ceb70f8 1594 /* REG_D2 */
252b5132 1595 {
ce518a5f
L		 1596 { "rolA", { Eb, CL } },
1597 { "rorA", { Eb, CL } },
1598 { "rclA", { Eb, CL } },
1599 { "rcrA", { Eb, CL } },
1600 { "shlA", { Eb, CL } },
1601 { "shrA", { Eb, CL } },
1602 { "(bad)", { XX } },
1603 { "sarA", { Eb, CL } },
252b5132 1604 },
1ceb70f8 1605 /* REG_D3 */
252b5132 1606 {
ce518a5f
L		 1607 { "rolQ", { Ev, CL } },
1608 { "rorQ", { Ev, CL } },
1609 { "rclQ", { Ev, CL } },
1610 { "rcrQ", { Ev, CL } },
1611 { "shlQ", { Ev, CL } },
1612 { "shrQ", { Ev, CL } },
1613 { "(bad)", { XX } },
1614 { "sarQ", { Ev, CL } },
252b5132 1615 },
1ceb70f8 1616 /* REG_F6 */
252b5132 1617 {
ce518a5f 1618 { "testA", { Eb, Ib } },
058f233b 1619 { "(bad)", { XX } },
ce518a5f
L		 1620 { "notA", { Eb } },
1621 { "negA", { Eb } },
1622 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
1623 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
1624 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
1625 { "idivA", { Eb } }, /* and idiv for consistency. */
252b5132 1626 },
1ceb70f8 1627 /* REG_F7 */
252b5132 1628 {
ce518a5f
L		 1629 { "testQ", { Ev, Iv } },
1630 { "(bad)", { XX } },
1631 { "notQ", { Ev } },
1632 { "negQ", { Ev } },
1633 { "mulQ", { Ev } }, /* Don't print the implicit register. */
1634 { "imulQ", { Ev } },
1635 { "divQ", { Ev } },
1636 { "idivQ", { Ev } },
252b5132 1637 },
1ceb70f8 1638 /* REG_FE */
252b5132 1639 {
ce518a5f
L		 1640 { "incA", { Eb } },
1641 { "decA", { Eb } },
1642 { "(bad)", { XX } },
1643 { "(bad)", { XX } },
1644 { "(bad)", { XX } },
1645 { "(bad)", { XX } },
1646 { "(bad)", { XX } },
1647 { "(bad)", { XX } },
252b5132 1648 },
1ceb70f8 1649 /* REG_FF */
252b5132 1650 {
ce518a5f
L		 1651 { "incQ", { Ev } },
1652 { "decQ", { Ev } },
1653 { "callT", { indirEv } },
1654 { "JcallT", { indirEp } },
1655 { "jmpT", { indirEv } },
1656 { "JjmpT", { indirEp } },
1657 { "pushU", { stackEv } },
1658 { "(bad)", { XX } },
252b5132 1659 },
1ceb70f8 1660 /* REG_0F00 */
252b5132 1661 {
ce518a5f
L		 1662 { "sldtD", { Sv } },
1663 { "strD", { Sv } },
1664 { "lldt", { Ew } },
1665 { "ltr", { Ew } },
1666 { "verr", { Ew } },
1667 { "verw", { Ew } },
1668 { "(bad)", { XX } },
1669 { "(bad)", { XX } },
252b5132 1670 },
1ceb70f8 1671 /* REG_0F01 */
252b5132 1672 {
1ceb70f8
L		 1673 { MOD_TABLE (MOD_0F01_REG_0) },
1674 { MOD_TABLE (MOD_0F01_REG_1) },
1675 { MOD_TABLE (MOD_0F01_REG_2) },
1676 { MOD_TABLE (MOD_0F01_REG_3) },
ce518a5f
L		 1677 { "smswD", { Sv } },
1678 { "(bad)", { XX } },
1679 { "lmsw", { Ew } },
1ceb70f8 1680 { MOD_TABLE (MOD_0F01_REG_7) },
252b5132 1681 },
b5b1fc4f 1682 /* REG_0F0D */
252b5132 1683 {
4e7d34a6
L		 1684 { "prefetch", { Eb } },
1685 { "prefetchw", { Eb } },
1686 { "(bad)", { XX } },
1687 { "(bad)", { XX } },
1688 { "(bad)", { XX } },
1689 { "(bad)", { XX } },
1690 { "(bad)", { XX } },
1691 { "(bad)", { XX } },
252b5132 1692 },
1ceb70f8 1693 /* REG_0F18 */
252b5132 1694 {
1ceb70f8
L		 1695 { MOD_TABLE (MOD_0F18_REG_0) },
1696 { MOD_TABLE (MOD_0F18_REG_1) },
1697 { MOD_TABLE (MOD_0F18_REG_2) },
1698 { MOD_TABLE (MOD_0F18_REG_3) },
ce518a5f
L		 1699 { "(bad)", { XX } },
1700 { "(bad)", { XX } },
1701 { "(bad)", { XX } },
1702 { "(bad)", { XX } },
252b5132 1703 },
1ceb70f8 1704 /* REG_0F71 */
a6bd098c 1705 {
ce518a5f
L		 1706 { "(bad)", { XX } },
1707 { "(bad)", { XX } },
1ceb70f8 1708 { MOD_TABLE (MOD_0F71_REG_2) },
ce518a5f 1709 { "(bad)", { XX } },
1ceb70f8 1710 { MOD_TABLE (MOD_0F71_REG_4) },
ce518a5f 1711 { "(bad)", { XX } },
1ceb70f8 1712 { MOD_TABLE (MOD_0F71_REG_6) },
ce518a5f 1713 { "(bad)", { XX } },
a6bd098c 1714 },
1ceb70f8 1715 /* REG_0F72 */
a6bd098c 1716 {
ce518a5f
L		 1717 { "(bad)", { XX } },
1718 { "(bad)", { XX } },
1ceb70f8 1719 { MOD_TABLE (MOD_0F72_REG_2) },
ce518a5f 1720 { "(bad)", { XX } },
1ceb70f8 1721 { MOD_TABLE (MOD_0F72_REG_4) },
ce518a5f 1722 { "(bad)", { XX } },
1ceb70f8 1723 { MOD_TABLE (MOD_0F72_REG_6) },
ce518a5f 1724 { "(bad)", { XX } },
a6bd098c 1725 },
1ceb70f8 1726 /* REG_0F73 */
252b5132 1727 {
ce518a5f
L		 1728 { "(bad)", { XX } },
1729 { "(bad)", { XX } },
1ceb70f8
L		 1730 { MOD_TABLE (MOD_0F73_REG_2) },
1731 { MOD_TABLE (MOD_0F73_REG_3) },
ce518a5f 1732 { "(bad)", { XX } },
ce518a5f 1733 { "(bad)", { XX } },
1ceb70f8
L		 1734 { MOD_TABLE (MOD_0F73_REG_6) },
1735 { MOD_TABLE (MOD_0F73_REG_7) },
252b5132 1736 },
1ceb70f8 1737 /* REG_0FA6 */
252b5132 1738 {
4e7d34a6
L		 1739 { "montmul", { { OP_0f07, 0 } } },
1740 { "xsha1", { { OP_0f07, 0 } } },
1741 { "xsha256", { { OP_0f07, 0 } } },
1742 { "(bad)", { { OP_0f07, 0 } } },
1743 { "(bad)", { { OP_0f07, 0 } } },
1744 { "(bad)", { { OP_0f07, 0 } } },
1745 { "(bad)", { { OP_0f07, 0 } } },
1746 { "(bad)", { { OP_0f07, 0 } } },
1747 },
1ceb70f8 1748 /* REG_0FA7 */
4e7d34a6
L		 1749 {
1750 { "xstore-rng", { { OP_0f07, 0 } } },
1751 { "xcrypt-ecb", { { OP_0f07, 0 } } },
1752 { "xcrypt-cbc", { { OP_0f07, 0 } } },
1753 { "xcrypt-ctr", { { OP_0f07, 0 } } },
1754 { "xcrypt-cfb", { { OP_0f07, 0 } } },
1755 { "xcrypt-ofb", { { OP_0f07, 0 } } },
1756 { "(bad)", { { OP_0f07, 0 } } },
1757 { "(bad)", { { OP_0f07, 0 } } },
1758 },
1ceb70f8 1759 /* REG_0FAE */
4e7d34a6 1760 {
1ceb70f8
L		 1761 { MOD_TABLE (MOD_0FAE_REG_0) },
1762 { MOD_TABLE (MOD_0FAE_REG_1) },
1763 { MOD_TABLE (MOD_0FAE_REG_2) },
1764 { MOD_TABLE (MOD_0FAE_REG_3) },
ce518a5f 1765 { "(bad)", { XX } },
1ceb70f8
L		 1766 { MOD_TABLE (MOD_0FAE_REG_5) },
1767 { MOD_TABLE (MOD_0FAE_REG_6) },
1768 { MOD_TABLE (MOD_0FAE_REG_7) },
252b5132 1769 },
1ceb70f8 1770 /* REG_0FBA */
252b5132 1771 {
ce518a5f
L		 1772 { "(bad)", { XX } },
1773 { "(bad)", { XX } },
d8faab4e
L		 1774 { "(bad)", { XX } },
1775 { "(bad)", { XX } },
4e7d34a6
L		 1776 { "btQ", { Ev, Ib } },
1777 { "btsQ", { Ev, Ib } },
1778 { "btrQ", { Ev, Ib } },
1779 { "btcQ", { Ev, Ib } },
c608c12e 1780 },
1ceb70f8 1781 /* REG_0FC7 */
c608c12e 1782 {
b844680a 1783 { "(bad)", { XX } },
4e7d34a6 1784 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
d8faab4e 1785 { "(bad)", { XX } },
b844680a
L		 1786 { "(bad)", { XX } },
1787 { "(bad)", { XX } },
1788 { "(bad)", { XX } },
1ceb70f8
L		 1789 { MOD_TABLE (MOD_0FC7_REG_6) },
1790 { MOD_TABLE (MOD_0FC7_REG_7) },
252b5132 1791 },
4e7d34a6
L		 1792};
1793
1ceb70f8
L		 1794static const struct dis386 prefix_table[][4] = {
1795 /* PREFIX_90 */
252b5132 1796 {
4e7d34a6
L		 1797 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
1798 { "pause", { XX } },
1799 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
1800 { "(bad)", { XX } },
0f10071e 1801 },
4e7d34a6 1802
1ceb70f8 1803 /* PREFIX_0F10 */
cc0ec051 1804 {
4e7d34a6
L		 1805 { "movups", { XM, EXx } },
1806 { "movss", { XM, EXd } },
1807 { "movupd", { XM, EXx } },
1808 { "movsd", { XM, EXq } },
30d1c836 1809 },
4e7d34a6 1810
1ceb70f8 1811 /* PREFIX_0F11 */
30d1c836 1812 {
d5d7db8e
L		 1813 { "movups", { EXx, XM } },
1814 { "movss", { EXd, XM } },
1815 { "movupd", { EXx, XM } },
1816 { "movsd", { EXq, XM } },
4e7d34a6 1817 },
252b5132 1818
1ceb70f8 1819 /* PREFIX_0F12 */
c608c12e 1820 {
1ceb70f8 1821 { MOD_TABLE (MOD_0F12_PREFIX_0) },
4e7d34a6
L		 1822 { "movsldup", { XM, EXx } },
1823 { "movlpd", { XM, EXq } },
1824 { "movddup", { XM, EXq } },
c608c12e 1825 },
4e7d34a6 1826
1ceb70f8 1827 /* PREFIX_0F16 */
c608c12e 1828 {
1ceb70f8 1829 { MOD_TABLE (MOD_0F16_PREFIX_0) },
4e7d34a6
L		 1830 { "movshdup", { XM, EXx } },
1831 { "movhpd", { XM, EXq } },
058f233b 1832 { "(bad)", { XX } },
c608c12e 1833 },
4e7d34a6 1834
1ceb70f8 1835 /* PREFIX_0F2A */
c608c12e 1836 {
09335d05 1837 { "cvtpi2ps", { XM, EMCq } },
98b528ac 1838 { "cvtsi2ss%LQ", { XM, Ev } },
09335d05 1839 { "cvtpi2pd", { XM, EMCq } },
98b528ac 1840 { "cvtsi2sd%LQ", { XM, Ev } },
c608c12e 1841 },
4e7d34a6 1842
1ceb70f8 1843 /* PREFIX_0F2B */
c608c12e 1844 {
75c135a8
L		 1845 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
1846 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
1847 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
1848 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
c608c12e 1849 },
4e7d34a6 1850
1ceb70f8 1851 /* PREFIX_0F2C */
c608c12e 1852 {
09335d05
L		 1853 { "cvttps2pi", { MXC, EXq } },
1854 { "cvttss2siY", { Gv, EXd } },
09a2c6cf 1855 { "cvttpd2pi", { MXC, EXx } },
09335d05 1856 { "cvttsd2siY", { Gv, EXq } },
c608c12e 1857 },
4e7d34a6 1858
1ceb70f8 1859 /* PREFIX_0F2D */
c608c12e 1860 {
4e7d34a6
L		 1861 { "cvtps2pi", { MXC, EXq } },
1862 { "cvtss2siY", { Gv, EXd } },
1863 { "cvtpd2pi", { MXC, EXx } },
1864 { "cvtsd2siY", { Gv, EXq } },
c608c12e 1865 },
4e7d34a6 1866
1ceb70f8 1867 /* PREFIX_0F2E */
c608c12e 1868 {
4e7d34a6
L		 1869 { "ucomiss",{ XM, EXd } },
1870 { "(bad)", { XX } },
1871 { "ucomisd",{ XM, EXq } },
1872 { "(bad)", { XX } },
c608c12e 1873 },
4e7d34a6 1874
1ceb70f8 1875 /* PREFIX_0F2F */
c608c12e 1876 {
4e7d34a6
L		 1877 { "comiss", { XM, EXd } },
1878 { "(bad)", { XX } },
1879 { "comisd", { XM, EXq } },
1880 { "(bad)", { XX } },
c608c12e 1881 },
4e7d34a6 1882
1ceb70f8 1883 /* PREFIX_0F51 */
c608c12e 1884 {
4e7d34a6
L		 1885 { "sqrtps", { XM, EXx } },
1886 { "sqrtss", { XM, EXd } },
1887 { "sqrtpd", { XM, EXx } },
1888 { "sqrtsd", { XM, EXq } },
c608c12e 1889 },
4e7d34a6 1890
1ceb70f8 1891 /* PREFIX_0F52 */
c608c12e 1892 {
4e7d34a6
L		 1893 { "rsqrtps",{ XM, EXx } },
1894 { "rsqrtss",{ XM, EXd } },
058f233b
L		 1895 { "(bad)", { XX } },
1896 { "(bad)", { XX } },
c608c12e 1897 },
4e7d34a6 1898
1ceb70f8 1899 /* PREFIX_0F53 */
c608c12e 1900 {
4e7d34a6
L		 1901 { "rcpps", { XM, EXx } },
1902 { "rcpss", { XM, EXd } },
058f233b
L		 1903 { "(bad)", { XX } },
1904 { "(bad)", { XX } },
c608c12e 1905 },
4e7d34a6 1906
1ceb70f8 1907 /* PREFIX_0F58 */
c608c12e 1908 {
4e7d34a6
L		 1909 { "addps", { XM, EXx } },
1910 { "addss", { XM, EXd } },
1911 { "addpd", { XM, EXx } },
1912 { "addsd", { XM, EXq } },
c608c12e 1913 },
4e7d34a6 1914
1ceb70f8 1915 /* PREFIX_0F59 */
c608c12e 1916 {
4e7d34a6
L		 1917 { "mulps", { XM, EXx } },
1918 { "mulss", { XM, EXd } },
1919 { "mulpd", { XM, EXx } },
1920 { "mulsd", { XM, EXq } },
041bd2e0 1921 },
4e7d34a6 1922
1ceb70f8 1923 /* PREFIX_0F5A */
041bd2e0 1924 {
4e7d34a6
L		 1925 { "cvtps2pd", { XM, EXq } },
1926 { "cvtss2sd", { XM, EXd } },
1927 { "cvtpd2ps", { XM, EXx } },
1928 { "cvtsd2ss", { XM, EXq } },
041bd2e0 1929 },
4e7d34a6 1930
1ceb70f8 1931 /* PREFIX_0F5B */
041bd2e0 1932 {
09a2c6cf
L		 1933 { "cvtdq2ps", { XM, EXx } },
1934 { "cvttps2dq", { XM, EXx } },
1935 { "cvtps2dq", { XM, EXx } },
058f233b 1936 { "(bad)", { XX } },
041bd2e0 1937 },
4e7d34a6 1938
1ceb70f8 1939 /* PREFIX_0F5C */
041bd2e0 1940 {
4e7d34a6
L		 1941 { "subps", { XM, EXx } },
1942 { "subss", { XM, EXd } },
1943 { "subpd", { XM, EXx } },
1944 { "subsd", { XM, EXq } },
041bd2e0 1945 },
4e7d34a6 1946
1ceb70f8 1947 /* PREFIX_0F5D */
041bd2e0 1948 {
4e7d34a6
L		 1949 { "minps", { XM, EXx } },
1950 { "minss", { XM, EXd } },
1951 { "minpd", { XM, EXx } },
1952 { "minsd", { XM, EXq } },
041bd2e0 1953 },
4e7d34a6 1954
1ceb70f8 1955 /* PREFIX_0F5E */
041bd2e0 1956 {
4e7d34a6
L		 1957 { "divps", { XM, EXx } },
1958 { "divss", { XM, EXd } },
1959 { "divpd", { XM, EXx } },
1960 { "divsd", { XM, EXq } },
041bd2e0 1961 },
4e7d34a6 1962
1ceb70f8 1963 /* PREFIX_0F5F */
041bd2e0 1964 {
4e7d34a6
L		 1965 { "maxps", { XM, EXx } },
1966 { "maxss", { XM, EXd } },
1967 { "maxpd", { XM, EXx } },
1968 { "maxsd", { XM, EXq } },
041bd2e0 1969 },
4e7d34a6 1970
1ceb70f8 1971 /* PREFIX_0F60 */
041bd2e0 1972 {
4e7d34a6
L		 1973 { "punpcklbw",{ MX, EMd } },
1974 { "(bad)", { XX } },
1975 { "punpcklbw",{ MX, EMx } },
1976 { "(bad)", { XX } },
041bd2e0 1977 },
4e7d34a6 1978
1ceb70f8 1979 /* PREFIX_0F61 */
041bd2e0 1980 {
4e7d34a6
L		 1981 { "punpcklwd",{ MX, EMd } },
1982 { "(bad)", { XX } },
1983 { "punpcklwd",{ MX, EMx } },
1984 { "(bad)", { XX } },
041bd2e0 1985 },
4e7d34a6 1986
1ceb70f8 1987 /* PREFIX_0F62 */
041bd2e0 1988 {
4e7d34a6
L		 1989 { "punpckldq",{ MX, EMd } },
1990 { "(bad)", { XX } },
1991 { "punpckldq",{ MX, EMx } },
1992 { "(bad)", { XX } },
041bd2e0 1993 },
4e7d34a6 1994
1ceb70f8 1995 /* PREFIX_0F6C */
041bd2e0 1996 {
058f233b
L		 1997 { "(bad)", { XX } },
1998 { "(bad)", { XX } },
4e7d34a6 1999 { "punpcklqdq", { XM, EXx } },
058f233b 2000 { "(bad)", { XX } },
0f17484f 2001 },
4e7d34a6 2002
1ceb70f8 2003 /* PREFIX_0F6D */
0f17484f 2004 {
058f233b
L		 2005 { "(bad)", { XX } },
2006 { "(bad)", { XX } },
4e7d34a6 2007 { "punpckhqdq", { XM, EXx } },
058f233b 2008 { "(bad)", { XX } },
041bd2e0 2009 },
4e7d34a6 2010
1ceb70f8 2011 /* PREFIX_0F6F */
ca164297 2012 {
4e7d34a6
L		 2013 { "movq", { MX, EM } },
2014 { "movdqu", { XM, EXx } },
2015 { "movdqa", { XM, EXx } },
058f233b 2016 { "(bad)", { XX } },
ca164297 2017 },
4e7d34a6 2018
1ceb70f8 2019 /* PREFIX_0F70 */
4e7d34a6
L		 2020 {
2021 { "pshufw", { MX, EM, Ib } },
2022 { "pshufhw",{ XM, EXx, Ib } },
2023 { "pshufd", { XM, EXx, Ib } },
2024 { "pshuflw",{ XM, EXx, Ib } },
2025 },
2026
92fddf8e
L		 2027 /* PREFIX_0F73_REG_3 */
2028 {
2029 { "(bad)", { XX } },
2030 { "(bad)", { XX } },
2031 { "psrldq", { XS, Ib } },
2032 { "(bad)", { XX } },
2033 },
2034
2035 /* PREFIX_0F73_REG_7 */
2036 {
2037 { "(bad)", { XX } },
2038 { "(bad)", { XX } },
2039 { "pslldq", { XS, Ib } },
2040 { "(bad)", { XX } },
2041 },
2042
1ceb70f8 2043 /* PREFIX_0F78 */
4e7d34a6
L		 2044 {
2045 {"vmread", { Em, Gm } },
2046 {"(bad)", { XX } },
2047 {"extrq", { XS, Ib, Ib } },
2048 {"insertq", { XM, XS, Ib, Ib } },
2049 },
2050
1ceb70f8 2051 /* PREFIX_0F79 */
4e7d34a6
L		 2052 {
2053 {"vmwrite", { Gm, Em } },
2054 {"(bad)", { XX } },
2055 {"extrq", { XM, XS } },
2056 {"insertq", { XM, XS } },
2057 },
2058
1ceb70f8 2059 /* PREFIX_0F7C */
ca164297 2060 {
058f233b
L		 2061 { "(bad)", { XX } },
2062 { "(bad)", { XX } },
09a2c6cf
L		 2063 { "haddpd", { XM, EXx } },
2064 { "haddps", { XM, EXx } },
ca164297 2065 },
4e7d34a6 2066
1ceb70f8 2067 /* PREFIX_0F7D */
ca164297 2068 {
058f233b
L		 2069 { "(bad)", { XX } },
2070 { "(bad)", { XX } },
09a2c6cf
L		 2071 { "hsubpd", { XM, EXx } },
2072 { "hsubps", { XM, EXx } },
ca164297 2073 },
4e7d34a6 2074
1ceb70f8 2075 /* PREFIX_0F7E */
ca164297 2076 {
4e7d34a6
L		 2077 { "movK", { Edq, MX } },
2078 { "movq", { XM, EXq } },
2079 { "movK", { Edq, XM } },
058f233b 2080 { "(bad)", { XX } },
ca164297 2081 },
4e7d34a6 2082
1ceb70f8 2083 /* PREFIX_0F7F */
ca164297 2084 {
4e7d34a6 2085 { "movq", { EM, MX } },
d5d7db8e
L		 2086 { "movdqu", { EXx, XM } },
2087 { "movdqa", { EXx, XM } },
058f233b 2088 { "(bad)", { XX } },
ca164297 2089 },
4e7d34a6 2090
1ceb70f8 2091 /* PREFIX_0FB8 */
ca164297 2092 {
4e7d34a6
L		 2093 { "(bad)", { XX } },
2094 { "popcntS", { Gv, Ev } },
2095 { "(bad)", { XX } },
2096 { "(bad)", { XX } },
ca164297 2097 },
4e7d34a6 2098
1ceb70f8 2099 /* PREFIX_0FBD */
050dfa73 2100 {
4e7d34a6
L		 2101 { "bsrS", { Gv, Ev } },
2102 { "lzcntS", { Gv, Ev } },
2103 { "bsrS", { Gv, Ev } },
2104 { "(bad)", { XX } },
050dfa73
MM		 2105 },
2106
1ceb70f8 2107 /* PREFIX_0FC2 */
050dfa73 2108 {
ad19981d
L		 2109 { "cmpps", { XM, EXx, CMP } },
2110 { "cmpss", { XM, EXd, CMP } },
2111 { "cmppd", { XM, EXx, CMP } },
2112 { "cmpsd", { XM, EXq, CMP } },
050dfa73 2113 },
246c51aa 2114
92fddf8e
L		 2115 /* PREFIX_0FC7_REG_6 */
2116 {
2117 { "vmptrld",{ Mq } },
2118 { "vmxon", { Mq } },
2119 { "vmclear",{ Mq } },
2120 { "(bad)", { XX } },
2121 },
2122
1ceb70f8 2123 /* PREFIX_0FD0 */
050dfa73 2124 {
058f233b
L		 2125 { "(bad)", { XX } },
2126 { "(bad)", { XX } },
4e7d34a6
L		 2127 { "addsubpd", { XM, EXx } },
2128 { "addsubps", { XM, EXx } },
246c51aa 2129 },
050dfa73 2130
1ceb70f8 2131 /* PREFIX_0FD6 */
050dfa73 2132 {
058f233b 2133 { "(bad)", { XX } },
4e7d34a6
L		 2134 { "movq2dq",{ XM, MS } },
2135 { "movq", { EXq, XM } },
2136 { "movdq2q",{ MX, XS } },
050dfa73
MM		 2137 },
2138
1ceb70f8 2139 /* PREFIX_0FE6 */
7918206c 2140 {
058f233b 2141 { "(bad)", { XX } },
4e7d34a6
L		 2142 { "cvtdq2pd", { XM, EXq } },
2143 { "cvttpd2dq", { XM, EXx } },
2144 { "cvtpd2dq", { XM, EXx } },
7918206c 2145 },
8b38ad71 2146
1ceb70f8 2147 /* PREFIX_0FE7 */
8b38ad71 2148 {
4e7d34a6 2149 { "movntq", { EM, MX } },
058f233b 2150 { "(bad)", { XX } },
75c135a8 2151 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
058f233b 2152 { "(bad)", { XX } },
4e7d34a6
L		 2153 },
2154
1ceb70f8 2155 /* PREFIX_0FF0 */
4e7d34a6 2156 {
058f233b
L		 2157 { "(bad)", { XX } },
2158 { "(bad)", { XX } },
2159 { "(bad)", { XX } },
1ceb70f8 2160 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4e7d34a6
L		 2161 },
2162
1ceb70f8 2163 /* PREFIX_0FF7 */
4e7d34a6
L		 2164 {
2165 { "maskmovq", { MX, MS } },
058f233b 2166 { "(bad)", { XX } },
4e7d34a6 2167 { "maskmovdqu", { XM, XS } },
058f233b 2168 { "(bad)", { XX } },
8b38ad71 2169 },
42903f7f 2170
1ceb70f8 2171 /* PREFIX_0F3810 */
42903f7f
L		 2172 {
2173 { "(bad)", { XX } },
2174 { "(bad)", { XX } },
88a94849 2175 { "pblendvb", { XM, EXx, XMM0 } },
42903f7f
L		 2176 { "(bad)", { XX } },
2177 },
2178
1ceb70f8 2179 /* PREFIX_0F3814 */
42903f7f
L		 2180 {
2181 { "(bad)", { XX } },
2182 { "(bad)", { XX } },
88a94849 2183 { "blendvps", { XM, EXx, XMM0 } },
42903f7f
L		 2184 { "(bad)", { XX } },
2185 },
2186
1ceb70f8 2187 /* PREFIX_0F3815 */
42903f7f
L		 2188 {
2189 { "(bad)", { XX } },
2190 { "(bad)", { XX } },
09a2c6cf 2191 { "blendvpd", { XM, EXx, XMM0 } },
42903f7f
L		 2192 { "(bad)", { XX } },
2193 },
2194
1ceb70f8 2195 /* PREFIX_0F3817 */
42903f7f
L		 2196 {
2197 { "(bad)", { XX } },
2198 { "(bad)", { XX } },
09a2c6cf 2199 { "ptest", { XM, EXx } },
42903f7f
L		 2200 { "(bad)", { XX } },
2201 },
2202
1ceb70f8 2203 /* PREFIX_0F3820 */
42903f7f
L		 2204 {
2205 { "(bad)", { XX } },
2206 { "(bad)", { XX } },
8976381e 2207 { "pmovsxbw", { XM, EXq } },
42903f7f
L		 2208 { "(bad)", { XX } },
2209 },
2210
1ceb70f8 2211 /* PREFIX_0F3821 */
42903f7f
L		 2212 {
2213 { "(bad)", { XX } },
2214 { "(bad)", { XX } },
8976381e 2215 { "pmovsxbd", { XM, EXd } },
42903f7f
L		 2216 { "(bad)", { XX } },
2217 },
2218
1ceb70f8 2219 /* PREFIX_0F3822 */
42903f7f
L		 2220 {
2221 { "(bad)", { XX } },
2222 { "(bad)", { XX } },
8976381e 2223 { "pmovsxbq", { XM, EXw } },
42903f7f
L		 2224 { "(bad)", { XX } },
2225 },
2226
1ceb70f8 2227 /* PREFIX_0F3823 */
42903f7f
L		 2228 {
2229 { "(bad)", { XX } },
2230 { "(bad)", { XX } },
8976381e 2231 { "pmovsxwd", { XM, EXq } },
42903f7f
L		 2232 { "(bad)", { XX } },
2233 },
2234
1ceb70f8 2235 /* PREFIX_0F3824 */
42903f7f
L		 2236 {
2237 { "(bad)", { XX } },
2238 { "(bad)", { XX } },
8976381e 2239 { "pmovsxwq", { XM, EXd } },
42903f7f
L		 2240 { "(bad)", { XX } },
2241 },
2242
1ceb70f8 2243 /* PREFIX_0F3825 */
42903f7f
L		 2244 {
2245 { "(bad)", { XX } },
2246 { "(bad)", { XX } },
8976381e 2247 { "pmovsxdq", { XM, EXq } },
42903f7f
L		 2248 { "(bad)", { XX } },
2249 },
2250
1ceb70f8 2251 /* PREFIX_0F3828 */
42903f7f
L		 2252 {
2253 { "(bad)", { XX } },
2254 { "(bad)", { XX } },
09a2c6cf 2255 { "pmuldq", { XM, EXx } },
42903f7f
L		 2256 { "(bad)", { XX } },
2257 },
2258
1ceb70f8 2259 /* PREFIX_0F3829 */
42903f7f
L		 2260 {
2261 { "(bad)", { XX } },
2262 { "(bad)", { XX } },
09a2c6cf 2263 { "pcmpeqq", { XM, EXx } },
42903f7f
L		 2264 { "(bad)", { XX } },
2265 },
2266
1ceb70f8 2267 /* PREFIX_0F382A */
42903f7f
L		 2268 {
2269 { "(bad)", { XX } },
2270 { "(bad)", { XX } },
75c135a8 2271 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
42903f7f
L		 2272 { "(bad)", { XX } },
2273 },
2274
1ceb70f8 2275 /* PREFIX_0F382B */
42903f7f
L		 2276 {
2277 { "(bad)", { XX } },
2278 { "(bad)", { XX } },
09a2c6cf 2279 { "packusdw", { XM, EXx } },
42903f7f
L		 2280 { "(bad)", { XX } },
2281 },
2282
1ceb70f8 2283 /* PREFIX_0F3830 */
42903f7f
L		 2284 {
2285 { "(bad)", { XX } },
2286 { "(bad)", { XX } },
8976381e 2287 { "pmovzxbw", { XM, EXq } },
42903f7f
L		 2288 { "(bad)", { XX } },
2289 },
2290
1ceb70f8 2291 /* PREFIX_0F3831 */
42903f7f
L		 2292 {
2293 { "(bad)", { XX } },
2294 { "(bad)", { XX } },
8976381e 2295 { "pmovzxbd", { XM, EXd } },
42903f7f
L		 2296 { "(bad)", { XX } },
2297 },
2298
1ceb70f8 2299 /* PREFIX_0F3832 */
42903f7f
L		 2300 {
2301 { "(bad)", { XX } },
2302 { "(bad)", { XX } },
8976381e 2303 { "pmovzxbq", { XM, EXw } },
42903f7f
L		 2304 { "(bad)", { XX } },
2305 },
2306
1ceb70f8 2307 /* PREFIX_0F3833 */
42903f7f
L		 2308 {
2309 { "(bad)", { XX } },
2310 { "(bad)", { XX } },
8976381e 2311 { "pmovzxwd", { XM, EXq } },
42903f7f
L		 2312 { "(bad)", { XX } },
2313 },
2314
1ceb70f8 2315 /* PREFIX_0F3834 */
42903f7f
L		 2316 {
2317 { "(bad)", { XX } },
2318 { "(bad)", { XX } },
8976381e 2319 { "pmovzxwq", { XM, EXd } },
42903f7f
L		 2320 { "(bad)", { XX } },
2321 },
2322
1ceb70f8 2323 /* PREFIX_0F3835 */
42903f7f
L		 2324 {
2325 { "(bad)", { XX } },
2326 { "(bad)", { XX } },
8976381e 2327 { "pmovzxdq", { XM, EXq } },
42903f7f
L		 2328 { "(bad)", { XX } },
2329 },
2330
1ceb70f8 2331 /* PREFIX_0F3837 */
4e7d34a6
L		 2332 {
2333 { "(bad)", { XX } },
2334 { "(bad)", { XX } },
2335 { "pcmpgtq", { XM, EXx } },
2336 { "(bad)", { XX } },
2337 },
2338
1ceb70f8 2339 /* PREFIX_0F3838 */
42903f7f
L		 2340 {
2341 { "(bad)", { XX } },
2342 { "(bad)", { XX } },
09a2c6cf 2343 { "pminsb", { XM, EXx } },
42903f7f
L		 2344 { "(bad)", { XX } },
2345 },
2346
1ceb70f8 2347 /* PREFIX_0F3839 */
42903f7f
L		 2348 {
2349 { "(bad)", { XX } },
2350 { "(bad)", { XX } },
09a2c6cf 2351 { "pminsd", { XM, EXx } },
42903f7f
L		 2352 { "(bad)", { XX } },
2353 },
2354
1ceb70f8 2355 /* PREFIX_0F383A */
42903f7f
L		 2356 {
2357 { "(bad)", { XX } },
2358 { "(bad)", { XX } },
09a2c6cf 2359 { "pminuw", { XM, EXx } },
42903f7f
L		 2360 { "(bad)", { XX } },
2361 },
2362
1ceb70f8 2363 /* PREFIX_0F383B */
42903f7f
L		 2364 {
2365 { "(bad)", { XX } },
2366 { "(bad)", { XX } },
09a2c6cf 2367 { "pminud", { XM, EXx } },
42903f7f
L		 2368 { "(bad)", { XX } },
2369 },
2370
1ceb70f8 2371 /* PREFIX_0F383C */
42903f7f
L		 2372 {
2373 { "(bad)", { XX } },
2374 { "(bad)", { XX } },
09a2c6cf 2375 { "pmaxsb", { XM, EXx } },
42903f7f
L		 2376 { "(bad)", { XX } },
2377 },
2378
1ceb70f8 2379 /* PREFIX_0F383D */
42903f7f
L		 2380 {
2381 { "(bad)", { XX } },
2382 { "(bad)", { XX } },
09a2c6cf 2383 { "pmaxsd", { XM, EXx } },
42903f7f
L		 2384 { "(bad)", { XX } },
2385 },
2386
1ceb70f8 2387 /* PREFIX_0F383E */
42903f7f
L		 2388 {
2389 { "(bad)", { XX } },
2390 { "(bad)", { XX } },
09a2c6cf 2391 { "pmaxuw", { XM, EXx } },
42903f7f
L		 2392 { "(bad)", { XX } },
2393 },
2394
1ceb70f8 2395 /* PREFIX_0F383F */
42903f7f
L		 2396 {
2397 { "(bad)", { XX } },
2398 { "(bad)", { XX } },
09a2c6cf 2399 { "pmaxud", { XM, EXx } },
42903f7f
L		 2400 { "(bad)", { XX } },
2401 },
2402
1ceb70f8 2403 /* PREFIX_0F3840 */
42903f7f
L		 2404 {
2405 { "(bad)", { XX } },
2406 { "(bad)", { XX } },
09a2c6cf 2407 { "pmulld", { XM, EXx } },
42903f7f
L		 2408 { "(bad)", { XX } },
2409 },
2410
1ceb70f8 2411 /* PREFIX_0F3841 */
42903f7f
L		 2412 {
2413 { "(bad)", { XX } },
2414 { "(bad)", { XX } },
09a2c6cf 2415 { "phminposuw", { XM, EXx } },
42903f7f
L		 2416 { "(bad)", { XX } },
2417 },
2418
1ceb70f8 2419 /* PREFIX_0F38F0 */
4e7d34a6
L		 2420 {
2421 { "(bad)", { XX } },
2422 { "(bad)", { XX } },
2423 { "(bad)", { XX } },
2424 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
2425 },
2426
1ceb70f8 2427 /* PREFIX_0F38F1 */
4e7d34a6
L		 2428 {
2429 { "(bad)", { XX } },
2430 { "(bad)", { XX } },
2431 { "(bad)", { XX } },
2432 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
2433 },
2434
1ceb70f8 2435 /* PREFIX_0F3A08 */
42903f7f
L		 2436 {
2437 { "(bad)", { XX } },
2438 { "(bad)", { XX } },
09a2c6cf 2439 { "roundps", { XM, EXx, Ib } },
42903f7f
L		 2440 { "(bad)", { XX } },
2441 },
2442
1ceb70f8 2443 /* PREFIX_0F3A09 */
42903f7f
L		 2444 {
2445 { "(bad)", { XX } },
2446 { "(bad)", { XX } },
09a2c6cf 2447 { "roundpd", { XM, EXx, Ib } },
42903f7f
L		 2448 { "(bad)", { XX } },
2449 },
2450
1ceb70f8 2451 /* PREFIX_0F3A0A */
42903f7f
L		 2452 {
2453 { "(bad)", { XX } },
2454 { "(bad)", { XX } },
09335d05 2455 { "roundss", { XM, EXd, Ib } },
42903f7f
L		 2456 { "(bad)", { XX } },
2457 },
2458
1ceb70f8 2459 /* PREFIX_0F3A0B */
42903f7f
L		 2460 {
2461 { "(bad)", { XX } },
2462 { "(bad)", { XX } },
09335d05 2463 { "roundsd", { XM, EXq, Ib } },
42903f7f
L		 2464 { "(bad)", { XX } },
2465 },
2466
1ceb70f8 2467 /* PREFIX_0F3A0C */
42903f7f
L		 2468 {
2469 { "(bad)", { XX } },
2470 { "(bad)", { XX } },
09a2c6cf 2471 { "blendps", { XM, EXx, Ib } },
42903f7f
L		 2472 { "(bad)", { XX } },
2473 },
2474
1ceb70f8 2475 /* PREFIX_0F3A0D */
42903f7f
L		 2476 {
2477 { "(bad)", { XX } },
2478 { "(bad)", { XX } },
09a2c6cf 2479 { "blendpd", { XM, EXx, Ib } },
42903f7f
L		 2480 { "(bad)", { XX } },
2481 },
2482
1ceb70f8 2483 /* PREFIX_0F3A0E */
42903f7f
L		 2484 {
2485 { "(bad)", { XX } },
2486 { "(bad)", { XX } },
09a2c6cf 2487 { "pblendw", { XM, EXx, Ib } },
42903f7f
L		 2488 { "(bad)", { XX } },
2489 },
2490
1ceb70f8 2491 /* PREFIX_0F3A14 */
42903f7f
L		 2492 {
2493 { "(bad)", { XX } },
2494 { "(bad)", { XX } },
2495 { "pextrb", { Edqb, XM, Ib } },
2496 { "(bad)", { XX } },
2497 },
2498
1ceb70f8 2499 /* PREFIX_0F3A15 */
42903f7f
L		 2500 {
2501 { "(bad)", { XX } },
2502 { "(bad)", { XX } },
2503 { "pextrw", { Edqw, XM, Ib } },
2504 { "(bad)", { XX } },
2505 },
2506
1ceb70f8 2507 /* PREFIX_0F3A16 */
42903f7f
L		 2508 {
2509 { "(bad)", { XX } },
2510 { "(bad)", { XX } },
2511 { "pextrK", { Edq, XM, Ib } },
2512 { "(bad)", { XX } },
2513 },
2514
1ceb70f8 2515 /* PREFIX_0F3A17 */
42903f7f
L		 2516 {
2517 { "(bad)", { XX } },
2518 { "(bad)", { XX } },
2519 { "extractps", { Edqd, XM, Ib } },
2520 { "(bad)", { XX } },
2521 },
2522
1ceb70f8 2523 /* PREFIX_0F3A20 */
42903f7f
L		 2524 {
2525 { "(bad)", { XX } },
2526 { "(bad)", { XX } },
2527 { "pinsrb", { XM, Edqb, Ib } },
2528 { "(bad)", { XX } },
2529 },
2530
1ceb70f8 2531 /* PREFIX_0F3A21 */
42903f7f
L		 2532 {
2533 { "(bad)", { XX } },
2534 { "(bad)", { XX } },
8976381e 2535 { "insertps", { XM, EXd, Ib } },
42903f7f
L		 2536 { "(bad)", { XX } },
2537 },
2538
1ceb70f8 2539 /* PREFIX_0F3A22 */
42903f7f
L		 2540 {
2541 { "(bad)", { XX } },
2542 { "(bad)", { XX } },
2543 { "pinsrK", { XM, Edq, Ib } },
2544 { "(bad)", { XX } },
2545 },
2546
1ceb70f8 2547 /* PREFIX_0F3A40 */
42903f7f
L		 2548 {
2549 { "(bad)", { XX } },
2550 { "(bad)", { XX } },
09a2c6cf 2551 { "dpps", { XM, EXx, Ib } },
42903f7f
L		 2552 { "(bad)", { XX } },
2553 },
2554
1ceb70f8 2555 /* PREFIX_0F3A41 */
42903f7f
L		 2556 {
2557 { "(bad)", { XX } },
2558 { "(bad)", { XX } },
09a2c6cf 2559 { "dppd", { XM, EXx, Ib } },
42903f7f
L		 2560 { "(bad)", { XX } },
2561 },
2562
1ceb70f8 2563 /* PREFIX_0F3A42 */
42903f7f
L		 2564 {
2565 { "(bad)", { XX } },
2566 { "(bad)", { XX } },
09a2c6cf 2567 { "mpsadbw", { XM, EXx, Ib } },
42903f7f
L		 2568 { "(bad)", { XX } },
2569 },
381d071f 2570
1ceb70f8 2571 /* PREFIX_0F3A60 */
381d071f
L		 2572 {
2573 { "(bad)", { XX } },
2574 { "(bad)", { XX } },
4e7d34a6 2575 { "pcmpestrm", { XM, EXx, Ib } },
381d071f
L		 2576 { "(bad)", { XX } },
2577 },
2578
1ceb70f8 2579 /* PREFIX_0F3A61 */
381d071f
L		 2580 {
2581 { "(bad)", { XX } },
2582 { "(bad)", { XX } },
4e7d34a6 2583 { "pcmpestri", { XM, EXx, Ib } },
381d071f 2584 { "(bad)", { XX } },
381d071f
L		 2585 },
2586
1ceb70f8 2587 /* PREFIX_0F3A62 */
381d071f
L		 2588 {
2589 { "(bad)", { XX } },
2590 { "(bad)", { XX } },
4e7d34a6 2591 { "pcmpistrm", { XM, EXx, Ib } },
381d071f 2592 { "(bad)", { XX } },
381d071f
L		 2593 },
2594
1ceb70f8 2595 /* PREFIX_0F3A63 */
381d071f
L		 2596 {
2597 { "(bad)", { XX } },
2598 { "(bad)", { XX } },
4e7d34a6 2599 { "pcmpistri", { XM, EXx, Ib } },
381d071f
L		 2600 { "(bad)", { XX } },
2601 },
4e7d34a6 2602};
09a2c6cf 2603
4e7d34a6
L		 2604static const struct dis386 x86_64_table[][2] = {
2605 /* X86_64_06 */
09a2c6cf 2606 {
4e7d34a6
L		 2607 { "push{T|}", { es } },
2608 { "(bad)", { XX } },
09a2c6cf
L		 2609 },
2610
4e7d34a6 2611 /* X86_64_07 */
09a2c6cf 2612 {
4e7d34a6
L		 2613 { "pop{T|}", { es } },
2614 { "(bad)", { XX } },
09a2c6cf
L		 2615 },
2616
4e7d34a6 2617 /* X86_64_0D */
09a2c6cf 2618 {
4e7d34a6
L		 2619 { "push{T|}", { cs } },
2620 { "(bad)", { XX } },
09a2c6cf
L		 2621 },
2622
4e7d34a6 2623 /* X86_64_16 */
09a2c6cf 2624 {
4e7d34a6
L		 2625 { "push{T|}", { ss } },
2626 { "(bad)", { XX } },
09a2c6cf
L		 2627 },
2628
4e7d34a6 2629 /* X86_64_17 */
09a2c6cf 2630 {
4e7d34a6 2631 { "pop{T|}", { ss } },
ce518a5f 2632 { "(bad)", { XX } },
5f754f58 2633 },
7c52e0e8 2634
4e7d34a6 2635 /* X86_64_1E */
5f754f58 2636 {
4e7d34a6 2637 { "push{T|}", { ds } },
ce518a5f 2638 { "(bad)", { XX } },
5f754f58 2639 },
7c52e0e8 2640
4e7d34a6 2641 /* X86_64_1F */
5f754f58 2642 {
4e7d34a6 2643 { "pop{T|}", { ds } },
ce518a5f 2644 { "(bad)", { XX } },
5f754f58 2645 },
7c52e0e8 2646
4e7d34a6 2647 /* X86_64_27 */
7c52e0e8 2648 {
4e7d34a6 2649 { "daa", { XX } },
7c52e0e8
L		 2650 { "(bad)", { XX } },
2651 },
2652
4e7d34a6 2653 /* X86_64_2F */
7c52e0e8 2654 {
4e7d34a6 2655 { "das", { XX } },
7c52e0e8
L		 2656 { "(bad)", { XX } },
2657 },
2658
4e7d34a6 2659 /* X86_64_37 */
7c52e0e8 2660 {
4e7d34a6 2661 { "aaa", { XX } },
7c52e0e8
L		 2662 { "(bad)", { XX } },
2663 },
2664
4e7d34a6 2665 /* X86_64_3F */
7c52e0e8 2666 {
4e7d34a6 2667 { "aas", { XX } },
7c52e0e8
L		 2668 { "(bad)", { XX } },
2669 },
2670
4e7d34a6 2671 /* X86_64_60 */
7c52e0e8 2672 {
4e7d34a6 2673 { "pusha{P|}", { XX } },
7c52e0e8
L		 2674 { "(bad)", { XX } },
2675 },
2676
4e7d34a6 2677 /* X86_64_61 */
7c52e0e8 2678 {
4e7d34a6 2679 { "popa{P|}", { XX } },
7c52e0e8
L		 2680 { "(bad)", { XX } },
2681 },
2682
4e7d34a6 2683 /* X86_64_62 */
7c52e0e8 2684 {
1ceb70f8 2685 { MOD_TABLE (MOD_62_32BIT) },
7c52e0e8
L		 2686 { "(bad)", { XX } },
2687 },
2688
4e7d34a6 2689 /* X86_64_63 */
7c52e0e8 2690 {
4e7d34a6
L		 2691 { "arpl", { Ew, Gw } },
2692 { "movs{lq|xd}", { Gv, Ed } },
7c52e0e8
L		 2693 },
2694
4e7d34a6 2695 /* X86_64_6D */
7c52e0e8 2696 {
4e7d34a6
L		 2697 { "ins{R|}", { Yzr, indirDX } },
2698 { "ins{G|}", { Yzr, indirDX } },
7c52e0e8
L		 2699 },
2700
4e7d34a6 2701 /* X86_64_6F */
7c52e0e8 2702 {
4e7d34a6
L		 2703 { "outs{R|}", { indirDXr, Xz } },
2704 { "outs{G|}", { indirDXr, Xz } },
7c52e0e8
L		 2705 },
2706
4e7d34a6 2707 /* X86_64_9A */
7c52e0e8 2708 {
4e7d34a6 2709 { "Jcall{T|}", { Ap } },
7c52e0e8
L		 2710 { "(bad)", { XX } },
2711 },
2712
4e7d34a6 2713 /* X86_64_C4 */
7c52e0e8 2714 {
1ceb70f8 2715 { MOD_TABLE (MOD_C4_32BIT) },
4e7d34a6 2716 { "(bad)", { XX } },
7c52e0e8
L		 2717 },
2718
4e7d34a6 2719 /* X86_64_C5 */
7c52e0e8 2720 {
1ceb70f8 2721 { MOD_TABLE (MOD_C5_32BIT) },
7c52e0e8
L		 2722 { "(bad)", { XX } },
2723 },
2724
4e7d34a6 2725 /* X86_64_CE */
7c52e0e8
L		 2726 {
2727 { "into", { XX } },
2728 { "(bad)", { XX } },
2729 },
2730
4e7d34a6 2731 /* X86_64_D4 */
7c52e0e8
L		 2732 {
2733 { "aam", { sIb } },
2734 { "(bad)", { XX } },
2735 },
2736
4e7d34a6 2737 /* X86_64_D5 */
7c52e0e8
L		 2738 {
2739 { "aad", { sIb } },
2740 { "(bad)", { XX } },
2741 },
2742
4e7d34a6 2743 /* X86_64_EA */
7c52e0e8
L		 2744 {
2745 { "Jjmp{T|}", { Ap } },
2746 { "(bad)", { XX } },
2747 },
2748
4e7d34a6 2749 /* X86_64_0F01_REG_0 */
7c52e0e8
L		 2750 {
2751 { "sgdt{Q|IQ}", { M } },
2752 { "sgdt", { M } },
2753 },
2754
4e7d34a6 2755 /* X86_64_0F01_REG_1 */
7c52e0e8
L		 2756 {
2757 { "sidt{Q|IQ}", { M } },
2758 { "sidt", { M } },
2759 },
2760
4e7d34a6 2761 /* X86_64_0F01_REG_2 */
7c52e0e8
L		 2762 {
2763 { "lgdt{Q|Q}", { M } },
2764 { "lgdt", { M } },
2765 },
2766
4e7d34a6 2767 /* X86_64_0F01_REG_3 */
7c52e0e8
L		 2768 {
2769 { "lidt{Q|Q}", { M } },
2770 { "lidt", { M } },
2771 },
6439fc28
AM		 2772};
2773
96fbad73 2774static const struct dis386 three_byte_table[][256] = {
4e7d34a6 2775 /* THREE_BYTE_0F24 */
331d2d0d 2776 {
96fbad73 2777 /* 00 */
4e7d34a6
L		 2778 { "fmaddps", { { OP_DREX4, q_mode } } },
2779 { "fmaddpd", { { OP_DREX4, q_mode } } },
2780 { "fmaddss", { { OP_DREX4, w_mode } } },
2781 { "fmaddsd", { { OP_DREX4, d_mode } } },
2782 { "fmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2783 { "fmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2784 { "fmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2785 { "fmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
96fbad73 2786 /* 08 */
4e7d34a6
L		 2787 { "fmsubps", { { OP_DREX4, q_mode } } },
2788 { "fmsubpd", { { OP_DREX4, q_mode } } },
2789 { "fmsubss", { { OP_DREX4, w_mode } } },
2790 { "fmsubsd", { { OP_DREX4, d_mode } } },
2791 { "fmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2792 { "fmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2793 { "fmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2794 { "fmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
85f10a01 2795 /* 10 */
4e7d34a6
L		 2796 { "fnmaddps", { { OP_DREX4, q_mode } } },
2797 { "fnmaddpd", { { OP_DREX4, q_mode } } },
2798 { "fnmaddss", { { OP_DREX4, w_mode } } },
2799 { "fnmaddsd", { { OP_DREX4, d_mode } } },
2800 { "fnmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2801 { "fnmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2802 { "fnmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2803 { "fnmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
85f10a01 2804 /* 18 */
4e7d34a6
L		 2805 { "fnmsubps", { { OP_DREX4, q_mode } } },
2806 { "fnmsubpd", { { OP_DREX4, q_mode } } },
2807 { "fnmsubss", { { OP_DREX4, w_mode } } },
2808 { "fnmsubsd", { { OP_DREX4, d_mode } } },
2809 { "fnmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2810 { "fnmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2811 { "fnmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2812 { "fnmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
85f10a01 2813 /* 20 */
4e7d34a6
L		 2814 { "permps", { { OP_DREX4, q_mode } } },
2815 { "permpd", { { OP_DREX4, q_mode } } },
2816 { "pcmov", { { OP_DREX4, q_mode } } },
2817 { "pperm", { { OP_DREX4, q_mode } } },
2818 { "permps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2819 { "permpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2820 { "pcmov", { { OP_DREX4, DREX_OC1 + w_mode } } },
2821 { "pperm", { { OP_DREX4, DREX_OC1 + d_mode } } },
85f10a01 2822 /* 28 */
4e7d34a6
L		 2823 { "(bad)", { XX } },
2824 { "(bad)", { XX } },
2825 { "(bad)", { XX } },
2826 { "(bad)", { XX } },
2827 { "(bad)", { XX } },
2828 { "(bad)", { XX } },
2829 { "(bad)", { XX } },
2830 { "(bad)", { XX } },
85f10a01 2831 /* 30 */
4e7d34a6
L		 2832 { "(bad)", { XX } },
2833 { "(bad)", { XX } },
2834 { "(bad)", { XX } },
2835 { "(bad)", { XX } },
2836 { "(bad)", { XX } },
2837 { "(bad)", { XX } },
2838 { "(bad)", { XX } },
2839 { "(bad)", { XX } },
85f10a01 2840 /* 38 */
4e7d34a6
L		 2841 { "(bad)", { XX } },
2842 { "(bad)", { XX } },
2843 { "(bad)", { XX } },
2844 { "(bad)", { XX } },
2845 { "(bad)", { XX } },
2846 { "(bad)", { XX } },
2847 { "(bad)", { XX } },
2848 { "(bad)", { XX } },
85f10a01 2849 /* 40 */
4e7d34a6
L		 2850 { "protb", { { OP_DREX3, q_mode } } },
2851 { "protw", { { OP_DREX3, q_mode } } },
2852 { "protd", { { OP_DREX3, q_mode } } },
2853 { "protq", { { OP_DREX3, q_mode } } },
2854 { "pshlb", { { OP_DREX3, q_mode } } },
2855 { "pshlw", { { OP_DREX3, q_mode } } },
2856 { "pshld", { { OP_DREX3, q_mode } } },
2857 { "pshlq", { { OP_DREX3, q_mode } } },
85f10a01 2858 /* 48 */
4e7d34a6
L		 2859 { "pshab", { { OP_DREX3, q_mode } } },
2860 { "pshaw", { { OP_DREX3, q_mode } } },
2861 { "pshad", { { OP_DREX3, q_mode } } },
2862 { "pshaq", { { OP_DREX3, q_mode } } },
2863 { "(bad)", { XX } },
2864 { "(bad)", { XX } },
2865 { "(bad)", { XX } },
2866 { "(bad)", { XX } },
85f10a01 2867 /* 50 */
4e7d34a6
L		 2868 { "(bad)", { XX } },
2869 { "(bad)", { XX } },
2870 { "(bad)", { XX } },
2871 { "(bad)", { XX } },
2872 { "(bad)", { XX } },
2873 { "(bad)", { XX } },
2874 { "(bad)", { XX } },
2875 { "(bad)", { XX } },
85f10a01 2876 /* 58 */
4e7d34a6
L		 2877 { "(bad)", { XX } },
2878 { "(bad)", { XX } },
2879 { "(bad)", { XX } },
2880 { "(bad)", { XX } },
2881 { "(bad)", { XX } },
2882 { "(bad)", { XX } },
2883 { "(bad)", { XX } },
2884 { "(bad)", { XX } },
85f10a01 2885 /* 60 */
4e7d34a6
L		 2886 { "(bad)", { XX } },
2887 { "(bad)", { XX } },
2888 { "(bad)", { XX } },
2889 { "(bad)", { XX } },
2890 { "(bad)", { XX } },
2891 { "(bad)", { XX } },
2892 { "(bad)", { XX } },
2893 { "(bad)", { XX } },
2894 /* 68 */
2895 { "(bad)", { XX } },
2896 { "(bad)", { XX } },
2897 { "(bad)", { XX } },
2898 { "(bad)", { XX } },
2899 { "(bad)", { XX } },
2900 { "(bad)", { XX } },
2901 { "(bad)", { XX } },
2902 { "(bad)", { XX } },
85f10a01 2903 /* 70 */
4e7d34a6
L		 2904 { "(bad)", { XX } },
2905 { "(bad)", { XX } },
2906 { "(bad)", { XX } },
2907 { "(bad)", { XX } },
2908 { "(bad)", { XX } },
2909 { "(bad)", { XX } },
2910 { "(bad)", { XX } },
2911 { "(bad)", { XX } },
85f10a01 2912 /* 78 */
4e7d34a6
L		 2913 { "(bad)", { XX } },
2914 { "(bad)", { XX } },
2915 { "(bad)", { XX } },
2916 { "(bad)", { XX } },
2917 { "(bad)", { XX } },
2918 { "(bad)", { XX } },
2919 { "(bad)", { XX } },
2920 { "(bad)", { XX } },
85f10a01 2921 /* 80 */
4e7d34a6
L		 2922 { "(bad)", { XX } },
2923 { "(bad)", { XX } },
2924 { "(bad)", { XX } },
2925 { "(bad)", { XX } },
2926 { "(bad)", { XX } },
2927 { "pmacssww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2928 { "pmacsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2929 { "pmacssdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
85f10a01 2930 /* 88 */
4e7d34a6
L		 2931 { "(bad)", { XX } },
2932 { "(bad)", { XX } },
2933 { "(bad)", { XX } },
2934 { "(bad)", { XX } },
2935 { "(bad)", { XX } },
2936 { "(bad)", { XX } },
2937 { "pmacssdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2938 { "pmacssdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
85f10a01 2939 /* 90 */
4e7d34a6
L		 2940 { "(bad)", { XX } },
2941 { "(bad)", { XX } },
2942 { "(bad)", { XX } },
2943 { "(bad)", { XX } },
2944 { "(bad)", { XX } },
2945 { "pmacsww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2946 { "pmacswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2947 { "pmacsdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
85f10a01 2948 /* 98 */
4e7d34a6
L		 2949 { "(bad)", { XX } },
2950 { "(bad)", { XX } },
2951 { "(bad)", { XX } },
2952 { "(bad)", { XX } },
2953 { "(bad)", { XX } },
2954 { "(bad)", { XX } },
2955 { "pmacsdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2956 { "pmacsdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
85f10a01 2957 /* a0 */
4e7d34a6
L		 2958 { "(bad)", { XX } },
2959 { "(bad)", { XX } },
2960 { "(bad)", { XX } },
2961 { "(bad)", { XX } },
2962 { "(bad)", { XX } },
2963 { "(bad)", { XX } },
2964 { "pmadcsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2965 { "(bad)", { XX } },
85f10a01 2966 /* a8 */
4e7d34a6
L		 2967 { "(bad)", { XX } },
2968 { "(bad)", { XX } },
2969 { "(bad)", { XX } },
2970 { "(bad)", { XX } },
2971 { "(bad)", { XX } },
2972 { "(bad)", { XX } },
2973 { "(bad)", { XX } },
2974 { "(bad)", { XX } },
85f10a01 2975 /* b0 */
4e7d34a6
L		 2976 { "(bad)", { XX } },
2977 { "(bad)", { XX } },
2978 { "(bad)", { XX } },
2979 { "(bad)", { XX } },
2980 { "(bad)", { XX } },
2981 { "(bad)", { XX } },
2982 { "pmadcswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2983 { "(bad)", { XX } },
85f10a01 2984 /* b8 */
4e7d34a6
L		 2985 { "(bad)", { XX } },
2986 { "(bad)", { XX } },
2987 { "(bad)", { XX } },
2988 { "(bad)", { XX } },
2989 { "(bad)", { XX } },
2990 { "(bad)", { XX } },
2991 { "(bad)", { XX } },
2992 { "(bad)", { XX } },
85f10a01 2993 /* c0 */
4e7d34a6
L		 2994 { "(bad)", { XX } },
2995 { "(bad)", { XX } },
2996 { "(bad)", { XX } },
2997 { "(bad)", { XX } },
2998 { "(bad)", { XX } },
2999 { "(bad)", { XX } },
3000 { "(bad)", { XX } },
3001 { "(bad)", { XX } },
85f10a01 3002 /* c8 */
4e7d34a6
L		 3003 { "(bad)", { XX } },
3004 { "(bad)", { XX } },
3005 { "(bad)", { XX } },
3006 { "(bad)", { XX } },
3007 { "(bad)", { XX } },
3008 { "(bad)", { XX } },
3009 { "(bad)", { XX } },
3010 { "(bad)", { XX } },
85f10a01 3011 /* d0 */
4e7d34a6
L		 3012 { "(bad)", { XX } },
3013 { "(bad)", { XX } },
3014 { "(bad)", { XX } },
3015 { "(bad)", { XX } },
3016 { "(bad)", { XX } },
3017 { "(bad)", { XX } },
3018 { "(bad)", { XX } },
3019 { "(bad)", { XX } },
85f10a01 3020 /* d8 */
4e7d34a6
L		 3021 { "(bad)", { XX } },
3022 { "(bad)", { XX } },
3023 { "(bad)", { XX } },
3024 { "(bad)", { XX } },
3025 { "(bad)", { XX } },
3026 { "(bad)", { XX } },
3027 { "(bad)", { XX } },
3028 { "(bad)", { XX } },
85f10a01 3029 /* e0 */
4e7d34a6
L		 3030 { "(bad)", { XX } },
3031 { "(bad)", { XX } },
3032 { "(bad)", { XX } },
3033 { "(bad)", { XX } },
3034 { "(bad)", { XX } },
3035 { "(bad)", { XX } },
3036 { "(bad)", { XX } },
3037 { "(bad)", { XX } },
85f10a01 3038 /* e8 */
4e7d34a6
L		 3039 { "(bad)", { XX } },
3040 { "(bad)", { XX } },
3041 { "(bad)", { XX } },
3042 { "(bad)", { XX } },
3043 { "(bad)", { XX } },
3044 { "(bad)", { XX } },
3045 { "(bad)", { XX } },
3046 { "(bad)", { XX } },
85f10a01 3047 /* f0 */
4e7d34a6
L		 3048 { "(bad)", { XX } },
3049 { "(bad)", { XX } },
3050 { "(bad)", { XX } },
3051 { "(bad)", { XX } },
3052 { "(bad)", { XX } },
3053 { "(bad)", { XX } },
3054 { "(bad)", { XX } },
3055 { "(bad)", { XX } },
85f10a01 3056 /* f8 */
4e7d34a6
L		 3057 { "(bad)", { XX } },
3058 { "(bad)", { XX } },
3059 { "(bad)", { XX } },
3060 { "(bad)", { XX } },
3061 { "(bad)", { XX } },
3062 { "(bad)", { XX } },
3063 { "(bad)", { XX } },
3064 { "(bad)", { XX } },
85f10a01 3065 },
4e7d34a6 3066 /* THREE_BYTE_0F25 */
85f10a01
MM		 3067 {
3068 /* 00 */
4e7d34a6
L		 3069 { "(bad)", { XX } },
3070 { "(bad)", { XX } },
3071 { "(bad)", { XX } },
3072 { "(bad)", { XX } },
3073 { "(bad)", { XX } },
3074 { "(bad)", { XX } },
3075 { "(bad)", { XX } },
3076 { "(bad)", { XX } },
85f10a01 3077 /* 08 */
4e7d34a6
L		 3078 { "(bad)", { XX } },
3079 { "(bad)", { XX } },
3080 { "(bad)", { XX } },
3081 { "(bad)", { XX } },
3082 { "(bad)", { XX } },
3083 { "(bad)", { XX } },
3084 { "(bad)", { XX } },
3085 { "(bad)", { XX } },
85f10a01 3086 /* 10 */
4e7d34a6
L		 3087 { "(bad)", { XX } },
3088 { "(bad)", { XX } },
3089 { "(bad)", { XX } },
3090 { "(bad)", { XX } },
3091 { "(bad)", { XX } },
3092 { "(bad)", { XX } },
3093 { "(bad)", { XX } },
3094 { "(bad)", { XX } },
85f10a01 3095 /* 18 */
4e7d34a6
L		 3096 { "(bad)", { XX } },
3097 { "(bad)", { XX } },
3098 { "(bad)", { XX } },
3099 { "(bad)", { XX } },
3100 { "(bad)", { XX } },
3101 { "(bad)", { XX } },
3102 { "(bad)", { XX } },
3103 { "(bad)", { XX } },
85f10a01 3104 /* 20 */
4e7d34a6
L		 3105 { "(bad)", { XX } },
3106 { "(bad)", { XX } },
3107 { "(bad)", { XX } },
3108 { "(bad)", { XX } },
3109 { "(bad)", { XX } },
3110 { "(bad)", { XX } },
3111 { "(bad)", { XX } },
3112 { "(bad)", { XX } },
85f10a01 3113 /* 28 */
4e7d34a6
L		 3114 { "(bad)", { XX } },
3115 { "(bad)", { XX } },
3116 { "(bad)", { XX } },
3117 { "(bad)", { XX } },
3118 { "comps", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
3119 { "compd", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
3120 { "comss", { { OP_DREX3, w_mode }, { OP_DREX_FCMP, b_mode } } },
3121 { "comsd", { { OP_DREX3, d_mode }, { OP_DREX_FCMP, b_mode } } },
85f10a01 3122 /* 30 */
4e7d34a6
L		 3123 { "(bad)", { XX } },
3124 { "(bad)", { XX } },
3125 { "(bad)", { XX } },
3126 { "(bad)", { XX } },
3127 { "(bad)", { XX } },
3128 { "(bad)", { XX } },
3129 { "(bad)", { XX } },
3130 { "(bad)", { XX } },
85f10a01 3131 /* 38 */
4e7d34a6
L		 3132 { "(bad)", { XX } },
3133 { "(bad)", { XX } },
3134 { "(bad)", { XX } },
3135 { "(bad)", { XX } },
3136 { "(bad)", { XX } },
3137 { "(bad)", { XX } },
3138 { "(bad)", { XX } },
3139 { "(bad)", { XX } },
85f10a01 3140 /* 40 */
4e7d34a6
L		 3141 { "(bad)", { XX } },
3142 { "(bad)", { XX } },
3143 { "(bad)", { XX } },
3144 { "(bad)", { XX } },
3145 { "(bad)", { XX } },
3146 { "(bad)", { XX } },
3147 { "(bad)", { XX } },
3148 { "(bad)", { XX } },
85f10a01 3149 /* 48 */
4e7d34a6
L		 3150 { "(bad)", { XX } },
3151 { "(bad)", { XX } },
3152 { "(bad)", { XX } },
3153 { "(bad)", { XX } },
3154 { "pcomb", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3155 { "pcomw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3156 { "pcomd", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3157 { "pcomq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
85f10a01 3158 /* 50 */
4e7d34a6
L		 3159 { "(bad)", { XX } },
3160 { "(bad)", { XX } },
3161 { "(bad)", { XX } },
3162 { "(bad)", { XX } },
3163 { "(bad)", { XX } },
3164 { "(bad)", { XX } },
3165 { "(bad)", { XX } },
3166 { "(bad)", { XX } },
85f10a01 3167 /* 58 */
4e7d34a6
L		 3168 { "(bad)", { XX } },
3169 { "(bad)", { XX } },
3170 { "(bad)", { XX } },
3171 { "(bad)", { XX } },
3172 { "(bad)", { XX } },
3173 { "(bad)", { XX } },
3174 { "(bad)", { XX } },
3175 { "(bad)", { XX } },
85f10a01 3176 /* 60 */
4e7d34a6
L		 3177 { "(bad)", { XX } },
3178 { "(bad)", { XX } },
3179 { "(bad)", { XX } },
3180 { "(bad)", { XX } },
3181 { "(bad)", { XX } },
3182 { "(bad)", { XX } },
3183 { "(bad)", { XX } },
3184 { "(bad)", { XX } },
85f10a01 3185 /* 68 */
4e7d34a6
L		 3186 { "(bad)", { XX } },
3187 { "(bad)", { XX } },
3188 { "(bad)", { XX } },
3189 { "(bad)", { XX } },
3190 { "pcomub", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3191 { "pcomuw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3192 { "pcomud", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3193 { "pcomuq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
85f10a01 3194 /* 70 */
4e7d34a6
L		 3195 { "(bad)", { XX } },
3196 { "(bad)", { XX } },
3197 { "(bad)", { XX } },
3198 { "(bad)", { XX } },
3199 { "(bad)", { XX } },
3200 { "(bad)", { XX } },
3201 { "(bad)", { XX } },
3202 { "(bad)", { XX } },
85f10a01 3203 /* 78 */
4e7d34a6
L		 3204 { "(bad)", { XX } },
3205 { "(bad)", { XX } },
3206 { "(bad)", { XX } },
3207 { "(bad)", { XX } },
3208 { "(bad)", { XX } },
3209 { "(bad)", { XX } },
3210 { "(bad)", { XX } },
3211 { "(bad)", { XX } },
85f10a01 3212 /* 80 */
4e7d34a6
L		 3213 { "(bad)", { XX } },
3214 { "(bad)", { XX } },
3215 { "(bad)", { XX } },
3216 { "(bad)", { XX } },
3217 { "(bad)", { XX } },
3218 { "(bad)", { XX } },
3219 { "(bad)", { XX } },
3220 { "(bad)", { XX } },
3221 /* 88 */
3222 { "(bad)", { XX } },
3223 { "(bad)", { XX } },
3224 { "(bad)", { XX } },
3225 { "(bad)", { XX } },
3226 { "(bad)", { XX } },
3227 { "(bad)", { XX } },
3228 { "(bad)", { XX } },
3229 { "(bad)", { XX } },
3230 /* 90 */
3231 { "(bad)", { XX } },
3232 { "(bad)", { XX } },
3233 { "(bad)", { XX } },
3234 { "(bad)", { XX } },
3235 { "(bad)", { XX } },
3236 { "(bad)", { XX } },
3237 { "(bad)", { XX } },
3238 { "(bad)", { XX } },
3239 /* 98 */
3240 { "(bad)", { XX } },
3241 { "(bad)", { XX } },
3242 { "(bad)", { XX } },
3243 { "(bad)", { XX } },
3244 { "(bad)", { XX } },
3245 { "(bad)", { XX } },
3246 { "(bad)", { XX } },
3247 { "(bad)", { XX } },
3248 /* a0 */
3249 { "(bad)", { XX } },
3250 { "(bad)", { XX } },
3251 { "(bad)", { XX } },
3252 { "(bad)", { XX } },
3253 { "(bad)", { XX } },
3254 { "(bad)", { XX } },
3255 { "(bad)", { XX } },
3256 { "(bad)", { XX } },
3257 /* a8 */
3258 { "(bad)", { XX } },
3259 { "(bad)", { XX } },
3260 { "(bad)", { XX } },
3261 { "(bad)", { XX } },
3262 { "(bad)", { XX } },
3263 { "(bad)", { XX } },
3264 { "(bad)", { XX } },
3265 { "(bad)", { XX } },
3266 /* b0 */
3267 { "(bad)", { XX } },
3268 { "(bad)", { XX } },
3269 { "(bad)", { XX } },
3270 { "(bad)", { XX } },
3271 { "(bad)", { XX } },
3272 { "(bad)", { XX } },
3273 { "(bad)", { XX } },
3274 { "(bad)", { XX } },
3275 /* b8 */
3276 { "(bad)", { XX } },
3277 { "(bad)", { XX } },
3278 { "(bad)", { XX } },
3279 { "(bad)", { XX } },
3280 { "(bad)", { XX } },
3281 { "(bad)", { XX } },
3282 { "(bad)", { XX } },
3283 { "(bad)", { XX } },
3284 /* c0 */
3285 { "(bad)", { XX } },
3286 { "(bad)", { XX } },
3287 { "(bad)", { XX } },
3288 { "(bad)", { XX } },
3289 { "(bad)", { XX } },
3290 { "(bad)", { XX } },
3291 { "(bad)", { XX } },
3292 { "(bad)", { XX } },
3293 /* c8 */
3294 { "(bad)", { XX } },
3295 { "(bad)", { XX } },
3296 { "(bad)", { XX } },
3297 { "(bad)", { XX } },
3298 { "(bad)", { XX } },
3299 { "(bad)", { XX } },
3300 { "(bad)", { XX } },
3301 { "(bad)", { XX } },
3302 /* d0 */
3303 { "(bad)", { XX } },
3304 { "(bad)", { XX } },
3305 { "(bad)", { XX } },
3306 { "(bad)", { XX } },
3307 { "(bad)", { XX } },
3308 { "(bad)", { XX } },
3309 { "(bad)", { XX } },
3310 { "(bad)", { XX } },
3311 /* d8 */
3312 { "(bad)", { XX } },
3313 { "(bad)", { XX } },
3314 { "(bad)", { XX } },
3315 { "(bad)", { XX } },
3316 { "(bad)", { XX } },
3317 { "(bad)", { XX } },
3318 { "(bad)", { XX } },
3319 { "(bad)", { XX } },
3320 /* e0 */
3321 { "(bad)", { XX } },
3322 { "(bad)", { XX } },
3323 { "(bad)", { XX } },
3324 { "(bad)", { XX } },
3325 { "(bad)", { XX } },
3326 { "(bad)", { XX } },
3327 { "(bad)", { XX } },
3328 { "(bad)", { XX } },
3329 /* e8 */
3330 { "(bad)", { XX } },
3331 { "(bad)", { XX } },
3332 { "(bad)", { XX } },
3333 { "(bad)", { XX } },
3334 { "(bad)", { XX } },
3335 { "(bad)", { XX } },
3336 { "(bad)", { XX } },
3337 { "(bad)", { XX } },
3338 /* f0 */
3339 { "(bad)", { XX } },
3340 { "(bad)", { XX } },
3341 { "(bad)", { XX } },
3342 { "(bad)", { XX } },
3343 { "(bad)", { XX } },
3344 { "(bad)", { XX } },
3345 { "(bad)", { XX } },
3346 { "(bad)", { XX } },
3347 /* f8 */
3348 { "(bad)", { XX } },
3349 { "(bad)", { XX } },
3350 { "(bad)", { XX } },
3351 { "(bad)", { XX } },
3352 { "(bad)", { XX } },
3353 { "(bad)", { XX } },
3354 { "(bad)", { XX } },
3355 { "(bad)", { XX } },
3356 },
3357 /* THREE_BYTE_0F38 */
3358 {
3359 /* 00 */
d5d7db8e
L		 3360 { "pshufb", { MX, EM } },
3361 { "phaddw", { MX, EM } },
3362 { "phaddd", { MX, EM } },
3363 { "phaddsw", { MX, EM } },
3364 { "pmaddubsw", { MX, EM } },
3365 { "phsubw", { MX, EM } },
3366 { "phsubd", { MX, EM } },
3367 { "phsubsw", { MX, EM } },
4e7d34a6 3368 /* 08 */
d5d7db8e
L		 3369 { "psignb", { MX, EM } },
3370 { "psignw", { MX, EM } },
3371 { "psignd", { MX, EM } },
3372 { "pmulhrsw", { MX, EM } },
3373 { "(bad)", { XX } },
3374 { "(bad)", { XX } },
3375 { "(bad)", { XX } },
3376 { "(bad)", { XX } },
4e7d34a6 3377 /* 10 */
1ceb70f8 3378 { PREFIX_TABLE (PREFIX_0F3810) },
d5d7db8e
L		 3379 { "(bad)", { XX } },
3380 { "(bad)", { XX } },
3381 { "(bad)", { XX } },
1ceb70f8
L		 3382 { PREFIX_TABLE (PREFIX_0F3814) },
3383 { PREFIX_TABLE (PREFIX_0F3815) },
d5d7db8e 3384 { "(bad)", { XX } },
1ceb70f8 3385 { PREFIX_TABLE (PREFIX_0F3817) },
4e7d34a6 3386 /* 18 */
d5d7db8e
L		 3387 { "(bad)", { XX } },
3388 { "(bad)", { XX } },
3389 { "(bad)", { XX } },
3390 { "(bad)", { XX } },
3391 { "pabsb", { MX, EM } },
3392 { "pabsw", { MX, EM } },
3393 { "pabsd", { MX, EM } },
3394 { "(bad)", { XX } },
4e7d34a6 3395 /* 20 */
1ceb70f8
L		 3396 { PREFIX_TABLE (PREFIX_0F3820) },
3397 { PREFIX_TABLE (PREFIX_0F3821) },
3398 { PREFIX_TABLE (PREFIX_0F3822) },
3399 { PREFIX_TABLE (PREFIX_0F3823) },
3400 { PREFIX_TABLE (PREFIX_0F3824) },
3401 { PREFIX_TABLE (PREFIX_0F3825) },
d5d7db8e
L		 3402 { "(bad)", { XX } },
3403 { "(bad)", { XX } },
4e7d34a6 3404 /* 28 */
1ceb70f8
L		 3405 { PREFIX_TABLE (PREFIX_0F3828) },
3406 { PREFIX_TABLE (PREFIX_0F3829) },
3407 { PREFIX_TABLE (PREFIX_0F382A) },
3408 { PREFIX_TABLE (PREFIX_0F382B) },
d5d7db8e
L		 3409 { "(bad)", { XX } },
3410 { "(bad)", { XX } },
3411 { "(bad)", { XX } },
3412 { "(bad)", { XX } },
4e7d34a6 3413 /* 30 */
1ceb70f8
L		 3414 { PREFIX_TABLE (PREFIX_0F3830) },
3415 { PREFIX_TABLE (PREFIX_0F3831) },
3416 { PREFIX_TABLE (PREFIX_0F3832) },
3417 { PREFIX_TABLE (PREFIX_0F3833) },
3418 { PREFIX_TABLE (PREFIX_0F3834) },
3419 { PREFIX_TABLE (PREFIX_0F3835) },
d5d7db8e 3420 { "(bad)", { XX } },
1ceb70f8 3421 { PREFIX_TABLE (PREFIX_0F3837) },
4e7d34a6 3422 /* 38 */
1ceb70f8
L		 3423 { PREFIX_TABLE (PREFIX_0F3838) },
3424 { PREFIX_TABLE (PREFIX_0F3839) },
3425 { PREFIX_TABLE (PREFIX_0F383A) },
3426 { PREFIX_TABLE (PREFIX_0F383B) },
3427 { PREFIX_TABLE (PREFIX_0F383C) },
3428 { PREFIX_TABLE (PREFIX_0F383D) },
3429 { PREFIX_TABLE (PREFIX_0F383E) },
3430 { PREFIX_TABLE (PREFIX_0F383F) },
4e7d34a6 3431 /* 40 */
1ceb70f8
L		 3432 { PREFIX_TABLE (PREFIX_0F3840) },
3433 { PREFIX_TABLE (PREFIX_0F3841) },
d5d7db8e
L		 3434 { "(bad)", { XX } },
3435 { "(bad)", { XX } },
3436 { "(bad)", { XX } },
3437 { "(bad)", { XX } },
3438 { "(bad)", { XX } },
3439 { "(bad)", { XX } },
4e7d34a6 3440 /* 48 */
d5d7db8e
L		 3441 { "(bad)", { XX } },
3442 { "(bad)", { XX } },
3443 { "(bad)", { XX } },
3444 { "(bad)", { XX } },
3445 { "(bad)", { XX } },
3446 { "(bad)", { XX } },
3447 { "(bad)", { XX } },
3448 { "(bad)", { XX } },
4e7d34a6 3449 /* 50 */
d5d7db8e
L		 3450 { "(bad)", { XX } },
3451 { "(bad)", { XX } },
3452 { "(bad)", { XX } },
3453 { "(bad)", { XX } },
3454 { "(bad)", { XX } },
3455 { "(bad)", { XX } },
3456 { "(bad)", { XX } },
3457 { "(bad)", { XX } },
4e7d34a6 3458 /* 58 */
d5d7db8e
L		 3459 { "(bad)", { XX } },
3460 { "(bad)", { XX } },
3461 { "(bad)", { XX } },
3462 { "(bad)", { XX } },
3463 { "(bad)", { XX } },
3464 { "(bad)", { XX } },
3465 { "(bad)", { XX } },
3466 { "(bad)", { XX } },
4e7d34a6 3467 /* 60 */
d5d7db8e
L		 3468 { "(bad)", { XX } },
3469 { "(bad)", { XX } },
3470 { "(bad)", { XX } },
3471 { "(bad)", { XX } },
3472 { "(bad)", { XX } },
3473 { "(bad)", { XX } },
3474 { "(bad)", { XX } },
3475 { "(bad)", { XX } },
4e7d34a6 3476 /* 68 */
d5d7db8e
L		 3477 { "(bad)", { XX } },
3478 { "(bad)", { XX } },
3479 { "(bad)", { XX } },
3480 { "(bad)", { XX } },
3481 { "(bad)", { XX } },
3482 { "(bad)", { XX } },
3483 { "(bad)", { XX } },
3484 { "(bad)", { XX } },
4e7d34a6 3485 /* 70 */
d5d7db8e
L		 3486 { "(bad)", { XX } },
3487 { "(bad)", { XX } },
3488 { "(bad)", { XX } },
3489 { "(bad)", { XX } },
3490 { "(bad)", { XX } },
3491 { "(bad)", { XX } },
3492 { "(bad)", { XX } },
3493 { "(bad)", { XX } },
4e7d34a6 3494 /* 78 */
d5d7db8e
L		 3495 { "(bad)", { XX } },
3496 { "(bad)", { XX } },
3497 { "(bad)", { XX } },
3498 { "(bad)", { XX } },
3499 { "(bad)", { XX } },
3500 { "(bad)", { XX } },
3501 { "(bad)", { XX } },
3502 { "(bad)", { XX } },
4e7d34a6 3503 /* 80 */
d5d7db8e
L		 3504 { "(bad)", { XX } },
3505 { "(bad)", { XX } },
3506 { "(bad)", { XX } },
3507 { "(bad)", { XX } },
3508 { "(bad)", { XX } },
3509 { "(bad)", { XX } },
3510 { "(bad)", { XX } },
3511 { "(bad)", { XX } },
4e7d34a6 3512 /* 88 */
d5d7db8e
L		 3513 { "(bad)", { XX } },
3514 { "(bad)", { XX } },
3515 { "(bad)", { XX } },
3516 { "(bad)", { XX } },
3517 { "(bad)", { XX } },
3518 { "(bad)", { XX } },
3519 { "(bad)", { XX } },
3520 { "(bad)", { XX } },
4e7d34a6 3521 /* 90 */
d5d7db8e
L		 3522 { "(bad)", { XX } },
3523 { "(bad)", { XX } },
3524 { "(bad)", { XX } },
3525 { "(bad)", { XX } },
3526 { "(bad)", { XX } },
3527 { "(bad)", { XX } },
3528 { "(bad)", { XX } },
3529 { "(bad)", { XX } },
4e7d34a6 3530 /* 98 */
d5d7db8e
L		 3531 { "(bad)", { XX } },
3532 { "(bad)", { XX } },
3533 { "(bad)", { XX } },
3534 { "(bad)", { XX } },
3535 { "(bad)", { XX } },
3536 { "(bad)", { XX } },
3537 { "(bad)", { XX } },
3538 { "(bad)", { XX } },
4e7d34a6 3539 /* a0 */
d5d7db8e
L		 3540 { "(bad)", { XX } },
3541 { "(bad)", { XX } },
3542 { "(bad)", { XX } },
3543 { "(bad)", { XX } },
3544 { "(bad)", { XX } },
3545 { "(bad)", { XX } },
3546 { "(bad)", { XX } },
3547 { "(bad)", { XX } },
4e7d34a6 3548 /* a8 */
d5d7db8e
L		 3549 { "(bad)", { XX } },
3550 { "(bad)", { XX } },
3551 { "(bad)", { XX } },
3552 { "(bad)", { XX } },
3553 { "(bad)", { XX } },
3554 { "(bad)", { XX } },
3555 { "(bad)", { XX } },
3556 { "(bad)", { XX } },
3557 /* b0 */
3558 { "(bad)", { XX } },
3559 { "(bad)", { XX } },
3560 { "(bad)", { XX } },
3561 { "(bad)", { XX } },
3562 { "(bad)", { XX } },
3563 { "(bad)", { XX } },
3564 { "(bad)", { XX } },
3565 { "(bad)", { XX } },
85f10a01 3566 /* b8 */
d5d7db8e
L		 3567 { "(bad)", { XX } },
3568 { "(bad)", { XX } },
3569 { "(bad)", { XX } },
3570 { "(bad)", { XX } },
3571 { "(bad)", { XX } },
3572 { "(bad)", { XX } },
3573 { "(bad)", { XX } },
3574 { "(bad)", { XX } },
85f10a01 3575 /* c0 */
d5d7db8e
L		 3576 { "(bad)", { XX } },
3577 { "(bad)", { XX } },
3578 { "(bad)", { XX } },
3579 { "(bad)", { XX } },
3580 { "(bad)", { XX } },
3581 { "(bad)", { XX } },
3582 { "(bad)", { XX } },
3583 { "(bad)", { XX } },
85f10a01 3584 /* c8 */
d5d7db8e
L		 3585 { "(bad)", { XX } },
3586 { "(bad)", { XX } },
3587 { "(bad)", { XX } },
3588 { "(bad)", { XX } },
3589 { "(bad)", { XX } },
3590 { "(bad)", { XX } },
3591 { "(bad)", { XX } },
3592 { "(bad)", { XX } },
85f10a01 3593 /* d0 */
d5d7db8e
L		 3594 { "(bad)", { XX } },
3595 { "(bad)", { XX } },
3596 { "(bad)", { XX } },
3597 { "(bad)", { XX } },
3598 { "(bad)", { XX } },
3599 { "(bad)", { XX } },
3600 { "(bad)", { XX } },
3601 { "(bad)", { XX } },
85f10a01 3602 /* d8 */
d5d7db8e
L		 3603 { "(bad)", { XX } },
3604 { "(bad)", { XX } },
3605 { "(bad)", { XX } },
3606 { "(bad)", { XX } },
3607 { "(bad)", { XX } },
3608 { "(bad)", { XX } },
3609 { "(bad)", { XX } },
3610 { "(bad)", { XX } },
85f10a01 3611 /* e0 */
d5d7db8e
L		 3612 { "(bad)", { XX } },
3613 { "(bad)", { XX } },
3614 { "(bad)", { XX } },
3615 { "(bad)", { XX } },
3616 { "(bad)", { XX } },
3617 { "(bad)", { XX } },
3618 { "(bad)", { XX } },
3619 { "(bad)", { XX } },
85f10a01 3620 /* e8 */
d5d7db8e
L		 3621 { "(bad)", { XX } },
3622 { "(bad)", { XX } },
3623 { "(bad)", { XX } },
3624 { "(bad)", { XX } },
3625 { "(bad)", { XX } },
3626 { "(bad)", { XX } },
3627 { "(bad)", { XX } },
3628 { "(bad)", { XX } },
85f10a01 3629 /* f0 */
1ceb70f8
L		 3630 { PREFIX_TABLE (PREFIX_0F38F0) },
3631 { PREFIX_TABLE (PREFIX_0F38F1) },
d5d7db8e
L		 3632 { "(bad)", { XX } },
3633 { "(bad)", { XX } },
3634 { "(bad)", { XX } },
3635 { "(bad)", { XX } },
3636 { "(bad)", { XX } },
3637 { "(bad)", { XX } },
85f10a01 3638 /* f8 */
d5d7db8e
L		 3639 { "(bad)", { XX } },
3640 { "(bad)", { XX } },
3641 { "(bad)", { XX } },
3642 { "(bad)", { XX } },
3643 { "(bad)", { XX } },
3644 { "(bad)", { XX } },
3645 { "(bad)", { XX } },
3646 { "(bad)", { XX } },
85f10a01 3647 },
4e7d34a6 3648 /* THREE_BYTE_0F3A */
85f10a01
MM		 3649 {
3650 /* 00 */
d5d7db8e
L		 3651 { "(bad)", { XX } },
3652 { "(bad)", { XX } },
3653 { "(bad)", { XX } },
3654 { "(bad)", { XX } },
3655 { "(bad)", { XX } },
3656 { "(bad)", { XX } },
3657 { "(bad)", { XX } },
3658 { "(bad)", { XX } },
85f10a01 3659 /* 08 */
1ceb70f8
L		 3660 { PREFIX_TABLE (PREFIX_0F3A08) },
3661 { PREFIX_TABLE (PREFIX_0F3A09) },
3662 { PREFIX_TABLE (PREFIX_0F3A0A) },
3663 { PREFIX_TABLE (PREFIX_0F3A0B) },
3664 { PREFIX_TABLE (PREFIX_0F3A0C) },
3665 { PREFIX_TABLE (PREFIX_0F3A0D) },
3666 { PREFIX_TABLE (PREFIX_0F3A0E) },
d5d7db8e 3667 { "palignr", { MX, EM, Ib } },
85f10a01 3668 /* 10 */
d5d7db8e
L		 3669 { "(bad)", { XX } },
3670 { "(bad)", { XX } },
3671 { "(bad)", { XX } },
3672 { "(bad)", { XX } },
1ceb70f8
L		 3673 { PREFIX_TABLE (PREFIX_0F3A14) },
3674 { PREFIX_TABLE (PREFIX_0F3A15) },
3675 { PREFIX_TABLE (PREFIX_0F3A16) },
3676 { PREFIX_TABLE (PREFIX_0F3A17) },
85f10a01 3677 /* 18 */
d5d7db8e
L		 3678 { "(bad)", { XX } },
3679 { "(bad)", { XX } },
3680 { "(bad)", { XX } },
3681 { "(bad)", { XX } },
3682 { "(bad)", { XX } },
3683 { "(bad)", { XX } },
3684 { "(bad)", { XX } },
3685 { "(bad)", { XX } },
85f10a01 3686 /* 20 */
1ceb70f8
L		 3687 { PREFIX_TABLE (PREFIX_0F3A20) },
3688 { PREFIX_TABLE (PREFIX_0F3A21) },
3689 { PREFIX_TABLE (PREFIX_0F3A22) },
d5d7db8e
L		 3690 { "(bad)", { XX } },
3691 { "(bad)", { XX } },
3692 { "(bad)", { XX } },
3693 { "(bad)", { XX } },
3694 { "(bad)", { XX } },
85f10a01 3695 /* 28 */
d5d7db8e
L		 3696 { "(bad)", { XX } },
3697 { "(bad)", { XX } },
3698 { "(bad)", { XX } },
3699 { "(bad)", { XX } },
3700 { "(bad)", { XX } },
3701 { "(bad)", { XX } },
3702 { "(bad)", { XX } },
3703 { "(bad)", { XX } },
85f10a01 3704 /* 30 */
d5d7db8e
L		 3705 { "(bad)", { XX } },
3706 { "(bad)", { XX } },
3707 { "(bad)", { XX } },
3708 { "(bad)", { XX } },
3709 { "(bad)", { XX } },
3710 { "(bad)", { XX } },
3711 { "(bad)", { XX } },
3712 { "(bad)", { XX } },
4e7d34a6 3713 /* 38 */
d5d7db8e
L		 3714 { "(bad)", { XX } },
3715 { "(bad)", { XX } },
3716 { "(bad)", { XX } },
3717 { "(bad)", { XX } },
3718 { "(bad)", { XX } },
3719 { "(bad)", { XX } },
3720 { "(bad)", { XX } },
3721 { "(bad)", { XX } },
3722 /* 40 */
3723 { PREFIX_TABLE (PREFIX_0F3A40) },
3724 { PREFIX_TABLE (PREFIX_0F3A41) },
3725 { PREFIX_TABLE (PREFIX_0F3A42) },
3726 { "(bad)", { XX } },
3727 { "(bad)", { XX } },
3728 { "(bad)", { XX } },
3729 { "(bad)", { XX } },
3730 { "(bad)", { XX } },
85f10a01 3731 /* 48 */
85f10a01
MM		 3732 { "(bad)", { XX } },
3733 { "(bad)", { XX } },
3734 { "(bad)", { XX } },
3735 { "(bad)", { XX } },
3736 { "(bad)", { XX } },
3737 { "(bad)", { XX } },
3738 { "(bad)", { XX } },
3739 { "(bad)", { XX } },
d5d7db8e 3740 /* 50 */
85f10a01
MM		 3741 { "(bad)", { XX } },
3742 { "(bad)", { XX } },
3743 { "(bad)", { XX } },
3744 { "(bad)", { XX } },
3745 { "(bad)", { XX } },
3746 { "(bad)", { XX } },
3747 { "(bad)", { XX } },
3748 { "(bad)", { XX } },
d5d7db8e 3749 /* 58 */
85f10a01
MM		 3750 { "(bad)", { XX } },
3751 { "(bad)", { XX } },
3752 { "(bad)", { XX } },
3753 { "(bad)", { XX } },
85f10a01
MM		 3754 { "(bad)", { XX } },
3755 { "(bad)", { XX } },
3756 { "(bad)", { XX } },
3757 { "(bad)", { XX } },
d5d7db8e
L		 3758 /* 60 */
3759 { PREFIX_TABLE (PREFIX_0F3A60) },
3760 { PREFIX_TABLE (PREFIX_0F3A61) },
3761 { PREFIX_TABLE (PREFIX_0F3A62) },
3762 { PREFIX_TABLE (PREFIX_0F3A63) },
85f10a01
MM		 3763 { "(bad)", { XX } },
3764 { "(bad)", { XX } },
3765 { "(bad)", { XX } },
3766 { "(bad)", { XX } },
d5d7db8e 3767 /* 68 */
85f10a01
MM		 3768 { "(bad)", { XX } },
3769 { "(bad)", { XX } },
3770 { "(bad)", { XX } },
3771 { "(bad)", { XX } },
3772 { "(bad)", { XX } },
3773 { "(bad)", { XX } },
3774 { "(bad)", { XX } },
85f10a01 3775 { "(bad)", { XX } },
d5d7db8e 3776 /* 70 */
85f10a01
MM		 3777 { "(bad)", { XX } },
3778 { "(bad)", { XX } },
3779 { "(bad)", { XX } },
d5d7db8e
L		 3780 { "(bad)", { XX } },
3781 { "(bad)", { XX } },
3782 { "(bad)", { XX } },
3783 { "(bad)", { XX } },
3784 { "(bad)", { XX } },
3785 /* 78 */
3786 { "(bad)", { XX } },
3787 { "(bad)", { XX } },
3788 { "(bad)", { XX } },
3789 { "(bad)", { XX } },
3790 { "(bad)", { XX } },
3791 { "(bad)", { XX } },
3792 { "(bad)", { XX } },
3793 { "(bad)", { XX } },
3794 /* 80 */
3795 { "(bad)", { XX } },
3796 { "(bad)", { XX } },
3797 { "(bad)", { XX } },
3798 { "(bad)", { XX } },
3799 { "(bad)", { XX } },
3800 { "(bad)", { XX } },
3801 { "(bad)", { XX } },
3802 { "(bad)", { XX } },
3803 /* 88 */
3804 { "(bad)", { XX } },
3805 { "(bad)", { XX } },
3806 { "(bad)", { XX } },
3807 { "(bad)", { XX } },
3808 { "(bad)", { XX } },
3809 { "(bad)", { XX } },
3810 { "(bad)", { XX } },
3811 { "(bad)", { XX } },
3812 /* 90 */
3813 { "(bad)", { XX } },
3814 { "(bad)", { XX } },
3815 { "(bad)", { XX } },
3816 { "(bad)", { XX } },
3817 { "(bad)", { XX } },
3818 { "(bad)", { XX } },
3819 { "(bad)", { XX } },
3820 { "(bad)", { XX } },
3821 /* 98 */
3822 { "(bad)", { XX } },
3823 { "(bad)", { XX } },
3824 { "(bad)", { XX } },
3825 { "(bad)", { XX } },
3826 { "(bad)", { XX } },
3827 { "(bad)", { XX } },
3828 { "(bad)", { XX } },
3829 { "(bad)", { XX } },
3830 /* a0 */
3831 { "(bad)", { XX } },
3832 { "(bad)", { XX } },
3833 { "(bad)", { XX } },
3834 { "(bad)", { XX } },
3835 { "(bad)", { XX } },
3836 { "(bad)", { XX } },
3837 { "(bad)", { XX } },
3838 { "(bad)", { XX } },
3839 /* a8 */
3840 { "(bad)", { XX } },
3841 { "(bad)", { XX } },
3842 { "(bad)", { XX } },
3843 { "(bad)", { XX } },
3844 { "(bad)", { XX } },
3845 { "(bad)", { XX } },
3846 { "(bad)", { XX } },
3847 { "(bad)", { XX } },
3848 /* b0 */
3849 { "(bad)", { XX } },
3850 { "(bad)", { XX } },
3851 { "(bad)", { XX } },
3852 { "(bad)", { XX } },
3853 { "(bad)", { XX } },
3854 { "(bad)", { XX } },
3855 { "(bad)", { XX } },
3856 { "(bad)", { XX } },
3857 /* b8 */
3858 { "(bad)", { XX } },
3859 { "(bad)", { XX } },
3860 { "(bad)", { XX } },
3861 { "(bad)", { XX } },
3862 { "(bad)", { XX } },
3863 { "(bad)", { XX } },
3864 { "(bad)", { XX } },
3865 { "(bad)", { XX } },
3866 /* c0 */
3867 { "(bad)", { XX } },
3868 { "(bad)", { XX } },
3869 { "(bad)", { XX } },
3870 { "(bad)", { XX } },
3871 { "(bad)", { XX } },
3872 { "(bad)", { XX } },
3873 { "(bad)", { XX } },
3874 { "(bad)", { XX } },
3875 /* c8 */
3876 { "(bad)", { XX } },
3877 { "(bad)", { XX } },
3878 { "(bad)", { XX } },
3879 { "(bad)", { XX } },
3880 { "(bad)", { XX } },
3881 { "(bad)", { XX } },
3882 { "(bad)", { XX } },
3883 { "(bad)", { XX } },
3884 /* d0 */
3885 { "(bad)", { XX } },
3886 { "(bad)", { XX } },
3887 { "(bad)", { XX } },
3888 { "(bad)", { XX } },
3889 { "(bad)", { XX } },
3890 { "(bad)", { XX } },
3891 { "(bad)", { XX } },
3892 { "(bad)", { XX } },
3893 /* d8 */
3894 { "(bad)", { XX } },
3895 { "(bad)", { XX } },
3896 { "(bad)", { XX } },
3897 { "(bad)", { XX } },
3898 { "(bad)", { XX } },
3899 { "(bad)", { XX } },
3900 { "(bad)", { XX } },
3901 { "(bad)", { XX } },
3902 /* e0 */
3903 { "(bad)", { XX } },
3904 { "(bad)", { XX } },
3905 { "(bad)", { XX } },
3906 { "(bad)", { XX } },
3907 { "(bad)", { XX } },
3908 { "(bad)", { XX } },
3909 { "(bad)", { XX } },
3910 { "(bad)", { XX } },
3911 /* e8 */
3912 { "(bad)", { XX } },
3913 { "(bad)", { XX } },
3914 { "(bad)", { XX } },
3915 { "(bad)", { XX } },
3916 { "(bad)", { XX } },
3917 { "(bad)", { XX } },
3918 { "(bad)", { XX } },
3919 { "(bad)", { XX } },
3920 /* f0 */
3921 { "(bad)", { XX } },
3922 { "(bad)", { XX } },
3923 { "(bad)", { XX } },
3924 { "(bad)", { XX } },
3925 { "(bad)", { XX } },
3926 { "(bad)", { XX } },
3927 { "(bad)", { XX } },
3928 { "(bad)", { XX } },
3929 /* f8 */
3930 { "(bad)", { XX } },
3931 { "(bad)", { XX } },
3932 { "(bad)", { XX } },
3933 { "(bad)", { XX } },
3934 { "(bad)", { XX } },
3935 { "(bad)", { XX } },
3936 { "(bad)", { XX } },
3937 { "(bad)", { XX } },
3938 },
3939 /* THREE_BYTE_0F7A */
3940 {
3941 /* 00 */
3942 { "(bad)", { XX } },
3943 { "(bad)", { XX } },
3944 { "(bad)", { XX } },
3945 { "(bad)", { XX } },
3946 { "(bad)", { XX } },
3947 { "(bad)", { XX } },
3948 { "(bad)", { XX } },
3949 { "(bad)", { XX } },
3950 /* 08 */
3951 { "(bad)", { XX } },
3952 { "(bad)", { XX } },
3953 { "(bad)", { XX } },
3954 { "(bad)", { XX } },
3955 { "(bad)", { XX } },
3956 { "(bad)", { XX } },
3957 { "(bad)", { XX } },
3958 { "(bad)", { XX } },
3959 /* 10 */
3960 { "frczps", { XM, EXq } },
3961 { "frczpd", { XM, EXq } },
3962 { "frczss", { XM, EXq } },
3963 { "frczsd", { XM, EXq } },
3964 { "(bad)", { XX } },
3965 { "(bad)", { XX } },
3966 { "(bad)", { XX } },
3967 { "(bad)", { XX } },
3968 /* 18 */
3969 { "(bad)", { XX } },
3970 { "(bad)", { XX } },
3971 { "(bad)", { XX } },
3972 { "(bad)", { XX } },
3973 { "(bad)", { XX } },
3974 { "(bad)", { XX } },
3975 { "(bad)", { XX } },
3976 { "(bad)", { XX } },
3977 /* 20 */
3978 { "ptest", { XX } },
3979 { "(bad)", { XX } },
3980 { "(bad)", { XX } },
3981 { "(bad)", { XX } },
3982 { "(bad)", { XX } },
3983 { "(bad)", { XX } },
3984 { "(bad)", { XX } },
3985 { "(bad)", { XX } },
3986 /* 28 */
3987 { "(bad)", { XX } },
3988 { "(bad)", { XX } },
3989 { "(bad)", { XX } },
3990 { "(bad)", { XX } },
3991 { "(bad)", { XX } },
3992 { "(bad)", { XX } },
3993 { "(bad)", { XX } },
3994 { "(bad)", { XX } },
3995 /* 30 */
85f10a01
MM		 3996 { "cvtph2ps", { XM, EXd } },
3997 { "cvtps2ph", { EXd, XM } },
d5d7db8e
L		 3998 { "(bad)", { XX } },
3999 { "(bad)", { XX } },
4000 { "(bad)", { XX } },
4001 { "(bad)", { XX } },
4002 { "(bad)", { XX } },
4003 { "(bad)", { XX } },
85f10a01 4004 /* 38 */
d5d7db8e
L		 4005 { "(bad)", { XX } },
4006 { "(bad)", { XX } },
4007 { "(bad)", { XX } },
4008 { "(bad)", { XX } },
4009 { "(bad)", { XX } },
4010 { "(bad)", { XX } },
4011 { "(bad)", { XX } },
4012 { "(bad)", { XX } },
96fbad73 4013 /* 40 */
d5d7db8e 4014 { "(bad)", { XX } },
85f10a01
MM		 4015 { "phaddbw", { XM, EXq } },
4016 { "phaddbd", { XM, EXq } },
4017 { "phaddbq", { XM, EXq } },
d5d7db8e
L		 4018 { "(bad)", { XX } },
4019 { "(bad)", { XX } },
85f10a01
MM		 4020 { "phaddwd", { XM, EXq } },
4021 { "phaddwq", { XM, EXq } },
96fbad73 4022 /* 48 */
d5d7db8e
L		 4023 { "(bad)", { XX } },
4024 { "(bad)", { XX } },
4025 { "(bad)", { XX } },
85f10a01 4026 { "phadddq", { XM, EXq } },
d5d7db8e
L		 4027 { "(bad)", { XX } },
4028 { "(bad)", { XX } },
4029 { "(bad)", { XX } },
4030 { "(bad)", { XX } },
96fbad73 4031 /* 50 */
d5d7db8e 4032 { "(bad)", { XX } },
85f10a01
MM		 4033 { "phaddubw", { XM, EXq } },
4034 { "phaddubd", { XM, EXq } },
4035 { "phaddubq", { XM, EXq } },
d5d7db8e
L		 4036 { "(bad)", { XX } },
4037 { "(bad)", { XX } },
85f10a01
MM		 4038 { "phadduwd", { XM, EXq } },
4039 { "phadduwq", { XM, EXq } },
96fbad73 4040 /* 58 */
d5d7db8e
L		 4041 { "(bad)", { XX } },
4042 { "(bad)", { XX } },
4043 { "(bad)", { XX } },
85f10a01 4044 { "phaddudq", { XM, EXq } },
d5d7db8e
L		 4045 { "(bad)", { XX } },
4046 { "(bad)", { XX } },
4047 { "(bad)", { XX } },
4048 { "(bad)", { XX } },
96fbad73 4049 /* 60 */
d5d7db8e 4050 { "(bad)", { XX } },
85f10a01
MM		 4051 { "phsubbw", { XM, EXq } },
4052 { "phsubbd", { XM, EXq } },
4053 { "phsubbq", { XM, EXq } },
d5d7db8e
L		 4054 { "(bad)", { XX } },
4055 { "(bad)", { XX } },
4056 { "(bad)", { XX } },
4057 { "(bad)", { XX } },
96fbad73 4058 /* 68 */
d5d7db8e
L		 4059 { "(bad)", { XX } },
4060 { "(bad)", { XX } },
4061 { "(bad)", { XX } },
4062 { "(bad)", { XX } },
4063 { "(bad)", { XX } },
4064 { "(bad)", { XX } },
4065 { "(bad)", { XX } },
4066 { "(bad)", { XX } },
96fbad73 4067 /* 70 */
d5d7db8e
L		 4068 { "(bad)", { XX } },
4069 { "(bad)", { XX } },
4070 { "(bad)", { XX } },
4071 { "(bad)", { XX } },
4072 { "(bad)", { XX } },
4073 { "(bad)", { XX } },
4074 { "(bad)", { XX } },
4075 { "(bad)", { XX } },
96fbad73 4076 /* 78 */
d5d7db8e
L		 4077 { "(bad)", { XX } },
4078 { "(bad)", { XX } },
4079 { "(bad)", { XX } },
4080 { "(bad)", { XX } },
4081 { "(bad)", { XX } },
4082 { "(bad)", { XX } },
4083 { "(bad)", { XX } },
4084 { "(bad)", { XX } },
96fbad73 4085 /* 80 */
d5d7db8e
L		 4086 { "(bad)", { XX } },
4087 { "(bad)", { XX } },
4088 { "(bad)", { XX } },
4089 { "(bad)", { XX } },
4090 { "(bad)", { XX } },
4091 { "(bad)", { XX } },
4092 { "(bad)", { XX } },
4093 { "(bad)", { XX } },
96fbad73 4094 /* 88 */
d5d7db8e
L		 4095 { "(bad)", { XX } },
4096 { "(bad)", { XX } },
4097 { "(bad)", { XX } },
4098 { "(bad)", { XX } },
4099 { "(bad)", { XX } },
4100 { "(bad)", { XX } },
4101 { "(bad)", { XX } },
4102 { "(bad)", { XX } },
96fbad73 4103 /* 90 */
d5d7db8e
L		 4104 { "(bad)", { XX } },
4105 { "(bad)", { XX } },
4106 { "(bad)", { XX } },
4107 { "(bad)", { XX } },
4108 { "(bad)", { XX } },
4109 { "(bad)", { XX } },
4110 { "(bad)", { XX } },
4111 { "(bad)", { XX } },
96fbad73 4112 /* 98 */
d5d7db8e
L		 4113 { "(bad)", { XX } },
4114 { "(bad)", { XX } },
4115 { "(bad)", { XX } },
4116 { "(bad)", { XX } },
4117 { "(bad)", { XX } },
4118 { "(bad)", { XX } },
4119 { "(bad)", { XX } },
4120 { "(bad)", { XX } },
96fbad73 4121 /* a0 */
d5d7db8e
L		 4122 { "(bad)", { XX } },
4123 { "(bad)", { XX } },
4124 { "(bad)", { XX } },
4125 { "(bad)", { XX } },
4126 { "(bad)", { XX } },
4127 { "(bad)", { XX } },
4128 { "(bad)", { XX } },
4129 { "(bad)", { XX } },
96fbad73 4130 /* a8 */
d5d7db8e
L		 4131 { "(bad)", { XX } },
4132 { "(bad)", { XX } },
4133 { "(bad)", { XX } },
4134 { "(bad)", { XX } },
4135 { "(bad)", { XX } },
4136 { "(bad)", { XX } },
4137 { "(bad)", { XX } },
4138 { "(bad)", { XX } },
96fbad73 4139 /* b0 */
d5d7db8e
L		 4140 { "(bad)", { XX } },
4141 { "(bad)", { XX } },
4142 { "(bad)", { XX } },
4143 { "(bad)", { XX } },
4144 { "(bad)", { XX } },
4145 { "(bad)", { XX } },
4146 { "(bad)", { XX } },
4147 { "(bad)", { XX } },
96fbad73 4148 /* b8 */
d5d7db8e
L		 4149 { "(bad)", { XX } },
4150 { "(bad)", { XX } },
4151 { "(bad)", { XX } },
4152 { "(bad)", { XX } },
4153 { "(bad)", { XX } },
4154 { "(bad)", { XX } },
4155 { "(bad)", { XX } },
4156 { "(bad)", { XX } },
96fbad73 4157 /* c0 */
d5d7db8e
L		 4158 { "(bad)", { XX } },
4159 { "(bad)", { XX } },
4160 { "(bad)", { XX } },
4161 { "(bad)", { XX } },
4162 { "(bad)", { XX } },
4163 { "(bad)", { XX } },
4164 { "(bad)", { XX } },
4165 { "(bad)", { XX } },
96fbad73 4166 /* c8 */
d5d7db8e
L		 4167 { "(bad)", { XX } },
4168 { "(bad)", { XX } },
4169 { "(bad)", { XX } },
4170 { "(bad)", { XX } },
4171 { "(bad)", { XX } },
4172 { "(bad)", { XX } },
4173 { "(bad)", { XX } },
4174 { "(bad)", { XX } },
96fbad73 4175 /* d0 */
d5d7db8e
L		 4176 { "(bad)", { XX } },
4177 { "(bad)", { XX } },
4178 { "(bad)", { XX } },
4179 { "(bad)", { XX } },
4180 { "(bad)", { XX } },
4181 { "(bad)", { XX } },
4182 { "(bad)", { XX } },
4183 { "(bad)", { XX } },
96fbad73 4184 /* d8 */
d5d7db8e
L		 4185 { "(bad)", { XX } },
4186 { "(bad)", { XX } },
4187 { "(bad)", { XX } },
4188 { "(bad)", { XX } },
4189 { "(bad)", { XX } },
4190 { "(bad)", { XX } },
4191 { "(bad)", { XX } },
4192 { "(bad)", { XX } },
96fbad73 4193 /* e0 */
d5d7db8e
L		 4194 { "(bad)", { XX } },
4195 { "(bad)", { XX } },
4196 { "(bad)", { XX } },
4197 { "(bad)", { XX } },
4198 { "(bad)", { XX } },
4199 { "(bad)", { XX } },
4200 { "(bad)", { XX } },
4201 { "(bad)", { XX } },
96fbad73 4202 /* e8 */
d5d7db8e
L		 4203 { "(bad)", { XX } },
4204 { "(bad)", { XX } },
4205 { "(bad)", { XX } },
4206 { "(bad)", { XX } },
4207 { "(bad)", { XX } },
4208 { "(bad)", { XX } },
4209 { "(bad)", { XX } },
4210 { "(bad)", { XX } },
96fbad73 4211 /* f0 */
85f10a01
MM		 4212 { "(bad)", { XX } },
4213 { "(bad)", { XX } },
d5d7db8e
L		 4214 { "(bad)", { XX } },
4215 { "(bad)", { XX } },
4216 { "(bad)", { XX } },
4217 { "(bad)", { XX } },
4218 { "(bad)", { XX } },
4219 { "(bad)", { XX } },
96fbad73 4220 /* f8 */
d5d7db8e
L		 4221 { "(bad)", { XX } },
4222 { "(bad)", { XX } },
4223 { "(bad)", { XX } },
4224 { "(bad)", { XX } },
4225 { "(bad)", { XX } },
4226 { "(bad)", { XX } },
4227 { "(bad)", { XX } },
4228 { "(bad)", { XX } },
331d2d0d 4229 },
89b66d55 4230 /* THREE_BYTE_0F7B */
331d2d0d 4231 {
96fbad73 4232 /* 00 */
d5d7db8e
L		 4233 { "(bad)", { XX } },
4234 { "(bad)", { XX } },
4235 { "(bad)", { XX } },
4236 { "(bad)", { XX } },
4237 { "(bad)", { XX } },
4238 { "(bad)", { XX } },
4239 { "(bad)", { XX } },
4240 { "(bad)", { XX } },
96fbad73 4241 /* 08 */
d5d7db8e
L		 4242 { "(bad)", { XX } },
4243 { "(bad)", { XX } },
4244 { "(bad)", { XX } },
4245 { "(bad)", { XX } },
4246 { "(bad)", { XX } },
4247 { "(bad)", { XX } },
4248 { "(bad)", { XX } },
4249 { "(bad)", { XX } },
85f10a01 4250 /* 10 */
d5d7db8e
L		 4251 { "(bad)", { XX } },
4252 { "(bad)", { XX } },
4253 { "(bad)", { XX } },
4254 { "(bad)", { XX } },
4255 { "(bad)", { XX } },
4256 { "(bad)", { XX } },
4257 { "(bad)", { XX } },
4258 { "(bad)", { XX } },
85f10a01 4259 /* 18 */
d5d7db8e
L		 4260 { "(bad)", { XX } },
4261 { "(bad)", { XX } },
4262 { "(bad)", { XX } },
4263 { "(bad)", { XX } },
4264 { "(bad)", { XX } },
4265 { "(bad)", { XX } },
4266 { "(bad)", { XX } },
4267 { "(bad)", { XX } },
85f10a01 4268 /* 20 */
d5d7db8e
L		 4269 { "(bad)", { XX } },
4270 { "(bad)", { XX } },
4271 { "(bad)", { XX } },
4272 { "(bad)", { XX } },
4273 { "(bad)", { XX } },
4274 { "(bad)", { XX } },
4275 { "(bad)", { XX } },
4276 { "(bad)", { XX } },
85f10a01 4277 /* 28 */
d5d7db8e
L		 4278 { "(bad)", { XX } },
4279 { "(bad)", { XX } },
4280 { "(bad)", { XX } },
4281 { "(bad)", { XX } },
4282 { "(bad)", { XX } },
4283 { "(bad)", { XX } },
4284 { "(bad)", { XX } },
4285 { "(bad)", { XX } },
85f10a01 4286 /* 30 */
d5d7db8e
L		 4287 { "(bad)", { XX } },
4288 { "(bad)", { XX } },
4289 { "(bad)", { XX } },
4290 { "(bad)", { XX } },
4291 { "(bad)", { XX } },
4292 { "(bad)", { XX } },
85f10a01
MM		 4293 { "(bad)", { XX } },
4294 { "(bad)", { XX } },
4295 /* 38 */
4296 { "(bad)", { XX } },
4297 { "(bad)", { XX } },
4298 { "(bad)", { XX } },
d5d7db8e
L		 4299 { "(bad)", { XX } },
4300 { "(bad)", { XX } },
4301 { "(bad)", { XX } },
4302 { "(bad)", { XX } },
4303 { "(bad)", { XX } },
85f10a01
MM		 4304 /* 40 */
4305 { "protb", { XM, EXq, Ib } },
4306 { "protw", { XM, EXq, Ib } },
4307 { "protd", { XM, EXq, Ib } },
4308 { "protq", { XM, EXq, Ib } },
4309 { "pshlb", { XM, EXq, Ib } },
4310 { "pshlw", { XM, EXq, Ib } },
4311 { "pshld", { XM, EXq, Ib } },
4312 { "pshlq", { XM, EXq, Ib } },
4313 /* 48 */
4314 { "pshab", { XM, EXq, Ib } },
4315 { "pshaw", { XM, EXq, Ib } },
4316 { "pshad", { XM, EXq, Ib } },
4317 { "pshaq", { XM, EXq, Ib } },
4318 { "(bad)", { XX } },
d5d7db8e
L		 4319 { "(bad)", { XX } },
4320 { "(bad)", { XX } },
4321 { "(bad)", { XX } },
96fbad73 4322 /* 50 */
d5d7db8e
L		 4323 { "(bad)", { XX } },
4324 { "(bad)", { XX } },
4325 { "(bad)", { XX } },
4326 { "(bad)", { XX } },
4327 { "(bad)", { XX } },
4328 { "(bad)", { XX } },
4329 { "(bad)", { XX } },
4330 { "(bad)", { XX } },
96fbad73 4331 /* 58 */
d5d7db8e
L		 4332 { "(bad)", { XX } },
4333 { "(bad)", { XX } },
4334 { "(bad)", { XX } },
4335 { "(bad)", { XX } },
4336 { "(bad)", { XX } },
4337 { "(bad)", { XX } },
4338 { "(bad)", { XX } },
4339 { "(bad)", { XX } },
96fbad73 4340 /* 60 */
85f10a01
MM		 4341 { "(bad)", { XX } },
4342 { "(bad)", { XX } },
4343 { "(bad)", { XX } },
4344 { "(bad)", { XX } },
d5d7db8e
L		 4345 { "(bad)", { XX } },
4346 { "(bad)", { XX } },
4347 { "(bad)", { XX } },
4348 { "(bad)", { XX } },
96fbad73 4349 /* 68 */
d5d7db8e
L		 4350 { "(bad)", { XX } },
4351 { "(bad)", { XX } },
4352 { "(bad)", { XX } },
4353 { "(bad)", { XX } },
4354 { "(bad)", { XX } },
4355 { "(bad)", { XX } },
4356 { "(bad)", { XX } },
4357 { "(bad)", { XX } },
96fbad73 4358 /* 70 */
d5d7db8e
L		 4359 { "(bad)", { XX } },
4360 { "(bad)", { XX } },
4361 { "(bad)", { XX } },
4362 { "(bad)", { XX } },
4363 { "(bad)", { XX } },
4364 { "(bad)", { XX } },
4365 { "(bad)", { XX } },
4366 { "(bad)", { XX } },
96fbad73 4367 /* 78 */
d5d7db8e
L		 4368 { "(bad)", { XX } },
4369 { "(bad)", { XX } },
4370 { "(bad)", { XX } },
4371 { "(bad)", { XX } },
4372 { "(bad)", { XX } },
4373 { "(bad)", { XX } },
4374 { "(bad)", { XX } },
4375 { "(bad)", { XX } },
96fbad73 4376 /* 80 */
d5d7db8e
L		 4377 { "(bad)", { XX } },
4378 { "(bad)", { XX } },
4379 { "(bad)", { XX } },
4380 { "(bad)", { XX } },
4381 { "(bad)", { XX } },
4382 { "(bad)", { XX } },
4383 { "(bad)", { XX } },
4384 { "(bad)", { XX } },
96fbad73 4385 /* 88 */
d5d7db8e
L		 4386 { "(bad)", { XX } },
4387 { "(bad)", { XX } },
4388 { "(bad)", { XX } },
4389 { "(bad)", { XX } },
4390 { "(bad)", { XX } },
4391 { "(bad)", { XX } },
4392 { "(bad)", { XX } },
4393 { "(bad)", { XX } },
96fbad73 4394 /* 90 */
d5d7db8e
L		 4395 { "(bad)", { XX } },
4396 { "(bad)", { XX } },
4397 { "(bad)", { XX } },
4398 { "(bad)", { XX } },
4399 { "(bad)", { XX } },
4400 { "(bad)", { XX } },
4401 { "(bad)", { XX } },
4402 { "(bad)", { XX } },
96fbad73 4403 /* 98 */
d5d7db8e
L		 4404 { "(bad)", { XX } },
4405 { "(bad)", { XX } },
4406 { "(bad)", { XX } },
4407 { "(bad)", { XX } },
4408 { "(bad)", { XX } },
4409 { "(bad)", { XX } },
4410 { "(bad)", { XX } },
4411 { "(bad)", { XX } },
96fbad73 4412 /* a0 */
d5d7db8e
L		 4413 { "(bad)", { XX } },
4414 { "(bad)", { XX } },
4415 { "(bad)", { XX } },
4416 { "(bad)", { XX } },
4417 { "(bad)", { XX } },
4418 { "(bad)", { XX } },
4419 { "(bad)", { XX } },
4420 { "(bad)", { XX } },
96fbad73 4421 /* a8 */
d5d7db8e
L		 4422 { "(bad)", { XX } },
4423 { "(bad)", { XX } },
4424 { "(bad)", { XX } },
4425 { "(bad)", { XX } },
4426 { "(bad)", { XX } },
4427 { "(bad)", { XX } },
4428 { "(bad)", { XX } },
4429 { "(bad)", { XX } },
96fbad73 4430 /* b0 */
d5d7db8e
L		 4431 { "(bad)", { XX } },
4432 { "(bad)", { XX } },
4433 { "(bad)", { XX } },
4434 { "(bad)", { XX } },
4435 { "(bad)", { XX } },
4436 { "(bad)", { XX } },
4437 { "(bad)", { XX } },
4438 { "(bad)", { XX } },
96fbad73 4439 /* b8 */
d5d7db8e
L		 4440 { "(bad)", { XX } },
4441 { "(bad)", { XX } },
4442 { "(bad)", { XX } },
4443 { "(bad)", { XX } },
4444 { "(bad)", { XX } },
4445 { "(bad)", { XX } },
4446 { "(bad)", { XX } },
4447 { "(bad)", { XX } },
96fbad73 4448 /* c0 */
d5d7db8e
L		 4449 { "(bad)", { XX } },
4450 { "(bad)", { XX } },
4451 { "(bad)", { XX } },
4452 { "(bad)", { XX } },
4453 { "(bad)", { XX } },
4454 { "(bad)", { XX } },
4455 { "(bad)", { XX } },
4456 { "(bad)", { XX } },
96fbad73 4457 /* c8 */
d5d7db8e
L		 4458 { "(bad)", { XX } },
4459 { "(bad)", { XX } },
4460 { "(bad)", { XX } },
4461 { "(bad)", { XX } },
4462 { "(bad)", { XX } },
4463 { "(bad)", { XX } },
4464 { "(bad)", { XX } },
4465 { "(bad)", { XX } },
96fbad73 4466 /* d0 */
d5d7db8e
L		 4467 { "(bad)", { XX } },
4468 { "(bad)", { XX } },
4469 { "(bad)", { XX } },
4470 { "(bad)", { XX } },
4471 { "(bad)", { XX } },
4472 { "(bad)", { XX } },
4473 { "(bad)", { XX } },
4474 { "(bad)", { XX } },
96fbad73 4475 /* d8 */
d5d7db8e
L		 4476 { "(bad)", { XX } },
4477 { "(bad)", { XX } },
4478 { "(bad)", { XX } },
4479 { "(bad)", { XX } },
4480 { "(bad)", { XX } },
4481 { "(bad)", { XX } },
4482 { "(bad)", { XX } },
4483 { "(bad)", { XX } },
96fbad73 4484 /* e0 */
d5d7db8e
L		 4485 { "(bad)", { XX } },
4486 { "(bad)", { XX } },
4487 { "(bad)", { XX } },
4488 { "(bad)", { XX } },
4489 { "(bad)", { XX } },
4490 { "(bad)", { XX } },
4491 { "(bad)", { XX } },
4492 { "(bad)", { XX } },
96fbad73 4493 /* e8 */
d5d7db8e
L		 4494 { "(bad)", { XX } },
4495 { "(bad)", { XX } },
4496 { "(bad)", { XX } },
4497 { "(bad)", { XX } },
4498 { "(bad)", { XX } },
4499 { "(bad)", { XX } },
4500 { "(bad)", { XX } },
4501 { "(bad)", { XX } },
96fbad73 4502 /* f0 */
d5d7db8e
L		 4503 { "(bad)", { XX } },
4504 { "(bad)", { XX } },
4505 { "(bad)", { XX } },
4506 { "(bad)", { XX } },
4507 { "(bad)", { XX } },
4508 { "(bad)", { XX } },
4509 { "(bad)", { XX } },
4510 { "(bad)", { XX } },
96fbad73 4511 /* f8 */
d5d7db8e
L		 4512 { "(bad)", { XX } },
4513 { "(bad)", { XX } },
4514 { "(bad)", { XX } },
4515 { "(bad)", { XX } },
4516 { "(bad)", { XX } },
4517 { "(bad)", { XX } },
4518 { "(bad)", { XX } },
4519 { "(bad)", { XX } },
ce518a5f 4520 }
331d2d0d
L		 4521};
4522
1ceb70f8 4523static const struct dis386 mod_table[][2] = {
b844680a 4524 {
1ceb70f8 4525 /* MOD_8D */
d8faab4e
L		 4526 { "leaS", { Gv, M } },
4527 { "(bad)", { XX } },
4528 },
4529 {
92fddf8e
L		 4530 /* MOD_0F01_REG_0 */
4531 { X86_64_TABLE (X86_64_0F01_REG_0) },
4532 { RM_TABLE (RM_0F01_REG_0) },
d8faab4e
L		 4533 },
4534 {
92fddf8e
L		 4535 /* MOD_0F01_REG_1 */
4536 { X86_64_TABLE (X86_64_0F01_REG_1) },
4537 { RM_TABLE (RM_0F01_REG_1) },
d8faab4e
L		 4538 },
4539 {
92fddf8e
L		 4540 /* MOD_0F01_REG_2 */
4541 { X86_64_TABLE (X86_64_0F01_REG_2) },
d8faab4e
L		 4542 { "(bad)", { XX } },
4543 },
4544 {
92fddf8e
L		 4545 /* MOD_0F01_REG_3 */
4546 { X86_64_TABLE (X86_64_0F01_REG_3) },
4547 { RM_TABLE (RM_0F01_REG_3) },
d8faab4e
L		 4548 },
4549 {
92fddf8e
L		 4550 /* MOD_0F01_REG_7 */
4551 { "invlpg", { Mb } },
4552 { RM_TABLE (RM_0F01_REG_7) },
b844680a
L		 4553 },
4554 {
92fddf8e
L		 4555 /* MOD_0F12_PREFIX_0 */
4556 { "movlps", { XM, EXq } },
4557 { "movhlps", { XM, EXq } },
b844680a
L		 4558 },
4559 {
92fddf8e
L		 4560 /* MOD_0F13 */
4561 { "movlpX", { EXq, XM } },
d8faab4e
L		 4562 { "(bad)", { XX } },
4563 },
4564 {
92fddf8e
L		 4565 /* MOD_0F16_PREFIX_0 */
4566 { "movhps", { XM, EXq } },
4567 { "movlhps", { XM, EXq } },
b844680a
L		 4568 },
4569 {
92fddf8e
L		 4570 /* MOD_0F17 */
4571 { "movhpX", { EXq, XM } },
b844680a
L		 4572 { "(bad)", { XX } },
4573 },
4574 {
92fddf8e
L		 4575 /* MOD_0F18_REG_0 */
4576 { "prefetchnta", { Mb } },
b844680a 4577 { "(bad)", { XX } },
b844680a
L		 4578 },
4579 {
92fddf8e
L		 4580 /* MOD_0F18_REG_1 */
4581 { "prefetcht0", { Mb } },
4582 { "(bad)", { XX } },
b844680a
L		 4583 },
4584 {
92fddf8e
L		 4585 /* MOD_0F18_REG_2 */
4586 { "prefetcht1", { Mb } },
4587 { "(bad)", { XX } },
b844680a
L		 4588 },
4589 {
92fddf8e
L		 4590 /* MOD_0F18_REG_3 */
4591 { "prefetcht2", { Mb } },
b844680a 4592 { "(bad)", { XX } },
b844680a
L		 4593 },
4594 {
92fddf8e
L		 4595 /* MOD_0F20 */
4596 { "(bad)", { XX } },
4597 { "movZ", { Rm, Cm } },
b844680a
L		 4598 },
4599 {
92fddf8e
L		 4600 /* MOD_0F21 */
4601 { "(bad)", { XX } },
4602 { "movZ", { Rm, Dm } },
b844680a
L		 4603 },
4604 {
92fddf8e 4605 /* MOD_0F22 */
b844680a 4606 { "(bad)", { XX } },
92fddf8e 4607 { "movZ", { Cm, Rm } },
b844680a
L		 4608 },
4609 {
92fddf8e 4610 /* MOD_0F23 */
b844680a 4611 { "(bad)", { XX } },
92fddf8e 4612 { "movZ", { Dm, Rm } },
b844680a
L		 4613 },
4614 {
92fddf8e
L		 4615 /* MOD_0F24 */
4616 { THREE_BYTE_TABLE (THREE_BYTE_0F24) },
4617 { "movL", { Rd, Td } },
b844680a
L		 4618 },
4619 {
92fddf8e 4620 /* MOD_0F26 */
b844680a 4621 { "(bad)", { XX } },
92fddf8e 4622 { "movL", { Td, Rd } },
b844680a 4623 },
75c135a8
L		 4624 {
4625 /* MOD_0F2B_PREFIX_0 */
4626 {"movntps", { Ev, XM } },
4627 { "(bad)", { XX } },
4628 },
4629 {
4630 /* MOD_0F2B_PREFIX_1 */
4631 {"movntss", { Ed, XM } },
4632 { "(bad)", { XX } },
4633 },
4634 {
4635 /* MOD_0F2B_PREFIX_2 */
4636 {"movntpd", { Ev, XM } },
4637 { "(bad)", { XX } },
4638 },
4639 {
4640 /* MOD_0F2B_PREFIX_3 */
4641 {"movntsd", { Eq, XM } },
4642 { "(bad)", { XX } },
4643 },
4644 {
4645 /* MOD_0F51 */
4646 { "(bad)", { XX } },
4647 { "movmskpX", { Gdq, XS } },
4648 },
b844680a 4649 {
1ceb70f8 4650 /* MOD_0F71_REG_2 */
b844680a 4651 { "(bad)", { XX } },
4e7d34a6 4652 { "psrlw", { MS, Ib } },
b844680a
L		 4653 },
4654 {
1ceb70f8 4655 /* MOD_0F71_REG_4 */
b844680a 4656 { "(bad)", { XX } },
4e7d34a6 4657 { "psraw", { MS, Ib } },
b844680a
L		 4658 },
4659 {
1ceb70f8 4660 /* MOD_0F71_REG_6 */
b844680a 4661 { "(bad)", { XX } },
4e7d34a6 4662 { "psllw", { MS, Ib } },
b844680a
L		 4663 },
4664 {
1ceb70f8 4665 /* MOD_0F72_REG_2 */
b844680a 4666 { "(bad)", { XX } },
4e7d34a6 4667 { "psrld", { MS, Ib } },
b844680a
L		 4668 },
4669 {
1ceb70f8 4670 /* MOD_0F72_REG_4 */
b844680a 4671 { "(bad)", { XX } },
4e7d34a6 4672 { "psrad", { MS, Ib } },
b844680a
L		 4673 },
4674 {
1ceb70f8 4675 /* MOD_0F72_REG_6 */
b844680a 4676 { "(bad)", { XX } },
4e7d34a6 4677 { "pslld", { MS, Ib } },
b844680a
L		 4678 },
4679 {
1ceb70f8 4680 /* MOD_0F73_REG_2 */
4e7d34a6
L		 4681 { "(bad)", { XX } },
4682 { "psrlq", { MS, Ib } },
b844680a
L		 4683 },
4684 {
1ceb70f8 4685 /* MOD_0F73_REG_3 */
b844680a 4686 { "(bad)", { XX } },
1ceb70f8 4687 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
b844680a
L		 4688 },
4689 {
1ceb70f8 4690 /* MOD_0F73_REG_6 */
b844680a 4691 { "(bad)", { XX } },
4e7d34a6 4692 { "psllq", { MS, Ib } },
b844680a
L		 4693 },
4694 {
1ceb70f8 4695 /* MOD_0F73_REG_7 */
b844680a 4696 { "(bad)", { XX } },
1ceb70f8 4697 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
b844680a
L		 4698 },
4699 {
1ceb70f8 4700 /* MOD_0FAE_REG_0 */
4e7d34a6 4701 { "fxsave", { M } },
b844680a
L		 4702 { "(bad)", { XX } },
4703 },
d8faab4e 4704 {
1ceb70f8 4705 /* MOD_0FAE_REG_1 */
4e7d34a6 4706 { "fxrstor", { M } },
d8faab4e
L		 4707 { "(bad)", { XX } },
4708 },
4709 {
1ceb70f8 4710 /* MOD_0FAE_REG_2 */
4e7d34a6 4711 { "ldmxcsr", { Md } },
d8faab4e
L		 4712 { "(bad)", { XX } },
4713 },
876d4bfa 4714 {
1ceb70f8 4715 /* MOD_0FAE_REG_3 */
4e7d34a6 4716 { "stmxcsr", { Md } },
876d4bfa
L		 4717 { "(bad)", { XX } },
4718 },
4719 {
1ceb70f8 4720 /* MOD_0FAE_REG_5 */
876d4bfa 4721 { "(bad)", { XX } },
1ceb70f8 4722 { RM_TABLE (RM_0FAE_REG_5) },
876d4bfa
L		 4723 },
4724 {
1ceb70f8 4725 /* MOD_0FAE_REG_6 */
4e7d34a6 4726 { "(bad)", { XX } },
1ceb70f8 4727 { RM_TABLE (RM_0FAE_REG_6) },
876d4bfa
L		 4728 },
4729 {
1ceb70f8 4730 /* MOD_0FAE_REG_7 */
4e7d34a6 4731 { "clflush", { Mb } },
1ceb70f8 4732 { RM_TABLE (RM_0FAE_REG_7) },
876d4bfa 4733 },
bbedc832 4734 {
92fddf8e
L		 4735 /* MOD_0FB2 */
4736 { "lssS", { Gv, Mp } },
4e7d34a6 4737 { "(bad)", { XX } },
bbedc832 4738 },
144c41d9 4739 {
92fddf8e
L		 4740 /* MOD_0FB4 */
4741 { "lfsS", { Gv, Mp } },
4e7d34a6 4742 { "(bad)", { XX } },
144c41d9 4743 },
1afd85e3 4744 {
92fddf8e
L		 4745 /* MOD_0FB5 */
4746 { "lgsS", { Gv, Mp } },
4747 { "(bad)", { XX } },
1afd85e3
L		 4748 },
4749 {
92fddf8e
L		 4750 /* MOD_0FC7_REG_6 */
4751 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
4752 { "(bad)", { XX } },
4753 },
4754 {
4755 /* MOD_0FC7_REG_7 */
4756 { "vmptrst", { Mq } },
4757 { "(bad)", { XX } },
1afd85e3 4758 },
75c135a8
L		 4759 {
4760 /* MOD_0FD7 */
4761 { "(bad)", { XX } },
4762 { "pmovmskb", { Gdq, MS } },
4763 },
4764 {
4765 /* MOD_0FE7_PREFIX_2 */
4766 { "movntdq", { EM, XM } },
4767 { "(bad)", { XX } },
4768 },
1afd85e3 4769 {
1ceb70f8 4770 /* MOD_0FF0_PREFIX_3 */
4e7d34a6 4771 { "lddqu", { XM, M } },
1afd85e3 4772 { "(bad)", { XX } },
1afd85e3 4773 },
75c135a8
L		 4774 {
4775 /* MOD_0F382A_PREFIX_2 */
4776 { "movntdqa", { XM, EM } },
4777 { "(bad)", { XX } },
4778 },
1afd85e3 4779 {
1ceb70f8 4780 /* MOD_62_32BIT */
4e7d34a6 4781 { "bound{S|}", { Gv, Ma } },
1afd85e3 4782 { "(bad)", { XX } },
1afd85e3
L		 4783 },
4784 {
1ceb70f8 4785 /* MOD_C4_32BIT */
4e7d34a6
L		 4786 { "lesS", { Gv, Mp } },
4787 { "(bad)", { XX } },
1afd85e3
L		 4788 },
4789 {
1ceb70f8 4790 /* MOD_C5_32BIT */
4e7d34a6 4791 { "ldsS", { Gv, Mp } },
1afd85e3 4792 { "(bad)", { XX } },
1afd85e3 4793 },
b844680a
L		 4794};
4795
1ceb70f8 4796static const struct dis386 rm_table[][8] = {
b844680a 4797 {
1ceb70f8 4798 /* RM_0F01_REG_0 */
b844680a
L		 4799 { "(bad)", { XX } },
4800 { "vmcall", { Skip_MODRM } },
4801 { "vmlaunch", { Skip_MODRM } },
4802 { "vmresume", { Skip_MODRM } },
4803 { "vmxoff", { Skip_MODRM } },
4804 { "(bad)", { XX } },
4805 { "(bad)", { XX } },
4806 { "(bad)", { XX } },
4807 },
4808 {
1ceb70f8 4809 /* RM_0F01_REG_1 */
b844680a
L		 4810 { "monitor", { { OP_Monitor, 0 } } },
4811 { "mwait", { { OP_Mwait, 0 } } },
4812 { "(bad)", { XX } },
4813 { "(bad)", { XX } },
4814 { "(bad)", { XX } },
4815 { "(bad)", { XX } },
4816 { "(bad)", { XX } },
4817 { "(bad)", { XX } },
4818 },
4819 {
1ceb70f8 4820 /* RM_0F01_REG_3 */
4e7d34a6
L		 4821 { "vmrun", { Skip_MODRM } },
4822 { "vmmcall", { Skip_MODRM } },
4823 { "vmload", { Skip_MODRM } },
4824 { "vmsave", { Skip_MODRM } },
4825 { "stgi", { Skip_MODRM } },
4826 { "clgi", { Skip_MODRM } },
4827 { "skinit", { Skip_MODRM } },
4828 { "invlpga", { Skip_MODRM } },
4829 },
4830 {
1ceb70f8 4831 /* RM_0F01_REG_7 */
4e7d34a6
L		 4832 { "swapgs", { Skip_MODRM } },
4833 { "rdtscp", { Skip_MODRM } },
b844680a
L		 4834 { "(bad)", { XX } },
4835 { "(bad)", { XX } },
4836 { "(bad)", { XX } },
4837 { "(bad)", { XX } },
4838 { "(bad)", { XX } },
4839 { "(bad)", { XX } },
4840 },
4841 {
1ceb70f8 4842 /* RM_0FAE_REG_5 */
4e7d34a6 4843 { "lfence", { Skip_MODRM } },
b844680a
L		 4844 { "(bad)", { XX } },
4845 { "(bad)", { XX } },
4846 { "(bad)", { XX } },
4847 { "(bad)", { XX } },
4848 { "(bad)", { XX } },
4849 { "(bad)", { XX } },
4850 { "(bad)", { XX } },
4851 },
4852 {
1ceb70f8 4853 /* RM_0FAE_REG_6 */
4e7d34a6 4854 { "mfence", { Skip_MODRM } },
b844680a
L		 4855 { "(bad)", { XX } },
4856 { "(bad)", { XX } },
4857 { "(bad)", { XX } },
4858 { "(bad)", { XX } },
4859 { "(bad)", { XX } },
4860 { "(bad)", { XX } },
4861 { "(bad)", { XX } },
4862 },
bbedc832 4863 {
1ceb70f8 4864 /* RM_0FAE_REG_7 */
4e7d34a6
L		 4865 { "sfence", { Skip_MODRM } },
4866 { "(bad)", { XX } },
bbedc832
L		 4867 { "(bad)", { XX } },
4868 { "(bad)", { XX } },
4869 { "(bad)", { XX } },
4870 { "(bad)", { XX } },
4871 { "(bad)", { XX } },
4872 { "(bad)", { XX } },
144c41d9 4873 },
b844680a
L		 4874};
4875
c608c12e
AM		 4876#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
4877
252b5132 4878static void
26ca5450 4879ckprefix (void)
252b5132 4880{
52b15da3
JH		 4881 int newrex;
4882 rex = 0;
252b5132 4883 prefixes = 0;
7d421014 4884 used_prefixes = 0;
52b15da3 4885 rex_used = 0;
252b5132
RH		 4886 while (1)
4887 {
4888 FETCH_DATA (the_info, codep + 1);
52b15da3 4889 newrex = 0;
252b5132
RH		 4890 switch (*codep)
4891 {
52b15da3
JH		 4892 /* REX prefixes family. */
4893 case 0x40:
4894 case 0x41:
4895 case 0x42:
4896 case 0x43:
4897 case 0x44:
4898 case 0x45:
4899 case 0x46:
4900 case 0x47:
4901 case 0x48:
4902 case 0x49:
4903 case 0x4a:
4904 case 0x4b:
4905 case 0x4c:
4906 case 0x4d:
4907 case 0x4e:
4908 case 0x4f:
cb712a9e 4909 if (address_mode == mode_64bit)
52b15da3
JH		 4910 newrex = *codep;
4911 else
4912 return;
4913 break;
252b5132
RH		 4914 case 0xf3:
4915 prefixes |= PREFIX_REPZ;
4916 break;
4917 case 0xf2:
4918 prefixes |= PREFIX_REPNZ;
4919 break;
4920 case 0xf0:
4921 prefixes |= PREFIX_LOCK;
4922 break;
4923 case 0x2e:
4924 prefixes |= PREFIX_CS;
4925 break;
4926 case 0x36:
4927 prefixes |= PREFIX_SS;
4928 break;
4929 case 0x3e:
4930 prefixes |= PREFIX_DS;
4931 break;
4932 case 0x26:
4933 prefixes |= PREFIX_ES;
4934 break;
4935 case 0x64:
4936 prefixes |= PREFIX_FS;
4937 break;
4938 case 0x65:
4939 prefixes |= PREFIX_GS;
4940 break;
4941 case 0x66:
4942 prefixes |= PREFIX_DATA;
4943 break;
4944 case 0x67:
4945 prefixes |= PREFIX_ADDR;
4946 break;
5076851f 4947 case FWAIT_OPCODE:
252b5132
RH		 4948 /* fwait is really an instruction. If there are prefixes
4949 before the fwait, they belong to the fwait, *not* to the
4950 following instruction. */
3e7d61b2 4951 if (prefixes || rex)
252b5132
RH		 4952 {
4953 prefixes |= PREFIX_FWAIT;
4954 codep++;
4955 return;
4956 }
4957 prefixes = PREFIX_FWAIT;
4958 break;
4959 default:
4960 return;
4961 }
52b15da3
JH		 4962 /* Rex is ignored when followed by another prefix. */
4963 if (rex)
4964 {
3e7d61b2
AM		 4965 rex_used = rex;
4966 return;
52b15da3
JH		 4967 }
4968 rex = newrex;
252b5132
RH		 4969 codep++;
4970 }
4971}
4972
7d421014
ILT		 4973/* Return the name of the prefix byte PREF, or NULL if PREF is not a
4974 prefix byte. */
4975
4976static const char *
26ca5450 4977prefix_name (int pref, int sizeflag)
7d421014 4978{
0003779b
L		 4979 static const char *rexes [16] =
4980 {
4981 "rex", /* 0x40 */
4982 "rex.B", /* 0x41 */
4983 "rex.X", /* 0x42 */
4984 "rex.XB", /* 0x43 */
4985 "rex.R", /* 0x44 */
4986 "rex.RB", /* 0x45 */
4987 "rex.RX", /* 0x46 */
4988 "rex.RXB", /* 0x47 */
4989 "rex.W", /* 0x48 */
4990 "rex.WB", /* 0x49 */
4991 "rex.WX", /* 0x4a */
4992 "rex.WXB", /* 0x4b */
4993 "rex.WR", /* 0x4c */
4994 "rex.WRB", /* 0x4d */
4995 "rex.WRX", /* 0x4e */
4996 "rex.WRXB", /* 0x4f */
4997 };
4998
7d421014
ILT		 4999 switch (pref)
5000 {
52b15da3
JH		 5001 /* REX prefixes family. */
5002 case 0x40:
52b15da3 5003 case 0x41:
52b15da3 5004 case 0x42:
52b15da3 5005 case 0x43:
52b15da3 5006 case 0x44:
52b15da3 5007 case 0x45:
52b15da3 5008 case 0x46:
52b15da3 5009 case 0x47:
52b15da3 5010 case 0x48:
52b15da3 5011 case 0x49:
52b15da3 5012 case 0x4a:
52b15da3 5013 case 0x4b:
52b15da3 5014 case 0x4c:
52b15da3 5015 case 0x4d:
52b15da3 5016 case 0x4e:
52b15da3 5017 case 0x4f:
0003779b 5018 return rexes [pref - 0x40];
7d421014
ILT		 5019 case 0xf3:
5020 return "repz";
5021 case 0xf2:
5022 return "repnz";
5023 case 0xf0:
5024 return "lock";
5025 case 0x2e:
5026 return "cs";
5027 case 0x36:
5028 return "ss";
5029 case 0x3e:
5030 return "ds";
5031 case 0x26:
5032 return "es";
5033 case 0x64:
5034 return "fs";
5035 case 0x65:
5036 return "gs";
5037 case 0x66:
5038 return (sizeflag & DFLAG) ? "data16" : "data32";
5039 case 0x67:
cb712a9e 5040 if (address_mode == mode_64bit)
db6eb5be 5041 return (sizeflag & AFLAG) ? "addr32" : "addr64";
c1a64871 5042 else
2888cb7a 5043 return (sizeflag & AFLAG) ? "addr16" : "addr32";
7d421014
ILT		 5044 case FWAIT_OPCODE:
5045 return "fwait";
5046 default:
5047 return NULL;
5048 }
5049}
5050
ce518a5f
L		 5051static char op_out[MAX_OPERANDS][100];
5052static int op_ad, op_index[MAX_OPERANDS];
1d9f512f 5053static int two_source_ops;
ce518a5f
L		 5054static bfd_vma op_address[MAX_OPERANDS];
5055static bfd_vma op_riprel[MAX_OPERANDS];
52b15da3 5056static bfd_vma start_pc;
ce518a5f 5057
252b5132
RH		 5058/*
5059 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
5060 * (see topic "Redundant prefixes" in the "Differences from 8086"
5061 * section of the "Virtual 8086 Mode" chapter.)
5062 * 'pc' should be the address of this instruction, it will
5063 * be used to print the target address if this is a relative jump or call
5064 * The function returns the length of this instruction in bytes.
5065 */
5066
252b5132 5067static char intel_syntax;
9d141669 5068static char intel_mnemonic = !SYSV386_COMPAT;
252b5132
RH		 5069static char open_char;
5070static char close_char;
5071static char separator_char;
5072static char scale_char;
5073
e396998b
AM		 5074/* Here for backwards compatibility. When gdb stops using
5075 print_insn_i386_att and print_insn_i386_intel these functions can
5076 disappear, and print_insn_i386 be merged into print_insn. */
252b5132 5077int
26ca5450 5078print_insn_i386_att (bfd_vma pc, disassemble_info *info)
252b5132
RH		 5079{
5080 intel_syntax = 0;
e396998b
AM		 5081
5082 return print_insn (pc, info);
252b5132
RH		 5083}
5084
5085int
26ca5450 5086print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
252b5132
RH		 5087{
5088 intel_syntax = 1;
e396998b
AM		 5089
5090 return print_insn (pc, info);
252b5132
RH		 5091}
5092
e396998b 5093int
26ca5450 5094print_insn_i386 (bfd_vma pc, disassemble_info *info)
e396998b
AM		 5095{
5096 intel_syntax = -1;
5097
5098 return print_insn (pc, info);
5099}
5100
f59a29b9
L		 5101void
5102print_i386_disassembler_options (FILE *stream)
5103{
5104 fprintf (stream, _("\n\
5105The following i386/x86-64 specific disassembler options are supported for use\n\
5106with the -M switch (multiple options should be separated by commas):\n"));
5107
5108 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
5109 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
5110 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
5111 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
5112 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
9d141669
L		 5113 fprintf (stream, _(" att-mnemonic\n"
5114 " Display instruction in AT&T mnemonic\n"));
5115 fprintf (stream, _(" intel-mnemonic\n"
5116 " Display instruction in Intel mnemonic\n"));
f59a29b9
L		 5117 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
5118 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
5119 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
5120 fprintf (stream, _(" data32 Assume 32bit data size\n"));
5121 fprintf (stream, _(" data16 Assume 16bit data size\n"));
5122 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
5123}
5124
b844680a
L		 5125/* Get a pointer to struct dis386 with a valid name. */
5126
5127static const struct dis386 *
8bb15339 5128get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
b844680a
L		 5129{
5130 int index;
5131
5132 if (dp->name != NULL)
5133 return dp;
5134
5135 switch (dp->op[0].bytemode)
5136 {
1ceb70f8
L		 5137 case USE_REG_TABLE:
5138 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
5139 break;
5140
5141 case USE_MOD_TABLE:
5142 index = modrm.mod == 0x3 ? 1 : 0;
5143 dp = &mod_table[dp->op[1].bytemode][index];
5144 break;
5145
5146 case USE_RM_TABLE:
5147 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
b844680a
L		 5148 break;
5149
4e7d34a6 5150 case USE_PREFIX_TABLE:
b844680a
L		 5151 index = 0;
5152 used_prefixes |= (prefixes & PREFIX_REPZ);
5153 if (prefixes & PREFIX_REPZ)
5154 {
5155 index = 1;
5156 repz_prefix = NULL;
5157 }
5158 else
5159 {
5160 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
5161 PREFIX_DATA. */
5162 used_prefixes |= (prefixes & PREFIX_REPNZ);
5163 if (prefixes & PREFIX_REPNZ)
5164 {
5165 index = 3;
5166 repnz_prefix = NULL;
5167 }
5168 else
5169 {
5170 used_prefixes |= (prefixes & PREFIX_DATA);
5171 if (prefixes & PREFIX_DATA)
5172 {
5173 index = 2;
5174 data_prefix = NULL;
5175 }
5176 }
5177 }
1ceb70f8 5178 dp = &prefix_table[dp->op[1].bytemode][index];
b844680a
L		 5179 break;
5180
4e7d34a6 5181 case USE_X86_64_TABLE:
b844680a
L		 5182 index = address_mode == mode_64bit ? 1 : 0;
5183 dp = &x86_64_table[dp->op[1].bytemode][index];
5184 break;
5185
4e7d34a6 5186 case USE_3BYTE_TABLE:
8bb15339
L		 5187 FETCH_DATA (info, codep + 2);
5188 index = *codep++;
5189 dp = &three_byte_table[dp->op[1].bytemode][index];
5190 modrm.mod = (*codep >> 6) & 3;
5191 modrm.reg = (*codep >> 3) & 7;
5192 modrm.rm = *codep & 7;
5193 break;
5194
b844680a
L		 5195 default:
5196 oappend (INTERNAL_DISASSEMBLER_ERROR);
5197 return NULL;
5198 }
5199
5200 if (dp->name != NULL)
5201 return dp;
5202 else
8bb15339 5203 return get_valid_dis386 (dp, info);
b844680a
L		 5204}
5205
e396998b 5206static int
26ca5450 5207print_insn (bfd_vma pc, disassemble_info *info)
252b5132 5208{
2da11e11 5209 const struct dis386 *dp;
252b5132 5210 int i;
ce518a5f 5211 char *op_txt[MAX_OPERANDS];
252b5132 5212 int needcomma;
e396998b
AM		 5213 int sizeflag;
5214 const char *p;
252b5132 5215 struct dis_private priv;
eec0f4ca 5216 unsigned char op;
b844680a
L		 5217 char prefix_obuf[32];
5218 char *prefix_obufp;
252b5132 5219
cb712a9e
L		 5220 if (info->mach == bfd_mach_x86_64_intel_syntax
5221 || info->mach == bfd_mach_x86_64)
5222 address_mode = mode_64bit;
5223 else
5224 address_mode = mode_32bit;
52b15da3 5225
8373f971 5226 if (intel_syntax == (char) -1)
e396998b
AM		 5227 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
5228 || info->mach == bfd_mach_x86_64_intel_syntax);
5229
2da11e11 5230 if (info->mach == bfd_mach_i386_i386
52b15da3
JH		 5231 || info->mach == bfd_mach_x86_64
5232 || info->mach == bfd_mach_i386_i386_intel_syntax
5233 || info->mach == bfd_mach_x86_64_intel_syntax)
e396998b 5234 priv.orig_sizeflag = AFLAG | DFLAG;
2da11e11 5235 else if (info->mach == bfd_mach_i386_i8086)
e396998b 5236 priv.orig_sizeflag = 0;
2da11e11
AM		 5237 else
5238 abort ();
e396998b
AM		 5239
5240 for (p = info->disassembler_options; p != NULL; )
5241 {
0112cd26 5242 if (CONST_STRNEQ (p, "x86-64"))
e396998b 5243 {
cb712a9e 5244 address_mode = mode_64bit;
e396998b
AM		 5245 priv.orig_sizeflag = AFLAG | DFLAG;
5246 }
0112cd26 5247 else if (CONST_STRNEQ (p, "i386"))
e396998b 5248 {
cb712a9e 5249 address_mode = mode_32bit;
e396998b
AM		 5250 priv.orig_sizeflag = AFLAG | DFLAG;
5251 }
0112cd26 5252 else if (CONST_STRNEQ (p, "i8086"))
e396998b 5253 {
cb712a9e 5254 address_mode = mode_16bit;
e396998b
AM		 5255 priv.orig_sizeflag = 0;
5256 }
0112cd26 5257 else if (CONST_STRNEQ (p, "intel"))
e396998b
AM		 5258 {
5259 intel_syntax = 1;
9d141669
L		 5260 if (CONST_STRNEQ (p + 5, "-mnemonic"))
5261 intel_mnemonic = 1;
e396998b 5262 }
0112cd26 5263 else if (CONST_STRNEQ (p, "att"))
e396998b
AM		 5264 {
5265 intel_syntax = 0;
9d141669
L		 5266 if (CONST_STRNEQ (p + 3, "-mnemonic"))
5267 intel_mnemonic = 0;
e396998b 5268 }
0112cd26 5269 else if (CONST_STRNEQ (p, "addr"))
e396998b 5270 {
f59a29b9
L		 5271 if (address_mode == mode_64bit)
5272 {
5273 if (p[4] == '3' && p[5] == '2')
5274 priv.orig_sizeflag &= ~AFLAG;
5275 else if (p[4] == '6' && p[5] == '4')
5276 priv.orig_sizeflag |= AFLAG;
5277 }
5278 else
5279 {
5280 if (p[4] == '1' && p[5] == '6')
5281 priv.orig_sizeflag &= ~AFLAG;
5282 else if (p[4] == '3' && p[5] == '2')
5283 priv.orig_sizeflag |= AFLAG;
5284 }
e396998b 5285 }
0112cd26 5286 else if (CONST_STRNEQ (p, "data"))
e396998b
AM		 5287 {
5288 if (p[4] == '1' && p[5] == '6')
5289 priv.orig_sizeflag &= ~DFLAG;
5290 else if (p[4] == '3' && p[5] == '2')
5291 priv.orig_sizeflag |= DFLAG;
5292 }
0112cd26 5293 else if (CONST_STRNEQ (p, "suffix"))
e396998b
AM		 5294 priv.orig_sizeflag |= SUFFIX_ALWAYS;
5295
5296 p = strchr (p, ',');
5297 if (p != NULL)
5298 p++;
5299 }
5300
5301 if (intel_syntax)
5302 {
5303 names64 = intel_names64;
5304 names32 = intel_names32;
5305 names16 = intel_names16;
5306 names8 = intel_names8;
5307 names8rex = intel_names8rex;
5308 names_seg = intel_names_seg;
db51cc60
L		 5309 index64 = intel_index64;
5310 index32 = intel_index32;
e396998b
AM		 5311 index16 = intel_index16;
5312 open_char = '[';
5313 close_char = ']';
5314 separator_char = '+';
5315 scale_char = '*';
5316 }
5317 else
5318 {
5319 names64 = att_names64;
5320 names32 = att_names32;
5321 names16 = att_names16;
5322 names8 = att_names8;
5323 names8rex = att_names8rex;
5324 names_seg = att_names_seg;
db51cc60
L		 5325 index64 = att_index64;
5326 index32 = att_index32;
e396998b
AM		 5327 index16 = att_index16;
5328 open_char = '(';
5329 close_char = ')';
5330 separator_char = ',';
5331 scale_char = ',';
5332 }
2da11e11 5333
4fe53c98 5334 /* The output looks better if we put 7 bytes on a line, since that
c608c12e 5335 puts most long word instructions on a single line. */
4fe53c98 5336 info->bytes_per_line = 7;
252b5132 5337
26ca5450 5338 info->private_data = &priv;
252b5132
RH		 5339 priv.max_fetched = priv.the_buffer;
5340 priv.insn_start = pc;
252b5132
RH		 5341
5342 obuf[0] = 0;
ce518a5f
L		 5343 for (i = 0; i < MAX_OPERANDS; ++i)
5344 {
5345 op_out[i][0] = 0;
5346 op_index[i] = -1;
5347 }
252b5132
RH		 5348
5349 the_info = info;
5350 start_pc = pc;
e396998b
AM		 5351 start_codep = priv.the_buffer;
5352 codep = priv.the_buffer;
252b5132 5353
5076851f
ILT		 5354 if (setjmp (priv.bailout) != 0)
5355 {
7d421014
ILT		 5356 const char *name;
5357
5076851f 5358 /* Getting here means we tried for data but didn't get it. That
e396998b
AM		 5359 means we have an incomplete instruction of some sort. Just
5360 print the first byte as a prefix or a .byte pseudo-op. */
5361 if (codep > priv.the_buffer)
5076851f 5362 {
e396998b 5363 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 5364 if (name != NULL)
5365 (*info->fprintf_func) (info->stream, "%s", name);
5366 else
5076851f 5367 {
7d421014
ILT		 5368 /* Just print the first byte as a .byte instruction. */
5369 (*info->fprintf_func) (info->stream, ".byte 0x%x",
e396998b 5370 (unsigned int) priv.the_buffer[0]);
5076851f 5371 }
5076851f 5372
7d421014 5373 return 1;
5076851f
ILT		 5374 }
5375
5376 return -1;
5377 }
5378
52b15da3 5379 obufp = obuf;
252b5132
RH		 5380 ckprefix ();
5381
5382 insn_codep = codep;
e396998b 5383 sizeflag = priv.orig_sizeflag;
252b5132
RH		 5384
5385 FETCH_DATA (info, codep + 1);
5386 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
5387
3e7d61b2
AM		 5388 if (((prefixes & PREFIX_FWAIT)
5389 && ((*codep < 0xd8) || (*codep > 0xdf)))
5390 || (rex && rex_used))
252b5132 5391 {
7d421014
ILT		 5392 const char *name;
5393
3e7d61b2
AM		 5394 /* fwait not followed by floating point instruction, or rex followed
5395 by other prefixes. Print the first prefix. */
e396998b 5396 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 5397 if (name == NULL)
5398 name = INTERNAL_DISASSEMBLER_ERROR;
5399 (*info->fprintf_func) (info->stream, "%s", name);
5400 return 1;
252b5132
RH		 5401 }
5402
eec0f4ca 5403 op = 0;
252b5132
RH		 5404 if (*codep == 0x0f)
5405 {
eec0f4ca 5406 unsigned char threebyte;
252b5132 5407 FETCH_DATA (info, codep + 2);
eec0f4ca
L		 5408 threebyte = *++codep;
5409 dp = &dis386_twobyte[threebyte];
252b5132 5410 need_modrm = twobyte_has_modrm[*codep];
eec0f4ca 5411 codep++;
252b5132
RH		 5412 }
5413 else
5414 {
6439fc28 5415 dp = &dis386[*codep];
252b5132 5416 need_modrm = onebyte_has_modrm[*codep];
eec0f4ca 5417 codep++;
252b5132 5418 }
246c51aa 5419
b844680a 5420 if ((prefixes & PREFIX_REPZ))
7d421014 5421 {
b844680a 5422 repz_prefix = "repz ";
7d421014
ILT		 5423 used_prefixes |= PREFIX_REPZ;
5424 }
b844680a
L		 5425 else
5426 repz_prefix = NULL;
5427
5428 if ((prefixes & PREFIX_REPNZ))
7d421014 5429 {
b844680a 5430 repnz_prefix = "repnz ";
7d421014
ILT		 5431 used_prefixes |= PREFIX_REPNZ;
5432 }
b844680a
L		 5433 else
5434 repnz_prefix = NULL;
050dfa73 5435
b844680a 5436 if ((prefixes & PREFIX_LOCK))
7d421014 5437 {
b844680a 5438 lock_prefix = "lock ";
7d421014
ILT		 5439 used_prefixes |= PREFIX_LOCK;
5440 }
b844680a
L		 5441 else
5442 lock_prefix = NULL;
c608c12e 5443
b844680a 5444 addr_prefix = NULL;
c608c12e
AM		 5445 if (prefixes & PREFIX_ADDR)
5446 {
5447 sizeflag ^= AFLAG;
ce518a5f 5448 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
3ffd33cf 5449 {
cb712a9e 5450 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
b844680a 5451 addr_prefix = "addr32 ";
3ffd33cf 5452 else
b844680a 5453 addr_prefix = "addr16 ";
3ffd33cf
AM		 5454 used_prefixes |= PREFIX_ADDR;
5455 }
5456 }
5457
b844680a
L		 5458 data_prefix = NULL;
5459 if ((prefixes & PREFIX_DATA))
3ffd33cf
AM		 5460 {
5461 sizeflag ^= DFLAG;
ce518a5f
L		 5462 if (dp->op[2].bytemode == cond_jump_mode
5463 && dp->op[0].bytemode == v_mode
6439fc28 5464 && !intel_syntax)
3ffd33cf
AM		 5465 {
5466 if (sizeflag & DFLAG)
b844680a 5467 data_prefix = "data32 ";
3ffd33cf 5468 else
b844680a 5469 data_prefix = "data16 ";
3ffd33cf
AM		 5470 used_prefixes |= PREFIX_DATA;
5471 }
5472 }
5473
8bb15339 5474 if (need_modrm)
252b5132
RH		 5475 {
5476 FETCH_DATA (info, codep + 1);
7967e09e
L		 5477 modrm.mod = (*codep >> 6) & 3;
5478 modrm.reg = (*codep >> 3) & 7;
5479 modrm.rm = *codep & 7;
252b5132
RH		 5480 }
5481
ce518a5f 5482 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
252b5132
RH		 5483 {
5484 dofloat (sizeflag);
5485 }
5486 else
5487 {
8bb15339 5488 dp = get_valid_dis386 (dp, info);
b844680a 5489 if (dp != NULL && putop (dp->name, sizeflag) == 0)
ce518a5f
L		 5490 {
5491 for (i = 0; i < MAX_OPERANDS; ++i)
5492 {
246c51aa 5493 obufp = op_out[i];
ce518a5f
L		 5494 op_ad = MAX_OPERANDS - 1 - i;
5495 if (dp->op[i].rtn)
5496 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
5497 }
6439fc28 5498 }
252b5132
RH		 5499 }
5500
7d421014
ILT		 5501 /* See if any prefixes were not used. If so, print the first one
5502 separately. If we don't do this, we'll wind up printing an
5503 instruction stream which does not precisely correspond to the
5504 bytes we are disassembling. */
5505 if ((prefixes & ~used_prefixes) != 0)
5506 {
5507 const char *name;
5508
e396998b 5509 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 5510 if (name == NULL)
5511 name = INTERNAL_DISASSEMBLER_ERROR;
5512 (*info->fprintf_func) (info->stream, "%s", name);
5513 return 1;
5514 }
52b15da3
JH		 5515 if (rex & ~rex_used)
5516 {
5517 const char *name;
e396998b 5518 name = prefix_name (rex | 0x40, priv.orig_sizeflag);
52b15da3
JH		 5519 if (name == NULL)
5520 name = INTERNAL_DISASSEMBLER_ERROR;
5521 (*info->fprintf_func) (info->stream, "%s ", name);
5522 }
7d421014 5523
b844680a
L		 5524 prefix_obuf[0] = 0;
5525 prefix_obufp = prefix_obuf;
5526 if (lock_prefix)
5527 prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
5528 if (repz_prefix)
5529 prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
5530 if (repnz_prefix)
5531 prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
5532 if (addr_prefix)
5533 prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
5534 if (data_prefix)
5535 prefix_obufp = stpcpy (prefix_obufp, data_prefix);
5536
5537 if (prefix_obuf[0] != 0)
5538 (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
5539
252b5132 5540 obufp = obuf + strlen (obuf);
b844680a 5541 for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
252b5132
RH		 5542 oappend (" ");
5543 oappend (" ");
5544 (*info->fprintf_func) (info->stream, "%s", obuf);
5545
5546 /* The enter and bound instructions are printed with operands in the same
5547 order as the intel book; everything else is printed in reverse order. */
2da11e11 5548 if (intel_syntax || two_source_ops)
252b5132 5549 {
185b1163
L		 5550 bfd_vma riprel;
5551
ce518a5f
L		 5552 for (i = 0; i < MAX_OPERANDS; ++i)
5553 op_txt[i] = op_out[i];
246c51aa 5554
ce518a5f
L		 5555 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
5556 {
5557 op_ad = op_index[i];
5558 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
5559 op_index[MAX_OPERANDS - 1 - i] = op_ad;
185b1163
L		 5560 riprel = op_riprel[i];
5561 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
5562 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
ce518a5f 5563 }
252b5132
RH		 5564 }
5565 else
5566 {
ce518a5f
L		 5567 for (i = 0; i < MAX_OPERANDS; ++i)
5568 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
050dfa73
MM		 5569 }
5570
ce518a5f
L		 5571 needcomma = 0;
5572 for (i = 0; i < MAX_OPERANDS; ++i)
5573 if (*op_txt[i])
5574 {
5575 if (needcomma)
5576 (*info->fprintf_func) (info->stream, ",");
5577 if (op_index[i] != -1 && !op_riprel[i])
5578 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
5579 else
5580 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
5581 needcomma = 1;
5582 }
050dfa73 5583
ce518a5f 5584 for (i = 0; i < MAX_OPERANDS; i++)
52b15da3
JH		 5585 if (op_index[i] != -1 && op_riprel[i])
5586 {
5587 (*info->fprintf_func) (info->stream, " # ");
5588 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
5589 + op_address[op_index[i]]), info);
185b1163 5590 break;
52b15da3 5591 }
e396998b 5592 return codep - priv.the_buffer;
252b5132
RH		 5593}
5594
6439fc28 5595static const char *float_mem[] = {
252b5132 5596 /* d8 */
7c52e0e8
L		 5597 "fadd{s|}",
5598 "fmul{s|}",
5599 "fcom{s|}",
5600 "fcomp{s|}",
5601 "fsub{s|}",
5602 "fsubr{s|}",
5603 "fdiv{s|}",
5604 "fdivr{s|}",
db6eb5be 5605 /* d9 */
7c52e0e8 5606 "fld{s|}",
252b5132 5607 "(bad)",
7c52e0e8
L		 5608 "fst{s|}",
5609 "fstp{s|}",
9306ca4a 5610 "fldenvIC",
252b5132 5611 "fldcw",
9306ca4a 5612 "fNstenvIC",
252b5132
RH		 5613 "fNstcw",
5614 /* da */
7c52e0e8
L		 5615 "fiadd{l|}",
5616 "fimul{l|}",
5617 "ficom{l|}",
5618 "ficomp{l|}",
5619 "fisub{l|}",
5620 "fisubr{l|}",
5621 "fidiv{l|}",
5622 "fidivr{l|}",
252b5132 5623 /* db */
7c52e0e8
L		 5624 "fild{l|}",
5625 "fisttp{l|}",
5626 "fist{l|}",
5627 "fistp{l|}",
252b5132 5628 "(bad)",
6439fc28 5629 "fld{t||t|}",
252b5132 5630 "(bad)",
6439fc28 5631 "fstp{t||t|}",
252b5132 5632 /* dc */
7c52e0e8
L		 5633 "fadd{l|}",
5634 "fmul{l|}",
5635 "fcom{l|}",
5636 "fcomp{l|}",
5637 "fsub{l|}",
5638 "fsubr{l|}",
5639 "fdiv{l|}",
5640 "fdivr{l|}",
252b5132 5641 /* dd */
7c52e0e8
L		 5642 "fld{l|}",
5643 "fisttp{ll|}",
5644 "fst{l||}",
5645 "fstp{l|}",
9306ca4a 5646 "frstorIC",
252b5132 5647 "(bad)",
9306ca4a 5648 "fNsaveIC",
252b5132
RH		 5649 "fNstsw",
5650 /* de */
5651 "fiadd",
5652 "fimul",
5653 "ficom",
5654 "ficomp",
5655 "fisub",
5656 "fisubr",
5657 "fidiv",
5658 "fidivr",
5659 /* df */
5660 "fild",
ca164297 5661 "fisttp",
252b5132
RH		 5662 "fist",
5663 "fistp",
5664 "fbld",
7c52e0e8 5665 "fild{ll|}",
252b5132 5666 "fbstp",
7c52e0e8 5667 "fistp{ll|}",
1d9f512f
AM		 5668};
5669
5670static const unsigned char float_mem_mode[] = {
5671 /* d8 */
5672 d_mode,
5673 d_mode,
5674 d_mode,
5675 d_mode,
5676 d_mode,
5677 d_mode,
5678 d_mode,
5679 d_mode,
5680 /* d9 */
5681 d_mode,
5682 0,
5683 d_mode,
5684 d_mode,
5685 0,
5686 w_mode,
5687 0,
5688 w_mode,
5689 /* da */
5690 d_mode,
5691 d_mode,
5692 d_mode,
5693 d_mode,
5694 d_mode,
5695 d_mode,
5696 d_mode,
5697 d_mode,
5698 /* db */
5699 d_mode,
5700 d_mode,
5701 d_mode,
5702 d_mode,
5703 0,
9306ca4a 5704 t_mode,
1d9f512f 5705 0,
9306ca4a 5706 t_mode,
1d9f512f
AM		 5707 /* dc */
5708 q_mode,
5709 q_mode,
5710 q_mode,
5711 q_mode,
5712 q_mode,
5713 q_mode,
5714 q_mode,
5715 q_mode,
5716 /* dd */
5717 q_mode,
5718 q_mode,
5719 q_mode,
5720 q_mode,
5721 0,
5722 0,
5723 0,
5724 w_mode,
5725 /* de */
5726 w_mode,
5727 w_mode,
5728 w_mode,
5729 w_mode,
5730 w_mode,
5731 w_mode,
5732 w_mode,
5733 w_mode,
5734 /* df */
5735 w_mode,
5736 w_mode,
5737 w_mode,
5738 w_mode,
9306ca4a 5739 t_mode,
1d9f512f 5740 q_mode,
9306ca4a 5741 t_mode,
1d9f512f 5742 q_mode
252b5132
RH		 5743};
5744
ce518a5f
L		 5745#define ST { OP_ST, 0 }
5746#define STi { OP_STi, 0 }
252b5132 5747
4efba78c
L		 5748#define FGRPd9_2 NULL, { { NULL, 0 } }
5749#define FGRPd9_4 NULL, { { NULL, 1 } }
5750#define FGRPd9_5 NULL, { { NULL, 2 } }
5751#define FGRPd9_6 NULL, { { NULL, 3 } }
5752#define FGRPd9_7 NULL, { { NULL, 4 } }
5753#define FGRPda_5 NULL, { { NULL, 5 } }
5754#define FGRPdb_4 NULL, { { NULL, 6 } }
5755#define FGRPde_3 NULL, { { NULL, 7 } }
5756#define FGRPdf_4 NULL, { { NULL, 8 } }
252b5132 5757
2da11e11 5758static const struct dis386 float_reg[][8] = {
252b5132
RH		 5759 /* d8 */
5760 {
ce518a5f
L		 5761 { "fadd", { ST, STi } },
5762 { "fmul", { ST, STi } },
5763 { "fcom", { STi } },
5764 { "fcomp", { STi } },
5765 { "fsub", { ST, STi } },
5766 { "fsubr", { ST, STi } },
5767 { "fdiv", { ST, STi } },
5768 { "fdivr", { ST, STi } },
252b5132
RH		 5769 },
5770 /* d9 */
5771 {
ce518a5f
L		 5772 { "fld", { STi } },
5773 { "fxch", { STi } },
252b5132 5774 { FGRPd9_2 },
ce518a5f 5775 { "(bad)", { XX } },
252b5132
RH		 5776 { FGRPd9_4 },
5777 { FGRPd9_5 },
5778 { FGRPd9_6 },
5779 { FGRPd9_7 },
5780 },
5781 /* da */
5782 {
ce518a5f
L		 5783 { "fcmovb", { ST, STi } },
5784 { "fcmove", { ST, STi } },
5785 { "fcmovbe",{ ST, STi } },
5786 { "fcmovu", { ST, STi } },
5787 { "(bad)", { XX } },
252b5132 5788 { FGRPda_5 },
ce518a5f
L		 5789 { "(bad)", { XX } },
5790 { "(bad)", { XX } },
252b5132
RH		 5791 },
5792 /* db */
5793 {
ce518a5f
L		 5794 { "fcmovnb",{ ST, STi } },
5795 { "fcmovne",{ ST, STi } },
5796 { "fcmovnbe",{ ST, STi } },
5797 { "fcmovnu",{ ST, STi } },
252b5132 5798 { FGRPdb_4 },
ce518a5f
L		 5799 { "fucomi", { ST, STi } },
5800 { "fcomi", { ST, STi } },
5801 { "(bad)", { XX } },
252b5132
RH		 5802 },
5803 /* dc */
5804 {
ce518a5f
L		 5805 { "fadd", { STi, ST } },
5806 { "fmul", { STi, ST } },
5807 { "(bad)", { XX } },
5808 { "(bad)", { XX } },
9d141669
L		 5809 { "fsub!M", { STi, ST } },
5810 { "fsubM", { STi, ST } },
5811 { "fdiv!M", { STi, ST } },
5812 { "fdivM", { STi, ST } },
252b5132
RH		 5813 },
5814 /* dd */
5815 {
ce518a5f
L		 5816 { "ffree", { STi } },
5817 { "(bad)", { XX } },
5818 { "fst", { STi } },
5819 { "fstp", { STi } },
5820 { "fucom", { STi } },
5821 { "fucomp", { STi } },
5822 { "(bad)", { XX } },
5823 { "(bad)", { XX } },
252b5132
RH		 5824 },
5825 /* de */
5826 {
ce518a5f
L		 5827 { "faddp", { STi, ST } },
5828 { "fmulp", { STi, ST } },
5829 { "(bad)", { XX } },
252b5132 5830 { FGRPde_3 },
9d141669
L		 5831 { "fsub!Mp", { STi, ST } },
5832 { "fsubMp", { STi, ST } },
5833 { "fdiv!Mp", { STi, ST } },
5834 { "fdivMp", { STi, ST } },
252b5132
RH		 5835 },
5836 /* df */
5837 {
ce518a5f
L		 5838 { "ffreep", { STi } },
5839 { "(bad)", { XX } },
5840 { "(bad)", { XX } },
5841 { "(bad)", { XX } },
252b5132 5842 { FGRPdf_4 },
ce518a5f
L		 5843 { "fucomip", { ST, STi } },
5844 { "fcomip", { ST, STi } },
5845 { "(bad)", { XX } },
252b5132
RH		 5846 },
5847};
5848
252b5132
RH		 5849static char *fgrps[][8] = {
5850 /* d9_2 0 */
5851 {
5852 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5853 },
5854
5855 /* d9_4 1 */
5856 {
5857 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
5858 },
5859
5860 /* d9_5 2 */
5861 {
5862 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
5863 },
5864
5865 /* d9_6 3 */
5866 {
5867 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
5868 },
5869
5870 /* d9_7 4 */
5871 {
5872 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
5873 },
5874
5875 /* da_5 5 */
5876 {
5877 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5878 },
5879
5880 /* db_4 6 */
5881 {
5882 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
5883 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
5884 },
5885
5886 /* de_3 7 */
5887 {
5888 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5889 },
5890
5891 /* df_4 8 */
5892 {
5893 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5894 },
5895};
5896
b844680a
L		 5897static void
5898OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
5899 int sizeflag ATTRIBUTE_UNUSED)
5900{
5901 /* Skip mod/rm byte. */
5902 MODRM_CHECK;
5903 codep++;
5904}
5905
252b5132 5906static void
26ca5450 5907dofloat (int sizeflag)
252b5132 5908{
2da11e11 5909 const struct dis386 *dp;
252b5132
RH		 5910 unsigned char floatop;
5911
5912 floatop = codep[-1];
5913
7967e09e 5914 if (modrm.mod != 3)
252b5132 5915 {
7967e09e 5916 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
1d9f512f
AM		 5917
5918 putop (float_mem[fp_indx], sizeflag);
ce518a5f 5919 obufp = op_out[0];
6e50d963 5920 op_ad = 2;
1d9f512f 5921 OP_E (float_mem_mode[fp_indx], sizeflag);
252b5132
RH		 5922 return;
5923 }
6608db57 5924 /* Skip mod/rm byte. */
4bba6815 5925 MODRM_CHECK;
252b5132
RH		 5926 codep++;
5927
7967e09e 5928 dp = &float_reg[floatop - 0xd8][modrm.reg];
252b5132
RH		 5929 if (dp->name == NULL)
5930 {
7967e09e 5931 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
252b5132 5932
6608db57 5933 /* Instruction fnstsw is only one with strange arg. */
252b5132 5934 if (floatop == 0xdf && codep[-1] == 0xe0)
ce518a5f 5935 strcpy (op_out[0], names16[0]);
252b5132
RH		 5936 }
5937 else
5938 {
5939 putop (dp->name, sizeflag);
5940
ce518a5f 5941 obufp = op_out[0];
6e50d963 5942 op_ad = 2;
ce518a5f
L		 5943 if (dp->op[0].rtn)
5944 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
6e50d963 5945
ce518a5f 5946 obufp = op_out[1];
6e50d963 5947 op_ad = 1;
ce518a5f
L		 5948 if (dp->op[1].rtn)
5949 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
252b5132
RH		 5950 }
5951}
5952
252b5132 5953static void
26ca5450 5954OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 5955{
422673a9 5956 oappend ("%st" + intel_syntax);
252b5132
RH		 5957}
5958
252b5132 5959static void
26ca5450 5960OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 5961{
7967e09e 5962 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
d708bcba 5963 oappend (scratchbuf + intel_syntax);
252b5132
RH		 5964}
5965
6608db57 5966/* Capital letters in template are macros. */
6439fc28 5967static int
26ca5450 5968putop (const char *template, int sizeflag)
252b5132 5969{
2da11e11 5970 const char *p;
9306ca4a 5971 int alt = 0;
9d141669 5972 int cond = 1;
98b528ac
L		 5973 unsigned int l = 0, len = 1;
5974 char last[4];
5975
5976#define SAVE_LAST(c) \
5977 if (l < len && l < sizeof (last)) \
5978 last[l++] = c; \
5979 else \
5980 abort ();
252b5132
RH		 5981
5982 for (p = template; *p; p++)
5983 {
5984 switch (*p)
5985 {
5986 default:
5987 *obufp++ = *p;
5988 break;
98b528ac
L		 5989 case '%':
5990 len++;
5991 break;
9d141669
L		 5992 case '!':
5993 cond = 0;
5994 break;
6439fc28
AM		 5995 case '{':
5996 alt = 0;
5997 if (intel_syntax)
6439fc28
AM		 5998 {
5999 while (*++p != '|')
7c52e0e8
L		 6000 if (*p == '}' || *p == '\0')
6001 abort ();
6439fc28 6002 }
9306ca4a
JB		 6003 /* Fall through. */
6004 case 'I':
6005 alt = 1;
6006 continue;
6439fc28
AM		 6007 case '|':
6008 while (*++p != '}')
6009 {
6010 if (*p == '\0')
6011 abort ();
6012 }
6013 break;
6014 case '}':
6015 break;
252b5132 6016 case 'A':
db6eb5be
AM		 6017 if (intel_syntax)
6018 break;
7967e09e 6019 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
252b5132
RH		 6020 *obufp++ = 'b';
6021 break;
6022 case 'B':
db6eb5be
AM		 6023 if (intel_syntax)
6024 break;
252b5132
RH		 6025 if (sizeflag & SUFFIX_ALWAYS)
6026 *obufp++ = 'b';
252b5132 6027 break;
9306ca4a
JB		 6028 case 'C':
6029 if (intel_syntax && !alt)
6030 break;
6031 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
6032 {
6033 if (sizeflag & DFLAG)
6034 *obufp++ = intel_syntax ? 'd' : 'l';
6035 else
6036 *obufp++ = intel_syntax ? 'w' : 's';
6037 used_prefixes |= (prefixes & PREFIX_DATA);
6038 }
6039 break;
ed7841b3
JB		 6040 case 'D':
6041 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
6042 break;
161a04f6 6043 USED_REX (REX_W);
7967e09e 6044 if (modrm.mod == 3)
ed7841b3 6045 {
161a04f6 6046 if (rex & REX_W)
ed7841b3
JB		 6047 *obufp++ = 'q';
6048 else if (sizeflag & DFLAG)
6049 *obufp++ = intel_syntax ? 'd' : 'l';
6050 else
6051 *obufp++ = 'w';
6052 used_prefixes |= (prefixes & PREFIX_DATA);
6053 }
6054 else
6055 *obufp++ = 'w';
6056 break;
252b5132 6057 case 'E': /* For jcxz/jecxz */
cb712a9e 6058 if (address_mode == mode_64bit)
c1a64871
JH		 6059 {
6060 if (sizeflag & AFLAG)
6061 *obufp++ = 'r';
6062 else
6063 *obufp++ = 'e';
6064 }
6065 else
6066 if (sizeflag & AFLAG)
6067 *obufp++ = 'e';
3ffd33cf
AM		 6068 used_prefixes |= (prefixes & PREFIX_ADDR);
6069 break;
6070 case 'F':
db6eb5be
AM		 6071 if (intel_syntax)
6072 break;
e396998b 6073 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
3ffd33cf
AM		 6074 {
6075 if (sizeflag & AFLAG)
cb712a9e 6076 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
3ffd33cf 6077 else
cb712a9e 6078 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
3ffd33cf
AM		 6079 used_prefixes |= (prefixes & PREFIX_ADDR);
6080 }
252b5132 6081 break;
52fd6d94
JB		 6082 case 'G':
6083 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
6084 break;
161a04f6 6085 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 6086 *obufp++ = 'l';
6087 else
6088 *obufp++ = 'w';
161a04f6 6089 if (!(rex & REX_W))
52fd6d94
JB		 6090 used_prefixes |= (prefixes & PREFIX_DATA);
6091 break;
5dd0794d 6092 case 'H':
db6eb5be
AM		 6093 if (intel_syntax)
6094 break;
5dd0794d
AM		 6095 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
6096 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
6097 {
6098 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
6099 *obufp++ = ',';
6100 *obufp++ = 'p';
6101 if (prefixes & PREFIX_DS)
6102 *obufp++ = 't';
6103 else
6104 *obufp++ = 'n';
6105 }
6106 break;
9306ca4a
JB		 6107 case 'J':
6108 if (intel_syntax)
6109 break;
6110 *obufp++ = 'l';
6111 break;
42903f7f
L		 6112 case 'K':
6113 USED_REX (REX_W);
6114 if (rex & REX_W)
6115 *obufp++ = 'q';
6116 else
6117 *obufp++ = 'd';
6118 break;
6dd5059a
L		 6119 case 'Z':
6120 if (intel_syntax)
6121 break;
6122 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
6123 {
6124 *obufp++ = 'q';
6125 break;
6126 }
6127 /* Fall through. */
98b528ac 6128 goto case_L;
252b5132 6129 case 'L':
98b528ac
L		 6130 if (l != 0 || len != 1)
6131 {
6132 SAVE_LAST (*p);
6133 break;
6134 }
6135case_L:
db6eb5be
AM		 6136 if (intel_syntax)
6137 break;
252b5132
RH		 6138 if (sizeflag & SUFFIX_ALWAYS)
6139 *obufp++ = 'l';
252b5132 6140 break;
9d141669
L		 6141 case 'M':
6142 if (intel_mnemonic != cond)
6143 *obufp++ = 'r';
6144 break;
252b5132
RH		 6145 case 'N':
6146 if ((prefixes & PREFIX_FWAIT) == 0)
6147 *obufp++ = 'n';
7d421014
ILT		 6148 else
6149 used_prefixes |= PREFIX_FWAIT;
252b5132 6150 break;
52b15da3 6151 case 'O':
161a04f6
L		 6152 USED_REX (REX_W);
6153 if (rex & REX_W)
6439fc28 6154 *obufp++ = 'o';
a35ca55a
JB		 6155 else if (intel_syntax && (sizeflag & DFLAG))
6156 *obufp++ = 'q';
52b15da3
JH		 6157 else
6158 *obufp++ = 'd';
161a04f6 6159 if (!(rex & REX_W))
a35ca55a 6160 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 6161 break;
6439fc28 6162 case 'T':
db6eb5be
AM		 6163 if (intel_syntax)
6164 break;
cb712a9e 6165 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 6166 {
6167 *obufp++ = 'q';
6168 break;
6169 }
6608db57 6170 /* Fall through. */
252b5132 6171 case 'P':
db6eb5be
AM		 6172 if (intel_syntax)
6173 break;
252b5132 6174 if ((prefixes & PREFIX_DATA)
161a04f6 6175 || (rex & REX_W)
e396998b 6176 || (sizeflag & SUFFIX_ALWAYS))
252b5132 6177 {
161a04f6
L		 6178 USED_REX (REX_W);
6179 if (rex & REX_W)
52b15da3 6180 *obufp++ = 'q';
c2419411 6181 else
52b15da3
JH		 6182 {
6183 if (sizeflag & DFLAG)
6184 *obufp++ = 'l';
6185 else
6186 *obufp++ = 'w';
52b15da3 6187 }
1a114b12 6188 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 6189 }
6190 break;
6439fc28 6191 case 'U':
db6eb5be
AM		 6192 if (intel_syntax)
6193 break;
cb712a9e 6194 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28 6195 {
7967e09e 6196 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
1a114b12 6197 *obufp++ = 'q';
6439fc28
AM		 6198 break;
6199 }
6608db57 6200 /* Fall through. */
98b528ac 6201 goto case_Q;
252b5132 6202 case 'Q':
98b528ac 6203 if (l == 0 && len == 1)
252b5132 6204 {
98b528ac
L		 6205case_Q:
6206 if (intel_syntax && !alt)
6207 break;
6208 USED_REX (REX_W);
6209 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
52b15da3 6210 {
98b528ac
L		 6211 if (rex & REX_W)
6212 *obufp++ = 'q';
52b15da3 6213 else
98b528ac
L		 6214 {
6215 if (sizeflag & DFLAG)
6216 *obufp++ = intel_syntax ? 'd' : 'l';
6217 else
6218 *obufp++ = 'w';
6219 }
6220 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 6221 }
98b528ac
L		 6222 }
6223 else
6224 {
6225 if (l != 1 || len != 2 || last[0] != 'L')
6226 {
6227 SAVE_LAST (*p);
6228 break;
6229 }
6230 if (intel_syntax
6231 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
6232 break;
6233 if ((rex & REX_W))
6234 {
6235 USED_REX (REX_W);
6236 *obufp++ = 'q';
6237 }
6238 else
6239 *obufp++ = 'l';
252b5132
RH		 6240 }
6241 break;
6242 case 'R':
161a04f6
L		 6243 USED_REX (REX_W);
6244 if (rex & REX_W)
a35ca55a
JB		 6245 *obufp++ = 'q';
6246 else if (sizeflag & DFLAG)
c608c12e 6247 {
a35ca55a 6248 if (intel_syntax)
c608c12e 6249 *obufp++ = 'd';
c608c12e 6250 else
a35ca55a 6251 *obufp++ = 'l';
c608c12e 6252 }
252b5132 6253 else
a35ca55a
JB		 6254 *obufp++ = 'w';
6255 if (intel_syntax && !p[1]
161a04f6 6256 && ((rex & REX_W) || (sizeflag & DFLAG)))
a35ca55a 6257 *obufp++ = 'e';
161a04f6 6258 if (!(rex & REX_W))
52b15da3 6259 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6260 break;
1a114b12
JB		 6261 case 'V':
6262 if (intel_syntax)
6263 break;
cb712a9e 6264 if (address_mode == mode_64bit && (sizeflag & DFLAG))
1a114b12
JB		 6265 {
6266 if (sizeflag & SUFFIX_ALWAYS)
6267 *obufp++ = 'q';
6268 break;
6269 }
6270 /* Fall through. */
252b5132 6271 case 'S':
db6eb5be
AM		 6272 if (intel_syntax)
6273 break;
252b5132
RH		 6274 if (sizeflag & SUFFIX_ALWAYS)
6275 {
161a04f6 6276 if (rex & REX_W)
52b15da3 6277 *obufp++ = 'q';
252b5132 6278 else
52b15da3
JH		 6279 {
6280 if (sizeflag & DFLAG)
6281 *obufp++ = 'l';
6282 else
6283 *obufp++ = 'w';
6284 used_prefixes |= (prefixes & PREFIX_DATA);
6285 }
252b5132 6286 }
252b5132 6287 break;
041bd2e0
JH		 6288 case 'X':
6289 if (prefixes & PREFIX_DATA)
6290 *obufp++ = 'd';
6291 else
6292 *obufp++ = 's';
db6eb5be 6293 used_prefixes |= (prefixes & PREFIX_DATA);
041bd2e0 6294 break;
76f227a5 6295 case 'Y':
8a72226a 6296 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
db6eb5be 6297 break;
161a04f6 6298 if (rex & REX_W)
76f227a5 6299 {
161a04f6 6300 USED_REX (REX_W);
76f227a5
JH		 6301 *obufp++ = 'q';
6302 }
6303 break;
52b15da3 6304 /* implicit operand size 'l' for i386 or 'q' for x86-64 */
252b5132 6305 case 'W':
252b5132 6306 /* operand size flag for cwtl, cbtw */
161a04f6
L		 6307 USED_REX (REX_W);
6308 if (rex & REX_W)
a35ca55a
JB		 6309 {
6310 if (intel_syntax)
6311 *obufp++ = 'd';
6312 else
6313 *obufp++ = 'l';
6314 }
52b15da3 6315 else if (sizeflag & DFLAG)
252b5132
RH		 6316 *obufp++ = 'w';
6317 else
6318 *obufp++ = 'b';
161a04f6 6319 if (!(rex & REX_W))
52b15da3 6320 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 6321 break;
6322 }
9306ca4a 6323 alt = 0;
252b5132
RH		 6324 }
6325 *obufp = 0;
6439fc28 6326 return 0;
252b5132
RH		 6327}
6328
6329static void
26ca5450 6330oappend (const char *s)
252b5132
RH		 6331{
6332 strcpy (obufp, s);
6333 obufp += strlen (s);
6334}
6335
6336static void
26ca5450 6337append_seg (void)
252b5132
RH		 6338{
6339 if (prefixes & PREFIX_CS)
7d421014 6340 {
7d421014 6341 used_prefixes |= PREFIX_CS;
d708bcba 6342 oappend ("%cs:" + intel_syntax);
7d421014 6343 }
252b5132 6344 if (prefixes & PREFIX_DS)
7d421014 6345 {
7d421014 6346 used_prefixes |= PREFIX_DS;
d708bcba 6347 oappend ("%ds:" + intel_syntax);
7d421014 6348 }
252b5132 6349 if (prefixes & PREFIX_SS)
7d421014 6350 {
7d421014 6351 used_prefixes |= PREFIX_SS;
d708bcba 6352 oappend ("%ss:" + intel_syntax);
7d421014 6353 }
252b5132 6354 if (prefixes & PREFIX_ES)
7d421014 6355 {
7d421014 6356 used_prefixes |= PREFIX_ES;
d708bcba 6357 oappend ("%es:" + intel_syntax);
7d421014 6358 }
252b5132 6359 if (prefixes & PREFIX_FS)
7d421014 6360 {
7d421014 6361 used_prefixes |= PREFIX_FS;
d708bcba 6362 oappend ("%fs:" + intel_syntax);
7d421014 6363 }
252b5132 6364 if (prefixes & PREFIX_GS)
7d421014 6365 {
7d421014 6366 used_prefixes |= PREFIX_GS;
d708bcba 6367 oappend ("%gs:" + intel_syntax);
7d421014 6368 }
252b5132
RH		 6369}
6370
6371static void
26ca5450 6372OP_indirE (int bytemode, int sizeflag)
252b5132
RH		 6373{
6374 if (!intel_syntax)
6375 oappend ("*");
6376 OP_E (bytemode, sizeflag);
6377}
6378
52b15da3 6379static void
26ca5450 6380print_operand_value (char *buf, int hex, bfd_vma disp)
52b15da3 6381{
cb712a9e 6382 if (address_mode == mode_64bit)
52b15da3
JH		 6383 {
6384 if (hex)
6385 {
6386 char tmp[30];
6387 int i;
6388 buf[0] = '0';
6389 buf[1] = 'x';
6390 sprintf_vma (tmp, disp);
6608db57 6391 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
52b15da3
JH		 6392 strcpy (buf + 2, tmp + i);
6393 }
6394 else
6395 {
6396 bfd_signed_vma v = disp;
6397 char tmp[30];
6398 int i;
6399 if (v < 0)
6400 {
6401 *(buf++) = '-';
6402 v = -disp;
6608db57 6403 /* Check for possible overflow on 0x8000000000000000. */
52b15da3
JH		 6404 if (v < 0)
6405 {
6406 strcpy (buf, "9223372036854775808");
6407 return;
6408 }
6409 }
6410 if (!v)
6411 {
6412 strcpy (buf, "0");
6413 return;
6414 }
6415
6416 i = 0;
6417 tmp[29] = 0;
6418 while (v)
6419 {
6608db57 6420 tmp[28 - i] = (v % 10) + '0';
52b15da3
JH		 6421 v /= 10;
6422 i++;
6423 }
6424 strcpy (buf, tmp + 29 - i);
6425 }
6426 }
6427 else
6428 {
6429 if (hex)
6430 sprintf (buf, "0x%x", (unsigned int) disp);
6431 else
6432 sprintf (buf, "%d", (int) disp);
6433 }
6434}
6435
5d669648
L		 6436/* Put DISP in BUF as signed hex number. */
6437
6438static void
6439print_displacement (char *buf, bfd_vma disp)
6440{
6441 bfd_signed_vma val = disp;
6442 char tmp[30];
6443 int i, j = 0;
6444
6445 if (val < 0)
6446 {
6447 buf[j++] = '-';
6448 val = -disp;
6449
6450 /* Check for possible overflow. */
6451 if (val < 0)
6452 {
6453 switch (address_mode)
6454 {
6455 case mode_64bit:
6456 strcpy (buf + j, "0x8000000000000000");
6457 break;
6458 case mode_32bit:
6459 strcpy (buf + j, "0x80000000");
6460 break;
6461 case mode_16bit:
6462 strcpy (buf + j, "0x8000");
6463 break;
6464 }
6465 return;
6466 }
6467 }
6468
6469 buf[j++] = '0';
6470 buf[j++] = 'x';
6471
6472 sprintf_vma (tmp, val);
6473 for (i = 0; tmp[i] == '0'; i++)
6474 continue;
6475 if (tmp[i] == '\0')
6476 i--;
6477 strcpy (buf + j, tmp + i);
6478}
6479
3f31e633
JB		 6480static void
6481intel_operand_size (int bytemode, int sizeflag)
6482{
6483 switch (bytemode)
6484 {
6485 case b_mode:
42903f7f 6486 case dqb_mode:
3f31e633
JB		 6487 oappend ("BYTE PTR ");
6488 break;
6489 case w_mode:
6490 case dqw_mode:
6491 oappend ("WORD PTR ");
6492 break;
1a114b12 6493 case stack_v_mode:
cb712a9e 6494 if (address_mode == mode_64bit && (sizeflag & DFLAG))
3f31e633
JB		 6495 {
6496 oappend ("QWORD PTR ");
6497 used_prefixes |= (prefixes & PREFIX_DATA);
6498 break;
6499 }
6500 /* FALLTHRU */
6501 case v_mode:
6502 case dq_mode:
161a04f6
L		 6503 USED_REX (REX_W);
6504 if (rex & REX_W)
3f31e633
JB		 6505 oappend ("QWORD PTR ");
6506 else if ((sizeflag & DFLAG) || bytemode == dq_mode)
6507 oappend ("DWORD PTR ");
6508 else
6509 oappend ("WORD PTR ");
6510 used_prefixes |= (prefixes & PREFIX_DATA);
6511 break;
52fd6d94 6512 case z_mode:
161a04f6 6513 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 6514 *obufp++ = 'D';
6515 oappend ("WORD PTR ");
161a04f6 6516 if (!(rex & REX_W))
52fd6d94
JB		 6517 used_prefixes |= (prefixes & PREFIX_DATA);
6518 break;
3f31e633 6519 case d_mode:
42903f7f 6520 case dqd_mode:
3f31e633
JB		 6521 oappend ("DWORD PTR ");
6522 break;
6523 case q_mode:
6524 oappend ("QWORD PTR ");
6525 break;
6526 case m_mode:
cb712a9e 6527 if (address_mode == mode_64bit)
3f31e633
JB		 6528 oappend ("QWORD PTR ");
6529 else
6530 oappend ("DWORD PTR ");
6531 break;
6532 case f_mode:
6533 if (sizeflag & DFLAG)
6534 oappend ("FWORD PTR ");
6535 else
6536 oappend ("DWORD PTR ");
6537 used_prefixes |= (prefixes & PREFIX_DATA);
6538 break;
6539 case t_mode:
6540 oappend ("TBYTE PTR ");
6541 break;
6542 case x_mode:
6543 oappend ("XMMWORD PTR ");
6544 break;
fb9c77c7
L		 6545 case o_mode:
6546 oappend ("OWORD PTR ");
6547 break;
3f31e633
JB		 6548 default:
6549 break;
6550 }
6551}
6552
252b5132 6553static void
85f10a01 6554OP_E_extended (int bytemode, int sizeflag, int has_drex)
252b5132 6555{
52b15da3
JH		 6556 bfd_vma disp;
6557 int add = 0;
6558 int riprel = 0;
161a04f6
L		 6559 USED_REX (REX_B);
6560 if (rex & REX_B)
52b15da3 6561 add += 8;
252b5132 6562
6608db57 6563 /* Skip mod/rm byte. */
4bba6815 6564 MODRM_CHECK;
252b5132
RH		 6565 codep++;
6566
7967e09e 6567 if (modrm.mod == 3)
252b5132
RH		 6568 {
6569 switch (bytemode)
6570 {
6571 case b_mode:
52b15da3
JH		 6572 USED_REX (0);
6573 if (rex)
7967e09e 6574 oappend (names8rex[modrm.rm + add]);
52b15da3 6575 else
7967e09e 6576 oappend (names8[modrm.rm + add]);
252b5132
RH		 6577 break;
6578 case w_mode:
7967e09e 6579 oappend (names16[modrm.rm + add]);
252b5132 6580 break;
2da11e11 6581 case d_mode:
7967e09e 6582 oappend (names32[modrm.rm + add]);
52b15da3
JH		 6583 break;
6584 case q_mode:
7967e09e 6585 oappend (names64[modrm.rm + add]);
52b15da3
JH		 6586 break;
6587 case m_mode:
cb712a9e 6588 if (address_mode == mode_64bit)
7967e09e 6589 oappend (names64[modrm.rm + add]);
52b15da3 6590 else
7967e09e 6591 oappend (names32[modrm.rm + add]);
2da11e11 6592 break;
1a114b12 6593 case stack_v_mode:
cb712a9e 6594 if (address_mode == mode_64bit && (sizeflag & DFLAG))
003519a7 6595 {
7967e09e 6596 oappend (names64[modrm.rm + add]);
003519a7 6597 used_prefixes |= (prefixes & PREFIX_DATA);
1a114b12 6598 break;
003519a7 6599 }
1a114b12
JB		 6600 bytemode = v_mode;
6601 /* FALLTHRU */
252b5132 6602 case v_mode:
db6eb5be 6603 case dq_mode:
42903f7f
L		 6604 case dqb_mode:
6605 case dqd_mode:
9306ca4a 6606 case dqw_mode:
161a04f6
L		 6607 USED_REX (REX_W);
6608 if (rex & REX_W)
7967e09e 6609 oappend (names64[modrm.rm + add]);
9306ca4a 6610 else if ((sizeflag & DFLAG) || bytemode != v_mode)
7967e09e 6611 oappend (names32[modrm.rm + add]);
252b5132 6612 else
7967e09e 6613 oappend (names16[modrm.rm + add]);
7d421014 6614 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6615 break;
2da11e11 6616 case 0:
c608c12e 6617 break;
252b5132 6618 default:
c608c12e 6619 oappend (INTERNAL_DISASSEMBLER_ERROR);
252b5132
RH		 6620 break;
6621 }
6622 return;
6623 }
6624
6625 disp = 0;
3f31e633
JB		 6626 if (intel_syntax)
6627 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 6628 append_seg ();
6629
5d669648 6630 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132 6631 {
5d669648
L		 6632 /* 32/64 bit address mode */
6633 int havedisp;
252b5132
RH		 6634 int havesib;
6635 int havebase;
0f7da397 6636 int haveindex;
20afcfb7 6637 int needindex;
252b5132
RH		 6638 int base;
6639 int index = 0;
6640 int scale = 0;
6641
6642 havesib = 0;
6643 havebase = 1;
0f7da397 6644 haveindex = 0;
7967e09e 6645 base = modrm.rm;
252b5132
RH		 6646
6647 if (base == 4)
6648 {
6649 havesib = 1;
6650 FETCH_DATA (the_info, codep + 1);
252b5132 6651 index = (*codep >> 3) & 7;
db51cc60 6652 scale = (*codep >> 6) & 3;
252b5132 6653 base = *codep & 7;
161a04f6
L		 6654 USED_REX (REX_X);
6655 if (rex & REX_X)
52b15da3 6656 index += 8;
0f7da397 6657 haveindex = index != 4;
252b5132
RH		 6658 codep++;
6659 }
2888cb7a 6660 base += add;
252b5132 6661
85f10a01
MM		 6662 /* If we have a DREX byte, skip it now
6663 (it has already been handled) */
6664 if (has_drex)
6665 {
6666 FETCH_DATA (the_info, codep + 1);
6667 codep++;
6668 }
6669
7967e09e 6670 switch (modrm.mod)
252b5132
RH		 6671 {
6672 case 0:
52b15da3 6673 if ((base & 7) == 5)
252b5132
RH		 6674 {
6675 havebase = 0;
cb712a9e 6676 if (address_mode == mode_64bit && !havesib)
52b15da3
JH		 6677 riprel = 1;
6678 disp = get32s ();
252b5132
RH		 6679 }
6680 break;
6681 case 1:
6682 FETCH_DATA (the_info, codep + 1);
6683 disp = *codep++;
6684 if ((disp & 0x80) != 0)
6685 disp -= 0x100;
6686 break;
6687 case 2:
52b15da3 6688 disp = get32s ();
252b5132
RH		 6689 break;
6690 }
6691
20afcfb7
L		 6692 /* In 32bit mode, we need index register to tell [offset] from
6693 [eiz*1 + offset]. */
6694 needindex = (havesib
6695 && !havebase
6696 && !haveindex
6697 && address_mode == mode_32bit);
6698 havedisp = (havebase
6699 || needindex
6700 || (havesib && (haveindex || scale != 0)));
5d669648 6701
252b5132 6702 if (!intel_syntax)
7967e09e 6703 if (modrm.mod != 0 || (base & 7) == 5)
db6eb5be 6704 {
5d669648
L		 6705 if (havedisp || riprel)
6706 print_displacement (scratchbuf, disp);
6707 else
6708 print_operand_value (scratchbuf, 1, disp);
db6eb5be 6709 oappend (scratchbuf);
52b15da3
JH		 6710 if (riprel)
6711 {
6712 set_op (disp, 1);
87767711 6713 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
52b15da3 6714 }
db6eb5be 6715 }
2da11e11 6716
87767711
JB		 6717 if (havebase || haveindex || riprel)
6718 used_prefixes |= PREFIX_ADDR;
6719
5d669648 6720 if (havedisp || (intel_syntax && riprel))
252b5132 6721 {
252b5132 6722 *obufp++ = open_char;
52b15da3 6723 if (intel_syntax && riprel)
185b1163
L		 6724 {
6725 set_op (disp, 1);
87767711 6726 oappend (sizeflag & AFLAG ? "rip" : "eip");
185b1163 6727 }
db6eb5be 6728 *obufp = '\0';
252b5132 6729 if (havebase)
cb712a9e 6730 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
c1a64871 6731 ? names64[base] : names32[base]);
252b5132
RH		 6732 if (havesib)
6733 {
db51cc60
L		 6734 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
6735 print index to tell base + index from base. */
6736 if (scale != 0
20afcfb7 6737 || needindex
db51cc60
L		 6738 || haveindex
6739 || (havebase && base != ESP_REG_NUM))
252b5132 6740 {
9306ca4a 6741 if (!intel_syntax || havebase)
db6eb5be 6742 {
9306ca4a
JB		 6743 *obufp++ = separator_char;
6744 *obufp = '\0';
db6eb5be 6745 }
db51cc60
L		 6746 if (haveindex)
6747 oappend (address_mode == mode_64bit
6748 && (sizeflag & AFLAG)
6749 ? names64[index] : names32[index]);
6750 else
6751 oappend (address_mode == mode_64bit
6752 && (sizeflag & AFLAG)
6753 ? index64 : index32);
6754
db6eb5be
AM		 6755 *obufp++ = scale_char;
6756 *obufp = '\0';
6757 sprintf (scratchbuf, "%d", 1 << scale);
6758 oappend (scratchbuf);
6759 }
252b5132 6760 }
185b1163
L		 6761 if (intel_syntax
6762 && (disp || modrm.mod != 0 || (base & 7) == 5))
3d456fa1 6763 {
db51cc60 6764 if (!havedisp || (bfd_signed_vma) disp >= 0)
3d456fa1
JB		 6765 {
6766 *obufp++ = '+';
6767 *obufp = '\0';
6768 }
7967e09e 6769 else if (modrm.mod != 1)
3d456fa1
JB		 6770 {
6771 *obufp++ = '-';
6772 *obufp = '\0';
6773 disp = - (bfd_signed_vma) disp;
6774 }
6775
db51cc60
L		 6776 if (havedisp)
6777 print_displacement (scratchbuf, disp);
6778 else
6779 print_operand_value (scratchbuf, 1, disp);
3d456fa1
JB		 6780 oappend (scratchbuf);
6781 }
252b5132
RH		 6782
6783 *obufp++ = close_char;
db6eb5be 6784 *obufp = '\0';
252b5132
RH		 6785 }
6786 else if (intel_syntax)
db6eb5be 6787 {
7967e09e 6788 if (modrm.mod != 0 || (base & 7) == 5)
db6eb5be 6789 {
252b5132
RH		 6790 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
6791 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
6792 ;
6793 else
6794 {
d708bcba 6795 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 6796 oappend (":");
6797 }
52b15da3 6798 print_operand_value (scratchbuf, 1, disp);
db6eb5be
AM		 6799 oappend (scratchbuf);
6800 }
6801 }
252b5132
RH		 6802 }
6803 else
6804 { /* 16 bit address mode */
7967e09e 6805 switch (modrm.mod)
252b5132
RH		 6806 {
6807 case 0:
7967e09e 6808 if (modrm.rm == 6)
252b5132
RH		 6809 {
6810 disp = get16 ();
6811 if ((disp & 0x8000) != 0)
6812 disp -= 0x10000;
6813 }
6814 break;
6815 case 1:
6816 FETCH_DATA (the_info, codep + 1);
6817 disp = *codep++;
6818 if ((disp & 0x80) != 0)
6819 disp -= 0x100;
6820 break;
6821 case 2:
6822 disp = get16 ();
6823 if ((disp & 0x8000) != 0)
6824 disp -= 0x10000;
6825 break;
6826 }
6827
6828 if (!intel_syntax)
7967e09e 6829 if (modrm.mod != 0 || modrm.rm == 6)
db6eb5be 6830 {
5d669648 6831 print_displacement (scratchbuf, disp);
db6eb5be
AM		 6832 oappend (scratchbuf);
6833 }
252b5132 6834
7967e09e 6835 if (modrm.mod != 0 || modrm.rm != 6)
252b5132
RH		 6836 {
6837 *obufp++ = open_char;
db6eb5be 6838 *obufp = '\0';
7967e09e 6839 oappend (index16[modrm.rm]);
5d669648
L		 6840 if (intel_syntax
6841 && (disp || modrm.mod != 0 || modrm.rm == 6))
3d456fa1 6842 {
5d669648 6843 if ((bfd_signed_vma) disp >= 0)
3d456fa1
JB		 6844 {
6845 *obufp++ = '+';
6846 *obufp = '\0';
6847 }
7967e09e 6848 else if (modrm.mod != 1)
3d456fa1
JB		 6849 {
6850 *obufp++ = '-';
6851 *obufp = '\0';
6852 disp = - (bfd_signed_vma) disp;
6853 }
6854
5d669648 6855 print_displacement (scratchbuf, disp);
3d456fa1
JB		 6856 oappend (scratchbuf);
6857 }
6858
db6eb5be
AM		 6859 *obufp++ = close_char;
6860 *obufp = '\0';
252b5132 6861 }
3d456fa1
JB		 6862 else if (intel_syntax)
6863 {
6864 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
6865 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
6866 ;
6867 else
6868 {
6869 oappend (names_seg[ds_reg - es_reg]);
6870 oappend (":");
6871 }
6872 print_operand_value (scratchbuf, 1, disp & 0xffff);
6873 oappend (scratchbuf);
6874 }
252b5132
RH		 6875 }
6876}
6877
85f10a01
MM		 6878static void
6879OP_E (int bytemode, int sizeflag)
6880{
6881 OP_E_extended (bytemode, sizeflag, 0);
6882}
6883
6884
252b5132 6885static void
26ca5450 6886OP_G (int bytemode, int sizeflag)
252b5132 6887{
52b15da3 6888 int add = 0;
161a04f6
L		 6889 USED_REX (REX_R);
6890 if (rex & REX_R)
52b15da3 6891 add += 8;
252b5132
RH		 6892 switch (bytemode)
6893 {
6894 case b_mode:
52b15da3
JH		 6895 USED_REX (0);
6896 if (rex)
7967e09e 6897 oappend (names8rex[modrm.reg + add]);
52b15da3 6898 else
7967e09e 6899 oappend (names8[modrm.reg + add]);
252b5132
RH		 6900 break;
6901 case w_mode:
7967e09e 6902 oappend (names16[modrm.reg + add]);
252b5132
RH		 6903 break;
6904 case d_mode:
7967e09e 6905 oappend (names32[modrm.reg + add]);
52b15da3
JH		 6906 break;
6907 case q_mode:
7967e09e 6908 oappend (names64[modrm.reg + add]);
252b5132
RH		 6909 break;
6910 case v_mode:
9306ca4a 6911 case dq_mode:
42903f7f
L		 6912 case dqb_mode:
6913 case dqd_mode:
9306ca4a 6914 case dqw_mode:
161a04f6
L		 6915 USED_REX (REX_W);
6916 if (rex & REX_W)
7967e09e 6917 oappend (names64[modrm.reg + add]);
9306ca4a 6918 else if ((sizeflag & DFLAG) || bytemode != v_mode)
7967e09e 6919 oappend (names32[modrm.reg + add]);
252b5132 6920 else
7967e09e 6921 oappend (names16[modrm.reg + add]);
7d421014 6922 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6923 break;
90700ea2 6924 case m_mode:
cb712a9e 6925 if (address_mode == mode_64bit)
7967e09e 6926 oappend (names64[modrm.reg + add]);
90700ea2 6927 else
7967e09e 6928 oappend (names32[modrm.reg + add]);
90700ea2 6929 break;
252b5132
RH		 6930 default:
6931 oappend (INTERNAL_DISASSEMBLER_ERROR);
6932 break;
6933 }
6934}
6935
52b15da3 6936static bfd_vma
26ca5450 6937get64 (void)
52b15da3 6938{
5dd0794d 6939 bfd_vma x;
52b15da3 6940#ifdef BFD64
5dd0794d
AM		 6941 unsigned int a;
6942 unsigned int b;
6943
52b15da3
JH		 6944 FETCH_DATA (the_info, codep + 8);
6945 a = *codep++ & 0xff;
6946 a |= (*codep++ & 0xff) << 8;
6947 a |= (*codep++ & 0xff) << 16;
6948 a |= (*codep++ & 0xff) << 24;
5dd0794d 6949 b = *codep++ & 0xff;
52b15da3
JH		 6950 b |= (*codep++ & 0xff) << 8;
6951 b |= (*codep++ & 0xff) << 16;
6952 b |= (*codep++ & 0xff) << 24;
6953 x = a + ((bfd_vma) b << 32);
6954#else
6608db57 6955 abort ();
5dd0794d 6956 x = 0;
52b15da3
JH		 6957#endif
6958 return x;
6959}
6960
6961static bfd_signed_vma
26ca5450 6962get32 (void)
252b5132 6963{
52b15da3 6964 bfd_signed_vma x = 0;
252b5132
RH		 6965
6966 FETCH_DATA (the_info, codep + 4);
52b15da3
JH		 6967 x = *codep++ & (bfd_signed_vma) 0xff;
6968 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
6969 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
6970 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
6971 return x;
6972}
6973
6974static bfd_signed_vma
26ca5450 6975get32s (void)
52b15da3
JH		 6976{
6977 bfd_signed_vma x = 0;
6978
6979 FETCH_DATA (the_info, codep + 4);
6980 x = *codep++ & (bfd_signed_vma) 0xff;
6981 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
6982 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
6983 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
6984
6985 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
6986
252b5132
RH		 6987 return x;
6988}
6989
6990static int
26ca5450 6991get16 (void)
252b5132
RH		 6992{
6993 int x = 0;
6994
6995 FETCH_DATA (the_info, codep + 2);
6996 x = *codep++ & 0xff;
6997 x |= (*codep++ & 0xff) << 8;
6998 return x;
6999}
7000
7001static void
26ca5450 7002set_op (bfd_vma op, int riprel)
252b5132
RH		 7003{
7004 op_index[op_ad] = op_ad;
cb712a9e 7005 if (address_mode == mode_64bit)
7081ff04
AJ		 7006 {
7007 op_address[op_ad] = op;
7008 op_riprel[op_ad] = riprel;
7009 }
7010 else
7011 {
7012 /* Mask to get a 32-bit address. */
7013 op_address[op_ad] = op & 0xffffffff;
7014 op_riprel[op_ad] = riprel & 0xffffffff;
7015 }
252b5132
RH		 7016}
7017
7018static void
26ca5450 7019OP_REG (int code, int sizeflag)
252b5132 7020{
2da11e11 7021 const char *s;
9b60702d 7022 int add;
161a04f6
L		 7023 USED_REX (REX_B);
7024 if (rex & REX_B)
52b15da3 7025 add = 8;
9b60702d
L		 7026 else
7027 add = 0;
52b15da3
JH		 7028
7029 switch (code)
7030 {
52b15da3
JH		 7031 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
7032 case sp_reg: case bp_reg: case si_reg: case di_reg:
7033 s = names16[code - ax_reg + add];
7034 break;
7035 case es_reg: case ss_reg: case cs_reg:
7036 case ds_reg: case fs_reg: case gs_reg:
7037 s = names_seg[code - es_reg + add];
7038 break;
7039 case al_reg: case ah_reg: case cl_reg: case ch_reg:
7040 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
7041 USED_REX (0);
7042 if (rex)
7043 s = names8rex[code - al_reg + add];
7044 else
7045 s = names8[code - al_reg];
7046 break;
6439fc28
AM		 7047 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
7048 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
cb712a9e 7049 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 7050 {
7051 s = names64[code - rAX_reg + add];
7052 break;
7053 }
7054 code += eAX_reg - rAX_reg;
6608db57 7055 /* Fall through. */
52b15da3
JH		 7056 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
7057 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 7058 USED_REX (REX_W);
7059 if (rex & REX_W)
52b15da3
JH		 7060 s = names64[code - eAX_reg + add];
7061 else if (sizeflag & DFLAG)
7062 s = names32[code - eAX_reg + add];
7063 else
7064 s = names16[code - eAX_reg + add];
7065 used_prefixes |= (prefixes & PREFIX_DATA);
7066 break;
52b15da3
JH		 7067 default:
7068 s = INTERNAL_DISASSEMBLER_ERROR;
7069 break;
7070 }
7071 oappend (s);
7072}
7073
7074static void
26ca5450 7075OP_IMREG (int code, int sizeflag)
52b15da3
JH		 7076{
7077 const char *s;
252b5132
RH		 7078
7079 switch (code)
7080 {
7081 case indir_dx_reg:
d708bcba 7082 if (intel_syntax)
52fd6d94 7083 s = "dx";
d708bcba 7084 else
db6eb5be 7085 s = "(%dx)";
252b5132
RH		 7086 break;
7087 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
7088 case sp_reg: case bp_reg: case si_reg: case di_reg:
7089 s = names16[code - ax_reg];
7090 break;
7091 case es_reg: case ss_reg: case cs_reg:
7092 case ds_reg: case fs_reg: case gs_reg:
7093 s = names_seg[code - es_reg];
7094 break;
7095 case al_reg: case ah_reg: case cl_reg: case ch_reg:
7096 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
52b15da3
JH		 7097 USED_REX (0);
7098 if (rex)
7099 s = names8rex[code - al_reg];
7100 else
7101 s = names8[code - al_reg];
252b5132
RH		 7102 break;
7103 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
7104 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 7105 USED_REX (REX_W);
7106 if (rex & REX_W)
52b15da3
JH		 7107 s = names64[code - eAX_reg];
7108 else if (sizeflag & DFLAG)
252b5132
RH		 7109 s = names32[code - eAX_reg];
7110 else
7111 s = names16[code - eAX_reg];
7d421014 7112 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 7113 break;
52fd6d94 7114 case z_mode_ax_reg:
161a04f6 7115 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 7116 s = *names32;
7117 else
7118 s = *names16;
161a04f6 7119 if (!(rex & REX_W))
52fd6d94
JB		 7120 used_prefixes |= (prefixes & PREFIX_DATA);
7121 break;
252b5132
RH		 7122 default:
7123 s = INTERNAL_DISASSEMBLER_ERROR;
7124 break;
7125 }
7126 oappend (s);
7127}
7128
7129static void
26ca5450 7130OP_I (int bytemode, int sizeflag)
252b5132 7131{
52b15da3
JH		 7132 bfd_signed_vma op;
7133 bfd_signed_vma mask = -1;
252b5132
RH		 7134
7135 switch (bytemode)
7136 {
7137 case b_mode:
7138 FETCH_DATA (the_info, codep + 1);
52b15da3
JH		 7139 op = *codep++;
7140 mask = 0xff;
7141 break;
7142 case q_mode:
cb712a9e 7143 if (address_mode == mode_64bit)
6439fc28
AM		 7144 {
7145 op = get32s ();
7146 break;
7147 }
6608db57 7148 /* Fall through. */
252b5132 7149 case v_mode:
161a04f6
L		 7150 USED_REX (REX_W);
7151 if (rex & REX_W)
52b15da3
JH		 7152 op = get32s ();
7153 else if (sizeflag & DFLAG)
7154 {
7155 op = get32 ();
7156 mask = 0xffffffff;
7157 }
252b5132 7158 else
52b15da3
JH		 7159 {
7160 op = get16 ();
7161 mask = 0xfffff;
7162 }
7d421014 7163 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 7164 break;
7165 case w_mode:
52b15da3 7166 mask = 0xfffff;
252b5132
RH		 7167 op = get16 ();
7168 break;
9306ca4a
JB		 7169 case const_1_mode:
7170 if (intel_syntax)
7171 oappend ("1");
7172 return;
252b5132
RH		 7173 default:
7174 oappend (INTERNAL_DISASSEMBLER_ERROR);
7175 return;
7176 }
7177
52b15da3
JH		 7178 op &= mask;
7179 scratchbuf[0] = '$';
d708bcba
AM		 7180 print_operand_value (scratchbuf + 1, 1, op);
7181 oappend (scratchbuf + intel_syntax);
52b15da3
JH		 7182 scratchbuf[0] = '\0';
7183}
7184
7185static void
26ca5450 7186OP_I64 (int bytemode, int sizeflag)
52b15da3
JH		 7187{
7188 bfd_signed_vma op;
7189 bfd_signed_vma mask = -1;
7190
cb712a9e 7191 if (address_mode != mode_64bit)
6439fc28
AM		 7192 {
7193 OP_I (bytemode, sizeflag);
7194 return;
7195 }
7196
52b15da3
JH		 7197 switch (bytemode)
7198 {
7199 case b_mode:
7200 FETCH_DATA (the_info, codep + 1);
7201 op = *codep++;
7202 mask = 0xff;
7203 break;
7204 case v_mode:
161a04f6
L		 7205 USED_REX (REX_W);
7206 if (rex & REX_W)
52b15da3
JH		 7207 op = get64 ();
7208 else if (sizeflag & DFLAG)
7209 {
7210 op = get32 ();
7211 mask = 0xffffffff;
7212 }
7213 else
7214 {
7215 op = get16 ();
7216 mask = 0xfffff;
7217 }
7218 used_prefixes |= (prefixes & PREFIX_DATA);
7219 break;
7220 case w_mode:
7221 mask = 0xfffff;
7222 op = get16 ();
7223 break;
7224 default:
7225 oappend (INTERNAL_DISASSEMBLER_ERROR);
7226 return;
7227 }
7228
7229 op &= mask;
7230 scratchbuf[0] = '$';
d708bcba
AM		 7231 print_operand_value (scratchbuf + 1, 1, op);
7232 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7233 scratchbuf[0] = '\0';
7234}
7235
7236static void
26ca5450 7237OP_sI (int bytemode, int sizeflag)
252b5132 7238{
52b15da3
JH		 7239 bfd_signed_vma op;
7240 bfd_signed_vma mask = -1;
252b5132
RH		 7241
7242 switch (bytemode)
7243 {
7244 case b_mode:
7245 FETCH_DATA (the_info, codep + 1);
7246 op = *codep++;
7247 if ((op & 0x80) != 0)
7248 op -= 0x100;
52b15da3 7249 mask = 0xffffffff;
252b5132
RH		 7250 break;
7251 case v_mode:
161a04f6
L		 7252 USED_REX (REX_W);
7253 if (rex & REX_W)
52b15da3
JH		 7254 op = get32s ();
7255 else if (sizeflag & DFLAG)
7256 {
7257 op = get32s ();
7258 mask = 0xffffffff;
7259 }
252b5132
RH		 7260 else
7261 {
52b15da3 7262 mask = 0xffffffff;
6608db57 7263 op = get16 ();
252b5132
RH		 7264 if ((op & 0x8000) != 0)
7265 op -= 0x10000;
7266 }
7d421014 7267 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 7268 break;
7269 case w_mode:
7270 op = get16 ();
52b15da3 7271 mask = 0xffffffff;
252b5132
RH		 7272 if ((op & 0x8000) != 0)
7273 op -= 0x10000;
7274 break;
7275 default:
7276 oappend (INTERNAL_DISASSEMBLER_ERROR);
7277 return;
7278 }
52b15da3
JH		 7279
7280 scratchbuf[0] = '$';
7281 print_operand_value (scratchbuf + 1, 1, op);
d708bcba 7282 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7283}
7284
7285static void
26ca5450 7286OP_J (int bytemode, int sizeflag)
252b5132 7287{
52b15da3 7288 bfd_vma disp;
7081ff04 7289 bfd_vma mask = -1;
65ca155d 7290 bfd_vma segment = 0;
252b5132
RH		 7291
7292 switch (bytemode)
7293 {
7294 case b_mode:
7295 FETCH_DATA (the_info, codep + 1);
7296 disp = *codep++;
7297 if ((disp & 0x80) != 0)
7298 disp -= 0x100;
7299 break;
7300 case v_mode:
161a04f6 7301 if ((sizeflag & DFLAG) || (rex & REX_W))
52b15da3 7302 disp = get32s ();
252b5132
RH		 7303 else
7304 {
7305 disp = get16 ();
206717e8
L		 7306 if ((disp & 0x8000) != 0)
7307 disp -= 0x10000;
65ca155d
L		 7308 /* In 16bit mode, address is wrapped around at 64k within
7309 the same segment. Otherwise, a data16 prefix on a jump
7310 instruction means that the pc is masked to 16 bits after
7311 the displacement is added! */
7312 mask = 0xffff;
7313 if ((prefixes & PREFIX_DATA) == 0)
7314 segment = ((start_pc + codep - start_codep)
7315 & ~((bfd_vma) 0xffff));
252b5132 7316 }
d807a492 7317 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 7318 break;
7319 default:
7320 oappend (INTERNAL_DISASSEMBLER_ERROR);
7321 return;
7322 }
65ca155d 7323 disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
52b15da3
JH		 7324 set_op (disp, 0);
7325 print_operand_value (scratchbuf, 1, disp);
252b5132
RH		 7326 oappend (scratchbuf);
7327}
7328
252b5132 7329static void
ed7841b3 7330OP_SEG (int bytemode, int sizeflag)
252b5132 7331{
ed7841b3 7332 if (bytemode == w_mode)
7967e09e 7333 oappend (names_seg[modrm.reg]);
ed7841b3 7334 else
7967e09e 7335 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
252b5132
RH		 7336}
7337
7338static void
26ca5450 7339OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
252b5132
RH		 7340{
7341 int seg, offset;
7342
c608c12e 7343 if (sizeflag & DFLAG)
252b5132 7344 {
c608c12e
AM		 7345 offset = get32 ();
7346 seg = get16 ();
252b5132 7347 }
c608c12e
AM		 7348 else
7349 {
7350 offset = get16 ();
7351 seg = get16 ();
7352 }
7d421014 7353 used_prefixes |= (prefixes & PREFIX_DATA);
d708bcba 7354 if (intel_syntax)
3f31e633 7355 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
d708bcba
AM		 7356 else
7357 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
c608c12e 7358 oappend (scratchbuf);
252b5132
RH		 7359}
7360
252b5132 7361static void
3f31e633 7362OP_OFF (int bytemode, int sizeflag)
252b5132 7363{
52b15da3 7364 bfd_vma off;
252b5132 7365
3f31e633
JB		 7366 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
7367 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 7368 append_seg ();
7369
cb712a9e 7370 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132
RH		 7371 off = get32 ();
7372 else
7373 off = get16 ();
7374
7375 if (intel_syntax)
7376 {
7377 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 7378 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
252b5132 7379 {
d708bcba 7380 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 7381 oappend (":");
7382 }
7383 }
52b15da3
JH		 7384 print_operand_value (scratchbuf, 1, off);
7385 oappend (scratchbuf);
7386}
6439fc28 7387
52b15da3 7388static void
3f31e633 7389OP_OFF64 (int bytemode, int sizeflag)
52b15da3
JH		 7390{
7391 bfd_vma off;
7392
539e75ad
L		 7393 if (address_mode != mode_64bit
7394 || (prefixes & PREFIX_ADDR))
6439fc28
AM		 7395 {
7396 OP_OFF (bytemode, sizeflag);
7397 return;
7398 }
7399
3f31e633
JB		 7400 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
7401 intel_operand_size (bytemode, sizeflag);
52b15da3
JH		 7402 append_seg ();
7403
6608db57 7404 off = get64 ();
52b15da3
JH		 7405
7406 if (intel_syntax)
7407 {
7408 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 7409 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
52b15da3 7410 {
d708bcba 7411 oappend (names_seg[ds_reg - es_reg]);
52b15da3
JH		 7412 oappend (":");
7413 }
7414 }
7415 print_operand_value (scratchbuf, 1, off);
252b5132
RH		 7416 oappend (scratchbuf);
7417}
7418
7419static void
26ca5450 7420ptr_reg (int code, int sizeflag)
252b5132 7421{
2da11e11 7422 const char *s;
d708bcba 7423
1d9f512f 7424 *obufp++ = open_char;
20f0a1fc 7425 used_prefixes |= (prefixes & PREFIX_ADDR);
cb712a9e 7426 if (address_mode == mode_64bit)
c1a64871
JH		 7427 {
7428 if (!(sizeflag & AFLAG))
db6eb5be 7429 s = names32[code - eAX_reg];
c1a64871 7430 else
db6eb5be 7431 s = names64[code - eAX_reg];
c1a64871 7432 }
52b15da3 7433 else if (sizeflag & AFLAG)
252b5132
RH		 7434 s = names32[code - eAX_reg];
7435 else
7436 s = names16[code - eAX_reg];
7437 oappend (s);
1d9f512f
AM		 7438 *obufp++ = close_char;
7439 *obufp = 0;
252b5132
RH		 7440}
7441
7442static void
26ca5450 7443OP_ESreg (int code, int sizeflag)
252b5132 7444{
9306ca4a 7445 if (intel_syntax)
52fd6d94
JB		 7446 {
7447 switch (codep[-1])
7448 {
7449 case 0x6d: /* insw/insl */
7450 intel_operand_size (z_mode, sizeflag);
7451 break;
7452 case 0xa5: /* movsw/movsl/movsq */
7453 case 0xa7: /* cmpsw/cmpsl/cmpsq */
7454 case 0xab: /* stosw/stosl */
7455 case 0xaf: /* scasw/scasl */
7456 intel_operand_size (v_mode, sizeflag);
7457 break;
7458 default:
7459 intel_operand_size (b_mode, sizeflag);
7460 }
7461 }
d708bcba 7462 oappend ("%es:" + intel_syntax);
252b5132
RH		 7463 ptr_reg (code, sizeflag);
7464}
7465
7466static void
26ca5450 7467OP_DSreg (int code, int sizeflag)
252b5132 7468{
9306ca4a 7469 if (intel_syntax)
52fd6d94
JB		 7470 {
7471 switch (codep[-1])
7472 {
7473 case 0x6f: /* outsw/outsl */
7474 intel_operand_size (z_mode, sizeflag);
7475 break;
7476 case 0xa5: /* movsw/movsl/movsq */
7477 case 0xa7: /* cmpsw/cmpsl/cmpsq */
7478 case 0xad: /* lodsw/lodsl/lodsq */
7479 intel_operand_size (v_mode, sizeflag);
7480 break;
7481 default:
7482 intel_operand_size (b_mode, sizeflag);
7483 }
7484 }
252b5132
RH		 7485 if ((prefixes
7486 & (PREFIX_CS
7487 | PREFIX_DS
7488 | PREFIX_SS
7489 | PREFIX_ES
7490 | PREFIX_FS
7491 | PREFIX_GS)) == 0)
7492 prefixes |= PREFIX_DS;
6608db57 7493 append_seg ();
252b5132
RH		 7494 ptr_reg (code, sizeflag);
7495}
7496
252b5132 7497static void
26ca5450 7498OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7499{
9b60702d 7500 int add;
161a04f6 7501 if (rex & REX_R)
c4a530c5 7502 {
161a04f6 7503 USED_REX (REX_R);
c4a530c5
JB		 7504 add = 8;
7505 }
cb712a9e 7506 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
c4a530c5 7507 {
b844680a 7508 lock_prefix = NULL;
c4a530c5
JB		 7509 used_prefixes |= PREFIX_LOCK;
7510 add = 8;
7511 }
9b60702d
L		 7512 else
7513 add = 0;
7967e09e 7514 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
d708bcba 7515 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7516}
7517
252b5132 7518static void
26ca5450 7519OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7520{
9b60702d 7521 int add;
161a04f6
L		 7522 USED_REX (REX_R);
7523 if (rex & REX_R)
52b15da3 7524 add = 8;
9b60702d
L		 7525 else
7526 add = 0;
d708bcba 7527 if (intel_syntax)
7967e09e 7528 sprintf (scratchbuf, "db%d", modrm.reg + add);
d708bcba 7529 else
7967e09e 7530 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
252b5132
RH		 7531 oappend (scratchbuf);
7532}
7533
252b5132 7534static void
26ca5450 7535OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7536{
7967e09e 7537 sprintf (scratchbuf, "%%tr%d", modrm.reg);
d708bcba 7538 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7539}
7540
7541static void
6f74c397 7542OP_R (int bytemode, int sizeflag)
252b5132 7543{
7967e09e 7544 if (modrm.mod == 3)
2da11e11
AM		 7545 OP_E (bytemode, sizeflag);
7546 else
6608db57 7547 BadOp ();
252b5132
RH		 7548}
7549
7550static void
26ca5450 7551OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7552{
041bd2e0
JH		 7553 used_prefixes |= (prefixes & PREFIX_DATA);
7554 if (prefixes & PREFIX_DATA)
20f0a1fc 7555 {
9b60702d 7556 int add;
161a04f6
L		 7557 USED_REX (REX_R);
7558 if (rex & REX_R)
20f0a1fc 7559 add = 8;
9b60702d
L		 7560 else
7561 add = 0;
7967e09e 7562 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
20f0a1fc 7563 }
041bd2e0 7564 else
7967e09e 7565 sprintf (scratchbuf, "%%mm%d", modrm.reg);
d708bcba 7566 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7567}
7568
c608c12e 7569static void
26ca5450 7570OP_XMM (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e 7571{
9b60702d 7572 int add;
161a04f6
L		 7573 USED_REX (REX_R);
7574 if (rex & REX_R)
041bd2e0 7575 add = 8;
9b60702d
L		 7576 else
7577 add = 0;
7967e09e 7578 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
d708bcba 7579 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 7580}
7581
252b5132 7582static void
26ca5450 7583OP_EM (int bytemode, int sizeflag)
252b5132 7584{
7967e09e 7585 if (modrm.mod != 3)
252b5132 7586 {
9306ca4a
JB		 7587 if (intel_syntax && bytemode == v_mode)
7588 {
7589 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
7590 used_prefixes |= (prefixes & PREFIX_DATA);
7591 }
252b5132
RH		 7592 OP_E (bytemode, sizeflag);
7593 return;
7594 }
7595
6608db57 7596 /* Skip mod/rm byte. */
4bba6815 7597 MODRM_CHECK;
252b5132 7598 codep++;
041bd2e0
JH		 7599 used_prefixes |= (prefixes & PREFIX_DATA);
7600 if (prefixes & PREFIX_DATA)
20f0a1fc 7601 {
9b60702d 7602 int add;
20f0a1fc 7603
161a04f6
L		 7604 USED_REX (REX_B);
7605 if (rex & REX_B)
20f0a1fc 7606 add = 8;
9b60702d
L		 7607 else
7608 add = 0;
7967e09e 7609 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
20f0a1fc 7610 }
041bd2e0 7611 else
7967e09e 7612 sprintf (scratchbuf, "%%mm%d", modrm.rm);
d708bcba 7613 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7614}
7615
246c51aa
L		 7616/* cvt* are the only instructions in sse2 which have
7617 both SSE and MMX operands and also have 0x66 prefix
7618 in their opcode. 0x66 was originally used to differentiate
7619 between SSE and MMX instruction(operands). So we have to handle the
4d9567e0
MM		 7620 cvt* separately using OP_EMC and OP_MXC */
7621static void
7622OP_EMC (int bytemode, int sizeflag)
7623{
7967e09e 7624 if (modrm.mod != 3)
4d9567e0
MM		 7625 {
7626 if (intel_syntax && bytemode == v_mode)
7627 {
7628 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
7629 used_prefixes |= (prefixes & PREFIX_DATA);
7630 }
7631 OP_E (bytemode, sizeflag);
7632 return;
7633 }
246c51aa 7634
4d9567e0
MM		 7635 /* Skip mod/rm byte. */
7636 MODRM_CHECK;
7637 codep++;
7638 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 7639 sprintf (scratchbuf, "%%mm%d", modrm.rm);
4d9567e0
MM		 7640 oappend (scratchbuf + intel_syntax);
7641}
7642
7643static void
7644OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
7645{
7646 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 7647 sprintf (scratchbuf, "%%mm%d", modrm.reg);
4d9567e0
MM		 7648 oappend (scratchbuf + intel_syntax);
7649}
7650
c608c12e 7651static void
26ca5450 7652OP_EX (int bytemode, int sizeflag)
c608c12e 7653{
9b60702d 7654 int add;
7967e09e 7655 if (modrm.mod != 3)
c608c12e
AM		 7656 {
7657 OP_E (bytemode, sizeflag);
7658 return;
7659 }
161a04f6
L		 7660 USED_REX (REX_B);
7661 if (rex & REX_B)
041bd2e0 7662 add = 8;
9b60702d
L		 7663 else
7664 add = 0;
c608c12e 7665
6608db57 7666 /* Skip mod/rm byte. */
4bba6815 7667 MODRM_CHECK;
c608c12e 7668 codep++;
7967e09e 7669 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
d708bcba 7670 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 7671}
7672
252b5132 7673static void
26ca5450 7674OP_MS (int bytemode, int sizeflag)
252b5132 7675{
7967e09e 7676 if (modrm.mod == 3)
2da11e11
AM		 7677 OP_EM (bytemode, sizeflag);
7678 else
6608db57 7679 BadOp ();
252b5132
RH		 7680}
7681
992aaec9 7682static void
26ca5450 7683OP_XS (int bytemode, int sizeflag)
992aaec9 7684{
7967e09e 7685 if (modrm.mod == 3)
992aaec9
AM		 7686 OP_EX (bytemode, sizeflag);
7687 else
6608db57 7688 BadOp ();
992aaec9
AM		 7689}
7690
cc0ec051
AM		 7691static void
7692OP_M (int bytemode, int sizeflag)
7693{
7967e09e 7694 if (modrm.mod == 3)
75413a22
L		 7695 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
7696 BadOp ();
cc0ec051
AM		 7697 else
7698 OP_E (bytemode, sizeflag);
7699}
7700
7701static void
7702OP_0f07 (int bytemode, int sizeflag)
7703{
7967e09e 7704 if (modrm.mod != 3 || modrm.rm != 0)
cc0ec051
AM		 7705 BadOp ();
7706 else
7707 OP_E (bytemode, sizeflag);
7708}
7709
46e883c5 7710/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
246c51aa 7711 32bit mode and "xchg %rax,%rax" in 64bit mode. */
46e883c5 7712
cc0ec051 7713static void
46e883c5 7714NOP_Fixup1 (int bytemode, int sizeflag)
cc0ec051 7715{
8b38ad71
L		 7716 if ((prefixes & PREFIX_DATA) != 0
7717 || (rex != 0
7718 && rex != 0x48
7719 && address_mode == mode_64bit))
46e883c5
L		 7720 OP_REG (bytemode, sizeflag);
7721 else
7722 strcpy (obuf, "nop");
7723}
7724
7725static void
7726NOP_Fixup2 (int bytemode, int sizeflag)
7727{
8b38ad71
L		 7728 if ((prefixes & PREFIX_DATA) != 0
7729 || (rex != 0
7730 && rex != 0x48
7731 && address_mode == mode_64bit))
46e883c5 7732 OP_IMREG (bytemode, sizeflag);
cc0ec051
AM		 7733}
7734
84037f8c 7735static const char *const Suffix3DNow[] = {
252b5132
RH		 7736/* 00 */ NULL, NULL, NULL, NULL,
7737/* 04 */ NULL, NULL, NULL, NULL,
7738/* 08 */ NULL, NULL, NULL, NULL,
9e525108 7739/* 0C */ "pi2fw", "pi2fd", NULL, NULL,
252b5132
RH		 7740/* 10 */ NULL, NULL, NULL, NULL,
7741/* 14 */ NULL, NULL, NULL, NULL,
7742/* 18 */ NULL, NULL, NULL, NULL,
9e525108 7743/* 1C */ "pf2iw", "pf2id", NULL, NULL,
252b5132
RH		 7744/* 20 */ NULL, NULL, NULL, NULL,
7745/* 24 */ NULL, NULL, NULL, NULL,
7746/* 28 */ NULL, NULL, NULL, NULL,
7747/* 2C */ NULL, NULL, NULL, NULL,
7748/* 30 */ NULL, NULL, NULL, NULL,
7749/* 34 */ NULL, NULL, NULL, NULL,
7750/* 38 */ NULL, NULL, NULL, NULL,
7751/* 3C */ NULL, NULL, NULL, NULL,
7752/* 40 */ NULL, NULL, NULL, NULL,
7753/* 44 */ NULL, NULL, NULL, NULL,
7754/* 48 */ NULL, NULL, NULL, NULL,
7755/* 4C */ NULL, NULL, NULL, NULL,
7756/* 50 */ NULL, NULL, NULL, NULL,
7757/* 54 */ NULL, NULL, NULL, NULL,
7758/* 58 */ NULL, NULL, NULL, NULL,
7759/* 5C */ NULL, NULL, NULL, NULL,
7760/* 60 */ NULL, NULL, NULL, NULL,
7761/* 64 */ NULL, NULL, NULL, NULL,
7762/* 68 */ NULL, NULL, NULL, NULL,
7763/* 6C */ NULL, NULL, NULL, NULL,
7764/* 70 */ NULL, NULL, NULL, NULL,
7765/* 74 */ NULL, NULL, NULL, NULL,
7766/* 78 */ NULL, NULL, NULL, NULL,
7767/* 7C */ NULL, NULL, NULL, NULL,
7768/* 80 */ NULL, NULL, NULL, NULL,
7769/* 84 */ NULL, NULL, NULL, NULL,
9e525108
AM		 7770/* 88 */ NULL, NULL, "pfnacc", NULL,
7771/* 8C */ NULL, NULL, "pfpnacc", NULL,
252b5132
RH		 7772/* 90 */ "pfcmpge", NULL, NULL, NULL,
7773/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
7774/* 98 */ NULL, NULL, "pfsub", NULL,
7775/* 9C */ NULL, NULL, "pfadd", NULL,
7776/* A0 */ "pfcmpgt", NULL, NULL, NULL,
7777/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
7778/* A8 */ NULL, NULL, "pfsubr", NULL,
7779/* AC */ NULL, NULL, "pfacc", NULL,
7780/* B0 */ "pfcmpeq", NULL, NULL, NULL,
9beff690 7781/* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
9e525108 7782/* B8 */ NULL, NULL, NULL, "pswapd",
252b5132
RH		 7783/* BC */ NULL, NULL, NULL, "pavgusb",
7784/* C0 */ NULL, NULL, NULL, NULL,
7785/* C4 */ NULL, NULL, NULL, NULL,
7786/* C8 */ NULL, NULL, NULL, NULL,
7787/* CC */ NULL, NULL, NULL, NULL,
7788/* D0 */ NULL, NULL, NULL, NULL,
7789/* D4 */ NULL, NULL, NULL, NULL,
7790/* D8 */ NULL, NULL, NULL, NULL,
7791/* DC */ NULL, NULL, NULL, NULL,
7792/* E0 */ NULL, NULL, NULL, NULL,
7793/* E4 */ NULL, NULL, NULL, NULL,
7794/* E8 */ NULL, NULL, NULL, NULL,
7795/* EC */ NULL, NULL, NULL, NULL,
7796/* F0 */ NULL, NULL, NULL, NULL,
7797/* F4 */ NULL, NULL, NULL, NULL,
7798/* F8 */ NULL, NULL, NULL, NULL,
7799/* FC */ NULL, NULL, NULL, NULL,
7800};
7801
7802static void
26ca5450 7803OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132
RH		 7804{
7805 const char *mnemonic;
7806
7807 FETCH_DATA (the_info, codep + 1);
7808 /* AMD 3DNow! instructions are specified by an opcode suffix in the
7809 place where an 8-bit immediate would normally go. ie. the last
7810 byte of the instruction. */
6608db57 7811 obufp = obuf + strlen (obuf);
c608c12e 7812 mnemonic = Suffix3DNow[*codep++ & 0xff];
252b5132 7813 if (mnemonic)
2da11e11 7814 oappend (mnemonic);
252b5132
RH		 7815 else
7816 {
7817 /* Since a variable sized modrm/sib chunk is between the start
7818 of the opcode (0x0f0f) and the opcode suffix, we need to do
7819 all the modrm processing first, and don't know until now that
7820 we have a bad opcode. This necessitates some cleaning up. */
ce518a5f
L		 7821 op_out[0][0] = '\0';
7822 op_out[1][0] = '\0';
6608db57 7823 BadOp ();
252b5132
RH		 7824 }
7825}
c608c12e 7826
6608db57 7827static const char *simd_cmp_op[] = {
c608c12e
AM		 7828 "eq",
7829 "lt",
7830 "le",
7831 "unord",
7832 "neq",
7833 "nlt",
7834 "nle",
7835 "ord"
7836};
7837
7838static void
ad19981d 7839CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e
AM		 7840{
7841 unsigned int cmp_type;
7842
7843 FETCH_DATA (the_info, codep + 1);
7844 cmp_type = *codep++ & 0xff;
7845 if (cmp_type < 8)
7846 {
ad19981d
L		 7847 char suffix [3];
7848 char *p = obuf + strlen (obuf) - 2;
7849 suffix[0] = p[0];
7850 suffix[1] = p[1];
7851 suffix[2] = '\0';
7852 sprintf (p, "%s%s", simd_cmp_op[cmp_type], suffix);
c608c12e
AM		 7853 }
7854 else
7855 {
ad19981d
L		 7856 /* We have a reserved extension byte. Output it directly. */
7857 scratchbuf[0] = '$';
7858 print_operand_value (scratchbuf + 1, 1, cmp_type);
7859 oappend (scratchbuf + intel_syntax);
7860 scratchbuf[0] = '\0';
c608c12e
AM		 7861 }
7862}
7863
ca164297 7864static void
b844680a
L		 7865OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
7866 int sizeflag ATTRIBUTE_UNUSED)
7867{
7868 /* mwait %eax,%ecx */
7869 if (!intel_syntax)
7870 {
7871 const char **names = (address_mode == mode_64bit
7872 ? names64 : names32);
7873 strcpy (op_out[0], names[0]);
7874 strcpy (op_out[1], names[1]);
7875 two_source_ops = 1;
7876 }
7877 /* Skip mod/rm byte. */
7878 MODRM_CHECK;
7879 codep++;
7880}
7881
7882static void
7883OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
7884 int sizeflag ATTRIBUTE_UNUSED)
ca164297 7885{
b844680a
L		 7886 /* monitor %eax,%ecx,%edx" */
7887 if (!intel_syntax)
ca164297 7888 {
b844680a 7889 const char **op1_names;
cb712a9e
L		 7890 const char **names = (address_mode == mode_64bit
7891 ? names64 : names32);
1d9f512f 7892
b844680a
L		 7893 if (!(prefixes & PREFIX_ADDR))
7894 op1_names = (address_mode == mode_16bit
7895 ? names16 : names);
ca164297
L		 7896 else
7897 {
b844680a
L		 7898 /* Remove "addr16/addr32". */
7899 addr_prefix = NULL;
7900 op1_names = (address_mode != mode_32bit
7901 ? names32 : names16);
7902 used_prefixes |= PREFIX_ADDR;
ca164297 7903 }
b844680a
L		 7904 strcpy (op_out[0], op1_names[0]);
7905 strcpy (op_out[1], names[1]);
7906 strcpy (op_out[2], names[2]);
7907 two_source_ops = 1;
ca164297 7908 }
b844680a
L		 7909 /* Skip mod/rm byte. */
7910 MODRM_CHECK;
7911 codep++;
30123838
JB		 7912}
7913
6608db57
KH		 7914static void
7915BadOp (void)
2da11e11 7916{
6608db57
KH		 7917 /* Throw away prefixes and 1st. opcode byte. */
7918 codep = insn_codep + 1;
2da11e11
AM		 7919 oappend ("(bad)");
7920}
4cc91dba 7921
35c52694
L		 7922static void
7923REP_Fixup (int bytemode, int sizeflag)
7924{
7925 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
7926 lods and stos. */
35c52694 7927 if (prefixes & PREFIX_REPZ)
b844680a 7928 repz_prefix = "rep ";
35c52694
L		 7929
7930 switch (bytemode)
7931 {
7932 case al_reg:
7933 case eAX_reg:
7934 case indir_dx_reg:
7935 OP_IMREG (bytemode, sizeflag);
7936 break;
7937 case eDI_reg:
7938 OP_ESreg (bytemode, sizeflag);
7939 break;
7940 case eSI_reg:
7941 OP_DSreg (bytemode, sizeflag);
7942 break;
7943 default:
7944 abort ();
7945 break;
7946 }
7947}
f5804c90
L		 7948
7949static void
7950CMPXCHG8B_Fixup (int bytemode, int sizeflag)
7951{
161a04f6
L		 7952 USED_REX (REX_W);
7953 if (rex & REX_W)
f5804c90
L		 7954 {
7955 /* Change cmpxchg8b to cmpxchg16b. */
7956 char *p = obuf + strlen (obuf) - 2;
7957 strcpy (p, "16b");
fb9c77c7 7958 bytemode = o_mode;
f5804c90
L		 7959 }
7960 OP_M (bytemode, sizeflag);
7961}
42903f7f
L		 7962
7963static void
7964XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
7965{
7966 sprintf (scratchbuf, "%%xmm%d", reg);
7967 oappend (scratchbuf + intel_syntax);
7968}
381d071f
L		 7969
7970static void
7971CRC32_Fixup (int bytemode, int sizeflag)
7972{
7973 /* Add proper suffix to "crc32". */
7974 char *p = obuf + strlen (obuf);
7975
7976 switch (bytemode)
7977 {
7978 case b_mode:
20592a94
L		 7979 if (intel_syntax)
7980 break;
7981
381d071f
L		 7982 *p++ = 'b';
7983 break;
7984 case v_mode:
20592a94
L		 7985 if (intel_syntax)
7986 break;
7987
381d071f
L		 7988 USED_REX (REX_W);
7989 if (rex & REX_W)
7990 *p++ = 'q';
9344ff29 7991 else if (sizeflag & DFLAG)
20592a94 7992 *p++ = 'l';
381d071f 7993 else
9344ff29
L		 7994 *p++ = 'w';
7995 used_prefixes |= (prefixes & PREFIX_DATA);
381d071f
L		 7996 break;
7997 default:
7998 oappend (INTERNAL_DISASSEMBLER_ERROR);
7999 break;
8000 }
8001 *p = '\0';
8002
8003 if (modrm.mod == 3)
8004 {
8005 int add;
8006
8007 /* Skip mod/rm byte. */
8008 MODRM_CHECK;
8009 codep++;
8010
8011 USED_REX (REX_B);
8012 add = (rex & REX_B) ? 8 : 0;
8013 if (bytemode == b_mode)
8014 {
8015 USED_REX (0);
8016 if (rex)
8017 oappend (names8rex[modrm.rm + add]);
8018 else
8019 oappend (names8[modrm.rm + add]);
8020 }
8021 else
8022 {
8023 USED_REX (REX_W);
8024 if (rex & REX_W)
8025 oappend (names64[modrm.rm + add]);
8026 else if ((prefixes & PREFIX_DATA))
8027 oappend (names16[modrm.rm + add]);
8028 else
8029 oappend (names32[modrm.rm + add]);
8030 }
8031 }
8032 else
9344ff29 8033 OP_E (bytemode, sizeflag);
381d071f 8034}
85f10a01
MM		 8035
8036/* Print a DREX argument as either a register or memory operation. */
8037static void
8038print_drex_arg (unsigned int reg, int bytemode, int sizeflag)
8039{
8040 if (reg == DREX_REG_UNKNOWN)
8041 BadOp ();
8042
8043 else if (reg != DREX_REG_MEMORY)
8044 {
8045 sprintf (scratchbuf, "%%xmm%d", reg);
8046 oappend (scratchbuf + intel_syntax);
8047 }
8048
8049 else
8050 OP_E_extended (bytemode, sizeflag, 1);
8051}
8052
8053/* SSE5 instructions that have 4 arguments are encoded as:
8054 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>.
8055
8056 The <sub-opcode> byte has 1 bit (0x4) that is combined with 1 bit in
8057 the DREX field (0x8) to determine how the arguments are laid out.
8058 The destination register must be the same register as one of the
8059 inputs, and it is encoded in the DREX byte. No REX prefix is used
8060 for these instructions, since the DREX field contains the 3 extension
8061 bits provided by the REX prefix.
8062
8063 The bytemode argument adds 2 extra bits for passing extra information:
8064 DREX_OC1 -- Set the OC1 bit to indicate dest == 1st arg
8065 DREX_NO_OC0 -- OC0 in DREX is invalid
8066 (but pretend it is set). */
8067
8068static void
8069OP_DREX4 (int flag_bytemode, int sizeflag)
8070{
8071 unsigned int drex_byte;
8072 unsigned int regs[4];
8073 unsigned int modrm_regmem;
8074 unsigned int modrm_reg;
8075 unsigned int drex_reg;
8076 int bytemode;
8077 int rex_save = rex;
8078 int rex_used_save = rex_used;
8079 int has_sib = 0;
8080 int oc1 = (flag_bytemode & DREX_OC1) ? 2 : 0;
8081 int oc0;
8082 int i;
8083
8084 bytemode = flag_bytemode & ~ DREX_MASK;
8085
8086 for (i = 0; i < 4; i++)
8087 regs[i] = DREX_REG_UNKNOWN;
8088
8089 /* Determine if we have a SIB byte in addition to MODRM before the
8090 DREX byte. */
8091 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
8092 && (modrm.mod != 3)
8093 && (modrm.rm == 4))
8094 has_sib = 1;
8095
8096 /* Get the DREX byte. */
8097 FETCH_DATA (the_info, codep + 2 + has_sib);
8098 drex_byte = codep[has_sib+1];
8099 drex_reg = DREX_XMM (drex_byte);
8100 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
8101
8102 /* Is OC0 legal? If not, hardwire oc0 == 1. */
8103 if (flag_bytemode & DREX_NO_OC0)
8104 {
8105 oc0 = 1;
8106 if (DREX_OC0 (drex_byte))
8107 BadOp ();
8108 }
8109 else
8110 oc0 = DREX_OC0 (drex_byte);
8111
8112 if (modrm.mod == 3)
8113 {
8114 /* regmem == register */
8115 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
8116 rex = rex_used = 0;
8117 /* skip modrm/drex since we don't call OP_E_extended */
8118 codep += 2;
8119 }
8120 else
8121 {
8122 /* regmem == memory, fill in appropriate REX bits */
8123 modrm_regmem = DREX_REG_MEMORY;
8124 rex = drex_byte & (REX_B | REX_X | REX_R);
8125 if (rex)
8126 rex |= REX_OPCODE;
8127 rex_used = rex;
8128 }
8129
8130 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
8131 order. */
8132 switch (oc0 + oc1)
8133 {
8134 default:
8135 BadOp ();
8136 return;
8137
8138 case 0:
8139 regs[0] = modrm_regmem;
8140 regs[1] = modrm_reg;
8141 regs[2] = drex_reg;
8142 regs[3] = drex_reg;
8143 break;
8144
8145 case 1:
8146 regs[0] = modrm_reg;
8147 regs[1] = modrm_regmem;
8148 regs[2] = drex_reg;
8149 regs[3] = drex_reg;
8150 break;
8151
8152 case 2:
8153 regs[0] = drex_reg;
8154 regs[1] = modrm_regmem;
8155 regs[2] = modrm_reg;
8156 regs[3] = drex_reg;
8157 break;
8158
8159 case 3:
8160 regs[0] = drex_reg;
8161 regs[1] = modrm_reg;
8162 regs[2] = modrm_regmem;
8163 regs[3] = drex_reg;
8164 break;
8165 }
8166
8167 /* Print out the arguments. */
8168 for (i = 0; i < 4; i++)
8169 {
8170 int j = (intel_syntax) ? 3 - i : i;
8171 if (i > 0)
8172 {
8173 *obufp++ = ',';
8174 *obufp = '\0';
8175 }
8176
8177 print_drex_arg (regs[j], bytemode, sizeflag);
8178 }
8179
8180 rex = rex_save;
8181 rex_used = rex_used_save;
8182}
8183
8184/* SSE5 instructions that have 3 arguments, and are encoded as:
8185 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset> (or)
8186 0f 25 <sub-opcode> <modrm> <optional-sib> <drex> <offset> <cmp-byte>
8187
8188 The DREX field has 1 bit (0x8) to determine how the arguments are
8189 laid out. The destination register is encoded in the DREX byte.
8190 No REX prefix is used for these instructions, since the DREX field
8191 contains the 3 extension bits provided by the REX prefix. */
8192
8193static void
8194OP_DREX3 (int flag_bytemode, int sizeflag)
8195{
8196 unsigned int drex_byte;
8197 unsigned int regs[3];
8198 unsigned int modrm_regmem;
8199 unsigned int modrm_reg;
8200 unsigned int drex_reg;
8201 int bytemode;
8202 int rex_save = rex;
8203 int rex_used_save = rex_used;
8204 int has_sib = 0;
8205 int oc0;
8206 int i;
8207
8208 bytemode = flag_bytemode & ~ DREX_MASK;
8209
8210 for (i = 0; i < 3; i++)
8211 regs[i] = DREX_REG_UNKNOWN;
8212
8213 /* Determine if we have a SIB byte in addition to MODRM before the
8214 DREX byte. */
8215 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
8216 && (modrm.mod != 3)
8217 && (modrm.rm == 4))
8218 has_sib = 1;
8219
8220 /* Get the DREX byte. */
8221 FETCH_DATA (the_info, codep + 2 + has_sib);
8222 drex_byte = codep[has_sib+1];
8223 drex_reg = DREX_XMM (drex_byte);
8224 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
8225
8226 /* Is OC0 legal? If not, hardwire oc0 == 0 */
8227 oc0 = DREX_OC0 (drex_byte);
8228 if ((flag_bytemode & DREX_NO_OC0) && oc0)
8229 BadOp ();
8230
8231 if (modrm.mod == 3)
8232 {
8233 /* regmem == register */
8234 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
8235 rex = rex_used = 0;
8236 /* skip modrm/drex since we don't call OP_E_extended. */
8237 codep += 2;
8238 }
8239 else
8240 {
8241 /* regmem == memory, fill in appropriate REX bits. */
8242 modrm_regmem = DREX_REG_MEMORY;
8243 rex = drex_byte & (REX_B | REX_X | REX_R);
8244 if (rex)
8245 rex |= REX_OPCODE;
8246 rex_used = rex;
8247 }
8248
8249 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
8250 order. */
8251 switch (oc0)
8252 {
8253 default:
8254 BadOp ();
8255 return;
8256
8257 case 0:
8258 regs[0] = modrm_regmem;
8259 regs[1] = modrm_reg;
8260 regs[2] = drex_reg;
8261 break;
8262
8263 case 1:
8264 regs[0] = modrm_reg;
8265 regs[1] = modrm_regmem;
8266 regs[2] = drex_reg;
8267 break;
8268 }
8269
8270 /* Print out the arguments. */
8271 for (i = 0; i < 3; i++)
8272 {
8273 int j = (intel_syntax) ? 2 - i : i;
8274 if (i > 0)
8275 {
8276 *obufp++ = ',';
8277 *obufp = '\0';
8278 }
8279
8280 print_drex_arg (regs[j], bytemode, sizeflag);
8281 }
8282
8283 rex = rex_save;
8284 rex_used = rex_used_save;
8285}
8286
8287/* Emit a floating point comparison for comp<xx> instructions. */
8288
8289static void
8290OP_DREX_FCMP (int bytemode ATTRIBUTE_UNUSED,
8291 int sizeflag ATTRIBUTE_UNUSED)
8292{
8293 unsigned char byte;
8294
8295 static const char *const cmp_test[] = {
8296 "eq",
8297 "lt",
8298 "le",
8299 "unord",
8300 "ne",
8301 "nlt",
8302 "nle",
8303 "ord",
8304 "ueq",
8305 "ult",
8306 "ule",
8307 "false",
8308 "une",
8309 "unlt",
8310 "unle",
8311 "true"
8312 };
8313
8314 FETCH_DATA (the_info, codep + 1);
8315 byte = *codep & 0xff;
8316
8317 if (byte >= ARRAY_SIZE (cmp_test)
8318 || obuf[0] != 'c'
8319 || obuf[1] != 'o'
8320 || obuf[2] != 'm')
8321 {
8322 /* The instruction isn't one we know about, so just append the
8323 extension byte as a numeric value. */
8324 OP_I (b_mode, 0);
8325 }
8326
8327 else
8328 {
8329 sprintf (scratchbuf, "com%s%s", cmp_test[byte], obuf+3);
8330 strcpy (obuf, scratchbuf);
8331 codep++;
8332 }
8333}
8334
8335/* Emit an integer point comparison for pcom<xx> instructions,
8336 rewriting the instruction to have the test inside of it. */
8337
8338static void
8339OP_DREX_ICMP (int bytemode ATTRIBUTE_UNUSED,
8340 int sizeflag ATTRIBUTE_UNUSED)
8341{
8342 unsigned char byte;
8343
8344 static const char *const cmp_test[] = {
8345 "lt",
8346 "le",
8347 "gt",
8348 "ge",
8349 "eq",
8350 "ne",
8351 "false",
8352 "true"
8353 };
8354
8355 FETCH_DATA (the_info, codep + 1);
8356 byte = *codep & 0xff;
8357
8358 if (byte >= ARRAY_SIZE (cmp_test)
8359 || obuf[0] != 'p'
8360 || obuf[1] != 'c'
8361 || obuf[2] != 'o'
8362 || obuf[3] != 'm')
8363 {
8364 /* The instruction isn't one we know about, so just print the
8365 comparison test byte as a numeric value. */
8366 OP_I (b_mode, 0);
8367 }
8368
8369 else
8370 {
8371 sprintf (scratchbuf, "pcom%s%s", cmp_test[byte], obuf+4);
8372 strcpy (obuf, scratchbuf);
8373 codep++;
8374 }
8375}
GDB Binutils - Deliverables
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