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* serial.h (struct serial_ops): Document read_prim to return zero
[deliverable/binutils-gdb.git] / opcodes / i386-dis.c
CommitLineData
252b5132 1/* Print i386 instructions for GDB, the GNU debugger.
060d22b0 2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
9b201bb5 3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
252b5132 4
9b201bb5 5 This file is part of the GNU opcodes library.
20f0a1fc 6
9b201bb5 7 This library is free software; you can redistribute it and/or modify
20f0a1fc 8 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
20f0a1fc 11
9b201bb5
NC		 12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
20f0a1fc
NC		 16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
9b201bb5
NC		 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
20f0a1fc
NC		 22
23/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 July 1988
25 modified by John Hassey (hassey@dg-rtp.dg.com)
26 x86-64 support added by Jan Hubicka (jh@suse.cz)
27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28
29/* The main tables describing the instructions is essentially a copy
30 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
31 Programmers Manual. Usually, there is a capital letter, followed
32 by a small letter. The capital letter tell the addressing mode,
33 and the small letter tells about the operand size. Refer to
34 the Intel manual for details. */
252b5132 35
252b5132 36#include "sysdep.h"
dabbade6 37#include "dis-asm.h"
252b5132 38#include "opintl.h"
0b1cf022 39#include "opcode/i386.h"
85f10a01 40#include "libiberty.h"
252b5132
RH		 41
42#include <setjmp.h>
43
26ca5450
AJ		 44static int fetch_data (struct disassemble_info *, bfd_byte *);
45static void ckprefix (void);
46static const char *prefix_name (int, int);
47static int print_insn (bfd_vma, disassemble_info *);
48static void dofloat (int);
49static void OP_ST (int, int);
50static void OP_STi (int, int);
51static int putop (const char *, int);
52static void oappend (const char *);
53static void append_seg (void);
54static void OP_indirE (int, int);
55static void print_operand_value (char *, int, bfd_vma);
85f10a01 56static void OP_E_extended (int, int, int);
5d669648 57static void print_displacement (char *, bfd_vma);
26ca5450
AJ		 58static void OP_E (int, int);
59static void OP_G (int, int);
60static bfd_vma get64 (void);
61static bfd_signed_vma get32 (void);
62static bfd_signed_vma get32s (void);
63static int get16 (void);
64static void set_op (bfd_vma, int);
b844680a 65static void OP_Skip_MODRM (int, int);
26ca5450
AJ		 66static void OP_REG (int, int);
67static void OP_IMREG (int, int);
68static void OP_I (int, int);
69static void OP_I64 (int, int);
70static void OP_sI (int, int);
71static void OP_J (int, int);
72static void OP_SEG (int, int);
73static void OP_DIR (int, int);
74static void OP_OFF (int, int);
75static void OP_OFF64 (int, int);
76static void ptr_reg (int, int);
77static void OP_ESreg (int, int);
78static void OP_DSreg (int, int);
79static void OP_C (int, int);
80static void OP_D (int, int);
81static void OP_T (int, int);
6f74c397 82static void OP_R (int, int);
26ca5450
AJ		 83static void OP_MMX (int, int);
84static void OP_XMM (int, int);
85static void OP_EM (int, int);
86static void OP_EX (int, int);
4d9567e0
MM		 87static void OP_EMC (int,int);
88static void OP_MXC (int,int);
26ca5450
AJ		 89static void OP_MS (int, int);
90static void OP_XS (int, int);
cc0ec051 91static void OP_M (int, int);
cc0ec051 92static void OP_0f07 (int, int);
b844680a
L		 93static void OP_Monitor (int, int);
94static void OP_Mwait (int, int);
46e883c5
L		 95static void NOP_Fixup1 (int, int);
96static void NOP_Fixup2 (int, int);
26ca5450
AJ		 97static void OP_3DNowSuffix (int, int);
98static void OP_SIMD_Suffix (int, int);
26ca5450 99static void BadOp (void);
35c52694 100static void REP_Fixup (int, int);
f5804c90 101static void CMPXCHG8B_Fixup (int, int);
42903f7f 102static void XMM_Fixup (int, int);
381d071f 103static void CRC32_Fixup (int, int);
85f10a01
MM		 104static void print_drex_arg (unsigned int, int, int);
105static void OP_DREX4 (int, int);
106static void OP_DREX3 (int, int);
107static void OP_DREX_ICMP (int, int);
108static void OP_DREX_FCMP (int, int);
252b5132 109
6608db57 110struct dis_private {
252b5132
RH		 111 /* Points to first byte not fetched. */
112 bfd_byte *max_fetched;
0b1cf022 113 bfd_byte the_buffer[MAX_MNEM_SIZE];
252b5132 114 bfd_vma insn_start;
e396998b 115 int orig_sizeflag;
252b5132
RH		 116 jmp_buf bailout;
117};
118
cb712a9e
L		 119enum address_mode
120{
121 mode_16bit,
122 mode_32bit,
123 mode_64bit
124};
125
126enum address_mode address_mode;
52b15da3 127
5076851f
ILT		 128/* Flags for the prefixes for the current instruction. See below. */
129static int prefixes;
130
52b15da3
JH		 131/* REX prefix the current instruction. See below. */
132static int rex;
133/* Bits of REX we've already used. */
134static int rex_used;
52b15da3
JH		 135/* Mark parts used in the REX prefix. When we are testing for
136 empty prefix (for 8bit register REX extension), just mask it
137 out. Otherwise test for REX bit is excuse for existence of REX
138 only in case value is nonzero. */
139#define USED_REX(value) \
140 { \
141 if (value) \
161a04f6
L		 142 { \
143 if ((rex & value)) \
144 rex_used |= (value) | REX_OPCODE; \
145 } \
52b15da3 146 else \
161a04f6 147 rex_used |= REX_OPCODE; \
52b15da3
JH		 148 }
149
85f10a01
MM		 150/* Special 'registers' for DREX handling */
151#define DREX_REG_UNKNOWN 1000 /* not initialized */
152#define DREX_REG_MEMORY 1001 /* use MODRM/SIB/OFFSET memory */
153
154/* The DREX byte has the following fields:
155 Bits 7-4 -- DREX.Dest, xmm destination register
156 Bit 3 -- DREX.OC0, operand config bit defines operand order
157 Bit 2 -- DREX.R, equivalent to REX_R bit, to extend ModRM register
158 Bit 1 -- DREX.X, equivalent to REX_X bit, to extend SIB index field
159 Bit 0 -- DREX.W, equivalent to REX_B bit, to extend ModRM r/m field,
160 SIB base field, or opcode reg field. */
161#define DREX_XMM(drex) ((drex >> 4) & 0xf)
162#define DREX_OC0(drex) ((drex >> 3) & 0x1)
163
7d421014
ILT		 164/* Flags for prefixes which we somehow handled when printing the
165 current instruction. */
166static int used_prefixes;
167
5076851f
ILT		 168/* Flags stored in PREFIXES. */
169#define PREFIX_REPZ 1
170#define PREFIX_REPNZ 2
171#define PREFIX_LOCK 4
172#define PREFIX_CS 8
173#define PREFIX_SS 0x10
174#define PREFIX_DS 0x20
175#define PREFIX_ES 0x40
176#define PREFIX_FS 0x80
177#define PREFIX_GS 0x100
178#define PREFIX_DATA 0x200
179#define PREFIX_ADDR 0x400
180#define PREFIX_FWAIT 0x800
181
252b5132
RH		 182/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
183 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
184 on error. */
185#define FETCH_DATA(info, addr) \
6608db57 186 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
252b5132
RH		 187 ? 1 : fetch_data ((info), (addr)))
188
189static int
26ca5450 190fetch_data (struct disassemble_info *info, bfd_byte *addr)
252b5132
RH		 191{
192 int status;
6608db57 193 struct dis_private *priv = (struct dis_private *) info->private_data;
252b5132
RH		 194 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
195
0b1cf022 196 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
272c9217
JB		 197 status = (*info->read_memory_func) (start,
198 priv->max_fetched,
199 addr - priv->max_fetched,
200 info);
201 else
202 status = -1;
252b5132
RH		 203 if (status != 0)
204 {
7d421014 205 /* If we did manage to read at least one byte, then
db6eb5be
AM		 206 print_insn_i386 will do something sensible. Otherwise, print
207 an error. We do that here because this is where we know
208 STATUS. */
7d421014 209 if (priv->max_fetched == priv->the_buffer)
5076851f 210 (*info->memory_error_func) (status, start, info);
252b5132
RH		 211 longjmp (priv->bailout, 1);
212 }
213 else
214 priv->max_fetched = addr;
215 return 1;
216}
217
ce518a5f
L		 218#define XX { NULL, 0 }
219
220#define Eb { OP_E, b_mode }
221#define Ev { OP_E, v_mode }
222#define Ed { OP_E, d_mode }
223#define Edq { OP_E, dq_mode }
224#define Edqw { OP_E, dqw_mode }
42903f7f
L		 225#define Edqb { OP_E, dqb_mode }
226#define Edqd { OP_E, dqd_mode }
09335d05 227#define Eq { OP_E, q_mode }
ce518a5f
L		 228#define indirEv { OP_indirE, stack_v_mode }
229#define indirEp { OP_indirE, f_mode }
230#define stackEv { OP_E, stack_v_mode }
231#define Em { OP_E, m_mode }
232#define Ew { OP_E, w_mode }
233#define M { OP_M, 0 } /* lea, lgdt, etc. */
234#define Ma { OP_M, v_mode }
b844680a 235#define Mb { OP_M, b_mode }
d9a5e5e5 236#define Md { OP_M, d_mode }
ce518a5f
L		 237#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
238#define Mq { OP_M, q_mode }
239#define Gb { OP_G, b_mode }
240#define Gv { OP_G, v_mode }
241#define Gd { OP_G, d_mode }
242#define Gdq { OP_G, dq_mode }
243#define Gm { OP_G, m_mode }
244#define Gw { OP_G, w_mode }
6f74c397
L		 245#define Rd { OP_R, d_mode }
246#define Rm { OP_R, m_mode }
ce518a5f
L		 247#define Ib { OP_I, b_mode }
248#define sIb { OP_sI, b_mode } /* sign extened byte */
249#define Iv { OP_I, v_mode }
250#define Iq { OP_I, q_mode }
251#define Iv64 { OP_I64, v_mode }
252#define Iw { OP_I, w_mode }
253#define I1 { OP_I, const_1_mode }
254#define Jb { OP_J, b_mode }
255#define Jv { OP_J, v_mode }
256#define Cm { OP_C, m_mode }
257#define Dm { OP_D, m_mode }
258#define Td { OP_T, d_mode }
b844680a 259#define Skip_MODRM { OP_Skip_MODRM, 0 }
ce518a5f
L		 260
261#define RMeAX { OP_REG, eAX_reg }
262#define RMeBX { OP_REG, eBX_reg }
263#define RMeCX { OP_REG, eCX_reg }
264#define RMeDX { OP_REG, eDX_reg }
265#define RMeSP { OP_REG, eSP_reg }
266#define RMeBP { OP_REG, eBP_reg }
267#define RMeSI { OP_REG, eSI_reg }
268#define RMeDI { OP_REG, eDI_reg }
269#define RMrAX { OP_REG, rAX_reg }
270#define RMrBX { OP_REG, rBX_reg }
271#define RMrCX { OP_REG, rCX_reg }
272#define RMrDX { OP_REG, rDX_reg }
273#define RMrSP { OP_REG, rSP_reg }
274#define RMrBP { OP_REG, rBP_reg }
275#define RMrSI { OP_REG, rSI_reg }
276#define RMrDI { OP_REG, rDI_reg }
277#define RMAL { OP_REG, al_reg }
278#define RMAL { OP_REG, al_reg }
279#define RMCL { OP_REG, cl_reg }
280#define RMDL { OP_REG, dl_reg }
281#define RMBL { OP_REG, bl_reg }
282#define RMAH { OP_REG, ah_reg }
283#define RMCH { OP_REG, ch_reg }
284#define RMDH { OP_REG, dh_reg }
285#define RMBH { OP_REG, bh_reg }
286#define RMAX { OP_REG, ax_reg }
287#define RMDX { OP_REG, dx_reg }
288
289#define eAX { OP_IMREG, eAX_reg }
290#define eBX { OP_IMREG, eBX_reg }
291#define eCX { OP_IMREG, eCX_reg }
292#define eDX { OP_IMREG, eDX_reg }
293#define eSP { OP_IMREG, eSP_reg }
294#define eBP { OP_IMREG, eBP_reg }
295#define eSI { OP_IMREG, eSI_reg }
296#define eDI { OP_IMREG, eDI_reg }
297#define AL { OP_IMREG, al_reg }
298#define CL { OP_IMREG, cl_reg }
299#define DL { OP_IMREG, dl_reg }
300#define BL { OP_IMREG, bl_reg }
301#define AH { OP_IMREG, ah_reg }
302#define CH { OP_IMREG, ch_reg }
303#define DH { OP_IMREG, dh_reg }
304#define BH { OP_IMREG, bh_reg }
305#define AX { OP_IMREG, ax_reg }
306#define DX { OP_IMREG, dx_reg }
307#define zAX { OP_IMREG, z_mode_ax_reg }
308#define indirDX { OP_IMREG, indir_dx_reg }
309
310#define Sw { OP_SEG, w_mode }
311#define Sv { OP_SEG, v_mode }
312#define Ap { OP_DIR, 0 }
313#define Ob { OP_OFF64, b_mode }
314#define Ov { OP_OFF64, v_mode }
315#define Xb { OP_DSreg, eSI_reg }
316#define Xv { OP_DSreg, eSI_reg }
317#define Xz { OP_DSreg, eSI_reg }
318#define Yb { OP_ESreg, eDI_reg }
319#define Yv { OP_ESreg, eDI_reg }
320#define DSBX { OP_DSreg, eBX_reg }
321
322#define es { OP_REG, es_reg }
323#define ss { OP_REG, ss_reg }
324#define cs { OP_REG, cs_reg }
325#define ds { OP_REG, ds_reg }
326#define fs { OP_REG, fs_reg }
327#define gs { OP_REG, gs_reg }
328
329#define MX { OP_MMX, 0 }
330#define XM { OP_XMM, 0 }
331#define EM { OP_EM, v_mode }
09a2c6cf 332#define EMd { OP_EM, d_mode }
14051056 333#define EMx { OP_EM, x_mode }
8976381e 334#define EXw { OP_EX, w_mode }
09a2c6cf
L		 335#define EXd { OP_EX, d_mode }
336#define EXq { OP_EX, q_mode }
337#define EXx { OP_EX, x_mode }
ce518a5f
L		 338#define MS { OP_MS, v_mode }
339#define XS { OP_XS, v_mode }
09335d05 340#define EMCq { OP_EMC, q_mode }
ce518a5f 341#define MXC { OP_MXC, 0 }
ce518a5f
L		 342#define OPSUF { OP_3DNowSuffix, 0 }
343#define OPSIMD { OP_SIMD_Suffix, 0 }
42903f7f 344#define XMM0 { XMM_Fixup, 0 }
252b5132 345
35c52694 346/* Used handle "rep" prefix for string instructions. */
ce518a5f
L		 347#define Xbr { REP_Fixup, eSI_reg }
348#define Xvr { REP_Fixup, eSI_reg }
349#define Ybr { REP_Fixup, eDI_reg }
350#define Yvr { REP_Fixup, eDI_reg }
351#define Yzr { REP_Fixup, eDI_reg }
352#define indirDXr { REP_Fixup, indir_dx_reg }
353#define ALr { REP_Fixup, al_reg }
354#define eAXr { REP_Fixup, eAX_reg }
355
356#define cond_jump_flag { NULL, cond_jump_mode }
357#define loop_jcxz_flag { NULL, loop_jcxz_mode }
3ffd33cf 358
252b5132 359/* bits in sizeflag */
252b5132 360#define SUFFIX_ALWAYS 4
252b5132
RH		 361#define AFLAG 2
362#define DFLAG 1
363
d55ee72f
L		 364/* byte operand */
365#define b_mode 1
366/* operand size depends on prefixes */
630c2cc5 367#define v_mode (b_mode + 1)
d55ee72f
L		 368/* word operand */
369#define w_mode (v_mode + 1)
370/* double word operand */
371#define d_mode (w_mode + 1)
372/* quad word operand */
373#define q_mode (d_mode + 1)
374/* ten-byte operand */
375#define t_mode (q_mode + 1)
376/* 16-byte XMM operand */
377#define x_mode (t_mode + 1)
378/* d_mode in 32bit, q_mode in 64bit mode. */
379#define m_mode (x_mode + 1)
380#define cond_jump_mode (m_mode + 1)
381#define loop_jcxz_mode (cond_jump_mode + 1)
382/* operand size depends on REX prefixes. */
383#define dq_mode (loop_jcxz_mode + 1)
384/* registers like dq_mode, memory like w_mode. */
385#define dqw_mode (dq_mode + 1)
386/* 4- or 6-byte pointer operand */
387#define f_mode (dqw_mode + 1)
388#define const_1_mode (f_mode + 1)
389/* v_mode for stack-related opcodes. */
390#define stack_v_mode (const_1_mode + 1)
391/* non-quad operand size depends on prefixes */
392#define z_mode (stack_v_mode + 1)
393/* 16-byte operand */
394#define o_mode (z_mode + 1)
395/* registers like dq_mode, memory like b_mode. */
396#define dqb_mode (o_mode + 1)
397/* registers like dq_mode, memory like d_mode. */
398#define dqd_mode (dqb_mode + 1)
399
400#define es_reg (dqd_mode + 1)
401#define cs_reg (es_reg + 1)
402#define ss_reg (cs_reg + 1)
403#define ds_reg (ss_reg + 1)
404#define fs_reg (ds_reg + 1)
405#define gs_reg (fs_reg + 1)
406
407#define eAX_reg (gs_reg + 1)
408#define eCX_reg (eAX_reg + 1)
409#define eDX_reg (eCX_reg + 1)
410#define eBX_reg (eDX_reg + 1)
411#define eSP_reg (eBX_reg + 1)
412#define eBP_reg (eSP_reg + 1)
413#define eSI_reg (eBP_reg + 1)
414#define eDI_reg (eSI_reg + 1)
415
416#define al_reg (eDI_reg + 1)
417#define cl_reg (al_reg + 1)
418#define dl_reg (cl_reg + 1)
419#define bl_reg (dl_reg + 1)
420#define ah_reg (bl_reg + 1)
421#define ch_reg (ah_reg + 1)
422#define dh_reg (ch_reg + 1)
423#define bh_reg (dh_reg + 1)
424
425#define ax_reg (bh_reg + 1)
426#define cx_reg (ax_reg + 1)
427#define dx_reg (cx_reg + 1)
428#define bx_reg (dx_reg + 1)
429#define sp_reg (bx_reg + 1)
430#define bp_reg (sp_reg + 1)
431#define si_reg (bp_reg + 1)
432#define di_reg (si_reg + 1)
433
434#define rAX_reg (di_reg + 1)
435#define rCX_reg (rAX_reg + 1)
436#define rDX_reg (rCX_reg + 1)
437#define rBX_reg (rDX_reg + 1)
438#define rSP_reg (rBX_reg + 1)
439#define rBP_reg (rSP_reg + 1)
440#define rSI_reg (rBP_reg + 1)
441#define rDI_reg (rSI_reg + 1)
442
443#define z_mode_ax_reg (rDI_reg + 1)
444#define indir_dx_reg (z_mode_ax_reg + 1)
445
446#define MAX_BYTEMODE indir_dx_reg
447
448/* Flags that are OR'ed into the bytemode field to pass extra
449 information. */
450#define DREX_OC1 0x10000 /* OC1 bit set */
451#define DREX_NO_OC0 0x20000 /* OC0 bit not used */
452#define DREX_MASK 0x40000 /* mask to delete */
453
454#if MAX_BYTEMODE >= DREX_OC1
455#error MAX_BYTEMODE must be less than DREX_OC1
456#endif
252b5132 457
6439fc28 458#define FLOATCODE 1
1ceb70f8
L		 459#define USE_REG_TABLE 2
460#define USE_MOD_TABLE 3
461#define USE_RM_TABLE 4
462#define USE_PREFIX_TABLE 5
463#define USE_X86_64_TABLE 6
464#define USE_3BYTE_TABLE 7
6439fc28 465
1ceb70f8 466#define FLOAT NULL, { { NULL, FLOATCODE } }
4efba78c 467
4e7d34a6 468#define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
1ceb70f8
L		 469#define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
470#define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
471#define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
472#define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
4e7d34a6
L		 473#define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
474#define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
1ceb70f8
L		 475
476#define REG_80 0
477#define REG_81 (REG_80 + 1)
478#define REG_82 (REG_81 + 1)
479#define REG_8F (REG_82 + 1)
480#define REG_C0 (REG_8F + 1)
481#define REG_C1 (REG_C0 + 1)
482#define REG_C6 (REG_C1 + 1)
483#define REG_C7 (REG_C6 + 1)
484#define REG_D0 (REG_C7 + 1)
485#define REG_D1 (REG_D0 + 1)
486#define REG_D2 (REG_D1 + 1)
487#define REG_D3 (REG_D2 + 1)
488#define REG_F6 (REG_D3 + 1)
489#define REG_F7 (REG_F6 + 1)
490#define REG_FE (REG_F7 + 1)
491#define REG_FF (REG_FE + 1)
492#define REG_0F00 (REG_FF + 1)
493#define REG_0F01 (REG_0F00 + 1)
494#define REG_0F0E (REG_0F01 + 1)
495#define REG_0F18 (REG_0F0E + 1)
496#define REG_0F71 (REG_0F18 + 1)
497#define REG_0F72 (REG_0F71 + 1)
498#define REG_0F73 (REG_0F72 + 1)
499#define REG_0FA6 (REG_0F73 + 1)
500#define REG_0FA7 (REG_0FA6 + 1)
501#define REG_0FAE (REG_0FA7 + 1)
502#define REG_0FBA (REG_0FAE + 1)
503#define REG_0FC7 (REG_0FBA + 1)
504
505#define MOD_8D 0
506#define MOD_0F13 (MOD_8D + 1)
507#define MOD_0F17 (MOD_0F13 + 1)
508#define MOD_0F20 (MOD_0F17 + 1)
509#define MOD_0F21 (MOD_0F20 + 1)
510#define MOD_0F22 (MOD_0F21 + 1)
511#define MOD_0F23 (MOD_0F22 + 1)
512#define MOD_0F24 (MOD_0F23 + 1)
513#define MOD_0F26 (MOD_0F24 + 1)
514#define MOD_0FB2 (MOD_0F26 + 1)
515#define MOD_0FB4 (MOD_0FB2 + 1)
516#define MOD_0FB5 (MOD_0FB4 + 1)
517#define MOD_0F01_REG_0 (MOD_0FB5 + 1)
518#define MOD_0F01_REG_1 (MOD_0F01_REG_0 + 1)
519#define MOD_0F01_REG_2 (MOD_0F01_REG_1 + 1)
520#define MOD_0F01_REG_3 (MOD_0F01_REG_2 + 1)
521#define MOD_0F01_REG_7 (MOD_0F01_REG_3 + 1)
522#define MOD_0F18_REG_0 (MOD_0F01_REG_7 + 1)
523#define MOD_0F18_REG_1 (MOD_0F18_REG_0 + 1)
524#define MOD_0F18_REG_2 (MOD_0F18_REG_1 + 1)
525#define MOD_0F18_REG_3 (MOD_0F18_REG_2 + 1)
526#define MOD_0F71_REG_2 (MOD_0F18_REG_3 + 1)
527#define MOD_0F71_REG_4 (MOD_0F71_REG_2 + 1)
528#define MOD_0F71_REG_6 (MOD_0F71_REG_4 + 1)
529#define MOD_0F72_REG_2 (MOD_0F71_REG_6 + 1)
530#define MOD_0F72_REG_4 (MOD_0F72_REG_2 + 1)
531#define MOD_0F72_REG_6 (MOD_0F72_REG_4 + 1)
532#define MOD_0F73_REG_2 (MOD_0F72_REG_6 + 1)
533#define MOD_0F73_REG_3 (MOD_0F73_REG_2 + 1)
534#define MOD_0F73_REG_6 (MOD_0F73_REG_3 + 1)
535#define MOD_0F73_REG_7 (MOD_0F73_REG_6 + 1)
536#define MOD_0FAE_REG_0 (MOD_0F73_REG_7 + 1)
537#define MOD_0FAE_REG_1 (MOD_0FAE_REG_0 + 1)
538#define MOD_0FAE_REG_2 (MOD_0FAE_REG_1 + 1)
539#define MOD_0FAE_REG_3 (MOD_0FAE_REG_2 + 1)
540#define MOD_0FAE_REG_5 (MOD_0FAE_REG_3 + 1)
541#define MOD_0FAE_REG_6 (MOD_0FAE_REG_5 + 1)
542#define MOD_0FAE_REG_7 (MOD_0FAE_REG_6 + 1)
543#define MOD_0FC7_REG_6 (MOD_0FAE_REG_7 + 1)
544#define MOD_0FC7_REG_7 (MOD_0FC7_REG_6 + 1)
545#define MOD_0F12_PREFIX_0 (MOD_0FC7_REG_7 + 1)
546#define MOD_0F16_PREFIX_0 (MOD_0F12_PREFIX_0 + 1)
547#define MOD_0FF0_PREFIX_3 (MOD_0F16_PREFIX_0 + 1)
548#define MOD_62_32BIT (MOD_0FF0_PREFIX_3 + 1)
549#define MOD_C4_32BIT (MOD_62_32BIT + 1)
550#define MOD_C5_32BIT (MOD_C4_32BIT + 1)
551
552#define RM_0F01_REG_0 0
553#define RM_0F01_REG_1 (RM_0F01_REG_0 + 1)
554#define RM_0F01_REG_3 (RM_0F01_REG_1 + 1)
555#define RM_0F01_REG_7 (RM_0F01_REG_3 + 1)
556#define RM_0FAE_REG_5 (RM_0F01_REG_7 + 1)
557#define RM_0FAE_REG_6 (RM_0FAE_REG_5 + 1)
558#define RM_0FAE_REG_7 (RM_0FAE_REG_6 + 1)
559
560#define PREFIX_90 0
561#define PREFIX_0F10 (PREFIX_90 + 1)
562#define PREFIX_0F11 (PREFIX_0F10 + 1)
563#define PREFIX_0F12 (PREFIX_0F11 + 1)
564#define PREFIX_0F16 (PREFIX_0F12 + 1)
565#define PREFIX_0F2A (PREFIX_0F16 + 1)
566#define PREFIX_0F2B (PREFIX_0F2A + 1)
567#define PREFIX_0F2C (PREFIX_0F2B + 1)
568#define PREFIX_0F2D (PREFIX_0F2C + 1)
569#define PREFIX_0F2E (PREFIX_0F2D + 1)
570#define PREFIX_0F2F (PREFIX_0F2E + 1)
571#define PREFIX_0F51 (PREFIX_0F2F + 1)
572#define PREFIX_0F52 (PREFIX_0F51 + 1)
573#define PREFIX_0F53 (PREFIX_0F52 + 1)
574#define PREFIX_0F58 (PREFIX_0F53 + 1)
575#define PREFIX_0F59 (PREFIX_0F58 + 1)
576#define PREFIX_0F5A (PREFIX_0F59 + 1)
577#define PREFIX_0F5B (PREFIX_0F5A + 1)
578#define PREFIX_0F5C (PREFIX_0F5B + 1)
579#define PREFIX_0F5D (PREFIX_0F5C + 1)
580#define PREFIX_0F5E (PREFIX_0F5D + 1)
581#define PREFIX_0F5F (PREFIX_0F5E + 1)
582#define PREFIX_0F60 (PREFIX_0F5F + 1)
583#define PREFIX_0F61 (PREFIX_0F60 + 1)
584#define PREFIX_0F62 (PREFIX_0F61 + 1)
585#define PREFIX_0F6C (PREFIX_0F62 + 1)
586#define PREFIX_0F6D (PREFIX_0F6C + 1)
587#define PREFIX_0F6F (PREFIX_0F6D + 1)
588#define PREFIX_0F70 (PREFIX_0F6F + 1)
589#define PREFIX_0F78 (PREFIX_0F70 + 1)
590#define PREFIX_0F79 (PREFIX_0F78 + 1)
591#define PREFIX_0F7C (PREFIX_0F79 + 1)
592#define PREFIX_0F7D (PREFIX_0F7C + 1)
593#define PREFIX_0F7E (PREFIX_0F7D + 1)
594#define PREFIX_0F7F (PREFIX_0F7E + 1)
595#define PREFIX_0FB8 (PREFIX_0F7F + 1)
596#define PREFIX_0FBD (PREFIX_0FB8 + 1)
597#define PREFIX_0FC2 (PREFIX_0FBD + 1)
598#define PREFIX_0FD0 (PREFIX_0FC2 + 1)
599#define PREFIX_0FD6 (PREFIX_0FD0 + 1)
600#define PREFIX_0FE6 (PREFIX_0FD6 + 1)
601#define PREFIX_0FE7 (PREFIX_0FE6 + 1)
602#define PREFIX_0FF0 (PREFIX_0FE7 + 1)
603#define PREFIX_0FF7 (PREFIX_0FF0 + 1)
604#define PREFIX_0F3810 (PREFIX_0FF7 + 1)
605#define PREFIX_0F3814 (PREFIX_0F3810 + 1)
606#define PREFIX_0F3815 (PREFIX_0F3814 + 1)
607#define PREFIX_0F3817 (PREFIX_0F3815 + 1)
608#define PREFIX_0F3820 (PREFIX_0F3817 + 1)
609#define PREFIX_0F3821 (PREFIX_0F3820 + 1)
610#define PREFIX_0F3822 (PREFIX_0F3821 + 1)
611#define PREFIX_0F3823 (PREFIX_0F3822 + 1)
612#define PREFIX_0F3824 (PREFIX_0F3823 + 1)
613#define PREFIX_0F3825 (PREFIX_0F3824 + 1)
614#define PREFIX_0F3828 (PREFIX_0F3825 + 1)
615#define PREFIX_0F3829 (PREFIX_0F3828 + 1)
616#define PREFIX_0F382A (PREFIX_0F3829 + 1)
617#define PREFIX_0F382B (PREFIX_0F382A + 1)
618#define PREFIX_0F3830 (PREFIX_0F382B + 1)
619#define PREFIX_0F3831 (PREFIX_0F3830 + 1)
620#define PREFIX_0F3832 (PREFIX_0F3831 + 1)
621#define PREFIX_0F3833 (PREFIX_0F3832 + 1)
622#define PREFIX_0F3834 (PREFIX_0F3833 + 1)
623#define PREFIX_0F3835 (PREFIX_0F3834 + 1)
624#define PREFIX_0F3837 (PREFIX_0F3835 + 1)
625#define PREFIX_0F3838 (PREFIX_0F3837 + 1)
626#define PREFIX_0F3839 (PREFIX_0F3838 + 1)
627#define PREFIX_0F383A (PREFIX_0F3839 + 1)
628#define PREFIX_0F383B (PREFIX_0F383A + 1)
629#define PREFIX_0F383C (PREFIX_0F383B + 1)
630#define PREFIX_0F383D (PREFIX_0F383C + 1)
631#define PREFIX_0F383E (PREFIX_0F383D + 1)
632#define PREFIX_0F383F (PREFIX_0F383E + 1)
633#define PREFIX_0F3840 (PREFIX_0F383F + 1)
634#define PREFIX_0F3841 (PREFIX_0F3840 + 1)
635#define PREFIX_0F38F0 (PREFIX_0F3841 + 1)
636#define PREFIX_0F38F1 (PREFIX_0F38F0 + 1)
637#define PREFIX_0F3A08 (PREFIX_0F38F1 + 1)
638#define PREFIX_0F3A09 (PREFIX_0F3A08 + 1)
639#define PREFIX_0F3A0A (PREFIX_0F3A09 + 1)
640#define PREFIX_0F3A0B (PREFIX_0F3A0A + 1)
641#define PREFIX_0F3A0C (PREFIX_0F3A0B + 1)
642#define PREFIX_0F3A0D (PREFIX_0F3A0C + 1)
643#define PREFIX_0F3A0E (PREFIX_0F3A0D + 1)
644#define PREFIX_0F3A14 (PREFIX_0F3A0E + 1)
645#define PREFIX_0F3A15 (PREFIX_0F3A14 + 1)
646#define PREFIX_0F3A16 (PREFIX_0F3A15 + 1)
647#define PREFIX_0F3A17 (PREFIX_0F3A16 + 1)
648#define PREFIX_0F3A20 (PREFIX_0F3A17 + 1)
649#define PREFIX_0F3A21 (PREFIX_0F3A20 + 1)
650#define PREFIX_0F3A22 (PREFIX_0F3A21 + 1)
651#define PREFIX_0F3A40 (PREFIX_0F3A22 + 1)
652#define PREFIX_0F3A41 (PREFIX_0F3A40 + 1)
653#define PREFIX_0F3A42 (PREFIX_0F3A41 + 1)
654#define PREFIX_0F3A60 (PREFIX_0F3A42 + 1)
655#define PREFIX_0F3A61 (PREFIX_0F3A60 + 1)
656#define PREFIX_0F3A62 (PREFIX_0F3A61 + 1)
657#define PREFIX_0F3A63 (PREFIX_0F3A62 + 1)
658#define PREFIX_0F73_REG_3 (PREFIX_0F3A63 + 1)
659#define PREFIX_0F73_REG_7 (PREFIX_0F73_REG_3 + 1)
660#define PREFIX_0FC7_REG_6 (PREFIX_0F73_REG_7 + 1)
4e7d34a6
L		 661
662#define X86_64_06 0
663#define X86_64_07 (X86_64_06 + 1)
664#define X86_64_0D (X86_64_07 + 1)
665#define X86_64_16 (X86_64_0D + 1)
666#define X86_64_17 (X86_64_16 + 1)
667#define X86_64_1E (X86_64_17 + 1)
668#define X86_64_1F (X86_64_1E + 1)
669#define X86_64_27 (X86_64_1F + 1)
670#define X86_64_2F (X86_64_27 + 1)
671#define X86_64_37 (X86_64_2F + 1)
672#define X86_64_3F (X86_64_37 + 1)
673#define X86_64_60 (X86_64_3F + 1)
674#define X86_64_61 (X86_64_60 + 1)
675#define X86_64_62 (X86_64_61 + 1)
676#define X86_64_63 (X86_64_62 + 1)
677#define X86_64_6D (X86_64_63 + 1)
678#define X86_64_6F (X86_64_6D + 1)
679#define X86_64_9A (X86_64_6F + 1)
680#define X86_64_C4 (X86_64_9A + 1)
681#define X86_64_C5 (X86_64_C4 + 1)
682#define X86_64_CE (X86_64_C5 + 1)
683#define X86_64_D4 (X86_64_CE + 1)
684#define X86_64_D5 (X86_64_D4 + 1)
685#define X86_64_EA (X86_64_D5 + 1)
686#define X86_64_0F01_REG_0 (X86_64_EA + 1)
687#define X86_64_0F01_REG_1 (X86_64_0F01_REG_0 + 1)
688#define X86_64_0F01_REG_2 (X86_64_0F01_REG_1 + 1)
689#define X86_64_0F01_REG_3 (X86_64_0F01_REG_2 + 1)
690
691#define THREE_BYTE_0F24 0
692#define THREE_BYTE_0F25 (THREE_BYTE_0F24 + 1)
693#define THREE_BYTE_0F38 (THREE_BYTE_0F25 + 1)
694#define THREE_BYTE_0F3A (THREE_BYTE_0F38 + 1)
695#define THREE_BYTE_0F7A (THREE_BYTE_0F3A + 1)
89b66d55 696#define THREE_BYTE_0F7B (THREE_BYTE_0F7A + 1)
4e7d34a6 697
26ca5450 698typedef void (*op_rtn) (int bytemode, int sizeflag);
252b5132
RH		 699
700struct dis386 {
2da11e11 701 const char *name;
ce518a5f
L		 702 struct
703 {
704 op_rtn rtn;
705 int bytemode;
706 } op[MAX_OPERANDS];
252b5132
RH		 707};
708
709/* Upper case letters in the instruction names here are macros.
710 'A' => print 'b' if no register operands or suffix_always is true
711 'B' => print 'b' if suffix_always is true
9306ca4a
JB		 712 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
713 . size prefix
ed7841b3
JB		 714 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
715 . suffix_always is true
252b5132 716 'E' => print 'e' if 32-bit form of jcxz
3ffd33cf 717 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
52fd6d94 718 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
5dd0794d 719 'H' => print ",pt" or ",pn" branch hint
9306ca4a
JB		 720 'I' => honor following macro letter even in Intel mode (implemented only
721 . for some of the macro letters)
722 'J' => print 'l'
42903f7f 723 'K' => print 'd' or 'q' if rex prefix is present.
252b5132
RH		 724 'L' => print 'l' if suffix_always is true
725 'N' => print 'n' if instruction has no wait "prefix"
a35ca55a 726 'O' => print 'd' or 'o' (or 'q' in Intel mode)
52b15da3 727 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
e396998b
AM		 728 . or suffix_always is true. print 'q' if rex prefix is present.
729 'Q' => print 'w', 'l' or 'q' if no register operands or suffix_always
730 . is true
a35ca55a 731 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
52b15da3 732 'S' => print 'w', 'l' or 'q' if suffix_always is true
6439fc28
AM		 733 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
734 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1a114b12 735 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
a35ca55a 736 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
9306ca4a 737 'X' => print 's', 'd' depending on data16 prefix (for XMM)
8a72226a
L		 738 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
739 suffix_always is true.
6dd5059a 740 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
52b15da3 741
6439fc28
AM		 742 Many of the above letters print nothing in Intel mode. See "putop"
743 for the details.
52b15da3 744
6439fc28 745 Braces '{' and '}', and vertical bars '|', indicate alternative
7c52e0e8 746 mnemonic strings for AT&T and Intel. */
252b5132 747
6439fc28 748static const struct dis386 dis386[] = {
252b5132 749 /* 00 */
ce518a5f
L		 750 { "addB", { Eb, Gb } },
751 { "addS", { Ev, Gv } },
752 { "addB", { Gb, Eb } },
753 { "addS", { Gv, Ev } },
754 { "addB", { AL, Ib } },
755 { "addS", { eAX, Iv } },
4e7d34a6
L		 756 { X86_64_TABLE (X86_64_06) },
757 { X86_64_TABLE (X86_64_07) },
252b5132 758 /* 08 */
ce518a5f
L		 759 { "orB", { Eb, Gb } },
760 { "orS", { Ev, Gv } },
761 { "orB", { Gb, Eb } },
762 { "orS", { Gv, Ev } },
763 { "orB", { AL, Ib } },
764 { "orS", { eAX, Iv } },
4e7d34a6 765 { X86_64_TABLE (X86_64_0D) },
ce518a5f 766 { "(bad)", { XX } }, /* 0x0f extended opcode escape */
252b5132 767 /* 10 */
ce518a5f
L		 768 { "adcB", { Eb, Gb } },
769 { "adcS", { Ev, Gv } },
770 { "adcB", { Gb, Eb } },
771 { "adcS", { Gv, Ev } },
772 { "adcB", { AL, Ib } },
773 { "adcS", { eAX, Iv } },
4e7d34a6
L		 774 { X86_64_TABLE (X86_64_16) },
775 { X86_64_TABLE (X86_64_17) },
252b5132 776 /* 18 */
ce518a5f
L		 777 { "sbbB", { Eb, Gb } },
778 { "sbbS", { Ev, Gv } },
779 { "sbbB", { Gb, Eb } },
780 { "sbbS", { Gv, Ev } },
781 { "sbbB", { AL, Ib } },
782 { "sbbS", { eAX, Iv } },
4e7d34a6
L		 783 { X86_64_TABLE (X86_64_1E) },
784 { X86_64_TABLE (X86_64_1F) },
252b5132 785 /* 20 */
ce518a5f
L		 786 { "andB", { Eb, Gb } },
787 { "andS", { Ev, Gv } },
788 { "andB", { Gb, Eb } },
789 { "andS", { Gv, Ev } },
790 { "andB", { AL, Ib } },
791 { "andS", { eAX, Iv } },
792 { "(bad)", { XX } }, /* SEG ES prefix */
4e7d34a6 793 { X86_64_TABLE (X86_64_27) },
252b5132 794 /* 28 */
ce518a5f
L		 795 { "subB", { Eb, Gb } },
796 { "subS", { Ev, Gv } },
797 { "subB", { Gb, Eb } },
798 { "subS", { Gv, Ev } },
799 { "subB", { AL, Ib } },
800 { "subS", { eAX, Iv } },
801 { "(bad)", { XX } }, /* SEG CS prefix */
4e7d34a6 802 { X86_64_TABLE (X86_64_2F) },
252b5132 803 /* 30 */
ce518a5f
L		 804 { "xorB", { Eb, Gb } },
805 { "xorS", { Ev, Gv } },
806 { "xorB", { Gb, Eb } },
807 { "xorS", { Gv, Ev } },
808 { "xorB", { AL, Ib } },
809 { "xorS", { eAX, Iv } },
810 { "(bad)", { XX } }, /* SEG SS prefix */
4e7d34a6 811 { X86_64_TABLE (X86_64_37) },
252b5132 812 /* 38 */
ce518a5f
L		 813 { "cmpB", { Eb, Gb } },
814 { "cmpS", { Ev, Gv } },
815 { "cmpB", { Gb, Eb } },
816 { "cmpS", { Gv, Ev } },
817 { "cmpB", { AL, Ib } },
818 { "cmpS", { eAX, Iv } },
819 { "(bad)", { XX } }, /* SEG DS prefix */
4e7d34a6 820 { X86_64_TABLE (X86_64_3F) },
252b5132 821 /* 40 */
ce518a5f
L		 822 { "inc{S|}", { RMeAX } },
823 { "inc{S|}", { RMeCX } },
824 { "inc{S|}", { RMeDX } },
825 { "inc{S|}", { RMeBX } },
826 { "inc{S|}", { RMeSP } },
827 { "inc{S|}", { RMeBP } },
828 { "inc{S|}", { RMeSI } },
829 { "inc{S|}", { RMeDI } },
252b5132 830 /* 48 */
ce518a5f
L		 831 { "dec{S|}", { RMeAX } },
832 { "dec{S|}", { RMeCX } },
833 { "dec{S|}", { RMeDX } },
834 { "dec{S|}", { RMeBX } },
835 { "dec{S|}", { RMeSP } },
836 { "dec{S|}", { RMeBP } },
837 { "dec{S|}", { RMeSI } },
838 { "dec{S|}", { RMeDI } },
252b5132 839 /* 50 */
ce518a5f
L		 840 { "pushV", { RMrAX } },
841 { "pushV", { RMrCX } },
842 { "pushV", { RMrDX } },
843 { "pushV", { RMrBX } },
844 { "pushV", { RMrSP } },
845 { "pushV", { RMrBP } },
846 { "pushV", { RMrSI } },
847 { "pushV", { RMrDI } },
252b5132 848 /* 58 */
ce518a5f
L		 849 { "popV", { RMrAX } },
850 { "popV", { RMrCX } },
851 { "popV", { RMrDX } },
852 { "popV", { RMrBX } },
853 { "popV", { RMrSP } },
854 { "popV", { RMrBP } },
855 { "popV", { RMrSI } },
856 { "popV", { RMrDI } },
252b5132 857 /* 60 */
4e7d34a6
L		 858 { X86_64_TABLE (X86_64_60) },
859 { X86_64_TABLE (X86_64_61) },
860 { X86_64_TABLE (X86_64_62) },
861 { X86_64_TABLE (X86_64_63) },
ce518a5f
L		 862 { "(bad)", { XX } }, /* seg fs */
863 { "(bad)", { XX } }, /* seg gs */
864 { "(bad)", { XX } }, /* op size prefix */
865 { "(bad)", { XX } }, /* adr size prefix */
252b5132 866 /* 68 */
ce518a5f
L		 867 { "pushT", { Iq } },
868 { "imulS", { Gv, Ev, Iv } },
869 { "pushT", { sIb } },
870 { "imulS", { Gv, Ev, sIb } },
7c52e0e8 871 { "ins{b|}", { Ybr, indirDX } },
4e7d34a6 872 { X86_64_TABLE (X86_64_6D) },
7c52e0e8 873 { "outs{b|}", { indirDXr, Xb } },
4e7d34a6 874 { X86_64_TABLE (X86_64_6F) },
252b5132 875 /* 70 */
ce518a5f
L		 876 { "joH", { Jb, XX, cond_jump_flag } },
877 { "jnoH", { Jb, XX, cond_jump_flag } },
878 { "jbH", { Jb, XX, cond_jump_flag } },
879 { "jaeH", { Jb, XX, cond_jump_flag } },
880 { "jeH", { Jb, XX, cond_jump_flag } },
881 { "jneH", { Jb, XX, cond_jump_flag } },
882 { "jbeH", { Jb, XX, cond_jump_flag } },
883 { "jaH", { Jb, XX, cond_jump_flag } },
252b5132 884 /* 78 */
ce518a5f
L		 885 { "jsH", { Jb, XX, cond_jump_flag } },
886 { "jnsH", { Jb, XX, cond_jump_flag } },
887 { "jpH", { Jb, XX, cond_jump_flag } },
888 { "jnpH", { Jb, XX, cond_jump_flag } },
889 { "jlH", { Jb, XX, cond_jump_flag } },
890 { "jgeH", { Jb, XX, cond_jump_flag } },
891 { "jleH", { Jb, XX, cond_jump_flag } },
892 { "jgH", { Jb, XX, cond_jump_flag } },
252b5132 893 /* 80 */
1ceb70f8
L		 894 { REG_TABLE (REG_80) },
895 { REG_TABLE (REG_81) },
ce518a5f 896 { "(bad)", { XX } },
1ceb70f8 897 { REG_TABLE (REG_82) },
ce518a5f
L		 898 { "testB", { Eb, Gb } },
899 { "testS", { Ev, Gv } },
900 { "xchgB", { Eb, Gb } },
901 { "xchgS", { Ev, Gv } },
252b5132 902 /* 88 */
ce518a5f
L		 903 { "movB", { Eb, Gb } },
904 { "movS", { Ev, Gv } },
905 { "movB", { Gb, Eb } },
906 { "movS", { Gv, Ev } },
907 { "movD", { Sv, Sw } },
1ceb70f8 908 { MOD_TABLE (MOD_8D) },
ce518a5f 909 { "movD", { Sw, Sv } },
1ceb70f8 910 { REG_TABLE (REG_8F) },
252b5132 911 /* 90 */
1ceb70f8 912 { PREFIX_TABLE (PREFIX_90) },
ce518a5f
L		 913 { "xchgS", { RMeCX, eAX } },
914 { "xchgS", { RMeDX, eAX } },
915 { "xchgS", { RMeBX, eAX } },
916 { "xchgS", { RMeSP, eAX } },
917 { "xchgS", { RMeBP, eAX } },
918 { "xchgS", { RMeSI, eAX } },
919 { "xchgS", { RMeDI, eAX } },
252b5132 920 /* 98 */
7c52e0e8
L		 921 { "cW{t|}R", { XX } },
922 { "cR{t|}O", { XX } },
4e7d34a6 923 { X86_64_TABLE (X86_64_9A) },
ce518a5f
L		 924 { "(bad)", { XX } }, /* fwait */
925 { "pushfT", { XX } },
926 { "popfT", { XX } },
7c52e0e8
L		 927 { "sahf", { XX } },
928 { "lahf", { XX } },
252b5132 929 /* a0 */
ce518a5f
L		 930 { "movB", { AL, Ob } },
931 { "movS", { eAX, Ov } },
932 { "movB", { Ob, AL } },
933 { "movS", { Ov, eAX } },
7c52e0e8
L		 934 { "movs{b|}", { Ybr, Xb } },
935 { "movs{R|}", { Yvr, Xv } },
936 { "cmps{b|}", { Xb, Yb } },
937 { "cmps{R|}", { Xv, Yv } },
252b5132 938 /* a8 */
ce518a5f
L		 939 { "testB", { AL, Ib } },
940 { "testS", { eAX, Iv } },
941 { "stosB", { Ybr, AL } },
942 { "stosS", { Yvr, eAX } },
943 { "lodsB", { ALr, Xb } },
944 { "lodsS", { eAXr, Xv } },
945 { "scasB", { AL, Yb } },
946 { "scasS", { eAX, Yv } },
252b5132 947 /* b0 */
ce518a5f
L		 948 { "movB", { RMAL, Ib } },
949 { "movB", { RMCL, Ib } },
950 { "movB", { RMDL, Ib } },
951 { "movB", { RMBL, Ib } },
952 { "movB", { RMAH, Ib } },
953 { "movB", { RMCH, Ib } },
954 { "movB", { RMDH, Ib } },
955 { "movB", { RMBH, Ib } },
252b5132 956 /* b8 */
ce518a5f
L		 957 { "movS", { RMeAX, Iv64 } },
958 { "movS", { RMeCX, Iv64 } },
959 { "movS", { RMeDX, Iv64 } },
960 { "movS", { RMeBX, Iv64 } },
961 { "movS", { RMeSP, Iv64 } },
962 { "movS", { RMeBP, Iv64 } },
963 { "movS", { RMeSI, Iv64 } },
964 { "movS", { RMeDI, Iv64 } },
252b5132 965 /* c0 */
1ceb70f8
L		 966 { REG_TABLE (REG_C0) },
967 { REG_TABLE (REG_C1) },
ce518a5f
L		 968 { "retT", { Iw } },
969 { "retT", { XX } },
4e7d34a6
L		 970 { X86_64_TABLE (X86_64_C4) },
971 { X86_64_TABLE (X86_64_C5) },
1ceb70f8
L		 972 { REG_TABLE (REG_C6) },
973 { REG_TABLE (REG_C7) },
252b5132 974 /* c8 */
ce518a5f
L		 975 { "enterT", { Iw, Ib } },
976 { "leaveT", { XX } },
977 { "lretP", { Iw } },
978 { "lretP", { XX } },
979 { "int3", { XX } },
980 { "int", { Ib } },
4e7d34a6 981 { X86_64_TABLE (X86_64_CE) },
ce518a5f 982 { "iretP", { XX } },
252b5132 983 /* d0 */
1ceb70f8
L		 984 { REG_TABLE (REG_D0) },
985 { REG_TABLE (REG_D1) },
986 { REG_TABLE (REG_D2) },
987 { REG_TABLE (REG_D3) },
4e7d34a6
L		 988 { X86_64_TABLE (X86_64_D4) },
989 { X86_64_TABLE (X86_64_D5) },
ce518a5f
L		 990 { "(bad)", { XX } },
991 { "xlat", { DSBX } },
252b5132
RH		 992 /* d8 */
993 { FLOAT },
994 { FLOAT },
995 { FLOAT },
996 { FLOAT },
997 { FLOAT },
998 { FLOAT },
999 { FLOAT },
1000 { FLOAT },
1001 /* e0 */
ce518a5f
L		 1002 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
1003 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
1004 { "loopFH", { Jb, XX, loop_jcxz_flag } },
1005 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
1006 { "inB", { AL, Ib } },
1007 { "inG", { zAX, Ib } },
1008 { "outB", { Ib, AL } },
1009 { "outG", { Ib, zAX } },
252b5132 1010 /* e8 */
ce518a5f
L		 1011 { "callT", { Jv } },
1012 { "jmpT", { Jv } },
4e7d34a6 1013 { X86_64_TABLE (X86_64_EA) },
ce518a5f
L		 1014 { "jmp", { Jb } },
1015 { "inB", { AL, indirDX } },
1016 { "inG", { zAX, indirDX } },
1017 { "outB", { indirDX, AL } },
1018 { "outG", { indirDX, zAX } },
252b5132 1019 /* f0 */
ce518a5f
L		 1020 { "(bad)", { XX } }, /* lock prefix */
1021 { "icebp", { XX } },
1022 { "(bad)", { XX } }, /* repne */
1023 { "(bad)", { XX } }, /* repz */
1024 { "hlt", { XX } },
1025 { "cmc", { XX } },
1ceb70f8
L		 1026 { REG_TABLE (REG_F6) },
1027 { REG_TABLE (REG_F7) },
252b5132 1028 /* f8 */
ce518a5f
L		 1029 { "clc", { XX } },
1030 { "stc", { XX } },
1031 { "cli", { XX } },
1032 { "sti", { XX } },
1033 { "cld", { XX } },
1034 { "std", { XX } },
1ceb70f8
L		 1035 { REG_TABLE (REG_FE) },
1036 { REG_TABLE (REG_FF) },
252b5132
RH		 1037};
1038
6439fc28 1039static const struct dis386 dis386_twobyte[] = {
252b5132 1040 /* 00 */
1ceb70f8
L		 1041 { REG_TABLE (REG_0F00 ) },
1042 { REG_TABLE (REG_0F01 ) },
ce518a5f
L		 1043 { "larS", { Gv, Ew } },
1044 { "lslS", { Gv, Ew } },
1045 { "(bad)", { XX } },
1046 { "syscall", { XX } },
1047 { "clts", { XX } },
1048 { "sysretP", { XX } },
252b5132 1049 /* 08 */
ce518a5f
L		 1050 { "invd", { XX } },
1051 { "wbinvd", { XX } },
1052 { "(bad)", { XX } },
1053 { "ud2a", { XX } },
1054 { "(bad)", { XX } },
1ceb70f8 1055 { REG_TABLE (REG_0F0E) },
ce518a5f
L		 1056 { "femms", { XX } },
1057 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
252b5132 1058 /* 10 */
1ceb70f8
L		 1059 { PREFIX_TABLE (PREFIX_0F10) },
1060 { PREFIX_TABLE (PREFIX_0F11) },
1061 { PREFIX_TABLE (PREFIX_0F12) },
1062 { MOD_TABLE (MOD_0F13) },
f2a421c4
L		 1063 { "unpcklpX", { XM, EXx } },
1064 { "unpckhpX", { XM, EXx } },
1ceb70f8
L		 1065 { PREFIX_TABLE (PREFIX_0F16) },
1066 { MOD_TABLE (MOD_0F17) },
252b5132 1067 /* 18 */
1ceb70f8 1068 { REG_TABLE (REG_0F18) },
ce518a5f
L		 1069 { "(bad)", { XX } },
1070 { "(bad)", { XX } },
1071 { "(bad)", { XX } },
1072 { "(bad)", { XX } },
1073 { "(bad)", { XX } },
1074 { "(bad)", { XX } },
1075 { "nopQ", { Ev } },
252b5132 1076 /* 20 */
1ceb70f8
L		 1077 { MOD_TABLE (MOD_0F20) },
1078 { MOD_TABLE (MOD_0F21) },
1079 { MOD_TABLE (MOD_0F22) },
1080 { MOD_TABLE (MOD_0F23) },
1081 { MOD_TABLE (MOD_0F24) },
4e7d34a6 1082 { THREE_BYTE_TABLE (THREE_BYTE_0F25) },
1ceb70f8 1083 { MOD_TABLE (MOD_0F26) },
ce518a5f 1084 { "(bad)", { XX } },
252b5132 1085 /* 28 */
09a2c6cf
L		 1086 { "movapX", { XM, EXx } },
1087 { "movapX", { EXx, XM } },
1ceb70f8
L		 1088 { PREFIX_TABLE (PREFIX_0F2A) },
1089 { PREFIX_TABLE (PREFIX_0F2B) },
1090 { PREFIX_TABLE (PREFIX_0F2C) },
1091 { PREFIX_TABLE (PREFIX_0F2D) },
1092 { PREFIX_TABLE (PREFIX_0F2E) },
1093 { PREFIX_TABLE (PREFIX_0F2F) },
252b5132 1094 /* 30 */
ce518a5f
L		 1095 { "wrmsr", { XX } },
1096 { "rdtsc", { XX } },
1097 { "rdmsr", { XX } },
1098 { "rdpmc", { XX } },
1099 { "sysenter", { XX } },
1100 { "sysexit", { XX } },
1101 { "(bad)", { XX } },
47dd174c 1102 { "getsec", { XX } },
252b5132 1103 /* 38 */
4e7d34a6 1104 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
ce518a5f 1105 { "(bad)", { XX } },
4e7d34a6 1106 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
ce518a5f
L		 1107 { "(bad)", { XX } },
1108 { "(bad)", { XX } },
1109 { "(bad)", { XX } },
1110 { "(bad)", { XX } },
1111 { "(bad)", { XX } },
252b5132 1112 /* 40 */
ce518a5f
L		 1113 { "cmovo", { Gv, Ev } },
1114 { "cmovno", { Gv, Ev } },
1115 { "cmovb", { Gv, Ev } },
1116 { "cmovae", { Gv, Ev } },
1117 { "cmove", { Gv, Ev } },
1118 { "cmovne", { Gv, Ev } },
1119 { "cmovbe", { Gv, Ev } },
1120 { "cmova", { Gv, Ev } },
252b5132 1121 /* 48 */
ce518a5f
L		 1122 { "cmovs", { Gv, Ev } },
1123 { "cmovns", { Gv, Ev } },
1124 { "cmovp", { Gv, Ev } },
1125 { "cmovnp", { Gv, Ev } },
1126 { "cmovl", { Gv, Ev } },
1127 { "cmovge", { Gv, Ev } },
1128 { "cmovle", { Gv, Ev } },
1129 { "cmovg", { Gv, Ev } },
252b5132 1130 /* 50 */
ce518a5f 1131 { "movmskpX", { Gdq, XS } },
1ceb70f8
L		 1132 { PREFIX_TABLE (PREFIX_0F51) },
1133 { PREFIX_TABLE (PREFIX_0F52) },
1134 { PREFIX_TABLE (PREFIX_0F53) },
09a2c6cf
L		 1135 { "andpX", { XM, EXx } },
1136 { "andnpX", { XM, EXx } },
1137 { "orpX", { XM, EXx } },
1138 { "xorpX", { XM, EXx } },
252b5132 1139 /* 58 */
1ceb70f8
L		 1140 { PREFIX_TABLE (PREFIX_0F58) },
1141 { PREFIX_TABLE (PREFIX_0F59) },
1142 { PREFIX_TABLE (PREFIX_0F5A) },
1143 { PREFIX_TABLE (PREFIX_0F5B) },
1144 { PREFIX_TABLE (PREFIX_0F5C) },
1145 { PREFIX_TABLE (PREFIX_0F5D) },
1146 { PREFIX_TABLE (PREFIX_0F5E) },
1147 { PREFIX_TABLE (PREFIX_0F5F) },
252b5132 1148 /* 60 */
1ceb70f8
L		 1149 { PREFIX_TABLE (PREFIX_0F60) },
1150 { PREFIX_TABLE (PREFIX_0F61) },
1151 { PREFIX_TABLE (PREFIX_0F62) },
ce518a5f
L		 1152 { "packsswb", { MX, EM } },
1153 { "pcmpgtb", { MX, EM } },
1154 { "pcmpgtw", { MX, EM } },
1155 { "pcmpgtd", { MX, EM } },
1156 { "packuswb", { MX, EM } },
252b5132 1157 /* 68 */
ce518a5f
L		 1158 { "punpckhbw", { MX, EM } },
1159 { "punpckhwd", { MX, EM } },
1160 { "punpckhdq", { MX, EM } },
1161 { "packssdw", { MX, EM } },
1ceb70f8
L		 1162 { PREFIX_TABLE (PREFIX_0F6C) },
1163 { PREFIX_TABLE (PREFIX_0F6D) },
231af070 1164 { "movK", { MX, Edq } },
1ceb70f8 1165 { PREFIX_TABLE (PREFIX_0F6F) },
252b5132 1166 /* 70 */
1ceb70f8
L		 1167 { PREFIX_TABLE (PREFIX_0F70) },
1168 { REG_TABLE (REG_0F71) },
1169 { REG_TABLE (REG_0F72) },
1170 { REG_TABLE (REG_0F73) },
ce518a5f
L		 1171 { "pcmpeqb", { MX, EM } },
1172 { "pcmpeqw", { MX, EM } },
1173 { "pcmpeqd", { MX, EM } },
1174 { "emms", { XX } },
252b5132 1175 /* 78 */
1ceb70f8
L		 1176 { PREFIX_TABLE (PREFIX_0F78) },
1177 { PREFIX_TABLE (PREFIX_0F79) },
4e7d34a6 1178 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
89b66d55 1179 { THREE_BYTE_TABLE (THREE_BYTE_0F7B) },
1ceb70f8
L		 1180 { PREFIX_TABLE (PREFIX_0F7C) },
1181 { PREFIX_TABLE (PREFIX_0F7D) },
1182 { PREFIX_TABLE (PREFIX_0F7E) },
1183 { PREFIX_TABLE (PREFIX_0F7F) },
252b5132 1184 /* 80 */
ce518a5f
L		 1185 { "joH", { Jv, XX, cond_jump_flag } },
1186 { "jnoH", { Jv, XX, cond_jump_flag } },
1187 { "jbH", { Jv, XX, cond_jump_flag } },
1188 { "jaeH", { Jv, XX, cond_jump_flag } },
1189 { "jeH", { Jv, XX, cond_jump_flag } },
1190 { "jneH", { Jv, XX, cond_jump_flag } },
1191 { "jbeH", { Jv, XX, cond_jump_flag } },
1192 { "jaH", { Jv, XX, cond_jump_flag } },
252b5132 1193 /* 88 */
ce518a5f
L		 1194 { "jsH", { Jv, XX, cond_jump_flag } },
1195 { "jnsH", { Jv, XX, cond_jump_flag } },
1196 { "jpH", { Jv, XX, cond_jump_flag } },
1197 { "jnpH", { Jv, XX, cond_jump_flag } },
1198 { "jlH", { Jv, XX, cond_jump_flag } },
1199 { "jgeH", { Jv, XX, cond_jump_flag } },
1200 { "jleH", { Jv, XX, cond_jump_flag } },
1201 { "jgH", { Jv, XX, cond_jump_flag } },
252b5132 1202 /* 90 */
ce518a5f
L		 1203 { "seto", { Eb } },
1204 { "setno", { Eb } },
1205 { "setb", { Eb } },
1206 { "setae", { Eb } },
1207 { "sete", { Eb } },
1208 { "setne", { Eb } },
1209 { "setbe", { Eb } },
1210 { "seta", { Eb } },
252b5132 1211 /* 98 */
ce518a5f
L		 1212 { "sets", { Eb } },
1213 { "setns", { Eb } },
1214 { "setp", { Eb } },
1215 { "setnp", { Eb } },
1216 { "setl", { Eb } },
1217 { "setge", { Eb } },
1218 { "setle", { Eb } },
1219 { "setg", { Eb } },
252b5132 1220 /* a0 */
ce518a5f
L		 1221 { "pushT", { fs } },
1222 { "popT", { fs } },
1223 { "cpuid", { XX } },
1224 { "btS", { Ev, Gv } },
1225 { "shldS", { Ev, Gv, Ib } },
1226 { "shldS", { Ev, Gv, CL } },
1ceb70f8
L		 1227 { REG_TABLE (REG_0FA6) },
1228 { REG_TABLE (REG_0FA7) },
252b5132 1229 /* a8 */
ce518a5f
L		 1230 { "pushT", { gs } },
1231 { "popT", { gs } },
1232 { "rsm", { XX } },
1233 { "btsS", { Ev, Gv } },
1234 { "shrdS", { Ev, Gv, Ib } },
1235 { "shrdS", { Ev, Gv, CL } },
1ceb70f8 1236 { REG_TABLE (REG_0FAE) },
ce518a5f 1237 { "imulS", { Gv, Ev } },
252b5132 1238 /* b0 */
ce518a5f
L		 1239 { "cmpxchgB", { Eb, Gb } },
1240 { "cmpxchgS", { Ev, Gv } },
1ceb70f8 1241 { MOD_TABLE (MOD_0FB2) },
ce518a5f 1242 { "btrS", { Ev, Gv } },
1ceb70f8
L		 1243 { MOD_TABLE (MOD_0FB4) },
1244 { MOD_TABLE (MOD_0FB5) },
7c52e0e8
L		 1245 { "movz{bR|x}", { Gv, Eb } },
1246 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
252b5132 1247 /* b8 */
1ceb70f8 1248 { PREFIX_TABLE (PREFIX_0FB8) },
ce518a5f 1249 { "ud2b", { XX } },
1ceb70f8 1250 { REG_TABLE (REG_0FBA) },
ce518a5f
L		 1251 { "btcS", { Ev, Gv } },
1252 { "bsfS", { Gv, Ev } },
1ceb70f8 1253 { PREFIX_TABLE (PREFIX_0FBD) },
7c52e0e8
L		 1254 { "movs{bR|x}", { Gv, Eb } },
1255 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
252b5132 1256 /* c0 */
ce518a5f
L		 1257 { "xaddB", { Eb, Gb } },
1258 { "xaddS", { Ev, Gv } },
1ceb70f8 1259 { PREFIX_TABLE (PREFIX_0FC2) },
ce518a5f
L		 1260 { "movntiS", { Ev, Gv } },
1261 { "pinsrw", { MX, Edqw, Ib } },
1262 { "pextrw", { Gdq, MS, Ib } },
09a2c6cf 1263 { "shufpX", { XM, EXx, Ib } },
1ceb70f8 1264 { REG_TABLE (REG_0FC7) },
252b5132 1265 /* c8 */
ce518a5f
L		 1266 { "bswap", { RMeAX } },
1267 { "bswap", { RMeCX } },
1268 { "bswap", { RMeDX } },
1269 { "bswap", { RMeBX } },
1270 { "bswap", { RMeSP } },
1271 { "bswap", { RMeBP } },
1272 { "bswap", { RMeSI } },
1273 { "bswap", { RMeDI } },
252b5132 1274 /* d0 */
1ceb70f8 1275 { PREFIX_TABLE (PREFIX_0FD0) },
ce518a5f
L		 1276 { "psrlw", { MX, EM } },
1277 { "psrld", { MX, EM } },
1278 { "psrlq", { MX, EM } },
1279 { "paddq", { MX, EM } },
1280 { "pmullw", { MX, EM } },
1ceb70f8 1281 { PREFIX_TABLE (PREFIX_0FD6) },
ce518a5f 1282 { "pmovmskb", { Gdq, MS } },
252b5132 1283 /* d8 */
ce518a5f
L		 1284 { "psubusb", { MX, EM } },
1285 { "psubusw", { MX, EM } },
1286 { "pminub", { MX, EM } },
1287 { "pand", { MX, EM } },
1288 { "paddusb", { MX, EM } },
1289 { "paddusw", { MX, EM } },
1290 { "pmaxub", { MX, EM } },
1291 { "pandn", { MX, EM } },
252b5132 1292 /* e0 */
ce518a5f
L		 1293 { "pavgb", { MX, EM } },
1294 { "psraw", { MX, EM } },
1295 { "psrad", { MX, EM } },
1296 { "pavgw", { MX, EM } },
1297 { "pmulhuw", { MX, EM } },
1298 { "pmulhw", { MX, EM } },
1ceb70f8
L		 1299 { PREFIX_TABLE (PREFIX_0FE6) },
1300 { PREFIX_TABLE (PREFIX_0FE7) },
252b5132 1301 /* e8 */
ce518a5f
L		 1302 { "psubsb", { MX, EM } },
1303 { "psubsw", { MX, EM } },
1304 { "pminsw", { MX, EM } },
1305 { "por", { MX, EM } },
1306 { "paddsb", { MX, EM } },
1307 { "paddsw", { MX, EM } },
1308 { "pmaxsw", { MX, EM } },
1309 { "pxor", { MX, EM } },
252b5132 1310 /* f0 */
1ceb70f8 1311 { PREFIX_TABLE (PREFIX_0FF0) },
ce518a5f
L		 1312 { "psllw", { MX, EM } },
1313 { "pslld", { MX, EM } },
1314 { "psllq", { MX, EM } },
1315 { "pmuludq", { MX, EM } },
1316 { "pmaddwd", { MX, EM } },
1317 { "psadbw", { MX, EM } },
1ceb70f8 1318 { PREFIX_TABLE (PREFIX_0FF7) },
252b5132 1319 /* f8 */
ce518a5f
L		 1320 { "psubb", { MX, EM } },
1321 { "psubw", { MX, EM } },
1322 { "psubd", { MX, EM } },
1323 { "psubq", { MX, EM } },
1324 { "paddb", { MX, EM } },
1325 { "paddw", { MX, EM } },
1326 { "paddd", { MX, EM } },
1327 { "(bad)", { XX } },
252b5132
RH		 1328};
1329
1330static const unsigned char onebyte_has_modrm[256] = {
c608c12e
AM		 1331 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1332 /* ------------------------------- */
1333 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1334 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1335 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1336 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1337 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1338 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1339 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1340 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1341 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1342 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1343 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1344 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1345 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1346 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1347 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1348 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1349 /* ------------------------------- */
1350 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
252b5132
RH		 1351};
1352
1353static const unsigned char twobyte_has_modrm[256] = {
c608c12e
AM		 1354 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1355 /* ------------------------------- */
252b5132 1356 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
15965411 1357 /* 10 */ 1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,1, /* 1f */
85f10a01 1358 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
331d2d0d 1359 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
252b5132 1360 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
4bba6815
AM		 1361 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1362 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
85f10a01 1363 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
252b5132
RH		 1364 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1365 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
30d1c836 1366 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
050dfa73 1367 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
252b5132 1368 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
ca164297 1369 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
4bba6815 1370 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
ca164297 1371 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
c608c12e
AM		 1372 /* ------------------------------- */
1373 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1374};
1375
252b5132
RH		 1376static char obuf[100];
1377static char *obufp;
1378static char scratchbuf[100];
1379static unsigned char *start_codep;
1380static unsigned char *insn_codep;
1381static unsigned char *codep;
b844680a
L		 1382static const char *lock_prefix;
1383static const char *data_prefix;
1384static const char *addr_prefix;
1385static const char *repz_prefix;
1386static const char *repnz_prefix;
252b5132 1387static disassemble_info *the_info;
7967e09e
L		 1388static struct
1389 {
1390 int mod;
7967e09e 1391 int reg;
484c222e 1392 int rm;
7967e09e
L		 1393 }
1394modrm;
4bba6815 1395static unsigned char need_modrm;
252b5132 1396
4bba6815
AM		 1397/* If we are accessing mod/rm/reg without need_modrm set, then the
1398 values are stale. Hitting this abort likely indicates that you
1399 need to update onebyte_has_modrm or twobyte_has_modrm. */
1400#define MODRM_CHECK if (!need_modrm) abort ()
1401
d708bcba
AM		 1402static const char **names64;
1403static const char **names32;
1404static const char **names16;
1405static const char **names8;
1406static const char **names8rex;
1407static const char **names_seg;
db51cc60
L		 1408static const char *index64;
1409static const char *index32;
d708bcba
AM		 1410static const char **index16;
1411
1412static const char *intel_names64[] = {
1413 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
1414 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
1415};
1416static const char *intel_names32[] = {
1417 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
1418 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
1419};
1420static const char *intel_names16[] = {
1421 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
1422 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
1423};
1424static const char *intel_names8[] = {
1425 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
1426};
1427static const char *intel_names8rex[] = {
1428 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
1429 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
1430};
1431static const char *intel_names_seg[] = {
1432 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
1433};
db51cc60
L		 1434static const char *intel_index64 = "riz";
1435static const char *intel_index32 = "eiz";
d708bcba
AM		 1436static const char *intel_index16[] = {
1437 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
1438};
1439
1440static const char *att_names64[] = {
1441 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
52b15da3
JH		 1442 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
1443};
d708bcba
AM		 1444static const char *att_names32[] = {
1445 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
52b15da3 1446 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
252b5132 1447};
d708bcba
AM		 1448static const char *att_names16[] = {
1449 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
52b15da3 1450 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
252b5132 1451};
d708bcba
AM		 1452static const char *att_names8[] = {
1453 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
252b5132 1454};
d708bcba
AM		 1455static const char *att_names8rex[] = {
1456 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
52b15da3
JH		 1457 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
1458};
d708bcba
AM		 1459static const char *att_names_seg[] = {
1460 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
252b5132 1461};
db51cc60
L		 1462static const char *att_index64 = "%riz";
1463static const char *att_index32 = "%eiz";
d708bcba
AM		 1464static const char *att_index16[] = {
1465 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
252b5132
RH		 1466};
1467
1ceb70f8
L		 1468static const struct dis386 reg_table[][8] = {
1469 /* REG_80 */
252b5132 1470 {
ce518a5f
L		 1471 { "addA", { Eb, Ib } },
1472 { "orA", { Eb, Ib } },
1473 { "adcA", { Eb, Ib } },
1474 { "sbbA", { Eb, Ib } },
1475 { "andA", { Eb, Ib } },
1476 { "subA", { Eb, Ib } },
1477 { "xorA", { Eb, Ib } },
1478 { "cmpA", { Eb, Ib } },
252b5132 1479 },
1ceb70f8 1480 /* REG_81 */
252b5132 1481 {
ce518a5f
L		 1482 { "addQ", { Ev, Iv } },
1483 { "orQ", { Ev, Iv } },
1484 { "adcQ", { Ev, Iv } },
1485 { "sbbQ", { Ev, Iv } },
1486 { "andQ", { Ev, Iv } },
1487 { "subQ", { Ev, Iv } },
1488 { "xorQ", { Ev, Iv } },
1489 { "cmpQ", { Ev, Iv } },
252b5132 1490 },
1ceb70f8 1491 /* REG_82 */
252b5132 1492 {
ce518a5f
L		 1493 { "addQ", { Ev, sIb } },
1494 { "orQ", { Ev, sIb } },
1495 { "adcQ", { Ev, sIb } },
1496 { "sbbQ", { Ev, sIb } },
1497 { "andQ", { Ev, sIb } },
1498 { "subQ", { Ev, sIb } },
1499 { "xorQ", { Ev, sIb } },
1500 { "cmpQ", { Ev, sIb } },
252b5132 1501 },
1ceb70f8 1502 /* REG_8F */
4e7d34a6
L		 1503 {
1504 { "popU", { stackEv } },
1505 { "(bad)", { XX } },
1506 { "(bad)", { XX } },
1507 { "(bad)", { XX } },
1508 { "(bad)", { XX } },
1509 { "(bad)", { XX } },
1510 { "(bad)", { XX } },
1511 { "(bad)", { XX } },
1512 },
1ceb70f8 1513 /* REG_C0 */
252b5132 1514 {
ce518a5f
L		 1515 { "rolA", { Eb, Ib } },
1516 { "rorA", { Eb, Ib } },
1517 { "rclA", { Eb, Ib } },
1518 { "rcrA", { Eb, Ib } },
1519 { "shlA", { Eb, Ib } },
1520 { "shrA", { Eb, Ib } },
1521 { "(bad)", { XX } },
1522 { "sarA", { Eb, Ib } },
252b5132 1523 },
1ceb70f8 1524 /* REG_C1 */
252b5132 1525 {
ce518a5f
L		 1526 { "rolQ", { Ev, Ib } },
1527 { "rorQ", { Ev, Ib } },
1528 { "rclQ", { Ev, Ib } },
1529 { "rcrQ", { Ev, Ib } },
1530 { "shlQ", { Ev, Ib } },
1531 { "shrQ", { Ev, Ib } },
1532 { "(bad)", { XX } },
1533 { "sarQ", { Ev, Ib } },
252b5132 1534 },
1ceb70f8 1535 /* REG_C6 */
4e7d34a6
L		 1536 {
1537 { "movA", { Eb, Ib } },
1538 { "(bad)", { XX } },
1539 { "(bad)", { XX } },
1540 { "(bad)", { XX } },
1541 { "(bad)", { XX } },
1542 { "(bad)", { XX } },
1543 { "(bad)", { XX } },
1544 { "(bad)", { XX } },
1545 },
1ceb70f8 1546 /* REG_C7 */
4e7d34a6
L		 1547 {
1548 { "movQ", { Ev, Iv } },
1549 { "(bad)", { XX } },
1550 { "(bad)", { XX } },
1551 { "(bad)", { XX } },
1552 { "(bad)", { XX } },
1553 { "(bad)", { XX } },
1554 { "(bad)", { XX } },
1555 { "(bad)", { XX } },
1556 },
1ceb70f8 1557 /* REG_D0 */
252b5132 1558 {
ce518a5f
L		 1559 { "rolA", { Eb, I1 } },
1560 { "rorA", { Eb, I1 } },
1561 { "rclA", { Eb, I1 } },
1562 { "rcrA", { Eb, I1 } },
1563 { "shlA", { Eb, I1 } },
1564 { "shrA", { Eb, I1 } },
1565 { "(bad)", { XX } },
1566 { "sarA", { Eb, I1 } },
252b5132 1567 },
1ceb70f8 1568 /* REG_D1 */
252b5132 1569 {
ce518a5f
L		 1570 { "rolQ", { Ev, I1 } },
1571 { "rorQ", { Ev, I1 } },
1572 { "rclQ", { Ev, I1 } },
1573 { "rcrQ", { Ev, I1 } },
1574 { "shlQ", { Ev, I1 } },
1575 { "shrQ", { Ev, I1 } },
1576 { "(bad)", { XX } },
1577 { "sarQ", { Ev, I1 } },
252b5132 1578 },
1ceb70f8 1579 /* REG_D2 */
252b5132 1580 {
ce518a5f
L		 1581 { "rolA", { Eb, CL } },
1582 { "rorA", { Eb, CL } },
1583 { "rclA", { Eb, CL } },
1584 { "rcrA", { Eb, CL } },
1585 { "shlA", { Eb, CL } },
1586 { "shrA", { Eb, CL } },
1587 { "(bad)", { XX } },
1588 { "sarA", { Eb, CL } },
252b5132 1589 },
1ceb70f8 1590 /* REG_D3 */
252b5132 1591 {
ce518a5f
L		 1592 { "rolQ", { Ev, CL } },
1593 { "rorQ", { Ev, CL } },
1594 { "rclQ", { Ev, CL } },
1595 { "rcrQ", { Ev, CL } },
1596 { "shlQ", { Ev, CL } },
1597 { "shrQ", { Ev, CL } },
1598 { "(bad)", { XX } },
1599 { "sarQ", { Ev, CL } },
252b5132 1600 },
1ceb70f8 1601 /* REG_F6 */
252b5132 1602 {
ce518a5f 1603 { "testA", { Eb, Ib } },
058f233b 1604 { "(bad)", { XX } },
ce518a5f
L		 1605 { "notA", { Eb } },
1606 { "negA", { Eb } },
1607 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
1608 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
1609 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
1610 { "idivA", { Eb } }, /* and idiv for consistency. */
252b5132 1611 },
1ceb70f8 1612 /* REG_F7 */
252b5132 1613 {
ce518a5f
L		 1614 { "testQ", { Ev, Iv } },
1615 { "(bad)", { XX } },
1616 { "notQ", { Ev } },
1617 { "negQ", { Ev } },
1618 { "mulQ", { Ev } }, /* Don't print the implicit register. */
1619 { "imulQ", { Ev } },
1620 { "divQ", { Ev } },
1621 { "idivQ", { Ev } },
252b5132 1622 },
1ceb70f8 1623 /* REG_FE */
252b5132 1624 {
ce518a5f
L		 1625 { "incA", { Eb } },
1626 { "decA", { Eb } },
1627 { "(bad)", { XX } },
1628 { "(bad)", { XX } },
1629 { "(bad)", { XX } },
1630 { "(bad)", { XX } },
1631 { "(bad)", { XX } },
1632 { "(bad)", { XX } },
252b5132 1633 },
1ceb70f8 1634 /* REG_FF */
252b5132 1635 {
ce518a5f
L		 1636 { "incQ", { Ev } },
1637 { "decQ", { Ev } },
1638 { "callT", { indirEv } },
1639 { "JcallT", { indirEp } },
1640 { "jmpT", { indirEv } },
1641 { "JjmpT", { indirEp } },
1642 { "pushU", { stackEv } },
1643 { "(bad)", { XX } },
252b5132 1644 },
1ceb70f8 1645 /* REG_0F00 */
252b5132 1646 {
ce518a5f
L		 1647 { "sldtD", { Sv } },
1648 { "strD", { Sv } },
1649 { "lldt", { Ew } },
1650 { "ltr", { Ew } },
1651 { "verr", { Ew } },
1652 { "verw", { Ew } },
1653 { "(bad)", { XX } },
1654 { "(bad)", { XX } },
252b5132 1655 },
1ceb70f8 1656 /* REG_0F01 */
252b5132 1657 {
1ceb70f8
L		 1658 { MOD_TABLE (MOD_0F01_REG_0) },
1659 { MOD_TABLE (MOD_0F01_REG_1) },
1660 { MOD_TABLE (MOD_0F01_REG_2) },
1661 { MOD_TABLE (MOD_0F01_REG_3) },
ce518a5f
L		 1662 { "smswD", { Sv } },
1663 { "(bad)", { XX } },
1664 { "lmsw", { Ew } },
1ceb70f8 1665 { MOD_TABLE (MOD_0F01_REG_7) },
252b5132 1666 },
1ceb70f8 1667 /* REG_0F0E */
252b5132 1668 {
4e7d34a6
L		 1669 { "prefetch", { Eb } },
1670 { "prefetchw", { Eb } },
1671 { "(bad)", { XX } },
1672 { "(bad)", { XX } },
1673 { "(bad)", { XX } },
1674 { "(bad)", { XX } },
1675 { "(bad)", { XX } },
1676 { "(bad)", { XX } },
252b5132 1677 },
1ceb70f8 1678 /* REG_0F18 */
252b5132 1679 {
1ceb70f8
L		 1680 { MOD_TABLE (MOD_0F18_REG_0) },
1681 { MOD_TABLE (MOD_0F18_REG_1) },
1682 { MOD_TABLE (MOD_0F18_REG_2) },
1683 { MOD_TABLE (MOD_0F18_REG_3) },
ce518a5f
L		 1684 { "(bad)", { XX } },
1685 { "(bad)", { XX } },
1686 { "(bad)", { XX } },
1687 { "(bad)", { XX } },
252b5132 1688 },
1ceb70f8 1689 /* REG_0F71 */
a6bd098c 1690 {
ce518a5f
L		 1691 { "(bad)", { XX } },
1692 { "(bad)", { XX } },
1ceb70f8 1693 { MOD_TABLE (MOD_0F71_REG_2) },
ce518a5f 1694 { "(bad)", { XX } },
1ceb70f8 1695 { MOD_TABLE (MOD_0F71_REG_4) },
ce518a5f 1696 { "(bad)", { XX } },
1ceb70f8 1697 { MOD_TABLE (MOD_0F71_REG_6) },
ce518a5f 1698 { "(bad)", { XX } },
a6bd098c 1699 },
1ceb70f8 1700 /* REG_0F72 */
a6bd098c 1701 {
ce518a5f
L		 1702 { "(bad)", { XX } },
1703 { "(bad)", { XX } },
1ceb70f8 1704 { MOD_TABLE (MOD_0F72_REG_2) },
ce518a5f 1705 { "(bad)", { XX } },
1ceb70f8 1706 { MOD_TABLE (MOD_0F72_REG_4) },
ce518a5f 1707 { "(bad)", { XX } },
1ceb70f8 1708 { MOD_TABLE (MOD_0F72_REG_6) },
ce518a5f 1709 { "(bad)", { XX } },
a6bd098c 1710 },
1ceb70f8 1711 /* REG_0F73 */
252b5132 1712 {
ce518a5f
L		 1713 { "(bad)", { XX } },
1714 { "(bad)", { XX } },
1ceb70f8
L		 1715 { MOD_TABLE (MOD_0F73_REG_2) },
1716 { MOD_TABLE (MOD_0F73_REG_3) },
ce518a5f 1717 { "(bad)", { XX } },
ce518a5f 1718 { "(bad)", { XX } },
1ceb70f8
L		 1719 { MOD_TABLE (MOD_0F73_REG_6) },
1720 { MOD_TABLE (MOD_0F73_REG_7) },
252b5132 1721 },
1ceb70f8 1722 /* REG_0FA6 */
252b5132 1723 {
4e7d34a6
L		 1724 { "montmul", { { OP_0f07, 0 } } },
1725 { "xsha1", { { OP_0f07, 0 } } },
1726 { "xsha256", { { OP_0f07, 0 } } },
1727 { "(bad)", { { OP_0f07, 0 } } },
1728 { "(bad)", { { OP_0f07, 0 } } },
1729 { "(bad)", { { OP_0f07, 0 } } },
1730 { "(bad)", { { OP_0f07, 0 } } },
1731 { "(bad)", { { OP_0f07, 0 } } },
1732 },
1ceb70f8 1733 /* REG_0FA7 */
4e7d34a6
L		 1734 {
1735 { "xstore-rng", { { OP_0f07, 0 } } },
1736 { "xcrypt-ecb", { { OP_0f07, 0 } } },
1737 { "xcrypt-cbc", { { OP_0f07, 0 } } },
1738 { "xcrypt-ctr", { { OP_0f07, 0 } } },
1739 { "xcrypt-cfb", { { OP_0f07, 0 } } },
1740 { "xcrypt-ofb", { { OP_0f07, 0 } } },
1741 { "(bad)", { { OP_0f07, 0 } } },
1742 { "(bad)", { { OP_0f07, 0 } } },
1743 },
1ceb70f8 1744 /* REG_0FAE */
4e7d34a6 1745 {
1ceb70f8
L		 1746 { MOD_TABLE (MOD_0FAE_REG_0) },
1747 { MOD_TABLE (MOD_0FAE_REG_1) },
1748 { MOD_TABLE (MOD_0FAE_REG_2) },
1749 { MOD_TABLE (MOD_0FAE_REG_3) },
ce518a5f 1750 { "(bad)", { XX } },
1ceb70f8
L		 1751 { MOD_TABLE (MOD_0FAE_REG_5) },
1752 { MOD_TABLE (MOD_0FAE_REG_6) },
1753 { MOD_TABLE (MOD_0FAE_REG_7) },
252b5132 1754 },
1ceb70f8 1755 /* REG_0FBA */
252b5132 1756 {
ce518a5f
L		 1757 { "(bad)", { XX } },
1758 { "(bad)", { XX } },
d8faab4e
L		 1759 { "(bad)", { XX } },
1760 { "(bad)", { XX } },
4e7d34a6
L		 1761 { "btQ", { Ev, Ib } },
1762 { "btsQ", { Ev, Ib } },
1763 { "btrQ", { Ev, Ib } },
1764 { "btcQ", { Ev, Ib } },
c608c12e 1765 },
1ceb70f8 1766 /* REG_0FC7 */
c608c12e 1767 {
b844680a 1768 { "(bad)", { XX } },
4e7d34a6 1769 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
d8faab4e 1770 { "(bad)", { XX } },
b844680a
L		 1771 { "(bad)", { XX } },
1772 { "(bad)", { XX } },
1773 { "(bad)", { XX } },
1ceb70f8
L		 1774 { MOD_TABLE (MOD_0FC7_REG_6) },
1775 { MOD_TABLE (MOD_0FC7_REG_7) },
252b5132 1776 },
4e7d34a6
L		 1777};
1778
1ceb70f8
L		 1779static const struct dis386 prefix_table[][4] = {
1780 /* PREFIX_90 */
252b5132 1781 {
4e7d34a6
L		 1782 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
1783 { "pause", { XX } },
1784 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
1785 { "(bad)", { XX } },
0f10071e 1786 },
4e7d34a6 1787
1ceb70f8 1788 /* PREFIX_0F10 */
cc0ec051 1789 {
4e7d34a6
L		 1790 { "movups", { XM, EXx } },
1791 { "movss", { XM, EXd } },
1792 { "movupd", { XM, EXx } },
1793 { "movsd", { XM, EXq } },
30d1c836 1794 },
4e7d34a6 1795
1ceb70f8 1796 /* PREFIX_0F11 */
30d1c836 1797 {
4e7d34a6
L		 1798 { "movups", { EXx, XM } },
1799 { "movss", { EXd, XM } },
1800 { "movupd", { EXx, XM } },
1801 { "movsd", { EXq, XM } },
1802 },
252b5132 1803
1ceb70f8 1804 /* PREFIX_0F12 */
c608c12e 1805 {
1ceb70f8 1806 { MOD_TABLE (MOD_0F12_PREFIX_0) },
4e7d34a6
L		 1807 { "movsldup", { XM, EXx } },
1808 { "movlpd", { XM, EXq } },
1809 { "movddup", { XM, EXq } },
c608c12e 1810 },
4e7d34a6 1811
1ceb70f8 1812 /* PREFIX_0F16 */
c608c12e 1813 {
1ceb70f8 1814 { MOD_TABLE (MOD_0F16_PREFIX_0) },
4e7d34a6
L		 1815 { "movshdup", { XM, EXx } },
1816 { "movhpd", { XM, EXq } },
058f233b 1817 { "(bad)", { XX } },
c608c12e 1818 },
4e7d34a6 1819
1ceb70f8 1820 /* PREFIX_0F2A */
c608c12e 1821 {
09335d05 1822 { "cvtpi2ps", { XM, EMCq } },
ce518a5f 1823 { "cvtsi2ssY", { XM, Ev } },
09335d05 1824 { "cvtpi2pd", { XM, EMCq } },
ce518a5f 1825 { "cvtsi2sdY", { XM, Ev } },
c608c12e 1826 },
4e7d34a6 1827
1ceb70f8 1828 /* PREFIX_0F2B */
c608c12e 1829 {
4e7d34a6
L		 1830 {"movntps", { Ev, XM } },
1831 {"movntss", { Ed, XM } },
1832 {"movntpd", { Ev, XM } },
1833 {"movntsd", { Eq, XM } },
c608c12e 1834 },
4e7d34a6 1835
1ceb70f8 1836 /* PREFIX_0F2C */
c608c12e 1837 {
09335d05
L		 1838 { "cvttps2pi", { MXC, EXq } },
1839 { "cvttss2siY", { Gv, EXd } },
09a2c6cf 1840 { "cvttpd2pi", { MXC, EXx } },
09335d05 1841 { "cvttsd2siY", { Gv, EXq } },
c608c12e 1842 },
4e7d34a6 1843
1ceb70f8 1844 /* PREFIX_0F2D */
c608c12e 1845 {
4e7d34a6
L		 1846 { "cvtps2pi", { MXC, EXq } },
1847 { "cvtss2siY", { Gv, EXd } },
1848 { "cvtpd2pi", { MXC, EXx } },
1849 { "cvtsd2siY", { Gv, EXq } },
c608c12e 1850 },
4e7d34a6 1851
1ceb70f8 1852 /* PREFIX_0F2E */
c608c12e 1853 {
4e7d34a6
L		 1854 { "ucomiss",{ XM, EXd } },
1855 { "(bad)", { XX } },
1856 { "ucomisd",{ XM, EXq } },
1857 { "(bad)", { XX } },
c608c12e 1858 },
4e7d34a6 1859
1ceb70f8 1860 /* PREFIX_0F2F */
c608c12e 1861 {
4e7d34a6
L		 1862 { "comiss", { XM, EXd } },
1863 { "(bad)", { XX } },
1864 { "comisd", { XM, EXq } },
1865 { "(bad)", { XX } },
c608c12e 1866 },
4e7d34a6 1867
1ceb70f8 1868 /* PREFIX_0F51 */
c608c12e 1869 {
4e7d34a6
L		 1870 { "sqrtps", { XM, EXx } },
1871 { "sqrtss", { XM, EXd } },
1872 { "sqrtpd", { XM, EXx } },
1873 { "sqrtsd", { XM, EXq } },
c608c12e 1874 },
4e7d34a6 1875
1ceb70f8 1876 /* PREFIX_0F52 */
c608c12e 1877 {
4e7d34a6
L		 1878 { "rsqrtps",{ XM, EXx } },
1879 { "rsqrtss",{ XM, EXd } },
058f233b
L		 1880 { "(bad)", { XX } },
1881 { "(bad)", { XX } },
c608c12e 1882 },
4e7d34a6 1883
1ceb70f8 1884 /* PREFIX_0F53 */
c608c12e 1885 {
4e7d34a6
L		 1886 { "rcpps", { XM, EXx } },
1887 { "rcpss", { XM, EXd } },
058f233b
L		 1888 { "(bad)", { XX } },
1889 { "(bad)", { XX } },
c608c12e 1890 },
4e7d34a6 1891
1ceb70f8 1892 /* PREFIX_0F58 */
c608c12e 1893 {
4e7d34a6
L		 1894 { "addps", { XM, EXx } },
1895 { "addss", { XM, EXd } },
1896 { "addpd", { XM, EXx } },
1897 { "addsd", { XM, EXq } },
c608c12e 1898 },
4e7d34a6 1899
1ceb70f8 1900 /* PREFIX_0F59 */
c608c12e 1901 {
4e7d34a6
L		 1902 { "mulps", { XM, EXx } },
1903 { "mulss", { XM, EXd } },
1904 { "mulpd", { XM, EXx } },
1905 { "mulsd", { XM, EXq } },
041bd2e0 1906 },
4e7d34a6 1907
1ceb70f8 1908 /* PREFIX_0F5A */
041bd2e0 1909 {
4e7d34a6
L		 1910 { "cvtps2pd", { XM, EXq } },
1911 { "cvtss2sd", { XM, EXd } },
1912 { "cvtpd2ps", { XM, EXx } },
1913 { "cvtsd2ss", { XM, EXq } },
041bd2e0 1914 },
4e7d34a6 1915
1ceb70f8 1916 /* PREFIX_0F5B */
041bd2e0 1917 {
09a2c6cf
L		 1918 { "cvtdq2ps", { XM, EXx } },
1919 { "cvttps2dq", { XM, EXx } },
1920 { "cvtps2dq", { XM, EXx } },
058f233b 1921 { "(bad)", { XX } },
041bd2e0 1922 },
4e7d34a6 1923
1ceb70f8 1924 /* PREFIX_0F5C */
041bd2e0 1925 {
4e7d34a6
L		 1926 { "subps", { XM, EXx } },
1927 { "subss", { XM, EXd } },
1928 { "subpd", { XM, EXx } },
1929 { "subsd", { XM, EXq } },
041bd2e0 1930 },
4e7d34a6 1931
1ceb70f8 1932 /* PREFIX_0F5D */
041bd2e0 1933 {
4e7d34a6
L		 1934 { "minps", { XM, EXx } },
1935 { "minss", { XM, EXd } },
1936 { "minpd", { XM, EXx } },
1937 { "minsd", { XM, EXq } },
041bd2e0 1938 },
4e7d34a6 1939
1ceb70f8 1940 /* PREFIX_0F5E */
041bd2e0 1941 {
4e7d34a6
L		 1942 { "divps", { XM, EXx } },
1943 { "divss", { XM, EXd } },
1944 { "divpd", { XM, EXx } },
1945 { "divsd", { XM, EXq } },
041bd2e0 1946 },
4e7d34a6 1947
1ceb70f8 1948 /* PREFIX_0F5F */
041bd2e0 1949 {
4e7d34a6
L		 1950 { "maxps", { XM, EXx } },
1951 { "maxss", { XM, EXd } },
1952 { "maxpd", { XM, EXx } },
1953 { "maxsd", { XM, EXq } },
041bd2e0 1954 },
4e7d34a6 1955
1ceb70f8 1956 /* PREFIX_0F60 */
041bd2e0 1957 {
4e7d34a6
L		 1958 { "punpcklbw",{ MX, EMd } },
1959 { "(bad)", { XX } },
1960 { "punpcklbw",{ MX, EMx } },
1961 { "(bad)", { XX } },
041bd2e0 1962 },
4e7d34a6 1963
1ceb70f8 1964 /* PREFIX_0F61 */
041bd2e0 1965 {
4e7d34a6
L		 1966 { "punpcklwd",{ MX, EMd } },
1967 { "(bad)", { XX } },
1968 { "punpcklwd",{ MX, EMx } },
1969 { "(bad)", { XX } },
041bd2e0 1970 },
4e7d34a6 1971
1ceb70f8 1972 /* PREFIX_0F62 */
041bd2e0 1973 {
4e7d34a6
L		 1974 { "punpckldq",{ MX, EMd } },
1975 { "(bad)", { XX } },
1976 { "punpckldq",{ MX, EMx } },
1977 { "(bad)", { XX } },
041bd2e0 1978 },
4e7d34a6 1979
1ceb70f8 1980 /* PREFIX_0F6C */
041bd2e0 1981 {
058f233b
L		 1982 { "(bad)", { XX } },
1983 { "(bad)", { XX } },
4e7d34a6 1984 { "punpcklqdq", { XM, EXx } },
058f233b 1985 { "(bad)", { XX } },
0f17484f 1986 },
4e7d34a6 1987
1ceb70f8 1988 /* PREFIX_0F6D */
0f17484f 1989 {
058f233b
L		 1990 { "(bad)", { XX } },
1991 { "(bad)", { XX } },
4e7d34a6 1992 { "punpckhqdq", { XM, EXx } },
058f233b 1993 { "(bad)", { XX } },
041bd2e0 1994 },
4e7d34a6 1995
1ceb70f8 1996 /* PREFIX_0F6F */
ca164297 1997 {
4e7d34a6
L		 1998 { "movq", { MX, EM } },
1999 { "movdqu", { XM, EXx } },
2000 { "movdqa", { XM, EXx } },
058f233b 2001 { "(bad)", { XX } },
ca164297 2002 },
4e7d34a6 2003
1ceb70f8 2004 /* PREFIX_0F70 */
4e7d34a6
L		 2005 {
2006 { "pshufw", { MX, EM, Ib } },
2007 { "pshufhw",{ XM, EXx, Ib } },
2008 { "pshufd", { XM, EXx, Ib } },
2009 { "pshuflw",{ XM, EXx, Ib } },
2010 },
2011
1ceb70f8 2012 /* PREFIX_0F78 */
4e7d34a6
L		 2013 {
2014 {"vmread", { Em, Gm } },
2015 {"(bad)", { XX } },
2016 {"extrq", { XS, Ib, Ib } },
2017 {"insertq", { XM, XS, Ib, Ib } },
2018 },
2019
1ceb70f8 2020 /* PREFIX_0F79 */
4e7d34a6
L		 2021 {
2022 {"vmwrite", { Gm, Em } },
2023 {"(bad)", { XX } },
2024 {"extrq", { XM, XS } },
2025 {"insertq", { XM, XS } },
2026 },
2027
1ceb70f8 2028 /* PREFIX_0F7C */
ca164297 2029 {
058f233b
L		 2030 { "(bad)", { XX } },
2031 { "(bad)", { XX } },
09a2c6cf
L		 2032 { "haddpd", { XM, EXx } },
2033 { "haddps", { XM, EXx } },
ca164297 2034 },
4e7d34a6 2035
1ceb70f8 2036 /* PREFIX_0F7D */
ca164297 2037 {
058f233b
L		 2038 { "(bad)", { XX } },
2039 { "(bad)", { XX } },
09a2c6cf
L		 2040 { "hsubpd", { XM, EXx } },
2041 { "hsubps", { XM, EXx } },
ca164297 2042 },
4e7d34a6 2043
1ceb70f8 2044 /* PREFIX_0F7E */
ca164297 2045 {
4e7d34a6
L		 2046 { "movK", { Edq, MX } },
2047 { "movq", { XM, EXq } },
2048 { "movK", { Edq, XM } },
058f233b 2049 { "(bad)", { XX } },
ca164297 2050 },
4e7d34a6 2051
1ceb70f8 2052 /* PREFIX_0F7F */
ca164297 2053 {
4e7d34a6
L		 2054 { "movq", { EM, MX } },
2055 { "movdqu", { EXx, XM } },
2056 { "movdqa", { EXx, XM } },
058f233b 2057 { "(bad)", { XX } },
ca164297 2058 },
4e7d34a6 2059
1ceb70f8 2060 /* PREFIX_0FB8 */
ca164297 2061 {
4e7d34a6
L		 2062 { "(bad)", { XX } },
2063 { "popcntS", { Gv, Ev } },
2064 { "(bad)", { XX } },
2065 { "(bad)", { XX } },
ca164297 2066 },
4e7d34a6 2067
1ceb70f8 2068 /* PREFIX_0FBD */
050dfa73 2069 {
4e7d34a6
L		 2070 { "bsrS", { Gv, Ev } },
2071 { "lzcntS", { Gv, Ev } },
2072 { "bsrS", { Gv, Ev } },
2073 { "(bad)", { XX } },
050dfa73
MM		 2074 },
2075
1ceb70f8 2076 /* PREFIX_0FC2 */
050dfa73 2077 {
4e7d34a6
L		 2078 { "", { XM, EXx, OPSIMD } }, /* See OP_SIMD_SUFFIX. */
2079 { "", { XM, EXd, OPSIMD } },
2080 { "", { XM, EXx, OPSIMD } },
2081 { "", { XM, EXq, OPSIMD } },
050dfa73 2082 },
246c51aa 2083
1ceb70f8 2084 /* PREFIX_0FD0 */
050dfa73 2085 {
058f233b
L		 2086 { "(bad)", { XX } },
2087 { "(bad)", { XX } },
4e7d34a6
L		 2088 { "addsubpd", { XM, EXx } },
2089 { "addsubps", { XM, EXx } },
246c51aa 2090 },
050dfa73 2091
1ceb70f8 2092 /* PREFIX_0FD6 */
050dfa73 2093 {
058f233b 2094 { "(bad)", { XX } },
4e7d34a6
L		 2095 { "movq2dq",{ XM, MS } },
2096 { "movq", { EXq, XM } },
2097 { "movdq2q",{ MX, XS } },
050dfa73
MM		 2098 },
2099
1ceb70f8 2100 /* PREFIX_0FE6 */
7918206c 2101 {
058f233b 2102 { "(bad)", { XX } },
4e7d34a6
L		 2103 { "cvtdq2pd", { XM, EXq } },
2104 { "cvttpd2dq", { XM, EXx } },
2105 { "cvtpd2dq", { XM, EXx } },
7918206c 2106 },
8b38ad71 2107
1ceb70f8 2108 /* PREFIX_0FE7 */
8b38ad71 2109 {
4e7d34a6 2110 { "movntq", { EM, MX } },
058f233b 2111 { "(bad)", { XX } },
4e7d34a6 2112 { "movntdq",{ EM, XM } },
058f233b 2113 { "(bad)", { XX } },
4e7d34a6
L		 2114 },
2115
1ceb70f8 2116 /* PREFIX_0FF0 */
4e7d34a6 2117 {
058f233b
L		 2118 { "(bad)", { XX } },
2119 { "(bad)", { XX } },
2120 { "(bad)", { XX } },
1ceb70f8 2121 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4e7d34a6
L		 2122 },
2123
1ceb70f8 2124 /* PREFIX_0FF7 */
4e7d34a6
L		 2125 {
2126 { "maskmovq", { MX, MS } },
058f233b 2127 { "(bad)", { XX } },
4e7d34a6 2128 { "maskmovdqu", { XM, XS } },
058f233b 2129 { "(bad)", { XX } },
8b38ad71 2130 },
42903f7f 2131
1ceb70f8 2132 /* PREFIX_0F3810 */
42903f7f
L		 2133 {
2134 { "(bad)", { XX } },
2135 { "(bad)", { XX } },
09a2c6cf 2136 { "pblendvb", {XM, EXx, XMM0 } },
42903f7f
L		 2137 { "(bad)", { XX } },
2138 },
2139
1ceb70f8 2140 /* PREFIX_0F3814 */
42903f7f
L		 2141 {
2142 { "(bad)", { XX } },
2143 { "(bad)", { XX } },
09a2c6cf 2144 { "blendvps", {XM, EXx, XMM0 } },
42903f7f
L		 2145 { "(bad)", { XX } },
2146 },
2147
1ceb70f8 2148 /* PREFIX_0F3815 */
42903f7f
L		 2149 {
2150 { "(bad)", { XX } },
2151 { "(bad)", { XX } },
09a2c6cf 2152 { "blendvpd", { XM, EXx, XMM0 } },
42903f7f
L		 2153 { "(bad)", { XX } },
2154 },
2155
1ceb70f8 2156 /* PREFIX_0F3817 */
42903f7f
L		 2157 {
2158 { "(bad)", { XX } },
2159 { "(bad)", { XX } },
09a2c6cf 2160 { "ptest", { XM, EXx } },
42903f7f
L		 2161 { "(bad)", { XX } },
2162 },
2163
1ceb70f8 2164 /* PREFIX_0F3820 */
42903f7f
L		 2165 {
2166 { "(bad)", { XX } },
2167 { "(bad)", { XX } },
8976381e 2168 { "pmovsxbw", { XM, EXq } },
42903f7f
L		 2169 { "(bad)", { XX } },
2170 },
2171
1ceb70f8 2172 /* PREFIX_0F3821 */
42903f7f
L		 2173 {
2174 { "(bad)", { XX } },
2175 { "(bad)", { XX } },
8976381e 2176 { "pmovsxbd", { XM, EXd } },
42903f7f
L		 2177 { "(bad)", { XX } },
2178 },
2179
1ceb70f8 2180 /* PREFIX_0F3822 */
42903f7f
L		 2181 {
2182 { "(bad)", { XX } },
2183 { "(bad)", { XX } },
8976381e 2184 { "pmovsxbq", { XM, EXw } },
42903f7f
L		 2185 { "(bad)", { XX } },
2186 },
2187
1ceb70f8 2188 /* PREFIX_0F3823 */
42903f7f
L		 2189 {
2190 { "(bad)", { XX } },
2191 { "(bad)", { XX } },
8976381e 2192 { "pmovsxwd", { XM, EXq } },
42903f7f
L		 2193 { "(bad)", { XX } },
2194 },
2195
1ceb70f8 2196 /* PREFIX_0F3824 */
42903f7f
L		 2197 {
2198 { "(bad)", { XX } },
2199 { "(bad)", { XX } },
8976381e 2200 { "pmovsxwq", { XM, EXd } },
42903f7f
L		 2201 { "(bad)", { XX } },
2202 },
2203
1ceb70f8 2204 /* PREFIX_0F3825 */
42903f7f
L		 2205 {
2206 { "(bad)", { XX } },
2207 { "(bad)", { XX } },
8976381e 2208 { "pmovsxdq", { XM, EXq } },
42903f7f
L		 2209 { "(bad)", { XX } },
2210 },
2211
1ceb70f8 2212 /* PREFIX_0F3828 */
42903f7f
L		 2213 {
2214 { "(bad)", { XX } },
2215 { "(bad)", { XX } },
09a2c6cf 2216 { "pmuldq", { XM, EXx } },
42903f7f
L		 2217 { "(bad)", { XX } },
2218 },
2219
1ceb70f8 2220 /* PREFIX_0F3829 */
42903f7f
L		 2221 {
2222 { "(bad)", { XX } },
2223 { "(bad)", { XX } },
09a2c6cf 2224 { "pcmpeqq", { XM, EXx } },
42903f7f
L		 2225 { "(bad)", { XX } },
2226 },
2227
1ceb70f8 2228 /* PREFIX_0F382A */
42903f7f
L		 2229 {
2230 { "(bad)", { XX } },
2231 { "(bad)", { XX } },
2232 { "movntdqa", { XM, EM } },
2233 { "(bad)", { XX } },
2234 },
2235
1ceb70f8 2236 /* PREFIX_0F382B */
42903f7f
L		 2237 {
2238 { "(bad)", { XX } },
2239 { "(bad)", { XX } },
09a2c6cf 2240 { "packusdw", { XM, EXx } },
42903f7f
L		 2241 { "(bad)", { XX } },
2242 },
2243
1ceb70f8 2244 /* PREFIX_0F3830 */
42903f7f
L		 2245 {
2246 { "(bad)", { XX } },
2247 { "(bad)", { XX } },
8976381e 2248 { "pmovzxbw", { XM, EXq } },
42903f7f
L		 2249 { "(bad)", { XX } },
2250 },
2251
1ceb70f8 2252 /* PREFIX_0F3831 */
42903f7f
L		 2253 {
2254 { "(bad)", { XX } },
2255 { "(bad)", { XX } },
8976381e 2256 { "pmovzxbd", { XM, EXd } },
42903f7f
L		 2257 { "(bad)", { XX } },
2258 },
2259
1ceb70f8 2260 /* PREFIX_0F3832 */
42903f7f
L		 2261 {
2262 { "(bad)", { XX } },
2263 { "(bad)", { XX } },
8976381e 2264 { "pmovzxbq", { XM, EXw } },
42903f7f
L		 2265 { "(bad)", { XX } },
2266 },
2267
1ceb70f8 2268 /* PREFIX_0F3833 */
42903f7f
L		 2269 {
2270 { "(bad)", { XX } },
2271 { "(bad)", { XX } },
8976381e 2272 { "pmovzxwd", { XM, EXq } },
42903f7f
L		 2273 { "(bad)", { XX } },
2274 },
2275
1ceb70f8 2276 /* PREFIX_0F3834 */
42903f7f
L		 2277 {
2278 { "(bad)", { XX } },
2279 { "(bad)", { XX } },
8976381e 2280 { "pmovzxwq", { XM, EXd } },
42903f7f
L		 2281 { "(bad)", { XX } },
2282 },
2283
1ceb70f8 2284 /* PREFIX_0F3835 */
42903f7f
L		 2285 {
2286 { "(bad)", { XX } },
2287 { "(bad)", { XX } },
8976381e 2288 { "pmovzxdq", { XM, EXq } },
42903f7f
L		 2289 { "(bad)", { XX } },
2290 },
2291
1ceb70f8 2292 /* PREFIX_0F3837 */
4e7d34a6
L		 2293 {
2294 { "(bad)", { XX } },
2295 { "(bad)", { XX } },
2296 { "pcmpgtq", { XM, EXx } },
2297 { "(bad)", { XX } },
2298 },
2299
1ceb70f8 2300 /* PREFIX_0F3838 */
42903f7f
L		 2301 {
2302 { "(bad)", { XX } },
2303 { "(bad)", { XX } },
09a2c6cf 2304 { "pminsb", { XM, EXx } },
42903f7f
L		 2305 { "(bad)", { XX } },
2306 },
2307
1ceb70f8 2308 /* PREFIX_0F3839 */
42903f7f
L		 2309 {
2310 { "(bad)", { XX } },
2311 { "(bad)", { XX } },
09a2c6cf 2312 { "pminsd", { XM, EXx } },
42903f7f
L		 2313 { "(bad)", { XX } },
2314 },
2315
1ceb70f8 2316 /* PREFIX_0F383A */
42903f7f
L		 2317 {
2318 { "(bad)", { XX } },
2319 { "(bad)", { XX } },
09a2c6cf 2320 { "pminuw", { XM, EXx } },
42903f7f
L		 2321 { "(bad)", { XX } },
2322 },
2323
1ceb70f8 2324 /* PREFIX_0F383B */
42903f7f
L		 2325 {
2326 { "(bad)", { XX } },
2327 { "(bad)", { XX } },
09a2c6cf 2328 { "pminud", { XM, EXx } },
42903f7f
L		 2329 { "(bad)", { XX } },
2330 },
2331
1ceb70f8 2332 /* PREFIX_0F383C */
42903f7f
L		 2333 {
2334 { "(bad)", { XX } },
2335 { "(bad)", { XX } },
09a2c6cf 2336 { "pmaxsb", { XM, EXx } },
42903f7f
L		 2337 { "(bad)", { XX } },
2338 },
2339
1ceb70f8 2340 /* PREFIX_0F383D */
42903f7f
L		 2341 {
2342 { "(bad)", { XX } },
2343 { "(bad)", { XX } },
09a2c6cf 2344 { "pmaxsd", { XM, EXx } },
42903f7f
L		 2345 { "(bad)", { XX } },
2346 },
2347
1ceb70f8 2348 /* PREFIX_0F383E */
42903f7f
L		 2349 {
2350 { "(bad)", { XX } },
2351 { "(bad)", { XX } },
09a2c6cf 2352 { "pmaxuw", { XM, EXx } },
42903f7f
L		 2353 { "(bad)", { XX } },
2354 },
2355
1ceb70f8 2356 /* PREFIX_0F383F */
42903f7f
L		 2357 {
2358 { "(bad)", { XX } },
2359 { "(bad)", { XX } },
09a2c6cf 2360 { "pmaxud", { XM, EXx } },
42903f7f
L		 2361 { "(bad)", { XX } },
2362 },
2363
1ceb70f8 2364 /* PREFIX_0F3840 */
42903f7f
L		 2365 {
2366 { "(bad)", { XX } },
2367 { "(bad)", { XX } },
09a2c6cf 2368 { "pmulld", { XM, EXx } },
42903f7f
L		 2369 { "(bad)", { XX } },
2370 },
2371
1ceb70f8 2372 /* PREFIX_0F3841 */
42903f7f
L		 2373 {
2374 { "(bad)", { XX } },
2375 { "(bad)", { XX } },
09a2c6cf 2376 { "phminposuw", { XM, EXx } },
42903f7f
L		 2377 { "(bad)", { XX } },
2378 },
2379
1ceb70f8 2380 /* PREFIX_0F38F0 */
4e7d34a6
L		 2381 {
2382 { "(bad)", { XX } },
2383 { "(bad)", { XX } },
2384 { "(bad)", { XX } },
2385 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
2386 },
2387
1ceb70f8 2388 /* PREFIX_0F38F1 */
4e7d34a6
L		 2389 {
2390 { "(bad)", { XX } },
2391 { "(bad)", { XX } },
2392 { "(bad)", { XX } },
2393 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
2394 },
2395
1ceb70f8 2396 /* PREFIX_0F3A08 */
42903f7f
L		 2397 {
2398 { "(bad)", { XX } },
2399 { "(bad)", { XX } },
09a2c6cf 2400 { "roundps", { XM, EXx, Ib } },
42903f7f
L		 2401 { "(bad)", { XX } },
2402 },
2403
1ceb70f8 2404 /* PREFIX_0F3A09 */
42903f7f
L		 2405 {
2406 { "(bad)", { XX } },
2407 { "(bad)", { XX } },
09a2c6cf 2408 { "roundpd", { XM, EXx, Ib } },
42903f7f
L		 2409 { "(bad)", { XX } },
2410 },
2411
1ceb70f8 2412 /* PREFIX_0F3A0A */
42903f7f
L		 2413 {
2414 { "(bad)", { XX } },
2415 { "(bad)", { XX } },
09335d05 2416 { "roundss", { XM, EXd, Ib } },
42903f7f
L		 2417 { "(bad)", { XX } },
2418 },
2419
1ceb70f8 2420 /* PREFIX_0F3A0B */
42903f7f
L		 2421 {
2422 { "(bad)", { XX } },
2423 { "(bad)", { XX } },
09335d05 2424 { "roundsd", { XM, EXq, Ib } },
42903f7f
L		 2425 { "(bad)", { XX } },
2426 },
2427
1ceb70f8 2428 /* PREFIX_0F3A0C */
42903f7f
L		 2429 {
2430 { "(bad)", { XX } },
2431 { "(bad)", { XX } },
09a2c6cf 2432 { "blendps", { XM, EXx, Ib } },
42903f7f
L		 2433 { "(bad)", { XX } },
2434 },
2435
1ceb70f8 2436 /* PREFIX_0F3A0D */
42903f7f
L		 2437 {
2438 { "(bad)", { XX } },
2439 { "(bad)", { XX } },
09a2c6cf 2440 { "blendpd", { XM, EXx, Ib } },
42903f7f
L		 2441 { "(bad)", { XX } },
2442 },
2443
1ceb70f8 2444 /* PREFIX_0F3A0E */
42903f7f
L		 2445 {
2446 { "(bad)", { XX } },
2447 { "(bad)", { XX } },
09a2c6cf 2448 { "pblendw", { XM, EXx, Ib } },
42903f7f
L		 2449 { "(bad)", { XX } },
2450 },
2451
1ceb70f8 2452 /* PREFIX_0F3A14 */
42903f7f
L		 2453 {
2454 { "(bad)", { XX } },
2455 { "(bad)", { XX } },
2456 { "pextrb", { Edqb, XM, Ib } },
2457 { "(bad)", { XX } },
2458 },
2459
1ceb70f8 2460 /* PREFIX_0F3A15 */
42903f7f
L		 2461 {
2462 { "(bad)", { XX } },
2463 { "(bad)", { XX } },
2464 { "pextrw", { Edqw, XM, Ib } },
2465 { "(bad)", { XX } },
2466 },
2467
1ceb70f8 2468 /* PREFIX_0F3A16 */
42903f7f
L		 2469 {
2470 { "(bad)", { XX } },
2471 { "(bad)", { XX } },
2472 { "pextrK", { Edq, XM, Ib } },
2473 { "(bad)", { XX } },
2474 },
2475
1ceb70f8 2476 /* PREFIX_0F3A17 */
42903f7f
L		 2477 {
2478 { "(bad)", { XX } },
2479 { "(bad)", { XX } },
2480 { "extractps", { Edqd, XM, Ib } },
2481 { "(bad)", { XX } },
2482 },
2483
1ceb70f8 2484 /* PREFIX_0F3A20 */
42903f7f
L		 2485 {
2486 { "(bad)", { XX } },
2487 { "(bad)", { XX } },
2488 { "pinsrb", { XM, Edqb, Ib } },
2489 { "(bad)", { XX } },
2490 },
2491
1ceb70f8 2492 /* PREFIX_0F3A21 */
42903f7f
L		 2493 {
2494 { "(bad)", { XX } },
2495 { "(bad)", { XX } },
8976381e 2496 { "insertps", { XM, EXd, Ib } },
42903f7f
L		 2497 { "(bad)", { XX } },
2498 },
2499
1ceb70f8 2500 /* PREFIX_0F3A22 */
42903f7f
L		 2501 {
2502 { "(bad)", { XX } },
2503 { "(bad)", { XX } },
2504 { "pinsrK", { XM, Edq, Ib } },
2505 { "(bad)", { XX } },
2506 },
2507
1ceb70f8 2508 /* PREFIX_0F3A40 */
42903f7f
L		 2509 {
2510 { "(bad)", { XX } },
2511 { "(bad)", { XX } },
09a2c6cf 2512 { "dpps", { XM, EXx, Ib } },
42903f7f
L		 2513 { "(bad)", { XX } },
2514 },
2515
1ceb70f8 2516 /* PREFIX_0F3A41 */
42903f7f
L		 2517 {
2518 { "(bad)", { XX } },
2519 { "(bad)", { XX } },
09a2c6cf 2520 { "dppd", { XM, EXx, Ib } },
42903f7f
L		 2521 { "(bad)", { XX } },
2522 },
2523
1ceb70f8 2524 /* PREFIX_0F3A42 */
42903f7f
L		 2525 {
2526 { "(bad)", { XX } },
2527 { "(bad)", { XX } },
09a2c6cf 2528 { "mpsadbw", { XM, EXx, Ib } },
42903f7f
L		 2529 { "(bad)", { XX } },
2530 },
381d071f 2531
1ceb70f8 2532 /* PREFIX_0F3A60 */
381d071f
L		 2533 {
2534 { "(bad)", { XX } },
2535 { "(bad)", { XX } },
4e7d34a6 2536 { "pcmpestrm", { XM, EXx, Ib } },
381d071f
L		 2537 { "(bad)", { XX } },
2538 },
2539
1ceb70f8 2540 /* PREFIX_0F3A61 */
381d071f
L		 2541 {
2542 { "(bad)", { XX } },
2543 { "(bad)", { XX } },
4e7d34a6 2544 { "pcmpestri", { XM, EXx, Ib } },
381d071f 2545 { "(bad)", { XX } },
381d071f
L		 2546 },
2547
1ceb70f8 2548 /* PREFIX_0F3A62 */
381d071f
L		 2549 {
2550 { "(bad)", { XX } },
2551 { "(bad)", { XX } },
4e7d34a6 2552 { "pcmpistrm", { XM, EXx, Ib } },
381d071f 2553 { "(bad)", { XX } },
381d071f
L		 2554 },
2555
1ceb70f8 2556 /* PREFIX_0F3A63 */
381d071f
L		 2557 {
2558 { "(bad)", { XX } },
2559 { "(bad)", { XX } },
4e7d34a6 2560 { "pcmpistri", { XM, EXx, Ib } },
381d071f
L		 2561 { "(bad)", { XX } },
2562 },
2563
1ceb70f8 2564 /* PREFIX_0F73_REG_3 */
381d071f
L		 2565 {
2566 { "(bad)", { XX } },
2567 { "(bad)", { XX } },
4e7d34a6 2568 { "psrldq", { MS, Ib } },
381d071f
L		 2569 { "(bad)", { XX } },
2570 },
2571
1ceb70f8 2572 /* PREFIX_0F73_REG_7 */
381d071f
L		 2573 {
2574 { "(bad)", { XX } },
2575 { "(bad)", { XX } },
4e7d34a6 2576 { "pslldq", { MS, Ib } },
381d071f
L		 2577 { "(bad)", { XX } },
2578 },
2579
4584a60d 2580 /* PREFIX_0FC7_REG_6 */
381d071f 2581 {
4e7d34a6
L		 2582 { "vmptrld",{ Mq } },
2583 { "vmxon", { Mq } },
2584 { "vmclear",{ Mq } },
09a2c6cf
L		 2585 { "(bad)", { XX } },
2586 },
4e7d34a6 2587};
09a2c6cf 2588
4e7d34a6
L		 2589static const struct dis386 x86_64_table[][2] = {
2590 /* X86_64_06 */
09a2c6cf 2591 {
4e7d34a6
L		 2592 { "push{T|}", { es } },
2593 { "(bad)", { XX } },
09a2c6cf
L		 2594 },
2595
4e7d34a6 2596 /* X86_64_07 */
09a2c6cf 2597 {
4e7d34a6
L		 2598 { "pop{T|}", { es } },
2599 { "(bad)", { XX } },
09a2c6cf
L		 2600 },
2601
4e7d34a6 2602 /* X86_64_0D */
09a2c6cf 2603 {
4e7d34a6
L		 2604 { "push{T|}", { cs } },
2605 { "(bad)", { XX } },
09a2c6cf
L		 2606 },
2607
4e7d34a6 2608 /* X86_64_16 */
09a2c6cf 2609 {
4e7d34a6
L		 2610 { "push{T|}", { ss } },
2611 { "(bad)", { XX } },
09a2c6cf
L		 2612 },
2613
4e7d34a6 2614 /* X86_64_17 */
09a2c6cf 2615 {
4e7d34a6 2616 { "pop{T|}", { ss } },
ce518a5f 2617 { "(bad)", { XX } },
5f754f58 2618 },
7c52e0e8 2619
4e7d34a6 2620 /* X86_64_1E */
5f754f58 2621 {
4e7d34a6 2622 { "push{T|}", { ds } },
ce518a5f 2623 { "(bad)", { XX } },
5f754f58 2624 },
7c52e0e8 2625
4e7d34a6 2626 /* X86_64_1F */
5f754f58 2627 {
4e7d34a6 2628 { "pop{T|}", { ds } },
ce518a5f 2629 { "(bad)", { XX } },
5f754f58 2630 },
7c52e0e8 2631
4e7d34a6 2632 /* X86_64_27 */
7c52e0e8 2633 {
4e7d34a6 2634 { "daa", { XX } },
7c52e0e8
L		 2635 { "(bad)", { XX } },
2636 },
2637
4e7d34a6 2638 /* X86_64_2F */
7c52e0e8 2639 {
4e7d34a6 2640 { "das", { XX } },
7c52e0e8
L		 2641 { "(bad)", { XX } },
2642 },
2643
4e7d34a6 2644 /* X86_64_37 */
7c52e0e8 2645 {
4e7d34a6 2646 { "aaa", { XX } },
7c52e0e8
L		 2647 { "(bad)", { XX } },
2648 },
2649
4e7d34a6 2650 /* X86_64_3F */
7c52e0e8 2651 {
4e7d34a6 2652 { "aas", { XX } },
7c52e0e8
L		 2653 { "(bad)", { XX } },
2654 },
2655
4e7d34a6 2656 /* X86_64_60 */
7c52e0e8 2657 {
4e7d34a6 2658 { "pusha{P|}", { XX } },
7c52e0e8
L		 2659 { "(bad)", { XX } },
2660 },
2661
4e7d34a6 2662 /* X86_64_61 */
7c52e0e8 2663 {
4e7d34a6 2664 { "popa{P|}", { XX } },
7c52e0e8
L		 2665 { "(bad)", { XX } },
2666 },
2667
4e7d34a6 2668 /* X86_64_62 */
7c52e0e8 2669 {
1ceb70f8 2670 { MOD_TABLE (MOD_62_32BIT) },
7c52e0e8
L		 2671 { "(bad)", { XX } },
2672 },
2673
4e7d34a6 2674 /* X86_64_63 */
7c52e0e8 2675 {
4e7d34a6
L		 2676 { "arpl", { Ew, Gw } },
2677 { "movs{lq|xd}", { Gv, Ed } },
7c52e0e8
L		 2678 },
2679
4e7d34a6 2680 /* X86_64_6D */
7c52e0e8 2681 {
4e7d34a6
L		 2682 { "ins{R|}", { Yzr, indirDX } },
2683 { "ins{G|}", { Yzr, indirDX } },
7c52e0e8
L		 2684 },
2685
4e7d34a6 2686 /* X86_64_6F */
7c52e0e8 2687 {
4e7d34a6
L		 2688 { "outs{R|}", { indirDXr, Xz } },
2689 { "outs{G|}", { indirDXr, Xz } },
7c52e0e8
L		 2690 },
2691
4e7d34a6 2692 /* X86_64_9A */
7c52e0e8 2693 {
4e7d34a6 2694 { "Jcall{T|}", { Ap } },
7c52e0e8
L		 2695 { "(bad)", { XX } },
2696 },
2697
4e7d34a6 2698 /* X86_64_C4 */
7c52e0e8 2699 {
1ceb70f8 2700 { MOD_TABLE (MOD_C4_32BIT) },
4e7d34a6 2701 { "(bad)", { XX } },
7c52e0e8
L		 2702 },
2703
4e7d34a6 2704 /* X86_64_C5 */
7c52e0e8 2705 {
1ceb70f8 2706 { MOD_TABLE (MOD_C5_32BIT) },
7c52e0e8
L		 2707 { "(bad)", { XX } },
2708 },
2709
4e7d34a6 2710 /* X86_64_CE */
7c52e0e8
L		 2711 {
2712 { "into", { XX } },
2713 { "(bad)", { XX } },
2714 },
2715
4e7d34a6 2716 /* X86_64_D4 */
7c52e0e8
L		 2717 {
2718 { "aam", { sIb } },
2719 { "(bad)", { XX } },
2720 },
2721
4e7d34a6 2722 /* X86_64_D5 */
7c52e0e8
L		 2723 {
2724 { "aad", { sIb } },
2725 { "(bad)", { XX } },
2726 },
2727
4e7d34a6 2728 /* X86_64_EA */
7c52e0e8
L		 2729 {
2730 { "Jjmp{T|}", { Ap } },
2731 { "(bad)", { XX } },
2732 },
2733
4e7d34a6 2734 /* X86_64_0F01_REG_0 */
7c52e0e8
L		 2735 {
2736 { "sgdt{Q|IQ}", { M } },
2737 { "sgdt", { M } },
2738 },
2739
4e7d34a6 2740 /* X86_64_0F01_REG_1 */
7c52e0e8
L		 2741 {
2742 { "sidt{Q|IQ}", { M } },
2743 { "sidt", { M } },
2744 },
2745
4e7d34a6 2746 /* X86_64_0F01_REG_2 */
7c52e0e8
L		 2747 {
2748 { "lgdt{Q|Q}", { M } },
2749 { "lgdt", { M } },
2750 },
2751
4e7d34a6 2752 /* X86_64_0F01_REG_3 */
7c52e0e8
L		 2753 {
2754 { "lidt{Q|Q}", { M } },
2755 { "lidt", { M } },
2756 },
6439fc28
AM		 2757};
2758
96fbad73 2759static const struct dis386 three_byte_table[][256] = {
4e7d34a6 2760 /* THREE_BYTE_0F24 */
331d2d0d 2761 {
96fbad73 2762 /* 00 */
4e7d34a6
L		 2763 { "fmaddps", { { OP_DREX4, q_mode } } },
2764 { "fmaddpd", { { OP_DREX4, q_mode } } },
2765 { "fmaddss", { { OP_DREX4, w_mode } } },
2766 { "fmaddsd", { { OP_DREX4, d_mode } } },
2767 { "fmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2768 { "fmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2769 { "fmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2770 { "fmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
96fbad73 2771 /* 08 */
4e7d34a6
L		 2772 { "fmsubps", { { OP_DREX4, q_mode } } },
2773 { "fmsubpd", { { OP_DREX4, q_mode } } },
2774 { "fmsubss", { { OP_DREX4, w_mode } } },
2775 { "fmsubsd", { { OP_DREX4, d_mode } } },
2776 { "fmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2777 { "fmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2778 { "fmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2779 { "fmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
85f10a01 2780 /* 10 */
4e7d34a6
L		 2781 { "fnmaddps", { { OP_DREX4, q_mode } } },
2782 { "fnmaddpd", { { OP_DREX4, q_mode } } },
2783 { "fnmaddss", { { OP_DREX4, w_mode } } },
2784 { "fnmaddsd", { { OP_DREX4, d_mode } } },
2785 { "fnmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2786 { "fnmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2787 { "fnmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2788 { "fnmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
85f10a01 2789 /* 18 */
4e7d34a6
L		 2790 { "fnmsubps", { { OP_DREX4, q_mode } } },
2791 { "fnmsubpd", { { OP_DREX4, q_mode } } },
2792 { "fnmsubss", { { OP_DREX4, w_mode } } },
2793 { "fnmsubsd", { { OP_DREX4, d_mode } } },
2794 { "fnmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2795 { "fnmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2796 { "fnmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
2797 { "fnmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
85f10a01 2798 /* 20 */
4e7d34a6
L		 2799 { "permps", { { OP_DREX4, q_mode } } },
2800 { "permpd", { { OP_DREX4, q_mode } } },
2801 { "pcmov", { { OP_DREX4, q_mode } } },
2802 { "pperm", { { OP_DREX4, q_mode } } },
2803 { "permps", { { OP_DREX4, DREX_OC1 + q_mode } } },
2804 { "permpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
2805 { "pcmov", { { OP_DREX4, DREX_OC1 + w_mode } } },
2806 { "pperm", { { OP_DREX4, DREX_OC1 + d_mode } } },
85f10a01 2807 /* 28 */
4e7d34a6
L		 2808 { "(bad)", { XX } },
2809 { "(bad)", { XX } },
2810 { "(bad)", { XX } },
2811 { "(bad)", { XX } },
2812 { "(bad)", { XX } },
2813 { "(bad)", { XX } },
2814 { "(bad)", { XX } },
2815 { "(bad)", { XX } },
85f10a01 2816 /* 30 */
4e7d34a6
L		 2817 { "(bad)", { XX } },
2818 { "(bad)", { XX } },
2819 { "(bad)", { XX } },
2820 { "(bad)", { XX } },
2821 { "(bad)", { XX } },
2822 { "(bad)", { XX } },
2823 { "(bad)", { XX } },
2824 { "(bad)", { XX } },
85f10a01 2825 /* 38 */
4e7d34a6
L		 2826 { "(bad)", { XX } },
2827 { "(bad)", { XX } },
2828 { "(bad)", { XX } },
2829 { "(bad)", { XX } },
2830 { "(bad)", { XX } },
2831 { "(bad)", { XX } },
2832 { "(bad)", { XX } },
2833 { "(bad)", { XX } },
85f10a01 2834 /* 40 */
4e7d34a6
L		 2835 { "protb", { { OP_DREX3, q_mode } } },
2836 { "protw", { { OP_DREX3, q_mode } } },
2837 { "protd", { { OP_DREX3, q_mode } } },
2838 { "protq", { { OP_DREX3, q_mode } } },
2839 { "pshlb", { { OP_DREX3, q_mode } } },
2840 { "pshlw", { { OP_DREX3, q_mode } } },
2841 { "pshld", { { OP_DREX3, q_mode } } },
2842 { "pshlq", { { OP_DREX3, q_mode } } },
85f10a01 2843 /* 48 */
4e7d34a6
L		 2844 { "pshab", { { OP_DREX3, q_mode } } },
2845 { "pshaw", { { OP_DREX3, q_mode } } },
2846 { "pshad", { { OP_DREX3, q_mode } } },
2847 { "pshaq", { { OP_DREX3, q_mode } } },
2848 { "(bad)", { XX } },
2849 { "(bad)", { XX } },
2850 { "(bad)", { XX } },
2851 { "(bad)", { XX } },
85f10a01 2852 /* 50 */
4e7d34a6
L		 2853 { "(bad)", { XX } },
2854 { "(bad)", { XX } },
2855 { "(bad)", { XX } },
2856 { "(bad)", { XX } },
2857 { "(bad)", { XX } },
2858 { "(bad)", { XX } },
2859 { "(bad)", { XX } },
2860 { "(bad)", { XX } },
85f10a01 2861 /* 58 */
4e7d34a6
L		 2862 { "(bad)", { XX } },
2863 { "(bad)", { XX } },
2864 { "(bad)", { XX } },
2865 { "(bad)", { XX } },
2866 { "(bad)", { XX } },
2867 { "(bad)", { XX } },
2868 { "(bad)", { XX } },
2869 { "(bad)", { XX } },
85f10a01 2870 /* 60 */
4e7d34a6
L		 2871 { "(bad)", { XX } },
2872 { "(bad)", { XX } },
2873 { "(bad)", { XX } },
2874 { "(bad)", { XX } },
2875 { "(bad)", { XX } },
2876 { "(bad)", { XX } },
2877 { "(bad)", { XX } },
2878 { "(bad)", { XX } },
2879 /* 68 */
2880 { "(bad)", { XX } },
2881 { "(bad)", { XX } },
2882 { "(bad)", { XX } },
2883 { "(bad)", { XX } },
2884 { "(bad)", { XX } },
2885 { "(bad)", { XX } },
2886 { "(bad)", { XX } },
2887 { "(bad)", { XX } },
85f10a01 2888 /* 70 */
4e7d34a6
L		 2889 { "(bad)", { XX } },
2890 { "(bad)", { XX } },
2891 { "(bad)", { XX } },
2892 { "(bad)", { XX } },
2893 { "(bad)", { XX } },
2894 { "(bad)", { XX } },
2895 { "(bad)", { XX } },
2896 { "(bad)", { XX } },
85f10a01 2897 /* 78 */
4e7d34a6
L		 2898 { "(bad)", { XX } },
2899 { "(bad)", { XX } },
2900 { "(bad)", { XX } },
2901 { "(bad)", { XX } },
2902 { "(bad)", { XX } },
2903 { "(bad)", { XX } },
2904 { "(bad)", { XX } },
2905 { "(bad)", { XX } },
85f10a01 2906 /* 80 */
4e7d34a6
L		 2907 { "(bad)", { XX } },
2908 { "(bad)", { XX } },
2909 { "(bad)", { XX } },
2910 { "(bad)", { XX } },
2911 { "(bad)", { XX } },
2912 { "pmacssww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2913 { "pmacsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2914 { "pmacssdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
85f10a01 2915 /* 88 */
4e7d34a6
L		 2916 { "(bad)", { XX } },
2917 { "(bad)", { XX } },
2918 { "(bad)", { XX } },
2919 { "(bad)", { XX } },
2920 { "(bad)", { XX } },
2921 { "(bad)", { XX } },
2922 { "pmacssdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2923 { "pmacssdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
85f10a01 2924 /* 90 */
4e7d34a6
L		 2925 { "(bad)", { XX } },
2926 { "(bad)", { XX } },
2927 { "(bad)", { XX } },
2928 { "(bad)", { XX } },
2929 { "(bad)", { XX } },
2930 { "pmacsww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2931 { "pmacswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2932 { "pmacsdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
85f10a01 2933 /* 98 */
4e7d34a6
L		 2934 { "(bad)", { XX } },
2935 { "(bad)", { XX } },
2936 { "(bad)", { XX } },
2937 { "(bad)", { XX } },
2938 { "(bad)", { XX } },
2939 { "(bad)", { XX } },
2940 { "pmacsdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2941 { "pmacsdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
85f10a01 2942 /* a0 */
4e7d34a6
L		 2943 { "(bad)", { XX } },
2944 { "(bad)", { XX } },
2945 { "(bad)", { XX } },
2946 { "(bad)", { XX } },
2947 { "(bad)", { XX } },
2948 { "(bad)", { XX } },
2949 { "pmadcsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2950 { "(bad)", { XX } },
85f10a01 2951 /* a8 */
4e7d34a6
L		 2952 { "(bad)", { XX } },
2953 { "(bad)", { XX } },
2954 { "(bad)", { XX } },
2955 { "(bad)", { XX } },
2956 { "(bad)", { XX } },
2957 { "(bad)", { XX } },
2958 { "(bad)", { XX } },
2959 { "(bad)", { XX } },
85f10a01 2960 /* b0 */
4e7d34a6
L		 2961 { "(bad)", { XX } },
2962 { "(bad)", { XX } },
2963 { "(bad)", { XX } },
2964 { "(bad)", { XX } },
2965 { "(bad)", { XX } },
2966 { "(bad)", { XX } },
2967 { "pmadcswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
2968 { "(bad)", { XX } },
85f10a01 2969 /* b8 */
4e7d34a6
L		 2970 { "(bad)", { XX } },
2971 { "(bad)", { XX } },
2972 { "(bad)", { XX } },
2973 { "(bad)", { XX } },
2974 { "(bad)", { XX } },
2975 { "(bad)", { XX } },
2976 { "(bad)", { XX } },
2977 { "(bad)", { XX } },
85f10a01 2978 /* c0 */
4e7d34a6
L		 2979 { "(bad)", { XX } },
2980 { "(bad)", { XX } },
2981 { "(bad)", { XX } },
2982 { "(bad)", { XX } },
2983 { "(bad)", { XX } },
2984 { "(bad)", { XX } },
2985 { "(bad)", { XX } },
2986 { "(bad)", { XX } },
85f10a01 2987 /* c8 */
4e7d34a6
L		 2988 { "(bad)", { XX } },
2989 { "(bad)", { XX } },
2990 { "(bad)", { XX } },
2991 { "(bad)", { XX } },
2992 { "(bad)", { XX } },
2993 { "(bad)", { XX } },
2994 { "(bad)", { XX } },
2995 { "(bad)", { XX } },
85f10a01 2996 /* d0 */
4e7d34a6
L		 2997 { "(bad)", { XX } },
2998 { "(bad)", { XX } },
2999 { "(bad)", { XX } },
3000 { "(bad)", { XX } },
3001 { "(bad)", { XX } },
3002 { "(bad)", { XX } },
3003 { "(bad)", { XX } },
3004 { "(bad)", { XX } },
85f10a01 3005 /* d8 */
4e7d34a6
L		 3006 { "(bad)", { XX } },
3007 { "(bad)", { XX } },
3008 { "(bad)", { XX } },
3009 { "(bad)", { XX } },
3010 { "(bad)", { XX } },
3011 { "(bad)", { XX } },
3012 { "(bad)", { XX } },
3013 { "(bad)", { XX } },
85f10a01 3014 /* e0 */
4e7d34a6
L		 3015 { "(bad)", { XX } },
3016 { "(bad)", { XX } },
3017 { "(bad)", { XX } },
3018 { "(bad)", { XX } },
3019 { "(bad)", { XX } },
3020 { "(bad)", { XX } },
3021 { "(bad)", { XX } },
3022 { "(bad)", { XX } },
85f10a01 3023 /* e8 */
4e7d34a6
L		 3024 { "(bad)", { XX } },
3025 { "(bad)", { XX } },
3026 { "(bad)", { XX } },
3027 { "(bad)", { XX } },
3028 { "(bad)", { XX } },
3029 { "(bad)", { XX } },
3030 { "(bad)", { XX } },
3031 { "(bad)", { XX } },
85f10a01 3032 /* f0 */
4e7d34a6
L		 3033 { "(bad)", { XX } },
3034 { "(bad)", { XX } },
3035 { "(bad)", { XX } },
3036 { "(bad)", { XX } },
3037 { "(bad)", { XX } },
3038 { "(bad)", { XX } },
3039 { "(bad)", { XX } },
3040 { "(bad)", { XX } },
85f10a01 3041 /* f8 */
4e7d34a6
L		 3042 { "(bad)", { XX } },
3043 { "(bad)", { XX } },
3044 { "(bad)", { XX } },
3045 { "(bad)", { XX } },
3046 { "(bad)", { XX } },
3047 { "(bad)", { XX } },
3048 { "(bad)", { XX } },
3049 { "(bad)", { XX } },
85f10a01 3050 },
4e7d34a6 3051 /* THREE_BYTE_0F25 */
85f10a01
MM		 3052 {
3053 /* 00 */
4e7d34a6
L		 3054 { "(bad)", { XX } },
3055 { "(bad)", { XX } },
3056 { "(bad)", { XX } },
3057 { "(bad)", { XX } },
3058 { "(bad)", { XX } },
3059 { "(bad)", { XX } },
3060 { "(bad)", { XX } },
3061 { "(bad)", { XX } },
85f10a01 3062 /* 08 */
4e7d34a6
L		 3063 { "(bad)", { XX } },
3064 { "(bad)", { XX } },
3065 { "(bad)", { XX } },
3066 { "(bad)", { XX } },
3067 { "(bad)", { XX } },
3068 { "(bad)", { XX } },
3069 { "(bad)", { XX } },
3070 { "(bad)", { XX } },
85f10a01 3071 /* 10 */
4e7d34a6
L		 3072 { "(bad)", { XX } },
3073 { "(bad)", { XX } },
3074 { "(bad)", { XX } },
3075 { "(bad)", { XX } },
3076 { "(bad)", { XX } },
3077 { "(bad)", { XX } },
3078 { "(bad)", { XX } },
3079 { "(bad)", { XX } },
85f10a01 3080 /* 18 */
4e7d34a6
L		 3081 { "(bad)", { XX } },
3082 { "(bad)", { XX } },
3083 { "(bad)", { XX } },
3084 { "(bad)", { XX } },
3085 { "(bad)", { XX } },
3086 { "(bad)", { XX } },
3087 { "(bad)", { XX } },
3088 { "(bad)", { XX } },
85f10a01 3089 /* 20 */
4e7d34a6
L		 3090 { "(bad)", { XX } },
3091 { "(bad)", { XX } },
3092 { "(bad)", { XX } },
3093 { "(bad)", { XX } },
3094 { "(bad)", { XX } },
3095 { "(bad)", { XX } },
3096 { "(bad)", { XX } },
3097 { "(bad)", { XX } },
85f10a01 3098 /* 28 */
4e7d34a6
L		 3099 { "(bad)", { XX } },
3100 { "(bad)", { XX } },
3101 { "(bad)", { XX } },
3102 { "(bad)", { XX } },
3103 { "comps", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
3104 { "compd", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
3105 { "comss", { { OP_DREX3, w_mode }, { OP_DREX_FCMP, b_mode } } },
3106 { "comsd", { { OP_DREX3, d_mode }, { OP_DREX_FCMP, b_mode } } },
85f10a01 3107 /* 30 */
4e7d34a6
L		 3108 { "(bad)", { XX } },
3109 { "(bad)", { XX } },
3110 { "(bad)", { XX } },
3111 { "(bad)", { XX } },
3112 { "(bad)", { XX } },
3113 { "(bad)", { XX } },
3114 { "(bad)", { XX } },
3115 { "(bad)", { XX } },
85f10a01 3116 /* 38 */
4e7d34a6
L		 3117 { "(bad)", { XX } },
3118 { "(bad)", { XX } },
3119 { "(bad)", { XX } },
3120 { "(bad)", { XX } },
3121 { "(bad)", { XX } },
3122 { "(bad)", { XX } },
3123 { "(bad)", { XX } },
3124 { "(bad)", { XX } },
85f10a01 3125 /* 40 */
4e7d34a6
L		 3126 { "(bad)", { XX } },
3127 { "(bad)", { XX } },
3128 { "(bad)", { XX } },
3129 { "(bad)", { XX } },
3130 { "(bad)", { XX } },
3131 { "(bad)", { XX } },
3132 { "(bad)", { XX } },
3133 { "(bad)", { XX } },
85f10a01 3134 /* 48 */
4e7d34a6
L		 3135 { "(bad)", { XX } },
3136 { "(bad)", { XX } },
3137 { "(bad)", { XX } },
3138 { "(bad)", { XX } },
3139 { "pcomb", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3140 { "pcomw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3141 { "pcomd", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3142 { "pcomq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
85f10a01 3143 /* 50 */
4e7d34a6
L		 3144 { "(bad)", { XX } },
3145 { "(bad)", { XX } },
3146 { "(bad)", { XX } },
3147 { "(bad)", { XX } },
3148 { "(bad)", { XX } },
3149 { "(bad)", { XX } },
3150 { "(bad)", { XX } },
3151 { "(bad)", { XX } },
85f10a01 3152 /* 58 */
4e7d34a6
L		 3153 { "(bad)", { XX } },
3154 { "(bad)", { XX } },
3155 { "(bad)", { XX } },
3156 { "(bad)", { XX } },
3157 { "(bad)", { XX } },
3158 { "(bad)", { XX } },
3159 { "(bad)", { XX } },
3160 { "(bad)", { XX } },
85f10a01 3161 /* 60 */
4e7d34a6
L		 3162 { "(bad)", { XX } },
3163 { "(bad)", { XX } },
3164 { "(bad)", { XX } },
3165 { "(bad)", { XX } },
3166 { "(bad)", { XX } },
3167 { "(bad)", { XX } },
3168 { "(bad)", { XX } },
3169 { "(bad)", { XX } },
85f10a01 3170 /* 68 */
4e7d34a6
L		 3171 { "(bad)", { XX } },
3172 { "(bad)", { XX } },
3173 { "(bad)", { XX } },
3174 { "(bad)", { XX } },
3175 { "pcomub", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3176 { "pcomuw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3177 { "pcomud", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
3178 { "pcomuq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
85f10a01 3179 /* 70 */
4e7d34a6
L		 3180 { "(bad)", { XX } },
3181 { "(bad)", { XX } },
3182 { "(bad)", { XX } },
3183 { "(bad)", { XX } },
3184 { "(bad)", { XX } },
3185 { "(bad)", { XX } },
3186 { "(bad)", { XX } },
3187 { "(bad)", { XX } },
85f10a01 3188 /* 78 */
4e7d34a6
L		 3189 { "(bad)", { XX } },
3190 { "(bad)", { XX } },
3191 { "(bad)", { XX } },
3192 { "(bad)", { XX } },
3193 { "(bad)", { XX } },
3194 { "(bad)", { XX } },
3195 { "(bad)", { XX } },
3196 { "(bad)", { XX } },
85f10a01 3197 /* 80 */
4e7d34a6
L		 3198 { "(bad)", { XX } },
3199 { "(bad)", { XX } },
3200 { "(bad)", { XX } },
3201 { "(bad)", { XX } },
3202 { "(bad)", { XX } },
3203 { "(bad)", { XX } },
3204 { "(bad)", { XX } },
3205 { "(bad)", { XX } },
3206 /* 88 */
3207 { "(bad)", { XX } },
3208 { "(bad)", { XX } },
3209 { "(bad)", { XX } },
3210 { "(bad)", { XX } },
3211 { "(bad)", { XX } },
3212 { "(bad)", { XX } },
3213 { "(bad)", { XX } },
3214 { "(bad)", { XX } },
3215 /* 90 */
3216 { "(bad)", { XX } },
3217 { "(bad)", { XX } },
3218 { "(bad)", { XX } },
3219 { "(bad)", { XX } },
3220 { "(bad)", { XX } },
3221 { "(bad)", { XX } },
3222 { "(bad)", { XX } },
3223 { "(bad)", { XX } },
3224 /* 98 */
3225 { "(bad)", { XX } },
3226 { "(bad)", { XX } },
3227 { "(bad)", { XX } },
3228 { "(bad)", { XX } },
3229 { "(bad)", { XX } },
3230 { "(bad)", { XX } },
3231 { "(bad)", { XX } },
3232 { "(bad)", { XX } },
3233 /* a0 */
3234 { "(bad)", { XX } },
3235 { "(bad)", { XX } },
3236 { "(bad)", { XX } },
3237 { "(bad)", { XX } },
3238 { "(bad)", { XX } },
3239 { "(bad)", { XX } },
3240 { "(bad)", { XX } },
3241 { "(bad)", { XX } },
3242 /* a8 */
3243 { "(bad)", { XX } },
3244 { "(bad)", { XX } },
3245 { "(bad)", { XX } },
3246 { "(bad)", { XX } },
3247 { "(bad)", { XX } },
3248 { "(bad)", { XX } },
3249 { "(bad)", { XX } },
3250 { "(bad)", { XX } },
3251 /* b0 */
3252 { "(bad)", { XX } },
3253 { "(bad)", { XX } },
3254 { "(bad)", { XX } },
3255 { "(bad)", { XX } },
3256 { "(bad)", { XX } },
3257 { "(bad)", { XX } },
3258 { "(bad)", { XX } },
3259 { "(bad)", { XX } },
3260 /* b8 */
3261 { "(bad)", { XX } },
3262 { "(bad)", { XX } },
3263 { "(bad)", { XX } },
3264 { "(bad)", { XX } },
3265 { "(bad)", { XX } },
3266 { "(bad)", { XX } },
3267 { "(bad)", { XX } },
3268 { "(bad)", { XX } },
3269 /* c0 */
3270 { "(bad)", { XX } },
3271 { "(bad)", { XX } },
3272 { "(bad)", { XX } },
3273 { "(bad)", { XX } },
3274 { "(bad)", { XX } },
3275 { "(bad)", { XX } },
3276 { "(bad)", { XX } },
3277 { "(bad)", { XX } },
3278 /* c8 */
3279 { "(bad)", { XX } },
3280 { "(bad)", { XX } },
3281 { "(bad)", { XX } },
3282 { "(bad)", { XX } },
3283 { "(bad)", { XX } },
3284 { "(bad)", { XX } },
3285 { "(bad)", { XX } },
3286 { "(bad)", { XX } },
3287 /* d0 */
3288 { "(bad)", { XX } },
3289 { "(bad)", { XX } },
3290 { "(bad)", { XX } },
3291 { "(bad)", { XX } },
3292 { "(bad)", { XX } },
3293 { "(bad)", { XX } },
3294 { "(bad)", { XX } },
3295 { "(bad)", { XX } },
3296 /* d8 */
3297 { "(bad)", { XX } },
3298 { "(bad)", { XX } },
3299 { "(bad)", { XX } },
3300 { "(bad)", { XX } },
3301 { "(bad)", { XX } },
3302 { "(bad)", { XX } },
3303 { "(bad)", { XX } },
3304 { "(bad)", { XX } },
3305 /* e0 */
3306 { "(bad)", { XX } },
3307 { "(bad)", { XX } },
3308 { "(bad)", { XX } },
3309 { "(bad)", { XX } },
3310 { "(bad)", { XX } },
3311 { "(bad)", { XX } },
3312 { "(bad)", { XX } },
3313 { "(bad)", { XX } },
3314 /* e8 */
3315 { "(bad)", { XX } },
3316 { "(bad)", { XX } },
3317 { "(bad)", { XX } },
3318 { "(bad)", { XX } },
3319 { "(bad)", { XX } },
3320 { "(bad)", { XX } },
3321 { "(bad)", { XX } },
3322 { "(bad)", { XX } },
3323 /* f0 */
3324 { "(bad)", { XX } },
3325 { "(bad)", { XX } },
3326 { "(bad)", { XX } },
3327 { "(bad)", { XX } },
3328 { "(bad)", { XX } },
3329 { "(bad)", { XX } },
3330 { "(bad)", { XX } },
3331 { "(bad)", { XX } },
3332 /* f8 */
3333 { "(bad)", { XX } },
3334 { "(bad)", { XX } },
3335 { "(bad)", { XX } },
3336 { "(bad)", { XX } },
3337 { "(bad)", { XX } },
3338 { "(bad)", { XX } },
3339 { "(bad)", { XX } },
3340 { "(bad)", { XX } },
3341 },
3342 /* THREE_BYTE_0F38 */
3343 {
3344 /* 00 */
3345 { "pshufb", { MX, EM } },
3346 { "phaddw", { MX, EM } },
3347 { "phaddd", { MX, EM } },
3348 { "phaddsw", { MX, EM } },
3349 { "pmaddubsw", { MX, EM } },
3350 { "phsubw", { MX, EM } },
3351 { "phsubd", { MX, EM } },
3352 { "phsubsw", { MX, EM } },
3353 /* 08 */
3354 { "psignb", { MX, EM } },
3355 { "psignw", { MX, EM } },
3356 { "psignd", { MX, EM } },
3357 { "pmulhrsw", { MX, EM } },
85f10a01
MM		 3358 { "(bad)", { XX } },
3359 { "(bad)", { XX } },
3360 { "(bad)", { XX } },
3361 { "(bad)", { XX } },
4e7d34a6 3362 /* 10 */
1ceb70f8 3363 { PREFIX_TABLE (PREFIX_0F3810) },
85f10a01
MM		 3364 { "(bad)", { XX } },
3365 { "(bad)", { XX } },
3366 { "(bad)", { XX } },
1ceb70f8
L		 3367 { PREFIX_TABLE (PREFIX_0F3814) },
3368 { PREFIX_TABLE (PREFIX_0F3815) },
85f10a01 3369 { "(bad)", { XX } },
1ceb70f8 3370 { PREFIX_TABLE (PREFIX_0F3817) },
4e7d34a6 3371 /* 18 */
85f10a01
MM		 3372 { "(bad)", { XX } },
3373 { "(bad)", { XX } },
3374 { "(bad)", { XX } },
3375 { "(bad)", { XX } },
4e7d34a6
L		 3376 { "pabsb", { MX, EM } },
3377 { "pabsw", { MX, EM } },
3378 { "pabsd", { MX, EM } },
85f10a01 3379 { "(bad)", { XX } },
4e7d34a6 3380 /* 20 */
1ceb70f8
L		 3381 { PREFIX_TABLE (PREFIX_0F3820) },
3382 { PREFIX_TABLE (PREFIX_0F3821) },
3383 { PREFIX_TABLE (PREFIX_0F3822) },
3384 { PREFIX_TABLE (PREFIX_0F3823) },
3385 { PREFIX_TABLE (PREFIX_0F3824) },
3386 { PREFIX_TABLE (PREFIX_0F3825) },
85f10a01
MM		 3387 { "(bad)", { XX } },
3388 { "(bad)", { XX } },
4e7d34a6 3389 /* 28 */
1ceb70f8
L		 3390 { PREFIX_TABLE (PREFIX_0F3828) },
3391 { PREFIX_TABLE (PREFIX_0F3829) },
3392 { PREFIX_TABLE (PREFIX_0F382A) },
3393 { PREFIX_TABLE (PREFIX_0F382B) },
85f10a01
MM		 3394 { "(bad)", { XX } },
3395 { "(bad)", { XX } },
3396 { "(bad)", { XX } },
3397 { "(bad)", { XX } },
4e7d34a6 3398 /* 30 */
1ceb70f8
L		 3399 { PREFIX_TABLE (PREFIX_0F3830) },
3400 { PREFIX_TABLE (PREFIX_0F3831) },
3401 { PREFIX_TABLE (PREFIX_0F3832) },
3402 { PREFIX_TABLE (PREFIX_0F3833) },
3403 { PREFIX_TABLE (PREFIX_0F3834) },
3404 { PREFIX_TABLE (PREFIX_0F3835) },
3405 { "(bad)", { XX } },
3406 { PREFIX_TABLE (PREFIX_0F3837) },
4e7d34a6 3407 /* 38 */
1ceb70f8
L		 3408 { PREFIX_TABLE (PREFIX_0F3838) },
3409 { PREFIX_TABLE (PREFIX_0F3839) },
3410 { PREFIX_TABLE (PREFIX_0F383A) },
3411 { PREFIX_TABLE (PREFIX_0F383B) },
3412 { PREFIX_TABLE (PREFIX_0F383C) },
3413 { PREFIX_TABLE (PREFIX_0F383D) },
3414 { PREFIX_TABLE (PREFIX_0F383E) },
3415 { PREFIX_TABLE (PREFIX_0F383F) },
4e7d34a6 3416 /* 40 */
1ceb70f8
L		 3417 { PREFIX_TABLE (PREFIX_0F3840) },
3418 { PREFIX_TABLE (PREFIX_0F3841) },
85f10a01
MM		 3419 { "(bad)", { XX } },
3420 { "(bad)", { XX } },
85f10a01
MM		 3421 { "(bad)", { XX } },
3422 { "(bad)", { XX } },
3423 { "(bad)", { XX } },
3424 { "(bad)", { XX } },
4e7d34a6 3425 /* 48 */
85f10a01
MM		 3426 { "(bad)", { XX } },
3427 { "(bad)", { XX } },
3428 { "(bad)", { XX } },
3429 { "(bad)", { XX } },
85f10a01
MM		 3430 { "(bad)", { XX } },
3431 { "(bad)", { XX } },
3432 { "(bad)", { XX } },
3433 { "(bad)", { XX } },
4e7d34a6 3434 /* 50 */
85f10a01
MM		 3435 { "(bad)", { XX } },
3436 { "(bad)", { XX } },
3437 { "(bad)", { XX } },
3438 { "(bad)", { XX } },
85f10a01
MM		 3439 { "(bad)", { XX } },
3440 { "(bad)", { XX } },
3441 { "(bad)", { XX } },
3442 { "(bad)", { XX } },
4e7d34a6 3443 /* 58 */
85f10a01
MM		 3444 { "(bad)", { XX } },
3445 { "(bad)", { XX } },
3446 { "(bad)", { XX } },
3447 { "(bad)", { XX } },
85f10a01
MM		 3448 { "(bad)", { XX } },
3449 { "(bad)", { XX } },
3450 { "(bad)", { XX } },
3451 { "(bad)", { XX } },
4e7d34a6 3452 /* 60 */
85f10a01
MM		 3453 { "(bad)", { XX } },
3454 { "(bad)", { XX } },
3455 { "(bad)", { XX } },
3456 { "(bad)", { XX } },
85f10a01
MM		 3457 { "(bad)", { XX } },
3458 { "(bad)", { XX } },
3459 { "(bad)", { XX } },
3460 { "(bad)", { XX } },
4e7d34a6 3461 /* 68 */
85f10a01
MM		 3462 { "(bad)", { XX } },
3463 { "(bad)", { XX } },
3464 { "(bad)", { XX } },
3465 { "(bad)", { XX } },
85f10a01
MM		 3466 { "(bad)", { XX } },
3467 { "(bad)", { XX } },
3468 { "(bad)", { XX } },
3469 { "(bad)", { XX } },
4e7d34a6 3470 /* 70 */
85f10a01
MM		 3471 { "(bad)", { XX } },
3472 { "(bad)", { XX } },
3473 { "(bad)", { XX } },
3474 { "(bad)", { XX } },
85f10a01
MM		 3475 { "(bad)", { XX } },
3476 { "(bad)", { XX } },
3477 { "(bad)", { XX } },
3478 { "(bad)", { XX } },
4e7d34a6 3479 /* 78 */
85f10a01
MM		 3480 { "(bad)", { XX } },
3481 { "(bad)", { XX } },
3482 { "(bad)", { XX } },
3483 { "(bad)", { XX } },
85f10a01
MM		 3484 { "(bad)", { XX } },
3485 { "(bad)", { XX } },
3486 { "(bad)", { XX } },
3487 { "(bad)", { XX } },
4e7d34a6 3488 /* 80 */
85f10a01
MM		 3489 { "(bad)", { XX } },
3490 { "(bad)", { XX } },
3491 { "(bad)", { XX } },
3492 { "(bad)", { XX } },
85f10a01
MM		 3493 { "(bad)", { XX } },
3494 { "(bad)", { XX } },
3495 { "(bad)", { XX } },
3496 { "(bad)", { XX } },
4e7d34a6 3497 /* 88 */
85f10a01
MM		 3498 { "(bad)", { XX } },
3499 { "(bad)", { XX } },
3500 { "(bad)", { XX } },
3501 { "(bad)", { XX } },
85f10a01
MM		 3502 { "(bad)", { XX } },
3503 { "(bad)", { XX } },
3504 { "(bad)", { XX } },
3505 { "(bad)", { XX } },
4e7d34a6 3506 /* 90 */
85f10a01
MM		 3507 { "(bad)", { XX } },
3508 { "(bad)", { XX } },
3509 { "(bad)", { XX } },
3510 { "(bad)", { XX } },
85f10a01
MM		 3511 { "(bad)", { XX } },
3512 { "(bad)", { XX } },
3513 { "(bad)", { XX } },
3514 { "(bad)", { XX } },
4e7d34a6 3515 /* 98 */
85f10a01
MM		 3516 { "(bad)", { XX } },
3517 { "(bad)", { XX } },
3518 { "(bad)", { XX } },
3519 { "(bad)", { XX } },
85f10a01
MM		 3520 { "(bad)", { XX } },
3521 { "(bad)", { XX } },
3522 { "(bad)", { XX } },
3523 { "(bad)", { XX } },
4e7d34a6 3524 /* a0 */
85f10a01
MM		 3525 { "(bad)", { XX } },
3526 { "(bad)", { XX } },
3527 { "(bad)", { XX } },
3528 { "(bad)", { XX } },
4e7d34a6
L		 3529 { "(bad)", { XX } },
3530 { "(bad)", { XX } },
3531 { "(bad)", { XX } },
3532 { "(bad)", { XX } },
3533 /* a8 */
3534 { "(bad)", { XX } },
3535 { "(bad)", { XX } },
3536 { "(bad)", { XX } },
3537 { "(bad)", { XX } },
3538 { "(bad)", { XX } },
3539 { "(bad)", { XX } },
3540 { "(bad)", { XX } },
3541 { "(bad)", { XX } },
3542 /* b0 */
85f10a01
MM		 3543 { "(bad)", { XX } },
3544 { "(bad)", { XX } },
3545 { "(bad)", { XX } },
3546 { "(bad)", { XX } },
3547 { "(bad)", { XX } },
3548 { "(bad)", { XX } },
3549 { "(bad)", { XX } },
3550 { "(bad)", { XX } },
85f10a01 3551 /* b8 */
4e7d34a6
L		 3552 { "(bad)", { XX } },
3553 { "(bad)", { XX } },
3554 { "(bad)", { XX } },
3555 { "(bad)", { XX } },
3556 { "(bad)", { XX } },
3557 { "(bad)", { XX } },
3558 { "(bad)", { XX } },
3559 { "(bad)", { XX } },
85f10a01 3560 /* c0 */
4e7d34a6
L		 3561 { "(bad)", { XX } },
3562 { "(bad)", { XX } },
3563 { "(bad)", { XX } },
3564 { "(bad)", { XX } },
3565 { "(bad)", { XX } },
3566 { "(bad)", { XX } },
3567 { "(bad)", { XX } },
3568 { "(bad)", { XX } },
85f10a01 3569 /* c8 */
4e7d34a6
L		 3570 { "(bad)", { XX } },
3571 { "(bad)", { XX } },
3572 { "(bad)", { XX } },
3573 { "(bad)", { XX } },
3574 { "(bad)", { XX } },
3575 { "(bad)", { XX } },
3576 { "(bad)", { XX } },
3577 { "(bad)", { XX } },
85f10a01 3578 /* d0 */
4e7d34a6
L		 3579 { "(bad)", { XX } },
3580 { "(bad)", { XX } },
3581 { "(bad)", { XX } },
3582 { "(bad)", { XX } },
3583 { "(bad)", { XX } },
3584 { "(bad)", { XX } },
3585 { "(bad)", { XX } },
3586 { "(bad)", { XX } },
85f10a01 3587 /* d8 */
4e7d34a6
L		 3588 { "(bad)", { XX } },
3589 { "(bad)", { XX } },
3590 { "(bad)", { XX } },
3591 { "(bad)", { XX } },
3592 { "(bad)", { XX } },
3593 { "(bad)", { XX } },
3594 { "(bad)", { XX } },
3595 { "(bad)", { XX } },
85f10a01 3596 /* e0 */
4e7d34a6
L		 3597 { "(bad)", { XX } },
3598 { "(bad)", { XX } },
3599 { "(bad)", { XX } },
3600 { "(bad)", { XX } },
3601 { "(bad)", { XX } },
3602 { "(bad)", { XX } },
3603 { "(bad)", { XX } },
3604 { "(bad)", { XX } },
85f10a01 3605 /* e8 */
4e7d34a6
L		 3606 { "(bad)", { XX } },
3607 { "(bad)", { XX } },
3608 { "(bad)", { XX } },
3609 { "(bad)", { XX } },
3610 { "(bad)", { XX } },
3611 { "(bad)", { XX } },
3612 { "(bad)", { XX } },
3613 { "(bad)", { XX } },
85f10a01 3614 /* f0 */
1ceb70f8
L		 3615 { PREFIX_TABLE (PREFIX_0F38F0) },
3616 { PREFIX_TABLE (PREFIX_0F38F1) },
4e7d34a6
L		 3617 { "(bad)", { XX } },
3618 { "(bad)", { XX } },
3619 { "(bad)", { XX } },
3620 { "(bad)", { XX } },
3621 { "(bad)", { XX } },
3622 { "(bad)", { XX } },
85f10a01 3623 /* f8 */
4e7d34a6
L		 3624 { "(bad)", { XX } },
3625 { "(bad)", { XX } },
3626 { "(bad)", { XX } },
3627 { "(bad)", { XX } },
3628 { "(bad)", { XX } },
3629 { "(bad)", { XX } },
3630 { "(bad)", { XX } },
3631 { "(bad)", { XX } },
85f10a01 3632 },
4e7d34a6 3633 /* THREE_BYTE_0F3A */
85f10a01
MM		 3634 {
3635 /* 00 */
4e7d34a6
L		 3636 { "(bad)", { XX } },
3637 { "(bad)", { XX } },
3638 { "(bad)", { XX } },
3639 { "(bad)", { XX } },
3640 { "(bad)", { XX } },
3641 { "(bad)", { XX } },
3642 { "(bad)", { XX } },
3643 { "(bad)", { XX } },
85f10a01 3644 /* 08 */
1ceb70f8
L		 3645 { PREFIX_TABLE (PREFIX_0F3A08) },
3646 { PREFIX_TABLE (PREFIX_0F3A09) },
3647 { PREFIX_TABLE (PREFIX_0F3A0A) },
3648 { PREFIX_TABLE (PREFIX_0F3A0B) },
3649 { PREFIX_TABLE (PREFIX_0F3A0C) },
3650 { PREFIX_TABLE (PREFIX_0F3A0D) },
3651 { PREFIX_TABLE (PREFIX_0F3A0E) },
4e7d34a6 3652 { "palignr", { MX, EM, Ib } },
85f10a01 3653 /* 10 */
4e7d34a6
L		 3654 { "(bad)", { XX } },
3655 { "(bad)", { XX } },
3656 { "(bad)", { XX } },
3657 { "(bad)", { XX } },
1ceb70f8
L		 3658 { PREFIX_TABLE (PREFIX_0F3A14) },
3659 { PREFIX_TABLE (PREFIX_0F3A15) },
3660 { PREFIX_TABLE (PREFIX_0F3A16) },
3661 { PREFIX_TABLE (PREFIX_0F3A17) },
85f10a01 3662 /* 18 */
4e7d34a6
L		 3663 { "(bad)", { XX } },
3664 { "(bad)", { XX } },
3665 { "(bad)", { XX } },
3666 { "(bad)", { XX } },
3667 { "(bad)", { XX } },
3668 { "(bad)", { XX } },
3669 { "(bad)", { XX } },
3670 { "(bad)", { XX } },
85f10a01 3671 /* 20 */
1ceb70f8
L		 3672 { PREFIX_TABLE (PREFIX_0F3A20) },
3673 { PREFIX_TABLE (PREFIX_0F3A21) },
3674 { PREFIX_TABLE (PREFIX_0F3A22) },
4e7d34a6
L		 3675 { "(bad)", { XX } },
3676 { "(bad)", { XX } },
3677 { "(bad)", { XX } },
3678 { "(bad)", { XX } },
3679 { "(bad)", { XX } },
85f10a01 3680 /* 28 */
4e7d34a6
L		 3681 { "(bad)", { XX } },
3682 { "(bad)", { XX } },
3683 { "(bad)", { XX } },
3684 { "(bad)", { XX } },
3685 { "(bad)", { XX } },
3686 { "(bad)", { XX } },
3687 { "(bad)", { XX } },
3688 { "(bad)", { XX } },
85f10a01 3689 /* 30 */
4e7d34a6
L		 3690 { "(bad)", { XX } },
3691 { "(bad)", { XX } },
3692 { "(bad)", { XX } },
3693 { "(bad)", { XX } },
3694 { "(bad)", { XX } },
3695 { "(bad)", { XX } },
3696 { "(bad)", { XX } },
3697 { "(bad)", { XX } },
3698 /* 38 */
3699 { "(bad)", { XX } },
3700 { "(bad)", { XX } },
3701 { "(bad)", { XX } },
3702 { "(bad)", { XX } },
3703 { "(bad)", { XX } },
3704 { "(bad)", { XX } },
3705 { "(bad)", { XX } },
3706 { "(bad)", { XX } },
85f10a01 3707 /* 40 */
1ceb70f8
L		 3708 { PREFIX_TABLE (PREFIX_0F3A40) },
3709 { PREFIX_TABLE (PREFIX_0F3A41) },
3710 { PREFIX_TABLE (PREFIX_0F3A42) },
4e7d34a6
L		 3711 { "(bad)", { XX } },
3712 { "(bad)", { XX } },
3713 { "(bad)", { XX } },
3714 { "(bad)", { XX } },
3715 { "(bad)", { XX } },
85f10a01 3716 /* 48 */
4e7d34a6
L		 3717 { "(bad)", { XX } },
3718 { "(bad)", { XX } },
3719 { "(bad)", { XX } },
3720 { "(bad)", { XX } },
3721 { "(bad)", { XX } },
3722 { "(bad)", { XX } },
3723 { "(bad)", { XX } },
3724 { "(bad)", { XX } },
85f10a01 3725 /* 50 */
4e7d34a6
L		 3726 { "(bad)", { XX } },
3727 { "(bad)", { XX } },
3728 { "(bad)", { XX } },
3729 { "(bad)", { XX } },
3730 { "(bad)", { XX } },
3731 { "(bad)", { XX } },
3732 { "(bad)", { XX } },
3733 { "(bad)", { XX } },
85f10a01 3734 /* 58 */
4e7d34a6
L		 3735 { "(bad)", { XX } },
3736 { "(bad)", { XX } },
3737 { "(bad)", { XX } },
3738 { "(bad)", { XX } },
3739 { "(bad)", { XX } },
3740 { "(bad)", { XX } },
3741 { "(bad)", { XX } },
3742 { "(bad)", { XX } },
85f10a01 3743 /* 60 */
1ceb70f8
L		 3744 { PREFIX_TABLE (PREFIX_0F3A60) },
3745 { PREFIX_TABLE (PREFIX_0F3A61) },
3746 { PREFIX_TABLE (PREFIX_0F3A62) },
3747 { PREFIX_TABLE (PREFIX_0F3A63) },
4e7d34a6
L		 3748 { "(bad)", { XX } },
3749 { "(bad)", { XX } },
3750 { "(bad)", { XX } },
3751 { "(bad)", { XX } },
85f10a01 3752 /* 68 */
4e7d34a6
L		 3753 { "(bad)", { XX } },
3754 { "(bad)", { XX } },
3755 { "(bad)", { XX } },
3756 { "(bad)", { XX } },
3757 { "(bad)", { XX } },
3758 { "(bad)", { XX } },
3759 { "(bad)", { XX } },
3760 { "(bad)", { XX } },
85f10a01 3761 /* 70 */
4e7d34a6
L		 3762 { "(bad)", { XX } },
3763 { "(bad)", { XX } },
3764 { "(bad)", { XX } },
3765 { "(bad)", { XX } },
3766 { "(bad)", { XX } },
3767 { "(bad)", { XX } },
3768 { "(bad)", { XX } },
3769 { "(bad)", { XX } },
85f10a01 3770 /* 78 */
4e7d34a6
L		 3771 { "(bad)", { XX } },
3772 { "(bad)", { XX } },
3773 { "(bad)", { XX } },
3774 { "(bad)", { XX } },
3775 { "(bad)", { XX } },
3776 { "(bad)", { XX } },
3777 { "(bad)", { XX } },
3778 { "(bad)", { XX } },
85f10a01 3779 /* 80 */
4e7d34a6
L		 3780 { "(bad)", { XX } },
3781 { "(bad)", { XX } },
3782 { "(bad)", { XX } },
3783 { "(bad)", { XX } },
3784 { "(bad)", { XX } },
3785 { "(bad)", { XX } },
3786 { "(bad)", { XX } },
3787 { "(bad)", { XX } },
85f10a01 3788 /* 88 */
4e7d34a6
L		 3789 { "(bad)", { XX } },
3790 { "(bad)", { XX } },
3791 { "(bad)", { XX } },
3792 { "(bad)", { XX } },
3793 { "(bad)", { XX } },
3794 { "(bad)", { XX } },
3795 { "(bad)", { XX } },
3796 { "(bad)", { XX } },
85f10a01 3797 /* 90 */
4e7d34a6
L		 3798 { "(bad)", { XX } },
3799 { "(bad)", { XX } },
3800 { "(bad)", { XX } },
3801 { "(bad)", { XX } },
3802 { "(bad)", { XX } },
3803 { "(bad)", { XX } },
3804 { "(bad)", { XX } },
3805 { "(bad)", { XX } },
85f10a01 3806 /* 98 */
4e7d34a6
L		 3807 { "(bad)", { XX } },
3808 { "(bad)", { XX } },
3809 { "(bad)", { XX } },
3810 { "(bad)", { XX } },
3811 { "(bad)", { XX } },
3812 { "(bad)", { XX } },
3813 { "(bad)", { XX } },
3814 { "(bad)", { XX } },
85f10a01 3815 /* a0 */
4e7d34a6
L		 3816 { "(bad)", { XX } },
3817 { "(bad)", { XX } },
3818 { "(bad)", { XX } },
3819 { "(bad)", { XX } },
3820 { "(bad)", { XX } },
3821 { "(bad)", { XX } },
3822 { "(bad)", { XX } },
3823 { "(bad)", { XX } },
85f10a01 3824 /* a8 */
4e7d34a6
L		 3825 { "(bad)", { XX } },
3826 { "(bad)", { XX } },
3827 { "(bad)", { XX } },
3828 { "(bad)", { XX } },
3829 { "(bad)", { XX } },
3830 { "(bad)", { XX } },
3831 { "(bad)", { XX } },
3832 { "(bad)", { XX } },
85f10a01 3833 /* b0 */
4e7d34a6
L		 3834 { "(bad)", { XX } },
3835 { "(bad)", { XX } },
3836 { "(bad)", { XX } },
3837 { "(bad)", { XX } },
3838 { "(bad)", { XX } },
3839 { "(bad)", { XX } },
3840 { "(bad)", { XX } },
3841 { "(bad)", { XX } },
3842 /* b8 */
3843 { "(bad)", { XX } },
3844 { "(bad)", { XX } },
3845 { "(bad)", { XX } },
3846 { "(bad)", { XX } },
3847 { "(bad)", { XX } },
3848 { "(bad)", { XX } },
3849 { "(bad)", { XX } },
3850 { "(bad)", { XX } },
85f10a01 3851 /* c0 */
4e7d34a6
L		 3852 { "(bad)", { XX } },
3853 { "(bad)", { XX } },
3854 { "(bad)", { XX } },
3855 { "(bad)", { XX } },
3856 { "(bad)", { XX } },
3857 { "(bad)", { XX } },
3858 { "(bad)", { XX } },
3859 { "(bad)", { XX } },
85f10a01 3860 /* c8 */
4e7d34a6
L		 3861 { "(bad)", { XX } },
3862 { "(bad)", { XX } },
3863 { "(bad)", { XX } },
3864 { "(bad)", { XX } },
3865 { "(bad)", { XX } },
3866 { "(bad)", { XX } },
3867 { "(bad)", { XX } },
3868 { "(bad)", { XX } },
85f10a01 3869 /* d0 */
4e7d34a6
L		 3870 { "(bad)", { XX } },
3871 { "(bad)", { XX } },
3872 { "(bad)", { XX } },
3873 { "(bad)", { XX } },
3874 { "(bad)", { XX } },
3875 { "(bad)", { XX } },
3876 { "(bad)", { XX } },
3877 { "(bad)", { XX } },
85f10a01 3878 /* d8 */
4e7d34a6
L		 3879 { "(bad)", { XX } },
3880 { "(bad)", { XX } },
3881 { "(bad)", { XX } },
3882 { "(bad)", { XX } },
3883 { "(bad)", { XX } },
3884 { "(bad)", { XX } },
3885 { "(bad)", { XX } },
3886 { "(bad)", { XX } },
85f10a01 3887 /* e0 */
4e7d34a6
L		 3888 { "(bad)", { XX } },
3889 { "(bad)", { XX } },
3890 { "(bad)", { XX } },
3891 { "(bad)", { XX } },
3892 { "(bad)", { XX } },
3893 { "(bad)", { XX } },
3894 { "(bad)", { XX } },
3895 { "(bad)", { XX } },
85f10a01 3896 /* e8 */
4e7d34a6
L		 3897 { "(bad)", { XX } },
3898 { "(bad)", { XX } },
3899 { "(bad)", { XX } },
3900 { "(bad)", { XX } },
3901 { "(bad)", { XX } },
3902 { "(bad)", { XX } },
3903 { "(bad)", { XX } },
3904 { "(bad)", { XX } },
85f10a01 3905 /* f0 */
4e7d34a6
L		 3906 { "(bad)", { XX } },
3907 { "(bad)", { XX } },
3908 { "(bad)", { XX } },
3909 { "(bad)", { XX } },
3910 { "(bad)", { XX } },
3911 { "(bad)", { XX } },
3912 { "(bad)", { XX } },
3913 { "(bad)", { XX } },
85f10a01 3914 /* f8 */
4e7d34a6
L		 3915 { "(bad)", { XX } },
3916 { "(bad)", { XX } },
3917 { "(bad)", { XX } },
3918 { "(bad)", { XX } },
3919 { "(bad)", { XX } },
3920 { "(bad)", { XX } },
3921 { "(bad)", { XX } },
3922 { "(bad)", { XX } },
85f10a01 3923 },
89b66d55 3924 /* THREE_BYTE_0F7A */
85f10a01
MM		 3925 {
3926 /* 00 */
3927 { "(bad)", { XX } },
3928 { "(bad)", { XX } },
3929 { "(bad)", { XX } },
3930 { "(bad)", { XX } },
3931 { "(bad)", { XX } },
3932 { "(bad)", { XX } },
3933 { "(bad)", { XX } },
3934 { "(bad)", { XX } },
3935 /* 08 */
3936 { "(bad)", { XX } },
3937 { "(bad)", { XX } },
3938 { "(bad)", { XX } },
3939 { "(bad)", { XX } },
3940 { "(bad)", { XX } },
3941 { "(bad)", { XX } },
3942 { "(bad)", { XX } },
3943 { "(bad)", { XX } },
3944 /* 10 */
3945 { "frczps", { XM, EXq } },
3946 { "frczpd", { XM, EXq } },
3947 { "frczss", { XM, EXq } },
3948 { "frczsd", { XM, EXq } },
3949 { "(bad)", { XX } },
3950 { "(bad)", { XX } },
3951 { "(bad)", { XX } },
3952 { "(bad)", { XX } },
3953 /* 18 */
3954 { "(bad)", { XX } },
3955 { "(bad)", { XX } },
3956 { "(bad)", { XX } },
3957 { "(bad)", { XX } },
3958 { "(bad)", { XX } },
3959 { "(bad)", { XX } },
3960 { "(bad)", { XX } },
3961 { "(bad)", { XX } },
3962 /* 20 */
3963 { "ptest", { XX } },
3964 { "(bad)", { XX } },
3965 { "(bad)", { XX } },
3966 { "(bad)", { XX } },
3967 { "(bad)", { XX } },
3968 { "(bad)", { XX } },
3969 { "(bad)", { XX } },
3970 { "(bad)", { XX } },
3971 /* 28 */
3972 { "(bad)", { XX } },
3973 { "(bad)", { XX } },
3974 { "(bad)", { XX } },
3975 { "(bad)", { XX } },
3976 { "(bad)", { XX } },
3977 { "(bad)", { XX } },
ce518a5f
L		 3978 { "(bad)", { XX } },
3979 { "(bad)", { XX } },
85f10a01
MM		 3980 /* 30 */
3981 { "cvtph2ps", { XM, EXd } },
3982 { "cvtps2ph", { EXd, XM } },
ce518a5f
L		 3983 { "(bad)", { XX } },
3984 { "(bad)", { XX } },
ce518a5f
L		 3985 { "(bad)", { XX } },
3986 { "(bad)", { XX } },
3987 { "(bad)", { XX } },
3988 { "(bad)", { XX } },
85f10a01 3989 /* 38 */
ce518a5f 3990 { "(bad)", { XX } },
ce518a5f
L		 3991 { "(bad)", { XX } },
3992 { "(bad)", { XX } },
ce518a5f
L		 3993 { "(bad)", { XX } },
3994 { "(bad)", { XX } },
3995 { "(bad)", { XX } },
3996 { "(bad)", { XX } },
ce518a5f 3997 { "(bad)", { XX } },
96fbad73 3998 /* 40 */
ce518a5f 3999 { "(bad)", { XX } },
85f10a01
MM		 4000 { "phaddbw", { XM, EXq } },
4001 { "phaddbd", { XM, EXq } },
4002 { "phaddbq", { XM, EXq } },
ce518a5f
L		 4003 { "(bad)", { XX } },
4004 { "(bad)", { XX } },
85f10a01
MM		 4005 { "phaddwd", { XM, EXq } },
4006 { "phaddwq", { XM, EXq } },
96fbad73 4007 /* 48 */
ce518a5f
L		 4008 { "(bad)", { XX } },
4009 { "(bad)", { XX } },
4010 { "(bad)", { XX } },
85f10a01 4011 { "phadddq", { XM, EXq } },
ce518a5f
L		 4012 { "(bad)", { XX } },
4013 { "(bad)", { XX } },
4014 { "(bad)", { XX } },
4015 { "(bad)", { XX } },
96fbad73 4016 /* 50 */
ce518a5f 4017 { "(bad)", { XX } },
85f10a01
MM		 4018 { "phaddubw", { XM, EXq } },
4019 { "phaddubd", { XM, EXq } },
4020 { "phaddubq", { XM, EXq } },
ce518a5f
L		 4021 { "(bad)", { XX } },
4022 { "(bad)", { XX } },
85f10a01
MM		 4023 { "phadduwd", { XM, EXq } },
4024 { "phadduwq", { XM, EXq } },
96fbad73 4025 /* 58 */
ce518a5f
L		 4026 { "(bad)", { XX } },
4027 { "(bad)", { XX } },
4028 { "(bad)", { XX } },
85f10a01 4029 { "phaddudq", { XM, EXq } },
ce518a5f
L		 4030 { "(bad)", { XX } },
4031 { "(bad)", { XX } },
4032 { "(bad)", { XX } },
4033 { "(bad)", { XX } },
96fbad73 4034 /* 60 */
ce518a5f 4035 { "(bad)", { XX } },
85f10a01
MM		 4036 { "phsubbw", { XM, EXq } },
4037 { "phsubbd", { XM, EXq } },
4038 { "phsubbq", { XM, EXq } },
ce518a5f
L		 4039 { "(bad)", { XX } },
4040 { "(bad)", { XX } },
4041 { "(bad)", { XX } },
4042 { "(bad)", { XX } },
96fbad73 4043 /* 68 */
ce518a5f
L		 4044 { "(bad)", { XX } },
4045 { "(bad)", { XX } },
4046 { "(bad)", { XX } },
4047 { "(bad)", { XX } },
4048 { "(bad)", { XX } },
4049 { "(bad)", { XX } },
4050 { "(bad)", { XX } },
4051 { "(bad)", { XX } },
96fbad73 4052 /* 70 */
ce518a5f
L		 4053 { "(bad)", { XX } },
4054 { "(bad)", { XX } },
4055 { "(bad)", { XX } },
4056 { "(bad)", { XX } },
4057 { "(bad)", { XX } },
4058 { "(bad)", { XX } },
4059 { "(bad)", { XX } },
4060 { "(bad)", { XX } },
96fbad73 4061 /* 78 */
ce518a5f
L		 4062 { "(bad)", { XX } },
4063 { "(bad)", { XX } },
4064 { "(bad)", { XX } },
4065 { "(bad)", { XX } },
4066 { "(bad)", { XX } },
4067 { "(bad)", { XX } },
4068 { "(bad)", { XX } },
4069 { "(bad)", { XX } },
96fbad73 4070 /* 80 */
ce518a5f
L		 4071 { "(bad)", { XX } },
4072 { "(bad)", { XX } },
4073 { "(bad)", { XX } },
4074 { "(bad)", { XX } },
4075 { "(bad)", { XX } },
4076 { "(bad)", { XX } },
4077 { "(bad)", { XX } },
4078 { "(bad)", { XX } },
96fbad73 4079 /* 88 */
ce518a5f
L		 4080 { "(bad)", { XX } },
4081 { "(bad)", { XX } },
4082 { "(bad)", { XX } },
4083 { "(bad)", { XX } },
4084 { "(bad)", { XX } },
4085 { "(bad)", { XX } },
4086 { "(bad)", { XX } },
4087 { "(bad)", { XX } },
96fbad73 4088 /* 90 */
ce518a5f
L		 4089 { "(bad)", { XX } },
4090 { "(bad)", { XX } },
4091 { "(bad)", { XX } },
4092 { "(bad)", { XX } },
4093 { "(bad)", { XX } },
4094 { "(bad)", { XX } },
4095 { "(bad)", { XX } },
4096 { "(bad)", { XX } },
96fbad73 4097 /* 98 */
ce518a5f
L		 4098 { "(bad)", { XX } },
4099 { "(bad)", { XX } },
4100 { "(bad)", { XX } },
4101 { "(bad)", { XX } },
4102 { "(bad)", { XX } },
4103 { "(bad)", { XX } },
4104 { "(bad)", { XX } },
4105 { "(bad)", { XX } },
96fbad73 4106 /* a0 */
ce518a5f
L		 4107 { "(bad)", { XX } },
4108 { "(bad)", { XX } },
4109 { "(bad)", { XX } },
4110 { "(bad)", { XX } },
4111 { "(bad)", { XX } },
4112 { "(bad)", { XX } },
4113 { "(bad)", { XX } },
4114 { "(bad)", { XX } },
96fbad73 4115 /* a8 */
ce518a5f
L		 4116 { "(bad)", { XX } },
4117 { "(bad)", { XX } },
4118 { "(bad)", { XX } },
4119 { "(bad)", { XX } },
4120 { "(bad)", { XX } },
4121 { "(bad)", { XX } },
4122 { "(bad)", { XX } },
4123 { "(bad)", { XX } },
96fbad73 4124 /* b0 */
ce518a5f
L		 4125 { "(bad)", { XX } },
4126 { "(bad)", { XX } },
4127 { "(bad)", { XX } },
4128 { "(bad)", { XX } },
4129 { "(bad)", { XX } },
4130 { "(bad)", { XX } },
4131 { "(bad)", { XX } },
4132 { "(bad)", { XX } },
96fbad73 4133 /* b8 */
ce518a5f
L		 4134 { "(bad)", { XX } },
4135 { "(bad)", { XX } },
4136 { "(bad)", { XX } },
4137 { "(bad)", { XX } },
4138 { "(bad)", { XX } },
4139 { "(bad)", { XX } },
4140 { "(bad)", { XX } },
4141 { "(bad)", { XX } },
96fbad73 4142 /* c0 */
ce518a5f
L		 4143 { "(bad)", { XX } },
4144 { "(bad)", { XX } },
4145 { "(bad)", { XX } },
4146 { "(bad)", { XX } },
4147 { "(bad)", { XX } },
4148 { "(bad)", { XX } },
4149 { "(bad)", { XX } },
4150 { "(bad)", { XX } },
96fbad73 4151 /* c8 */
ce518a5f
L		 4152 { "(bad)", { XX } },
4153 { "(bad)", { XX } },
4154 { "(bad)", { XX } },
4155 { "(bad)", { XX } },
4156 { "(bad)", { XX } },
4157 { "(bad)", { XX } },
4158 { "(bad)", { XX } },
4159 { "(bad)", { XX } },
96fbad73 4160 /* d0 */
ce518a5f
L		 4161 { "(bad)", { XX } },
4162 { "(bad)", { XX } },
4163 { "(bad)", { XX } },
4164 { "(bad)", { XX } },
4165 { "(bad)", { XX } },
4166 { "(bad)", { XX } },
4167 { "(bad)", { XX } },
4168 { "(bad)", { XX } },
96fbad73 4169 /* d8 */
ce518a5f
L		 4170 { "(bad)", { XX } },
4171 { "(bad)", { XX } },
4172 { "(bad)", { XX } },
4173 { "(bad)", { XX } },
4174 { "(bad)", { XX } },
4175 { "(bad)", { XX } },
4176 { "(bad)", { XX } },
4177 { "(bad)", { XX } },
96fbad73 4178 /* e0 */
ce518a5f
L		 4179 { "(bad)", { XX } },
4180 { "(bad)", { XX } },
4181 { "(bad)", { XX } },
4182 { "(bad)", { XX } },
4183 { "(bad)", { XX } },
4184 { "(bad)", { XX } },
4185 { "(bad)", { XX } },
4186 { "(bad)", { XX } },
96fbad73 4187 /* e8 */
ce518a5f
L		 4188 { "(bad)", { XX } },
4189 { "(bad)", { XX } },
4190 { "(bad)", { XX } },
4191 { "(bad)", { XX } },
4192 { "(bad)", { XX } },
4193 { "(bad)", { XX } },
4194 { "(bad)", { XX } },
4195 { "(bad)", { XX } },
96fbad73 4196 /* f0 */
85f10a01
MM		 4197 { "(bad)", { XX } },
4198 { "(bad)", { XX } },
ce518a5f
L		 4199 { "(bad)", { XX } },
4200 { "(bad)", { XX } },
4201 { "(bad)", { XX } },
4202 { "(bad)", { XX } },
4203 { "(bad)", { XX } },
4204 { "(bad)", { XX } },
96fbad73 4205 /* f8 */
ce518a5f
L		 4206 { "(bad)", { XX } },
4207 { "(bad)", { XX } },
4208 { "(bad)", { XX } },
4209 { "(bad)", { XX } },
4210 { "(bad)", { XX } },
4211 { "(bad)", { XX } },
4212 { "(bad)", { XX } },
4213 { "(bad)", { XX } },
331d2d0d 4214 },
89b66d55 4215 /* THREE_BYTE_0F7B */
331d2d0d 4216 {
96fbad73 4217 /* 00 */
ce518a5f
L		 4218 { "(bad)", { XX } },
4219 { "(bad)", { XX } },
4220 { "(bad)", { XX } },
4221 { "(bad)", { XX } },
4222 { "(bad)", { XX } },
4223 { "(bad)", { XX } },
4224 { "(bad)", { XX } },
4225 { "(bad)", { XX } },
96fbad73 4226 /* 08 */
ce518a5f
L		 4227 { "(bad)", { XX } },
4228 { "(bad)", { XX } },
4229 { "(bad)", { XX } },
4230 { "(bad)", { XX } },
ce518a5f
L		 4231 { "(bad)", { XX } },
4232 { "(bad)", { XX } },
4233 { "(bad)", { XX } },
4234 { "(bad)", { XX } },
85f10a01 4235 /* 10 */
ce518a5f
L		 4236 { "(bad)", { XX } },
4237 { "(bad)", { XX } },
4238 { "(bad)", { XX } },
4239 { "(bad)", { XX } },
ce518a5f
L		 4240 { "(bad)", { XX } },
4241 { "(bad)", { XX } },
4242 { "(bad)", { XX } },
4243 { "(bad)", { XX } },
85f10a01 4244 /* 18 */
ce518a5f 4245 { "(bad)", { XX } },
ce518a5f
L		 4246 { "(bad)", { XX } },
4247 { "(bad)", { XX } },
4248 { "(bad)", { XX } },
4249 { "(bad)", { XX } },
4250 { "(bad)", { XX } },
4251 { "(bad)", { XX } },
4252 { "(bad)", { XX } },
85f10a01 4253 /* 20 */
ce518a5f 4254 { "(bad)", { XX } },
ce518a5f
L		 4255 { "(bad)", { XX } },
4256 { "(bad)", { XX } },
4257 { "(bad)", { XX } },
4258 { "(bad)", { XX } },
4259 { "(bad)", { XX } },
4260 { "(bad)", { XX } },
4261 { "(bad)", { XX } },
85f10a01 4262 /* 28 */
ce518a5f 4263 { "(bad)", { XX } },
ce518a5f
L		 4264 { "(bad)", { XX } },
4265 { "(bad)", { XX } },
4266 { "(bad)", { XX } },
4267 { "(bad)", { XX } },
4268 { "(bad)", { XX } },
4269 { "(bad)", { XX } },
4270 { "(bad)", { XX } },
85f10a01 4271 /* 30 */
ce518a5f 4272 { "(bad)", { XX } },
ce518a5f
L		 4273 { "(bad)", { XX } },
4274 { "(bad)", { XX } },
4275 { "(bad)", { XX } },
4276 { "(bad)", { XX } },
4277 { "(bad)", { XX } },
85f10a01
MM		 4278 { "(bad)", { XX } },
4279 { "(bad)", { XX } },
4280 /* 38 */
4281 { "(bad)", { XX } },
4282 { "(bad)", { XX } },
4283 { "(bad)", { XX } },
ce518a5f
L		 4284 { "(bad)", { XX } },
4285 { "(bad)", { XX } },
4286 { "(bad)", { XX } },
4287 { "(bad)", { XX } },
4288 { "(bad)", { XX } },
85f10a01
MM		 4289 /* 40 */
4290 { "protb", { XM, EXq, Ib } },
4291 { "protw", { XM, EXq, Ib } },
4292 { "protd", { XM, EXq, Ib } },
4293 { "protq", { XM, EXq, Ib } },
4294 { "pshlb", { XM, EXq, Ib } },
4295 { "pshlw", { XM, EXq, Ib } },
4296 { "pshld", { XM, EXq, Ib } },
4297 { "pshlq", { XM, EXq, Ib } },
4298 /* 48 */
4299 { "pshab", { XM, EXq, Ib } },
4300 { "pshaw", { XM, EXq, Ib } },
4301 { "pshad", { XM, EXq, Ib } },
4302 { "pshaq", { XM, EXq, Ib } },
4303 { "(bad)", { XX } },
ce518a5f
L		 4304 { "(bad)", { XX } },
4305 { "(bad)", { XX } },
4306 { "(bad)", { XX } },
96fbad73 4307 /* 50 */
ce518a5f
L		 4308 { "(bad)", { XX } },
4309 { "(bad)", { XX } },
4310 { "(bad)", { XX } },
4311 { "(bad)", { XX } },
4312 { "(bad)", { XX } },
4313 { "(bad)", { XX } },
4314 { "(bad)", { XX } },
4315 { "(bad)", { XX } },
96fbad73 4316 /* 58 */
ce518a5f
L		 4317 { "(bad)", { XX } },
4318 { "(bad)", { XX } },
4319 { "(bad)", { XX } },
4320 { "(bad)", { XX } },
4321 { "(bad)", { XX } },
4322 { "(bad)", { XX } },
4323 { "(bad)", { XX } },
4324 { "(bad)", { XX } },
96fbad73 4325 /* 60 */
85f10a01
MM		 4326 { "(bad)", { XX } },
4327 { "(bad)", { XX } },
4328 { "(bad)", { XX } },
4329 { "(bad)", { XX } },
ce518a5f
L		 4330 { "(bad)", { XX } },
4331 { "(bad)", { XX } },
4332 { "(bad)", { XX } },
4333 { "(bad)", { XX } },
96fbad73 4334 /* 68 */
ce518a5f
L		 4335 { "(bad)", { XX } },
4336 { "(bad)", { XX } },
4337 { "(bad)", { XX } },
4338 { "(bad)", { XX } },
4339 { "(bad)", { XX } },
4340 { "(bad)", { XX } },
4341 { "(bad)", { XX } },
4342 { "(bad)", { XX } },
96fbad73 4343 /* 70 */
ce518a5f
L		 4344 { "(bad)", { XX } },
4345 { "(bad)", { XX } },
4346 { "(bad)", { XX } },
4347 { "(bad)", { XX } },
4348 { "(bad)", { XX } },
4349 { "(bad)", { XX } },
4350 { "(bad)", { XX } },
4351 { "(bad)", { XX } },
96fbad73 4352 /* 78 */
ce518a5f
L		 4353 { "(bad)", { XX } },
4354 { "(bad)", { XX } },
4355 { "(bad)", { XX } },
4356 { "(bad)", { XX } },
4357 { "(bad)", { XX } },
4358 { "(bad)", { XX } },
4359 { "(bad)", { XX } },
4360 { "(bad)", { XX } },
96fbad73 4361 /* 80 */
ce518a5f
L		 4362 { "(bad)", { XX } },
4363 { "(bad)", { XX } },
4364 { "(bad)", { XX } },
4365 { "(bad)", { XX } },
4366 { "(bad)", { XX } },
4367 { "(bad)", { XX } },
4368 { "(bad)", { XX } },
4369 { "(bad)", { XX } },
96fbad73 4370 /* 88 */
ce518a5f
L		 4371 { "(bad)", { XX } },
4372 { "(bad)", { XX } },
4373 { "(bad)", { XX } },
4374 { "(bad)", { XX } },
4375 { "(bad)", { XX } },
4376 { "(bad)", { XX } },
4377 { "(bad)", { XX } },
4378 { "(bad)", { XX } },
96fbad73 4379 /* 90 */
ce518a5f
L		 4380 { "(bad)", { XX } },
4381 { "(bad)", { XX } },
4382 { "(bad)", { XX } },
4383 { "(bad)", { XX } },
4384 { "(bad)", { XX } },
4385 { "(bad)", { XX } },
4386 { "(bad)", { XX } },
4387 { "(bad)", { XX } },
96fbad73 4388 /* 98 */
ce518a5f
L		 4389 { "(bad)", { XX } },
4390 { "(bad)", { XX } },
4391 { "(bad)", { XX } },
4392 { "(bad)", { XX } },
4393 { "(bad)", { XX } },
4394 { "(bad)", { XX } },
4395 { "(bad)", { XX } },
4396 { "(bad)", { XX } },
96fbad73 4397 /* a0 */
ce518a5f
L		 4398 { "(bad)", { XX } },
4399 { "(bad)", { XX } },
4400 { "(bad)", { XX } },
4401 { "(bad)", { XX } },
4402 { "(bad)", { XX } },
4403 { "(bad)", { XX } },
4404 { "(bad)", { XX } },
4405 { "(bad)", { XX } },
96fbad73 4406 /* a8 */
ce518a5f
L		 4407 { "(bad)", { XX } },
4408 { "(bad)", { XX } },
4409 { "(bad)", { XX } },
4410 { "(bad)", { XX } },
4411 { "(bad)", { XX } },
4412 { "(bad)", { XX } },
4413 { "(bad)", { XX } },
4414 { "(bad)", { XX } },
96fbad73 4415 /* b0 */
ce518a5f
L		 4416 { "(bad)", { XX } },
4417 { "(bad)", { XX } },
4418 { "(bad)", { XX } },
4419 { "(bad)", { XX } },
4420 { "(bad)", { XX } },
4421 { "(bad)", { XX } },
4422 { "(bad)", { XX } },
4423 { "(bad)", { XX } },
96fbad73 4424 /* b8 */
ce518a5f
L		 4425 { "(bad)", { XX } },
4426 { "(bad)", { XX } },
4427 { "(bad)", { XX } },
4428 { "(bad)", { XX } },
4429 { "(bad)", { XX } },
4430 { "(bad)", { XX } },
4431 { "(bad)", { XX } },
4432 { "(bad)", { XX } },
96fbad73 4433 /* c0 */
ce518a5f
L		 4434 { "(bad)", { XX } },
4435 { "(bad)", { XX } },
4436 { "(bad)", { XX } },
4437 { "(bad)", { XX } },
4438 { "(bad)", { XX } },
4439 { "(bad)", { XX } },
4440 { "(bad)", { XX } },
4441 { "(bad)", { XX } },
96fbad73 4442 /* c8 */
ce518a5f
L		 4443 { "(bad)", { XX } },
4444 { "(bad)", { XX } },
4445 { "(bad)", { XX } },
4446 { "(bad)", { XX } },
4447 { "(bad)", { XX } },
4448 { "(bad)", { XX } },
4449 { "(bad)", { XX } },
4450 { "(bad)", { XX } },
96fbad73 4451 /* d0 */
ce518a5f
L		 4452 { "(bad)", { XX } },
4453 { "(bad)", { XX } },
4454 { "(bad)", { XX } },
4455 { "(bad)", { XX } },
4456 { "(bad)", { XX } },
4457 { "(bad)", { XX } },
4458 { "(bad)", { XX } },
4459 { "(bad)", { XX } },
96fbad73 4460 /* d8 */
ce518a5f
L		 4461 { "(bad)", { XX } },
4462 { "(bad)", { XX } },
4463 { "(bad)", { XX } },
4464 { "(bad)", { XX } },
4465 { "(bad)", { XX } },
4466 { "(bad)", { XX } },
4467 { "(bad)", { XX } },
4468 { "(bad)", { XX } },
96fbad73 4469 /* e0 */
ce518a5f
L		 4470 { "(bad)", { XX } },
4471 { "(bad)", { XX } },
4472 { "(bad)", { XX } },
4473 { "(bad)", { XX } },
4474 { "(bad)", { XX } },
4475 { "(bad)", { XX } },
4476 { "(bad)", { XX } },
4477 { "(bad)", { XX } },
96fbad73 4478 /* e8 */
ce518a5f
L		 4479 { "(bad)", { XX } },
4480 { "(bad)", { XX } },
4481 { "(bad)", { XX } },
4482 { "(bad)", { XX } },
4483 { "(bad)", { XX } },
4484 { "(bad)", { XX } },
4485 { "(bad)", { XX } },
4486 { "(bad)", { XX } },
96fbad73 4487 /* f0 */
ce518a5f
L		 4488 { "(bad)", { XX } },
4489 { "(bad)", { XX } },
4490 { "(bad)", { XX } },
4491 { "(bad)", { XX } },
4492 { "(bad)", { XX } },
4493 { "(bad)", { XX } },
4494 { "(bad)", { XX } },
4495 { "(bad)", { XX } },
96fbad73 4496 /* f8 */
ce518a5f
L		 4497 { "(bad)", { XX } },
4498 { "(bad)", { XX } },
4499 { "(bad)", { XX } },
4500 { "(bad)", { XX } },
4501 { "(bad)", { XX } },
4502 { "(bad)", { XX } },
4503 { "(bad)", { XX } },
4504 { "(bad)", { XX } },
4505 }
331d2d0d
L		 4506};
4507
1ceb70f8 4508static const struct dis386 mod_table[][2] = {
b844680a 4509 {
1ceb70f8 4510 /* MOD_8D */
d8faab4e
L		 4511 { "leaS", { Gv, M } },
4512 { "(bad)", { XX } },
4513 },
4514 {
1ceb70f8 4515 /* MOD_0F13 */
4e7d34a6 4516 { "movlpX", { EXq, XM } },
d8faab4e
L		 4517 { "(bad)", { XX } },
4518 },
4519 {
1ceb70f8 4520 /* MOD_0F17 */
4e7d34a6 4521 { "movhpX", { EXq, XM } },
d8faab4e
L		 4522 { "(bad)", { XX } },
4523 },
4524 {
1ceb70f8 4525 /* MOD_0F20 */
d8faab4e 4526 { "(bad)", { XX } },
4e7d34a6 4527 { "movZ", { Rm, Cm } },
d8faab4e
L		 4528 },
4529 {
1ceb70f8 4530 /* MOD_0F21 */
d8faab4e 4531 { "(bad)", { XX } },
4e7d34a6 4532 { "movZ", { Rm, Dm } },
d8faab4e
L		 4533 },
4534 {
1ceb70f8 4535 /* MOD_0F22 */
d8faab4e 4536 { "(bad)", { XX } },
4e7d34a6 4537 { "movZ", { Cm, Rm } },
d8faab4e
L		 4538 },
4539 {
1ceb70f8 4540 /* MOD_0F23 */
4e7d34a6
L		 4541 { "(bad)", { XX } },
4542 { "movZ", { Dm, Rm } },
b844680a
L		 4543 },
4544 {
1ceb70f8 4545 /* MOD_0F24 */
4e7d34a6
L		 4546 { THREE_BYTE_TABLE (THREE_BYTE_0F24) },
4547 { "movL", { Rd, Td } },
b844680a
L		 4548 },
4549 {
1ceb70f8 4550 /* MOD_0F26 */
d8faab4e 4551 { "(bad)", { XX } },
4e7d34a6 4552 { "movL", { Td, Rd } },
d8faab4e
L		 4553 },
4554 {
1ceb70f8 4555 /* MOD_0FB2 */
4e7d34a6 4556 { "lssS", { Gv, Mp } },
b844680a
L		 4557 { "(bad)", { XX } },
4558 },
4559 {
1ceb70f8 4560 /* MOD_0FB4 */
4e7d34a6 4561 { "lfsS", { Gv, Mp } },
b844680a
L		 4562 { "(bad)", { XX } },
4563 },
4564 {
1ceb70f8 4565 /* MOD_0FB5 */
4e7d34a6 4566 { "lgsS", { Gv, Mp } },
b844680a 4567 { "(bad)", { XX } },
b844680a
L		 4568 },
4569 {
1ceb70f8 4570 /* MOD_0F01_REG_0 */
4e7d34a6 4571 { X86_64_TABLE (X86_64_0F01_REG_0) },
1ceb70f8 4572 { RM_TABLE (RM_0F01_REG_0) },
b844680a
L		 4573 },
4574 {
1ceb70f8 4575 /* MOD_0F01_REG_1 */
4e7d34a6 4576 { X86_64_TABLE (X86_64_0F01_REG_1) },
1ceb70f8 4577 { RM_TABLE (RM_0F01_REG_1) },
b844680a
L		 4578 },
4579 {
1ceb70f8 4580 /* MOD_0F01_REG_2 */
4e7d34a6 4581 { X86_64_TABLE (X86_64_0F01_REG_2) },
b844680a 4582 { "(bad)", { XX } },
b844680a
L		 4583 },
4584 {
1ceb70f8 4585 /* MOD_0F01_REG_3 */
4e7d34a6 4586 { X86_64_TABLE (X86_64_0F01_REG_3) },
1ceb70f8 4587 { RM_TABLE (RM_0F01_REG_3) },
b844680a
L		 4588 },
4589 {
1ceb70f8 4590 /* MOD_0F01_REG_7 */
4e7d34a6 4591 { "invlpg", { Mb } },
1ceb70f8 4592 { RM_TABLE (RM_0F01_REG_7) },
b844680a
L		 4593 },
4594 {
1ceb70f8 4595 /* MOD_0F18_REG_0 */
4e7d34a6 4596 { "prefetchnta", { Mb } },
b844680a 4597 { "(bad)", { XX } },
b844680a
L		 4598 },
4599 {
1ceb70f8 4600 /* MOD_0F18_REG_1 */
4e7d34a6 4601 { "prefetcht0", { Mb } },
b844680a 4602 { "(bad)", { XX } },
b844680a
L		 4603 },
4604 {
1ceb70f8 4605 /* MOD_0F18_REG_2 */
4e7d34a6 4606 { "prefetcht1", { Mb } },
b844680a 4607 { "(bad)", { XX } },
b844680a
L		 4608 },
4609 {
1ceb70f8 4610 /* MOD_0F18_REG_3 */
4e7d34a6 4611 { "prefetcht2", { Mb } },
b844680a 4612 { "(bad)", { XX } },
b844680a
L		 4613 },
4614 {
1ceb70f8 4615 /* MOD_0F71_REG_2 */
b844680a 4616 { "(bad)", { XX } },
4e7d34a6 4617 { "psrlw", { MS, Ib } },
b844680a
L		 4618 },
4619 {
1ceb70f8 4620 /* MOD_0F71_REG_4 */
b844680a 4621 { "(bad)", { XX } },
4e7d34a6 4622 { "psraw", { MS, Ib } },
b844680a
L		 4623 },
4624 {
1ceb70f8 4625 /* MOD_0F71_REG_6 */
b844680a 4626 { "(bad)", { XX } },
4e7d34a6 4627 { "psllw", { MS, Ib } },
b844680a
L		 4628 },
4629 {
1ceb70f8 4630 /* MOD_0F72_REG_2 */
b844680a 4631 { "(bad)", { XX } },
4e7d34a6 4632 { "psrld", { MS, Ib } },
b844680a
L		 4633 },
4634 {
1ceb70f8 4635 /* MOD_0F72_REG_4 */
b844680a 4636 { "(bad)", { XX } },
4e7d34a6 4637 { "psrad", { MS, Ib } },
b844680a
L		 4638 },
4639 {
1ceb70f8 4640 /* MOD_0F72_REG_6 */
b844680a 4641 { "(bad)", { XX } },
4e7d34a6 4642 { "pslld", { MS, Ib } },
b844680a
L		 4643 },
4644 {
1ceb70f8 4645 /* MOD_0F73_REG_2 */
4e7d34a6
L		 4646 { "(bad)", { XX } },
4647 { "psrlq", { MS, Ib } },
b844680a
L		 4648 },
4649 {
1ceb70f8 4650 /* MOD_0F73_REG_3 */
b844680a 4651 { "(bad)", { XX } },
1ceb70f8 4652 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
b844680a
L		 4653 },
4654 {
1ceb70f8 4655 /* MOD_0F73_REG_6 */
b844680a 4656 { "(bad)", { XX } },
4e7d34a6 4657 { "psllq", { MS, Ib } },
b844680a
L		 4658 },
4659 {
1ceb70f8 4660 /* MOD_0F73_REG_7 */
b844680a 4661 { "(bad)", { XX } },
1ceb70f8 4662 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
b844680a
L		 4663 },
4664 {
1ceb70f8 4665 /* MOD_0FAE_REG_0 */
4e7d34a6 4666 { "fxsave", { M } },
b844680a
L		 4667 { "(bad)", { XX } },
4668 },
d8faab4e 4669 {
1ceb70f8 4670 /* MOD_0FAE_REG_1 */
4e7d34a6 4671 { "fxrstor", { M } },
d8faab4e
L		 4672 { "(bad)", { XX } },
4673 },
4674 {
1ceb70f8 4675 /* MOD_0FAE_REG_2 */
4e7d34a6 4676 { "ldmxcsr", { Md } },
d8faab4e
L		 4677 { "(bad)", { XX } },
4678 },
876d4bfa 4679 {
1ceb70f8 4680 /* MOD_0FAE_REG_3 */
4e7d34a6 4681 { "stmxcsr", { Md } },
876d4bfa
L		 4682 { "(bad)", { XX } },
4683 },
4684 {
1ceb70f8 4685 /* MOD_0FAE_REG_5 */
876d4bfa 4686 { "(bad)", { XX } },
1ceb70f8 4687 { RM_TABLE (RM_0FAE_REG_5) },
876d4bfa
L		 4688 },
4689 {
1ceb70f8 4690 /* MOD_0FAE_REG_6 */
4e7d34a6 4691 { "(bad)", { XX } },
1ceb70f8 4692 { RM_TABLE (RM_0FAE_REG_6) },
876d4bfa
L		 4693 },
4694 {
1ceb70f8 4695 /* MOD_0FAE_REG_7 */
4e7d34a6 4696 { "clflush", { Mb } },
1ceb70f8 4697 { RM_TABLE (RM_0FAE_REG_7) },
876d4bfa 4698 },
bbedc832 4699 {
1ceb70f8
L		 4700 /* MOD_0FC7_REG_6 */
4701 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
4e7d34a6 4702 { "(bad)", { XX } },
bbedc832 4703 },
144c41d9 4704 {
1ceb70f8 4705 /* MOD_0FC7_REG_7 */
4e7d34a6
L		 4706 { "vmptrst", { Mq } },
4707 { "(bad)", { XX } },
144c41d9 4708 },
1afd85e3 4709 {
1ceb70f8 4710 /* MOD_0F12_PREFIX_0 */
df26e7af
L		 4711 { "movlps", { XM, EXq } },
4712 { "movhlps", { XM, EXq } },
1afd85e3
L		 4713 },
4714 {
1ceb70f8 4715 /* MOD_0F16_PREFIX_0 */
df26e7af
L		 4716 { "movhps", { XM, EXq } },
4717 { "movlhps", { XM, EXq } },
1afd85e3
L		 4718 },
4719 {
1ceb70f8 4720 /* MOD_0FF0_PREFIX_3 */
4e7d34a6 4721 { "lddqu", { XM, M } },
1afd85e3 4722 { "(bad)", { XX } },
1afd85e3
L		 4723 },
4724 {
1ceb70f8 4725 /* MOD_62_32BIT */
4e7d34a6 4726 { "bound{S|}", { Gv, Ma } },
1afd85e3 4727 { "(bad)", { XX } },
1afd85e3
L		 4728 },
4729 {
1ceb70f8 4730 /* MOD_C4_32BIT */
4e7d34a6
L		 4731 { "lesS", { Gv, Mp } },
4732 { "(bad)", { XX } },
1afd85e3
L		 4733 },
4734 {
1ceb70f8 4735 /* MOD_C5_32BIT */
4e7d34a6 4736 { "ldsS", { Gv, Mp } },
1afd85e3 4737 { "(bad)", { XX } },
1afd85e3 4738 },
b844680a
L		 4739};
4740
1ceb70f8 4741static const struct dis386 rm_table[][8] = {
b844680a 4742 {
1ceb70f8 4743 /* RM_0F01_REG_0 */
b844680a
L		 4744 { "(bad)", { XX } },
4745 { "vmcall", { Skip_MODRM } },
4746 { "vmlaunch", { Skip_MODRM } },
4747 { "vmresume", { Skip_MODRM } },
4748 { "vmxoff", { Skip_MODRM } },
4749 { "(bad)", { XX } },
4750 { "(bad)", { XX } },
4751 { "(bad)", { XX } },
4752 },
4753 {
1ceb70f8 4754 /* RM_0F01_REG_1 */
b844680a
L		 4755 { "monitor", { { OP_Monitor, 0 } } },
4756 { "mwait", { { OP_Mwait, 0 } } },
4757 { "(bad)", { XX } },
4758 { "(bad)", { XX } },
4759 { "(bad)", { XX } },
4760 { "(bad)", { XX } },
4761 { "(bad)", { XX } },
4762 { "(bad)", { XX } },
4763 },
4764 {
1ceb70f8 4765 /* RM_0F01_REG_3 */
4e7d34a6
L		 4766 { "vmrun", { Skip_MODRM } },
4767 { "vmmcall", { Skip_MODRM } },
4768 { "vmload", { Skip_MODRM } },
4769 { "vmsave", { Skip_MODRM } },
4770 { "stgi", { Skip_MODRM } },
4771 { "clgi", { Skip_MODRM } },
4772 { "skinit", { Skip_MODRM } },
4773 { "invlpga", { Skip_MODRM } },
4774 },
4775 {
1ceb70f8 4776 /* RM_0F01_REG_7 */
4e7d34a6
L		 4777 { "swapgs", { Skip_MODRM } },
4778 { "rdtscp", { Skip_MODRM } },
b844680a
L		 4779 { "(bad)", { XX } },
4780 { "(bad)", { XX } },
4781 { "(bad)", { XX } },
4782 { "(bad)", { XX } },
4783 { "(bad)", { XX } },
4784 { "(bad)", { XX } },
4785 },
4786 {
1ceb70f8 4787 /* RM_0FAE_REG_5 */
4e7d34a6 4788 { "lfence", { Skip_MODRM } },
b844680a
L		 4789 { "(bad)", { XX } },
4790 { "(bad)", { XX } },
4791 { "(bad)", { XX } },
4792 { "(bad)", { XX } },
4793 { "(bad)", { XX } },
4794 { "(bad)", { XX } },
4795 { "(bad)", { XX } },
4796 },
4797 {
1ceb70f8 4798 /* RM_0FAE_REG_6 */
4e7d34a6 4799 { "mfence", { Skip_MODRM } },
b844680a
L		 4800 { "(bad)", { XX } },
4801 { "(bad)", { XX } },
4802 { "(bad)", { XX } },
4803 { "(bad)", { XX } },
4804 { "(bad)", { XX } },
4805 { "(bad)", { XX } },
4806 { "(bad)", { XX } },
4807 },
bbedc832 4808 {
1ceb70f8 4809 /* RM_0FAE_REG_7 */
4e7d34a6
L		 4810 { "sfence", { Skip_MODRM } },
4811 { "(bad)", { XX } },
bbedc832
L		 4812 { "(bad)", { XX } },
4813 { "(bad)", { XX } },
4814 { "(bad)", { XX } },
4815 { "(bad)", { XX } },
4816 { "(bad)", { XX } },
4817 { "(bad)", { XX } },
144c41d9 4818 },
b844680a
L		 4819};
4820
c608c12e
AM		 4821#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
4822
252b5132 4823static void
26ca5450 4824ckprefix (void)
252b5132 4825{
52b15da3
JH		 4826 int newrex;
4827 rex = 0;
252b5132 4828 prefixes = 0;
7d421014 4829 used_prefixes = 0;
52b15da3 4830 rex_used = 0;
252b5132
RH		 4831 while (1)
4832 {
4833 FETCH_DATA (the_info, codep + 1);
52b15da3 4834 newrex = 0;
252b5132
RH		 4835 switch (*codep)
4836 {
52b15da3
JH		 4837 /* REX prefixes family. */
4838 case 0x40:
4839 case 0x41:
4840 case 0x42:
4841 case 0x43:
4842 case 0x44:
4843 case 0x45:
4844 case 0x46:
4845 case 0x47:
4846 case 0x48:
4847 case 0x49:
4848 case 0x4a:
4849 case 0x4b:
4850 case 0x4c:
4851 case 0x4d:
4852 case 0x4e:
4853 case 0x4f:
cb712a9e 4854 if (address_mode == mode_64bit)
52b15da3
JH		 4855 newrex = *codep;
4856 else
4857 return;
4858 break;
252b5132
RH		 4859 case 0xf3:
4860 prefixes |= PREFIX_REPZ;
4861 break;
4862 case 0xf2:
4863 prefixes |= PREFIX_REPNZ;
4864 break;
4865 case 0xf0:
4866 prefixes |= PREFIX_LOCK;
4867 break;
4868 case 0x2e:
4869 prefixes |= PREFIX_CS;
4870 break;
4871 case 0x36:
4872 prefixes |= PREFIX_SS;
4873 break;
4874 case 0x3e:
4875 prefixes |= PREFIX_DS;
4876 break;
4877 case 0x26:
4878 prefixes |= PREFIX_ES;
4879 break;
4880 case 0x64:
4881 prefixes |= PREFIX_FS;
4882 break;
4883 case 0x65:
4884 prefixes |= PREFIX_GS;
4885 break;
4886 case 0x66:
4887 prefixes |= PREFIX_DATA;
4888 break;
4889 case 0x67:
4890 prefixes |= PREFIX_ADDR;
4891 break;
5076851f 4892 case FWAIT_OPCODE:
252b5132
RH		 4893 /* fwait is really an instruction. If there are prefixes
4894 before the fwait, they belong to the fwait, *not* to the
4895 following instruction. */
3e7d61b2 4896 if (prefixes || rex)
252b5132
RH		 4897 {
4898 prefixes |= PREFIX_FWAIT;
4899 codep++;
4900 return;
4901 }
4902 prefixes = PREFIX_FWAIT;
4903 break;
4904 default:
4905 return;
4906 }
52b15da3
JH		 4907 /* Rex is ignored when followed by another prefix. */
4908 if (rex)
4909 {
3e7d61b2
AM		 4910 rex_used = rex;
4911 return;
52b15da3
JH		 4912 }
4913 rex = newrex;
252b5132
RH		 4914 codep++;
4915 }
4916}
4917
7d421014
ILT		 4918/* Return the name of the prefix byte PREF, or NULL if PREF is not a
4919 prefix byte. */
4920
4921static const char *
26ca5450 4922prefix_name (int pref, int sizeflag)
7d421014 4923{
0003779b
L		 4924 static const char *rexes [16] =
4925 {
4926 "rex", /* 0x40 */
4927 "rex.B", /* 0x41 */
4928 "rex.X", /* 0x42 */
4929 "rex.XB", /* 0x43 */
4930 "rex.R", /* 0x44 */
4931 "rex.RB", /* 0x45 */
4932 "rex.RX", /* 0x46 */
4933 "rex.RXB", /* 0x47 */
4934 "rex.W", /* 0x48 */
4935 "rex.WB", /* 0x49 */
4936 "rex.WX", /* 0x4a */
4937 "rex.WXB", /* 0x4b */
4938 "rex.WR", /* 0x4c */
4939 "rex.WRB", /* 0x4d */
4940 "rex.WRX", /* 0x4e */
4941 "rex.WRXB", /* 0x4f */
4942 };
4943
7d421014
ILT		 4944 switch (pref)
4945 {
52b15da3
JH		 4946 /* REX prefixes family. */
4947 case 0x40:
52b15da3 4948 case 0x41:
52b15da3 4949 case 0x42:
52b15da3 4950 case 0x43:
52b15da3 4951 case 0x44:
52b15da3 4952 case 0x45:
52b15da3 4953 case 0x46:
52b15da3 4954 case 0x47:
52b15da3 4955 case 0x48:
52b15da3 4956 case 0x49:
52b15da3 4957 case 0x4a:
52b15da3 4958 case 0x4b:
52b15da3 4959 case 0x4c:
52b15da3 4960 case 0x4d:
52b15da3 4961 case 0x4e:
52b15da3 4962 case 0x4f:
0003779b 4963 return rexes [pref - 0x40];
7d421014
ILT		 4964 case 0xf3:
4965 return "repz";
4966 case 0xf2:
4967 return "repnz";
4968 case 0xf0:
4969 return "lock";
4970 case 0x2e:
4971 return "cs";
4972 case 0x36:
4973 return "ss";
4974 case 0x3e:
4975 return "ds";
4976 case 0x26:
4977 return "es";
4978 case 0x64:
4979 return "fs";
4980 case 0x65:
4981 return "gs";
4982 case 0x66:
4983 return (sizeflag & DFLAG) ? "data16" : "data32";
4984 case 0x67:
cb712a9e 4985 if (address_mode == mode_64bit)
db6eb5be 4986 return (sizeflag & AFLAG) ? "addr32" : "addr64";
c1a64871 4987 else
2888cb7a 4988 return (sizeflag & AFLAG) ? "addr16" : "addr32";
7d421014
ILT		 4989 case FWAIT_OPCODE:
4990 return "fwait";
4991 default:
4992 return NULL;
4993 }
4994}
4995
ce518a5f
L		 4996static char op_out[MAX_OPERANDS][100];
4997static int op_ad, op_index[MAX_OPERANDS];
1d9f512f 4998static int two_source_ops;
ce518a5f
L		 4999static bfd_vma op_address[MAX_OPERANDS];
5000static bfd_vma op_riprel[MAX_OPERANDS];
52b15da3 5001static bfd_vma start_pc;
ce518a5f 5002
252b5132
RH		 5003/*
5004 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
5005 * (see topic "Redundant prefixes" in the "Differences from 8086"
5006 * section of the "Virtual 8086 Mode" chapter.)
5007 * 'pc' should be the address of this instruction, it will
5008 * be used to print the target address if this is a relative jump or call
5009 * The function returns the length of this instruction in bytes.
5010 */
5011
252b5132
RH		 5012static char intel_syntax;
5013static char open_char;
5014static char close_char;
5015static char separator_char;
5016static char scale_char;
5017
e396998b
AM		 5018/* Here for backwards compatibility. When gdb stops using
5019 print_insn_i386_att and print_insn_i386_intel these functions can
5020 disappear, and print_insn_i386 be merged into print_insn. */
252b5132 5021int
26ca5450 5022print_insn_i386_att (bfd_vma pc, disassemble_info *info)
252b5132
RH		 5023{
5024 intel_syntax = 0;
e396998b
AM		 5025
5026 return print_insn (pc, info);
252b5132
RH		 5027}
5028
5029int
26ca5450 5030print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
252b5132
RH		 5031{
5032 intel_syntax = 1;
e396998b
AM		 5033
5034 return print_insn (pc, info);
252b5132
RH		 5035}
5036
e396998b 5037int
26ca5450 5038print_insn_i386 (bfd_vma pc, disassemble_info *info)
e396998b
AM		 5039{
5040 intel_syntax = -1;
5041
5042 return print_insn (pc, info);
5043}
5044
f59a29b9
L		 5045void
5046print_i386_disassembler_options (FILE *stream)
5047{
5048 fprintf (stream, _("\n\
5049The following i386/x86-64 specific disassembler options are supported for use\n\
5050with the -M switch (multiple options should be separated by commas):\n"));
5051
5052 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
5053 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
5054 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
5055 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
5056 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
5057 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
5058 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
5059 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
5060 fprintf (stream, _(" data32 Assume 32bit data size\n"));
5061 fprintf (stream, _(" data16 Assume 16bit data size\n"));
5062 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
5063}
5064
b844680a
L		 5065/* Get a pointer to struct dis386 with a valid name. */
5066
5067static const struct dis386 *
8bb15339 5068get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
b844680a
L		 5069{
5070 int index;
5071
5072 if (dp->name != NULL)
5073 return dp;
5074
5075 switch (dp->op[0].bytemode)
5076 {
1ceb70f8
L		 5077 case USE_REG_TABLE:
5078 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
5079 break;
5080
5081 case USE_MOD_TABLE:
5082 index = modrm.mod == 0x3 ? 1 : 0;
5083 dp = &mod_table[dp->op[1].bytemode][index];
5084 break;
5085
5086 case USE_RM_TABLE:
5087 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
b844680a
L		 5088 break;
5089
4e7d34a6 5090 case USE_PREFIX_TABLE:
b844680a
L		 5091 index = 0;
5092 used_prefixes |= (prefixes & PREFIX_REPZ);
5093 if (prefixes & PREFIX_REPZ)
5094 {
5095 index = 1;
5096 repz_prefix = NULL;
5097 }
5098 else
5099 {
5100 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
5101 PREFIX_DATA. */
5102 used_prefixes |= (prefixes & PREFIX_REPNZ);
5103 if (prefixes & PREFIX_REPNZ)
5104 {
5105 index = 3;
5106 repnz_prefix = NULL;
5107 }
5108 else
5109 {
5110 used_prefixes |= (prefixes & PREFIX_DATA);
5111 if (prefixes & PREFIX_DATA)
5112 {
5113 index = 2;
5114 data_prefix = NULL;
5115 }
5116 }
5117 }
1ceb70f8 5118 dp = &prefix_table[dp->op[1].bytemode][index];
b844680a
L		 5119 break;
5120
4e7d34a6 5121 case USE_X86_64_TABLE:
b844680a
L		 5122 index = address_mode == mode_64bit ? 1 : 0;
5123 dp = &x86_64_table[dp->op[1].bytemode][index];
5124 break;
5125
4e7d34a6 5126 case USE_3BYTE_TABLE:
8bb15339
L		 5127 FETCH_DATA (info, codep + 2);
5128 index = *codep++;
5129 dp = &three_byte_table[dp->op[1].bytemode][index];
5130 modrm.mod = (*codep >> 6) & 3;
5131 modrm.reg = (*codep >> 3) & 7;
5132 modrm.rm = *codep & 7;
5133 break;
5134
b844680a
L		 5135 default:
5136 oappend (INTERNAL_DISASSEMBLER_ERROR);
5137 return NULL;
5138 }
5139
5140 if (dp->name != NULL)
5141 return dp;
5142 else
8bb15339 5143 return get_valid_dis386 (dp, info);
b844680a
L		 5144}
5145
e396998b 5146static int
26ca5450 5147print_insn (bfd_vma pc, disassemble_info *info)
252b5132 5148{
2da11e11 5149 const struct dis386 *dp;
252b5132 5150 int i;
ce518a5f 5151 char *op_txt[MAX_OPERANDS];
252b5132 5152 int needcomma;
e396998b
AM		 5153 int sizeflag;
5154 const char *p;
252b5132 5155 struct dis_private priv;
eec0f4ca 5156 unsigned char op;
b844680a
L		 5157 char prefix_obuf[32];
5158 char *prefix_obufp;
252b5132 5159
cb712a9e
L		 5160 if (info->mach == bfd_mach_x86_64_intel_syntax
5161 || info->mach == bfd_mach_x86_64)
5162 address_mode = mode_64bit;
5163 else
5164 address_mode = mode_32bit;
52b15da3 5165
8373f971 5166 if (intel_syntax == (char) -1)
e396998b
AM		 5167 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
5168 || info->mach == bfd_mach_x86_64_intel_syntax);
5169
2da11e11 5170 if (info->mach == bfd_mach_i386_i386
52b15da3
JH		 5171 || info->mach == bfd_mach_x86_64
5172 || info->mach == bfd_mach_i386_i386_intel_syntax
5173 || info->mach == bfd_mach_x86_64_intel_syntax)
e396998b 5174 priv.orig_sizeflag = AFLAG | DFLAG;
2da11e11 5175 else if (info->mach == bfd_mach_i386_i8086)
e396998b 5176 priv.orig_sizeflag = 0;
2da11e11
AM		 5177 else
5178 abort ();
e396998b
AM		 5179
5180 for (p = info->disassembler_options; p != NULL; )
5181 {
0112cd26 5182 if (CONST_STRNEQ (p, "x86-64"))
e396998b 5183 {
cb712a9e 5184 address_mode = mode_64bit;
e396998b
AM		 5185 priv.orig_sizeflag = AFLAG | DFLAG;
5186 }
0112cd26 5187 else if (CONST_STRNEQ (p, "i386"))
e396998b 5188 {
cb712a9e 5189 address_mode = mode_32bit;
e396998b
AM		 5190 priv.orig_sizeflag = AFLAG | DFLAG;
5191 }
0112cd26 5192 else if (CONST_STRNEQ (p, "i8086"))
e396998b 5193 {
cb712a9e 5194 address_mode = mode_16bit;
e396998b
AM		 5195 priv.orig_sizeflag = 0;
5196 }
0112cd26 5197 else if (CONST_STRNEQ (p, "intel"))
e396998b
AM		 5198 {
5199 intel_syntax = 1;
5200 }
0112cd26 5201 else if (CONST_STRNEQ (p, "att"))
e396998b
AM		 5202 {
5203 intel_syntax = 0;
5204 }
0112cd26 5205 else if (CONST_STRNEQ (p, "addr"))
e396998b 5206 {
f59a29b9
L		 5207 if (address_mode == mode_64bit)
5208 {
5209 if (p[4] == '3' && p[5] == '2')
5210 priv.orig_sizeflag &= ~AFLAG;
5211 else if (p[4] == '6' && p[5] == '4')
5212 priv.orig_sizeflag |= AFLAG;
5213 }
5214 else
5215 {
5216 if (p[4] == '1' && p[5] == '6')
5217 priv.orig_sizeflag &= ~AFLAG;
5218 else if (p[4] == '3' && p[5] == '2')
5219 priv.orig_sizeflag |= AFLAG;
5220 }
e396998b 5221 }
0112cd26 5222 else if (CONST_STRNEQ (p, "data"))
e396998b
AM		 5223 {
5224 if (p[4] == '1' && p[5] == '6')
5225 priv.orig_sizeflag &= ~DFLAG;
5226 else if (p[4] == '3' && p[5] == '2')
5227 priv.orig_sizeflag |= DFLAG;
5228 }
0112cd26 5229 else if (CONST_STRNEQ (p, "suffix"))
e396998b
AM		 5230 priv.orig_sizeflag |= SUFFIX_ALWAYS;
5231
5232 p = strchr (p, ',');
5233 if (p != NULL)
5234 p++;
5235 }
5236
5237 if (intel_syntax)
5238 {
5239 names64 = intel_names64;
5240 names32 = intel_names32;
5241 names16 = intel_names16;
5242 names8 = intel_names8;
5243 names8rex = intel_names8rex;
5244 names_seg = intel_names_seg;
db51cc60
L		 5245 index64 = intel_index64;
5246 index32 = intel_index32;
e396998b
AM		 5247 index16 = intel_index16;
5248 open_char = '[';
5249 close_char = ']';
5250 separator_char = '+';
5251 scale_char = '*';
5252 }
5253 else
5254 {
5255 names64 = att_names64;
5256 names32 = att_names32;
5257 names16 = att_names16;
5258 names8 = att_names8;
5259 names8rex = att_names8rex;
5260 names_seg = att_names_seg;
db51cc60
L		 5261 index64 = att_index64;
5262 index32 = att_index32;
e396998b
AM		 5263 index16 = att_index16;
5264 open_char = '(';
5265 close_char = ')';
5266 separator_char = ',';
5267 scale_char = ',';
5268 }
2da11e11 5269
4fe53c98 5270 /* The output looks better if we put 7 bytes on a line, since that
c608c12e 5271 puts most long word instructions on a single line. */
4fe53c98 5272 info->bytes_per_line = 7;
252b5132 5273
26ca5450 5274 info->private_data = &priv;
252b5132
RH		 5275 priv.max_fetched = priv.the_buffer;
5276 priv.insn_start = pc;
252b5132
RH		 5277
5278 obuf[0] = 0;
ce518a5f
L		 5279 for (i = 0; i < MAX_OPERANDS; ++i)
5280 {
5281 op_out[i][0] = 0;
5282 op_index[i] = -1;
5283 }
252b5132
RH		 5284
5285 the_info = info;
5286 start_pc = pc;
e396998b
AM		 5287 start_codep = priv.the_buffer;
5288 codep = priv.the_buffer;
252b5132 5289
5076851f
ILT		 5290 if (setjmp (priv.bailout) != 0)
5291 {
7d421014
ILT		 5292 const char *name;
5293
5076851f 5294 /* Getting here means we tried for data but didn't get it. That
e396998b
AM		 5295 means we have an incomplete instruction of some sort. Just
5296 print the first byte as a prefix or a .byte pseudo-op. */
5297 if (codep > priv.the_buffer)
5076851f 5298 {
e396998b 5299 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 5300 if (name != NULL)
5301 (*info->fprintf_func) (info->stream, "%s", name);
5302 else
5076851f 5303 {
7d421014
ILT		 5304 /* Just print the first byte as a .byte instruction. */
5305 (*info->fprintf_func) (info->stream, ".byte 0x%x",
e396998b 5306 (unsigned int) priv.the_buffer[0]);
5076851f 5307 }
5076851f 5308
7d421014 5309 return 1;
5076851f
ILT		 5310 }
5311
5312 return -1;
5313 }
5314
52b15da3 5315 obufp = obuf;
252b5132
RH		 5316 ckprefix ();
5317
5318 insn_codep = codep;
e396998b 5319 sizeflag = priv.orig_sizeflag;
252b5132
RH		 5320
5321 FETCH_DATA (info, codep + 1);
5322 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
5323
3e7d61b2
AM		 5324 if (((prefixes & PREFIX_FWAIT)
5325 && ((*codep < 0xd8) || (*codep > 0xdf)))
5326 || (rex && rex_used))
252b5132 5327 {
7d421014
ILT		 5328 const char *name;
5329
3e7d61b2
AM		 5330 /* fwait not followed by floating point instruction, or rex followed
5331 by other prefixes. Print the first prefix. */
e396998b 5332 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 5333 if (name == NULL)
5334 name = INTERNAL_DISASSEMBLER_ERROR;
5335 (*info->fprintf_func) (info->stream, "%s", name);
5336 return 1;
252b5132
RH		 5337 }
5338
eec0f4ca 5339 op = 0;
252b5132
RH		 5340 if (*codep == 0x0f)
5341 {
eec0f4ca 5342 unsigned char threebyte;
252b5132 5343 FETCH_DATA (info, codep + 2);
eec0f4ca
L		 5344 threebyte = *++codep;
5345 dp = &dis386_twobyte[threebyte];
252b5132 5346 need_modrm = twobyte_has_modrm[*codep];
eec0f4ca 5347 codep++;
252b5132
RH		 5348 }
5349 else
5350 {
6439fc28 5351 dp = &dis386[*codep];
252b5132 5352 need_modrm = onebyte_has_modrm[*codep];
eec0f4ca 5353 codep++;
252b5132 5354 }
246c51aa 5355
b844680a 5356 if ((prefixes & PREFIX_REPZ))
7d421014 5357 {
b844680a 5358 repz_prefix = "repz ";
7d421014
ILT		 5359 used_prefixes |= PREFIX_REPZ;
5360 }
b844680a
L		 5361 else
5362 repz_prefix = NULL;
5363
5364 if ((prefixes & PREFIX_REPNZ))
7d421014 5365 {
b844680a 5366 repnz_prefix = "repnz ";
7d421014
ILT		 5367 used_prefixes |= PREFIX_REPNZ;
5368 }
b844680a
L		 5369 else
5370 repnz_prefix = NULL;
050dfa73 5371
b844680a 5372 if ((prefixes & PREFIX_LOCK))
7d421014 5373 {
b844680a 5374 lock_prefix = "lock ";
7d421014
ILT		 5375 used_prefixes |= PREFIX_LOCK;
5376 }
b844680a
L		 5377 else
5378 lock_prefix = NULL;
c608c12e 5379
b844680a 5380 addr_prefix = NULL;
c608c12e
AM		 5381 if (prefixes & PREFIX_ADDR)
5382 {
5383 sizeflag ^= AFLAG;
ce518a5f 5384 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
3ffd33cf 5385 {
cb712a9e 5386 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
b844680a 5387 addr_prefix = "addr32 ";
3ffd33cf 5388 else
b844680a 5389 addr_prefix = "addr16 ";
3ffd33cf
AM		 5390 used_prefixes |= PREFIX_ADDR;
5391 }
5392 }
5393
b844680a
L		 5394 data_prefix = NULL;
5395 if ((prefixes & PREFIX_DATA))
3ffd33cf
AM		 5396 {
5397 sizeflag ^= DFLAG;
ce518a5f
L		 5398 if (dp->op[2].bytemode == cond_jump_mode
5399 && dp->op[0].bytemode == v_mode
6439fc28 5400 && !intel_syntax)
3ffd33cf
AM		 5401 {
5402 if (sizeflag & DFLAG)
b844680a 5403 data_prefix = "data32 ";
3ffd33cf 5404 else
b844680a 5405 data_prefix = "data16 ";
3ffd33cf
AM		 5406 used_prefixes |= PREFIX_DATA;
5407 }
5408 }
5409
8bb15339 5410 if (need_modrm)
252b5132
RH		 5411 {
5412 FETCH_DATA (info, codep + 1);
7967e09e
L		 5413 modrm.mod = (*codep >> 6) & 3;
5414 modrm.reg = (*codep >> 3) & 7;
5415 modrm.rm = *codep & 7;
252b5132
RH		 5416 }
5417
ce518a5f 5418 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
252b5132
RH		 5419 {
5420 dofloat (sizeflag);
5421 }
5422 else
5423 {
8bb15339 5424 dp = get_valid_dis386 (dp, info);
b844680a 5425 if (dp != NULL && putop (dp->name, sizeflag) == 0)
ce518a5f
L		 5426 {
5427 for (i = 0; i < MAX_OPERANDS; ++i)
5428 {
246c51aa 5429 obufp = op_out[i];
ce518a5f
L		 5430 op_ad = MAX_OPERANDS - 1 - i;
5431 if (dp->op[i].rtn)
5432 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
5433 }
6439fc28 5434 }
252b5132
RH		 5435 }
5436
7d421014
ILT		 5437 /* See if any prefixes were not used. If so, print the first one
5438 separately. If we don't do this, we'll wind up printing an
5439 instruction stream which does not precisely correspond to the
5440 bytes we are disassembling. */
5441 if ((prefixes & ~used_prefixes) != 0)
5442 {
5443 const char *name;
5444
e396998b 5445 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 5446 if (name == NULL)
5447 name = INTERNAL_DISASSEMBLER_ERROR;
5448 (*info->fprintf_func) (info->stream, "%s", name);
5449 return 1;
5450 }
52b15da3
JH		 5451 if (rex & ~rex_used)
5452 {
5453 const char *name;
e396998b 5454 name = prefix_name (rex | 0x40, priv.orig_sizeflag);
52b15da3
JH		 5455 if (name == NULL)
5456 name = INTERNAL_DISASSEMBLER_ERROR;
5457 (*info->fprintf_func) (info->stream, "%s ", name);
5458 }
7d421014 5459
b844680a
L		 5460 prefix_obuf[0] = 0;
5461 prefix_obufp = prefix_obuf;
5462 if (lock_prefix)
5463 prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
5464 if (repz_prefix)
5465 prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
5466 if (repnz_prefix)
5467 prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
5468 if (addr_prefix)
5469 prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
5470 if (data_prefix)
5471 prefix_obufp = stpcpy (prefix_obufp, data_prefix);
5472
5473 if (prefix_obuf[0] != 0)
5474 (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
5475
252b5132 5476 obufp = obuf + strlen (obuf);
b844680a 5477 for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
252b5132
RH		 5478 oappend (" ");
5479 oappend (" ");
5480 (*info->fprintf_func) (info->stream, "%s", obuf);
5481
5482 /* The enter and bound instructions are printed with operands in the same
5483 order as the intel book; everything else is printed in reverse order. */
2da11e11 5484 if (intel_syntax || two_source_ops)
252b5132 5485 {
185b1163
L		 5486 bfd_vma riprel;
5487
ce518a5f
L		 5488 for (i = 0; i < MAX_OPERANDS; ++i)
5489 op_txt[i] = op_out[i];
246c51aa 5490
ce518a5f
L		 5491 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
5492 {
5493 op_ad = op_index[i];
5494 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
5495 op_index[MAX_OPERANDS - 1 - i] = op_ad;
185b1163
L		 5496 riprel = op_riprel[i];
5497 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
5498 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
ce518a5f 5499 }
252b5132
RH		 5500 }
5501 else
5502 {
ce518a5f
L		 5503 for (i = 0; i < MAX_OPERANDS; ++i)
5504 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
050dfa73
MM		 5505 }
5506
ce518a5f
L		 5507 needcomma = 0;
5508 for (i = 0; i < MAX_OPERANDS; ++i)
5509 if (*op_txt[i])
5510 {
5511 if (needcomma)
5512 (*info->fprintf_func) (info->stream, ",");
5513 if (op_index[i] != -1 && !op_riprel[i])
5514 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
5515 else
5516 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
5517 needcomma = 1;
5518 }
050dfa73 5519
ce518a5f 5520 for (i = 0; i < MAX_OPERANDS; i++)
52b15da3
JH		 5521 if (op_index[i] != -1 && op_riprel[i])
5522 {
5523 (*info->fprintf_func) (info->stream, " # ");
5524 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
5525 + op_address[op_index[i]]), info);
185b1163 5526 break;
52b15da3 5527 }
e396998b 5528 return codep - priv.the_buffer;
252b5132
RH		 5529}
5530
6439fc28 5531static const char *float_mem[] = {
252b5132 5532 /* d8 */
7c52e0e8
L		 5533 "fadd{s|}",
5534 "fmul{s|}",
5535 "fcom{s|}",
5536 "fcomp{s|}",
5537 "fsub{s|}",
5538 "fsubr{s|}",
5539 "fdiv{s|}",
5540 "fdivr{s|}",
db6eb5be 5541 /* d9 */
7c52e0e8 5542 "fld{s|}",
252b5132 5543 "(bad)",
7c52e0e8
L		 5544 "fst{s|}",
5545 "fstp{s|}",
9306ca4a 5546 "fldenvIC",
252b5132 5547 "fldcw",
9306ca4a 5548 "fNstenvIC",
252b5132
RH		 5549 "fNstcw",
5550 /* da */
7c52e0e8
L		 5551 "fiadd{l|}",
5552 "fimul{l|}",
5553 "ficom{l|}",
5554 "ficomp{l|}",
5555 "fisub{l|}",
5556 "fisubr{l|}",
5557 "fidiv{l|}",
5558 "fidivr{l|}",
252b5132 5559 /* db */
7c52e0e8
L		 5560 "fild{l|}",
5561 "fisttp{l|}",
5562 "fist{l|}",
5563 "fistp{l|}",
252b5132 5564 "(bad)",
6439fc28 5565 "fld{t||t|}",
252b5132 5566 "(bad)",
6439fc28 5567 "fstp{t||t|}",
252b5132 5568 /* dc */
7c52e0e8
L		 5569 "fadd{l|}",
5570 "fmul{l|}",
5571 "fcom{l|}",
5572 "fcomp{l|}",
5573 "fsub{l|}",
5574 "fsubr{l|}",
5575 "fdiv{l|}",
5576 "fdivr{l|}",
252b5132 5577 /* dd */
7c52e0e8
L		 5578 "fld{l|}",
5579 "fisttp{ll|}",
5580 "fst{l||}",
5581 "fstp{l|}",
9306ca4a 5582 "frstorIC",
252b5132 5583 "(bad)",
9306ca4a 5584 "fNsaveIC",
252b5132
RH		 5585 "fNstsw",
5586 /* de */
5587 "fiadd",
5588 "fimul",
5589 "ficom",
5590 "ficomp",
5591 "fisub",
5592 "fisubr",
5593 "fidiv",
5594 "fidivr",
5595 /* df */
5596 "fild",
ca164297 5597 "fisttp",
252b5132
RH		 5598 "fist",
5599 "fistp",
5600 "fbld",
7c52e0e8 5601 "fild{ll|}",
252b5132 5602 "fbstp",
7c52e0e8 5603 "fistp{ll|}",
1d9f512f
AM		 5604};
5605
5606static const unsigned char float_mem_mode[] = {
5607 /* d8 */
5608 d_mode,
5609 d_mode,
5610 d_mode,
5611 d_mode,
5612 d_mode,
5613 d_mode,
5614 d_mode,
5615 d_mode,
5616 /* d9 */
5617 d_mode,
5618 0,
5619 d_mode,
5620 d_mode,
5621 0,
5622 w_mode,
5623 0,
5624 w_mode,
5625 /* da */
5626 d_mode,
5627 d_mode,
5628 d_mode,
5629 d_mode,
5630 d_mode,
5631 d_mode,
5632 d_mode,
5633 d_mode,
5634 /* db */
5635 d_mode,
5636 d_mode,
5637 d_mode,
5638 d_mode,
5639 0,
9306ca4a 5640 t_mode,
1d9f512f 5641 0,
9306ca4a 5642 t_mode,
1d9f512f
AM		 5643 /* dc */
5644 q_mode,
5645 q_mode,
5646 q_mode,
5647 q_mode,
5648 q_mode,
5649 q_mode,
5650 q_mode,
5651 q_mode,
5652 /* dd */
5653 q_mode,
5654 q_mode,
5655 q_mode,
5656 q_mode,
5657 0,
5658 0,
5659 0,
5660 w_mode,
5661 /* de */
5662 w_mode,
5663 w_mode,
5664 w_mode,
5665 w_mode,
5666 w_mode,
5667 w_mode,
5668 w_mode,
5669 w_mode,
5670 /* df */
5671 w_mode,
5672 w_mode,
5673 w_mode,
5674 w_mode,
9306ca4a 5675 t_mode,
1d9f512f 5676 q_mode,
9306ca4a 5677 t_mode,
1d9f512f 5678 q_mode
252b5132
RH		 5679};
5680
ce518a5f
L		 5681#define ST { OP_ST, 0 }
5682#define STi { OP_STi, 0 }
252b5132 5683
4efba78c
L		 5684#define FGRPd9_2 NULL, { { NULL, 0 } }
5685#define FGRPd9_4 NULL, { { NULL, 1 } }
5686#define FGRPd9_5 NULL, { { NULL, 2 } }
5687#define FGRPd9_6 NULL, { { NULL, 3 } }
5688#define FGRPd9_7 NULL, { { NULL, 4 } }
5689#define FGRPda_5 NULL, { { NULL, 5 } }
5690#define FGRPdb_4 NULL, { { NULL, 6 } }
5691#define FGRPde_3 NULL, { { NULL, 7 } }
5692#define FGRPdf_4 NULL, { { NULL, 8 } }
252b5132 5693
2da11e11 5694static const struct dis386 float_reg[][8] = {
252b5132
RH		 5695 /* d8 */
5696 {
ce518a5f
L		 5697 { "fadd", { ST, STi } },
5698 { "fmul", { ST, STi } },
5699 { "fcom", { STi } },
5700 { "fcomp", { STi } },
5701 { "fsub", { ST, STi } },
5702 { "fsubr", { ST, STi } },
5703 { "fdiv", { ST, STi } },
5704 { "fdivr", { ST, STi } },
252b5132
RH		 5705 },
5706 /* d9 */
5707 {
ce518a5f
L		 5708 { "fld", { STi } },
5709 { "fxch", { STi } },
252b5132 5710 { FGRPd9_2 },
ce518a5f 5711 { "(bad)", { XX } },
252b5132
RH		 5712 { FGRPd9_4 },
5713 { FGRPd9_5 },
5714 { FGRPd9_6 },
5715 { FGRPd9_7 },
5716 },
5717 /* da */
5718 {
ce518a5f
L		 5719 { "fcmovb", { ST, STi } },
5720 { "fcmove", { ST, STi } },
5721 { "fcmovbe",{ ST, STi } },
5722 { "fcmovu", { ST, STi } },
5723 { "(bad)", { XX } },
252b5132 5724 { FGRPda_5 },
ce518a5f
L		 5725 { "(bad)", { XX } },
5726 { "(bad)", { XX } },
252b5132
RH		 5727 },
5728 /* db */
5729 {
ce518a5f
L		 5730 { "fcmovnb",{ ST, STi } },
5731 { "fcmovne",{ ST, STi } },
5732 { "fcmovnbe",{ ST, STi } },
5733 { "fcmovnu",{ ST, STi } },
252b5132 5734 { FGRPdb_4 },
ce518a5f
L		 5735 { "fucomi", { ST, STi } },
5736 { "fcomi", { ST, STi } },
5737 { "(bad)", { XX } },
252b5132
RH		 5738 },
5739 /* dc */
5740 {
ce518a5f
L		 5741 { "fadd", { STi, ST } },
5742 { "fmul", { STi, ST } },
5743 { "(bad)", { XX } },
5744 { "(bad)", { XX } },
0b1cf022 5745#if SYSV386_COMPAT
ce518a5f
L		 5746 { "fsub", { STi, ST } },
5747 { "fsubr", { STi, ST } },
5748 { "fdiv", { STi, ST } },
5749 { "fdivr", { STi, ST } },
252b5132 5750#else
ce518a5f
L		 5751 { "fsubr", { STi, ST } },
5752 { "fsub", { STi, ST } },
5753 { "fdivr", { STi, ST } },
5754 { "fdiv", { STi, ST } },
252b5132
RH		 5755#endif
5756 },
5757 /* dd */
5758 {
ce518a5f
L		 5759 { "ffree", { STi } },
5760 { "(bad)", { XX } },
5761 { "fst", { STi } },
5762 { "fstp", { STi } },
5763 { "fucom", { STi } },
5764 { "fucomp", { STi } },
5765 { "(bad)", { XX } },
5766 { "(bad)", { XX } },
252b5132
RH		 5767 },
5768 /* de */
5769 {
ce518a5f
L		 5770 { "faddp", { STi, ST } },
5771 { "fmulp", { STi, ST } },
5772 { "(bad)", { XX } },
252b5132 5773 { FGRPde_3 },
0b1cf022 5774#if SYSV386_COMPAT
ce518a5f
L		 5775 { "fsubp", { STi, ST } },
5776 { "fsubrp", { STi, ST } },
5777 { "fdivp", { STi, ST } },
5778 { "fdivrp", { STi, ST } },
252b5132 5779#else
ce518a5f
L		 5780 { "fsubrp", { STi, ST } },
5781 { "fsubp", { STi, ST } },
5782 { "fdivrp", { STi, ST } },
5783 { "fdivp", { STi, ST } },
252b5132
RH		 5784#endif
5785 },
5786 /* df */
5787 {
ce518a5f
L		 5788 { "ffreep", { STi } },
5789 { "(bad)", { XX } },
5790 { "(bad)", { XX } },
5791 { "(bad)", { XX } },
252b5132 5792 { FGRPdf_4 },
ce518a5f
L		 5793 { "fucomip", { ST, STi } },
5794 { "fcomip", { ST, STi } },
5795 { "(bad)", { XX } },
252b5132
RH		 5796 },
5797};
5798
252b5132
RH		 5799static char *fgrps[][8] = {
5800 /* d9_2 0 */
5801 {
5802 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5803 },
5804
5805 /* d9_4 1 */
5806 {
5807 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
5808 },
5809
5810 /* d9_5 2 */
5811 {
5812 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
5813 },
5814
5815 /* d9_6 3 */
5816 {
5817 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
5818 },
5819
5820 /* d9_7 4 */
5821 {
5822 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
5823 },
5824
5825 /* da_5 5 */
5826 {
5827 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5828 },
5829
5830 /* db_4 6 */
5831 {
5832 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
5833 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
5834 },
5835
5836 /* de_3 7 */
5837 {
5838 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5839 },
5840
5841 /* df_4 8 */
5842 {
5843 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
5844 },
5845};
5846
b844680a
L		 5847static void
5848OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
5849 int sizeflag ATTRIBUTE_UNUSED)
5850{
5851 /* Skip mod/rm byte. */
5852 MODRM_CHECK;
5853 codep++;
5854}
5855
252b5132 5856static void
26ca5450 5857dofloat (int sizeflag)
252b5132 5858{
2da11e11 5859 const struct dis386 *dp;
252b5132
RH		 5860 unsigned char floatop;
5861
5862 floatop = codep[-1];
5863
7967e09e 5864 if (modrm.mod != 3)
252b5132 5865 {
7967e09e 5866 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
1d9f512f
AM		 5867
5868 putop (float_mem[fp_indx], sizeflag);
ce518a5f 5869 obufp = op_out[0];
6e50d963 5870 op_ad = 2;
1d9f512f 5871 OP_E (float_mem_mode[fp_indx], sizeflag);
252b5132
RH		 5872 return;
5873 }
6608db57 5874 /* Skip mod/rm byte. */
4bba6815 5875 MODRM_CHECK;
252b5132
RH		 5876 codep++;
5877
7967e09e 5878 dp = &float_reg[floatop - 0xd8][modrm.reg];
252b5132
RH		 5879 if (dp->name == NULL)
5880 {
7967e09e 5881 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
252b5132 5882
6608db57 5883 /* Instruction fnstsw is only one with strange arg. */
252b5132 5884 if (floatop == 0xdf && codep[-1] == 0xe0)
ce518a5f 5885 strcpy (op_out[0], names16[0]);
252b5132
RH		 5886 }
5887 else
5888 {
5889 putop (dp->name, sizeflag);
5890
ce518a5f 5891 obufp = op_out[0];
6e50d963 5892 op_ad = 2;
ce518a5f
L		 5893 if (dp->op[0].rtn)
5894 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
6e50d963 5895
ce518a5f 5896 obufp = op_out[1];
6e50d963 5897 op_ad = 1;
ce518a5f
L		 5898 if (dp->op[1].rtn)
5899 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
252b5132
RH		 5900 }
5901}
5902
252b5132 5903static void
26ca5450 5904OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 5905{
422673a9 5906 oappend ("%st" + intel_syntax);
252b5132
RH		 5907}
5908
252b5132 5909static void
26ca5450 5910OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 5911{
7967e09e 5912 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
d708bcba 5913 oappend (scratchbuf + intel_syntax);
252b5132
RH		 5914}
5915
6608db57 5916/* Capital letters in template are macros. */
6439fc28 5917static int
26ca5450 5918putop (const char *template, int sizeflag)
252b5132 5919{
2da11e11 5920 const char *p;
9306ca4a 5921 int alt = 0;
252b5132
RH		 5922
5923 for (p = template; *p; p++)
5924 {
5925 switch (*p)
5926 {
5927 default:
5928 *obufp++ = *p;
5929 break;
6439fc28
AM		 5930 case '{':
5931 alt = 0;
5932 if (intel_syntax)
6439fc28
AM		 5933 {
5934 while (*++p != '|')
7c52e0e8
L		 5935 if (*p == '}' || *p == '\0')
5936 abort ();
6439fc28 5937 }
9306ca4a
JB		 5938 /* Fall through. */
5939 case 'I':
5940 alt = 1;
5941 continue;
6439fc28
AM		 5942 case '|':
5943 while (*++p != '}')
5944 {
5945 if (*p == '\0')
5946 abort ();
5947 }
5948 break;
5949 case '}':
5950 break;
252b5132 5951 case 'A':
db6eb5be
AM		 5952 if (intel_syntax)
5953 break;
7967e09e 5954 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
252b5132
RH		 5955 *obufp++ = 'b';
5956 break;
5957 case 'B':
db6eb5be
AM		 5958 if (intel_syntax)
5959 break;
252b5132
RH		 5960 if (sizeflag & SUFFIX_ALWAYS)
5961 *obufp++ = 'b';
252b5132 5962 break;
9306ca4a
JB		 5963 case 'C':
5964 if (intel_syntax && !alt)
5965 break;
5966 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
5967 {
5968 if (sizeflag & DFLAG)
5969 *obufp++ = intel_syntax ? 'd' : 'l';
5970 else
5971 *obufp++ = intel_syntax ? 'w' : 's';
5972 used_prefixes |= (prefixes & PREFIX_DATA);
5973 }
5974 break;
ed7841b3
JB		 5975 case 'D':
5976 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
5977 break;
161a04f6 5978 USED_REX (REX_W);
7967e09e 5979 if (modrm.mod == 3)
ed7841b3 5980 {
161a04f6 5981 if (rex & REX_W)
ed7841b3
JB		 5982 *obufp++ = 'q';
5983 else if (sizeflag & DFLAG)
5984 *obufp++ = intel_syntax ? 'd' : 'l';
5985 else
5986 *obufp++ = 'w';
5987 used_prefixes |= (prefixes & PREFIX_DATA);
5988 }
5989 else
5990 *obufp++ = 'w';
5991 break;
252b5132 5992 case 'E': /* For jcxz/jecxz */
cb712a9e 5993 if (address_mode == mode_64bit)
c1a64871
JH		 5994 {
5995 if (sizeflag & AFLAG)
5996 *obufp++ = 'r';
5997 else
5998 *obufp++ = 'e';
5999 }
6000 else
6001 if (sizeflag & AFLAG)
6002 *obufp++ = 'e';
3ffd33cf
AM		 6003 used_prefixes |= (prefixes & PREFIX_ADDR);
6004 break;
6005 case 'F':
db6eb5be
AM		 6006 if (intel_syntax)
6007 break;
e396998b 6008 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
3ffd33cf
AM		 6009 {
6010 if (sizeflag & AFLAG)
cb712a9e 6011 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
3ffd33cf 6012 else
cb712a9e 6013 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
3ffd33cf
AM		 6014 used_prefixes |= (prefixes & PREFIX_ADDR);
6015 }
252b5132 6016 break;
52fd6d94
JB		 6017 case 'G':
6018 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
6019 break;
161a04f6 6020 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 6021 *obufp++ = 'l';
6022 else
6023 *obufp++ = 'w';
161a04f6 6024 if (!(rex & REX_W))
52fd6d94
JB		 6025 used_prefixes |= (prefixes & PREFIX_DATA);
6026 break;
5dd0794d 6027 case 'H':
db6eb5be
AM		 6028 if (intel_syntax)
6029 break;
5dd0794d
AM		 6030 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
6031 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
6032 {
6033 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
6034 *obufp++ = ',';
6035 *obufp++ = 'p';
6036 if (prefixes & PREFIX_DS)
6037 *obufp++ = 't';
6038 else
6039 *obufp++ = 'n';
6040 }
6041 break;
9306ca4a
JB		 6042 case 'J':
6043 if (intel_syntax)
6044 break;
6045 *obufp++ = 'l';
6046 break;
42903f7f
L		 6047 case 'K':
6048 USED_REX (REX_W);
6049 if (rex & REX_W)
6050 *obufp++ = 'q';
6051 else
6052 *obufp++ = 'd';
6053 break;
6dd5059a
L		 6054 case 'Z':
6055 if (intel_syntax)
6056 break;
6057 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
6058 {
6059 *obufp++ = 'q';
6060 break;
6061 }
6062 /* Fall through. */
252b5132 6063 case 'L':
db6eb5be
AM		 6064 if (intel_syntax)
6065 break;
252b5132
RH		 6066 if (sizeflag & SUFFIX_ALWAYS)
6067 *obufp++ = 'l';
252b5132
RH		 6068 break;
6069 case 'N':
6070 if ((prefixes & PREFIX_FWAIT) == 0)
6071 *obufp++ = 'n';
7d421014
ILT		 6072 else
6073 used_prefixes |= PREFIX_FWAIT;
252b5132 6074 break;
52b15da3 6075 case 'O':
161a04f6
L		 6076 USED_REX (REX_W);
6077 if (rex & REX_W)
6439fc28 6078 *obufp++ = 'o';
a35ca55a
JB		 6079 else if (intel_syntax && (sizeflag & DFLAG))
6080 *obufp++ = 'q';
52b15da3
JH		 6081 else
6082 *obufp++ = 'd';
161a04f6 6083 if (!(rex & REX_W))
a35ca55a 6084 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 6085 break;
6439fc28 6086 case 'T':
db6eb5be
AM		 6087 if (intel_syntax)
6088 break;
cb712a9e 6089 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 6090 {
6091 *obufp++ = 'q';
6092 break;
6093 }
6608db57 6094 /* Fall through. */
252b5132 6095 case 'P':
db6eb5be
AM		 6096 if (intel_syntax)
6097 break;
252b5132 6098 if ((prefixes & PREFIX_DATA)
161a04f6 6099 || (rex & REX_W)
e396998b 6100 || (sizeflag & SUFFIX_ALWAYS))
252b5132 6101 {
161a04f6
L		 6102 USED_REX (REX_W);
6103 if (rex & REX_W)
52b15da3 6104 *obufp++ = 'q';
c2419411 6105 else
52b15da3
JH		 6106 {
6107 if (sizeflag & DFLAG)
6108 *obufp++ = 'l';
6109 else
6110 *obufp++ = 'w';
52b15da3 6111 }
1a114b12 6112 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 6113 }
6114 break;
6439fc28 6115 case 'U':
db6eb5be
AM		 6116 if (intel_syntax)
6117 break;
cb712a9e 6118 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28 6119 {
7967e09e 6120 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
1a114b12 6121 *obufp++ = 'q';
6439fc28
AM		 6122 break;
6123 }
6608db57 6124 /* Fall through. */
252b5132 6125 case 'Q':
9306ca4a 6126 if (intel_syntax && !alt)
db6eb5be 6127 break;
161a04f6 6128 USED_REX (REX_W);
7967e09e 6129 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
252b5132 6130 {
161a04f6 6131 if (rex & REX_W)
52b15da3 6132 *obufp++ = 'q';
252b5132 6133 else
52b15da3
JH		 6134 {
6135 if (sizeflag & DFLAG)
9306ca4a 6136 *obufp++ = intel_syntax ? 'd' : 'l';
52b15da3
JH		 6137 else
6138 *obufp++ = 'w';
52b15da3 6139 }
1a114b12 6140 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 6141 }
6142 break;
6143 case 'R':
161a04f6
L		 6144 USED_REX (REX_W);
6145 if (rex & REX_W)
a35ca55a
JB		 6146 *obufp++ = 'q';
6147 else if (sizeflag & DFLAG)
c608c12e 6148 {
a35ca55a 6149 if (intel_syntax)
c608c12e 6150 *obufp++ = 'd';
c608c12e 6151 else
a35ca55a 6152 *obufp++ = 'l';
c608c12e 6153 }
252b5132 6154 else
a35ca55a
JB		 6155 *obufp++ = 'w';
6156 if (intel_syntax && !p[1]
161a04f6 6157 && ((rex & REX_W) || (sizeflag & DFLAG)))
a35ca55a 6158 *obufp++ = 'e';
161a04f6 6159 if (!(rex & REX_W))
52b15da3 6160 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6161 break;
1a114b12
JB		 6162 case 'V':
6163 if (intel_syntax)
6164 break;
cb712a9e 6165 if (address_mode == mode_64bit && (sizeflag & DFLAG))
1a114b12
JB		 6166 {
6167 if (sizeflag & SUFFIX_ALWAYS)
6168 *obufp++ = 'q';
6169 break;
6170 }
6171 /* Fall through. */
252b5132 6172 case 'S':
db6eb5be
AM		 6173 if (intel_syntax)
6174 break;
252b5132
RH		 6175 if (sizeflag & SUFFIX_ALWAYS)
6176 {
161a04f6 6177 if (rex & REX_W)
52b15da3 6178 *obufp++ = 'q';
252b5132 6179 else
52b15da3
JH		 6180 {
6181 if (sizeflag & DFLAG)
6182 *obufp++ = 'l';
6183 else
6184 *obufp++ = 'w';
6185 used_prefixes |= (prefixes & PREFIX_DATA);
6186 }
252b5132 6187 }
252b5132 6188 break;
041bd2e0
JH		 6189 case 'X':
6190 if (prefixes & PREFIX_DATA)
6191 *obufp++ = 'd';
6192 else
6193 *obufp++ = 's';
db6eb5be 6194 used_prefixes |= (prefixes & PREFIX_DATA);
041bd2e0 6195 break;
76f227a5 6196 case 'Y':
8a72226a 6197 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
db6eb5be 6198 break;
161a04f6 6199 if (rex & REX_W)
76f227a5 6200 {
161a04f6 6201 USED_REX (REX_W);
76f227a5
JH		 6202 *obufp++ = 'q';
6203 }
6204 break;
52b15da3 6205 /* implicit operand size 'l' for i386 or 'q' for x86-64 */
252b5132 6206 case 'W':
252b5132 6207 /* operand size flag for cwtl, cbtw */
161a04f6
L		 6208 USED_REX (REX_W);
6209 if (rex & REX_W)
a35ca55a
JB		 6210 {
6211 if (intel_syntax)
6212 *obufp++ = 'd';
6213 else
6214 *obufp++ = 'l';
6215 }
52b15da3 6216 else if (sizeflag & DFLAG)
252b5132
RH		 6217 *obufp++ = 'w';
6218 else
6219 *obufp++ = 'b';
161a04f6 6220 if (!(rex & REX_W))
52b15da3 6221 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 6222 break;
6223 }
9306ca4a 6224 alt = 0;
252b5132
RH		 6225 }
6226 *obufp = 0;
6439fc28 6227 return 0;
252b5132
RH		 6228}
6229
6230static void
26ca5450 6231oappend (const char *s)
252b5132
RH		 6232{
6233 strcpy (obufp, s);
6234 obufp += strlen (s);
6235}
6236
6237static void
26ca5450 6238append_seg (void)
252b5132
RH		 6239{
6240 if (prefixes & PREFIX_CS)
7d421014 6241 {
7d421014 6242 used_prefixes |= PREFIX_CS;
d708bcba 6243 oappend ("%cs:" + intel_syntax);
7d421014 6244 }
252b5132 6245 if (prefixes & PREFIX_DS)
7d421014 6246 {
7d421014 6247 used_prefixes |= PREFIX_DS;
d708bcba 6248 oappend ("%ds:" + intel_syntax);
7d421014 6249 }
252b5132 6250 if (prefixes & PREFIX_SS)
7d421014 6251 {
7d421014 6252 used_prefixes |= PREFIX_SS;
d708bcba 6253 oappend ("%ss:" + intel_syntax);
7d421014 6254 }
252b5132 6255 if (prefixes & PREFIX_ES)
7d421014 6256 {
7d421014 6257 used_prefixes |= PREFIX_ES;
d708bcba 6258 oappend ("%es:" + intel_syntax);
7d421014 6259 }
252b5132 6260 if (prefixes & PREFIX_FS)
7d421014 6261 {
7d421014 6262 used_prefixes |= PREFIX_FS;
d708bcba 6263 oappend ("%fs:" + intel_syntax);
7d421014 6264 }
252b5132 6265 if (prefixes & PREFIX_GS)
7d421014 6266 {
7d421014 6267 used_prefixes |= PREFIX_GS;
d708bcba 6268 oappend ("%gs:" + intel_syntax);
7d421014 6269 }
252b5132
RH		 6270}
6271
6272static void
26ca5450 6273OP_indirE (int bytemode, int sizeflag)
252b5132
RH		 6274{
6275 if (!intel_syntax)
6276 oappend ("*");
6277 OP_E (bytemode, sizeflag);
6278}
6279
52b15da3 6280static void
26ca5450 6281print_operand_value (char *buf, int hex, bfd_vma disp)
52b15da3 6282{
cb712a9e 6283 if (address_mode == mode_64bit)
52b15da3
JH		 6284 {
6285 if (hex)
6286 {
6287 char tmp[30];
6288 int i;
6289 buf[0] = '0';
6290 buf[1] = 'x';
6291 sprintf_vma (tmp, disp);
6608db57 6292 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
52b15da3
JH		 6293 strcpy (buf + 2, tmp + i);
6294 }
6295 else
6296 {
6297 bfd_signed_vma v = disp;
6298 char tmp[30];
6299 int i;
6300 if (v < 0)
6301 {
6302 *(buf++) = '-';
6303 v = -disp;
6608db57 6304 /* Check for possible overflow on 0x8000000000000000. */
52b15da3
JH		 6305 if (v < 0)
6306 {
6307 strcpy (buf, "9223372036854775808");
6308 return;
6309 }
6310 }
6311 if (!v)
6312 {
6313 strcpy (buf, "0");
6314 return;
6315 }
6316
6317 i = 0;
6318 tmp[29] = 0;
6319 while (v)
6320 {
6608db57 6321 tmp[28 - i] = (v % 10) + '0';
52b15da3
JH		 6322 v /= 10;
6323 i++;
6324 }
6325 strcpy (buf, tmp + 29 - i);
6326 }
6327 }
6328 else
6329 {
6330 if (hex)
6331 sprintf (buf, "0x%x", (unsigned int) disp);
6332 else
6333 sprintf (buf, "%d", (int) disp);
6334 }
6335}
6336
5d669648
L		 6337/* Put DISP in BUF as signed hex number. */
6338
6339static void
6340print_displacement (char *buf, bfd_vma disp)
6341{
6342 bfd_signed_vma val = disp;
6343 char tmp[30];
6344 int i, j = 0;
6345
6346 if (val < 0)
6347 {
6348 buf[j++] = '-';
6349 val = -disp;
6350
6351 /* Check for possible overflow. */
6352 if (val < 0)
6353 {
6354 switch (address_mode)
6355 {
6356 case mode_64bit:
6357 strcpy (buf + j, "0x8000000000000000");
6358 break;
6359 case mode_32bit:
6360 strcpy (buf + j, "0x80000000");
6361 break;
6362 case mode_16bit:
6363 strcpy (buf + j, "0x8000");
6364 break;
6365 }
6366 return;
6367 }
6368 }
6369
6370 buf[j++] = '0';
6371 buf[j++] = 'x';
6372
6373 sprintf_vma (tmp, val);
6374 for (i = 0; tmp[i] == '0'; i++)
6375 continue;
6376 if (tmp[i] == '\0')
6377 i--;
6378 strcpy (buf + j, tmp + i);
6379}
6380
3f31e633
JB		 6381static void
6382intel_operand_size (int bytemode, int sizeflag)
6383{
6384 switch (bytemode)
6385 {
6386 case b_mode:
42903f7f 6387 case dqb_mode:
3f31e633
JB		 6388 oappend ("BYTE PTR ");
6389 break;
6390 case w_mode:
6391 case dqw_mode:
6392 oappend ("WORD PTR ");
6393 break;
1a114b12 6394 case stack_v_mode:
cb712a9e 6395 if (address_mode == mode_64bit && (sizeflag & DFLAG))
3f31e633
JB		 6396 {
6397 oappend ("QWORD PTR ");
6398 used_prefixes |= (prefixes & PREFIX_DATA);
6399 break;
6400 }
6401 /* FALLTHRU */
6402 case v_mode:
6403 case dq_mode:
161a04f6
L		 6404 USED_REX (REX_W);
6405 if (rex & REX_W)
3f31e633
JB		 6406 oappend ("QWORD PTR ");
6407 else if ((sizeflag & DFLAG) || bytemode == dq_mode)
6408 oappend ("DWORD PTR ");
6409 else
6410 oappend ("WORD PTR ");
6411 used_prefixes |= (prefixes & PREFIX_DATA);
6412 break;
52fd6d94 6413 case z_mode:
161a04f6 6414 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 6415 *obufp++ = 'D';
6416 oappend ("WORD PTR ");
161a04f6 6417 if (!(rex & REX_W))
52fd6d94
JB		 6418 used_prefixes |= (prefixes & PREFIX_DATA);
6419 break;
3f31e633 6420 case d_mode:
42903f7f 6421 case dqd_mode:
3f31e633
JB		 6422 oappend ("DWORD PTR ");
6423 break;
6424 case q_mode:
6425 oappend ("QWORD PTR ");
6426 break;
6427 case m_mode:
cb712a9e 6428 if (address_mode == mode_64bit)
3f31e633
JB		 6429 oappend ("QWORD PTR ");
6430 else
6431 oappend ("DWORD PTR ");
6432 break;
6433 case f_mode:
6434 if (sizeflag & DFLAG)
6435 oappend ("FWORD PTR ");
6436 else
6437 oappend ("DWORD PTR ");
6438 used_prefixes |= (prefixes & PREFIX_DATA);
6439 break;
6440 case t_mode:
6441 oappend ("TBYTE PTR ");
6442 break;
6443 case x_mode:
6444 oappend ("XMMWORD PTR ");
6445 break;
fb9c77c7
L		 6446 case o_mode:
6447 oappend ("OWORD PTR ");
6448 break;
3f31e633
JB		 6449 default:
6450 break;
6451 }
6452}
6453
252b5132 6454static void
85f10a01 6455OP_E_extended (int bytemode, int sizeflag, int has_drex)
252b5132 6456{
52b15da3
JH		 6457 bfd_vma disp;
6458 int add = 0;
6459 int riprel = 0;
161a04f6
L		 6460 USED_REX (REX_B);
6461 if (rex & REX_B)
52b15da3 6462 add += 8;
252b5132 6463
6608db57 6464 /* Skip mod/rm byte. */
4bba6815 6465 MODRM_CHECK;
252b5132
RH		 6466 codep++;
6467
7967e09e 6468 if (modrm.mod == 3)
252b5132
RH		 6469 {
6470 switch (bytemode)
6471 {
6472 case b_mode:
52b15da3
JH		 6473 USED_REX (0);
6474 if (rex)
7967e09e 6475 oappend (names8rex[modrm.rm + add]);
52b15da3 6476 else
7967e09e 6477 oappend (names8[modrm.rm + add]);
252b5132
RH		 6478 break;
6479 case w_mode:
7967e09e 6480 oappend (names16[modrm.rm + add]);
252b5132 6481 break;
2da11e11 6482 case d_mode:
7967e09e 6483 oappend (names32[modrm.rm + add]);
52b15da3
JH		 6484 break;
6485 case q_mode:
7967e09e 6486 oappend (names64[modrm.rm + add]);
52b15da3
JH		 6487 break;
6488 case m_mode:
cb712a9e 6489 if (address_mode == mode_64bit)
7967e09e 6490 oappend (names64[modrm.rm + add]);
52b15da3 6491 else
7967e09e 6492 oappend (names32[modrm.rm + add]);
2da11e11 6493 break;
1a114b12 6494 case stack_v_mode:
cb712a9e 6495 if (address_mode == mode_64bit && (sizeflag & DFLAG))
003519a7 6496 {
7967e09e 6497 oappend (names64[modrm.rm + add]);
003519a7 6498 used_prefixes |= (prefixes & PREFIX_DATA);
1a114b12 6499 break;
003519a7 6500 }
1a114b12
JB		 6501 bytemode = v_mode;
6502 /* FALLTHRU */
252b5132 6503 case v_mode:
db6eb5be 6504 case dq_mode:
42903f7f
L		 6505 case dqb_mode:
6506 case dqd_mode:
9306ca4a 6507 case dqw_mode:
161a04f6
L		 6508 USED_REX (REX_W);
6509 if (rex & REX_W)
7967e09e 6510 oappend (names64[modrm.rm + add]);
9306ca4a 6511 else if ((sizeflag & DFLAG) || bytemode != v_mode)
7967e09e 6512 oappend (names32[modrm.rm + add]);
252b5132 6513 else
7967e09e 6514 oappend (names16[modrm.rm + add]);
7d421014 6515 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6516 break;
2da11e11 6517 case 0:
c608c12e 6518 break;
252b5132 6519 default:
c608c12e 6520 oappend (INTERNAL_DISASSEMBLER_ERROR);
252b5132
RH		 6521 break;
6522 }
6523 return;
6524 }
6525
6526 disp = 0;
3f31e633
JB		 6527 if (intel_syntax)
6528 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 6529 append_seg ();
6530
5d669648 6531 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132 6532 {
5d669648
L		 6533 /* 32/64 bit address mode */
6534 int havedisp;
252b5132
RH		 6535 int havesib;
6536 int havebase;
0f7da397 6537 int haveindex;
20afcfb7 6538 int needindex;
252b5132
RH		 6539 int base;
6540 int index = 0;
6541 int scale = 0;
6542
6543 havesib = 0;
6544 havebase = 1;
0f7da397 6545 haveindex = 0;
7967e09e 6546 base = modrm.rm;
252b5132
RH		 6547
6548 if (base == 4)
6549 {
6550 havesib = 1;
6551 FETCH_DATA (the_info, codep + 1);
252b5132 6552 index = (*codep >> 3) & 7;
db51cc60 6553 scale = (*codep >> 6) & 3;
252b5132 6554 base = *codep & 7;
161a04f6
L		 6555 USED_REX (REX_X);
6556 if (rex & REX_X)
52b15da3 6557 index += 8;
0f7da397 6558 haveindex = index != 4;
252b5132
RH		 6559 codep++;
6560 }
2888cb7a 6561 base += add;
252b5132 6562
85f10a01
MM		 6563 /* If we have a DREX byte, skip it now
6564 (it has already been handled) */
6565 if (has_drex)
6566 {
6567 FETCH_DATA (the_info, codep + 1);
6568 codep++;
6569 }
6570
7967e09e 6571 switch (modrm.mod)
252b5132
RH		 6572 {
6573 case 0:
52b15da3 6574 if ((base & 7) == 5)
252b5132
RH		 6575 {
6576 havebase = 0;
cb712a9e 6577 if (address_mode == mode_64bit && !havesib)
52b15da3
JH		 6578 riprel = 1;
6579 disp = get32s ();
252b5132
RH		 6580 }
6581 break;
6582 case 1:
6583 FETCH_DATA (the_info, codep + 1);
6584 disp = *codep++;
6585 if ((disp & 0x80) != 0)
6586 disp -= 0x100;
6587 break;
6588 case 2:
52b15da3 6589 disp = get32s ();
252b5132
RH		 6590 break;
6591 }
6592
20afcfb7
L		 6593 /* In 32bit mode, we need index register to tell [offset] from
6594 [eiz*1 + offset]. */
6595 needindex = (havesib
6596 && !havebase
6597 && !haveindex
6598 && address_mode == mode_32bit);
6599 havedisp = (havebase
6600 || needindex
6601 || (havesib && (haveindex || scale != 0)));
5d669648 6602
252b5132 6603 if (!intel_syntax)
7967e09e 6604 if (modrm.mod != 0 || (base & 7) == 5)
db6eb5be 6605 {
5d669648
L		 6606 if (havedisp || riprel)
6607 print_displacement (scratchbuf, disp);
6608 else
6609 print_operand_value (scratchbuf, 1, disp);
db6eb5be 6610 oappend (scratchbuf);
52b15da3
JH		 6611 if (riprel)
6612 {
6613 set_op (disp, 1);
87767711 6614 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
52b15da3 6615 }
db6eb5be 6616 }
2da11e11 6617
87767711
JB		 6618 if (havebase || haveindex || riprel)
6619 used_prefixes |= PREFIX_ADDR;
6620
5d669648 6621 if (havedisp || (intel_syntax && riprel))
252b5132 6622 {
252b5132 6623 *obufp++ = open_char;
52b15da3 6624 if (intel_syntax && riprel)
185b1163
L		 6625 {
6626 set_op (disp, 1);
87767711 6627 oappend (sizeflag & AFLAG ? "rip" : "eip");
185b1163 6628 }
db6eb5be 6629 *obufp = '\0';
252b5132 6630 if (havebase)
cb712a9e 6631 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
c1a64871 6632 ? names64[base] : names32[base]);
252b5132
RH		 6633 if (havesib)
6634 {
db51cc60
L		 6635 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
6636 print index to tell base + index from base. */
6637 if (scale != 0
20afcfb7 6638 || needindex
db51cc60
L		 6639 || haveindex
6640 || (havebase && base != ESP_REG_NUM))
252b5132 6641 {
9306ca4a 6642 if (!intel_syntax || havebase)
db6eb5be 6643 {
9306ca4a
JB		 6644 *obufp++ = separator_char;
6645 *obufp = '\0';
db6eb5be 6646 }
db51cc60
L		 6647 if (haveindex)
6648 oappend (address_mode == mode_64bit
6649 && (sizeflag & AFLAG)
6650 ? names64[index] : names32[index]);
6651 else
6652 oappend (address_mode == mode_64bit
6653 && (sizeflag & AFLAG)
6654 ? index64 : index32);
6655
db6eb5be
AM		 6656 *obufp++ = scale_char;
6657 *obufp = '\0';
6658 sprintf (scratchbuf, "%d", 1 << scale);
6659 oappend (scratchbuf);
6660 }
252b5132 6661 }
185b1163
L		 6662 if (intel_syntax
6663 && (disp || modrm.mod != 0 || (base & 7) == 5))
3d456fa1 6664 {
db51cc60 6665 if (!havedisp || (bfd_signed_vma) disp >= 0)
3d456fa1
JB		 6666 {
6667 *obufp++ = '+';
6668 *obufp = '\0';
6669 }
7967e09e 6670 else if (modrm.mod != 1)
3d456fa1
JB		 6671 {
6672 *obufp++ = '-';
6673 *obufp = '\0';
6674 disp = - (bfd_signed_vma) disp;
6675 }
6676
db51cc60
L		 6677 if (havedisp)
6678 print_displacement (scratchbuf, disp);
6679 else
6680 print_operand_value (scratchbuf, 1, disp);
3d456fa1
JB		 6681 oappend (scratchbuf);
6682 }
252b5132
RH		 6683
6684 *obufp++ = close_char;
db6eb5be 6685 *obufp = '\0';
252b5132
RH		 6686 }
6687 else if (intel_syntax)
db6eb5be 6688 {
7967e09e 6689 if (modrm.mod != 0 || (base & 7) == 5)
db6eb5be 6690 {
252b5132
RH		 6691 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
6692 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
6693 ;
6694 else
6695 {
d708bcba 6696 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 6697 oappend (":");
6698 }
52b15da3 6699 print_operand_value (scratchbuf, 1, disp);
db6eb5be
AM		 6700 oappend (scratchbuf);
6701 }
6702 }
252b5132
RH		 6703 }
6704 else
6705 { /* 16 bit address mode */
7967e09e 6706 switch (modrm.mod)
252b5132
RH		 6707 {
6708 case 0:
7967e09e 6709 if (modrm.rm == 6)
252b5132
RH		 6710 {
6711 disp = get16 ();
6712 if ((disp & 0x8000) != 0)
6713 disp -= 0x10000;
6714 }
6715 break;
6716 case 1:
6717 FETCH_DATA (the_info, codep + 1);
6718 disp = *codep++;
6719 if ((disp & 0x80) != 0)
6720 disp -= 0x100;
6721 break;
6722 case 2:
6723 disp = get16 ();
6724 if ((disp & 0x8000) != 0)
6725 disp -= 0x10000;
6726 break;
6727 }
6728
6729 if (!intel_syntax)
7967e09e 6730 if (modrm.mod != 0 || modrm.rm == 6)
db6eb5be 6731 {
5d669648 6732 print_displacement (scratchbuf, disp);
db6eb5be
AM		 6733 oappend (scratchbuf);
6734 }
252b5132 6735
7967e09e 6736 if (modrm.mod != 0 || modrm.rm != 6)
252b5132
RH		 6737 {
6738 *obufp++ = open_char;
db6eb5be 6739 *obufp = '\0';
7967e09e 6740 oappend (index16[modrm.rm]);
5d669648
L		 6741 if (intel_syntax
6742 && (disp || modrm.mod != 0 || modrm.rm == 6))
3d456fa1 6743 {
5d669648 6744 if ((bfd_signed_vma) disp >= 0)
3d456fa1
JB		 6745 {
6746 *obufp++ = '+';
6747 *obufp = '\0';
6748 }
7967e09e 6749 else if (modrm.mod != 1)
3d456fa1
JB		 6750 {
6751 *obufp++ = '-';
6752 *obufp = '\0';
6753 disp = - (bfd_signed_vma) disp;
6754 }
6755
5d669648 6756 print_displacement (scratchbuf, disp);
3d456fa1
JB		 6757 oappend (scratchbuf);
6758 }
6759
db6eb5be
AM		 6760 *obufp++ = close_char;
6761 *obufp = '\0';
252b5132 6762 }
3d456fa1
JB		 6763 else if (intel_syntax)
6764 {
6765 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
6766 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
6767 ;
6768 else
6769 {
6770 oappend (names_seg[ds_reg - es_reg]);
6771 oappend (":");
6772 }
6773 print_operand_value (scratchbuf, 1, disp & 0xffff);
6774 oappend (scratchbuf);
6775 }
252b5132
RH		 6776 }
6777}
6778
85f10a01
MM		 6779static void
6780OP_E (int bytemode, int sizeflag)
6781{
6782 OP_E_extended (bytemode, sizeflag, 0);
6783}
6784
6785
252b5132 6786static void
26ca5450 6787OP_G (int bytemode, int sizeflag)
252b5132 6788{
52b15da3 6789 int add = 0;
161a04f6
L		 6790 USED_REX (REX_R);
6791 if (rex & REX_R)
52b15da3 6792 add += 8;
252b5132
RH		 6793 switch (bytemode)
6794 {
6795 case b_mode:
52b15da3
JH		 6796 USED_REX (0);
6797 if (rex)
7967e09e 6798 oappend (names8rex[modrm.reg + add]);
52b15da3 6799 else
7967e09e 6800 oappend (names8[modrm.reg + add]);
252b5132
RH		 6801 break;
6802 case w_mode:
7967e09e 6803 oappend (names16[modrm.reg + add]);
252b5132
RH		 6804 break;
6805 case d_mode:
7967e09e 6806 oappend (names32[modrm.reg + add]);
52b15da3
JH		 6807 break;
6808 case q_mode:
7967e09e 6809 oappend (names64[modrm.reg + add]);
252b5132
RH		 6810 break;
6811 case v_mode:
9306ca4a 6812 case dq_mode:
42903f7f
L		 6813 case dqb_mode:
6814 case dqd_mode:
9306ca4a 6815 case dqw_mode:
161a04f6
L		 6816 USED_REX (REX_W);
6817 if (rex & REX_W)
7967e09e 6818 oappend (names64[modrm.reg + add]);
9306ca4a 6819 else if ((sizeflag & DFLAG) || bytemode != v_mode)
7967e09e 6820 oappend (names32[modrm.reg + add]);
252b5132 6821 else
7967e09e 6822 oappend (names16[modrm.reg + add]);
7d421014 6823 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 6824 break;
90700ea2 6825 case m_mode:
cb712a9e 6826 if (address_mode == mode_64bit)
7967e09e 6827 oappend (names64[modrm.reg + add]);
90700ea2 6828 else
7967e09e 6829 oappend (names32[modrm.reg + add]);
90700ea2 6830 break;
252b5132
RH		 6831 default:
6832 oappend (INTERNAL_DISASSEMBLER_ERROR);
6833 break;
6834 }
6835}
6836
52b15da3 6837static bfd_vma
26ca5450 6838get64 (void)
52b15da3 6839{
5dd0794d 6840 bfd_vma x;
52b15da3 6841#ifdef BFD64
5dd0794d
AM		 6842 unsigned int a;
6843 unsigned int b;
6844
52b15da3
JH		 6845 FETCH_DATA (the_info, codep + 8);
6846 a = *codep++ & 0xff;
6847 a |= (*codep++ & 0xff) << 8;
6848 a |= (*codep++ & 0xff) << 16;
6849 a |= (*codep++ & 0xff) << 24;
5dd0794d 6850 b = *codep++ & 0xff;
52b15da3
JH		 6851 b |= (*codep++ & 0xff) << 8;
6852 b |= (*codep++ & 0xff) << 16;
6853 b |= (*codep++ & 0xff) << 24;
6854 x = a + ((bfd_vma) b << 32);
6855#else
6608db57 6856 abort ();
5dd0794d 6857 x = 0;
52b15da3
JH		 6858#endif
6859 return x;
6860}
6861
6862static bfd_signed_vma
26ca5450 6863get32 (void)
252b5132 6864{
52b15da3 6865 bfd_signed_vma x = 0;
252b5132
RH		 6866
6867 FETCH_DATA (the_info, codep + 4);
52b15da3
JH		 6868 x = *codep++ & (bfd_signed_vma) 0xff;
6869 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
6870 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
6871 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
6872 return x;
6873}
6874
6875static bfd_signed_vma
26ca5450 6876get32s (void)
52b15da3
JH		 6877{
6878 bfd_signed_vma x = 0;
6879
6880 FETCH_DATA (the_info, codep + 4);
6881 x = *codep++ & (bfd_signed_vma) 0xff;
6882 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
6883 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
6884 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
6885
6886 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
6887
252b5132
RH		 6888 return x;
6889}
6890
6891static int
26ca5450 6892get16 (void)
252b5132
RH		 6893{
6894 int x = 0;
6895
6896 FETCH_DATA (the_info, codep + 2);
6897 x = *codep++ & 0xff;
6898 x |= (*codep++ & 0xff) << 8;
6899 return x;
6900}
6901
6902static void
26ca5450 6903set_op (bfd_vma op, int riprel)
252b5132
RH		 6904{
6905 op_index[op_ad] = op_ad;
cb712a9e 6906 if (address_mode == mode_64bit)
7081ff04
AJ		 6907 {
6908 op_address[op_ad] = op;
6909 op_riprel[op_ad] = riprel;
6910 }
6911 else
6912 {
6913 /* Mask to get a 32-bit address. */
6914 op_address[op_ad] = op & 0xffffffff;
6915 op_riprel[op_ad] = riprel & 0xffffffff;
6916 }
252b5132
RH		 6917}
6918
6919static void
26ca5450 6920OP_REG (int code, int sizeflag)
252b5132 6921{
2da11e11 6922 const char *s;
9b60702d 6923 int add;
161a04f6
L		 6924 USED_REX (REX_B);
6925 if (rex & REX_B)
52b15da3 6926 add = 8;
9b60702d
L		 6927 else
6928 add = 0;
52b15da3
JH		 6929
6930 switch (code)
6931 {
52b15da3
JH		 6932 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
6933 case sp_reg: case bp_reg: case si_reg: case di_reg:
6934 s = names16[code - ax_reg + add];
6935 break;
6936 case es_reg: case ss_reg: case cs_reg:
6937 case ds_reg: case fs_reg: case gs_reg:
6938 s = names_seg[code - es_reg + add];
6939 break;
6940 case al_reg: case ah_reg: case cl_reg: case ch_reg:
6941 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
6942 USED_REX (0);
6943 if (rex)
6944 s = names8rex[code - al_reg + add];
6945 else
6946 s = names8[code - al_reg];
6947 break;
6439fc28
AM		 6948 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
6949 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
cb712a9e 6950 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 6951 {
6952 s = names64[code - rAX_reg + add];
6953 break;
6954 }
6955 code += eAX_reg - rAX_reg;
6608db57 6956 /* Fall through. */
52b15da3
JH		 6957 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
6958 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 6959 USED_REX (REX_W);
6960 if (rex & REX_W)
52b15da3
JH		 6961 s = names64[code - eAX_reg + add];
6962 else if (sizeflag & DFLAG)
6963 s = names32[code - eAX_reg + add];
6964 else
6965 s = names16[code - eAX_reg + add];
6966 used_prefixes |= (prefixes & PREFIX_DATA);
6967 break;
52b15da3
JH		 6968 default:
6969 s = INTERNAL_DISASSEMBLER_ERROR;
6970 break;
6971 }
6972 oappend (s);
6973}
6974
6975static void
26ca5450 6976OP_IMREG (int code, int sizeflag)
52b15da3
JH		 6977{
6978 const char *s;
252b5132
RH		 6979
6980 switch (code)
6981 {
6982 case indir_dx_reg:
d708bcba 6983 if (intel_syntax)
52fd6d94 6984 s = "dx";
d708bcba 6985 else
db6eb5be 6986 s = "(%dx)";
252b5132
RH		 6987 break;
6988 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
6989 case sp_reg: case bp_reg: case si_reg: case di_reg:
6990 s = names16[code - ax_reg];
6991 break;
6992 case es_reg: case ss_reg: case cs_reg:
6993 case ds_reg: case fs_reg: case gs_reg:
6994 s = names_seg[code - es_reg];
6995 break;
6996 case al_reg: case ah_reg: case cl_reg: case ch_reg:
6997 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
52b15da3
JH		 6998 USED_REX (0);
6999 if (rex)
7000 s = names8rex[code - al_reg];
7001 else
7002 s = names8[code - al_reg];
252b5132
RH		 7003 break;
7004 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
7005 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 7006 USED_REX (REX_W);
7007 if (rex & REX_W)
52b15da3
JH		 7008 s = names64[code - eAX_reg];
7009 else if (sizeflag & DFLAG)
252b5132
RH		 7010 s = names32[code - eAX_reg];
7011 else
7012 s = names16[code - eAX_reg];
7d421014 7013 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 7014 break;
52fd6d94 7015 case z_mode_ax_reg:
161a04f6 7016 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 7017 s = *names32;
7018 else
7019 s = *names16;
161a04f6 7020 if (!(rex & REX_W))
52fd6d94
JB		 7021 used_prefixes |= (prefixes & PREFIX_DATA);
7022 break;
252b5132
RH		 7023 default:
7024 s = INTERNAL_DISASSEMBLER_ERROR;
7025 break;
7026 }
7027 oappend (s);
7028}
7029
7030static void
26ca5450 7031OP_I (int bytemode, int sizeflag)
252b5132 7032{
52b15da3
JH		 7033 bfd_signed_vma op;
7034 bfd_signed_vma mask = -1;
252b5132
RH		 7035
7036 switch (bytemode)
7037 {
7038 case b_mode:
7039 FETCH_DATA (the_info, codep + 1);
52b15da3
JH		 7040 op = *codep++;
7041 mask = 0xff;
7042 break;
7043 case q_mode:
cb712a9e 7044 if (address_mode == mode_64bit)
6439fc28
AM		 7045 {
7046 op = get32s ();
7047 break;
7048 }
6608db57 7049 /* Fall through. */
252b5132 7050 case v_mode:
161a04f6
L		 7051 USED_REX (REX_W);
7052 if (rex & REX_W)
52b15da3
JH		 7053 op = get32s ();
7054 else if (sizeflag & DFLAG)
7055 {
7056 op = get32 ();
7057 mask = 0xffffffff;
7058 }
252b5132 7059 else
52b15da3
JH		 7060 {
7061 op = get16 ();
7062 mask = 0xfffff;
7063 }
7d421014 7064 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 7065 break;
7066 case w_mode:
52b15da3 7067 mask = 0xfffff;
252b5132
RH		 7068 op = get16 ();
7069 break;
9306ca4a
JB		 7070 case const_1_mode:
7071 if (intel_syntax)
7072 oappend ("1");
7073 return;
252b5132
RH		 7074 default:
7075 oappend (INTERNAL_DISASSEMBLER_ERROR);
7076 return;
7077 }
7078
52b15da3
JH		 7079 op &= mask;
7080 scratchbuf[0] = '$';
d708bcba
AM		 7081 print_operand_value (scratchbuf + 1, 1, op);
7082 oappend (scratchbuf + intel_syntax);
52b15da3
JH		 7083 scratchbuf[0] = '\0';
7084}
7085
7086static void
26ca5450 7087OP_I64 (int bytemode, int sizeflag)
52b15da3
JH		 7088{
7089 bfd_signed_vma op;
7090 bfd_signed_vma mask = -1;
7091
cb712a9e 7092 if (address_mode != mode_64bit)
6439fc28
AM		 7093 {
7094 OP_I (bytemode, sizeflag);
7095 return;
7096 }
7097
52b15da3
JH		 7098 switch (bytemode)
7099 {
7100 case b_mode:
7101 FETCH_DATA (the_info, codep + 1);
7102 op = *codep++;
7103 mask = 0xff;
7104 break;
7105 case v_mode:
161a04f6
L		 7106 USED_REX (REX_W);
7107 if (rex & REX_W)
52b15da3
JH		 7108 op = get64 ();
7109 else if (sizeflag & DFLAG)
7110 {
7111 op = get32 ();
7112 mask = 0xffffffff;
7113 }
7114 else
7115 {
7116 op = get16 ();
7117 mask = 0xfffff;
7118 }
7119 used_prefixes |= (prefixes & PREFIX_DATA);
7120 break;
7121 case w_mode:
7122 mask = 0xfffff;
7123 op = get16 ();
7124 break;
7125 default:
7126 oappend (INTERNAL_DISASSEMBLER_ERROR);
7127 return;
7128 }
7129
7130 op &= mask;
7131 scratchbuf[0] = '$';
d708bcba
AM		 7132 print_operand_value (scratchbuf + 1, 1, op);
7133 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7134 scratchbuf[0] = '\0';
7135}
7136
7137static void
26ca5450 7138OP_sI (int bytemode, int sizeflag)
252b5132 7139{
52b15da3
JH		 7140 bfd_signed_vma op;
7141 bfd_signed_vma mask = -1;
252b5132
RH		 7142
7143 switch (bytemode)
7144 {
7145 case b_mode:
7146 FETCH_DATA (the_info, codep + 1);
7147 op = *codep++;
7148 if ((op & 0x80) != 0)
7149 op -= 0x100;
52b15da3 7150 mask = 0xffffffff;
252b5132
RH		 7151 break;
7152 case v_mode:
161a04f6
L		 7153 USED_REX (REX_W);
7154 if (rex & REX_W)
52b15da3
JH		 7155 op = get32s ();
7156 else if (sizeflag & DFLAG)
7157 {
7158 op = get32s ();
7159 mask = 0xffffffff;
7160 }
252b5132
RH		 7161 else
7162 {
52b15da3 7163 mask = 0xffffffff;
6608db57 7164 op = get16 ();
252b5132
RH		 7165 if ((op & 0x8000) != 0)
7166 op -= 0x10000;
7167 }
7d421014 7168 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 7169 break;
7170 case w_mode:
7171 op = get16 ();
52b15da3 7172 mask = 0xffffffff;
252b5132
RH		 7173 if ((op & 0x8000) != 0)
7174 op -= 0x10000;
7175 break;
7176 default:
7177 oappend (INTERNAL_DISASSEMBLER_ERROR);
7178 return;
7179 }
52b15da3
JH		 7180
7181 scratchbuf[0] = '$';
7182 print_operand_value (scratchbuf + 1, 1, op);
d708bcba 7183 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7184}
7185
7186static void
26ca5450 7187OP_J (int bytemode, int sizeflag)
252b5132 7188{
52b15da3 7189 bfd_vma disp;
7081ff04 7190 bfd_vma mask = -1;
65ca155d 7191 bfd_vma segment = 0;
252b5132
RH		 7192
7193 switch (bytemode)
7194 {
7195 case b_mode:
7196 FETCH_DATA (the_info, codep + 1);
7197 disp = *codep++;
7198 if ((disp & 0x80) != 0)
7199 disp -= 0x100;
7200 break;
7201 case v_mode:
161a04f6 7202 if ((sizeflag & DFLAG) || (rex & REX_W))
52b15da3 7203 disp = get32s ();
252b5132
RH		 7204 else
7205 {
7206 disp = get16 ();
206717e8
L		 7207 if ((disp & 0x8000) != 0)
7208 disp -= 0x10000;
65ca155d
L		 7209 /* In 16bit mode, address is wrapped around at 64k within
7210 the same segment. Otherwise, a data16 prefix on a jump
7211 instruction means that the pc is masked to 16 bits after
7212 the displacement is added! */
7213 mask = 0xffff;
7214 if ((prefixes & PREFIX_DATA) == 0)
7215 segment = ((start_pc + codep - start_codep)
7216 & ~((bfd_vma) 0xffff));
252b5132 7217 }
d807a492 7218 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 7219 break;
7220 default:
7221 oappend (INTERNAL_DISASSEMBLER_ERROR);
7222 return;
7223 }
65ca155d 7224 disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
52b15da3
JH		 7225 set_op (disp, 0);
7226 print_operand_value (scratchbuf, 1, disp);
252b5132
RH		 7227 oappend (scratchbuf);
7228}
7229
252b5132 7230static void
ed7841b3 7231OP_SEG (int bytemode, int sizeflag)
252b5132 7232{
ed7841b3 7233 if (bytemode == w_mode)
7967e09e 7234 oappend (names_seg[modrm.reg]);
ed7841b3 7235 else
7967e09e 7236 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
252b5132
RH		 7237}
7238
7239static void
26ca5450 7240OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
252b5132
RH		 7241{
7242 int seg, offset;
7243
c608c12e 7244 if (sizeflag & DFLAG)
252b5132 7245 {
c608c12e
AM		 7246 offset = get32 ();
7247 seg = get16 ();
252b5132 7248 }
c608c12e
AM		 7249 else
7250 {
7251 offset = get16 ();
7252 seg = get16 ();
7253 }
7d421014 7254 used_prefixes |= (prefixes & PREFIX_DATA);
d708bcba 7255 if (intel_syntax)
3f31e633 7256 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
d708bcba
AM		 7257 else
7258 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
c608c12e 7259 oappend (scratchbuf);
252b5132
RH		 7260}
7261
252b5132 7262static void
3f31e633 7263OP_OFF (int bytemode, int sizeflag)
252b5132 7264{
52b15da3 7265 bfd_vma off;
252b5132 7266
3f31e633
JB		 7267 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
7268 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 7269 append_seg ();
7270
cb712a9e 7271 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132
RH		 7272 off = get32 ();
7273 else
7274 off = get16 ();
7275
7276 if (intel_syntax)
7277 {
7278 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 7279 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
252b5132 7280 {
d708bcba 7281 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 7282 oappend (":");
7283 }
7284 }
52b15da3
JH		 7285 print_operand_value (scratchbuf, 1, off);
7286 oappend (scratchbuf);
7287}
6439fc28 7288
52b15da3 7289static void
3f31e633 7290OP_OFF64 (int bytemode, int sizeflag)
52b15da3
JH		 7291{
7292 bfd_vma off;
7293
539e75ad
L		 7294 if (address_mode != mode_64bit
7295 || (prefixes & PREFIX_ADDR))
6439fc28
AM		 7296 {
7297 OP_OFF (bytemode, sizeflag);
7298 return;
7299 }
7300
3f31e633
JB		 7301 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
7302 intel_operand_size (bytemode, sizeflag);
52b15da3
JH		 7303 append_seg ();
7304
6608db57 7305 off = get64 ();
52b15da3
JH		 7306
7307 if (intel_syntax)
7308 {
7309 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 7310 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
52b15da3 7311 {
d708bcba 7312 oappend (names_seg[ds_reg - es_reg]);
52b15da3
JH		 7313 oappend (":");
7314 }
7315 }
7316 print_operand_value (scratchbuf, 1, off);
252b5132
RH		 7317 oappend (scratchbuf);
7318}
7319
7320static void
26ca5450 7321ptr_reg (int code, int sizeflag)
252b5132 7322{
2da11e11 7323 const char *s;
d708bcba 7324
1d9f512f 7325 *obufp++ = open_char;
20f0a1fc 7326 used_prefixes |= (prefixes & PREFIX_ADDR);
cb712a9e 7327 if (address_mode == mode_64bit)
c1a64871
JH		 7328 {
7329 if (!(sizeflag & AFLAG))
db6eb5be 7330 s = names32[code - eAX_reg];
c1a64871 7331 else
db6eb5be 7332 s = names64[code - eAX_reg];
c1a64871 7333 }
52b15da3 7334 else if (sizeflag & AFLAG)
252b5132
RH		 7335 s = names32[code - eAX_reg];
7336 else
7337 s = names16[code - eAX_reg];
7338 oappend (s);
1d9f512f
AM		 7339 *obufp++ = close_char;
7340 *obufp = 0;
252b5132
RH		 7341}
7342
7343static void
26ca5450 7344OP_ESreg (int code, int sizeflag)
252b5132 7345{
9306ca4a 7346 if (intel_syntax)
52fd6d94
JB		 7347 {
7348 switch (codep[-1])
7349 {
7350 case 0x6d: /* insw/insl */
7351 intel_operand_size (z_mode, sizeflag);
7352 break;
7353 case 0xa5: /* movsw/movsl/movsq */
7354 case 0xa7: /* cmpsw/cmpsl/cmpsq */
7355 case 0xab: /* stosw/stosl */
7356 case 0xaf: /* scasw/scasl */
7357 intel_operand_size (v_mode, sizeflag);
7358 break;
7359 default:
7360 intel_operand_size (b_mode, sizeflag);
7361 }
7362 }
d708bcba 7363 oappend ("%es:" + intel_syntax);
252b5132
RH		 7364 ptr_reg (code, sizeflag);
7365}
7366
7367static void
26ca5450 7368OP_DSreg (int code, int sizeflag)
252b5132 7369{
9306ca4a 7370 if (intel_syntax)
52fd6d94
JB		 7371 {
7372 switch (codep[-1])
7373 {
7374 case 0x6f: /* outsw/outsl */
7375 intel_operand_size (z_mode, sizeflag);
7376 break;
7377 case 0xa5: /* movsw/movsl/movsq */
7378 case 0xa7: /* cmpsw/cmpsl/cmpsq */
7379 case 0xad: /* lodsw/lodsl/lodsq */
7380 intel_operand_size (v_mode, sizeflag);
7381 break;
7382 default:
7383 intel_operand_size (b_mode, sizeflag);
7384 }
7385 }
252b5132
RH		 7386 if ((prefixes
7387 & (PREFIX_CS
7388 | PREFIX_DS
7389 | PREFIX_SS
7390 | PREFIX_ES
7391 | PREFIX_FS
7392 | PREFIX_GS)) == 0)
7393 prefixes |= PREFIX_DS;
6608db57 7394 append_seg ();
252b5132
RH		 7395 ptr_reg (code, sizeflag);
7396}
7397
252b5132 7398static void
26ca5450 7399OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7400{
9b60702d 7401 int add;
161a04f6 7402 if (rex & REX_R)
c4a530c5 7403 {
161a04f6 7404 USED_REX (REX_R);
c4a530c5
JB		 7405 add = 8;
7406 }
cb712a9e 7407 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
c4a530c5 7408 {
b844680a 7409 lock_prefix = NULL;
c4a530c5
JB		 7410 used_prefixes |= PREFIX_LOCK;
7411 add = 8;
7412 }
9b60702d
L		 7413 else
7414 add = 0;
7967e09e 7415 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
d708bcba 7416 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7417}
7418
252b5132 7419static void
26ca5450 7420OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7421{
9b60702d 7422 int add;
161a04f6
L		 7423 USED_REX (REX_R);
7424 if (rex & REX_R)
52b15da3 7425 add = 8;
9b60702d
L		 7426 else
7427 add = 0;
d708bcba 7428 if (intel_syntax)
7967e09e 7429 sprintf (scratchbuf, "db%d", modrm.reg + add);
d708bcba 7430 else
7967e09e 7431 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
252b5132
RH		 7432 oappend (scratchbuf);
7433}
7434
252b5132 7435static void
26ca5450 7436OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7437{
7967e09e 7438 sprintf (scratchbuf, "%%tr%d", modrm.reg);
d708bcba 7439 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7440}
7441
7442static void
6f74c397 7443OP_R (int bytemode, int sizeflag)
252b5132 7444{
7967e09e 7445 if (modrm.mod == 3)
2da11e11
AM		 7446 OP_E (bytemode, sizeflag);
7447 else
6608db57 7448 BadOp ();
252b5132
RH		 7449}
7450
7451static void
26ca5450 7452OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 7453{
041bd2e0
JH		 7454 used_prefixes |= (prefixes & PREFIX_DATA);
7455 if (prefixes & PREFIX_DATA)
20f0a1fc 7456 {
9b60702d 7457 int add;
161a04f6
L		 7458 USED_REX (REX_R);
7459 if (rex & REX_R)
20f0a1fc 7460 add = 8;
9b60702d
L		 7461 else
7462 add = 0;
7967e09e 7463 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
20f0a1fc 7464 }
041bd2e0 7465 else
7967e09e 7466 sprintf (scratchbuf, "%%mm%d", modrm.reg);
d708bcba 7467 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7468}
7469
c608c12e 7470static void
26ca5450 7471OP_XMM (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e 7472{
9b60702d 7473 int add;
161a04f6
L		 7474 USED_REX (REX_R);
7475 if (rex & REX_R)
041bd2e0 7476 add = 8;
9b60702d
L		 7477 else
7478 add = 0;
7967e09e 7479 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
d708bcba 7480 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 7481}
7482
252b5132 7483static void
26ca5450 7484OP_EM (int bytemode, int sizeflag)
252b5132 7485{
7967e09e 7486 if (modrm.mod != 3)
252b5132 7487 {
9306ca4a
JB		 7488 if (intel_syntax && bytemode == v_mode)
7489 {
7490 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
7491 used_prefixes |= (prefixes & PREFIX_DATA);
7492 }
252b5132
RH		 7493 OP_E (bytemode, sizeflag);
7494 return;
7495 }
7496
6608db57 7497 /* Skip mod/rm byte. */
4bba6815 7498 MODRM_CHECK;
252b5132 7499 codep++;
041bd2e0
JH		 7500 used_prefixes |= (prefixes & PREFIX_DATA);
7501 if (prefixes & PREFIX_DATA)
20f0a1fc 7502 {
9b60702d 7503 int add;
20f0a1fc 7504
161a04f6
L		 7505 USED_REX (REX_B);
7506 if (rex & REX_B)
20f0a1fc 7507 add = 8;
9b60702d
L		 7508 else
7509 add = 0;
7967e09e 7510 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
20f0a1fc 7511 }
041bd2e0 7512 else
7967e09e 7513 sprintf (scratchbuf, "%%mm%d", modrm.rm);
d708bcba 7514 oappend (scratchbuf + intel_syntax);
252b5132
RH		 7515}
7516
246c51aa
L		 7517/* cvt* are the only instructions in sse2 which have
7518 both SSE and MMX operands and also have 0x66 prefix
7519 in their opcode. 0x66 was originally used to differentiate
7520 between SSE and MMX instruction(operands). So we have to handle the
4d9567e0
MM		 7521 cvt* separately using OP_EMC and OP_MXC */
7522static void
7523OP_EMC (int bytemode, int sizeflag)
7524{
7967e09e 7525 if (modrm.mod != 3)
4d9567e0
MM		 7526 {
7527 if (intel_syntax && bytemode == v_mode)
7528 {
7529 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
7530 used_prefixes |= (prefixes & PREFIX_DATA);
7531 }
7532 OP_E (bytemode, sizeflag);
7533 return;
7534 }
246c51aa 7535
4d9567e0
MM		 7536 /* Skip mod/rm byte. */
7537 MODRM_CHECK;
7538 codep++;
7539 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 7540 sprintf (scratchbuf, "%%mm%d", modrm.rm);
4d9567e0
MM		 7541 oappend (scratchbuf + intel_syntax);
7542}
7543
7544static void
7545OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
7546{
7547 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 7548 sprintf (scratchbuf, "%%mm%d", modrm.reg);
4d9567e0
MM		 7549 oappend (scratchbuf + intel_syntax);
7550}
7551
c608c12e 7552static void
26ca5450 7553OP_EX (int bytemode, int sizeflag)
c608c12e 7554{
9b60702d 7555 int add;
7967e09e 7556 if (modrm.mod != 3)
c608c12e
AM		 7557 {
7558 OP_E (bytemode, sizeflag);
7559 return;
7560 }
161a04f6
L		 7561 USED_REX (REX_B);
7562 if (rex & REX_B)
041bd2e0 7563 add = 8;
9b60702d
L		 7564 else
7565 add = 0;
c608c12e 7566
6608db57 7567 /* Skip mod/rm byte. */
4bba6815 7568 MODRM_CHECK;
c608c12e 7569 codep++;
7967e09e 7570 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
d708bcba 7571 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 7572}
7573
252b5132 7574static void
26ca5450 7575OP_MS (int bytemode, int sizeflag)
252b5132 7576{
7967e09e 7577 if (modrm.mod == 3)
2da11e11
AM		 7578 OP_EM (bytemode, sizeflag);
7579 else
6608db57 7580 BadOp ();
252b5132
RH		 7581}
7582
992aaec9 7583static void
26ca5450 7584OP_XS (int bytemode, int sizeflag)
992aaec9 7585{
7967e09e 7586 if (modrm.mod == 3)
992aaec9
AM		 7587 OP_EX (bytemode, sizeflag);
7588 else
6608db57 7589 BadOp ();
992aaec9
AM		 7590}
7591
cc0ec051
AM		 7592static void
7593OP_M (int bytemode, int sizeflag)
7594{
7967e09e 7595 if (modrm.mod == 3)
75413a22
L		 7596 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
7597 BadOp ();
cc0ec051
AM		 7598 else
7599 OP_E (bytemode, sizeflag);
7600}
7601
7602static void
7603OP_0f07 (int bytemode, int sizeflag)
7604{
7967e09e 7605 if (modrm.mod != 3 || modrm.rm != 0)
cc0ec051
AM		 7606 BadOp ();
7607 else
7608 OP_E (bytemode, sizeflag);
7609}
7610
46e883c5 7611/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
246c51aa 7612 32bit mode and "xchg %rax,%rax" in 64bit mode. */
46e883c5 7613
cc0ec051 7614static void
46e883c5 7615NOP_Fixup1 (int bytemode, int sizeflag)
cc0ec051 7616{
8b38ad71
L		 7617 if ((prefixes & PREFIX_DATA) != 0
7618 || (rex != 0
7619 && rex != 0x48
7620 && address_mode == mode_64bit))
46e883c5
L		 7621 OP_REG (bytemode, sizeflag);
7622 else
7623 strcpy (obuf, "nop");
7624}
7625
7626static void
7627NOP_Fixup2 (int bytemode, int sizeflag)
7628{
8b38ad71
L		 7629 if ((prefixes & PREFIX_DATA) != 0
7630 || (rex != 0
7631 && rex != 0x48
7632 && address_mode == mode_64bit))
46e883c5 7633 OP_IMREG (bytemode, sizeflag);
cc0ec051
AM		 7634}
7635
84037f8c 7636static const char *const Suffix3DNow[] = {
252b5132
RH		 7637/* 00 */ NULL, NULL, NULL, NULL,
7638/* 04 */ NULL, NULL, NULL, NULL,
7639/* 08 */ NULL, NULL, NULL, NULL,
9e525108 7640/* 0C */ "pi2fw", "pi2fd", NULL, NULL,
252b5132
RH		 7641/* 10 */ NULL, NULL, NULL, NULL,
7642/* 14 */ NULL, NULL, NULL, NULL,
7643/* 18 */ NULL, NULL, NULL, NULL,
9e525108 7644/* 1C */ "pf2iw", "pf2id", NULL, NULL,
252b5132
RH		 7645/* 20 */ NULL, NULL, NULL, NULL,
7646/* 24 */ NULL, NULL, NULL, NULL,
7647/* 28 */ NULL, NULL, NULL, NULL,
7648/* 2C */ NULL, NULL, NULL, NULL,
7649/* 30 */ NULL, NULL, NULL, NULL,
7650/* 34 */ NULL, NULL, NULL, NULL,
7651/* 38 */ NULL, NULL, NULL, NULL,
7652/* 3C */ NULL, NULL, NULL, NULL,
7653/* 40 */ NULL, NULL, NULL, NULL,
7654/* 44 */ NULL, NULL, NULL, NULL,
7655/* 48 */ NULL, NULL, NULL, NULL,
7656/* 4C */ NULL, NULL, NULL, NULL,
7657/* 50 */ NULL, NULL, NULL, NULL,
7658/* 54 */ NULL, NULL, NULL, NULL,
7659/* 58 */ NULL, NULL, NULL, NULL,
7660/* 5C */ NULL, NULL, NULL, NULL,
7661/* 60 */ NULL, NULL, NULL, NULL,
7662/* 64 */ NULL, NULL, NULL, NULL,
7663/* 68 */ NULL, NULL, NULL, NULL,
7664/* 6C */ NULL, NULL, NULL, NULL,
7665/* 70 */ NULL, NULL, NULL, NULL,
7666/* 74 */ NULL, NULL, NULL, NULL,
7667/* 78 */ NULL, NULL, NULL, NULL,
7668/* 7C */ NULL, NULL, NULL, NULL,
7669/* 80 */ NULL, NULL, NULL, NULL,
7670/* 84 */ NULL, NULL, NULL, NULL,
9e525108
AM		 7671/* 88 */ NULL, NULL, "pfnacc", NULL,
7672/* 8C */ NULL, NULL, "pfpnacc", NULL,
252b5132
RH		 7673/* 90 */ "pfcmpge", NULL, NULL, NULL,
7674/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
7675/* 98 */ NULL, NULL, "pfsub", NULL,
7676/* 9C */ NULL, NULL, "pfadd", NULL,
7677/* A0 */ "pfcmpgt", NULL, NULL, NULL,
7678/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
7679/* A8 */ NULL, NULL, "pfsubr", NULL,
7680/* AC */ NULL, NULL, "pfacc", NULL,
7681/* B0 */ "pfcmpeq", NULL, NULL, NULL,
9beff690 7682/* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
9e525108 7683/* B8 */ NULL, NULL, NULL, "pswapd",
252b5132
RH		 7684/* BC */ NULL, NULL, NULL, "pavgusb",
7685/* C0 */ NULL, NULL, NULL, NULL,
7686/* C4 */ NULL, NULL, NULL, NULL,
7687/* C8 */ NULL, NULL, NULL, NULL,
7688/* CC */ NULL, NULL, NULL, NULL,
7689/* D0 */ NULL, NULL, NULL, NULL,
7690/* D4 */ NULL, NULL, NULL, NULL,
7691/* D8 */ NULL, NULL, NULL, NULL,
7692/* DC */ NULL, NULL, NULL, NULL,
7693/* E0 */ NULL, NULL, NULL, NULL,
7694/* E4 */ NULL, NULL, NULL, NULL,
7695/* E8 */ NULL, NULL, NULL, NULL,
7696/* EC */ NULL, NULL, NULL, NULL,
7697/* F0 */ NULL, NULL, NULL, NULL,
7698/* F4 */ NULL, NULL, NULL, NULL,
7699/* F8 */ NULL, NULL, NULL, NULL,
7700/* FC */ NULL, NULL, NULL, NULL,
7701};
7702
7703static void
26ca5450 7704OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132
RH		 7705{
7706 const char *mnemonic;
7707
7708 FETCH_DATA (the_info, codep + 1);
7709 /* AMD 3DNow! instructions are specified by an opcode suffix in the
7710 place where an 8-bit immediate would normally go. ie. the last
7711 byte of the instruction. */
6608db57 7712 obufp = obuf + strlen (obuf);
c608c12e 7713 mnemonic = Suffix3DNow[*codep++ & 0xff];
252b5132 7714 if (mnemonic)
2da11e11 7715 oappend (mnemonic);
252b5132
RH		 7716 else
7717 {
7718 /* Since a variable sized modrm/sib chunk is between the start
7719 of the opcode (0x0f0f) and the opcode suffix, we need to do
7720 all the modrm processing first, and don't know until now that
7721 we have a bad opcode. This necessitates some cleaning up. */
ce518a5f
L		 7722 op_out[0][0] = '\0';
7723 op_out[1][0] = '\0';
6608db57 7724 BadOp ();
252b5132
RH		 7725 }
7726}
c608c12e 7727
6608db57 7728static const char *simd_cmp_op[] = {
c608c12e
AM		 7729 "eq",
7730 "lt",
7731 "le",
7732 "unord",
7733 "neq",
7734 "nlt",
7735 "nle",
7736 "ord"
7737};
7738
7739static void
26ca5450 7740OP_SIMD_Suffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e
AM		 7741{
7742 unsigned int cmp_type;
7743
7744 FETCH_DATA (the_info, codep + 1);
6608db57 7745 obufp = obuf + strlen (obuf);
c608c12e
AM		 7746 cmp_type = *codep++ & 0xff;
7747 if (cmp_type < 8)
7748 {
041bd2e0
JH		 7749 char suffix1 = 'p', suffix2 = 's';
7750 used_prefixes |= (prefixes & PREFIX_REPZ);
7751 if (prefixes & PREFIX_REPZ)
7752 suffix1 = 's';
7753 else
7754 {
7755 used_prefixes |= (prefixes & PREFIX_DATA);
7756 if (prefixes & PREFIX_DATA)
7757 suffix2 = 'd';
7758 else
7759 {
7760 used_prefixes |= (prefixes & PREFIX_REPNZ);
7761 if (prefixes & PREFIX_REPNZ)
7762 suffix1 = 's', suffix2 = 'd';
7763 }
7764 }
7765 sprintf (scratchbuf, "cmp%s%c%c",
7766 simd_cmp_op[cmp_type], suffix1, suffix2);
7d421014 7767 used_prefixes |= (prefixes & PREFIX_REPZ);
2da11e11 7768 oappend (scratchbuf);
c608c12e
AM		 7769 }
7770 else
7771 {
7772 /* We have a bad extension byte. Clean up. */
ce518a5f
L		 7773 op_out[0][0] = '\0';
7774 op_out[1][0] = '\0';
6608db57 7775 BadOp ();
c608c12e
AM		 7776 }
7777}
7778
ca164297 7779static void
b844680a
L		 7780OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
7781 int sizeflag ATTRIBUTE_UNUSED)
7782{
7783 /* mwait %eax,%ecx */
7784 if (!intel_syntax)
7785 {
7786 const char **names = (address_mode == mode_64bit
7787 ? names64 : names32);
7788 strcpy (op_out[0], names[0]);
7789 strcpy (op_out[1], names[1]);
7790 two_source_ops = 1;
7791 }
7792 /* Skip mod/rm byte. */
7793 MODRM_CHECK;
7794 codep++;
7795}
7796
7797static void
7798OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
7799 int sizeflag ATTRIBUTE_UNUSED)
ca164297 7800{
b844680a
L		 7801 /* monitor %eax,%ecx,%edx" */
7802 if (!intel_syntax)
ca164297 7803 {
b844680a 7804 const char **op1_names;
cb712a9e
L		 7805 const char **names = (address_mode == mode_64bit
7806 ? names64 : names32);
1d9f512f 7807
b844680a
L		 7808 if (!(prefixes & PREFIX_ADDR))
7809 op1_names = (address_mode == mode_16bit
7810 ? names16 : names);
ca164297
L		 7811 else
7812 {
b844680a
L		 7813 /* Remove "addr16/addr32". */
7814 addr_prefix = NULL;
7815 op1_names = (address_mode != mode_32bit
7816 ? names32 : names16);
7817 used_prefixes |= PREFIX_ADDR;
ca164297 7818 }
b844680a
L		 7819 strcpy (op_out[0], op1_names[0]);
7820 strcpy (op_out[1], names[1]);
7821 strcpy (op_out[2], names[2]);
7822 two_source_ops = 1;
ca164297 7823 }
b844680a
L		 7824 /* Skip mod/rm byte. */
7825 MODRM_CHECK;
7826 codep++;
30123838
JB		 7827}
7828
6608db57
KH		 7829static void
7830BadOp (void)
2da11e11 7831{
6608db57
KH		 7832 /* Throw away prefixes and 1st. opcode byte. */
7833 codep = insn_codep + 1;
2da11e11
AM		 7834 oappend ("(bad)");
7835}
4cc91dba 7836
35c52694
L		 7837static void
7838REP_Fixup (int bytemode, int sizeflag)
7839{
7840 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
7841 lods and stos. */
35c52694 7842 if (prefixes & PREFIX_REPZ)
b844680a 7843 repz_prefix = "rep ";
35c52694
L		 7844
7845 switch (bytemode)
7846 {
7847 case al_reg:
7848 case eAX_reg:
7849 case indir_dx_reg:
7850 OP_IMREG (bytemode, sizeflag);
7851 break;
7852 case eDI_reg:
7853 OP_ESreg (bytemode, sizeflag);
7854 break;
7855 case eSI_reg:
7856 OP_DSreg (bytemode, sizeflag);
7857 break;
7858 default:
7859 abort ();
7860 break;
7861 }
7862}
f5804c90
L		 7863
7864static void
7865CMPXCHG8B_Fixup (int bytemode, int sizeflag)
7866{
161a04f6
L		 7867 USED_REX (REX_W);
7868 if (rex & REX_W)
f5804c90
L		 7869 {
7870 /* Change cmpxchg8b to cmpxchg16b. */
7871 char *p = obuf + strlen (obuf) - 2;
7872 strcpy (p, "16b");
fb9c77c7 7873 bytemode = o_mode;
f5804c90
L		 7874 }
7875 OP_M (bytemode, sizeflag);
7876}
42903f7f
L		 7877
7878static void
7879XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
7880{
7881 sprintf (scratchbuf, "%%xmm%d", reg);
7882 oappend (scratchbuf + intel_syntax);
7883}
381d071f
L		 7884
7885static void
7886CRC32_Fixup (int bytemode, int sizeflag)
7887{
7888 /* Add proper suffix to "crc32". */
7889 char *p = obuf + strlen (obuf);
7890
7891 switch (bytemode)
7892 {
7893 case b_mode:
20592a94
L		 7894 if (intel_syntax)
7895 break;
7896
381d071f
L		 7897 *p++ = 'b';
7898 break;
7899 case v_mode:
20592a94
L		 7900 if (intel_syntax)
7901 break;
7902
381d071f
L		 7903 USED_REX (REX_W);
7904 if (rex & REX_W)
7905 *p++ = 'q';
9344ff29 7906 else if (sizeflag & DFLAG)
20592a94 7907 *p++ = 'l';
381d071f 7908 else
9344ff29
L		 7909 *p++ = 'w';
7910 used_prefixes |= (prefixes & PREFIX_DATA);
381d071f
L		 7911 break;
7912 default:
7913 oappend (INTERNAL_DISASSEMBLER_ERROR);
7914 break;
7915 }
7916 *p = '\0';
7917
7918 if (modrm.mod == 3)
7919 {
7920 int add;
7921
7922 /* Skip mod/rm byte. */
7923 MODRM_CHECK;
7924 codep++;
7925
7926 USED_REX (REX_B);
7927 add = (rex & REX_B) ? 8 : 0;
7928 if (bytemode == b_mode)
7929 {
7930 USED_REX (0);
7931 if (rex)
7932 oappend (names8rex[modrm.rm + add]);
7933 else
7934 oappend (names8[modrm.rm + add]);
7935 }
7936 else
7937 {
7938 USED_REX (REX_W);
7939 if (rex & REX_W)
7940 oappend (names64[modrm.rm + add]);
7941 else if ((prefixes & PREFIX_DATA))
7942 oappend (names16[modrm.rm + add]);
7943 else
7944 oappend (names32[modrm.rm + add]);
7945 }
7946 }
7947 else
9344ff29 7948 OP_E (bytemode, sizeflag);
381d071f 7949}
85f10a01
MM		 7950
7951/* Print a DREX argument as either a register or memory operation. */
7952static void
7953print_drex_arg (unsigned int reg, int bytemode, int sizeflag)
7954{
7955 if (reg == DREX_REG_UNKNOWN)
7956 BadOp ();
7957
7958 else if (reg != DREX_REG_MEMORY)
7959 {
7960 sprintf (scratchbuf, "%%xmm%d", reg);
7961 oappend (scratchbuf + intel_syntax);
7962 }
7963
7964 else
7965 OP_E_extended (bytemode, sizeflag, 1);
7966}
7967
7968/* SSE5 instructions that have 4 arguments are encoded as:
7969 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>.
7970
7971 The <sub-opcode> byte has 1 bit (0x4) that is combined with 1 bit in
7972 the DREX field (0x8) to determine how the arguments are laid out.
7973 The destination register must be the same register as one of the
7974 inputs, and it is encoded in the DREX byte. No REX prefix is used
7975 for these instructions, since the DREX field contains the 3 extension
7976 bits provided by the REX prefix.
7977
7978 The bytemode argument adds 2 extra bits for passing extra information:
7979 DREX_OC1 -- Set the OC1 bit to indicate dest == 1st arg
7980 DREX_NO_OC0 -- OC0 in DREX is invalid
7981 (but pretend it is set). */
7982
7983static void
7984OP_DREX4 (int flag_bytemode, int sizeflag)
7985{
7986 unsigned int drex_byte;
7987 unsigned int regs[4];
7988 unsigned int modrm_regmem;
7989 unsigned int modrm_reg;
7990 unsigned int drex_reg;
7991 int bytemode;
7992 int rex_save = rex;
7993 int rex_used_save = rex_used;
7994 int has_sib = 0;
7995 int oc1 = (flag_bytemode & DREX_OC1) ? 2 : 0;
7996 int oc0;
7997 int i;
7998
7999 bytemode = flag_bytemode & ~ DREX_MASK;
8000
8001 for (i = 0; i < 4; i++)
8002 regs[i] = DREX_REG_UNKNOWN;
8003
8004 /* Determine if we have a SIB byte in addition to MODRM before the
8005 DREX byte. */
8006 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
8007 && (modrm.mod != 3)
8008 && (modrm.rm == 4))
8009 has_sib = 1;
8010
8011 /* Get the DREX byte. */
8012 FETCH_DATA (the_info, codep + 2 + has_sib);
8013 drex_byte = codep[has_sib+1];
8014 drex_reg = DREX_XMM (drex_byte);
8015 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
8016
8017 /* Is OC0 legal? If not, hardwire oc0 == 1. */
8018 if (flag_bytemode & DREX_NO_OC0)
8019 {
8020 oc0 = 1;
8021 if (DREX_OC0 (drex_byte))
8022 BadOp ();
8023 }
8024 else
8025 oc0 = DREX_OC0 (drex_byte);
8026
8027 if (modrm.mod == 3)
8028 {
8029 /* regmem == register */
8030 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
8031 rex = rex_used = 0;
8032 /* skip modrm/drex since we don't call OP_E_extended */
8033 codep += 2;
8034 }
8035 else
8036 {
8037 /* regmem == memory, fill in appropriate REX bits */
8038 modrm_regmem = DREX_REG_MEMORY;
8039 rex = drex_byte & (REX_B | REX_X | REX_R);
8040 if (rex)
8041 rex |= REX_OPCODE;
8042 rex_used = rex;
8043 }
8044
8045 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
8046 order. */
8047 switch (oc0 + oc1)
8048 {
8049 default:
8050 BadOp ();
8051 return;
8052
8053 case 0:
8054 regs[0] = modrm_regmem;
8055 regs[1] = modrm_reg;
8056 regs[2] = drex_reg;
8057 regs[3] = drex_reg;
8058 break;
8059
8060 case 1:
8061 regs[0] = modrm_reg;
8062 regs[1] = modrm_regmem;
8063 regs[2] = drex_reg;
8064 regs[3] = drex_reg;
8065 break;
8066
8067 case 2:
8068 regs[0] = drex_reg;
8069 regs[1] = modrm_regmem;
8070 regs[2] = modrm_reg;
8071 regs[3] = drex_reg;
8072 break;
8073
8074 case 3:
8075 regs[0] = drex_reg;
8076 regs[1] = modrm_reg;
8077 regs[2] = modrm_regmem;
8078 regs[3] = drex_reg;
8079 break;
8080 }
8081
8082 /* Print out the arguments. */
8083 for (i = 0; i < 4; i++)
8084 {
8085 int j = (intel_syntax) ? 3 - i : i;
8086 if (i > 0)
8087 {
8088 *obufp++ = ',';
8089 *obufp = '\0';
8090 }
8091
8092 print_drex_arg (regs[j], bytemode, sizeflag);
8093 }
8094
8095 rex = rex_save;
8096 rex_used = rex_used_save;
8097}
8098
8099/* SSE5 instructions that have 3 arguments, and are encoded as:
8100 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset> (or)
8101 0f 25 <sub-opcode> <modrm> <optional-sib> <drex> <offset> <cmp-byte>
8102
8103 The DREX field has 1 bit (0x8) to determine how the arguments are
8104 laid out. The destination register is encoded in the DREX byte.
8105 No REX prefix is used for these instructions, since the DREX field
8106 contains the 3 extension bits provided by the REX prefix. */
8107
8108static void
8109OP_DREX3 (int flag_bytemode, int sizeflag)
8110{
8111 unsigned int drex_byte;
8112 unsigned int regs[3];
8113 unsigned int modrm_regmem;
8114 unsigned int modrm_reg;
8115 unsigned int drex_reg;
8116 int bytemode;
8117 int rex_save = rex;
8118 int rex_used_save = rex_used;
8119 int has_sib = 0;
8120 int oc0;
8121 int i;
8122
8123 bytemode = flag_bytemode & ~ DREX_MASK;
8124
8125 for (i = 0; i < 3; i++)
8126 regs[i] = DREX_REG_UNKNOWN;
8127
8128 /* Determine if we have a SIB byte in addition to MODRM before the
8129 DREX byte. */
8130 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
8131 && (modrm.mod != 3)
8132 && (modrm.rm == 4))
8133 has_sib = 1;
8134
8135 /* Get the DREX byte. */
8136 FETCH_DATA (the_info, codep + 2 + has_sib);
8137 drex_byte = codep[has_sib+1];
8138 drex_reg = DREX_XMM (drex_byte);
8139 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
8140
8141 /* Is OC0 legal? If not, hardwire oc0 == 0 */
8142 oc0 = DREX_OC0 (drex_byte);
8143 if ((flag_bytemode & DREX_NO_OC0) && oc0)
8144 BadOp ();
8145
8146 if (modrm.mod == 3)
8147 {
8148 /* regmem == register */
8149 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
8150 rex = rex_used = 0;
8151 /* skip modrm/drex since we don't call OP_E_extended. */
8152 codep += 2;
8153 }
8154 else
8155 {
8156 /* regmem == memory, fill in appropriate REX bits. */
8157 modrm_regmem = DREX_REG_MEMORY;
8158 rex = drex_byte & (REX_B | REX_X | REX_R);
8159 if (rex)
8160 rex |= REX_OPCODE;
8161 rex_used = rex;
8162 }
8163
8164 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
8165 order. */
8166 switch (oc0)
8167 {
8168 default:
8169 BadOp ();
8170 return;
8171
8172 case 0:
8173 regs[0] = modrm_regmem;
8174 regs[1] = modrm_reg;
8175 regs[2] = drex_reg;
8176 break;
8177
8178 case 1:
8179 regs[0] = modrm_reg;
8180 regs[1] = modrm_regmem;
8181 regs[2] = drex_reg;
8182 break;
8183 }
8184
8185 /* Print out the arguments. */
8186 for (i = 0; i < 3; i++)
8187 {
8188 int j = (intel_syntax) ? 2 - i : i;
8189 if (i > 0)
8190 {
8191 *obufp++ = ',';
8192 *obufp = '\0';
8193 }
8194
8195 print_drex_arg (regs[j], bytemode, sizeflag);
8196 }
8197
8198 rex = rex_save;
8199 rex_used = rex_used_save;
8200}
8201
8202/* Emit a floating point comparison for comp<xx> instructions. */
8203
8204static void
8205OP_DREX_FCMP (int bytemode ATTRIBUTE_UNUSED,
8206 int sizeflag ATTRIBUTE_UNUSED)
8207{
8208 unsigned char byte;
8209
8210 static const char *const cmp_test[] = {
8211 "eq",
8212 "lt",
8213 "le",
8214 "unord",
8215 "ne",
8216 "nlt",
8217 "nle",
8218 "ord",
8219 "ueq",
8220 "ult",
8221 "ule",
8222 "false",
8223 "une",
8224 "unlt",
8225 "unle",
8226 "true"
8227 };
8228
8229 FETCH_DATA (the_info, codep + 1);
8230 byte = *codep & 0xff;
8231
8232 if (byte >= ARRAY_SIZE (cmp_test)
8233 || obuf[0] != 'c'
8234 || obuf[1] != 'o'
8235 || obuf[2] != 'm')
8236 {
8237 /* The instruction isn't one we know about, so just append the
8238 extension byte as a numeric value. */
8239 OP_I (b_mode, 0);
8240 }
8241
8242 else
8243 {
8244 sprintf (scratchbuf, "com%s%s", cmp_test[byte], obuf+3);
8245 strcpy (obuf, scratchbuf);
8246 codep++;
8247 }
8248}
8249
8250/* Emit an integer point comparison for pcom<xx> instructions,
8251 rewriting the instruction to have the test inside of it. */
8252
8253static void
8254OP_DREX_ICMP (int bytemode ATTRIBUTE_UNUSED,
8255 int sizeflag ATTRIBUTE_UNUSED)
8256{
8257 unsigned char byte;
8258
8259 static const char *const cmp_test[] = {
8260 "lt",
8261 "le",
8262 "gt",
8263 "ge",
8264 "eq",
8265 "ne",
8266 "false",
8267 "true"
8268 };
8269
8270 FETCH_DATA (the_info, codep + 1);
8271 byte = *codep & 0xff;
8272
8273 if (byte >= ARRAY_SIZE (cmp_test)
8274 || obuf[0] != 'p'
8275 || obuf[1] != 'c'
8276 || obuf[2] != 'o'
8277 || obuf[3] != 'm')
8278 {
8279 /* The instruction isn't one we know about, so just print the
8280 comparison test byte as a numeric value. */
8281 OP_I (b_mode, 0);
8282 }
8283
8284 else
8285 {
8286 sprintf (scratchbuf, "pcom%s%s", cmp_test[byte], obuf+4);
8287 strcpy (obuf, scratchbuf);
8288 codep++;
8289 }
8290}
GDB Binutils - Deliverables
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