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* dwarf2read.c (struct dwarf2_cu): Remove ranges_offset and
[deliverable/binutils-gdb.git] / opcodes / i386-dis.c
CommitLineData
252b5132 1/* Print i386 instructions for GDB, the GNU debugger.
060d22b0 2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0bfee649 3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
0af1713e 4 Free Software Foundation, Inc.
252b5132 5
9b201bb5 6 This file is part of the GNU opcodes library.
20f0a1fc 7
9b201bb5 8 This library is free software; you can redistribute it and/or modify
20f0a1fc 9 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
20f0a1fc 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
20f0a1fc
NC		 17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
20f0a1fc
NC		 23
24/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
25 July 1988
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
29
30/* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
252b5132 36
252b5132 37#include "sysdep.h"
dabbade6 38#include "dis-asm.h"
252b5132 39#include "opintl.h"
0b1cf022 40#include "opcode/i386.h"
85f10a01 41#include "libiberty.h"
252b5132
RH		 42
43#include <setjmp.h>
44
26ca5450
AJ		 45static int fetch_data (struct disassemble_info *, bfd_byte *);
46static void ckprefix (void);
47static const char *prefix_name (int, int);
48static int print_insn (bfd_vma, disassemble_info *);
49static void dofloat (int);
50static void OP_ST (int, int);
51static void OP_STi (int, int);
52static int putop (const char *, int);
53static void oappend (const char *);
54static void append_seg (void);
55static void OP_indirE (int, int);
56static void print_operand_value (char *, int, bfd_vma);
c0f3af97 57static void OP_E_register (int, int);
c1e679ec
DR		 58static void OP_E_memory (int, int);
59static void OP_E_extended (int, int);
5d669648 60static void print_displacement (char *, bfd_vma);
26ca5450
AJ		 61static void OP_E (int, int);
62static void OP_G (int, int);
63static bfd_vma get64 (void);
64static bfd_signed_vma get32 (void);
65static bfd_signed_vma get32s (void);
66static int get16 (void);
67static void set_op (bfd_vma, int);
b844680a 68static void OP_Skip_MODRM (int, int);
26ca5450
AJ		 69static void OP_REG (int, int);
70static void OP_IMREG (int, int);
71static void OP_I (int, int);
72static void OP_I64 (int, int);
73static void OP_sI (int, int);
74static void OP_J (int, int);
75static void OP_SEG (int, int);
76static void OP_DIR (int, int);
77static void OP_OFF (int, int);
78static void OP_OFF64 (int, int);
79static void ptr_reg (int, int);
80static void OP_ESreg (int, int);
81static void OP_DSreg (int, int);
82static void OP_C (int, int);
83static void OP_D (int, int);
84static void OP_T (int, int);
6f74c397 85static void OP_R (int, int);
26ca5450
AJ		 86static void OP_MMX (int, int);
87static void OP_XMM (int, int);
88static void OP_EM (int, int);
89static void OP_EX (int, int);
4d9567e0
MM		 90static void OP_EMC (int,int);
91static void OP_MXC (int,int);
26ca5450
AJ		 92static void OP_MS (int, int);
93static void OP_XS (int, int);
cc0ec051 94static void OP_M (int, int);
c0f3af97
L		 95static void OP_VEX (int, int);
96static void OP_EX_Vex (int, int);
922d8de8 97static void OP_EX_VexW (int, int);
c0f3af97 98static void OP_XMM_Vex (int, int);
922d8de8 99static void OP_XMM_VexW (int, int);
c0f3af97
L		 100static void OP_REG_VexI4 (int, int);
101static void PCLMUL_Fixup (int, int);
922d8de8 102static void VEXI4_Fixup (int, int);
c0f3af97
L		 103static void VZERO_Fixup (int, int);
104static void VCMP_Fixup (int, int);
cc0ec051 105static void OP_0f07 (int, int);
b844680a
L		 106static void OP_Monitor (int, int);
107static void OP_Mwait (int, int);
46e883c5
L		 108static void NOP_Fixup1 (int, int);
109static void NOP_Fixup2 (int, int);
26ca5450 110static void OP_3DNowSuffix (int, int);
ad19981d 111static void CMP_Fixup (int, int);
26ca5450 112static void BadOp (void);
35c52694 113static void REP_Fixup (int, int);
f5804c90 114static void CMPXCHG8B_Fixup (int, int);
42903f7f 115static void XMM_Fixup (int, int);
381d071f 116static void CRC32_Fixup (int, int);
c1e679ec 117
f1f8f695 118static void MOVBE_Fixup (int, int);
252b5132 119
6608db57 120struct dis_private {
252b5132
RH		 121 /* Points to first byte not fetched. */
122 bfd_byte *max_fetched;
0b1cf022 123 bfd_byte the_buffer[MAX_MNEM_SIZE];
252b5132 124 bfd_vma insn_start;
e396998b 125 int orig_sizeflag;
252b5132
RH		 126 jmp_buf bailout;
127};
128
cb712a9e
L		 129enum address_mode
130{
131 mode_16bit,
132 mode_32bit,
133 mode_64bit
134};
135
136enum address_mode address_mode;
52b15da3 137
5076851f
ILT		 138/* Flags for the prefixes for the current instruction. See below. */
139static int prefixes;
140
52b15da3
JH		 141/* REX prefix the current instruction. See below. */
142static int rex;
143/* Bits of REX we've already used. */
144static int rex_used;
c0f3af97
L		 145/* Original REX prefix. */
146static int rex_original;
147/* REX bits in original REX prefix ignored. It may not be the same
148 as rex_original since some bits may not be ignored. */
149static int rex_ignored;
52b15da3
JH		 150/* Mark parts used in the REX prefix. When we are testing for
151 empty prefix (for 8bit register REX extension), just mask it
152 out. Otherwise test for REX bit is excuse for existence of REX
153 only in case value is nonzero. */
154#define USED_REX(value) \
155 { \
156 if (value) \
161a04f6
L		 157 { \
158 if ((rex & value)) \
159 rex_used |= (value) | REX_OPCODE; \
160 } \
52b15da3 161 else \
161a04f6 162 rex_used |= REX_OPCODE; \
52b15da3
JH		 163 }
164
7d421014
ILT		 165/* Flags for prefixes which we somehow handled when printing the
166 current instruction. */
167static int used_prefixes;
168
5076851f
ILT		 169/* Flags stored in PREFIXES. */
170#define PREFIX_REPZ 1
171#define PREFIX_REPNZ 2
172#define PREFIX_LOCK 4
173#define PREFIX_CS 8
174#define PREFIX_SS 0x10
175#define PREFIX_DS 0x20
176#define PREFIX_ES 0x40
177#define PREFIX_FS 0x80
178#define PREFIX_GS 0x100
179#define PREFIX_DATA 0x200
180#define PREFIX_ADDR 0x400
181#define PREFIX_FWAIT 0x800
182
252b5132
RH		 183/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
184 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
185 on error. */
186#define FETCH_DATA(info, addr) \
6608db57 187 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
252b5132
RH		 188 ? 1 : fetch_data ((info), (addr)))
189
190static int
26ca5450 191fetch_data (struct disassemble_info *info, bfd_byte *addr)
252b5132
RH		 192{
193 int status;
6608db57 194 struct dis_private *priv = (struct dis_private *) info->private_data;
252b5132
RH		 195 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
196
0b1cf022 197 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
272c9217
JB		 198 status = (*info->read_memory_func) (start,
199 priv->max_fetched,
200 addr - priv->max_fetched,
201 info);
202 else
203 status = -1;
252b5132
RH		 204 if (status != 0)
205 {
7d421014 206 /* If we did manage to read at least one byte, then
db6eb5be
AM		 207 print_insn_i386 will do something sensible. Otherwise, print
208 an error. We do that here because this is where we know
209 STATUS. */
7d421014 210 if (priv->max_fetched == priv->the_buffer)
5076851f 211 (*info->memory_error_func) (status, start, info);
252b5132
RH		 212 longjmp (priv->bailout, 1);
213 }
214 else
215 priv->max_fetched = addr;
216 return 1;
217}
218
ce518a5f
L		 219#define XX { NULL, 0 }
220
221#define Eb { OP_E, b_mode }
b6169b20 222#define EbS { OP_E, b_swap_mode }
ce518a5f 223#define Ev { OP_E, v_mode }
b6169b20 224#define EvS { OP_E, v_swap_mode }
ce518a5f
L		 225#define Ed { OP_E, d_mode }
226#define Edq { OP_E, dq_mode }
227#define Edqw { OP_E, dqw_mode }
42903f7f
L		 228#define Edqb { OP_E, dqb_mode }
229#define Edqd { OP_E, dqd_mode }
09335d05 230#define Eq { OP_E, q_mode }
ce518a5f
L		 231#define indirEv { OP_indirE, stack_v_mode }
232#define indirEp { OP_indirE, f_mode }
233#define stackEv { OP_E, stack_v_mode }
234#define Em { OP_E, m_mode }
235#define Ew { OP_E, w_mode }
236#define M { OP_M, 0 } /* lea, lgdt, etc. */
34b772a6 237#define Ma { OP_M, a_mode }
b844680a 238#define Mb { OP_M, b_mode }
d9a5e5e5 239#define Md { OP_M, d_mode }
f1f8f695 240#define Mo { OP_M, o_mode }
ce518a5f
L		 241#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
242#define Mq { OP_M, q_mode }
4ee52178 243#define Mx { OP_M, x_mode }
c0f3af97 244#define Mxmm { OP_M, xmm_mode }
ce518a5f
L		 245#define Gb { OP_G, b_mode }
246#define Gv { OP_G, v_mode }
247#define Gd { OP_G, d_mode }
248#define Gdq { OP_G, dq_mode }
249#define Gm { OP_G, m_mode }
250#define Gw { OP_G, w_mode }
6f74c397
L		 251#define Rd { OP_R, d_mode }
252#define Rm { OP_R, m_mode }
ce518a5f
L		 253#define Ib { OP_I, b_mode }
254#define sIb { OP_sI, b_mode } /* sign extened byte */
255#define Iv { OP_I, v_mode }
256#define Iq { OP_I, q_mode }
257#define Iv64 { OP_I64, v_mode }
258#define Iw { OP_I, w_mode }
259#define I1 { OP_I, const_1_mode }
260#define Jb { OP_J, b_mode }
261#define Jv { OP_J, v_mode }
262#define Cm { OP_C, m_mode }
263#define Dm { OP_D, m_mode }
264#define Td { OP_T, d_mode }
b844680a 265#define Skip_MODRM { OP_Skip_MODRM, 0 }
ce518a5f
L		 266
267#define RMeAX { OP_REG, eAX_reg }
268#define RMeBX { OP_REG, eBX_reg }
269#define RMeCX { OP_REG, eCX_reg }
270#define RMeDX { OP_REG, eDX_reg }
271#define RMeSP { OP_REG, eSP_reg }
272#define RMeBP { OP_REG, eBP_reg }
273#define RMeSI { OP_REG, eSI_reg }
274#define RMeDI { OP_REG, eDI_reg }
275#define RMrAX { OP_REG, rAX_reg }
276#define RMrBX { OP_REG, rBX_reg }
277#define RMrCX { OP_REG, rCX_reg }
278#define RMrDX { OP_REG, rDX_reg }
279#define RMrSP { OP_REG, rSP_reg }
280#define RMrBP { OP_REG, rBP_reg }
281#define RMrSI { OP_REG, rSI_reg }
282#define RMrDI { OP_REG, rDI_reg }
283#define RMAL { OP_REG, al_reg }
284#define RMAL { OP_REG, al_reg }
285#define RMCL { OP_REG, cl_reg }
286#define RMDL { OP_REG, dl_reg }
287#define RMBL { OP_REG, bl_reg }
288#define RMAH { OP_REG, ah_reg }
289#define RMCH { OP_REG, ch_reg }
290#define RMDH { OP_REG, dh_reg }
291#define RMBH { OP_REG, bh_reg }
292#define RMAX { OP_REG, ax_reg }
293#define RMDX { OP_REG, dx_reg }
294
295#define eAX { OP_IMREG, eAX_reg }
296#define eBX { OP_IMREG, eBX_reg }
297#define eCX { OP_IMREG, eCX_reg }
298#define eDX { OP_IMREG, eDX_reg }
299#define eSP { OP_IMREG, eSP_reg }
300#define eBP { OP_IMREG, eBP_reg }
301#define eSI { OP_IMREG, eSI_reg }
302#define eDI { OP_IMREG, eDI_reg }
303#define AL { OP_IMREG, al_reg }
304#define CL { OP_IMREG, cl_reg }
305#define DL { OP_IMREG, dl_reg }
306#define BL { OP_IMREG, bl_reg }
307#define AH { OP_IMREG, ah_reg }
308#define CH { OP_IMREG, ch_reg }
309#define DH { OP_IMREG, dh_reg }
310#define BH { OP_IMREG, bh_reg }
311#define AX { OP_IMREG, ax_reg }
312#define DX { OP_IMREG, dx_reg }
313#define zAX { OP_IMREG, z_mode_ax_reg }
314#define indirDX { OP_IMREG, indir_dx_reg }
315
316#define Sw { OP_SEG, w_mode }
317#define Sv { OP_SEG, v_mode }
318#define Ap { OP_DIR, 0 }
319#define Ob { OP_OFF64, b_mode }
320#define Ov { OP_OFF64, v_mode }
321#define Xb { OP_DSreg, eSI_reg }
322#define Xv { OP_DSreg, eSI_reg }
323#define Xz { OP_DSreg, eSI_reg }
324#define Yb { OP_ESreg, eDI_reg }
325#define Yv { OP_ESreg, eDI_reg }
326#define DSBX { OP_DSreg, eBX_reg }
327
328#define es { OP_REG, es_reg }
329#define ss { OP_REG, ss_reg }
330#define cs { OP_REG, cs_reg }
331#define ds { OP_REG, ds_reg }
332#define fs { OP_REG, fs_reg }
333#define gs { OP_REG, gs_reg }
334
335#define MX { OP_MMX, 0 }
336#define XM { OP_XMM, 0 }
c0f3af97 337#define XMM { OP_XMM, xmm_mode }
ce518a5f 338#define EM { OP_EM, v_mode }
b6169b20 339#define EMS { OP_EM, v_swap_mode }
09a2c6cf 340#define EMd { OP_EM, d_mode }
14051056 341#define EMx { OP_EM, x_mode }
8976381e 342#define EXw { OP_EX, w_mode }
09a2c6cf 343#define EXd { OP_EX, d_mode }
fa99fab2 344#define EXdS { OP_EX, d_swap_mode }
09a2c6cf 345#define EXq { OP_EX, q_mode }
b6169b20 346#define EXqS { OP_EX, q_swap_mode }
09a2c6cf 347#define EXx { OP_EX, x_mode }
b6169b20 348#define EXxS { OP_EX, x_swap_mode }
c0f3af97
L		 349#define EXxmm { OP_EX, xmm_mode }
350#define EXxmmq { OP_EX, xmmq_mode }
351#define EXymmq { OP_EX, ymmq_mode }
0bfee649 352#define EXVexWdq { OP_EX, vex_w_dq_mode }
ce518a5f
L		 353#define MS { OP_MS, v_mode }
354#define XS { OP_XS, v_mode }
09335d05 355#define EMCq { OP_EMC, q_mode }
ce518a5f 356#define MXC { OP_MXC, 0 }
ce518a5f 357#define OPSUF { OP_3DNowSuffix, 0 }
ad19981d 358#define CMP { CMP_Fixup, 0 }
42903f7f 359#define XMM0 { XMM_Fixup, 0 }
252b5132 360
c0f3af97
L		 361#define Vex { OP_VEX, vex_mode }
362#define Vex128 { OP_VEX, vex128_mode }
363#define Vex256 { OP_VEX, vex256_mode }
922d8de8 364#define VexI4 { VEXI4_Fixup, 0}
c0f3af97 365#define EXdVex { OP_EX_Vex, d_mode }
fa99fab2 366#define EXdVexS { OP_EX_Vex, d_swap_mode }
c0f3af97 367#define EXqVex { OP_EX_Vex, q_mode }
fa99fab2 368#define EXqVexS { OP_EX_Vex, q_swap_mode }
922d8de8
DR		 369#define EXVexW { OP_EX_VexW, x_mode }
370#define EXdVexW { OP_EX_VexW, d_mode }
371#define EXqVexW { OP_EX_VexW, q_mode }
c0f3af97 372#define XMVex { OP_XMM_Vex, 0 }
922d8de8 373#define XMVexW { OP_XMM_VexW, 0 }
c0f3af97
L		 374#define XMVexI4 { OP_REG_VexI4, x_mode }
375#define PCLMUL { PCLMUL_Fixup, 0 }
376#define VZERO { VZERO_Fixup, 0 }
377#define VCMP { VCMP_Fixup, 0 }
c0f3af97 378
35c52694 379/* Used handle "rep" prefix for string instructions. */
ce518a5f
L		 380#define Xbr { REP_Fixup, eSI_reg }
381#define Xvr { REP_Fixup, eSI_reg }
382#define Ybr { REP_Fixup, eDI_reg }
383#define Yvr { REP_Fixup, eDI_reg }
384#define Yzr { REP_Fixup, eDI_reg }
385#define indirDXr { REP_Fixup, indir_dx_reg }
386#define ALr { REP_Fixup, al_reg }
387#define eAXr { REP_Fixup, eAX_reg }
388
389#define cond_jump_flag { NULL, cond_jump_mode }
390#define loop_jcxz_flag { NULL, loop_jcxz_mode }
3ffd33cf 391
252b5132 392/* bits in sizeflag */
252b5132 393#define SUFFIX_ALWAYS 4
252b5132
RH		 394#define AFLAG 2
395#define DFLAG 1
396
51e7da1b
L		 397enum
398{
399 /* byte operand */
400 b_mode = 1,
401 /* byte operand with operand swapped */
3873ba12 402 b_swap_mode,
51e7da1b 403 /* operand size depends on prefixes */
3873ba12 404 v_mode,
51e7da1b 405 /* operand size depends on prefixes with operand swapped */
3873ba12 406 v_swap_mode,
51e7da1b 407 /* word operand */
3873ba12 408 w_mode,
51e7da1b 409 /* double word operand */
3873ba12 410 d_mode,
51e7da1b 411 /* double word operand with operand swapped */
3873ba12 412 d_swap_mode,
51e7da1b 413 /* quad word operand */
3873ba12 414 q_mode,
51e7da1b 415 /* quad word operand with operand swapped */
3873ba12 416 q_swap_mode,
51e7da1b 417 /* ten-byte operand */
3873ba12 418 t_mode,
51e7da1b 419 /* 16-byte XMM or 32-byte YMM operand */
3873ba12 420 x_mode,
51e7da1b 421 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
3873ba12 422 x_swap_mode,
51e7da1b 423 /* 16-byte XMM operand */
3873ba12 424 xmm_mode,
51e7da1b 425 /* 16-byte XMM or quad word operand */
3873ba12 426 xmmq_mode,
51e7da1b 427 /* 32-byte YMM or quad word operand */
3873ba12 428 ymmq_mode,
51e7da1b 429 /* d_mode in 32bit, q_mode in 64bit mode. */
3873ba12 430 m_mode,
51e7da1b 431 /* pair of v_mode operands */
3873ba12
L		 432 a_mode,
433 cond_jump_mode,
434 loop_jcxz_mode,
51e7da1b 435 /* operand size depends on REX prefixes. */
3873ba12 436 dq_mode,
51e7da1b 437 /* registers like dq_mode, memory like w_mode. */
3873ba12 438 dqw_mode,
51e7da1b 439 /* 4- or 6-byte pointer operand */
3873ba12
L		 440 f_mode,
441 const_1_mode,
51e7da1b 442 /* v_mode for stack-related opcodes. */
3873ba12 443 stack_v_mode,
51e7da1b 444 /* non-quad operand size depends on prefixes */
3873ba12 445 z_mode,
51e7da1b 446 /* 16-byte operand */
3873ba12 447 o_mode,
51e7da1b 448 /* registers like dq_mode, memory like b_mode. */
3873ba12 449 dqb_mode,
51e7da1b 450 /* registers like dq_mode, memory like d_mode. */
3873ba12 451 dqd_mode,
51e7da1b 452 /* normal vex mode */
3873ba12 453 vex_mode,
51e7da1b 454 /* 128bit vex mode */
3873ba12 455 vex128_mode,
51e7da1b 456 /* 256bit vex mode */
3873ba12 457 vex256_mode,
51e7da1b 458 /* operand size depends on the VEX.W bit. */
3873ba12 459 vex_w_dq_mode,
d55ee72f 460
3873ba12
L		 461 es_reg,
462 cs_reg,
463 ss_reg,
464 ds_reg,
465 fs_reg,
466 gs_reg,
d55ee72f 467
3873ba12
L		 468 eAX_reg,
469 eCX_reg,
470 eDX_reg,
471 eBX_reg,
472 eSP_reg,
473 eBP_reg,
474 eSI_reg,
475 eDI_reg,
d55ee72f 476
3873ba12
L		 477 al_reg,
478 cl_reg,
479 dl_reg,
480 bl_reg,
481 ah_reg,
482 ch_reg,
483 dh_reg,
484 bh_reg,
d55ee72f 485
3873ba12
L		 486 ax_reg,
487 cx_reg,
488 dx_reg,
489 bx_reg,
490 sp_reg,
491 bp_reg,
492 si_reg,
493 di_reg,
d55ee72f 494
3873ba12
L		 495 rAX_reg,
496 rCX_reg,
497 rDX_reg,
498 rBX_reg,
499 rSP_reg,
500 rBP_reg,
501 rSI_reg,
502 rDI_reg,
d55ee72f 503
3873ba12
L		 504 z_mode_ax_reg,
505 indir_dx_reg
51e7da1b 506};
252b5132 507
51e7da1b
L		 508enum
509{
510 FLOATCODE = 1,
3873ba12
L		 511 USE_REG_TABLE,
512 USE_MOD_TABLE,
513 USE_RM_TABLE,
514 USE_PREFIX_TABLE,
515 USE_X86_64_TABLE,
516 USE_3BYTE_TABLE,
517 USE_VEX_C4_TABLE,
518 USE_VEX_C5_TABLE,
519 USE_VEX_LEN_TABLE
51e7da1b 520};
6439fc28 521
1ceb70f8 522#define FLOAT NULL, { { NULL, FLOATCODE } }
4efba78c 523
4e7d34a6 524#define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
1ceb70f8
L		 525#define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
526#define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
527#define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
528#define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
4e7d34a6
L		 529#define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
530#define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
c0f3af97
L		 531#define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
532#define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
533#define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
1ceb70f8 534
51e7da1b
L		 535enum
536{
537 REG_80 = 0,
3873ba12
L		 538 REG_81,
539 REG_82,
540 REG_8F,
541 REG_C0,
542 REG_C1,
543 REG_C6,
544 REG_C7,
545 REG_D0,
546 REG_D1,
547 REG_D2,
548 REG_D3,
549 REG_F6,
550 REG_F7,
551 REG_FE,
552 REG_FF,
553 REG_0F00,
554 REG_0F01,
555 REG_0F0D,
556 REG_0F18,
557 REG_0F71,
558 REG_0F72,
559 REG_0F73,
560 REG_0FA6,
561 REG_0FA7,
562 REG_0FAE,
563 REG_0FBA,
564 REG_0FC7,
565 REG_VEX_71,
566 REG_VEX_72,
567 REG_VEX_73,
568 REG_VEX_AE
51e7da1b 569};
1ceb70f8 570
51e7da1b
L		 571enum
572{
573 MOD_8D = 0,
3873ba12
L		 574 MOD_0F01_REG_0,
575 MOD_0F01_REG_1,
576 MOD_0F01_REG_2,
577 MOD_0F01_REG_3,
578 MOD_0F01_REG_7,
579 MOD_0F12_PREFIX_0,
580 MOD_0F13,
581 MOD_0F16_PREFIX_0,
582 MOD_0F17,
583 MOD_0F18_REG_0,
584 MOD_0F18_REG_1,
585 MOD_0F18_REG_2,
586 MOD_0F18_REG_3,
587 MOD_0F20,
588 MOD_0F21,
589 MOD_0F22,
590 MOD_0F23,
591 MOD_0F24,
592 MOD_0F26,
593 MOD_0F2B_PREFIX_0,
594 MOD_0F2B_PREFIX_1,
595 MOD_0F2B_PREFIX_2,
596 MOD_0F2B_PREFIX_3,
597 MOD_0F51,
598 MOD_0F71_REG_2,
599 MOD_0F71_REG_4,
600 MOD_0F71_REG_6,
601 MOD_0F72_REG_2,
602 MOD_0F72_REG_4,
603 MOD_0F72_REG_6,
604 MOD_0F73_REG_2,
605 MOD_0F73_REG_3,
606 MOD_0F73_REG_6,
607 MOD_0F73_REG_7,
608 MOD_0FAE_REG_0,
609 MOD_0FAE_REG_1,
610 MOD_0FAE_REG_2,
611 MOD_0FAE_REG_3,
612 MOD_0FAE_REG_4,
613 MOD_0FAE_REG_5,
614 MOD_0FAE_REG_6,
615 MOD_0FAE_REG_7,
616 MOD_0FB2,
617 MOD_0FB4,
618 MOD_0FB5,
619 MOD_0FC7_REG_6,
620 MOD_0FC7_REG_7,
621 MOD_0FD7,
622 MOD_0FE7_PREFIX_2,
623 MOD_0FF0_PREFIX_3,
624 MOD_0F382A_PREFIX_2,
625 MOD_62_32BIT,
626 MOD_C4_32BIT,
627 MOD_C5_32BIT,
628 MOD_VEX_12_PREFIX_0,
629 MOD_VEX_13,
630 MOD_VEX_16_PREFIX_0,
631 MOD_VEX_17,
632 MOD_VEX_2B,
633 MOD_VEX_51,
634 MOD_VEX_71_REG_2,
635 MOD_VEX_71_REG_4,
636 MOD_VEX_71_REG_6,
637 MOD_VEX_72_REG_2,
638 MOD_VEX_72_REG_4,
639 MOD_VEX_72_REG_6,
640 MOD_VEX_73_REG_2,
641 MOD_VEX_73_REG_3,
642 MOD_VEX_73_REG_6,
643 MOD_VEX_73_REG_7,
644 MOD_VEX_AE_REG_2,
645 MOD_VEX_AE_REG_3,
646 MOD_VEX_D7_PREFIX_2,
647 MOD_VEX_E7_PREFIX_2,
648 MOD_VEX_F0_PREFIX_3,
649 MOD_VEX_3818_PREFIX_2,
650 MOD_VEX_3819_PREFIX_2,
651 MOD_VEX_381A_PREFIX_2,
652 MOD_VEX_382A_PREFIX_2,
653 MOD_VEX_382C_PREFIX_2,
654 MOD_VEX_382D_PREFIX_2,
655 MOD_VEX_382E_PREFIX_2,
656 MOD_VEX_382F_PREFIX_2
51e7da1b 657};
1ceb70f8 658
51e7da1b
L		 659enum
660{
661 RM_0F01_REG_0 = 0,
3873ba12
L		 662 RM_0F01_REG_1,
663 RM_0F01_REG_2,
664 RM_0F01_REG_3,
665 RM_0F01_REG_7,
666 RM_0FAE_REG_5,
667 RM_0FAE_REG_6,
668 RM_0FAE_REG_7
51e7da1b 669};
1ceb70f8 670
51e7da1b
L		 671enum
672{
673 PREFIX_90 = 0,
3873ba12
L		 674 PREFIX_0F10,
675 PREFIX_0F11,
676 PREFIX_0F12,
677 PREFIX_0F16,
678 PREFIX_0F2A,
679 PREFIX_0F2B,
680 PREFIX_0F2C,
681 PREFIX_0F2D,
682 PREFIX_0F2E,
683 PREFIX_0F2F,
684 PREFIX_0F51,
685 PREFIX_0F52,
686 PREFIX_0F53,
687 PREFIX_0F58,
688 PREFIX_0F59,
689 PREFIX_0F5A,
690 PREFIX_0F5B,
691 PREFIX_0F5C,
692 PREFIX_0F5D,
693 PREFIX_0F5E,
694 PREFIX_0F5F,
695 PREFIX_0F60,
696 PREFIX_0F61,
697 PREFIX_0F62,
698 PREFIX_0F6C,
699 PREFIX_0F6D,
700 PREFIX_0F6F,
701 PREFIX_0F70,
702 PREFIX_0F73_REG_3,
703 PREFIX_0F73_REG_7,
704 PREFIX_0F78,
705 PREFIX_0F79,
706 PREFIX_0F7C,
707 PREFIX_0F7D,
708 PREFIX_0F7E,
709 PREFIX_0F7F,
710 PREFIX_0FB8,
711 PREFIX_0FBD,
712 PREFIX_0FC2,
713 PREFIX_0FC3,
714 PREFIX_0FC7_REG_6,
715 PREFIX_0FD0,
716 PREFIX_0FD6,
717 PREFIX_0FE6,
718 PREFIX_0FE7,
719 PREFIX_0FF0,
720 PREFIX_0FF7,
721 PREFIX_0F3810,
722 PREFIX_0F3814,
723 PREFIX_0F3815,
724 PREFIX_0F3817,
725 PREFIX_0F3820,
726 PREFIX_0F3821,
727 PREFIX_0F3822,
728 PREFIX_0F3823,
729 PREFIX_0F3824,
730 PREFIX_0F3825,
731 PREFIX_0F3828,
732 PREFIX_0F3829,
733 PREFIX_0F382A,
734 PREFIX_0F382B,
735 PREFIX_0F3830,
736 PREFIX_0F3831,
737 PREFIX_0F3832,
738 PREFIX_0F3833,
739 PREFIX_0F3834,
740 PREFIX_0F3835,
741 PREFIX_0F3837,
742 PREFIX_0F3838,
743 PREFIX_0F3839,
744 PREFIX_0F383A,
745 PREFIX_0F383B,
746 PREFIX_0F383C,
747 PREFIX_0F383D,
748 PREFIX_0F383E,
749 PREFIX_0F383F,
750 PREFIX_0F3840,
751 PREFIX_0F3841,
752 PREFIX_0F3880,
753 PREFIX_0F3881,
754 PREFIX_0F38DB,
755 PREFIX_0F38DC,
756 PREFIX_0F38DD,
757 PREFIX_0F38DE,
758 PREFIX_0F38DF,
759 PREFIX_0F38F0,
760 PREFIX_0F38F1,
761 PREFIX_0F3A08,
762 PREFIX_0F3A09,
763 PREFIX_0F3A0A,
764 PREFIX_0F3A0B,
765 PREFIX_0F3A0C,
766 PREFIX_0F3A0D,
767 PREFIX_0F3A0E,
768 PREFIX_0F3A14,
769 PREFIX_0F3A15,
770 PREFIX_0F3A16,
771 PREFIX_0F3A17,
772 PREFIX_0F3A20,
773 PREFIX_0F3A21,
774 PREFIX_0F3A22,
775 PREFIX_0F3A40,
776 PREFIX_0F3A41,
777 PREFIX_0F3A42,
778 PREFIX_0F3A44,
779 PREFIX_0F3A60,
780 PREFIX_0F3A61,
781 PREFIX_0F3A62,
782 PREFIX_0F3A63,
783 PREFIX_0F3ADF,
784 PREFIX_VEX_10,
785 PREFIX_VEX_11,
786 PREFIX_VEX_12,
787 PREFIX_VEX_16,
788 PREFIX_VEX_2A,
789 PREFIX_VEX_2C,
790 PREFIX_VEX_2D,
791 PREFIX_VEX_2E,
792 PREFIX_VEX_2F,
793 PREFIX_VEX_51,
794 PREFIX_VEX_52,
795 PREFIX_VEX_53,
796 PREFIX_VEX_58,
797 PREFIX_VEX_59,
798 PREFIX_VEX_5A,
799 PREFIX_VEX_5B,
800 PREFIX_VEX_5C,
801 PREFIX_VEX_5D,
802 PREFIX_VEX_5E,
803 PREFIX_VEX_5F,
804 PREFIX_VEX_60,
805 PREFIX_VEX_61,
806 PREFIX_VEX_62,
807 PREFIX_VEX_63,
808 PREFIX_VEX_64,
809 PREFIX_VEX_65,
810 PREFIX_VEX_66,
811 PREFIX_VEX_67,
812 PREFIX_VEX_68,
813 PREFIX_VEX_69,
814 PREFIX_VEX_6A,
815 PREFIX_VEX_6B,
816 PREFIX_VEX_6C,
817 PREFIX_VEX_6D,
818 PREFIX_VEX_6E,
819 PREFIX_VEX_6F,
820 PREFIX_VEX_70,
821 PREFIX_VEX_71_REG_2,
822 PREFIX_VEX_71_REG_4,
823 PREFIX_VEX_71_REG_6,
824 PREFIX_VEX_72_REG_2,
825 PREFIX_VEX_72_REG_4,
826 PREFIX_VEX_72_REG_6,
827 PREFIX_VEX_73_REG_2,
828 PREFIX_VEX_73_REG_3,
829 PREFIX_VEX_73_REG_6,
830 PREFIX_VEX_73_REG_7,
831 PREFIX_VEX_74,
832 PREFIX_VEX_75,
833 PREFIX_VEX_76,
834 PREFIX_VEX_77,
835 PREFIX_VEX_7C,
836 PREFIX_VEX_7D,
837 PREFIX_VEX_7E,
838 PREFIX_VEX_7F,
839 PREFIX_VEX_C2,
840 PREFIX_VEX_C4,
841 PREFIX_VEX_C5,
842 PREFIX_VEX_D0,
843 PREFIX_VEX_D1,
844 PREFIX_VEX_D2,
845 PREFIX_VEX_D3,
846 PREFIX_VEX_D4,
847 PREFIX_VEX_D5,
848 PREFIX_VEX_D6,
849 PREFIX_VEX_D7,
850 PREFIX_VEX_D8,
851 PREFIX_VEX_D9,
852 PREFIX_VEX_DA,
853 PREFIX_VEX_DB,
854 PREFIX_VEX_DC,
855 PREFIX_VEX_DD,
856 PREFIX_VEX_DE,
857 PREFIX_VEX_DF,
858 PREFIX_VEX_E0,
859 PREFIX_VEX_E1,
860 PREFIX_VEX_E2,
861 PREFIX_VEX_E3,
862 PREFIX_VEX_E4,
863 PREFIX_VEX_E5,
864 PREFIX_VEX_E6,
865 PREFIX_VEX_E7,
866 PREFIX_VEX_E8,
867 PREFIX_VEX_E9,
868 PREFIX_VEX_EA,
869 PREFIX_VEX_EB,
870 PREFIX_VEX_EC,
871 PREFIX_VEX_ED,
872 PREFIX_VEX_EE,
873 PREFIX_VEX_EF,
874 PREFIX_VEX_F0,
875 PREFIX_VEX_F1,
876 PREFIX_VEX_F2,
877 PREFIX_VEX_F3,
878 PREFIX_VEX_F4,
879 PREFIX_VEX_F5,
880 PREFIX_VEX_F6,
881 PREFIX_VEX_F7,
882 PREFIX_VEX_F8,
883 PREFIX_VEX_F9,
884 PREFIX_VEX_FA,
885 PREFIX_VEX_FB,
886 PREFIX_VEX_FC,
887 PREFIX_VEX_FD,
888 PREFIX_VEX_FE,
889 PREFIX_VEX_3800,
890 PREFIX_VEX_3801,
891 PREFIX_VEX_3802,
892 PREFIX_VEX_3803,
893 PREFIX_VEX_3804,
894 PREFIX_VEX_3805,
895 PREFIX_VEX_3806,
896 PREFIX_VEX_3807,
897 PREFIX_VEX_3808,
898 PREFIX_VEX_3809,
899 PREFIX_VEX_380A,
900 PREFIX_VEX_380B,
901 PREFIX_VEX_380C,
902 PREFIX_VEX_380D,
903 PREFIX_VEX_380E,
904 PREFIX_VEX_380F,
905 PREFIX_VEX_3817,
906 PREFIX_VEX_3818,
907 PREFIX_VEX_3819,
908 PREFIX_VEX_381A,
909 PREFIX_VEX_381C,
910 PREFIX_VEX_381D,
911 PREFIX_VEX_381E,
912 PREFIX_VEX_3820,
913 PREFIX_VEX_3821,
914 PREFIX_VEX_3822,
915 PREFIX_VEX_3823,
916 PREFIX_VEX_3824,
917 PREFIX_VEX_3825,
918 PREFIX_VEX_3828,
919 PREFIX_VEX_3829,
920 PREFIX_VEX_382A,
921 PREFIX_VEX_382B,
922 PREFIX_VEX_382C,
923 PREFIX_VEX_382D,
924 PREFIX_VEX_382E,
925 PREFIX_VEX_382F,
926 PREFIX_VEX_3830,
927 PREFIX_VEX_3831,
928 PREFIX_VEX_3832,
929 PREFIX_VEX_3833,
930 PREFIX_VEX_3834,
931 PREFIX_VEX_3835,
932 PREFIX_VEX_3837,
933 PREFIX_VEX_3838,
934 PREFIX_VEX_3839,
935 PREFIX_VEX_383A,
936 PREFIX_VEX_383B,
937 PREFIX_VEX_383C,
938 PREFIX_VEX_383D,
939 PREFIX_VEX_383E,
940 PREFIX_VEX_383F,
941 PREFIX_VEX_3840,
942 PREFIX_VEX_3841,
943 PREFIX_VEX_3896,
944 PREFIX_VEX_3897,
945 PREFIX_VEX_3898,
946 PREFIX_VEX_3899,
947 PREFIX_VEX_389A,
948 PREFIX_VEX_389B,
949 PREFIX_VEX_389C,
950 PREFIX_VEX_389D,
951 PREFIX_VEX_389E,
952 PREFIX_VEX_389F,
953 PREFIX_VEX_38A6,
954 PREFIX_VEX_38A7,
955 PREFIX_VEX_38A8,
956 PREFIX_VEX_38A9,
957 PREFIX_VEX_38AA,
958 PREFIX_VEX_38AB,
959 PREFIX_VEX_38AC,
960 PREFIX_VEX_38AD,
961 PREFIX_VEX_38AE,
962 PREFIX_VEX_38AF,
963 PREFIX_VEX_38B6,
964 PREFIX_VEX_38B7,
965 PREFIX_VEX_38B8,
966 PREFIX_VEX_38B9,
967 PREFIX_VEX_38BA,
968 PREFIX_VEX_38BB,
969 PREFIX_VEX_38BC,
970 PREFIX_VEX_38BD,
971 PREFIX_VEX_38BE,
972 PREFIX_VEX_38BF,
973 PREFIX_VEX_38DB,
974 PREFIX_VEX_38DC,
975 PREFIX_VEX_38DD,
976 PREFIX_VEX_38DE,
977 PREFIX_VEX_38DF,
978 PREFIX_VEX_3A04,
979 PREFIX_VEX_3A05,
980 PREFIX_VEX_3A06,
981 PREFIX_VEX_3A08,
982 PREFIX_VEX_3A09,
983 PREFIX_VEX_3A0A,
984 PREFIX_VEX_3A0B,
985 PREFIX_VEX_3A0C,
986 PREFIX_VEX_3A0D,
987 PREFIX_VEX_3A0E,
988 PREFIX_VEX_3A0F,
989 PREFIX_VEX_3A14,
990 PREFIX_VEX_3A15,
991 PREFIX_VEX_3A16,
992 PREFIX_VEX_3A17,
993 PREFIX_VEX_3A18,
994 PREFIX_VEX_3A19,
995 PREFIX_VEX_3A20,
996 PREFIX_VEX_3A21,
997 PREFIX_VEX_3A22,
998 PREFIX_VEX_3A40,
999 PREFIX_VEX_3A41,
1000 PREFIX_VEX_3A42,
1001 PREFIX_VEX_3A44,
1002 PREFIX_VEX_3A4A,
1003 PREFIX_VEX_3A4B,
1004 PREFIX_VEX_3A4C,
1005 PREFIX_VEX_3A5C,
1006 PREFIX_VEX_3A5D,
1007 PREFIX_VEX_3A5E,
1008 PREFIX_VEX_3A5F,
1009 PREFIX_VEX_3A60,
1010 PREFIX_VEX_3A61,
1011 PREFIX_VEX_3A62,
1012 PREFIX_VEX_3A63,
1013 PREFIX_VEX_3A68,
1014 PREFIX_VEX_3A69,
1015 PREFIX_VEX_3A6A,
1016 PREFIX_VEX_3A6B,
1017 PREFIX_VEX_3A6C,
1018 PREFIX_VEX_3A6D,
1019 PREFIX_VEX_3A6E,
1020 PREFIX_VEX_3A6F,
1021 PREFIX_VEX_3A78,
1022 PREFIX_VEX_3A79,
1023 PREFIX_VEX_3A7A,
1024 PREFIX_VEX_3A7B,
1025 PREFIX_VEX_3A7C,
1026 PREFIX_VEX_3A7D,
1027 PREFIX_VEX_3A7E,
1028 PREFIX_VEX_3A7F,
1029 PREFIX_VEX_3ADF
51e7da1b 1030};
4e7d34a6 1031
51e7da1b
L		 1032enum
1033{
1034 X86_64_06 = 0,
3873ba12
L		 1035 X86_64_07,
1036 X86_64_0D,
1037 X86_64_16,
1038 X86_64_17,
1039 X86_64_1E,
1040 X86_64_1F,
1041 X86_64_27,
1042 X86_64_2F,
1043 X86_64_37,
1044 X86_64_3F,
1045 X86_64_60,
1046 X86_64_61,
1047 X86_64_62,
1048 X86_64_63,
1049 X86_64_6D,
1050 X86_64_6F,
1051 X86_64_9A,
1052 X86_64_C4,
1053 X86_64_C5,
1054 X86_64_CE,
1055 X86_64_D4,
1056 X86_64_D5,
1057 X86_64_EA,
1058 X86_64_0F01_REG_0,
1059 X86_64_0F01_REG_1,
1060 X86_64_0F01_REG_2,
1061 X86_64_0F01_REG_3
51e7da1b 1062};
4e7d34a6 1063
51e7da1b
L		 1064enum
1065{
1066 THREE_BYTE_0F38 = 0,
3873ba12
L		 1067 THREE_BYTE_0F3A,
1068 THREE_BYTE_0F7A
51e7da1b 1069};
4e7d34a6 1070
51e7da1b
L		 1071enum
1072{
1073 VEX_0F = 0,
3873ba12
L		 1074 VEX_0F38,
1075 VEX_0F3A
51e7da1b 1076};
c0f3af97 1077
51e7da1b
L		 1078enum
1079{
1080 VEX_LEN_10_P_1 = 0,
3873ba12
L		 1081 VEX_LEN_10_P_3,
1082 VEX_LEN_11_P_1,
1083 VEX_LEN_11_P_3,
1084 VEX_LEN_12_P_0_M_0,
1085 VEX_LEN_12_P_0_M_1,
1086 VEX_LEN_12_P_2,
1087 VEX_LEN_13_M_0,
1088 VEX_LEN_16_P_0_M_0,
1089 VEX_LEN_16_P_0_M_1,
1090 VEX_LEN_16_P_2,
1091 VEX_LEN_17_M_0,
1092 VEX_LEN_2A_P_1,
1093 VEX_LEN_2A_P_3,
1094 VEX_LEN_2C_P_1,
1095 VEX_LEN_2C_P_3,
1096 VEX_LEN_2D_P_1,
1097 VEX_LEN_2D_P_3,
1098 VEX_LEN_2E_P_0,
1099 VEX_LEN_2E_P_2,
1100 VEX_LEN_2F_P_0,
1101 VEX_LEN_2F_P_2,
1102 VEX_LEN_51_P_1,
1103 VEX_LEN_51_P_3,
1104 VEX_LEN_52_P_1,
1105 VEX_LEN_53_P_1,
1106 VEX_LEN_58_P_1,
1107 VEX_LEN_58_P_3,
1108 VEX_LEN_59_P_1,
1109 VEX_LEN_59_P_3,
1110 VEX_LEN_5A_P_1,
1111 VEX_LEN_5A_P_3,
1112 VEX_LEN_5C_P_1,
1113 VEX_LEN_5C_P_3,
1114 VEX_LEN_5D_P_1,
1115 VEX_LEN_5D_P_3,
1116 VEX_LEN_5E_P_1,
1117 VEX_LEN_5E_P_3,
1118 VEX_LEN_5F_P_1,
1119 VEX_LEN_5F_P_3,
1120 VEX_LEN_60_P_2,
1121 VEX_LEN_61_P_2,
1122 VEX_LEN_62_P_2,
1123 VEX_LEN_63_P_2,
1124 VEX_LEN_64_P_2,
1125 VEX_LEN_65_P_2,
1126 VEX_LEN_66_P_2,
1127 VEX_LEN_67_P_2,
1128 VEX_LEN_68_P_2,
1129 VEX_LEN_69_P_2,
1130 VEX_LEN_6A_P_2,
1131 VEX_LEN_6B_P_2,
1132 VEX_LEN_6C_P_2,
1133 VEX_LEN_6D_P_2,
1134 VEX_LEN_6E_P_2,
1135 VEX_LEN_70_P_1,
1136 VEX_LEN_70_P_2,
1137 VEX_LEN_70_P_3,
1138 VEX_LEN_71_R_2_P_2,
1139 VEX_LEN_71_R_4_P_2,
1140 VEX_LEN_71_R_6_P_2,
1141 VEX_LEN_72_R_2_P_2,
1142 VEX_LEN_72_R_4_P_2,
1143 VEX_LEN_72_R_6_P_2,
1144 VEX_LEN_73_R_2_P_2,
1145 VEX_LEN_73_R_3_P_2,
1146 VEX_LEN_73_R_6_P_2,
1147 VEX_LEN_73_R_7_P_2,
1148 VEX_LEN_74_P_2,
1149 VEX_LEN_75_P_2,
1150 VEX_LEN_76_P_2,
1151 VEX_LEN_7E_P_1,
1152 VEX_LEN_7E_P_2,
1153 VEX_LEN_AE_R_2_M_0,
1154 VEX_LEN_AE_R_3_M_0,
1155 VEX_LEN_C2_P_1,
1156 VEX_LEN_C2_P_3,
1157 VEX_LEN_C4_P_2,
1158 VEX_LEN_C5_P_2,
1159 VEX_LEN_D1_P_2,
1160 VEX_LEN_D2_P_2,
1161 VEX_LEN_D3_P_2,
1162 VEX_LEN_D4_P_2,
1163 VEX_LEN_D5_P_2,
1164 VEX_LEN_D6_P_2,
1165 VEX_LEN_D7_P_2_M_1,
1166 VEX_LEN_D8_P_2,
1167 VEX_LEN_D9_P_2,
1168 VEX_LEN_DA_P_2,
1169 VEX_LEN_DB_P_2,
1170 VEX_LEN_DC_P_2,
1171 VEX_LEN_DD_P_2,
1172 VEX_LEN_DE_P_2,
1173 VEX_LEN_DF_P_2,
1174 VEX_LEN_E0_P_2,
1175 VEX_LEN_E1_P_2,
1176 VEX_LEN_E2_P_2,
1177 VEX_LEN_E3_P_2,
1178 VEX_LEN_E4_P_2,
1179 VEX_LEN_E5_P_2,
1180 VEX_LEN_E8_P_2,
1181 VEX_LEN_E9_P_2,
1182 VEX_LEN_EA_P_2,
1183 VEX_LEN_EB_P_2,
1184 VEX_LEN_EC_P_2,
1185 VEX_LEN_ED_P_2,
1186 VEX_LEN_EE_P_2,
1187 VEX_LEN_EF_P_2,
1188 VEX_LEN_F1_P_2,
1189 VEX_LEN_F2_P_2,
1190 VEX_LEN_F3_P_2,
1191 VEX_LEN_F4_P_2,
1192 VEX_LEN_F5_P_2,
1193 VEX_LEN_F6_P_2,
1194 VEX_LEN_F7_P_2,
1195 VEX_LEN_F8_P_2,
1196 VEX_LEN_F9_P_2,
1197 VEX_LEN_FA_P_2,
1198 VEX_LEN_FB_P_2,
1199 VEX_LEN_FC_P_2,
1200 VEX_LEN_FD_P_2,
1201 VEX_LEN_FE_P_2,
1202 VEX_LEN_3800_P_2,
1203 VEX_LEN_3801_P_2,
1204 VEX_LEN_3802_P_2,
1205 VEX_LEN_3803_P_2,
1206 VEX_LEN_3804_P_2,
1207 VEX_LEN_3805_P_2,
1208 VEX_LEN_3806_P_2,
1209 VEX_LEN_3807_P_2,
1210 VEX_LEN_3808_P_2,
1211 VEX_LEN_3809_P_2,
1212 VEX_LEN_380A_P_2,
1213 VEX_LEN_380B_P_2,
1214 VEX_LEN_3819_P_2_M_0,
1215 VEX_LEN_381A_P_2_M_0,
1216 VEX_LEN_381C_P_2,
1217 VEX_LEN_381D_P_2,
1218 VEX_LEN_381E_P_2,
1219 VEX_LEN_3820_P_2,
1220 VEX_LEN_3821_P_2,
1221 VEX_LEN_3822_P_2,
1222 VEX_LEN_3823_P_2,
1223 VEX_LEN_3824_P_2,
1224 VEX_LEN_3825_P_2,
1225 VEX_LEN_3828_P_2,
1226 VEX_LEN_3829_P_2,
1227 VEX_LEN_382A_P_2_M_0,
1228 VEX_LEN_382B_P_2,
1229 VEX_LEN_3830_P_2,
1230 VEX_LEN_3831_P_2,
1231 VEX_LEN_3832_P_2,
1232 VEX_LEN_3833_P_2,
1233 VEX_LEN_3834_P_2,
1234 VEX_LEN_3835_P_2,
1235 VEX_LEN_3837_P_2,
1236 VEX_LEN_3838_P_2,
1237 VEX_LEN_3839_P_2,
1238 VEX_LEN_383A_P_2,
1239 VEX_LEN_383B_P_2,
1240 VEX_LEN_383C_P_2,
1241 VEX_LEN_383D_P_2,
1242 VEX_LEN_383E_P_2,
1243 VEX_LEN_383F_P_2,
1244 VEX_LEN_3840_P_2,
1245 VEX_LEN_3841_P_2,
1246 VEX_LEN_38DB_P_2,
1247 VEX_LEN_38DC_P_2,
1248 VEX_LEN_38DD_P_2,
1249 VEX_LEN_38DE_P_2,
1250 VEX_LEN_38DF_P_2,
1251 VEX_LEN_3A06_P_2,
1252 VEX_LEN_3A0A_P_2,
1253 VEX_LEN_3A0B_P_2,
1254 VEX_LEN_3A0E_P_2,
1255 VEX_LEN_3A0F_P_2,
1256 VEX_LEN_3A14_P_2,
1257 VEX_LEN_3A15_P_2,
1258 VEX_LEN_3A16_P_2,
1259 VEX_LEN_3A17_P_2,
1260 VEX_LEN_3A18_P_2,
1261 VEX_LEN_3A19_P_2,
1262 VEX_LEN_3A20_P_2,
1263 VEX_LEN_3A21_P_2,
1264 VEX_LEN_3A22_P_2,
1265 VEX_LEN_3A41_P_2,
1266 VEX_LEN_3A42_P_2,
1267 VEX_LEN_3A44_P_2,
1268 VEX_LEN_3A4C_P_2,
1269 VEX_LEN_3A60_P_2,
1270 VEX_LEN_3A61_P_2,
1271 VEX_LEN_3A62_P_2,
1272 VEX_LEN_3A63_P_2,
1273 VEX_LEN_3A6A_P_2,
1274 VEX_LEN_3A6B_P_2,
1275 VEX_LEN_3A6E_P_2,
1276 VEX_LEN_3A6F_P_2,
1277 VEX_LEN_3A7A_P_2,
1278 VEX_LEN_3A7B_P_2,
1279 VEX_LEN_3A7E_P_2,
1280 VEX_LEN_3A7F_P_2,
1281 VEX_LEN_3ADF_P_2
51e7da1b 1282};
c0f3af97 1283
26ca5450 1284typedef void (*op_rtn) (int bytemode, int sizeflag);
252b5132
RH		 1285
1286struct dis386 {
2da11e11 1287 const char *name;
ce518a5f
L		 1288 struct
1289 {
1290 op_rtn rtn;
1291 int bytemode;
1292 } op[MAX_OPERANDS];
252b5132
RH		 1293};
1294
1295/* Upper case letters in the instruction names here are macros.
1296 'A' => print 'b' if no register operands or suffix_always is true
1297 'B' => print 'b' if suffix_always is true
9306ca4a 1298 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
98b528ac 1299 size prefix
ed7841b3 1300 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
98b528ac 1301 suffix_always is true
252b5132 1302 'E' => print 'e' if 32-bit form of jcxz
3ffd33cf 1303 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
52fd6d94 1304 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
5dd0794d 1305 'H' => print ",pt" or ",pn" branch hint
9306ca4a 1306 'I' => honor following macro letter even in Intel mode (implemented only
98b528ac 1307 for some of the macro letters)
9306ca4a 1308 'J' => print 'l'
42903f7f 1309 'K' => print 'd' or 'q' if rex prefix is present.
252b5132 1310 'L' => print 'l' if suffix_always is true
9d141669 1311 'M' => print 'r' if intel_mnemonic is false.
252b5132 1312 'N' => print 'n' if instruction has no wait "prefix"
a35ca55a 1313 'O' => print 'd' or 'o' (or 'q' in Intel mode)
52b15da3 1314 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
98b528ac
L		 1315 or suffix_always is true. print 'q' if rex prefix is present.
1316 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1317 is true
a35ca55a 1318 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
52b15da3 1319 'S' => print 'w', 'l' or 'q' if suffix_always is true
6439fc28
AM		 1320 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1321 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1a114b12 1322 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
a35ca55a 1323 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
9306ca4a 1324 'X' => print 's', 'd' depending on data16 prefix (for XMM)
8a72226a
L		 1325 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1326 suffix_always is true.
6dd5059a 1327 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
9d141669 1328 '!' => change condition from true to false or from false to true.
98b528ac
L		 1329 '%' => add 1 upper case letter to the macro.
1330
1331 2 upper case letter macros:
c0f3af97
L		 1332 "XY" => print 'x' or 'y' if no register operands or suffix_always
1333 is true.
4b06377f
L		 1334 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1335 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
98b528ac 1336 or suffix_always is true
4b06377f
L		 1337 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1338 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1339 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
52b15da3 1340
6439fc28
AM		 1341 Many of the above letters print nothing in Intel mode. See "putop"
1342 for the details.
52b15da3 1343
6439fc28 1344 Braces '{' and '}', and vertical bars '|', indicate alternative
7c52e0e8 1345 mnemonic strings for AT&T and Intel. */
252b5132 1346
6439fc28 1347static const struct dis386 dis386[] = {
252b5132 1348 /* 00 */
ce518a5f
L		 1349 { "addB", { Eb, Gb } },
1350 { "addS", { Ev, Gv } },
c7532693
L		 1351 { "addB", { Gb, EbS } },
1352 { "addS", { Gv, EvS } },
ce518a5f
L		 1353 { "addB", { AL, Ib } },
1354 { "addS", { eAX, Iv } },
4e7d34a6
L		 1355 { X86_64_TABLE (X86_64_06) },
1356 { X86_64_TABLE (X86_64_07) },
252b5132 1357 /* 08 */
ce518a5f
L		 1358 { "orB", { Eb, Gb } },
1359 { "orS", { Ev, Gv } },
c7532693
L		 1360 { "orB", { Gb, EbS } },
1361 { "orS", { Gv, EvS } },
ce518a5f
L		 1362 { "orB", { AL, Ib } },
1363 { "orS", { eAX, Iv } },
4e7d34a6 1364 { X86_64_TABLE (X86_64_0D) },
ce518a5f 1365 { "(bad)", { XX } }, /* 0x0f extended opcode escape */
252b5132 1366 /* 10 */
ce518a5f
L		 1367 { "adcB", { Eb, Gb } },
1368 { "adcS", { Ev, Gv } },
c7532693
L		 1369 { "adcB", { Gb, EbS } },
1370 { "adcS", { Gv, EvS } },
ce518a5f
L		 1371 { "adcB", { AL, Ib } },
1372 { "adcS", { eAX, Iv } },
4e7d34a6
L		 1373 { X86_64_TABLE (X86_64_16) },
1374 { X86_64_TABLE (X86_64_17) },
252b5132 1375 /* 18 */
ce518a5f
L		 1376 { "sbbB", { Eb, Gb } },
1377 { "sbbS", { Ev, Gv } },
c7532693
L		 1378 { "sbbB", { Gb, EbS } },
1379 { "sbbS", { Gv, EvS } },
ce518a5f
L		 1380 { "sbbB", { AL, Ib } },
1381 { "sbbS", { eAX, Iv } },
4e7d34a6
L		 1382 { X86_64_TABLE (X86_64_1E) },
1383 { X86_64_TABLE (X86_64_1F) },
252b5132 1384 /* 20 */
ce518a5f
L		 1385 { "andB", { Eb, Gb } },
1386 { "andS", { Ev, Gv } },
c7532693
L		 1387 { "andB", { Gb, EbS } },
1388 { "andS", { Gv, EvS } },
ce518a5f
L		 1389 { "andB", { AL, Ib } },
1390 { "andS", { eAX, Iv } },
1391 { "(bad)", { XX } }, /* SEG ES prefix */
4e7d34a6 1392 { X86_64_TABLE (X86_64_27) },
252b5132 1393 /* 28 */
ce518a5f
L		 1394 { "subB", { Eb, Gb } },
1395 { "subS", { Ev, Gv } },
c7532693
L		 1396 { "subB", { Gb, EbS } },
1397 { "subS", { Gv, EvS } },
ce518a5f
L		 1398 { "subB", { AL, Ib } },
1399 { "subS", { eAX, Iv } },
1400 { "(bad)", { XX } }, /* SEG CS prefix */
4e7d34a6 1401 { X86_64_TABLE (X86_64_2F) },
252b5132 1402 /* 30 */
ce518a5f
L		 1403 { "xorB", { Eb, Gb } },
1404 { "xorS", { Ev, Gv } },
c7532693
L		 1405 { "xorB", { Gb, EbS } },
1406 { "xorS", { Gv, EvS } },
ce518a5f
L		 1407 { "xorB", { AL, Ib } },
1408 { "xorS", { eAX, Iv } },
1409 { "(bad)", { XX } }, /* SEG SS prefix */
4e7d34a6 1410 { X86_64_TABLE (X86_64_37) },
252b5132 1411 /* 38 */
ce518a5f
L		 1412 { "cmpB", { Eb, Gb } },
1413 { "cmpS", { Ev, Gv } },
c7532693
L		 1414 { "cmpB", { Gb, EbS } },
1415 { "cmpS", { Gv, EvS } },
ce518a5f
L		 1416 { "cmpB", { AL, Ib } },
1417 { "cmpS", { eAX, Iv } },
1418 { "(bad)", { XX } }, /* SEG DS prefix */
4e7d34a6 1419 { X86_64_TABLE (X86_64_3F) },
252b5132 1420 /* 40 */
ce518a5f
L		 1421 { "inc{S|}", { RMeAX } },
1422 { "inc{S|}", { RMeCX } },
1423 { "inc{S|}", { RMeDX } },
1424 { "inc{S|}", { RMeBX } },
1425 { "inc{S|}", { RMeSP } },
1426 { "inc{S|}", { RMeBP } },
1427 { "inc{S|}", { RMeSI } },
1428 { "inc{S|}", { RMeDI } },
252b5132 1429 /* 48 */
ce518a5f
L		 1430 { "dec{S|}", { RMeAX } },
1431 { "dec{S|}", { RMeCX } },
1432 { "dec{S|}", { RMeDX } },
1433 { "dec{S|}", { RMeBX } },
1434 { "dec{S|}", { RMeSP } },
1435 { "dec{S|}", { RMeBP } },
1436 { "dec{S|}", { RMeSI } },
1437 { "dec{S|}", { RMeDI } },
252b5132 1438 /* 50 */
ce518a5f
L		 1439 { "pushV", { RMrAX } },
1440 { "pushV", { RMrCX } },
1441 { "pushV", { RMrDX } },
1442 { "pushV", { RMrBX } },
1443 { "pushV", { RMrSP } },
1444 { "pushV", { RMrBP } },
1445 { "pushV", { RMrSI } },
1446 { "pushV", { RMrDI } },
252b5132 1447 /* 58 */
ce518a5f
L		 1448 { "popV", { RMrAX } },
1449 { "popV", { RMrCX } },
1450 { "popV", { RMrDX } },
1451 { "popV", { RMrBX } },
1452 { "popV", { RMrSP } },
1453 { "popV", { RMrBP } },
1454 { "popV", { RMrSI } },
1455 { "popV", { RMrDI } },
252b5132 1456 /* 60 */
4e7d34a6
L		 1457 { X86_64_TABLE (X86_64_60) },
1458 { X86_64_TABLE (X86_64_61) },
1459 { X86_64_TABLE (X86_64_62) },
1460 { X86_64_TABLE (X86_64_63) },
ce518a5f
L		 1461 { "(bad)", { XX } }, /* seg fs */
1462 { "(bad)", { XX } }, /* seg gs */
1463 { "(bad)", { XX } }, /* op size prefix */
1464 { "(bad)", { XX } }, /* adr size prefix */
252b5132 1465 /* 68 */
ce518a5f
L		 1466 { "pushT", { Iq } },
1467 { "imulS", { Gv, Ev, Iv } },
1468 { "pushT", { sIb } },
1469 { "imulS", { Gv, Ev, sIb } },
7c52e0e8 1470 { "ins{b|}", { Ybr, indirDX } },
4e7d34a6 1471 { X86_64_TABLE (X86_64_6D) },
7c52e0e8 1472 { "outs{b|}", { indirDXr, Xb } },
4e7d34a6 1473 { X86_64_TABLE (X86_64_6F) },
252b5132 1474 /* 70 */
ce518a5f
L		 1475 { "joH", { Jb, XX, cond_jump_flag } },
1476 { "jnoH", { Jb, XX, cond_jump_flag } },
1477 { "jbH", { Jb, XX, cond_jump_flag } },
1478 { "jaeH", { Jb, XX, cond_jump_flag } },
1479 { "jeH", { Jb, XX, cond_jump_flag } },
1480 { "jneH", { Jb, XX, cond_jump_flag } },
1481 { "jbeH", { Jb, XX, cond_jump_flag } },
1482 { "jaH", { Jb, XX, cond_jump_flag } },
252b5132 1483 /* 78 */
ce518a5f
L		 1484 { "jsH", { Jb, XX, cond_jump_flag } },
1485 { "jnsH", { Jb, XX, cond_jump_flag } },
1486 { "jpH", { Jb, XX, cond_jump_flag } },
1487 { "jnpH", { Jb, XX, cond_jump_flag } },
1488 { "jlH", { Jb, XX, cond_jump_flag } },
1489 { "jgeH", { Jb, XX, cond_jump_flag } },
1490 { "jleH", { Jb, XX, cond_jump_flag } },
1491 { "jgH", { Jb, XX, cond_jump_flag } },
252b5132 1492 /* 80 */
1ceb70f8
L		 1493 { REG_TABLE (REG_80) },
1494 { REG_TABLE (REG_81) },
ce518a5f 1495 { "(bad)", { XX } },
1ceb70f8 1496 { REG_TABLE (REG_82) },
ce518a5f
L		 1497 { "testB", { Eb, Gb } },
1498 { "testS", { Ev, Gv } },
1499 { "xchgB", { Eb, Gb } },
1500 { "xchgS", { Ev, Gv } },
252b5132 1501 /* 88 */
ce518a5f
L		 1502 { "movB", { Eb, Gb } },
1503 { "movS", { Ev, Gv } },
b6169b20
L		 1504 { "movB", { Gb, EbS } },
1505 { "movS", { Gv, EvS } },
ce518a5f 1506 { "movD", { Sv, Sw } },
1ceb70f8 1507 { MOD_TABLE (MOD_8D) },
ce518a5f 1508 { "movD", { Sw, Sv } },
1ceb70f8 1509 { REG_TABLE (REG_8F) },
252b5132 1510 /* 90 */
1ceb70f8 1511 { PREFIX_TABLE (PREFIX_90) },
ce518a5f
L		 1512 { "xchgS", { RMeCX, eAX } },
1513 { "xchgS", { RMeDX, eAX } },
1514 { "xchgS", { RMeBX, eAX } },
1515 { "xchgS", { RMeSP, eAX } },
1516 { "xchgS", { RMeBP, eAX } },
1517 { "xchgS", { RMeSI, eAX } },
1518 { "xchgS", { RMeDI, eAX } },
252b5132 1519 /* 98 */
7c52e0e8
L		 1520 { "cW{t|}R", { XX } },
1521 { "cR{t|}O", { XX } },
4e7d34a6 1522 { X86_64_TABLE (X86_64_9A) },
ce518a5f
L		 1523 { "(bad)", { XX } }, /* fwait */
1524 { "pushfT", { XX } },
1525 { "popfT", { XX } },
7c52e0e8
L		 1526 { "sahf", { XX } },
1527 { "lahf", { XX } },
252b5132 1528 /* a0 */
4b06377f
L		 1529 { "mov%LB", { AL, Ob } },
1530 { "mov%LS", { eAX, Ov } },
1531 { "mov%LB", { Ob, AL } },
1532 { "mov%LS", { Ov, eAX } },
7c52e0e8
L		 1533 { "movs{b|}", { Ybr, Xb } },
1534 { "movs{R|}", { Yvr, Xv } },
1535 { "cmps{b|}", { Xb, Yb } },
1536 { "cmps{R|}", { Xv, Yv } },
252b5132 1537 /* a8 */
ce518a5f
L		 1538 { "testB", { AL, Ib } },
1539 { "testS", { eAX, Iv } },
1540 { "stosB", { Ybr, AL } },
1541 { "stosS", { Yvr, eAX } },
1542 { "lodsB", { ALr, Xb } },
1543 { "lodsS", { eAXr, Xv } },
1544 { "scasB", { AL, Yb } },
1545 { "scasS", { eAX, Yv } },
252b5132 1546 /* b0 */
ce518a5f
L		 1547 { "movB", { RMAL, Ib } },
1548 { "movB", { RMCL, Ib } },
1549 { "movB", { RMDL, Ib } },
1550 { "movB", { RMBL, Ib } },
1551 { "movB", { RMAH, Ib } },
1552 { "movB", { RMCH, Ib } },
1553 { "movB", { RMDH, Ib } },
1554 { "movB", { RMBH, Ib } },
252b5132 1555 /* b8 */
4b06377f
L		 1556 { "mov%LV", { RMeAX, Iv64 } },
1557 { "mov%LV", { RMeCX, Iv64 } },
1558 { "mov%LV", { RMeDX, Iv64 } },
1559 { "mov%LV", { RMeBX, Iv64 } },
1560 { "mov%LV", { RMeSP, Iv64 } },
1561 { "mov%LV", { RMeBP, Iv64 } },
1562 { "mov%LV", { RMeSI, Iv64 } },
1563 { "mov%LV", { RMeDI, Iv64 } },
252b5132 1564 /* c0 */
1ceb70f8
L		 1565 { REG_TABLE (REG_C0) },
1566 { REG_TABLE (REG_C1) },
ce518a5f
L		 1567 { "retT", { Iw } },
1568 { "retT", { XX } },
4e7d34a6
L		 1569 { X86_64_TABLE (X86_64_C4) },
1570 { X86_64_TABLE (X86_64_C5) },
1ceb70f8
L		 1571 { REG_TABLE (REG_C6) },
1572 { REG_TABLE (REG_C7) },
252b5132 1573 /* c8 */
ce518a5f
L		 1574 { "enterT", { Iw, Ib } },
1575 { "leaveT", { XX } },
ddab3d59
JB		 1576 { "Jret{|f}P", { Iw } },
1577 { "Jret{|f}P", { XX } },
ce518a5f
L		 1578 { "int3", { XX } },
1579 { "int", { Ib } },
4e7d34a6 1580 { X86_64_TABLE (X86_64_CE) },
ce518a5f 1581 { "iretP", { XX } },
252b5132 1582 /* d0 */
1ceb70f8
L		 1583 { REG_TABLE (REG_D0) },
1584 { REG_TABLE (REG_D1) },
1585 { REG_TABLE (REG_D2) },
1586 { REG_TABLE (REG_D3) },
4e7d34a6
L		 1587 { X86_64_TABLE (X86_64_D4) },
1588 { X86_64_TABLE (X86_64_D5) },
ce518a5f
L		 1589 { "(bad)", { XX } },
1590 { "xlat", { DSBX } },
252b5132
RH		 1591 /* d8 */
1592 { FLOAT },
1593 { FLOAT },
1594 { FLOAT },
1595 { FLOAT },
1596 { FLOAT },
1597 { FLOAT },
1598 { FLOAT },
1599 { FLOAT },
1600 /* e0 */
ce518a5f
L		 1601 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
1602 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
1603 { "loopFH", { Jb, XX, loop_jcxz_flag } },
1604 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
1605 { "inB", { AL, Ib } },
1606 { "inG", { zAX, Ib } },
1607 { "outB", { Ib, AL } },
1608 { "outG", { Ib, zAX } },
252b5132 1609 /* e8 */
ce518a5f
L		 1610 { "callT", { Jv } },
1611 { "jmpT", { Jv } },
4e7d34a6 1612 { X86_64_TABLE (X86_64_EA) },
ce518a5f
L		 1613 { "jmp", { Jb } },
1614 { "inB", { AL, indirDX } },
1615 { "inG", { zAX, indirDX } },
1616 { "outB", { indirDX, AL } },
1617 { "outG", { indirDX, zAX } },
252b5132 1618 /* f0 */
ce518a5f
L		 1619 { "(bad)", { XX } }, /* lock prefix */
1620 { "icebp", { XX } },
1621 { "(bad)", { XX } }, /* repne */
1622 { "(bad)", { XX } }, /* repz */
1623 { "hlt", { XX } },
1624 { "cmc", { XX } },
1ceb70f8
L		 1625 { REG_TABLE (REG_F6) },
1626 { REG_TABLE (REG_F7) },
252b5132 1627 /* f8 */
ce518a5f
L		 1628 { "clc", { XX } },
1629 { "stc", { XX } },
1630 { "cli", { XX } },
1631 { "sti", { XX } },
1632 { "cld", { XX } },
1633 { "std", { XX } },
1ceb70f8
L		 1634 { REG_TABLE (REG_FE) },
1635 { REG_TABLE (REG_FF) },
252b5132
RH		 1636};
1637
6439fc28 1638static const struct dis386 dis386_twobyte[] = {
252b5132 1639 /* 00 */
1ceb70f8
L		 1640 { REG_TABLE (REG_0F00 ) },
1641 { REG_TABLE (REG_0F01 ) },
ce518a5f
L		 1642 { "larS", { Gv, Ew } },
1643 { "lslS", { Gv, Ew } },
1644 { "(bad)", { XX } },
1645 { "syscall", { XX } },
1646 { "clts", { XX } },
1647 { "sysretP", { XX } },
252b5132 1648 /* 08 */
ce518a5f
L		 1649 { "invd", { XX } },
1650 { "wbinvd", { XX } },
1651 { "(bad)", { XX } },
1652 { "ud2a", { XX } },
1653 { "(bad)", { XX } },
b5b1fc4f 1654 { REG_TABLE (REG_0F0D) },
ce518a5f
L		 1655 { "femms", { XX } },
1656 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
252b5132 1657 /* 10 */
1ceb70f8
L		 1658 { PREFIX_TABLE (PREFIX_0F10) },
1659 { PREFIX_TABLE (PREFIX_0F11) },
1660 { PREFIX_TABLE (PREFIX_0F12) },
1661 { MOD_TABLE (MOD_0F13) },
f2a421c4
L		 1662 { "unpcklpX", { XM, EXx } },
1663 { "unpckhpX", { XM, EXx } },
1ceb70f8
L		 1664 { PREFIX_TABLE (PREFIX_0F16) },
1665 { MOD_TABLE (MOD_0F17) },
252b5132 1666 /* 18 */
1ceb70f8 1667 { REG_TABLE (REG_0F18) },
b5b1fc4f
L		 1668 { "nopQ", { Ev } },
1669 { "nopQ", { Ev } },
1670 { "nopQ", { Ev } },
1671 { "nopQ", { Ev } },
1672 { "nopQ", { Ev } },
1673 { "nopQ", { Ev } },
ce518a5f 1674 { "nopQ", { Ev } },
252b5132 1675 /* 20 */
1ceb70f8
L		 1676 { MOD_TABLE (MOD_0F20) },
1677 { MOD_TABLE (MOD_0F21) },
1678 { MOD_TABLE (MOD_0F22) },
1679 { MOD_TABLE (MOD_0F23) },
1680 { MOD_TABLE (MOD_0F24) },
c1e679ec 1681 { "(bad)", { XX } },
1ceb70f8 1682 { MOD_TABLE (MOD_0F26) },
ce518a5f 1683 { "(bad)", { XX } },
252b5132 1684 /* 28 */
09a2c6cf 1685 { "movapX", { XM, EXx } },
b6169b20 1686 { "movapX", { EXxS, XM } },
1ceb70f8
L		 1687 { PREFIX_TABLE (PREFIX_0F2A) },
1688 { PREFIX_TABLE (PREFIX_0F2B) },
1689 { PREFIX_TABLE (PREFIX_0F2C) },
1690 { PREFIX_TABLE (PREFIX_0F2D) },
1691 { PREFIX_TABLE (PREFIX_0F2E) },
1692 { PREFIX_TABLE (PREFIX_0F2F) },
252b5132 1693 /* 30 */
ce518a5f
L		 1694 { "wrmsr", { XX } },
1695 { "rdtsc", { XX } },
1696 { "rdmsr", { XX } },
1697 { "rdpmc", { XX } },
1698 { "sysenter", { XX } },
1699 { "sysexit", { XX } },
1700 { "(bad)", { XX } },
47dd174c 1701 { "getsec", { XX } },
252b5132 1702 /* 38 */
4e7d34a6 1703 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
ce518a5f 1704 { "(bad)", { XX } },
4e7d34a6 1705 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
ce518a5f
L		 1706 { "(bad)", { XX } },
1707 { "(bad)", { XX } },
1708 { "(bad)", { XX } },
1709 { "(bad)", { XX } },
1710 { "(bad)", { XX } },
252b5132 1711 /* 40 */
b19d5385
JB		 1712 { "cmovoS", { Gv, Ev } },
1713 { "cmovnoS", { Gv, Ev } },
1714 { "cmovbS", { Gv, Ev } },
1715 { "cmovaeS", { Gv, Ev } },
1716 { "cmoveS", { Gv, Ev } },
1717 { "cmovneS", { Gv, Ev } },
1718 { "cmovbeS", { Gv, Ev } },
1719 { "cmovaS", { Gv, Ev } },
252b5132 1720 /* 48 */
b19d5385
JB		 1721 { "cmovsS", { Gv, Ev } },
1722 { "cmovnsS", { Gv, Ev } },
1723 { "cmovpS", { Gv, Ev } },
1724 { "cmovnpS", { Gv, Ev } },
1725 { "cmovlS", { Gv, Ev } },
1726 { "cmovgeS", { Gv, Ev } },
1727 { "cmovleS", { Gv, Ev } },
1728 { "cmovgS", { Gv, Ev } },
252b5132 1729 /* 50 */
75c135a8 1730 { MOD_TABLE (MOD_0F51) },
1ceb70f8
L		 1731 { PREFIX_TABLE (PREFIX_0F51) },
1732 { PREFIX_TABLE (PREFIX_0F52) },
1733 { PREFIX_TABLE (PREFIX_0F53) },
09a2c6cf
L		 1734 { "andpX", { XM, EXx } },
1735 { "andnpX", { XM, EXx } },
1736 { "orpX", { XM, EXx } },
1737 { "xorpX", { XM, EXx } },
252b5132 1738 /* 58 */
1ceb70f8
L		 1739 { PREFIX_TABLE (PREFIX_0F58) },
1740 { PREFIX_TABLE (PREFIX_0F59) },
1741 { PREFIX_TABLE (PREFIX_0F5A) },
1742 { PREFIX_TABLE (PREFIX_0F5B) },
1743 { PREFIX_TABLE (PREFIX_0F5C) },
1744 { PREFIX_TABLE (PREFIX_0F5D) },
1745 { PREFIX_TABLE (PREFIX_0F5E) },
1746 { PREFIX_TABLE (PREFIX_0F5F) },
252b5132 1747 /* 60 */
1ceb70f8
L		 1748 { PREFIX_TABLE (PREFIX_0F60) },
1749 { PREFIX_TABLE (PREFIX_0F61) },
1750 { PREFIX_TABLE (PREFIX_0F62) },
ce518a5f
L		 1751 { "packsswb", { MX, EM } },
1752 { "pcmpgtb", { MX, EM } },
1753 { "pcmpgtw", { MX, EM } },
1754 { "pcmpgtd", { MX, EM } },
1755 { "packuswb", { MX, EM } },
252b5132 1756 /* 68 */
ce518a5f
L		 1757 { "punpckhbw", { MX, EM } },
1758 { "punpckhwd", { MX, EM } },
1759 { "punpckhdq", { MX, EM } },
1760 { "packssdw", { MX, EM } },
1ceb70f8
L		 1761 { PREFIX_TABLE (PREFIX_0F6C) },
1762 { PREFIX_TABLE (PREFIX_0F6D) },
231af070 1763 { "movK", { MX, Edq } },
1ceb70f8 1764 { PREFIX_TABLE (PREFIX_0F6F) },
252b5132 1765 /* 70 */
1ceb70f8
L		 1766 { PREFIX_TABLE (PREFIX_0F70) },
1767 { REG_TABLE (REG_0F71) },
1768 { REG_TABLE (REG_0F72) },
1769 { REG_TABLE (REG_0F73) },
ce518a5f
L		 1770 { "pcmpeqb", { MX, EM } },
1771 { "pcmpeqw", { MX, EM } },
1772 { "pcmpeqd", { MX, EM } },
1773 { "emms", { XX } },
252b5132 1774 /* 78 */
1ceb70f8
L		 1775 { PREFIX_TABLE (PREFIX_0F78) },
1776 { PREFIX_TABLE (PREFIX_0F79) },
4e7d34a6 1777 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
c1e679ec 1778 { "(bad)", { XX } },
1ceb70f8
L		 1779 { PREFIX_TABLE (PREFIX_0F7C) },
1780 { PREFIX_TABLE (PREFIX_0F7D) },
1781 { PREFIX_TABLE (PREFIX_0F7E) },
1782 { PREFIX_TABLE (PREFIX_0F7F) },
252b5132 1783 /* 80 */
ce518a5f
L		 1784 { "joH", { Jv, XX, cond_jump_flag } },
1785 { "jnoH", { Jv, XX, cond_jump_flag } },
1786 { "jbH", { Jv, XX, cond_jump_flag } },
1787 { "jaeH", { Jv, XX, cond_jump_flag } },
1788 { "jeH", { Jv, XX, cond_jump_flag } },
1789 { "jneH", { Jv, XX, cond_jump_flag } },
1790 { "jbeH", { Jv, XX, cond_jump_flag } },
1791 { "jaH", { Jv, XX, cond_jump_flag } },
252b5132 1792 /* 88 */
ce518a5f
L		 1793 { "jsH", { Jv, XX, cond_jump_flag } },
1794 { "jnsH", { Jv, XX, cond_jump_flag } },
1795 { "jpH", { Jv, XX, cond_jump_flag } },
1796 { "jnpH", { Jv, XX, cond_jump_flag } },
1797 { "jlH", { Jv, XX, cond_jump_flag } },
1798 { "jgeH", { Jv, XX, cond_jump_flag } },
1799 { "jleH", { Jv, XX, cond_jump_flag } },
1800 { "jgH", { Jv, XX, cond_jump_flag } },
252b5132 1801 /* 90 */
ce518a5f
L		 1802 { "seto", { Eb } },
1803 { "setno", { Eb } },
1804 { "setb", { Eb } },
1805 { "setae", { Eb } },
1806 { "sete", { Eb } },
1807 { "setne", { Eb } },
1808 { "setbe", { Eb } },
1809 { "seta", { Eb } },
252b5132 1810 /* 98 */
ce518a5f
L		 1811 { "sets", { Eb } },
1812 { "setns", { Eb } },
1813 { "setp", { Eb } },
1814 { "setnp", { Eb } },
1815 { "setl", { Eb } },
1816 { "setge", { Eb } },
1817 { "setle", { Eb } },
1818 { "setg", { Eb } },
252b5132 1819 /* a0 */
ce518a5f
L		 1820 { "pushT", { fs } },
1821 { "popT", { fs } },
1822 { "cpuid", { XX } },
1823 { "btS", { Ev, Gv } },
1824 { "shldS", { Ev, Gv, Ib } },
1825 { "shldS", { Ev, Gv, CL } },
1ceb70f8
L		 1826 { REG_TABLE (REG_0FA6) },
1827 { REG_TABLE (REG_0FA7) },
252b5132 1828 /* a8 */
ce518a5f
L		 1829 { "pushT", { gs } },
1830 { "popT", { gs } },
1831 { "rsm", { XX } },
1832 { "btsS", { Ev, Gv } },
1833 { "shrdS", { Ev, Gv, Ib } },
1834 { "shrdS", { Ev, Gv, CL } },
1ceb70f8 1835 { REG_TABLE (REG_0FAE) },
ce518a5f 1836 { "imulS", { Gv, Ev } },
252b5132 1837 /* b0 */
ce518a5f
L		 1838 { "cmpxchgB", { Eb, Gb } },
1839 { "cmpxchgS", { Ev, Gv } },
1ceb70f8 1840 { MOD_TABLE (MOD_0FB2) },
ce518a5f 1841 { "btrS", { Ev, Gv } },
1ceb70f8
L		 1842 { MOD_TABLE (MOD_0FB4) },
1843 { MOD_TABLE (MOD_0FB5) },
7c52e0e8
L		 1844 { "movz{bR|x}", { Gv, Eb } },
1845 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
252b5132 1846 /* b8 */
1ceb70f8 1847 { PREFIX_TABLE (PREFIX_0FB8) },
ce518a5f 1848 { "ud2b", { XX } },
1ceb70f8 1849 { REG_TABLE (REG_0FBA) },
ce518a5f
L		 1850 { "btcS", { Ev, Gv } },
1851 { "bsfS", { Gv, Ev } },
1ceb70f8 1852 { PREFIX_TABLE (PREFIX_0FBD) },
7c52e0e8
L		 1853 { "movs{bR|x}", { Gv, Eb } },
1854 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
252b5132 1855 /* c0 */
ce518a5f
L		 1856 { "xaddB", { Eb, Gb } },
1857 { "xaddS", { Ev, Gv } },
1ceb70f8 1858 { PREFIX_TABLE (PREFIX_0FC2) },
4ee52178 1859 { PREFIX_TABLE (PREFIX_0FC3) },
ce518a5f
L		 1860 { "pinsrw", { MX, Edqw, Ib } },
1861 { "pextrw", { Gdq, MS, Ib } },
09a2c6cf 1862 { "shufpX", { XM, EXx, Ib } },
1ceb70f8 1863 { REG_TABLE (REG_0FC7) },
252b5132 1864 /* c8 */
ce518a5f
L		 1865 { "bswap", { RMeAX } },
1866 { "bswap", { RMeCX } },
1867 { "bswap", { RMeDX } },
1868 { "bswap", { RMeBX } },
1869 { "bswap", { RMeSP } },
1870 { "bswap", { RMeBP } },
1871 { "bswap", { RMeSI } },
1872 { "bswap", { RMeDI } },
252b5132 1873 /* d0 */
1ceb70f8 1874 { PREFIX_TABLE (PREFIX_0FD0) },
ce518a5f
L		 1875 { "psrlw", { MX, EM } },
1876 { "psrld", { MX, EM } },
1877 { "psrlq", { MX, EM } },
1878 { "paddq", { MX, EM } },
1879 { "pmullw", { MX, EM } },
1ceb70f8 1880 { PREFIX_TABLE (PREFIX_0FD6) },
75c135a8 1881 { MOD_TABLE (MOD_0FD7) },
252b5132 1882 /* d8 */
ce518a5f
L		 1883 { "psubusb", { MX, EM } },
1884 { "psubusw", { MX, EM } },
1885 { "pminub", { MX, EM } },
1886 { "pand", { MX, EM } },
1887 { "paddusb", { MX, EM } },
1888 { "paddusw", { MX, EM } },
1889 { "pmaxub", { MX, EM } },
1890 { "pandn", { MX, EM } },
252b5132 1891 /* e0 */
ce518a5f
L		 1892 { "pavgb", { MX, EM } },
1893 { "psraw", { MX, EM } },
1894 { "psrad", { MX, EM } },
1895 { "pavgw", { MX, EM } },
1896 { "pmulhuw", { MX, EM } },
1897 { "pmulhw", { MX, EM } },
1ceb70f8
L		 1898 { PREFIX_TABLE (PREFIX_0FE6) },
1899 { PREFIX_TABLE (PREFIX_0FE7) },
252b5132 1900 /* e8 */
ce518a5f
L		 1901 { "psubsb", { MX, EM } },
1902 { "psubsw", { MX, EM } },
1903 { "pminsw", { MX, EM } },
1904 { "por", { MX, EM } },
1905 { "paddsb", { MX, EM } },
1906 { "paddsw", { MX, EM } },
1907 { "pmaxsw", { MX, EM } },
1908 { "pxor", { MX, EM } },
252b5132 1909 /* f0 */
1ceb70f8 1910 { PREFIX_TABLE (PREFIX_0FF0) },
ce518a5f
L		 1911 { "psllw", { MX, EM } },
1912 { "pslld", { MX, EM } },
1913 { "psllq", { MX, EM } },
1914 { "pmuludq", { MX, EM } },
1915 { "pmaddwd", { MX, EM } },
1916 { "psadbw", { MX, EM } },
1ceb70f8 1917 { PREFIX_TABLE (PREFIX_0FF7) },
252b5132 1918 /* f8 */
ce518a5f
L		 1919 { "psubb", { MX, EM } },
1920 { "psubw", { MX, EM } },
1921 { "psubd", { MX, EM } },
1922 { "psubq", { MX, EM } },
1923 { "paddb", { MX, EM } },
1924 { "paddw", { MX, EM } },
1925 { "paddd", { MX, EM } },
1926 { "(bad)", { XX } },
252b5132
RH		 1927};
1928
1929static const unsigned char onebyte_has_modrm[256] = {
c608c12e
AM		 1930 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1931 /* ------------------------------- */
1932 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1933 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1934 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1935 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1936 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1937 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1938 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1939 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1940 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1941 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1942 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1943 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1944 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1945 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1946 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1947 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1948 /* ------------------------------- */
1949 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
252b5132
RH		 1950};
1951
1952static const unsigned char twobyte_has_modrm[256] = {
c608c12e
AM		 1953 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1954 /* ------------------------------- */
252b5132 1955 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
b5b1fc4f 1956 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
85f10a01 1957 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
331d2d0d 1958 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
252b5132 1959 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
4bba6815
AM		 1960 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1961 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
85f10a01 1962 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
252b5132
RH		 1963 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1964 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
30d1c836 1965 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
050dfa73 1966 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
252b5132 1967 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
ca164297 1968 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
4bba6815 1969 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
ca164297 1970 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
c608c12e
AM		 1971 /* ------------------------------- */
1972 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1973};
1974
252b5132
RH		 1975static char obuf[100];
1976static char *obufp;
ea397f5b 1977static char *mnemonicendp;
252b5132
RH		 1978static char scratchbuf[100];
1979static unsigned char *start_codep;
1980static unsigned char *insn_codep;
1981static unsigned char *codep;
b844680a
L		 1982static const char *lock_prefix;
1983static const char *data_prefix;
1984static const char *addr_prefix;
1985static const char *repz_prefix;
1986static const char *repnz_prefix;
252b5132 1987static disassemble_info *the_info;
7967e09e
L		 1988static struct
1989 {
1990 int mod;
7967e09e 1991 int reg;
484c222e 1992 int rm;
7967e09e
L		 1993 }
1994modrm;
4bba6815 1995static unsigned char need_modrm;
c0f3af97
L		 1996static struct
1997 {
1998 int register_specifier;
1999 int length;
2000 int prefix;
2001 int w;
2002 }
2003vex;
2004static unsigned char need_vex;
2005static unsigned char need_vex_reg;
dae39acc 2006static unsigned char vex_w_done;
252b5132 2007
ea397f5b
L		 2008struct op
2009 {
2010 const char *name;
2011 unsigned int len;
2012 };
2013
4bba6815
AM		 2014/* If we are accessing mod/rm/reg without need_modrm set, then the
2015 values are stale. Hitting this abort likely indicates that you
2016 need to update onebyte_has_modrm or twobyte_has_modrm. */
2017#define MODRM_CHECK if (!need_modrm) abort ()
2018
d708bcba
AM		 2019static const char **names64;
2020static const char **names32;
2021static const char **names16;
2022static const char **names8;
2023static const char **names8rex;
2024static const char **names_seg;
db51cc60
L		 2025static const char *index64;
2026static const char *index32;
d708bcba
AM		 2027static const char **index16;
2028
2029static const char *intel_names64[] = {
2030 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2031 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2032};
2033static const char *intel_names32[] = {
2034 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2035 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2036};
2037static const char *intel_names16[] = {
2038 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2039 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2040};
2041static const char *intel_names8[] = {
2042 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2043};
2044static const char *intel_names8rex[] = {
2045 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2046 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2047};
2048static const char *intel_names_seg[] = {
2049 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2050};
db51cc60
L		 2051static const char *intel_index64 = "riz";
2052static const char *intel_index32 = "eiz";
d708bcba
AM		 2053static const char *intel_index16[] = {
2054 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2055};
2056
2057static const char *att_names64[] = {
2058 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
52b15da3
JH		 2059 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2060};
d708bcba
AM		 2061static const char *att_names32[] = {
2062 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
52b15da3 2063 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
252b5132 2064};
d708bcba
AM		 2065static const char *att_names16[] = {
2066 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
52b15da3 2067 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
252b5132 2068};
d708bcba
AM		 2069static const char *att_names8[] = {
2070 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
252b5132 2071};
d708bcba
AM		 2072static const char *att_names8rex[] = {
2073 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
52b15da3
JH		 2074 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2075};
d708bcba
AM		 2076static const char *att_names_seg[] = {
2077 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
252b5132 2078};
db51cc60
L		 2079static const char *att_index64 = "%riz";
2080static const char *att_index32 = "%eiz";
d708bcba
AM		 2081static const char *att_index16[] = {
2082 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
252b5132
RH		 2083};
2084
1ceb70f8
L		 2085static const struct dis386 reg_table[][8] = {
2086 /* REG_80 */
252b5132 2087 {
ce518a5f
L		 2088 { "addA", { Eb, Ib } },
2089 { "orA", { Eb, Ib } },
2090 { "adcA", { Eb, Ib } },
2091 { "sbbA", { Eb, Ib } },
2092 { "andA", { Eb, Ib } },
2093 { "subA", { Eb, Ib } },
2094 { "xorA", { Eb, Ib } },
2095 { "cmpA", { Eb, Ib } },
252b5132 2096 },
1ceb70f8 2097 /* REG_81 */
252b5132 2098 {
ce518a5f
L		 2099 { "addQ", { Ev, Iv } },
2100 { "orQ", { Ev, Iv } },
2101 { "adcQ", { Ev, Iv } },
2102 { "sbbQ", { Ev, Iv } },
2103 { "andQ", { Ev, Iv } },
2104 { "subQ", { Ev, Iv } },
2105 { "xorQ", { Ev, Iv } },
2106 { "cmpQ", { Ev, Iv } },
252b5132 2107 },
1ceb70f8 2108 /* REG_82 */
252b5132 2109 {
ce518a5f
L		 2110 { "addQ", { Ev, sIb } },
2111 { "orQ", { Ev, sIb } },
2112 { "adcQ", { Ev, sIb } },
2113 { "sbbQ", { Ev, sIb } },
2114 { "andQ", { Ev, sIb } },
2115 { "subQ", { Ev, sIb } },
2116 { "xorQ", { Ev, sIb } },
2117 { "cmpQ", { Ev, sIb } },
252b5132 2118 },
1ceb70f8 2119 /* REG_8F */
4e7d34a6
L		 2120 {
2121 { "popU", { stackEv } },
2122 { "(bad)", { XX } },
2123 { "(bad)", { XX } },
2124 { "(bad)", { XX } },
2125 { "(bad)", { XX } },
2126 { "(bad)", { XX } },
2127 { "(bad)", { XX } },
2128 { "(bad)", { XX } },
2129 },
1ceb70f8 2130 /* REG_C0 */
252b5132 2131 {
ce518a5f
L		 2132 { "rolA", { Eb, Ib } },
2133 { "rorA", { Eb, Ib } },
2134 { "rclA", { Eb, Ib } },
2135 { "rcrA", { Eb, Ib } },
2136 { "shlA", { Eb, Ib } },
2137 { "shrA", { Eb, Ib } },
2138 { "(bad)", { XX } },
2139 { "sarA", { Eb, Ib } },
252b5132 2140 },
1ceb70f8 2141 /* REG_C1 */
252b5132 2142 {
ce518a5f
L		 2143 { "rolQ", { Ev, Ib } },
2144 { "rorQ", { Ev, Ib } },
2145 { "rclQ", { Ev, Ib } },
2146 { "rcrQ", { Ev, Ib } },
2147 { "shlQ", { Ev, Ib } },
2148 { "shrQ", { Ev, Ib } },
2149 { "(bad)", { XX } },
2150 { "sarQ", { Ev, Ib } },
252b5132 2151 },
1ceb70f8 2152 /* REG_C6 */
4e7d34a6
L		 2153 {
2154 { "movA", { Eb, Ib } },
2155 { "(bad)", { XX } },
2156 { "(bad)", { XX } },
2157 { "(bad)", { XX } },
2158 { "(bad)", { XX } },
2159 { "(bad)", { XX } },
2160 { "(bad)", { XX } },
2161 { "(bad)", { XX } },
2162 },
1ceb70f8 2163 /* REG_C7 */
4e7d34a6
L		 2164 {
2165 { "movQ", { Ev, Iv } },
2166 { "(bad)", { XX } },
2167 { "(bad)", { XX } },
2168 { "(bad)", { XX } },
2169 { "(bad)", { XX } },
2170 { "(bad)", { XX } },
2171 { "(bad)", { XX } },
2172 { "(bad)", { XX } },
2173 },
1ceb70f8 2174 /* REG_D0 */
252b5132 2175 {
ce518a5f
L		 2176 { "rolA", { Eb, I1 } },
2177 { "rorA", { Eb, I1 } },
2178 { "rclA", { Eb, I1 } },
2179 { "rcrA", { Eb, I1 } },
2180 { "shlA", { Eb, I1 } },
2181 { "shrA", { Eb, I1 } },
2182 { "(bad)", { XX } },
2183 { "sarA", { Eb, I1 } },
252b5132 2184 },
1ceb70f8 2185 /* REG_D1 */
252b5132 2186 {
ce518a5f
L		 2187 { "rolQ", { Ev, I1 } },
2188 { "rorQ", { Ev, I1 } },
2189 { "rclQ", { Ev, I1 } },
2190 { "rcrQ", { Ev, I1 } },
2191 { "shlQ", { Ev, I1 } },
2192 { "shrQ", { Ev, I1 } },
2193 { "(bad)", { XX } },
2194 { "sarQ", { Ev, I1 } },
252b5132 2195 },
1ceb70f8 2196 /* REG_D2 */
252b5132 2197 {
ce518a5f
L		 2198 { "rolA", { Eb, CL } },
2199 { "rorA", { Eb, CL } },
2200 { "rclA", { Eb, CL } },
2201 { "rcrA", { Eb, CL } },
2202 { "shlA", { Eb, CL } },
2203 { "shrA", { Eb, CL } },
2204 { "(bad)", { XX } },
2205 { "sarA", { Eb, CL } },
252b5132 2206 },
1ceb70f8 2207 /* REG_D3 */
252b5132 2208 {
ce518a5f
L		 2209 { "rolQ", { Ev, CL } },
2210 { "rorQ", { Ev, CL } },
2211 { "rclQ", { Ev, CL } },
2212 { "rcrQ", { Ev, CL } },
2213 { "shlQ", { Ev, CL } },
2214 { "shrQ", { Ev, CL } },
2215 { "(bad)", { XX } },
2216 { "sarQ", { Ev, CL } },
252b5132 2217 },
1ceb70f8 2218 /* REG_F6 */
252b5132 2219 {
ce518a5f 2220 { "testA", { Eb, Ib } },
058f233b 2221 { "(bad)", { XX } },
ce518a5f
L		 2222 { "notA", { Eb } },
2223 { "negA", { Eb } },
2224 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
2225 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
2226 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
2227 { "idivA", { Eb } }, /* and idiv for consistency. */
252b5132 2228 },
1ceb70f8 2229 /* REG_F7 */
252b5132 2230 {
ce518a5f
L		 2231 { "testQ", { Ev, Iv } },
2232 { "(bad)", { XX } },
2233 { "notQ", { Ev } },
2234 { "negQ", { Ev } },
2235 { "mulQ", { Ev } }, /* Don't print the implicit register. */
2236 { "imulQ", { Ev } },
2237 { "divQ", { Ev } },
2238 { "idivQ", { Ev } },
252b5132 2239 },
1ceb70f8 2240 /* REG_FE */
252b5132 2241 {
ce518a5f
L		 2242 { "incA", { Eb } },
2243 { "decA", { Eb } },
2244 { "(bad)", { XX } },
2245 { "(bad)", { XX } },
2246 { "(bad)", { XX } },
2247 { "(bad)", { XX } },
2248 { "(bad)", { XX } },
2249 { "(bad)", { XX } },
252b5132 2250 },
1ceb70f8 2251 /* REG_FF */
252b5132 2252 {
ce518a5f
L		 2253 { "incQ", { Ev } },
2254 { "decQ", { Ev } },
2255 { "callT", { indirEv } },
2256 { "JcallT", { indirEp } },
2257 { "jmpT", { indirEv } },
2258 { "JjmpT", { indirEp } },
2259 { "pushU", { stackEv } },
2260 { "(bad)", { XX } },
252b5132 2261 },
1ceb70f8 2262 /* REG_0F00 */
252b5132 2263 {
ce518a5f
L		 2264 { "sldtD", { Sv } },
2265 { "strD", { Sv } },
2266 { "lldt", { Ew } },
2267 { "ltr", { Ew } },
2268 { "verr", { Ew } },
2269 { "verw", { Ew } },
2270 { "(bad)", { XX } },
2271 { "(bad)", { XX } },
252b5132 2272 },
1ceb70f8 2273 /* REG_0F01 */
252b5132 2274 {
1ceb70f8
L		 2275 { MOD_TABLE (MOD_0F01_REG_0) },
2276 { MOD_TABLE (MOD_0F01_REG_1) },
2277 { MOD_TABLE (MOD_0F01_REG_2) },
2278 { MOD_TABLE (MOD_0F01_REG_3) },
ce518a5f
L		 2279 { "smswD", { Sv } },
2280 { "(bad)", { XX } },
2281 { "lmsw", { Ew } },
1ceb70f8 2282 { MOD_TABLE (MOD_0F01_REG_7) },
252b5132 2283 },
b5b1fc4f 2284 /* REG_0F0D */
252b5132 2285 {
4e7d34a6
L		 2286 { "prefetch", { Eb } },
2287 { "prefetchw", { Eb } },
2288 { "(bad)", { XX } },
2289 { "(bad)", { XX } },
2290 { "(bad)", { XX } },
2291 { "(bad)", { XX } },
2292 { "(bad)", { XX } },
2293 { "(bad)", { XX } },
252b5132 2294 },
1ceb70f8 2295 /* REG_0F18 */
252b5132 2296 {
1ceb70f8
L		 2297 { MOD_TABLE (MOD_0F18_REG_0) },
2298 { MOD_TABLE (MOD_0F18_REG_1) },
2299 { MOD_TABLE (MOD_0F18_REG_2) },
2300 { MOD_TABLE (MOD_0F18_REG_3) },
ce518a5f
L		 2301 { "(bad)", { XX } },
2302 { "(bad)", { XX } },
2303 { "(bad)", { XX } },
2304 { "(bad)", { XX } },
252b5132 2305 },
1ceb70f8 2306 /* REG_0F71 */
a6bd098c 2307 {
ce518a5f
L		 2308 { "(bad)", { XX } },
2309 { "(bad)", { XX } },
1ceb70f8 2310 { MOD_TABLE (MOD_0F71_REG_2) },
ce518a5f 2311 { "(bad)", { XX } },
1ceb70f8 2312 { MOD_TABLE (MOD_0F71_REG_4) },
ce518a5f 2313 { "(bad)", { XX } },
1ceb70f8 2314 { MOD_TABLE (MOD_0F71_REG_6) },
ce518a5f 2315 { "(bad)", { XX } },
a6bd098c 2316 },
1ceb70f8 2317 /* REG_0F72 */
a6bd098c 2318 {
ce518a5f
L		 2319 { "(bad)", { XX } },
2320 { "(bad)", { XX } },
1ceb70f8 2321 { MOD_TABLE (MOD_0F72_REG_2) },
ce518a5f 2322 { "(bad)", { XX } },
1ceb70f8 2323 { MOD_TABLE (MOD_0F72_REG_4) },
ce518a5f 2324 { "(bad)", { XX } },
1ceb70f8 2325 { MOD_TABLE (MOD_0F72_REG_6) },
ce518a5f 2326 { "(bad)", { XX } },
a6bd098c 2327 },
1ceb70f8 2328 /* REG_0F73 */
252b5132 2329 {
ce518a5f
L		 2330 { "(bad)", { XX } },
2331 { "(bad)", { XX } },
1ceb70f8
L		 2332 { MOD_TABLE (MOD_0F73_REG_2) },
2333 { MOD_TABLE (MOD_0F73_REG_3) },
ce518a5f 2334 { "(bad)", { XX } },
ce518a5f 2335 { "(bad)", { XX } },
1ceb70f8
L		 2336 { MOD_TABLE (MOD_0F73_REG_6) },
2337 { MOD_TABLE (MOD_0F73_REG_7) },
252b5132 2338 },
1ceb70f8 2339 /* REG_0FA6 */
252b5132 2340 {
4e7d34a6
L		 2341 { "montmul", { { OP_0f07, 0 } } },
2342 { "xsha1", { { OP_0f07, 0 } } },
2343 { "xsha256", { { OP_0f07, 0 } } },
2344 { "(bad)", { { OP_0f07, 0 } } },
2345 { "(bad)", { { OP_0f07, 0 } } },
2346 { "(bad)", { { OP_0f07, 0 } } },
2347 { "(bad)", { { OP_0f07, 0 } } },
2348 { "(bad)", { { OP_0f07, 0 } } },
2349 },
1ceb70f8 2350 /* REG_0FA7 */
4e7d34a6
L		 2351 {
2352 { "xstore-rng", { { OP_0f07, 0 } } },
2353 { "xcrypt-ecb", { { OP_0f07, 0 } } },
2354 { "xcrypt-cbc", { { OP_0f07, 0 } } },
2355 { "xcrypt-ctr", { { OP_0f07, 0 } } },
2356 { "xcrypt-cfb", { { OP_0f07, 0 } } },
2357 { "xcrypt-ofb", { { OP_0f07, 0 } } },
2358 { "(bad)", { { OP_0f07, 0 } } },
2359 { "(bad)", { { OP_0f07, 0 } } },
2360 },
1ceb70f8 2361 /* REG_0FAE */
4e7d34a6 2362 {
1ceb70f8
L		 2363 { MOD_TABLE (MOD_0FAE_REG_0) },
2364 { MOD_TABLE (MOD_0FAE_REG_1) },
2365 { MOD_TABLE (MOD_0FAE_REG_2) },
2366 { MOD_TABLE (MOD_0FAE_REG_3) },
475a2301 2367 { MOD_TABLE (MOD_0FAE_REG_4) },
1ceb70f8
L		 2368 { MOD_TABLE (MOD_0FAE_REG_5) },
2369 { MOD_TABLE (MOD_0FAE_REG_6) },
2370 { MOD_TABLE (MOD_0FAE_REG_7) },
252b5132 2371 },
1ceb70f8 2372 /* REG_0FBA */
252b5132 2373 {
ce518a5f
L		 2374 { "(bad)", { XX } },
2375 { "(bad)", { XX } },
d8faab4e
L		 2376 { "(bad)", { XX } },
2377 { "(bad)", { XX } },
4e7d34a6
L		 2378 { "btQ", { Ev, Ib } },
2379 { "btsQ", { Ev, Ib } },
2380 { "btrQ", { Ev, Ib } },
2381 { "btcQ", { Ev, Ib } },
c608c12e 2382 },
1ceb70f8 2383 /* REG_0FC7 */
c608c12e 2384 {
b844680a 2385 { "(bad)", { XX } },
4e7d34a6 2386 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
d8faab4e 2387 { "(bad)", { XX } },
b844680a
L		 2388 { "(bad)", { XX } },
2389 { "(bad)", { XX } },
2390 { "(bad)", { XX } },
1ceb70f8
L		 2391 { MOD_TABLE (MOD_0FC7_REG_6) },
2392 { MOD_TABLE (MOD_0FC7_REG_7) },
252b5132 2393 },
c0f3af97
L		 2394 /* REG_VEX_71 */
2395 {
2396 { "(bad)", { XX } },
2397 { "(bad)", { XX } },
2398 { MOD_TABLE (MOD_VEX_71_REG_2) },
2399 { "(bad)", { XX } },
2400 { MOD_TABLE (MOD_VEX_71_REG_4) },
2401 { "(bad)", { XX } },
2402 { MOD_TABLE (MOD_VEX_71_REG_6) },
2403 { "(bad)", { XX } },
2404 },
2405 /* REG_VEX_72 */
2406 {
2407 { "(bad)", { XX } },
2408 { "(bad)", { XX } },
2409 { MOD_TABLE (MOD_VEX_72_REG_2) },
2410 { "(bad)", { XX } },
2411 { MOD_TABLE (MOD_VEX_72_REG_4) },
2412 { "(bad)", { XX } },
2413 { MOD_TABLE (MOD_VEX_72_REG_6) },
2414 { "(bad)", { XX } },
2415 },
2416 /* REG_VEX_73 */
2417 {
2418 { "(bad)", { XX } },
2419 { "(bad)", { XX } },
2420 { MOD_TABLE (MOD_VEX_73_REG_2) },
2421 { MOD_TABLE (MOD_VEX_73_REG_3) },
2422 { "(bad)", { XX } },
2423 { "(bad)", { XX } },
2424 { MOD_TABLE (MOD_VEX_73_REG_6) },
2425 { MOD_TABLE (MOD_VEX_73_REG_7) },
2426 },
2427 /* REG_VEX_AE */
2428 {
2429 { "(bad)", { XX } },
2430 { "(bad)", { XX } },
2431 { MOD_TABLE (MOD_VEX_AE_REG_2) },
2432 { MOD_TABLE (MOD_VEX_AE_REG_3) },
2433 { "(bad)", { XX } },
2434 { "(bad)", { XX } },
2435 { "(bad)", { XX } },
2436 { "(bad)", { XX } },
2437 },
4e7d34a6
L		 2438};
2439
1ceb70f8
L		 2440static const struct dis386 prefix_table[][4] = {
2441 /* PREFIX_90 */
252b5132 2442 {
4e7d34a6
L		 2443 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2444 { "pause", { XX } },
2445 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2446 { "(bad)", { XX } },
0f10071e 2447 },
4e7d34a6 2448
1ceb70f8 2449 /* PREFIX_0F10 */
cc0ec051 2450 {
4e7d34a6
L		 2451 { "movups", { XM, EXx } },
2452 { "movss", { XM, EXd } },
2453 { "movupd", { XM, EXx } },
2454 { "movsd", { XM, EXq } },
30d1c836 2455 },
4e7d34a6 2456
1ceb70f8 2457 /* PREFIX_0F11 */
30d1c836 2458 {
b6169b20 2459 { "movups", { EXxS, XM } },
fa99fab2 2460 { "movss", { EXdS, XM } },
b6169b20 2461 { "movupd", { EXxS, XM } },
fa99fab2 2462 { "movsd", { EXqS, XM } },
4e7d34a6 2463 },
252b5132 2464
1ceb70f8 2465 /* PREFIX_0F12 */
c608c12e 2466 {
1ceb70f8 2467 { MOD_TABLE (MOD_0F12_PREFIX_0) },
4e7d34a6
L		 2468 { "movsldup", { XM, EXx } },
2469 { "movlpd", { XM, EXq } },
2470 { "movddup", { XM, EXq } },
c608c12e 2471 },
4e7d34a6 2472
1ceb70f8 2473 /* PREFIX_0F16 */
c608c12e 2474 {
1ceb70f8 2475 { MOD_TABLE (MOD_0F16_PREFIX_0) },
4e7d34a6
L		 2476 { "movshdup", { XM, EXx } },
2477 { "movhpd", { XM, EXq } },
058f233b 2478 { "(bad)", { XX } },
c608c12e 2479 },
4e7d34a6 2480
1ceb70f8 2481 /* PREFIX_0F2A */
c608c12e 2482 {
09335d05 2483 { "cvtpi2ps", { XM, EMCq } },
98b528ac 2484 { "cvtsi2ss%LQ", { XM, Ev } },
09335d05 2485 { "cvtpi2pd", { XM, EMCq } },
98b528ac 2486 { "cvtsi2sd%LQ", { XM, Ev } },
c608c12e 2487 },
4e7d34a6 2488
1ceb70f8 2489 /* PREFIX_0F2B */
c608c12e 2490 {
75c135a8
L		 2491 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2492 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2493 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2494 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
c608c12e 2495 },
4e7d34a6 2496
1ceb70f8 2497 /* PREFIX_0F2C */
c608c12e 2498 {
09335d05
L		 2499 { "cvttps2pi", { MXC, EXq } },
2500 { "cvttss2siY", { Gv, EXd } },
09a2c6cf 2501 { "cvttpd2pi", { MXC, EXx } },
09335d05 2502 { "cvttsd2siY", { Gv, EXq } },
c608c12e 2503 },
4e7d34a6 2504
1ceb70f8 2505 /* PREFIX_0F2D */
c608c12e 2506 {
4e7d34a6
L		 2507 { "cvtps2pi", { MXC, EXq } },
2508 { "cvtss2siY", { Gv, EXd } },
2509 { "cvtpd2pi", { MXC, EXx } },
2510 { "cvtsd2siY", { Gv, EXq } },
c608c12e 2511 },
4e7d34a6 2512
1ceb70f8 2513 /* PREFIX_0F2E */
c608c12e 2514 {
4e7d34a6
L		 2515 { "ucomiss",{ XM, EXd } },
2516 { "(bad)", { XX } },
2517 { "ucomisd",{ XM, EXq } },
2518 { "(bad)", { XX } },
c608c12e 2519 },
4e7d34a6 2520
1ceb70f8 2521 /* PREFIX_0F2F */
c608c12e 2522 {
4e7d34a6
L		 2523 { "comiss", { XM, EXd } },
2524 { "(bad)", { XX } },
2525 { "comisd", { XM, EXq } },
2526 { "(bad)", { XX } },
c608c12e 2527 },
4e7d34a6 2528
1ceb70f8 2529 /* PREFIX_0F51 */
c608c12e 2530 {
4e7d34a6
L		 2531 { "sqrtps", { XM, EXx } },
2532 { "sqrtss", { XM, EXd } },
2533 { "sqrtpd", { XM, EXx } },
2534 { "sqrtsd", { XM, EXq } },
c608c12e 2535 },
4e7d34a6 2536
1ceb70f8 2537 /* PREFIX_0F52 */
c608c12e 2538 {
4e7d34a6
L		 2539 { "rsqrtps",{ XM, EXx } },
2540 { "rsqrtss",{ XM, EXd } },
058f233b
L		 2541 { "(bad)", { XX } },
2542 { "(bad)", { XX } },
c608c12e 2543 },
4e7d34a6 2544
1ceb70f8 2545 /* PREFIX_0F53 */
c608c12e 2546 {
4e7d34a6
L		 2547 { "rcpps", { XM, EXx } },
2548 { "rcpss", { XM, EXd } },
058f233b
L		 2549 { "(bad)", { XX } },
2550 { "(bad)", { XX } },
c608c12e 2551 },
4e7d34a6 2552
1ceb70f8 2553 /* PREFIX_0F58 */
c608c12e 2554 {
4e7d34a6
L		 2555 { "addps", { XM, EXx } },
2556 { "addss", { XM, EXd } },
2557 { "addpd", { XM, EXx } },
2558 { "addsd", { XM, EXq } },
c608c12e 2559 },
4e7d34a6 2560
1ceb70f8 2561 /* PREFIX_0F59 */
c608c12e 2562 {
4e7d34a6
L		 2563 { "mulps", { XM, EXx } },
2564 { "mulss", { XM, EXd } },
2565 { "mulpd", { XM, EXx } },
2566 { "mulsd", { XM, EXq } },
041bd2e0 2567 },
4e7d34a6 2568
1ceb70f8 2569 /* PREFIX_0F5A */
041bd2e0 2570 {
4e7d34a6
L		 2571 { "cvtps2pd", { XM, EXq } },
2572 { "cvtss2sd", { XM, EXd } },
2573 { "cvtpd2ps", { XM, EXx } },
2574 { "cvtsd2ss", { XM, EXq } },
041bd2e0 2575 },
4e7d34a6 2576
1ceb70f8 2577 /* PREFIX_0F5B */
041bd2e0 2578 {
09a2c6cf
L		 2579 { "cvtdq2ps", { XM, EXx } },
2580 { "cvttps2dq", { XM, EXx } },
2581 { "cvtps2dq", { XM, EXx } },
058f233b 2582 { "(bad)", { XX } },
041bd2e0 2583 },
4e7d34a6 2584
1ceb70f8 2585 /* PREFIX_0F5C */
041bd2e0 2586 {
4e7d34a6
L		 2587 { "subps", { XM, EXx } },
2588 { "subss", { XM, EXd } },
2589 { "subpd", { XM, EXx } },
2590 { "subsd", { XM, EXq } },
041bd2e0 2591 },
4e7d34a6 2592
1ceb70f8 2593 /* PREFIX_0F5D */
041bd2e0 2594 {
4e7d34a6
L		 2595 { "minps", { XM, EXx } },
2596 { "minss", { XM, EXd } },
2597 { "minpd", { XM, EXx } },
2598 { "minsd", { XM, EXq } },
041bd2e0 2599 },
4e7d34a6 2600
1ceb70f8 2601 /* PREFIX_0F5E */
041bd2e0 2602 {
4e7d34a6
L		 2603 { "divps", { XM, EXx } },
2604 { "divss", { XM, EXd } },
2605 { "divpd", { XM, EXx } },
2606 { "divsd", { XM, EXq } },
041bd2e0 2607 },
4e7d34a6 2608
1ceb70f8 2609 /* PREFIX_0F5F */
041bd2e0 2610 {
4e7d34a6
L		 2611 { "maxps", { XM, EXx } },
2612 { "maxss", { XM, EXd } },
2613 { "maxpd", { XM, EXx } },
2614 { "maxsd", { XM, EXq } },
041bd2e0 2615 },
4e7d34a6 2616
1ceb70f8 2617 /* PREFIX_0F60 */
041bd2e0 2618 {
4e7d34a6
L		 2619 { "punpcklbw",{ MX, EMd } },
2620 { "(bad)", { XX } },
2621 { "punpcklbw",{ MX, EMx } },
2622 { "(bad)", { XX } },
041bd2e0 2623 },
4e7d34a6 2624
1ceb70f8 2625 /* PREFIX_0F61 */
041bd2e0 2626 {
4e7d34a6
L		 2627 { "punpcklwd",{ MX, EMd } },
2628 { "(bad)", { XX } },
2629 { "punpcklwd",{ MX, EMx } },
2630 { "(bad)", { XX } },
041bd2e0 2631 },
4e7d34a6 2632
1ceb70f8 2633 /* PREFIX_0F62 */
041bd2e0 2634 {
4e7d34a6
L		 2635 { "punpckldq",{ MX, EMd } },
2636 { "(bad)", { XX } },
2637 { "punpckldq",{ MX, EMx } },
2638 { "(bad)", { XX } },
041bd2e0 2639 },
4e7d34a6 2640
1ceb70f8 2641 /* PREFIX_0F6C */
041bd2e0 2642 {
058f233b
L		 2643 { "(bad)", { XX } },
2644 { "(bad)", { XX } },
4e7d34a6 2645 { "punpcklqdq", { XM, EXx } },
058f233b 2646 { "(bad)", { XX } },
0f17484f 2647 },
4e7d34a6 2648
1ceb70f8 2649 /* PREFIX_0F6D */
0f17484f 2650 {
058f233b
L		 2651 { "(bad)", { XX } },
2652 { "(bad)", { XX } },
4e7d34a6 2653 { "punpckhqdq", { XM, EXx } },
058f233b 2654 { "(bad)", { XX } },
041bd2e0 2655 },
4e7d34a6 2656
1ceb70f8 2657 /* PREFIX_0F6F */
ca164297 2658 {
4e7d34a6
L		 2659 { "movq", { MX, EM } },
2660 { "movdqu", { XM, EXx } },
2661 { "movdqa", { XM, EXx } },
058f233b 2662 { "(bad)", { XX } },
ca164297 2663 },
4e7d34a6 2664
1ceb70f8 2665 /* PREFIX_0F70 */
4e7d34a6
L		 2666 {
2667 { "pshufw", { MX, EM, Ib } },
2668 { "pshufhw",{ XM, EXx, Ib } },
2669 { "pshufd", { XM, EXx, Ib } },
2670 { "pshuflw",{ XM, EXx, Ib } },
2671 },
2672
92fddf8e
L		 2673 /* PREFIX_0F73_REG_3 */
2674 {
2675 { "(bad)", { XX } },
2676 { "(bad)", { XX } },
2677 { "psrldq", { XS, Ib } },
2678 { "(bad)", { XX } },
2679 },
2680
2681 /* PREFIX_0F73_REG_7 */
2682 {
2683 { "(bad)", { XX } },
2684 { "(bad)", { XX } },
2685 { "pslldq", { XS, Ib } },
2686 { "(bad)", { XX } },
2687 },
2688
1ceb70f8 2689 /* PREFIX_0F78 */
4e7d34a6
L		 2690 {
2691 {"vmread", { Em, Gm } },
2692 {"(bad)", { XX } },
2693 {"extrq", { XS, Ib, Ib } },
2694 {"insertq", { XM, XS, Ib, Ib } },
2695 },
2696
1ceb70f8 2697 /* PREFIX_0F79 */
4e7d34a6
L		 2698 {
2699 {"vmwrite", { Gm, Em } },
2700 {"(bad)", { XX } },
2701 {"extrq", { XM, XS } },
2702 {"insertq", { XM, XS } },
2703 },
2704
1ceb70f8 2705 /* PREFIX_0F7C */
ca164297 2706 {
058f233b
L		 2707 { "(bad)", { XX } },
2708 { "(bad)", { XX } },
09a2c6cf
L		 2709 { "haddpd", { XM, EXx } },
2710 { "haddps", { XM, EXx } },
ca164297 2711 },
4e7d34a6 2712
1ceb70f8 2713 /* PREFIX_0F7D */
ca164297 2714 {
058f233b
L		 2715 { "(bad)", { XX } },
2716 { "(bad)", { XX } },
09a2c6cf
L		 2717 { "hsubpd", { XM, EXx } },
2718 { "hsubps", { XM, EXx } },
ca164297 2719 },
4e7d34a6 2720
1ceb70f8 2721 /* PREFIX_0F7E */
ca164297 2722 {
4e7d34a6
L		 2723 { "movK", { Edq, MX } },
2724 { "movq", { XM, EXq } },
2725 { "movK", { Edq, XM } },
058f233b 2726 { "(bad)", { XX } },
ca164297 2727 },
4e7d34a6 2728
1ceb70f8 2729 /* PREFIX_0F7F */
ca164297 2730 {
b6169b20
L		 2731 { "movq", { EMS, MX } },
2732 { "movdqu", { EXxS, XM } },
2733 { "movdqa", { EXxS, XM } },
058f233b 2734 { "(bad)", { XX } },
ca164297 2735 },
4e7d34a6 2736
1ceb70f8 2737 /* PREFIX_0FB8 */
ca164297 2738 {
4e7d34a6
L		 2739 { "(bad)", { XX } },
2740 { "popcntS", { Gv, Ev } },
2741 { "(bad)", { XX } },
2742 { "(bad)", { XX } },
ca164297 2743 },
4e7d34a6 2744
1ceb70f8 2745 /* PREFIX_0FBD */
050dfa73 2746 {
4e7d34a6
L		 2747 { "bsrS", { Gv, Ev } },
2748 { "lzcntS", { Gv, Ev } },
2749 { "bsrS", { Gv, Ev } },
2750 { "(bad)", { XX } },
050dfa73
MM		 2751 },
2752
1ceb70f8 2753 /* PREFIX_0FC2 */
050dfa73 2754 {
ad19981d
L		 2755 { "cmpps", { XM, EXx, CMP } },
2756 { "cmpss", { XM, EXd, CMP } },
2757 { "cmppd", { XM, EXx, CMP } },
2758 { "cmpsd", { XM, EXq, CMP } },
050dfa73 2759 },
246c51aa 2760
4ee52178
L		 2761 /* PREFIX_0FC3 */
2762 {
2763 { "movntiS", { Ma, Gv } },
2764 { "(bad)", { XX } },
2765 { "(bad)", { XX } },
2766 { "(bad)", { XX } },
2767 },
2768
92fddf8e
L		 2769 /* PREFIX_0FC7_REG_6 */
2770 {
2771 { "vmptrld",{ Mq } },
2772 { "vmxon", { Mq } },
2773 { "vmclear",{ Mq } },
2774 { "(bad)", { XX } },
2775 },
2776
1ceb70f8 2777 /* PREFIX_0FD0 */
050dfa73 2778 {
058f233b
L		 2779 { "(bad)", { XX } },
2780 { "(bad)", { XX } },
4e7d34a6
L		 2781 { "addsubpd", { XM, EXx } },
2782 { "addsubps", { XM, EXx } },
246c51aa 2783 },
050dfa73 2784
1ceb70f8 2785 /* PREFIX_0FD6 */
050dfa73 2786 {
058f233b 2787 { "(bad)", { XX } },
4e7d34a6 2788 { "movq2dq",{ XM, MS } },
b6169b20 2789 { "movq", { EXqS, XM } },
4e7d34a6 2790 { "movdq2q",{ MX, XS } },
050dfa73
MM		 2791 },
2792
1ceb70f8 2793 /* PREFIX_0FE6 */
7918206c 2794 {
058f233b 2795 { "(bad)", { XX } },
4e7d34a6
L		 2796 { "cvtdq2pd", { XM, EXq } },
2797 { "cvttpd2dq", { XM, EXx } },
2798 { "cvtpd2dq", { XM, EXx } },
7918206c 2799 },
8b38ad71 2800
1ceb70f8 2801 /* PREFIX_0FE7 */
8b38ad71 2802 {
4ee52178 2803 { "movntq", { Mq, MX } },
058f233b 2804 { "(bad)", { XX } },
75c135a8 2805 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
058f233b 2806 { "(bad)", { XX } },
4e7d34a6
L		 2807 },
2808
1ceb70f8 2809 /* PREFIX_0FF0 */
4e7d34a6 2810 {
058f233b
L		 2811 { "(bad)", { XX } },
2812 { "(bad)", { XX } },
2813 { "(bad)", { XX } },
1ceb70f8 2814 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4e7d34a6
L		 2815 },
2816
1ceb70f8 2817 /* PREFIX_0FF7 */
4e7d34a6
L		 2818 {
2819 { "maskmovq", { MX, MS } },
058f233b 2820 { "(bad)", { XX } },
4e7d34a6 2821 { "maskmovdqu", { XM, XS } },
058f233b 2822 { "(bad)", { XX } },
8b38ad71 2823 },
42903f7f 2824
1ceb70f8 2825 /* PREFIX_0F3810 */
42903f7f
L		 2826 {
2827 { "(bad)", { XX } },
2828 { "(bad)", { XX } },
88a94849 2829 { "pblendvb", { XM, EXx, XMM0 } },
42903f7f
L		 2830 { "(bad)", { XX } },
2831 },
2832
1ceb70f8 2833 /* PREFIX_0F3814 */
42903f7f
L		 2834 {
2835 { "(bad)", { XX } },
2836 { "(bad)", { XX } },
88a94849 2837 { "blendvps", { XM, EXx, XMM0 } },
42903f7f
L		 2838 { "(bad)", { XX } },
2839 },
2840
1ceb70f8 2841 /* PREFIX_0F3815 */
42903f7f
L		 2842 {
2843 { "(bad)", { XX } },
2844 { "(bad)", { XX } },
09a2c6cf 2845 { "blendvpd", { XM, EXx, XMM0 } },
42903f7f
L		 2846 { "(bad)", { XX } },
2847 },
2848
1ceb70f8 2849 /* PREFIX_0F3817 */
42903f7f
L		 2850 {
2851 { "(bad)", { XX } },
2852 { "(bad)", { XX } },
09a2c6cf 2853 { "ptest", { XM, EXx } },
42903f7f
L		 2854 { "(bad)", { XX } },
2855 },
2856
1ceb70f8 2857 /* PREFIX_0F3820 */
42903f7f
L		 2858 {
2859 { "(bad)", { XX } },
2860 { "(bad)", { XX } },
8976381e 2861 { "pmovsxbw", { XM, EXq } },
42903f7f
L		 2862 { "(bad)", { XX } },
2863 },
2864
1ceb70f8 2865 /* PREFIX_0F3821 */
42903f7f
L		 2866 {
2867 { "(bad)", { XX } },
2868 { "(bad)", { XX } },
8976381e 2869 { "pmovsxbd", { XM, EXd } },
42903f7f
L		 2870 { "(bad)", { XX } },
2871 },
2872
1ceb70f8 2873 /* PREFIX_0F3822 */
42903f7f
L		 2874 {
2875 { "(bad)", { XX } },
2876 { "(bad)", { XX } },
8976381e 2877 { "pmovsxbq", { XM, EXw } },
42903f7f
L		 2878 { "(bad)", { XX } },
2879 },
2880
1ceb70f8 2881 /* PREFIX_0F3823 */
42903f7f
L		 2882 {
2883 { "(bad)", { XX } },
2884 { "(bad)", { XX } },
8976381e 2885 { "pmovsxwd", { XM, EXq } },
42903f7f
L		 2886 { "(bad)", { XX } },
2887 },
2888
1ceb70f8 2889 /* PREFIX_0F3824 */
42903f7f
L		 2890 {
2891 { "(bad)", { XX } },
2892 { "(bad)", { XX } },
8976381e 2893 { "pmovsxwq", { XM, EXd } },
42903f7f
L		 2894 { "(bad)", { XX } },
2895 },
2896
1ceb70f8 2897 /* PREFIX_0F3825 */
42903f7f
L		 2898 {
2899 { "(bad)", { XX } },
2900 { "(bad)", { XX } },
8976381e 2901 { "pmovsxdq", { XM, EXq } },
42903f7f
L		 2902 { "(bad)", { XX } },
2903 },
2904
1ceb70f8 2905 /* PREFIX_0F3828 */
42903f7f
L		 2906 {
2907 { "(bad)", { XX } },
2908 { "(bad)", { XX } },
09a2c6cf 2909 { "pmuldq", { XM, EXx } },
42903f7f
L		 2910 { "(bad)", { XX } },
2911 },
2912
1ceb70f8 2913 /* PREFIX_0F3829 */
42903f7f
L		 2914 {
2915 { "(bad)", { XX } },
2916 { "(bad)", { XX } },
09a2c6cf 2917 { "pcmpeqq", { XM, EXx } },
42903f7f
L		 2918 { "(bad)", { XX } },
2919 },
2920
1ceb70f8 2921 /* PREFIX_0F382A */
42903f7f
L		 2922 {
2923 { "(bad)", { XX } },
2924 { "(bad)", { XX } },
75c135a8 2925 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
42903f7f
L		 2926 { "(bad)", { XX } },
2927 },
2928
1ceb70f8 2929 /* PREFIX_0F382B */
42903f7f
L		 2930 {
2931 { "(bad)", { XX } },
2932 { "(bad)", { XX } },
09a2c6cf 2933 { "packusdw", { XM, EXx } },
42903f7f
L		 2934 { "(bad)", { XX } },
2935 },
2936
1ceb70f8 2937 /* PREFIX_0F3830 */
42903f7f
L		 2938 {
2939 { "(bad)", { XX } },
2940 { "(bad)", { XX } },
8976381e 2941 { "pmovzxbw", { XM, EXq } },
42903f7f
L		 2942 { "(bad)", { XX } },
2943 },
2944
1ceb70f8 2945 /* PREFIX_0F3831 */
42903f7f
L		 2946 {
2947 { "(bad)", { XX } },
2948 { "(bad)", { XX } },
8976381e 2949 { "pmovzxbd", { XM, EXd } },
42903f7f
L		 2950 { "(bad)", { XX } },
2951 },
2952
1ceb70f8 2953 /* PREFIX_0F3832 */
42903f7f
L		 2954 {
2955 { "(bad)", { XX } },
2956 { "(bad)", { XX } },
8976381e 2957 { "pmovzxbq", { XM, EXw } },
42903f7f
L		 2958 { "(bad)", { XX } },
2959 },
2960
1ceb70f8 2961 /* PREFIX_0F3833 */
42903f7f
L		 2962 {
2963 { "(bad)", { XX } },
2964 { "(bad)", { XX } },
8976381e 2965 { "pmovzxwd", { XM, EXq } },
42903f7f
L		 2966 { "(bad)", { XX } },
2967 },
2968
1ceb70f8 2969 /* PREFIX_0F3834 */
42903f7f
L		 2970 {
2971 { "(bad)", { XX } },
2972 { "(bad)", { XX } },
8976381e 2973 { "pmovzxwq", { XM, EXd } },
42903f7f
L		 2974 { "(bad)", { XX } },
2975 },
2976
1ceb70f8 2977 /* PREFIX_0F3835 */
42903f7f
L		 2978 {
2979 { "(bad)", { XX } },
2980 { "(bad)", { XX } },
8976381e 2981 { "pmovzxdq", { XM, EXq } },
42903f7f
L		 2982 { "(bad)", { XX } },
2983 },
2984
1ceb70f8 2985 /* PREFIX_0F3837 */
4e7d34a6
L		 2986 {
2987 { "(bad)", { XX } },
2988 { "(bad)", { XX } },
2989 { "pcmpgtq", { XM, EXx } },
2990 { "(bad)", { XX } },
2991 },
2992
1ceb70f8 2993 /* PREFIX_0F3838 */
42903f7f
L		 2994 {
2995 { "(bad)", { XX } },
2996 { "(bad)", { XX } },
09a2c6cf 2997 { "pminsb", { XM, EXx } },
42903f7f
L		 2998 { "(bad)", { XX } },
2999 },
3000
1ceb70f8 3001 /* PREFIX_0F3839 */
42903f7f
L		 3002 {
3003 { "(bad)", { XX } },
3004 { "(bad)", { XX } },
09a2c6cf 3005 { "pminsd", { XM, EXx } },
42903f7f
L		 3006 { "(bad)", { XX } },
3007 },
3008
1ceb70f8 3009 /* PREFIX_0F383A */
42903f7f
L		 3010 {
3011 { "(bad)", { XX } },
3012 { "(bad)", { XX } },
09a2c6cf 3013 { "pminuw", { XM, EXx } },
42903f7f
L		 3014 { "(bad)", { XX } },
3015 },
3016
1ceb70f8 3017 /* PREFIX_0F383B */
42903f7f
L		 3018 {
3019 { "(bad)", { XX } },
3020 { "(bad)", { XX } },
09a2c6cf 3021 { "pminud", { XM, EXx } },
42903f7f
L		 3022 { "(bad)", { XX } },
3023 },
3024
1ceb70f8 3025 /* PREFIX_0F383C */
42903f7f
L		 3026 {
3027 { "(bad)", { XX } },
3028 { "(bad)", { XX } },
09a2c6cf 3029 { "pmaxsb", { XM, EXx } },
42903f7f
L		 3030 { "(bad)", { XX } },
3031 },
3032
1ceb70f8 3033 /* PREFIX_0F383D */
42903f7f
L		 3034 {
3035 { "(bad)", { XX } },
3036 { "(bad)", { XX } },
09a2c6cf 3037 { "pmaxsd", { XM, EXx } },
42903f7f
L		 3038 { "(bad)", { XX } },
3039 },
3040
1ceb70f8 3041 /* PREFIX_0F383E */
42903f7f
L		 3042 {
3043 { "(bad)", { XX } },
3044 { "(bad)", { XX } },
09a2c6cf 3045 { "pmaxuw", { XM, EXx } },
42903f7f
L		 3046 { "(bad)", { XX } },
3047 },
3048
1ceb70f8 3049 /* PREFIX_0F383F */
42903f7f
L		 3050 {
3051 { "(bad)", { XX } },
3052 { "(bad)", { XX } },
09a2c6cf 3053 { "pmaxud", { XM, EXx } },
42903f7f
L		 3054 { "(bad)", { XX } },
3055 },
3056
1ceb70f8 3057 /* PREFIX_0F3840 */
42903f7f
L		 3058 {
3059 { "(bad)", { XX } },
3060 { "(bad)", { XX } },
09a2c6cf 3061 { "pmulld", { XM, EXx } },
42903f7f
L		 3062 { "(bad)", { XX } },
3063 },
3064
1ceb70f8 3065 /* PREFIX_0F3841 */
42903f7f
L		 3066 {
3067 { "(bad)", { XX } },
3068 { "(bad)", { XX } },
09a2c6cf 3069 { "phminposuw", { XM, EXx } },
42903f7f
L		 3070 { "(bad)", { XX } },
3071 },
3072
f1f8f695
L		 3073 /* PREFIX_0F3880 */
3074 {
3075 { "(bad)", { XX } },
3076 { "(bad)", { XX } },
3077 { "invept", { Gm, Mo } },
3078 { "(bad)", { XX } },
3079 },
3080
3081 /* PREFIX_0F3881 */
3082 {
3083 { "(bad)", { XX } },
3084 { "(bad)", { XX } },
3085 { "invvpid", { Gm, Mo } },
3086 { "(bad)", { XX } },
3087 },
3088
c0f3af97
L		 3089 /* PREFIX_0F38DB */
3090 {
3091 { "(bad)", { XX } },
3092 { "(bad)", { XX } },
3093 { "aesimc", { XM, EXx } },
3094 { "(bad)", { XX } },
3095 },
3096
3097 /* PREFIX_0F38DC */
3098 {
3099 { "(bad)", { XX } },
3100 { "(bad)", { XX } },
3101 { "aesenc", { XM, EXx } },
3102 { "(bad)", { XX } },
3103 },
3104
3105 /* PREFIX_0F38DD */
3106 {
3107 { "(bad)", { XX } },
3108 { "(bad)", { XX } },
3109 { "aesenclast", { XM, EXx } },
3110 { "(bad)", { XX } },
3111 },
3112
3113 /* PREFIX_0F38DE */
3114 {
3115 { "(bad)", { XX } },
3116 { "(bad)", { XX } },
3117 { "aesdec", { XM, EXx } },
3118 { "(bad)", { XX } },
3119 },
3120
3121 /* PREFIX_0F38DF */
3122 {
3123 { "(bad)", { XX } },
3124 { "(bad)", { XX } },
3125 { "aesdeclast", { XM, EXx } },
3126 { "(bad)", { XX } },
3127 },
3128
1ceb70f8 3129 /* PREFIX_0F38F0 */
4e7d34a6 3130 {
f1f8f695 3131 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4e7d34a6 3132 { "(bad)", { XX } },
f1f8f695 3133 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4e7d34a6
L		 3134 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
3135 },
3136
1ceb70f8 3137 /* PREFIX_0F38F1 */
4e7d34a6 3138 {
f1f8f695 3139 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4e7d34a6 3140 { "(bad)", { XX } },
f1f8f695 3141 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4e7d34a6
L		 3142 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
3143 },
3144
1ceb70f8 3145 /* PREFIX_0F3A08 */
42903f7f
L		 3146 {
3147 { "(bad)", { XX } },
3148 { "(bad)", { XX } },
09a2c6cf 3149 { "roundps", { XM, EXx, Ib } },
42903f7f
L		 3150 { "(bad)", { XX } },
3151 },
3152
1ceb70f8 3153 /* PREFIX_0F3A09 */
42903f7f
L		 3154 {
3155 { "(bad)", { XX } },
3156 { "(bad)", { XX } },
09a2c6cf 3157 { "roundpd", { XM, EXx, Ib } },
42903f7f
L		 3158 { "(bad)", { XX } },
3159 },
3160
1ceb70f8 3161 /* PREFIX_0F3A0A */
42903f7f
L		 3162 {
3163 { "(bad)", { XX } },
3164 { "(bad)", { XX } },
09335d05 3165 { "roundss", { XM, EXd, Ib } },
42903f7f
L		 3166 { "(bad)", { XX } },
3167 },
3168
1ceb70f8 3169 /* PREFIX_0F3A0B */
42903f7f
L		 3170 {
3171 { "(bad)", { XX } },
3172 { "(bad)", { XX } },
09335d05 3173 { "roundsd", { XM, EXq, Ib } },
42903f7f
L		 3174 { "(bad)", { XX } },
3175 },
3176
1ceb70f8 3177 /* PREFIX_0F3A0C */
42903f7f
L		 3178 {
3179 { "(bad)", { XX } },
3180 { "(bad)", { XX } },
09a2c6cf 3181 { "blendps", { XM, EXx, Ib } },
42903f7f
L		 3182 { "(bad)", { XX } },
3183 },
3184
1ceb70f8 3185 /* PREFIX_0F3A0D */
42903f7f
L		 3186 {
3187 { "(bad)", { XX } },
3188 { "(bad)", { XX } },
09a2c6cf 3189 { "blendpd", { XM, EXx, Ib } },
42903f7f
L		 3190 { "(bad)", { XX } },
3191 },
3192
1ceb70f8 3193 /* PREFIX_0F3A0E */
42903f7f
L		 3194 {
3195 { "(bad)", { XX } },
3196 { "(bad)", { XX } },
09a2c6cf 3197 { "pblendw", { XM, EXx, Ib } },
42903f7f
L		 3198 { "(bad)", { XX } },
3199 },
3200
1ceb70f8 3201 /* PREFIX_0F3A14 */
42903f7f
L		 3202 {
3203 { "(bad)", { XX } },
3204 { "(bad)", { XX } },
3205 { "pextrb", { Edqb, XM, Ib } },
3206 { "(bad)", { XX } },
3207 },
3208
1ceb70f8 3209 /* PREFIX_0F3A15 */
42903f7f
L		 3210 {
3211 { "(bad)", { XX } },
3212 { "(bad)", { XX } },
3213 { "pextrw", { Edqw, XM, Ib } },
3214 { "(bad)", { XX } },
3215 },
3216
1ceb70f8 3217 /* PREFIX_0F3A16 */
42903f7f
L		 3218 {
3219 { "(bad)", { XX } },
3220 { "(bad)", { XX } },
3221 { "pextrK", { Edq, XM, Ib } },
3222 { "(bad)", { XX } },
3223 },
3224
1ceb70f8 3225 /* PREFIX_0F3A17 */
42903f7f
L		 3226 {
3227 { "(bad)", { XX } },
3228 { "(bad)", { XX } },
3229 { "extractps", { Edqd, XM, Ib } },
3230 { "(bad)", { XX } },
3231 },
3232
1ceb70f8 3233 /* PREFIX_0F3A20 */
42903f7f
L		 3234 {
3235 { "(bad)", { XX } },
3236 { "(bad)", { XX } },
3237 { "pinsrb", { XM, Edqb, Ib } },
3238 { "(bad)", { XX } },
3239 },
3240
1ceb70f8 3241 /* PREFIX_0F3A21 */
42903f7f
L		 3242 {
3243 { "(bad)", { XX } },
3244 { "(bad)", { XX } },
8976381e 3245 { "insertps", { XM, EXd, Ib } },
42903f7f
L		 3246 { "(bad)", { XX } },
3247 },
3248
1ceb70f8 3249 /* PREFIX_0F3A22 */
42903f7f
L		 3250 {
3251 { "(bad)", { XX } },
3252 { "(bad)", { XX } },
3253 { "pinsrK", { XM, Edq, Ib } },
3254 { "(bad)", { XX } },
3255 },
3256
1ceb70f8 3257 /* PREFIX_0F3A40 */
42903f7f
L		 3258 {
3259 { "(bad)", { XX } },
3260 { "(bad)", { XX } },
09a2c6cf 3261 { "dpps", { XM, EXx, Ib } },
42903f7f
L		 3262 { "(bad)", { XX } },
3263 },
3264
1ceb70f8 3265 /* PREFIX_0F3A41 */
42903f7f
L		 3266 {
3267 { "(bad)", { XX } },
3268 { "(bad)", { XX } },
09a2c6cf 3269 { "dppd", { XM, EXx, Ib } },
42903f7f
L		 3270 { "(bad)", { XX } },
3271 },
3272
1ceb70f8 3273 /* PREFIX_0F3A42 */
42903f7f
L		 3274 {
3275 { "(bad)", { XX } },
3276 { "(bad)", { XX } },
09a2c6cf 3277 { "mpsadbw", { XM, EXx, Ib } },
42903f7f
L		 3278 { "(bad)", { XX } },
3279 },
381d071f 3280
c0f3af97
L		 3281 /* PREFIX_0F3A44 */
3282 {
3283 { "(bad)", { XX } },
3284 { "(bad)", { XX } },
3285 { "pclmulqdq", { XM, EXx, PCLMUL } },
3286 { "(bad)", { XX } },
3287 },
3288
1ceb70f8 3289 /* PREFIX_0F3A60 */
381d071f
L		 3290 {
3291 { "(bad)", { XX } },
3292 { "(bad)", { XX } },
4e7d34a6 3293 { "pcmpestrm", { XM, EXx, Ib } },
381d071f
L		 3294 { "(bad)", { XX } },
3295 },
3296
1ceb70f8 3297 /* PREFIX_0F3A61 */
381d071f
L		 3298 {
3299 { "(bad)", { XX } },
3300 { "(bad)", { XX } },
4e7d34a6 3301 { "pcmpestri", { XM, EXx, Ib } },
381d071f 3302 { "(bad)", { XX } },
381d071f
L		 3303 },
3304
1ceb70f8 3305 /* PREFIX_0F3A62 */
381d071f
L		 3306 {
3307 { "(bad)", { XX } },
3308 { "(bad)", { XX } },
4e7d34a6 3309 { "pcmpistrm", { XM, EXx, Ib } },
381d071f 3310 { "(bad)", { XX } },
381d071f
L		 3311 },
3312
1ceb70f8 3313 /* PREFIX_0F3A63 */
381d071f
L		 3314 {
3315 { "(bad)", { XX } },
3316 { "(bad)", { XX } },
4e7d34a6 3317 { "pcmpistri", { XM, EXx, Ib } },
381d071f
L		 3318 { "(bad)", { XX } },
3319 },
09a2c6cf 3320
c0f3af97 3321 /* PREFIX_0F3ADF */
09a2c6cf 3322 {
c0f3af97
L		 3323 { "(bad)", { XX } },
3324 { "(bad)", { XX } },
3325 { "aeskeygenassist", { XM, EXx, Ib } },
3326 { "(bad)", { XX } },
09a2c6cf
L		 3327 },
3328
c0f3af97 3329 /* PREFIX_VEX_10 */
09a2c6cf 3330 {
c0f3af97
L		 3331 { "vmovups", { XM, EXx } },
3332 { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3333 { "vmovupd", { XM, EXx } },
3334 { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
09a2c6cf
L		 3335 },
3336
c0f3af97 3337 /* PREFIX_VEX_11 */
09a2c6cf 3338 {
b6169b20 3339 { "vmovups", { EXxS, XM } },
c0f3af97 3340 { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
b6169b20 3341 { "vmovupd", { EXxS, XM } },
c0f3af97 3342 { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
09a2c6cf
L		 3343 },
3344
c0f3af97 3345 /* PREFIX_VEX_12 */
09a2c6cf 3346 {
c0f3af97
L		 3347 { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3348 { "vmovsldup", { XM, EXx } },
3349 { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3350 { "vmovddup", { XM, EXymmq } },
09a2c6cf
L		 3351 },
3352
c0f3af97 3353 /* PREFIX_VEX_16 */
09a2c6cf 3354 {
c0f3af97
L		 3355 { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3356 { "vmovshdup", { XM, EXx } },
3357 { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3358 { "(bad)", { XX } },
5f754f58 3359 },
7c52e0e8 3360
c0f3af97 3361 /* PREFIX_VEX_2A */
5f754f58 3362 {
c0f3af97
L		 3363 { "(bad)", { XX } },
3364 { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3365 { "(bad)", { XX } },
3366 { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
5f754f58 3367 },
7c52e0e8 3368
c0f3af97 3369 /* PREFIX_VEX_2C */
5f754f58 3370 {
c0f3af97
L		 3371 { "(bad)", { XX } },
3372 { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3373 { "(bad)", { XX } },
3374 { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
5f754f58 3375 },
7c52e0e8 3376
c0f3af97 3377 /* PREFIX_VEX_2D */
7c52e0e8 3378 {
c0f3af97
L		 3379 { "(bad)", { XX } },
3380 { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3381 { "(bad)", { XX } },
3382 { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
7c52e0e8
L		 3383 },
3384
c0f3af97 3385 /* PREFIX_VEX_2E */
7c52e0e8 3386 {
c0f3af97
L		 3387 { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3388 { "(bad)", { XX } },
3389 { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3390 { "(bad)", { XX } },
7c52e0e8
L		 3391 },
3392
c0f3af97 3393 /* PREFIX_VEX_2F */
7c52e0e8 3394 {
c0f3af97
L		 3395 { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3396 { "(bad)", { XX } },
3397 { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3398 { "(bad)", { XX } },
7c52e0e8
L		 3399 },
3400
c0f3af97 3401 /* PREFIX_VEX_51 */
7c52e0e8 3402 {
c0f3af97
L		 3403 { "vsqrtps", { XM, EXx } },
3404 { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3405 { "vsqrtpd", { XM, EXx } },
3406 { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
7c52e0e8
L		 3407 },
3408
c0f3af97 3409 /* PREFIX_VEX_52 */
7c52e0e8 3410 {
c0f3af97
L		 3411 { "vrsqrtps", { XM, EXx } },
3412 { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3413 { "(bad)", { XX } },
3414 { "(bad)", { XX } },
7c52e0e8
L		 3415 },
3416
c0f3af97 3417 /* PREFIX_VEX_53 */
7c52e0e8 3418 {
c0f3af97
L		 3419 { "vrcpps", { XM, EXx } },
3420 { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3421 { "(bad)", { XX } },
3422 { "(bad)", { XX } },
7c52e0e8
L		 3423 },
3424
c0f3af97 3425 /* PREFIX_VEX_58 */
7c52e0e8 3426 {
c0f3af97
L		 3427 { "vaddps", { XM, Vex, EXx } },
3428 { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3429 { "vaddpd", { XM, Vex, EXx } },
3430 { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
7c52e0e8
L		 3431 },
3432
c0f3af97 3433 /* PREFIX_VEX_59 */
7c52e0e8 3434 {
c0f3af97
L		 3435 { "vmulps", { XM, Vex, EXx } },
3436 { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3437 { "vmulpd", { XM, Vex, EXx } },
3438 { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
7c52e0e8
L		 3439 },
3440
c0f3af97 3441 /* PREFIX_VEX_5A */
7c52e0e8 3442 {
c0f3af97
L		 3443 { "vcvtps2pd", { XM, EXxmmq } },
3444 { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3445 { "vcvtpd2ps%XY", { XMM, EXx } },
3446 { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
7c52e0e8
L		 3447 },
3448
c0f3af97 3449 /* PREFIX_VEX_5B */
7c52e0e8 3450 {
c0f3af97
L		 3451 { "vcvtdq2ps", { XM, EXx } },
3452 { "vcvttps2dq", { XM, EXx } },
3453 { "vcvtps2dq", { XM, EXx } },
3454 { "(bad)", { XX } },
7c52e0e8
L		 3455 },
3456
c0f3af97 3457 /* PREFIX_VEX_5C */
7c52e0e8 3458 {
c0f3af97
L		 3459 { "vsubps", { XM, Vex, EXx } },
3460 { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3461 { "vsubpd", { XM, Vex, EXx } },
3462 { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
7c52e0e8
L		 3463 },
3464
c0f3af97 3465 /* PREFIX_VEX_5D */
7c52e0e8 3466 {
c0f3af97
L		 3467 { "vminps", { XM, Vex, EXx } },
3468 { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3469 { "vminpd", { XM, Vex, EXx } },
3470 { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
7c52e0e8
L		 3471 },
3472
c0f3af97 3473 /* PREFIX_VEX_5E */
7c52e0e8 3474 {
c0f3af97
L		 3475 { "vdivps", { XM, Vex, EXx } },
3476 { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3477 { "vdivpd", { XM, Vex, EXx } },
3478 { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
7c52e0e8
L		 3479 },
3480
c0f3af97 3481 /* PREFIX_VEX_5F */
7c52e0e8 3482 {
c0f3af97
L		 3483 { "vmaxps", { XM, Vex, EXx } },
3484 { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3485 { "vmaxpd", { XM, Vex, EXx } },
3486 { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
7c52e0e8
L		 3487 },
3488
c0f3af97 3489 /* PREFIX_VEX_60 */
7c52e0e8 3490 {
c0f3af97
L		 3491 { "(bad)", { XX } },
3492 { "(bad)", { XX } },
3493 { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3494 { "(bad)", { XX } },
7c52e0e8
L		 3495 },
3496
c0f3af97 3497 /* PREFIX_VEX_61 */
7c52e0e8 3498 {
c0f3af97
L		 3499 { "(bad)", { XX } },
3500 { "(bad)", { XX } },
3501 { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3502 { "(bad)", { XX } },
7c52e0e8
L		 3503 },
3504
c0f3af97 3505 /* PREFIX_VEX_62 */
7c52e0e8 3506 {
c0f3af97
L		 3507 { "(bad)", { XX } },
3508 { "(bad)", { XX } },
3509 { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3510 { "(bad)", { XX } },
7c52e0e8
L		 3511 },
3512
c0f3af97 3513 /* PREFIX_VEX_63 */
7c52e0e8 3514 {
c0f3af97
L		 3515 { "(bad)", { XX } },
3516 { "(bad)", { XX } },
3517 { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3518 { "(bad)", { XX } },
7c52e0e8
L		 3519 },
3520
c0f3af97 3521 /* PREFIX_VEX_64 */
7c52e0e8 3522 {
c0f3af97
L		 3523 { "(bad)", { XX } },
3524 { "(bad)", { XX } },
3525 { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3526 { "(bad)", { XX } },
7c52e0e8
L		 3527 },
3528
c0f3af97 3529 /* PREFIX_VEX_65 */
7c52e0e8 3530 {
c0f3af97
L		 3531 { "(bad)", { XX } },
3532 { "(bad)", { XX } },
3533 { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3534 { "(bad)", { XX } },
7c52e0e8
L		 3535 },
3536
c0f3af97 3537 /* PREFIX_VEX_66 */
7c52e0e8 3538 {
c0f3af97
L		 3539 { "(bad)", { XX } },
3540 { "(bad)", { XX } },
3541 { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3542 { "(bad)", { XX } },
7c52e0e8 3543 },
6439fc28 3544
c0f3af97 3545 /* PREFIX_VEX_67 */
331d2d0d 3546 {
c0f3af97
L		 3547 { "(bad)", { XX } },
3548 { "(bad)", { XX } },
3549 { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3550 { "(bad)", { XX } },
3551 },
3552
3553 /* PREFIX_VEX_68 */
3554 {
3555 { "(bad)", { XX } },
3556 { "(bad)", { XX } },
3557 { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3558 { "(bad)", { XX } },
3559 },
3560
3561 /* PREFIX_VEX_69 */
3562 {
3563 { "(bad)", { XX } },
3564 { "(bad)", { XX } },
3565 { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3566 { "(bad)", { XX } },
3567 },
3568
3569 /* PREFIX_VEX_6A */
3570 {
3571 { "(bad)", { XX } },
3572 { "(bad)", { XX } },
3573 { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3574 { "(bad)", { XX } },
3575 },
3576
3577 /* PREFIX_VEX_6B */
3578 {
3579 { "(bad)", { XX } },
3580 { "(bad)", { XX } },
3581 { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3582 { "(bad)", { XX } },
3583 },
3584
3585 /* PREFIX_VEX_6C */
3586 {
3587 { "(bad)", { XX } },
3588 { "(bad)", { XX } },
3589 { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3590 { "(bad)", { XX } },
3591 },
3592
3593 /* PREFIX_VEX_6D */
3594 {
3595 { "(bad)", { XX } },
3596 { "(bad)", { XX } },
3597 { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3598 { "(bad)", { XX } },
3599 },
3600
3601 /* PREFIX_VEX_6E */
3602 {
3603 { "(bad)", { XX } },
3604 { "(bad)", { XX } },
3605 { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3606 { "(bad)", { XX } },
3607 },
3608
3609 /* PREFIX_VEX_6F */
3610 {
3611 { "(bad)", { XX } },
3612 { "vmovdqu", { XM, EXx } },
3613 { "vmovdqa", { XM, EXx } },
3614 { "(bad)", { XX } },
3615 },
3616
3617 /* PREFIX_VEX_70 */
3618 {
3619 { "(bad)", { XX } },
3620 { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3621 { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3622 { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3623 },
3624
3625 /* PREFIX_VEX_71_REG_2 */
3626 {
3627 { "(bad)", { XX } },
3628 { "(bad)", { XX } },
3629 { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3630 { "(bad)", { XX } },
3631 },
3632
3633 /* PREFIX_VEX_71_REG_4 */
3634 {
3635 { "(bad)", { XX } },
3636 { "(bad)", { XX } },
3637 { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3638 { "(bad)", { XX } },
3639 },
3640
3641 /* PREFIX_VEX_71_REG_6 */
3642 {
3643 { "(bad)", { XX } },
3644 { "(bad)", { XX } },
3645 { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3646 { "(bad)", { XX } },
3647 },
3648
3649 /* PREFIX_VEX_72_REG_2 */
3650 {
3651 { "(bad)", { XX } },
3652 { "(bad)", { XX } },
3653 { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3654 { "(bad)", { XX } },
3655 },
3656
3657 /* PREFIX_VEX_72_REG_4 */
3658 {
3659 { "(bad)", { XX } },
3660 { "(bad)", { XX } },
3661 { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3662 { "(bad)", { XX } },
3663 },
3664
3665 /* PREFIX_VEX_72_REG_6 */
3666 {
3667 { "(bad)", { XX } },
3668 { "(bad)", { XX } },
3669 { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3670 { "(bad)", { XX } },
3671 },
3672
3673 /* PREFIX_VEX_73_REG_2 */
3674 {
3675 { "(bad)", { XX } },
3676 { "(bad)", { XX } },
3677 { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3678 { "(bad)", { XX } },
3679 },
3680
3681 /* PREFIX_VEX_73_REG_3 */
3682 {
3683 { "(bad)", { XX } },
3684 { "(bad)", { XX } },
3685 { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3686 { "(bad)", { XX } },
3687 },
3688
3689 /* PREFIX_VEX_73_REG_6 */
3690 {
3691 { "(bad)", { XX } },
3692 { "(bad)", { XX } },
3693 { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3694 { "(bad)", { XX } },
3695 },
3696
3697 /* PREFIX_VEX_73_REG_7 */
3698 {
3699 { "(bad)", { XX } },
3700 { "(bad)", { XX } },
3701 { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3702 { "(bad)", { XX } },
3703 },
3704
3705 /* PREFIX_VEX_74 */
3706 {
3707 { "(bad)", { XX } },
3708 { "(bad)", { XX } },
3709 { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3710 { "(bad)", { XX } },
3711 },
3712
3713 /* PREFIX_VEX_75 */
3714 {
3715 { "(bad)", { XX } },
3716 { "(bad)", { XX } },
3717 { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3718 { "(bad)", { XX } },
3719 },
3720
3721 /* PREFIX_VEX_76 */
3722 {
3723 { "(bad)", { XX } },
3724 { "(bad)", { XX } },
3725 { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3726 { "(bad)", { XX } },
3727 },
3728
3729 /* PREFIX_VEX_77 */
3730 {
3731 { "", { VZERO } },
3732 { "(bad)", { XX } },
3733 { "(bad)", { XX } },
3734 { "(bad)", { XX } },
3735 },
3736
3737 /* PREFIX_VEX_7C */
3738 {
3739 { "(bad)", { XX } },
3740 { "(bad)", { XX } },
3741 { "vhaddpd", { XM, Vex, EXx } },
3742 { "vhaddps", { XM, Vex, EXx } },
3743 },
3744
3745 /* PREFIX_VEX_7D */
3746 {
3747 { "(bad)", { XX } },
3748 { "(bad)", { XX } },
3749 { "vhsubpd", { XM, Vex, EXx } },
3750 { "vhsubps", { XM, Vex, EXx } },
3751 },
3752
3753 /* PREFIX_VEX_7E */
3754 {
3755 { "(bad)", { XX } },
3756 { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3757 { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3758 { "(bad)", { XX } },
3759 },
3760
3761 /* PREFIX_VEX_7F */
3762 {
3763 { "(bad)", { XX } },
b6169b20
L		 3764 { "vmovdqu", { EXxS, XM } },
3765 { "vmovdqa", { EXxS, XM } },
c0f3af97
L		 3766 { "(bad)", { XX } },
3767 },
3768
3769 /* PREFIX_VEX_C2 */
3770 {
3771 { "vcmpps", { XM, Vex, EXx, VCMP } },
3772 { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3773 { "vcmppd", { XM, Vex, EXx, VCMP } },
3774 { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3775 },
3776
3777 /* PREFIX_VEX_C4 */
3778 {
3779 { "(bad)", { XX } },
3780 { "(bad)", { XX } },
3781 { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3782 { "(bad)", { XX } },
3783 },
3784
3785 /* PREFIX_VEX_C5 */
3786 {
3787 { "(bad)", { XX } },
3788 { "(bad)", { XX } },
3789 { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3790 { "(bad)", { XX } },
3791 },
3792
3793 /* PREFIX_VEX_D0 */
3794 {
3795 { "(bad)", { XX } },
3796 { "(bad)", { XX } },
3797 { "vaddsubpd", { XM, Vex, EXx } },
3798 { "vaddsubps", { XM, Vex, EXx } },
3799 },
3800
3801 /* PREFIX_VEX_D1 */
3802 {
3803 { "(bad)", { XX } },
3804 { "(bad)", { XX } },
3805 { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3806 { "(bad)", { XX } },
3807 },
3808
3809 /* PREFIX_VEX_D2 */
3810 {
3811 { "(bad)", { XX } },
3812 { "(bad)", { XX } },
3813 { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3814 { "(bad)", { XX } },
3815 },
3816
3817 /* PREFIX_VEX_D3 */
3818 {
3819 { "(bad)", { XX } },
3820 { "(bad)", { XX } },
3821 { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3822 { "(bad)", { XX } },
3823 },
3824
3825 /* PREFIX_VEX_D4 */
3826 {
3827 { "(bad)", { XX } },
3828 { "(bad)", { XX } },
3829 { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
3830 { "(bad)", { XX } },
3831 },
3832
3833 /* PREFIX_VEX_D5 */
3834 {
3835 { "(bad)", { XX } },
3836 { "(bad)", { XX } },
3837 { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
3838 { "(bad)", { XX } },
3839 },
3840
3841 /* PREFIX_VEX_D6 */
3842 {
3843 { "(bad)", { XX } },
3844 { "(bad)", { XX } },
3845 { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
3846 { "(bad)", { XX } },
3847 },
3848
3849 /* PREFIX_VEX_D7 */
3850 {
3851 { "(bad)", { XX } },
3852 { "(bad)", { XX } },
3853 { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
3854 { "(bad)", { XX } },
3855 },
3856
3857 /* PREFIX_VEX_D8 */
3858 {
3859 { "(bad)", { XX } },
3860 { "(bad)", { XX } },
3861 { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
3862 { "(bad)", { XX } },
3863 },
3864
3865 /* PREFIX_VEX_D9 */
3866 {
3867 { "(bad)", { XX } },
3868 { "(bad)", { XX } },
3869 { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
3870 { "(bad)", { XX } },
3871 },
3872
3873 /* PREFIX_VEX_DA */
3874 {
3875 { "(bad)", { XX } },
3876 { "(bad)", { XX } },
3877 { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
3878 { "(bad)", { XX } },
3879 },
3880
3881 /* PREFIX_VEX_DB */
3882 {
3883 { "(bad)", { XX } },
3884 { "(bad)", { XX } },
3885 { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
3886 { "(bad)", { XX } },
3887 },
3888
3889 /* PREFIX_VEX_DC */
3890 {
3891 { "(bad)", { XX } },
3892 { "(bad)", { XX } },
3893 { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
3894 { "(bad)", { XX } },
3895 },
3896
3897 /* PREFIX_VEX_DD */
3898 {
3899 { "(bad)", { XX } },
3900 { "(bad)", { XX } },
3901 { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
3902 { "(bad)", { XX } },
3903 },
3904
3905 /* PREFIX_VEX_DE */
3906 {
3907 { "(bad)", { XX } },
3908 { "(bad)", { XX } },
3909 { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
3910 { "(bad)", { XX } },
3911 },
3912
3913 /* PREFIX_VEX_DF */
3914 {
3915 { "(bad)", { XX } },
3916 { "(bad)", { XX } },
3917 { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
3918 { "(bad)", { XX } },
3919 },
3920
3921 /* PREFIX_VEX_E0 */
3922 {
3923 { "(bad)", { XX } },
3924 { "(bad)", { XX } },
3925 { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
3926 { "(bad)", { XX } },
3927 },
3928
3929 /* PREFIX_VEX_E1 */
3930 {
3931 { "(bad)", { XX } },
3932 { "(bad)", { XX } },
3933 { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
3934 { "(bad)", { XX } },
3935 },
3936
3937 /* PREFIX_VEX_E2 */
3938 {
3939 { "(bad)", { XX } },
3940 { "(bad)", { XX } },
3941 { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
3942 { "(bad)", { XX } },
3943 },
3944
3945 /* PREFIX_VEX_E3 */
3946 {
3947 { "(bad)", { XX } },
3948 { "(bad)", { XX } },
3949 { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
3950 { "(bad)", { XX } },
3951 },
3952
3953 /* PREFIX_VEX_E4 */
3954 {
3955 { "(bad)", { XX } },
3956 { "(bad)", { XX } },
3957 { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
3958 { "(bad)", { XX } },
3959 },
3960
3961 /* PREFIX_VEX_E5 */
3962 {
3963 { "(bad)", { XX } },
3964 { "(bad)", { XX } },
3965 { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
3966 { "(bad)", { XX } },
3967 },
3968
3969 /* PREFIX_VEX_E6 */
3970 {
3971 { "(bad)", { XX } },
3972 { "vcvtdq2pd", { XM, EXxmmq } },
3973 { "vcvttpd2dq%XY", { XMM, EXx } },
3974 { "vcvtpd2dq%XY", { XMM, EXx } },
3975 },
3976
3977 /* PREFIX_VEX_E7 */
3978 {
3979 { "(bad)", { XX } },
3980 { "(bad)", { XX } },
3981 { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
3982 { "(bad)", { XX } },
3983 },
3984
3985 /* PREFIX_VEX_E8 */
3986 {
3987 { "(bad)", { XX } },
3988 { "(bad)", { XX } },
3989 { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
3990 { "(bad)", { XX } },
3991 },
3992
3993 /* PREFIX_VEX_E9 */
3994 {
3995 { "(bad)", { XX } },
3996 { "(bad)", { XX } },
3997 { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
3998 { "(bad)", { XX } },
3999 },
4000
4001 /* PREFIX_VEX_EA */
4002 {
4003 { "(bad)", { XX } },
4004 { "(bad)", { XX } },
4005 { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
4006 { "(bad)", { XX } },
4007 },
4008
4009 /* PREFIX_VEX_EB */
4010 {
4011 { "(bad)", { XX } },
4012 { "(bad)", { XX } },
4013 { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
4014 { "(bad)", { XX } },
4015 },
4016
4017 /* PREFIX_VEX_EC */
4018 {
4019 { "(bad)", { XX } },
4020 { "(bad)", { XX } },
4021 { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
4022 { "(bad)", { XX } },
4023 },
4024
4025 /* PREFIX_VEX_ED */
4026 {
4027 { "(bad)", { XX } },
4028 { "(bad)", { XX } },
4029 { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
4030 { "(bad)", { XX } },
4031 },
4032
4033 /* PREFIX_VEX_EE */
4034 {
4035 { "(bad)", { XX } },
4036 { "(bad)", { XX } },
4037 { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4038 { "(bad)", { XX } },
4039 },
4040
4041 /* PREFIX_VEX_EF */
4042 {
4043 { "(bad)", { XX } },
4044 { "(bad)", { XX } },
4045 { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4046 { "(bad)", { XX } },
4047 },
4048
4049 /* PREFIX_VEX_F0 */
4050 {
4051 { "(bad)", { XX } },
4052 { "(bad)", { XX } },
4053 { "(bad)", { XX } },
4054 { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4055 },
4056
4057 /* PREFIX_VEX_F1 */
4058 {
4059 { "(bad)", { XX } },
4060 { "(bad)", { XX } },
4061 { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4062 { "(bad)", { XX } },
4063 },
4064
4065 /* PREFIX_VEX_F2 */
4066 {
4067 { "(bad)", { XX } },
4068 { "(bad)", { XX } },
4069 { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4070 { "(bad)", { XX } },
4071 },
4072
4073 /* PREFIX_VEX_F3 */
4074 {
4075 { "(bad)", { XX } },
4076 { "(bad)", { XX } },
4077 { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4078 { "(bad)", { XX } },
4079 },
4080
4081 /* PREFIX_VEX_F4 */
4082 {
4083 { "(bad)", { XX } },
4084 { "(bad)", { XX } },
4085 { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4086 { "(bad)", { XX } },
4087 },
4088
4089 /* PREFIX_VEX_F5 */
4090 {
4091 { "(bad)", { XX } },
4092 { "(bad)", { XX } },
4093 { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4094 { "(bad)", { XX } },
4095 },
4096
4097 /* PREFIX_VEX_F6 */
4098 {
4099 { "(bad)", { XX } },
4100 { "(bad)", { XX } },
4101 { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4102 { "(bad)", { XX } },
4103 },
4104
4105 /* PREFIX_VEX_F7 */
4106 {
4107 { "(bad)", { XX } },
4108 { "(bad)", { XX } },
4109 { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4110 { "(bad)", { XX } },
4111 },
4112
4113 /* PREFIX_VEX_F8 */
4114 {
4115 { "(bad)", { XX } },
4116 { "(bad)", { XX } },
4117 { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4118 { "(bad)", { XX } },
4119 },
4120
4121 /* PREFIX_VEX_F9 */
4122 {
4123 { "(bad)", { XX } },
4124 { "(bad)", { XX } },
4125 { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4126 { "(bad)", { XX } },
4127 },
4128
4129 /* PREFIX_VEX_FA */
4130 {
4131 { "(bad)", { XX } },
4132 { "(bad)", { XX } },
4133 { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4134 { "(bad)", { XX } },
4135 },
4136
4137 /* PREFIX_VEX_FB */
4138 {
4139 { "(bad)", { XX } },
4140 { "(bad)", { XX } },
4141 { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4142 { "(bad)", { XX } },
4143 },
4144
4145 /* PREFIX_VEX_FC */
4146 {
4147 { "(bad)", { XX } },
4148 { "(bad)", { XX } },
4149 { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4150 { "(bad)", { XX } },
4151 },
4152
4153 /* PREFIX_VEX_FD */
4154 {
4155 { "(bad)", { XX } },
4156 { "(bad)", { XX } },
4157 { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4158 { "(bad)", { XX } },
4159 },
4160
4161 /* PREFIX_VEX_FE */
4162 {
4163 { "(bad)", { XX } },
4164 { "(bad)", { XX } },
4165 { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4166 { "(bad)", { XX } },
4167 },
4168
4169 /* PREFIX_VEX_3800 */
4170 {
4171 { "(bad)", { XX } },
4172 { "(bad)", { XX } },
4173 { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4174 { "(bad)", { XX } },
4175 },
4176
4177 /* PREFIX_VEX_3801 */
4178 {
4179 { "(bad)", { XX } },
4180 { "(bad)", { XX } },
4181 { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4182 { "(bad)", { XX } },
4183 },
4184
4185 /* PREFIX_VEX_3802 */
4186 {
4187 { "(bad)", { XX } },
4188 { "(bad)", { XX } },
4189 { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4190 { "(bad)", { XX } },
4191 },
4192
4193 /* PREFIX_VEX_3803 */
4194 {
4195 { "(bad)", { XX } },
4196 { "(bad)", { XX } },
4197 { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4198 { "(bad)", { XX } },
4199 },
4200
4201 /* PREFIX_VEX_3804 */
4202 {
4203 { "(bad)", { XX } },
4204 { "(bad)", { XX } },
4205 { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4206 { "(bad)", { XX } },
4207 },
4208
4209 /* PREFIX_VEX_3805 */
4210 {
4211 { "(bad)", { XX } },
4212 { "(bad)", { XX } },
4213 { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4214 { "(bad)", { XX } },
4215 },
4216
4217 /* PREFIX_VEX_3806 */
4218 {
4219 { "(bad)", { XX } },
4220 { "(bad)", { XX } },
4221 { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4222 { "(bad)", { XX } },
4223 },
4224
4225 /* PREFIX_VEX_3807 */
4226 {
4227 { "(bad)", { XX } },
4228 { "(bad)", { XX } },
4229 { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4230 { "(bad)", { XX } },
4231 },
4232
4233 /* PREFIX_VEX_3808 */
4234 {
4235 { "(bad)", { XX } },
4236 { "(bad)", { XX } },
4237 { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4238 { "(bad)", { XX } },
4239 },
4240
4241 /* PREFIX_VEX_3809 */
4242 {
4243 { "(bad)", { XX } },
4244 { "(bad)", { XX } },
4245 { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4246 { "(bad)", { XX } },
4247 },
4248
4249 /* PREFIX_VEX_380A */
4250 {
4251 { "(bad)", { XX } },
4252 { "(bad)", { XX } },
4253 { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4254 { "(bad)", { XX } },
4255 },
4256
4257 /* PREFIX_VEX_380B */
4258 {
4259 { "(bad)", { XX } },
4260 { "(bad)", { XX } },
4261 { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4262 { "(bad)", { XX } },
4263 },
4264
4265 /* PREFIX_VEX_380C */
4266 {
4267 { "(bad)", { XX } },
4268 { "(bad)", { XX } },
4269 { "vpermilps", { XM, Vex, EXx } },
4270 { "(bad)", { XX } },
4271 },
4272
4273 /* PREFIX_VEX_380D */
4274 {
4275 { "(bad)", { XX } },
4276 { "(bad)", { XX } },
4277 { "vpermilpd", { XM, Vex, EXx } },
4278 { "(bad)", { XX } },
4279 },
4280
4281 /* PREFIX_VEX_380E */
4282 {
4283 { "(bad)", { XX } },
4284 { "(bad)", { XX } },
4285 { "vtestps", { XM, EXx } },
4286 { "(bad)", { XX } },
4287 },
4288
4289 /* PREFIX_VEX_380F */
4290 {
4291 { "(bad)", { XX } },
4292 { "(bad)", { XX } },
4293 { "vtestpd", { XM, EXx } },
4294 { "(bad)", { XX } },
4295 },
4296
4297 /* PREFIX_VEX_3817 */
4298 {
4299 { "(bad)", { XX } },
4300 { "(bad)", { XX } },
4301 { "vptest", { XM, EXx } },
4302 { "(bad)", { XX } },
4303 },
4304
4305 /* PREFIX_VEX_3818 */
4306 {
4307 { "(bad)", { XX } },
4308 { "(bad)", { XX } },
4309 { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4310 { "(bad)", { XX } },
4311 },
4312
4313 /* PREFIX_VEX_3819 */
4314 {
4315 { "(bad)", { XX } },
4316 { "(bad)", { XX } },
4317 { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4318 { "(bad)", { XX } },
4319 },
4320
4321 /* PREFIX_VEX_381A */
4322 {
4323 { "(bad)", { XX } },
4324 { "(bad)", { XX } },
4325 { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4326 { "(bad)", { XX } },
4327 },
4328
4329 /* PREFIX_VEX_381C */
4330 {
4331 { "(bad)", { XX } },
4332 { "(bad)", { XX } },
4333 { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4334 { "(bad)", { XX } },
4335 },
4336
4337 /* PREFIX_VEX_381D */
4338 {
4339 { "(bad)", { XX } },
4340 { "(bad)", { XX } },
4341 { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4342 { "(bad)", { XX } },
4343 },
4344
4345 /* PREFIX_VEX_381E */
4346 {
4347 { "(bad)", { XX } },
4348 { "(bad)", { XX } },
4349 { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4350 { "(bad)", { XX } },
4351 },
4352
4353 /* PREFIX_VEX_3820 */
4354 {
4355 { "(bad)", { XX } },
4356 { "(bad)", { XX } },
4357 { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4358 { "(bad)", { XX } },
4359 },
4360
4361 /* PREFIX_VEX_3821 */
4362 {
4363 { "(bad)", { XX } },
4364 { "(bad)", { XX } },
4365 { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4366 { "(bad)", { XX } },
4367 },
4368
4369 /* PREFIX_VEX_3822 */
4370 {
4371 { "(bad)", { XX } },
4372 { "(bad)", { XX } },
4373 { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4374 { "(bad)", { XX } },
4375 },
4376
4377 /* PREFIX_VEX_3823 */
4378 {
4379 { "(bad)", { XX } },
4380 { "(bad)", { XX } },
4381 { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4382 { "(bad)", { XX } },
4383 },
4384
4385 /* PREFIX_VEX_3824 */
4386 {
4387 { "(bad)", { XX } },
4388 { "(bad)", { XX } },
4389 { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4390 { "(bad)", { XX } },
4391 },
4392
4393 /* PREFIX_VEX_3825 */
4394 {
4395 { "(bad)", { XX } },
4396 { "(bad)", { XX } },
4397 { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4398 { "(bad)", { XX } },
4399 },
4400
4401 /* PREFIX_VEX_3828 */
4402 {
4403 { "(bad)", { XX } },
4404 { "(bad)", { XX } },
4405 { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4406 { "(bad)", { XX } },
4407 },
4408
4409 /* PREFIX_VEX_3829 */
4410 {
4411 { "(bad)", { XX } },
4412 { "(bad)", { XX } },
4413 { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4414 { "(bad)", { XX } },
4415 },
4416
4417 /* PREFIX_VEX_382A */
4418 {
4419 { "(bad)", { XX } },
4420 { "(bad)", { XX } },
4421 { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4422 { "(bad)", { XX } },
4423 },
4424
4425 /* PREFIX_VEX_382B */
4426 {
4427 { "(bad)", { XX } },
4428 { "(bad)", { XX } },
4429 { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4430 { "(bad)", { XX } },
4431 },
4432
4433 /* PREFIX_VEX_382C */
4434 {
4435 { "(bad)", { XX } },
4436 { "(bad)", { XX } },
4437 { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4438 { "(bad)", { XX } },
4439 },
4440
4441 /* PREFIX_VEX_382D */
4442 {
4443 { "(bad)", { XX } },
4444 { "(bad)", { XX } },
4445 { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4446 { "(bad)", { XX } },
4447 },
4448
4449 /* PREFIX_VEX_382E */
4450 {
4451 { "(bad)", { XX } },
4452 { "(bad)", { XX } },
4453 { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4454 { "(bad)", { XX } },
4455 },
4456
4457 /* PREFIX_VEX_382F */
4458 {
4459 { "(bad)", { XX } },
4460 { "(bad)", { XX } },
4461 { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4462 { "(bad)", { XX } },
4463 },
4464
4465 /* PREFIX_VEX_3830 */
4466 {
4467 { "(bad)", { XX } },
4468 { "(bad)", { XX } },
4469 { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4470 { "(bad)", { XX } },
4471 },
4472
4473 /* PREFIX_VEX_3831 */
4474 {
4475 { "(bad)", { XX } },
4476 { "(bad)", { XX } },
4477 { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4478 { "(bad)", { XX } },
4479 },
4480
4481 /* PREFIX_VEX_3832 */
4482 {
4483 { "(bad)", { XX } },
4484 { "(bad)", { XX } },
4485 { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4486 { "(bad)", { XX } },
4487 },
4488
4489 /* PREFIX_VEX_3833 */
4490 {
4491 { "(bad)", { XX } },
4492 { "(bad)", { XX } },
4493 { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4494 { "(bad)", { XX } },
4495 },
4496
4497 /* PREFIX_VEX_3834 */
4498 {
4499 { "(bad)", { XX } },
4500 { "(bad)", { XX } },
4501 { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4502 { "(bad)", { XX } },
4503 },
4504
4505 /* PREFIX_VEX_3835 */
4506 {
4507 { "(bad)", { XX } },
4508 { "(bad)", { XX } },
4509 { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4510 { "(bad)", { XX } },
4511 },
4512
4513 /* PREFIX_VEX_3837 */
4514 {
4515 { "(bad)", { XX } },
4516 { "(bad)", { XX } },
4517 { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4518 { "(bad)", { XX } },
4519 },
4520
4521 /* PREFIX_VEX_3838 */
4522 {
4523 { "(bad)", { XX } },
4524 { "(bad)", { XX } },
4525 { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4526 { "(bad)", { XX } },
4527 },
4528
4529 /* PREFIX_VEX_3839 */
4530 {
4531 { "(bad)", { XX } },
4532 { "(bad)", { XX } },
4533 { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4534 { "(bad)", { XX } },
4535 },
4536
4537 /* PREFIX_VEX_383A */
4538 {
4539 { "(bad)", { XX } },
4540 { "(bad)", { XX } },
4541 { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4542 { "(bad)", { XX } },
4543 },
4544
4545 /* PREFIX_VEX_383B */
4546 {
4547 { "(bad)", { XX } },
4548 { "(bad)", { XX } },
4549 { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4550 { "(bad)", { XX } },
4551 },
4552
4553 /* PREFIX_VEX_383C */
4554 {
4555 { "(bad)", { XX } },
4556 { "(bad)", { XX } },
4557 { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4558 { "(bad)", { XX } },
4559 },
4560
4561 /* PREFIX_VEX_383D */
4562 {
4563 { "(bad)", { XX } },
4564 { "(bad)", { XX } },
4565 { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4566 { "(bad)", { XX } },
4567 },
4568
4569 /* PREFIX_VEX_383E */
4570 {
4571 { "(bad)", { XX } },
4572 { "(bad)", { XX } },
4573 { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4574 { "(bad)", { XX } },
4575 },
4576
4577 /* PREFIX_VEX_383F */
4578 {
4579 { "(bad)", { XX } },
4580 { "(bad)", { XX } },
4581 { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4582 { "(bad)", { XX } },
4583 },
4584
4585 /* PREFIX_VEX_3840 */
4586 {
4587 { "(bad)", { XX } },
4588 { "(bad)", { XX } },
4589 { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4590 { "(bad)", { XX } },
4591 },
4592
4593 /* PREFIX_VEX_3841 */
4594 {
4595 { "(bad)", { XX } },
4596 { "(bad)", { XX } },
4597 { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4598 { "(bad)", { XX } },
4599 },
4600
0bfee649 4601 /* PREFIX_VEX_3896 */
a5ff0eb2
L		 4602 {
4603 { "(bad)", { XX } },
4604 { "(bad)", { XX } },
0bfee649 4605 { "vfmaddsub132p%XW", { XM, Vex, EXx } },
a5ff0eb2
L		 4606 { "(bad)", { XX } },
4607 },
4608
0bfee649 4609 /* PREFIX_VEX_3897 */
a5ff0eb2
L		 4610 {
4611 { "(bad)", { XX } },
4612 { "(bad)", { XX } },
0bfee649 4613 { "vfmsubadd132p%XW", { XM, Vex, EXx } },
a5ff0eb2
L		 4614 { "(bad)", { XX } },
4615 },
4616
0bfee649 4617 /* PREFIX_VEX_3898 */
a5ff0eb2
L		 4618 {
4619 { "(bad)", { XX } },
4620 { "(bad)", { XX } },
0bfee649 4621 { "vfmadd132p%XW", { XM, Vex, EXx } },
a5ff0eb2
L		 4622 { "(bad)", { XX } },
4623 },
4624
0bfee649 4625 /* PREFIX_VEX_3899 */
a5ff0eb2
L		 4626 {
4627 { "(bad)", { XX } },
4628 { "(bad)", { XX } },
0bfee649 4629 { "vfmadd132s%XW", { XM, Vex, EXVexWdq } },
a5ff0eb2
L		 4630 { "(bad)", { XX } },
4631 },
4632
0bfee649 4633 /* PREFIX_VEX_389A */
a5ff0eb2
L		 4634 {
4635 { "(bad)", { XX } },
4636 { "(bad)", { XX } },
0bfee649 4637 { "vfmsub132p%XW", { XM, Vex, EXx } },
a5ff0eb2
L		 4638 { "(bad)", { XX } },
4639 },
4640
0bfee649 4641 /* PREFIX_VEX_389B */
c0f3af97
L		 4642 {
4643 { "(bad)", { XX } },
4644 { "(bad)", { XX } },
0bfee649 4645 { "vfmsub132s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4646 { "(bad)", { XX } },
4647 },
4648
0bfee649 4649 /* PREFIX_VEX_389C */
c0f3af97
L		 4650 {
4651 { "(bad)", { XX } },
4652 { "(bad)", { XX } },
0bfee649 4653 { "vfnmadd132p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4654 { "(bad)", { XX } },
4655 },
4656
0bfee649 4657 /* PREFIX_VEX_389D */
c0f3af97
L		 4658 {
4659 { "(bad)", { XX } },
4660 { "(bad)", { XX } },
0bfee649 4661 { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4662 { "(bad)", { XX } },
4663 },
4664
0bfee649 4665 /* PREFIX_VEX_389E */
c0f3af97
L		 4666 {
4667 { "(bad)", { XX } },
4668 { "(bad)", { XX } },
0bfee649 4669 { "vfnmsub132p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4670 { "(bad)", { XX } },
4671 },
4672
0bfee649 4673 /* PREFIX_VEX_389F */
c0f3af97
L		 4674 {
4675 { "(bad)", { XX } },
4676 { "(bad)", { XX } },
0bfee649 4677 { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4678 { "(bad)", { XX } },
4679 },
4680
0bfee649 4681 /* PREFIX_VEX_38A6 */
c0f3af97
L		 4682 {
4683 { "(bad)", { XX } },
4684 { "(bad)", { XX } },
0bfee649 4685 { "vfmaddsub213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4686 { "(bad)", { XX } },
4687 },
4688
0bfee649 4689 /* PREFIX_VEX_38A7 */
c0f3af97
L		 4690 {
4691 { "(bad)", { XX } },
4692 { "(bad)", { XX } },
0bfee649 4693 { "vfmsubadd213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4694 { "(bad)", { XX } },
4695 },
4696
0bfee649 4697 /* PREFIX_VEX_38A8 */
c0f3af97
L		 4698 {
4699 { "(bad)", { XX } },
4700 { "(bad)", { XX } },
0bfee649 4701 { "vfmadd213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4702 { "(bad)", { XX } },
4703 },
4704
0bfee649 4705 /* PREFIX_VEX_38A9 */
c0f3af97
L		 4706 {
4707 { "(bad)", { XX } },
4708 { "(bad)", { XX } },
0bfee649 4709 { "vfmadd213s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4710 { "(bad)", { XX } },
4711 },
4712
0bfee649 4713 /* PREFIX_VEX_38AA */
c0f3af97
L		 4714 {
4715 { "(bad)", { XX } },
4716 { "(bad)", { XX } },
0bfee649 4717 { "vfmsub213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4718 { "(bad)", { XX } },
4719 },
4720
0bfee649 4721 /* PREFIX_VEX_38AB */
c0f3af97
L		 4722 {
4723 { "(bad)", { XX } },
4724 { "(bad)", { XX } },
0bfee649 4725 { "vfmsub213s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4726 { "(bad)", { XX } },
4727 },
4728
0bfee649 4729 /* PREFIX_VEX_38AC */
c0f3af97
L		 4730 {
4731 { "(bad)", { XX } },
4732 { "(bad)", { XX } },
0bfee649 4733 { "vfnmadd213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4734 { "(bad)", { XX } },
4735 },
4736
0bfee649 4737 /* PREFIX_VEX_38AD */
c0f3af97
L		 4738 {
4739 { "(bad)", { XX } },
4740 { "(bad)", { XX } },
0bfee649 4741 { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4742 { "(bad)", { XX } },
4743 },
4744
0bfee649 4745 /* PREFIX_VEX_38AE */
c0f3af97
L		 4746 {
4747 { "(bad)", { XX } },
4748 { "(bad)", { XX } },
0bfee649 4749 { "vfnmsub213p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4750 { "(bad)", { XX } },
4751 },
4752
0bfee649 4753 /* PREFIX_VEX_38AF */
c0f3af97
L		 4754 {
4755 { "(bad)", { XX } },
4756 { "(bad)", { XX } },
0bfee649 4757 { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4758 { "(bad)", { XX } },
4759 },
4760
0bfee649 4761 /* PREFIX_VEX_38B6 */
c0f3af97
L		 4762 {
4763 { "(bad)", { XX } },
4764 { "(bad)", { XX } },
0bfee649 4765 { "vfmaddsub231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4766 { "(bad)", { XX } },
4767 },
4768
0bfee649 4769 /* PREFIX_VEX_38B7 */
c0f3af97
L		 4770 {
4771 { "(bad)", { XX } },
4772 { "(bad)", { XX } },
0bfee649 4773 { "vfmsubadd231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4774 { "(bad)", { XX } },
4775 },
4776
0bfee649 4777 /* PREFIX_VEX_38B8 */
c0f3af97
L		 4778 {
4779 { "(bad)", { XX } },
4780 { "(bad)", { XX } },
0bfee649 4781 { "vfmadd231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4782 { "(bad)", { XX } },
4783 },
4784
0bfee649 4785 /* PREFIX_VEX_38B9 */
c0f3af97
L		 4786 {
4787 { "(bad)", { XX } },
4788 { "(bad)", { XX } },
0bfee649 4789 { "vfmadd231s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4790 { "(bad)", { XX } },
4791 },
4792
0bfee649 4793 /* PREFIX_VEX_38BA */
c0f3af97
L		 4794 {
4795 { "(bad)", { XX } },
4796 { "(bad)", { XX } },
0bfee649 4797 { "vfmsub231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4798 { "(bad)", { XX } },
4799 },
4800
0bfee649 4801 /* PREFIX_VEX_38BB */
c0f3af97
L		 4802 {
4803 { "(bad)", { XX } },
4804 { "(bad)", { XX } },
0bfee649 4805 { "vfmsub231s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4806 { "(bad)", { XX } },
4807 },
4808
0bfee649 4809 /* PREFIX_VEX_38BC */
c0f3af97
L		 4810 {
4811 { "(bad)", { XX } },
4812 { "(bad)", { XX } },
0bfee649 4813 { "vfnmadd231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4814 { "(bad)", { XX } },
4815 },
4816
0bfee649 4817 /* PREFIX_VEX_38BD */
c0f3af97
L		 4818 {
4819 { "(bad)", { XX } },
4820 { "(bad)", { XX } },
0bfee649 4821 { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4822 { "(bad)", { XX } },
4823 },
4824
0bfee649 4825 /* PREFIX_VEX_38BE */
c0f3af97
L		 4826 {
4827 { "(bad)", { XX } },
4828 { "(bad)", { XX } },
0bfee649 4829 { "vfnmsub231p%XW", { XM, Vex, EXx } },
c0f3af97
L		 4830 { "(bad)", { XX } },
4831 },
4832
0bfee649 4833 /* PREFIX_VEX_38BF */
c0f3af97
L		 4834 {
4835 { "(bad)", { XX } },
4836 { "(bad)", { XX } },
0bfee649 4837 { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } },
c0f3af97
L		 4838 { "(bad)", { XX } },
4839 },
4840
0bfee649 4841 /* PREFIX_VEX_38DB */
c0f3af97
L		 4842 {
4843 { "(bad)", { XX } },
4844 { "(bad)", { XX } },
0bfee649 4845 { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
c0f3af97
L		 4846 { "(bad)", { XX } },
4847 },
4848
0bfee649 4849 /* PREFIX_VEX_38DC */
c0f3af97
L		 4850 {
4851 { "(bad)", { XX } },
4852 { "(bad)", { XX } },
0bfee649 4853 { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
c0f3af97
L		 4854 { "(bad)", { XX } },
4855 },
4856
0bfee649 4857 /* PREFIX_VEX_38DD */
c0f3af97
L		 4858 {
4859 { "(bad)", { XX } },
4860 { "(bad)", { XX } },
0bfee649 4861 { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
c0f3af97
L		 4862 { "(bad)", { XX } },
4863 },
4864
0bfee649 4865 /* PREFIX_VEX_38DE */
c0f3af97
L		 4866 {
4867 { "(bad)", { XX } },
4868 { "(bad)", { XX } },
0bfee649 4869 { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
c0f3af97
L		 4870 { "(bad)", { XX } },
4871 },
4872
0bfee649 4873 /* PREFIX_VEX_38DF */
c0f3af97
L		 4874 {
4875 { "(bad)", { XX } },
4876 { "(bad)", { XX } },
0bfee649 4877 { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
c0f3af97
L		 4878 { "(bad)", { XX } },
4879 },
4880
0bfee649 4881 /* PREFIX_VEX_3A04 */
c0f3af97
L		 4882 {
4883 { "(bad)", { XX } },
4884 { "(bad)", { XX } },
0bfee649 4885 { "vpermilps", { XM, EXx, Ib } },
c0f3af97
L		 4886 { "(bad)", { XX } },
4887 },
4888
0bfee649 4889 /* PREFIX_VEX_3A05 */
c0f3af97
L		 4890 {
4891 { "(bad)", { XX } },
4892 { "(bad)", { XX } },
0bfee649 4893 { "vpermilpd", { XM, EXx, Ib } },
c0f3af97
L		 4894 { "(bad)", { XX } },
4895 },
4896
0bfee649 4897 /* PREFIX_VEX_3A06 */
c0f3af97
L		 4898 {
4899 { "(bad)", { XX } },
4900 { "(bad)", { XX } },
0bfee649 4901 { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
c0f3af97
L		 4902 { "(bad)", { XX } },
4903 },
4904
0bfee649 4905 /* PREFIX_VEX_3A08 */
c0f3af97
L		 4906 {
4907 { "(bad)", { XX } },
4908 { "(bad)", { XX } },
0bfee649 4909 { "vroundps", { XM, EXx, Ib } },
c0f3af97
L		 4910 { "(bad)", { XX } },
4911 },
4912
0bfee649 4913 /* PREFIX_VEX_3A09 */
c0f3af97
L		 4914 {
4915 { "(bad)", { XX } },
4916 { "(bad)", { XX } },
0bfee649 4917 { "vroundpd", { XM, EXx, Ib } },
c0f3af97
L		 4918 { "(bad)", { XX } },
4919 },
4920
0bfee649 4921 /* PREFIX_VEX_3A0A */
c0f3af97
L		 4922 {
4923 { "(bad)", { XX } },
4924 { "(bad)", { XX } },
0bfee649
L		 4925 { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4926 { "(bad)", { XX } },
4927 },
4928
4929 /* PREFIX_VEX_3A0B */
4930 {
4931 { "(bad)", { XX } },
4932 { "(bad)", { XX } },
4933 { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4934 { "(bad)", { XX } },
4935 },
4936
4937 /* PREFIX_VEX_3A0C */
4938 {
4939 { "(bad)", { XX } },
4940 { "(bad)", { XX } },
4941 { "vblendps", { XM, Vex, EXx, Ib } },
4942 { "(bad)", { XX } },
4943 },
4944
4945 /* PREFIX_VEX_3A0D */
4946 {
4947 { "(bad)", { XX } },
4948 { "(bad)", { XX } },
4949 { "vblendpd", { XM, Vex, EXx, Ib } },
c0f3af97
L		 4950 { "(bad)", { XX } },
4951 },
4952
0bfee649
L		 4953 /* PREFIX_VEX_3A0E */
4954 {
4955 { "(bad)", { XX } },
4956 { "(bad)", { XX } },
4957 { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4958 { "(bad)", { XX } },
4959 },
4960
4961 /* PREFIX_VEX_3A0F */
4962 {
4963 { "(bad)", { XX } },
4964 { "(bad)", { XX } },
4965 { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
4966 { "(bad)", { XX } },
4967 },
4968
4969 /* PREFIX_VEX_3A14 */
4970 {
4971 { "(bad)", { XX } },
4972 { "(bad)", { XX } },
4973 { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
4974 { "(bad)", { XX } },
4975 },
4976
4977 /* PREFIX_VEX_3A15 */
4978 {
4979 { "(bad)", { XX } },
4980 { "(bad)", { XX } },
4981 { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
4982 { "(bad)", { XX } },
4983 },
4984
4985 /* PREFIX_VEX_3A16 */
c0f3af97
L		 4986 {
4987 { "(bad)", { XX } },
4988 { "(bad)", { XX } },
0bfee649 4989 { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
c0f3af97
L		 4990 { "(bad)", { XX } },
4991 },
4992
0bfee649 4993 /* PREFIX_VEX_3A17 */
c0f3af97
L		 4994 {
4995 { "(bad)", { XX } },
4996 { "(bad)", { XX } },
0bfee649 4997 { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
c0f3af97
L		 4998 { "(bad)", { XX } },
4999 },
5000
0bfee649 5001 /* PREFIX_VEX_3A18 */
c0f3af97
L		 5002 {
5003 { "(bad)", { XX } },
5004 { "(bad)", { XX } },
0bfee649 5005 { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
c0f3af97
L		 5006 { "(bad)", { XX } },
5007 },
5008
0bfee649 5009 /* PREFIX_VEX_3A19 */
c0f3af97
L		 5010 {
5011 { "(bad)", { XX } },
5012 { "(bad)", { XX } },
0bfee649 5013 { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
c0f3af97
L		 5014 { "(bad)", { XX } },
5015 },
5016
0bfee649 5017 /* PREFIX_VEX_3A20 */
c0f3af97
L		 5018 {
5019 { "(bad)", { XX } },
5020 { "(bad)", { XX } },
0bfee649 5021 { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
c0f3af97
L		 5022 { "(bad)", { XX } },
5023 },
5024
0bfee649 5025 /* PREFIX_VEX_3A21 */
c0f3af97
L		 5026 {
5027 { "(bad)", { XX } },
5028 { "(bad)", { XX } },
0bfee649 5029 { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
c0f3af97
L		 5030 { "(bad)", { XX } },
5031 },
5032
0bfee649
L		 5033 /* PREFIX_VEX_3A22 */
5034 {
5035 { "(bad)", { XX } },
5036 { "(bad)", { XX } },
5037 { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
5038 { "(bad)", { XX } },
5039 },
5040
5041 /* PREFIX_VEX_3A40 */
c0f3af97
L		 5042 {
5043 { "(bad)", { XX } },
5044 { "(bad)", { XX } },
0bfee649 5045 { "vdpps", { XM, Vex, EXx, Ib } },
c0f3af97
L		 5046 { "(bad)", { XX } },
5047 },
5048
0bfee649 5049 /* PREFIX_VEX_3A41 */
c0f3af97
L		 5050 {
5051 { "(bad)", { XX } },
5052 { "(bad)", { XX } },
0bfee649 5053 { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
c0f3af97
L		 5054 { "(bad)", { XX } },
5055 },
5056
0bfee649 5057 /* PREFIX_VEX_3A42 */
c0f3af97
L		 5058 {
5059 { "(bad)", { XX } },
5060 { "(bad)", { XX } },
0bfee649 5061 { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
c0f3af97
L		 5062 { "(bad)", { XX } },
5063 },
5064
ce2f5b3c
L		 5065 /* PREFIX_VEX_3A44 */
5066 {
5067 { "(bad)", { XX } },
5068 { "(bad)", { XX } },
5069 { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) },
5070 { "(bad)", { XX } },
5071 },
5072
0bfee649 5073 /* PREFIX_VEX_3A4A */
c0f3af97
L		 5074 {
5075 { "(bad)", { XX } },
5076 { "(bad)", { XX } },
0bfee649 5077 { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
c0f3af97
L		 5078 { "(bad)", { XX } },
5079 },
5080
0bfee649 5081 /* PREFIX_VEX_3A4B */
c0f3af97
L		 5082 {
5083 { "(bad)", { XX } },
5084 { "(bad)", { XX } },
0bfee649 5085 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
c0f3af97
L		 5086 { "(bad)", { XX } },
5087 },
5088
0bfee649 5089 /* PREFIX_VEX_3A4C */
c0f3af97
L		 5090 {
5091 { "(bad)", { XX } },
5092 { "(bad)", { XX } },
0bfee649 5093 { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
c0f3af97
L		 5094 { "(bad)", { XX } },
5095 },
5096
922d8de8
DR		 5097 /* PREFIX_VEX_3A5C */
5098 {
5099 { "(bad)", { XX } },
5100 { "(bad)", { XX } },
206c2556 5101 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5102 { "(bad)", { XX } },
5103 },
5104
5105 /* PREFIX_VEX_3A5D */
5106 {
5107 { "(bad)", { XX } },
5108 { "(bad)", { XX } },
206c2556 5109 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5110 { "(bad)", { XX } },
5111 },
5112
5113 /* PREFIX_VEX_3A5E */
5114 {
5115 { "(bad)", { XX } },
5116 { "(bad)", { XX } },
206c2556 5117 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5118 { "(bad)", { XX } },
5119 },
5120
5121 /* PREFIX_VEX_3A5F */
5122 {
5123 { "(bad)", { XX } },
5124 { "(bad)", { XX } },
206c2556 5125 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5126 { "(bad)", { XX } },
5127 },
5128
0bfee649 5129 /* PREFIX_VEX_3A60 */
c0f3af97
L		 5130 {
5131 { "(bad)", { XX } },
5132 { "(bad)", { XX } },
0bfee649 5133 { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
c0f3af97
L		 5134 { "(bad)", { XX } },
5135 },
5136
0bfee649 5137 /* PREFIX_VEX_3A61 */
c0f3af97
L		 5138 {
5139 { "(bad)", { XX } },
5140 { "(bad)", { XX } },
0bfee649 5141 { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
c0f3af97
L		 5142 { "(bad)", { XX } },
5143 },
5144
0bfee649 5145 /* PREFIX_VEX_3A62 */
c0f3af97
L		 5146 {
5147 { "(bad)", { XX } },
5148 { "(bad)", { XX } },
0bfee649 5149 { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
c0f3af97
L		 5150 { "(bad)", { XX } },
5151 },
5152
0bfee649 5153 /* PREFIX_VEX_3A63 */
c0f3af97
L		 5154 {
5155 { "(bad)", { XX } },
5156 { "(bad)", { XX } },
0bfee649 5157 { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
c0f3af97
L		 5158 { "(bad)", { XX } },
5159 },
a5ff0eb2 5160
922d8de8
DR		 5161 /* PREFIX_VEX_3A68 */
5162 {
5163 { "(bad)", { XX } },
5164 { "(bad)", { XX } },
206c2556 5165 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5166 { "(bad)", { XX } },
5167 },
5168
5169 /* PREFIX_VEX_3A69 */
5170 {
5171 { "(bad)", { XX } },
5172 { "(bad)", { XX } },
206c2556 5173 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5174 { "(bad)", { XX } },
5175 },
5176
5177 /* PREFIX_VEX_3A6A */
5178 {
5179 { "(bad)", { XX } },
5180 { "(bad)", { XX } },
5181 { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
5182 { "(bad)", { XX } },
5183 },
5184
5185 /* PREFIX_VEX_3A6B */
5186 {
5187 { "(bad)", { XX } },
5188 { "(bad)", { XX } },
5189 { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
5190 { "(bad)", { XX } },
5191 },
5192
5193 /* PREFIX_VEX_3A6C */
5194 {
5195 { "(bad)", { XX } },
5196 { "(bad)", { XX } },
206c2556 5197 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5198 { "(bad)", { XX } },
5199 },
5200
5201 /* PREFIX_VEX_3A6D */
5202 {
5203 { "(bad)", { XX } },
5204 { "(bad)", { XX } },
206c2556 5205 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5206 { "(bad)", { XX } },
5207 },
5208
5209 /* PREFIX_VEX_3A6E */
5210 {
5211 { "(bad)", { XX } },
5212 { "(bad)", { XX } },
5213 { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
5214 { "(bad)", { XX } },
5215 },
5216
5217 /* PREFIX_VEX_3A6F */
5218 {
5219 { "(bad)", { XX } },
5220 { "(bad)", { XX } },
5221 { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
5222 { "(bad)", { XX } },
5223 },
5224
5225 /* PREFIX_VEX_3A78 */
5226 {
5227 { "(bad)", { XX } },
5228 { "(bad)", { XX } },
206c2556 5229 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5230 { "(bad)", { XX } },
5231 },
5232
5233 /* PREFIX_VEX_3A79 */
5234 {
5235 { "(bad)", { XX } },
5236 { "(bad)", { XX } },
206c2556 5237 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5238 { "(bad)", { XX } },
5239 },
5240
5241 /* PREFIX_VEX_3A7A */
5242 {
5243 { "(bad)", { XX } },
5244 { "(bad)", { XX } },
5245 { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
5246 { "(bad)", { XX } },
5247 },
5248
5249 /* PREFIX_VEX_3A7B */
5250 {
5251 { "(bad)", { XX } },
5252 { "(bad)", { XX } },
5253 { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
5254 { "(bad)", { XX } },
5255 },
5256
5257 /* PREFIX_VEX_3A7C */
5258 {
5259 { "(bad)", { XX } },
5260 { "(bad)", { XX } },
206c2556 5261 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5262 { "(bad)", { XX } },
5263 },
5264
5265 /* PREFIX_VEX_3A7D */
5266 {
5267 { "(bad)", { XX } },
5268 { "(bad)", { XX } },
206c2556 5269 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
922d8de8
DR		 5270 { "(bad)", { XX } },
5271 },
5272
5273 /* PREFIX_VEX_3A7E */
5274 {
5275 { "(bad)", { XX } },
5276 { "(bad)", { XX } },
5277 { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
5278 { "(bad)", { XX } },
5279 },
5280
5281 /* PREFIX_VEX_3A7F */
5282 {
5283 { "(bad)", { XX } },
5284 { "(bad)", { XX } },
5285 { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5286 { "(bad)", { XX } },
5287 },
5288
a5ff0eb2
L		 5289 /* PREFIX_VEX_3ADF */
5290 {
5291 { "(bad)", { XX } },
5292 { "(bad)", { XX } },
5293 { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5294 { "(bad)", { XX } },
5295 },
c0f3af97
L		 5296};
5297
5298static const struct dis386 x86_64_table[][2] = {
5299 /* X86_64_06 */
5300 {
5301 { "push{T|}", { es } },
5302 { "(bad)", { XX } },
5303 },
5304
5305 /* X86_64_07 */
5306 {
5307 { "pop{T|}", { es } },
5308 { "(bad)", { XX } },
5309 },
5310
5311 /* X86_64_0D */
5312 {
5313 { "push{T|}", { cs } },
5314 { "(bad)", { XX } },
5315 },
5316
5317 /* X86_64_16 */
5318 {
5319 { "push{T|}", { ss } },
5320 { "(bad)", { XX } },
5321 },
5322
5323 /* X86_64_17 */
5324 {
5325 { "pop{T|}", { ss } },
5326 { "(bad)", { XX } },
5327 },
5328
5329 /* X86_64_1E */
5330 {
5331 { "push{T|}", { ds } },
5332 { "(bad)", { XX } },
5333 },
5334
5335 /* X86_64_1F */
5336 {
5337 { "pop{T|}", { ds } },
5338 { "(bad)", { XX } },
5339 },
5340
5341 /* X86_64_27 */
5342 {
5343 { "daa", { XX } },
5344 { "(bad)", { XX } },
5345 },
5346
5347 /* X86_64_2F */
5348 {
5349 { "das", { XX } },
5350 { "(bad)", { XX } },
5351 },
5352
5353 /* X86_64_37 */
5354 {
5355 { "aaa", { XX } },
5356 { "(bad)", { XX } },
5357 },
5358
5359 /* X86_64_3F */
5360 {
5361 { "aas", { XX } },
5362 { "(bad)", { XX } },
5363 },
5364
5365 /* X86_64_60 */
5366 {
5367 { "pusha{P|}", { XX } },
5368 { "(bad)", { XX } },
5369 },
5370
5371 /* X86_64_61 */
5372 {
5373 { "popa{P|}", { XX } },
5374 { "(bad)", { XX } },
5375 },
5376
5377 /* X86_64_62 */
5378 {
5379 { MOD_TABLE (MOD_62_32BIT) },
5380 { "(bad)", { XX } },
5381 },
5382
5383 /* X86_64_63 */
5384 {
5385 { "arpl", { Ew, Gw } },
5386 { "movs{lq|xd}", { Gv, Ed } },
5387 },
5388
5389 /* X86_64_6D */
5390 {
5391 { "ins{R|}", { Yzr, indirDX } },
5392 { "ins{G|}", { Yzr, indirDX } },
5393 },
5394
5395 /* X86_64_6F */
5396 {
5397 { "outs{R|}", { indirDXr, Xz } },
5398 { "outs{G|}", { indirDXr, Xz } },
5399 },
5400
5401 /* X86_64_9A */
5402 {
5403 { "Jcall{T|}", { Ap } },
5404 { "(bad)", { XX } },
5405 },
5406
5407 /* X86_64_C4 */
5408 {
5409 { MOD_TABLE (MOD_C4_32BIT) },
5410 { VEX_C4_TABLE (VEX_0F) },
5411 },
5412
5413 /* X86_64_C5 */
5414 {
5415 { MOD_TABLE (MOD_C5_32BIT) },
5416 { VEX_C5_TABLE (VEX_0F) },
5417 },
5418
5419 /* X86_64_CE */
5420 {
5421 { "into", { XX } },
5422 { "(bad)", { XX } },
5423 },
5424
5425 /* X86_64_D4 */
5426 {
5427 { "aam", { sIb } },
5428 { "(bad)", { XX } },
5429 },
5430
5431 /* X86_64_D5 */
5432 {
5433 { "aad", { sIb } },
5434 { "(bad)", { XX } },
5435 },
5436
5437 /* X86_64_EA */
5438 {
5439 { "Jjmp{T|}", { Ap } },
5440 { "(bad)", { XX } },
5441 },
5442
5443 /* X86_64_0F01_REG_0 */
5444 {
5445 { "sgdt{Q|IQ}", { M } },
5446 { "sgdt", { M } },
5447 },
5448
5449 /* X86_64_0F01_REG_1 */
5450 {
5451 { "sidt{Q|IQ}", { M } },
5452 { "sidt", { M } },
5453 },
5454
5455 /* X86_64_0F01_REG_2 */
5456 {
5457 { "lgdt{Q|Q}", { M } },
5458 { "lgdt", { M } },
5459 },
5460
5461 /* X86_64_0F01_REG_3 */
5462 {
5463 { "lidt{Q|Q}", { M } },
5464 { "lidt", { M } },
5465 },
5466};
5467
5468static const struct dis386 three_byte_table[][256] = {
c1e679ec
DR		 5469
5470 /* THREE_BYTE_0F38 */
c0f3af97
L		 5471 {
5472 /* 00 */
c1e679ec
DR		 5473 { "pshufb", { MX, EM } },
5474 { "phaddw", { MX, EM } },
5475 { "phaddd", { MX, EM } },
5476 { "phaddsw", { MX, EM } },
5477 { "pmaddubsw", { MX, EM } },
5478 { "phsubw", { MX, EM } },
5479 { "phsubd", { MX, EM } },
5480 { "phsubsw", { MX, EM } },
c0f3af97 5481 /* 08 */
c1e679ec
DR		 5482 { "psignb", { MX, EM } },
5483 { "psignw", { MX, EM } },
5484 { "psignd", { MX, EM } },
5485 { "pmulhrsw", { MX, EM } },
c0f3af97
L		 5486 { "(bad)", { XX } },
5487 { "(bad)", { XX } },
5488 { "(bad)", { XX } },
5489 { "(bad)", { XX } },
c1e679ec
DR		 5490 /* 10 */
5491 { PREFIX_TABLE (PREFIX_0F3810) },
c0f3af97
L		 5492 { "(bad)", { XX } },
5493 { "(bad)", { XX } },
5494 { "(bad)", { XX } },
c1e679ec
DR		 5495 { PREFIX_TABLE (PREFIX_0F3814) },
5496 { PREFIX_TABLE (PREFIX_0F3815) },
c0f3af97 5497 { "(bad)", { XX } },
c1e679ec
DR		 5498 { PREFIX_TABLE (PREFIX_0F3817) },
5499 /* 18 */
c0f3af97
L		 5500 { "(bad)", { XX } },
5501 { "(bad)", { XX } },
5502 { "(bad)", { XX } },
5503 { "(bad)", { XX } },
c1e679ec
DR		 5504 { "pabsb", { MX, EM } },
5505 { "pabsw", { MX, EM } },
5506 { "pabsd", { MX, EM } },
c0f3af97 5507 { "(bad)", { XX } },
c1e679ec
DR		 5508 /* 20 */
5509 { PREFIX_TABLE (PREFIX_0F3820) },
5510 { PREFIX_TABLE (PREFIX_0F3821) },
5511 { PREFIX_TABLE (PREFIX_0F3822) },
5512 { PREFIX_TABLE (PREFIX_0F3823) },
5513 { PREFIX_TABLE (PREFIX_0F3824) },
5514 { PREFIX_TABLE (PREFIX_0F3825) },
c0f3af97
L		 5515 { "(bad)", { XX } },
5516 { "(bad)", { XX } },
c1e679ec
DR		 5517 /* 28 */
5518 { PREFIX_TABLE (PREFIX_0F3828) },
5519 { PREFIX_TABLE (PREFIX_0F3829) },
5520 { PREFIX_TABLE (PREFIX_0F382A) },
5521 { PREFIX_TABLE (PREFIX_0F382B) },
c0f3af97
L		 5522 { "(bad)", { XX } },
5523 { "(bad)", { XX } },
5524 { "(bad)", { XX } },
5525 { "(bad)", { XX } },
c1e679ec
DR		 5526 /* 30 */
5527 { PREFIX_TABLE (PREFIX_0F3830) },
5528 { PREFIX_TABLE (PREFIX_0F3831) },
5529 { PREFIX_TABLE (PREFIX_0F3832) },
5530 { PREFIX_TABLE (PREFIX_0F3833) },
5531 { PREFIX_TABLE (PREFIX_0F3834) },
5532 { PREFIX_TABLE (PREFIX_0F3835) },
c0f3af97 5533 { "(bad)", { XX } },
c1e679ec
DR		 5534 { PREFIX_TABLE (PREFIX_0F3837) },
5535 /* 38 */
5536 { PREFIX_TABLE (PREFIX_0F3838) },
5537 { PREFIX_TABLE (PREFIX_0F3839) },
5538 { PREFIX_TABLE (PREFIX_0F383A) },
5539 { PREFIX_TABLE (PREFIX_0F383B) },
5540 { PREFIX_TABLE (PREFIX_0F383C) },
5541 { PREFIX_TABLE (PREFIX_0F383D) },
5542 { PREFIX_TABLE (PREFIX_0F383E) },
5543 { PREFIX_TABLE (PREFIX_0F383F) },
c0f3af97 5544 /* 40 */
c1e679ec
DR		 5545 { PREFIX_TABLE (PREFIX_0F3840) },
5546 { PREFIX_TABLE (PREFIX_0F3841) },
4e7d34a6
L		 5547 { "(bad)", { XX } },
5548 { "(bad)", { XX } },
c0f3af97 5549 { "(bad)", { XX } },
c0f3af97
L		 5550 { "(bad)", { XX } },
5551 { "(bad)", { XX } },
5552 { "(bad)", { XX } },
85f10a01 5553 /* 48 */
4e7d34a6
L		 5554 { "(bad)", { XX } },
5555 { "(bad)", { XX } },
5556 { "(bad)", { XX } },
5557 { "(bad)", { XX } },
4e7d34a6
L		 5558 { "(bad)", { XX } },
5559 { "(bad)", { XX } },
5560 { "(bad)", { XX } },
5561 { "(bad)", { XX } },
c0f3af97 5562 /* 50 */
4e7d34a6
L		 5563 { "(bad)", { XX } },
5564 { "(bad)", { XX } },
5565 { "(bad)", { XX } },
5566 { "(bad)", { XX } },
4e7d34a6
L		 5567 { "(bad)", { XX } },
5568 { "(bad)", { XX } },
5569 { "(bad)", { XX } },
5570 { "(bad)", { XX } },
c0f3af97 5571 /* 58 */
4e7d34a6
L		 5572 { "(bad)", { XX } },
5573 { "(bad)", { XX } },
5574 { "(bad)", { XX } },
5575 { "(bad)", { XX } },
4e7d34a6
L		 5576 { "(bad)", { XX } },
5577 { "(bad)", { XX } },
5578 { "(bad)", { XX } },
5579 { "(bad)", { XX } },
c0f3af97 5580 /* 60 */
c1e679ec
DR		 5581 { "(bad)", { XX } },
5582 { "(bad)", { XX } },
5583 { "(bad)", { XX } },
5584 { "(bad)", { XX } },
4e7d34a6
L		 5585 { "(bad)", { XX } },
5586 { "(bad)", { XX } },
5587 { "(bad)", { XX } },
5588 { "(bad)", { XX } },
5589 /* 68 */
5590 { "(bad)", { XX } },
5591 { "(bad)", { XX } },
5592 { "(bad)", { XX } },
5593 { "(bad)", { XX } },
5594 { "(bad)", { XX } },
5595 { "(bad)", { XX } },
5596 { "(bad)", { XX } },
5597 { "(bad)", { XX } },
85f10a01 5598 /* 70 */
4e7d34a6
L		 5599 { "(bad)", { XX } },
5600 { "(bad)", { XX } },
5601 { "(bad)", { XX } },
5602 { "(bad)", { XX } },
5603 { "(bad)", { XX } },
5604 { "(bad)", { XX } },
5605 { "(bad)", { XX } },
5606 { "(bad)", { XX } },
85f10a01 5607 /* 78 */
4e7d34a6
L		 5608 { "(bad)", { XX } },
5609 { "(bad)", { XX } },
5610 { "(bad)", { XX } },
5611 { "(bad)", { XX } },
5612 { "(bad)", { XX } },
5613 { "(bad)", { XX } },
5614 { "(bad)", { XX } },
5615 { "(bad)", { XX } },
85f10a01 5616 /* 80 */
c1e679ec
DR		 5617 { PREFIX_TABLE (PREFIX_0F3880) },
5618 { PREFIX_TABLE (PREFIX_0F3881) },
4e7d34a6
L		 5619 { "(bad)", { XX } },
5620 { "(bad)", { XX } },
5621 { "(bad)", { XX } },
c0f3af97
L		 5622 { "(bad)", { XX } },
5623 { "(bad)", { XX } },
5624 { "(bad)", { XX } },
85f10a01 5625 /* 88 */
4e7d34a6
L		 5626 { "(bad)", { XX } },
5627 { "(bad)", { XX } },
5628 { "(bad)", { XX } },
5629 { "(bad)", { XX } },
5630 { "(bad)", { XX } },
5631 { "(bad)", { XX } },
c0f3af97
L		 5632 { "(bad)", { XX } },
5633 { "(bad)", { XX } },
85f10a01 5634 /* 90 */
4e7d34a6
L		 5635 { "(bad)", { XX } },
5636 { "(bad)", { XX } },
5637 { "(bad)", { XX } },
5638 { "(bad)", { XX } },
5639 { "(bad)", { XX } },
c0f3af97
L		 5640 { "(bad)", { XX } },
5641 { "(bad)", { XX } },
5642 { "(bad)", { XX } },
85f10a01 5643 /* 98 */
4e7d34a6
L		 5644 { "(bad)", { XX } },
5645 { "(bad)", { XX } },
5646 { "(bad)", { XX } },
5647 { "(bad)", { XX } },
5648 { "(bad)", { XX } },
5649 { "(bad)", { XX } },
c0f3af97
L		 5650 { "(bad)", { XX } },
5651 { "(bad)", { XX } },
85f10a01 5652 /* a0 */
4e7d34a6
L		 5653 { "(bad)", { XX } },
5654 { "(bad)", { XX } },
5655 { "(bad)", { XX } },
5656 { "(bad)", { XX } },
5657 { "(bad)", { XX } },
5658 { "(bad)", { XX } },
c0f3af97 5659 { "(bad)", { XX } },
4e7d34a6 5660 { "(bad)", { XX } },
85f10a01 5661 /* a8 */
4e7d34a6
L		 5662 { "(bad)", { XX } },
5663 { "(bad)", { XX } },
5664 { "(bad)", { XX } },
5665 { "(bad)", { XX } },
5666 { "(bad)", { XX } },
5667 { "(bad)", { XX } },
5668 { "(bad)", { XX } },
5669 { "(bad)", { XX } },
85f10a01 5670 /* b0 */
4e7d34a6
L		 5671 { "(bad)", { XX } },
5672 { "(bad)", { XX } },
5673 { "(bad)", { XX } },
5674 { "(bad)", { XX } },
5675 { "(bad)", { XX } },
5676 { "(bad)", { XX } },
c0f3af97 5677 { "(bad)", { XX } },
4e7d34a6 5678 { "(bad)", { XX } },
85f10a01 5679 /* b8 */
4e7d34a6
L		 5680 { "(bad)", { XX } },
5681 { "(bad)", { XX } },
5682 { "(bad)", { XX } },
5683 { "(bad)", { XX } },
5684 { "(bad)", { XX } },
5685 { "(bad)", { XX } },
5686 { "(bad)", { XX } },
5687 { "(bad)", { XX } },
85f10a01 5688 /* c0 */
4e7d34a6
L		 5689 { "(bad)", { XX } },
5690 { "(bad)", { XX } },
5691 { "(bad)", { XX } },
5692 { "(bad)", { XX } },
5693 { "(bad)", { XX } },
5694 { "(bad)", { XX } },
5695 { "(bad)", { XX } },
5696 { "(bad)", { XX } },
85f10a01 5697 /* c8 */
4e7d34a6
L		 5698 { "(bad)", { XX } },
5699 { "(bad)", { XX } },
5700 { "(bad)", { XX } },
5701 { "(bad)", { XX } },
5702 { "(bad)", { XX } },
5703 { "(bad)", { XX } },
5704 { "(bad)", { XX } },
5705 { "(bad)", { XX } },
85f10a01 5706 /* d0 */
4e7d34a6
L		 5707 { "(bad)", { XX } },
5708 { "(bad)", { XX } },
5709 { "(bad)", { XX } },
5710 { "(bad)", { XX } },
5711 { "(bad)", { XX } },
5712 { "(bad)", { XX } },
5713 { "(bad)", { XX } },
5714 { "(bad)", { XX } },
85f10a01 5715 /* d8 */
4e7d34a6
L		 5716 { "(bad)", { XX } },
5717 { "(bad)", { XX } },
5718 { "(bad)", { XX } },
c1e679ec
DR		 5719 { PREFIX_TABLE (PREFIX_0F38DB) },
5720 { PREFIX_TABLE (PREFIX_0F38DC) },
5721 { PREFIX_TABLE (PREFIX_0F38DD) },
5722 { PREFIX_TABLE (PREFIX_0F38DE) },
5723 { PREFIX_TABLE (PREFIX_0F38DF) },
85f10a01 5724 /* e0 */
4e7d34a6
L		 5725 { "(bad)", { XX } },
5726 { "(bad)", { XX } },
5727 { "(bad)", { XX } },
5728 { "(bad)", { XX } },
5729 { "(bad)", { XX } },
5730 { "(bad)", { XX } },
5731 { "(bad)", { XX } },
5732 { "(bad)", { XX } },
85f10a01 5733 /* e8 */
4e7d34a6
L		 5734 { "(bad)", { XX } },
5735 { "(bad)", { XX } },
5736 { "(bad)", { XX } },
5737 { "(bad)", { XX } },
5738 { "(bad)", { XX } },
5739 { "(bad)", { XX } },
5740 { "(bad)", { XX } },
5741 { "(bad)", { XX } },
85f10a01 5742 /* f0 */
c1e679ec
DR		 5743 { PREFIX_TABLE (PREFIX_0F38F0) },
5744 { PREFIX_TABLE (PREFIX_0F38F1) },
4e7d34a6
L		 5745 { "(bad)", { XX } },
5746 { "(bad)", { XX } },
5747 { "(bad)", { XX } },
5748 { "(bad)", { XX } },
5749 { "(bad)", { XX } },
5750 { "(bad)", { XX } },
85f10a01 5751 /* f8 */
4e7d34a6
L		 5752 { "(bad)", { XX } },
5753 { "(bad)", { XX } },
5754 { "(bad)", { XX } },
5755 { "(bad)", { XX } },
5756 { "(bad)", { XX } },
5757 { "(bad)", { XX } },
5758 { "(bad)", { XX } },
5759 { "(bad)", { XX } },
85f10a01 5760 },
c1e679ec 5761 /* THREE_BYTE_0F3A */
85f10a01
MM		 5762 {
5763 /* 00 */
4e7d34a6
L		 5764 { "(bad)", { XX } },
5765 { "(bad)", { XX } },
5766 { "(bad)", { XX } },
5767 { "(bad)", { XX } },
5768 { "(bad)", { XX } },
5769 { "(bad)", { XX } },
5770 { "(bad)", { XX } },
5771 { "(bad)", { XX } },
85f10a01 5772 /* 08 */
c1e679ec
DR		 5773 { PREFIX_TABLE (PREFIX_0F3A08) },
5774 { PREFIX_TABLE (PREFIX_0F3A09) },
5775 { PREFIX_TABLE (PREFIX_0F3A0A) },
5776 { PREFIX_TABLE (PREFIX_0F3A0B) },
5777 { PREFIX_TABLE (PREFIX_0F3A0C) },
5778 { PREFIX_TABLE (PREFIX_0F3A0D) },
5779 { PREFIX_TABLE (PREFIX_0F3A0E) },
5780 { "palignr", { MX, EM, Ib } },
85f10a01 5781 /* 10 */
4e7d34a6
L		 5782 { "(bad)", { XX } },
5783 { "(bad)", { XX } },
5784 { "(bad)", { XX } },
5785 { "(bad)", { XX } },
c1e679ec
DR		 5786 { PREFIX_TABLE (PREFIX_0F3A14) },
5787 { PREFIX_TABLE (PREFIX_0F3A15) },
5788 { PREFIX_TABLE (PREFIX_0F3A16) },
5789 { PREFIX_TABLE (PREFIX_0F3A17) },
85f10a01 5790 /* 18 */
4e7d34a6
L		 5791 { "(bad)", { XX } },
5792 { "(bad)", { XX } },
5793 { "(bad)", { XX } },
5794 { "(bad)", { XX } },
5795 { "(bad)", { XX } },
5796 { "(bad)", { XX } },
5797 { "(bad)", { XX } },
5798 { "(bad)", { XX } },
85f10a01 5799 /* 20 */
c1e679ec
DR		 5800 { PREFIX_TABLE (PREFIX_0F3A20) },
5801 { PREFIX_TABLE (PREFIX_0F3A21) },
5802 { PREFIX_TABLE (PREFIX_0F3A22) },
4e7d34a6
L		 5803 { "(bad)", { XX } },
5804 { "(bad)", { XX } },
5805 { "(bad)", { XX } },
5806 { "(bad)", { XX } },
5807 { "(bad)", { XX } },
85f10a01 5808 /* 28 */
4e7d34a6
L		 5809 { "(bad)", { XX } },
5810 { "(bad)", { XX } },
5811 { "(bad)", { XX } },
5812 { "(bad)", { XX } },
4e7d34a6
L		 5813 { "(bad)", { XX } },
5814 { "(bad)", { XX } },
5815 { "(bad)", { XX } },
5816 { "(bad)", { XX } },
c0f3af97 5817 /* 30 */
c1e679ec
DR		 5818 { "(bad)", { XX } },
5819 { "(bad)", { XX } },
4e7d34a6 5820 { "(bad)", { XX } },
4e7d34a6
L		 5821 { "(bad)", { XX } },
5822 { "(bad)", { XX } },
5823 { "(bad)", { XX } },
5824 { "(bad)", { XX } },
5825 { "(bad)", { XX } },
c0f3af97 5826 /* 38 */
4e7d34a6
L		 5827 { "(bad)", { XX } },
5828 { "(bad)", { XX } },
5829 { "(bad)", { XX } },
4e7d34a6
L		 5830 { "(bad)", { XX } },
5831 { "(bad)", { XX } },
5832 { "(bad)", { XX } },
5833 { "(bad)", { XX } },
5834 { "(bad)", { XX } },
c0f3af97 5835 /* 40 */
c1e679ec
DR		 5836 { PREFIX_TABLE (PREFIX_0F3A40) },
5837 { PREFIX_TABLE (PREFIX_0F3A41) },
5838 { PREFIX_TABLE (PREFIX_0F3A42) },
5839 { "(bad)", { XX } },
5840 { PREFIX_TABLE (PREFIX_0F3A44) },
4e7d34a6
L		 5841 { "(bad)", { XX } },
5842 { "(bad)", { XX } },
5843 { "(bad)", { XX } },
85f10a01 5844 /* 48 */
4e7d34a6
L		 5845 { "(bad)", { XX } },
5846 { "(bad)", { XX } },
5847 { "(bad)", { XX } },
c1e679ec 5848 { "(bad)", { XX } },
4e7d34a6
L		 5849 { "(bad)", { XX } },
5850 { "(bad)", { XX } },
5851 { "(bad)", { XX } },
5852 { "(bad)", { XX } },
c0f3af97 5853 /* 50 */
4e7d34a6
L		 5854 { "(bad)", { XX } },
5855 { "(bad)", { XX } },
5856 { "(bad)", { XX } },
c1e679ec
DR		 5857 { "(bad)", { XX } },
5858 { "(bad)", { XX } },
5859 { "(bad)", { XX } },
5860 { "(bad)", { XX } },
5861 { "(bad)", { XX } },
85f10a01 5862 /* 58 */
4e7d34a6
L		 5863 { "(bad)", { XX } },
5864 { "(bad)", { XX } },
5865 { "(bad)", { XX } },
4e7d34a6
L		 5866 { "(bad)", { XX } },
5867 { "(bad)", { XX } },
5868 { "(bad)", { XX } },
5869 { "(bad)", { XX } },
4e7d34a6 5870 { "(bad)", { XX } },
c1e679ec
DR		 5871 /* 60 */
5872 { PREFIX_TABLE (PREFIX_0F3A60) },
5873 { PREFIX_TABLE (PREFIX_0F3A61) },
5874 { PREFIX_TABLE (PREFIX_0F3A62) },
5875 { PREFIX_TABLE (PREFIX_0F3A63) },
4e7d34a6
L		 5876 { "(bad)", { XX } },
5877 { "(bad)", { XX } },
5878 { "(bad)", { XX } },
5879 { "(bad)", { XX } },
c0f3af97
L		 5880 /* 68 */
5881 { "(bad)", { XX } },
4e7d34a6
L		 5882 { "(bad)", { XX } },
5883 { "(bad)", { XX } },
5884 { "(bad)", { XX } },
4e7d34a6
L		 5885 { "(bad)", { XX } },
5886 { "(bad)", { XX } },
5887 { "(bad)", { XX } },
5888 { "(bad)", { XX } },
85f10a01 5889 /* 70 */
4e7d34a6
L		 5890 { "(bad)", { XX } },
5891 { "(bad)", { XX } },
5892 { "(bad)", { XX } },
5893 { "(bad)", { XX } },
5894 { "(bad)", { XX } },
5895 { "(bad)", { XX } },
5896 { "(bad)", { XX } },
5897 { "(bad)", { XX } },
85f10a01 5898 /* 78 */
4e7d34a6
L		 5899 { "(bad)", { XX } },
5900 { "(bad)", { XX } },
5901 { "(bad)", { XX } },
5902 { "(bad)", { XX } },
5903 { "(bad)", { XX } },
5904 { "(bad)", { XX } },
5905 { "(bad)", { XX } },
5906 { "(bad)", { XX } },
85f10a01 5907 /* 80 */
4e7d34a6
L		 5908 { "(bad)", { XX } },
5909 { "(bad)", { XX } },
5910 { "(bad)", { XX } },
5911 { "(bad)", { XX } },
5912 { "(bad)", { XX } },
5913 { "(bad)", { XX } },
5914 { "(bad)", { XX } },
5915 { "(bad)", { XX } },
5916 /* 88 */
5917 { "(bad)", { XX } },
5918 { "(bad)", { XX } },
5919 { "(bad)", { XX } },
5920 { "(bad)", { XX } },
5921 { "(bad)", { XX } },
5922 { "(bad)", { XX } },
5923 { "(bad)", { XX } },
5924 { "(bad)", { XX } },
5925 /* 90 */
5926 { "(bad)", { XX } },
5927 { "(bad)", { XX } },
5928 { "(bad)", { XX } },
5929 { "(bad)", { XX } },
5930 { "(bad)", { XX } },
5931 { "(bad)", { XX } },
5932 { "(bad)", { XX } },
5933 { "(bad)", { XX } },
5934 /* 98 */
5935 { "(bad)", { XX } },
5936 { "(bad)", { XX } },
5937 { "(bad)", { XX } },
5938 { "(bad)", { XX } },
5939 { "(bad)", { XX } },
5940 { "(bad)", { XX } },
5941 { "(bad)", { XX } },
5942 { "(bad)", { XX } },
5943 /* a0 */
5944 { "(bad)", { XX } },
5945 { "(bad)", { XX } },
5946 { "(bad)", { XX } },
5947 { "(bad)", { XX } },
5948 { "(bad)", { XX } },
5949 { "(bad)", { XX } },
5950 { "(bad)", { XX } },
5951 { "(bad)", { XX } },
5952 /* a8 */
5953 { "(bad)", { XX } },
5954 { "(bad)", { XX } },
5955 { "(bad)", { XX } },
5956 { "(bad)", { XX } },
5957 { "(bad)", { XX } },
5958 { "(bad)", { XX } },
5959 { "(bad)", { XX } },
5960 { "(bad)", { XX } },
5961 /* b0 */
5962 { "(bad)", { XX } },
5963 { "(bad)", { XX } },
5964 { "(bad)", { XX } },
5965 { "(bad)", { XX } },
5966 { "(bad)", { XX } },
5967 { "(bad)", { XX } },
5968 { "(bad)", { XX } },
5969 { "(bad)", { XX } },
5970 /* b8 */
5971 { "(bad)", { XX } },
5972 { "(bad)", { XX } },
5973 { "(bad)", { XX } },
5974 { "(bad)", { XX } },
5975 { "(bad)", { XX } },
5976 { "(bad)", { XX } },
5977 { "(bad)", { XX } },
5978 { "(bad)", { XX } },
5979 /* c0 */
5980 { "(bad)", { XX } },
5981 { "(bad)", { XX } },
5982 { "(bad)", { XX } },
5983 { "(bad)", { XX } },
5984 { "(bad)", { XX } },
5985 { "(bad)", { XX } },
5986 { "(bad)", { XX } },
5987 { "(bad)", { XX } },
5988 /* c8 */
5989 { "(bad)", { XX } },
5990 { "(bad)", { XX } },
5991 { "(bad)", { XX } },
5992 { "(bad)", { XX } },
5993 { "(bad)", { XX } },
5994 { "(bad)", { XX } },
5995 { "(bad)", { XX } },
5996 { "(bad)", { XX } },
5997 /* d0 */
5998 { "(bad)", { XX } },
5999 { "(bad)", { XX } },
6000 { "(bad)", { XX } },
6001 { "(bad)", { XX } },
6002 { "(bad)", { XX } },
6003 { "(bad)", { XX } },
6004 { "(bad)", { XX } },
6005 { "(bad)", { XX } },
6006 /* d8 */
6007 { "(bad)", { XX } },
6008 { "(bad)", { XX } },
6009 { "(bad)", { XX } },
6010 { "(bad)", { XX } },
6011 { "(bad)", { XX } },
6012 { "(bad)", { XX } },
6013 { "(bad)", { XX } },
c1e679ec 6014 { PREFIX_TABLE (PREFIX_0F3ADF) },
4e7d34a6
L		 6015 /* e0 */
6016 { "(bad)", { XX } },
6017 { "(bad)", { XX } },
6018 { "(bad)", { XX } },
6019 { "(bad)", { XX } },
6020 { "(bad)", { XX } },
6021 { "(bad)", { XX } },
6022 { "(bad)", { XX } },
6023 { "(bad)", { XX } },
6024 /* e8 */
6025 { "(bad)", { XX } },
6026 { "(bad)", { XX } },
6027 { "(bad)", { XX } },
6028 { "(bad)", { XX } },
6029 { "(bad)", { XX } },
6030 { "(bad)", { XX } },
6031 { "(bad)", { XX } },
6032 { "(bad)", { XX } },
6033 /* f0 */
6034 { "(bad)", { XX } },
6035 { "(bad)", { XX } },
6036 { "(bad)", { XX } },
6037 { "(bad)", { XX } },
6038 { "(bad)", { XX } },
6039 { "(bad)", { XX } },
6040 { "(bad)", { XX } },
6041 { "(bad)", { XX } },
6042 /* f8 */
6043 { "(bad)", { XX } },
6044 { "(bad)", { XX } },
6045 { "(bad)", { XX } },
6046 { "(bad)", { XX } },
6047 { "(bad)", { XX } },
6048 { "(bad)", { XX } },
6049 { "(bad)", { XX } },
6050 { "(bad)", { XX } },
6051 },
c1e679ec
DR		 6052
6053 /* THREE_BYTE_0F7A */
4e7d34a6
L		 6054 {
6055 /* 00 */
c0f3af97
L		 6056 { "(bad)", { XX } },
6057 { "(bad)", { XX } },
6058 { "(bad)", { XX } },
6059 { "(bad)", { XX } },
6060 { "(bad)", { XX } },
6061 { "(bad)", { XX } },
6062 { "(bad)", { XX } },
6063 { "(bad)", { XX } },
4e7d34a6 6064 /* 08 */
c0f3af97
L		 6065 { "(bad)", { XX } },
6066 { "(bad)", { XX } },
6067 { "(bad)", { XX } },
6068 { "(bad)", { XX } },
d5d7db8e
L		 6069 { "(bad)", { XX } },
6070 { "(bad)", { XX } },
6071 { "(bad)", { XX } },
6072 { "(bad)", { XX } },
4e7d34a6 6073 /* 10 */
d5d7db8e
L		 6074 { "(bad)", { XX } },
6075 { "(bad)", { XX } },
6076 { "(bad)", { XX } },
d5d7db8e 6077 { "(bad)", { XX } },
c0f3af97
L		 6078 { "(bad)", { XX } },
6079 { "(bad)", { XX } },
6080 { "(bad)", { XX } },
6081 { "(bad)", { XX } },
4e7d34a6 6082 /* 18 */
d5d7db8e
L		 6083 { "(bad)", { XX } },
6084 { "(bad)", { XX } },
6085 { "(bad)", { XX } },
6086 { "(bad)", { XX } },
c0f3af97
L		 6087 { "(bad)", { XX } },
6088 { "(bad)", { XX } },
6089 { "(bad)", { XX } },
d5d7db8e 6090 { "(bad)", { XX } },
4e7d34a6 6091 /* 20 */
c1e679ec 6092 { "ptest", { XX } },
c0f3af97
L		 6093 { "(bad)", { XX } },
6094 { "(bad)", { XX } },
6095 { "(bad)", { XX } },
6096 { "(bad)", { XX } },
6097 { "(bad)", { XX } },
d5d7db8e
L		 6098 { "(bad)", { XX } },
6099 { "(bad)", { XX } },
4e7d34a6 6100 /* 28 */
c0f3af97
L		 6101 { "(bad)", { XX } },
6102 { "(bad)", { XX } },
6103 { "(bad)", { XX } },
6104 { "(bad)", { XX } },
d5d7db8e
L		 6105 { "(bad)", { XX } },
6106 { "(bad)", { XX } },
6107 { "(bad)", { XX } },
6108 { "(bad)", { XX } },
4e7d34a6 6109 /* 30 */
d5d7db8e 6110 { "(bad)", { XX } },
d5d7db8e
L		 6111 { "(bad)", { XX } },
6112 { "(bad)", { XX } },
6113 { "(bad)", { XX } },
6114 { "(bad)", { XX } },
6115 { "(bad)", { XX } },
6116 { "(bad)", { XX } },
c0f3af97
L		 6117 { "(bad)", { XX } },
6118 /* 38 */
6119 { "(bad)", { XX } },
6120 { "(bad)", { XX } },
6121 { "(bad)", { XX } },
6122 { "(bad)", { XX } },
d5d7db8e
L		 6123 { "(bad)", { XX } },
6124 { "(bad)", { XX } },
6125 { "(bad)", { XX } },
6126 { "(bad)", { XX } },
c0f3af97 6127 /* 40 */
c1e679ec
DR		 6128 { "(bad)", { XX } },
6129 { "phaddbw", { XM, EXq } },
6130 { "phaddbd", { XM, EXq } },
6131 { "phaddbq", { XM, EXq } },
d5d7db8e
L		 6132 { "(bad)", { XX } },
6133 { "(bad)", { XX } },
c1e679ec
DR		 6134 { "phaddwd", { XM, EXq } },
6135 { "phaddwq", { XM, EXq } },
6136 /* 48 */
d5d7db8e
L		 6137 { "(bad)", { XX } },
6138 { "(bad)", { XX } },
d5d7db8e 6139 { "(bad)", { XX } },
c1e679ec 6140 { "phadddq", { XM, EXq } },
d5d7db8e
L		 6141 { "(bad)", { XX } },
6142 { "(bad)", { XX } },
6143 { "(bad)", { XX } },
6144 { "(bad)", { XX } },
c1e679ec 6145 /* 50 */
d5d7db8e 6146 { "(bad)", { XX } },
c1e679ec
DR		 6147 { "phaddubw", { XM, EXq } },
6148 { "phaddubd", { XM, EXq } },
6149 { "phaddubq", { XM, EXq } },
d5d7db8e
L		 6150 { "(bad)", { XX } },
6151 { "(bad)", { XX } },
c1e679ec
DR		 6152 { "phadduwd", { XM, EXq } },
6153 { "phadduwq", { XM, EXq } },
4e7d34a6 6154 /* 58 */
d5d7db8e
L		 6155 { "(bad)", { XX } },
6156 { "(bad)", { XX } },
6157 { "(bad)", { XX } },
c1e679ec 6158 { "phaddudq", { XM, EXq } },
d5d7db8e
L		 6159 { "(bad)", { XX } },
6160 { "(bad)", { XX } },
6161 { "(bad)", { XX } },
6162 { "(bad)", { XX } },
4e7d34a6 6163 /* 60 */
d5d7db8e 6164 { "(bad)", { XX } },
c1e679ec
DR		 6165 { "phsubbw", { XM, EXq } },
6166 { "phsubbd", { XM, EXq } },
6167 { "phsubbq", { XM, EXq } },
d5d7db8e
L		 6168 { "(bad)", { XX } },
6169 { "(bad)", { XX } },
6170 { "(bad)", { XX } },
6171 { "(bad)", { XX } },
4e7d34a6 6172 /* 68 */
d5d7db8e
L		 6173 { "(bad)", { XX } },
6174 { "(bad)", { XX } },
6175 { "(bad)", { XX } },
6176 { "(bad)", { XX } },
6177 { "(bad)", { XX } },
6178 { "(bad)", { XX } },
6179 { "(bad)", { XX } },
6180 { "(bad)", { XX } },
4e7d34a6 6181 /* 70 */
d5d7db8e
L		 6182 { "(bad)", { XX } },
6183 { "(bad)", { XX } },
6184 { "(bad)", { XX } },
6185 { "(bad)", { XX } },
6186 { "(bad)", { XX } },
6187 { "(bad)", { XX } },
6188 { "(bad)", { XX } },
6189 { "(bad)", { XX } },
4e7d34a6 6190 /* 78 */
d5d7db8e
L		 6191 { "(bad)", { XX } },
6192 { "(bad)", { XX } },
6193 { "(bad)", { XX } },
6194 { "(bad)", { XX } },
6195 { "(bad)", { XX } },
6196 { "(bad)", { XX } },
6197 { "(bad)", { XX } },
6198 { "(bad)", { XX } },
4e7d34a6 6199 /* 80 */
d5d7db8e
L		 6200 { "(bad)", { XX } },
6201 { "(bad)", { XX } },
6202 { "(bad)", { XX } },
6203 { "(bad)", { XX } },
6204 { "(bad)", { XX } },
6205 { "(bad)", { XX } },
6206 { "(bad)", { XX } },
6207 { "(bad)", { XX } },
4e7d34a6 6208 /* 88 */
d5d7db8e
L		 6209 { "(bad)", { XX } },
6210 { "(bad)", { XX } },
6211 { "(bad)", { XX } },
6212 { "(bad)", { XX } },
6213 { "(bad)", { XX } },
6214 { "(bad)", { XX } },
6215 { "(bad)", { XX } },
6216 { "(bad)", { XX } },
4e7d34a6 6217 /* 90 */
d5d7db8e
L		 6218 { "(bad)", { XX } },
6219 { "(bad)", { XX } },
6220 { "(bad)", { XX } },
6221 { "(bad)", { XX } },
6222 { "(bad)", { XX } },
6223 { "(bad)", { XX } },
6224 { "(bad)", { XX } },
6225 { "(bad)", { XX } },
4e7d34a6 6226 /* 98 */
d5d7db8e
L		 6227 { "(bad)", { XX } },
6228 { "(bad)", { XX } },
6229 { "(bad)", { XX } },
6230 { "(bad)", { XX } },
6231 { "(bad)", { XX } },
6232 { "(bad)", { XX } },
6233 { "(bad)", { XX } },
6234 { "(bad)", { XX } },
4e7d34a6 6235 /* a0 */
d5d7db8e
L		 6236 { "(bad)", { XX } },
6237 { "(bad)", { XX } },
6238 { "(bad)", { XX } },
6239 { "(bad)", { XX } },
6240 { "(bad)", { XX } },
6241 { "(bad)", { XX } },
6242 { "(bad)", { XX } },
6243 { "(bad)", { XX } },
4e7d34a6 6244 /* a8 */
d5d7db8e
L		 6245 { "(bad)", { XX } },
6246 { "(bad)", { XX } },
6247 { "(bad)", { XX } },
6248 { "(bad)", { XX } },
6249 { "(bad)", { XX } },
6250 { "(bad)", { XX } },
6251 { "(bad)", { XX } },
6252 { "(bad)", { XX } },
6253 /* b0 */
6254 { "(bad)", { XX } },
6255 { "(bad)", { XX } },
6256 { "(bad)", { XX } },
6257 { "(bad)", { XX } },
6258 { "(bad)", { XX } },
6259 { "(bad)", { XX } },
6260 { "(bad)", { XX } },
6261 { "(bad)", { XX } },
85f10a01 6262 /* b8 */
d5d7db8e
L		 6263 { "(bad)", { XX } },
6264 { "(bad)", { XX } },
6265 { "(bad)", { XX } },
6266 { "(bad)", { XX } },
6267 { "(bad)", { XX } },
6268 { "(bad)", { XX } },
6269 { "(bad)", { XX } },
6270 { "(bad)", { XX } },
85f10a01 6271 /* c0 */
d5d7db8e
L		 6272 { "(bad)", { XX } },
6273 { "(bad)", { XX } },
6274 { "(bad)", { XX } },
6275 { "(bad)", { XX } },
6276 { "(bad)", { XX } },
6277 { "(bad)", { XX } },
6278 { "(bad)", { XX } },
6279 { "(bad)", { XX } },
85f10a01 6280 /* c8 */
d5d7db8e
L		 6281 { "(bad)", { XX } },
6282 { "(bad)", { XX } },
6283 { "(bad)", { XX } },
6284 { "(bad)", { XX } },
6285 { "(bad)", { XX } },
6286 { "(bad)", { XX } },
6287 { "(bad)", { XX } },
6288 { "(bad)", { XX } },
85f10a01 6289 /* d0 */
d5d7db8e
L		 6290 { "(bad)", { XX } },
6291 { "(bad)", { XX } },
6292 { "(bad)", { XX } },
6293 { "(bad)", { XX } },
6294 { "(bad)", { XX } },
6295 { "(bad)", { XX } },
6296 { "(bad)", { XX } },
6297 { "(bad)", { XX } },
85f10a01 6298 /* d8 */
d5d7db8e
L		 6299 { "(bad)", { XX } },
6300 { "(bad)", { XX } },
6301 { "(bad)", { XX } },
6302 { "(bad)", { XX } },
6303 { "(bad)", { XX } },
6304 { "(bad)", { XX } },
6305 { "(bad)", { XX } },
6306 { "(bad)", { XX } },
85f10a01 6307 /* e0 */
d5d7db8e
L		 6308 { "(bad)", { XX } },
6309 { "(bad)", { XX } },
6310 { "(bad)", { XX } },
6311 { "(bad)", { XX } },
6312 { "(bad)", { XX } },
6313 { "(bad)", { XX } },
6314 { "(bad)", { XX } },
6315 { "(bad)", { XX } },
85f10a01 6316 /* e8 */
d5d7db8e
L		 6317 { "(bad)", { XX } },
6318 { "(bad)", { XX } },
6319 { "(bad)", { XX } },
6320 { "(bad)", { XX } },
6321 { "(bad)", { XX } },
6322 { "(bad)", { XX } },
6323 { "(bad)", { XX } },
6324 { "(bad)", { XX } },
85f10a01 6325 /* f0 */
c0f3af97
L		 6326 { "(bad)", { XX } },
6327 { "(bad)", { XX } },
d5d7db8e
L		 6328 { "(bad)", { XX } },
6329 { "(bad)", { XX } },
6330 { "(bad)", { XX } },
6331 { "(bad)", { XX } },
6332 { "(bad)", { XX } },
6333 { "(bad)", { XX } },
85f10a01 6334 /* f8 */
d5d7db8e
L		 6335 { "(bad)", { XX } },
6336 { "(bad)", { XX } },
6337 { "(bad)", { XX } },
6338 { "(bad)", { XX } },
6339 { "(bad)", { XX } },
6340 { "(bad)", { XX } },
6341 { "(bad)", { XX } },
6342 { "(bad)", { XX } },
85f10a01 6343 },
c0f3af97
L		 6344};
6345
c1e679ec 6346
c0f3af97
L		 6347static const struct dis386 vex_table[][256] = {
6348 /* VEX_0F */
85f10a01
MM		 6349 {
6350 /* 00 */
d5d7db8e
L		 6351 { "(bad)", { XX } },
6352 { "(bad)", { XX } },
6353 { "(bad)", { XX } },
6354 { "(bad)", { XX } },
6355 { "(bad)", { XX } },
6356 { "(bad)", { XX } },
6357 { "(bad)", { XX } },
6358 { "(bad)", { XX } },
85f10a01 6359 /* 08 */
d5d7db8e
L		 6360 { "(bad)", { XX } },
6361 { "(bad)", { XX } },
6362 { "(bad)", { XX } },
6363 { "(bad)", { XX } },
d5d7db8e
L		 6364 { "(bad)", { XX } },
6365 { "(bad)", { XX } },
6366 { "(bad)", { XX } },
6367 { "(bad)", { XX } },
c0f3af97
L		 6368 /* 10 */
6369 { PREFIX_TABLE (PREFIX_VEX_10) },
6370 { PREFIX_TABLE (PREFIX_VEX_11) },
6371 { PREFIX_TABLE (PREFIX_VEX_12) },
6372 { MOD_TABLE (MOD_VEX_13) },
6373 { "vunpcklpX", { XM, Vex, EXx } },
6374 { "vunpckhpX", { XM, Vex, EXx } },
6375 { PREFIX_TABLE (PREFIX_VEX_16) },
6376 { MOD_TABLE (MOD_VEX_17) },
6377 /* 18 */
d5d7db8e
L		 6378 { "(bad)", { XX } },
6379 { "(bad)", { XX } },
6380 { "(bad)", { XX } },
d5d7db8e
L		 6381 { "(bad)", { XX } },
6382 { "(bad)", { XX } },
6383 { "(bad)", { XX } },
6384 { "(bad)", { XX } },
6385 { "(bad)", { XX } },
c0f3af97 6386 /* 20 */
d5d7db8e
L		 6387 { "(bad)", { XX } },
6388 { "(bad)", { XX } },
6389 { "(bad)", { XX } },
6390 { "(bad)", { XX } },
6391 { "(bad)", { XX } },
6392 { "(bad)", { XX } },
6393 { "(bad)", { XX } },
6394 { "(bad)", { XX } },
c0f3af97
L		 6395 /* 28 */
6396 { "vmovapX", { XM, EXx } },
b6169b20 6397 { "vmovapX", { EXxS, XM } },
c0f3af97
L		 6398 { PREFIX_TABLE (PREFIX_VEX_2A) },
6399 { MOD_TABLE (MOD_VEX_2B) },
6400 { PREFIX_TABLE (PREFIX_VEX_2C) },
6401 { PREFIX_TABLE (PREFIX_VEX_2D) },
6402 { PREFIX_TABLE (PREFIX_VEX_2E) },
6403 { PREFIX_TABLE (PREFIX_VEX_2F) },
85f10a01 6404 /* 30 */
d5d7db8e
L		 6405 { "(bad)", { XX } },
6406 { "(bad)", { XX } },
6407 { "(bad)", { XX } },
6408 { "(bad)", { XX } },
6409 { "(bad)", { XX } },
6410 { "(bad)", { XX } },
6411 { "(bad)", { XX } },
6412 { "(bad)", { XX } },
4e7d34a6 6413 /* 38 */
d5d7db8e
L		 6414 { "(bad)", { XX } },
6415 { "(bad)", { XX } },
6416 { "(bad)", { XX } },
6417 { "(bad)", { XX } },
6418 { "(bad)", { XX } },
6419 { "(bad)", { XX } },
6420 { "(bad)", { XX } },
6421 { "(bad)", { XX } },
6422 /* 40 */
c0f3af97
L		 6423 { "(bad)", { XX } },
6424 { "(bad)", { XX } },
6425 { "(bad)", { XX } },
d5d7db8e
L		 6426 { "(bad)", { XX } },
6427 { "(bad)", { XX } },
6428 { "(bad)", { XX } },
6429 { "(bad)", { XX } },
6430 { "(bad)", { XX } },
85f10a01 6431 /* 48 */
85f10a01
MM		 6432 { "(bad)", { XX } },
6433 { "(bad)", { XX } },
6434 { "(bad)", { XX } },
6435 { "(bad)", { XX } },
6436 { "(bad)", { XX } },
6437 { "(bad)", { XX } },
6438 { "(bad)", { XX } },
6439 { "(bad)", { XX } },
d5d7db8e 6440 /* 50 */
c0f3af97
L		 6441 { MOD_TABLE (MOD_VEX_51) },
6442 { PREFIX_TABLE (PREFIX_VEX_51) },
6443 { PREFIX_TABLE (PREFIX_VEX_52) },
6444 { PREFIX_TABLE (PREFIX_VEX_53) },
6445 { "vandpX", { XM, Vex, EXx } },
6446 { "vandnpX", { XM, Vex, EXx } },
6447 { "vorpX", { XM, Vex, EXx } },
6448 { "vxorpX", { XM, Vex, EXx } },
6449 /* 58 */
6450 { PREFIX_TABLE (PREFIX_VEX_58) },
6451 { PREFIX_TABLE (PREFIX_VEX_59) },
6452 { PREFIX_TABLE (PREFIX_VEX_5A) },
6453 { PREFIX_TABLE (PREFIX_VEX_5B) },
6454 { PREFIX_TABLE (PREFIX_VEX_5C) },
6455 { PREFIX_TABLE (PREFIX_VEX_5D) },
6456 { PREFIX_TABLE (PREFIX_VEX_5E) },
6457 { PREFIX_TABLE (PREFIX_VEX_5F) },
6458 /* 60 */
6459 { PREFIX_TABLE (PREFIX_VEX_60) },
6460 { PREFIX_TABLE (PREFIX_VEX_61) },
6461 { PREFIX_TABLE (PREFIX_VEX_62) },
6462 { PREFIX_TABLE (PREFIX_VEX_63) },
6463 { PREFIX_TABLE (PREFIX_VEX_64) },
6464 { PREFIX_TABLE (PREFIX_VEX_65) },
6465 { PREFIX_TABLE (PREFIX_VEX_66) },
6466 { PREFIX_TABLE (PREFIX_VEX_67) },
6467 /* 68 */
6468 { PREFIX_TABLE (PREFIX_VEX_68) },
6469 { PREFIX_TABLE (PREFIX_VEX_69) },
6470 { PREFIX_TABLE (PREFIX_VEX_6A) },
6471 { PREFIX_TABLE (PREFIX_VEX_6B) },
6472 { PREFIX_TABLE (PREFIX_VEX_6C) },
6473 { PREFIX_TABLE (PREFIX_VEX_6D) },
6474 { PREFIX_TABLE (PREFIX_VEX_6E) },
6475 { PREFIX_TABLE (PREFIX_VEX_6F) },
6476 /* 70 */
6477 { PREFIX_TABLE (PREFIX_VEX_70) },
6478 { REG_TABLE (REG_VEX_71) },
6479 { REG_TABLE (REG_VEX_72) },
6480 { REG_TABLE (REG_VEX_73) },
6481 { PREFIX_TABLE (PREFIX_VEX_74) },
6482 { PREFIX_TABLE (PREFIX_VEX_75) },
6483 { PREFIX_TABLE (PREFIX_VEX_76) },
6484 { PREFIX_TABLE (PREFIX_VEX_77) },
6485 /* 78 */
85f10a01
MM		 6486 { "(bad)", { XX } },
6487 { "(bad)", { XX } },
6488 { "(bad)", { XX } },
6489 { "(bad)", { XX } },
c0f3af97
L		 6490 { PREFIX_TABLE (PREFIX_VEX_7C) },
6491 { PREFIX_TABLE (PREFIX_VEX_7D) },
6492 { PREFIX_TABLE (PREFIX_VEX_7E) },
6493 { PREFIX_TABLE (PREFIX_VEX_7F) },
6494 /* 80 */
85f10a01
MM		 6495 { "(bad)", { XX } },
6496 { "(bad)", { XX } },
6497 { "(bad)", { XX } },
6498 { "(bad)", { XX } },
85f10a01
MM		 6499 { "(bad)", { XX } },
6500 { "(bad)", { XX } },
6501 { "(bad)", { XX } },
6502 { "(bad)", { XX } },
c0f3af97 6503 /* 88 */
85f10a01
MM		 6504 { "(bad)", { XX } },
6505 { "(bad)", { XX } },
6506 { "(bad)", { XX } },
6507 { "(bad)", { XX } },
6508 { "(bad)", { XX } },
6509 { "(bad)", { XX } },
6510 { "(bad)", { XX } },
6511 { "(bad)", { XX } },
c0f3af97 6512 /* 90 */
85f10a01
MM		 6513 { "(bad)", { XX } },
6514 { "(bad)", { XX } },
6515 { "(bad)", { XX } },
6516 { "(bad)", { XX } },
6517 { "(bad)", { XX } },
6518 { "(bad)", { XX } },
6519 { "(bad)", { XX } },
85f10a01 6520 { "(bad)", { XX } },
c0f3af97 6521 /* 98 */
85f10a01
MM		 6522 { "(bad)", { XX } },
6523 { "(bad)", { XX } },
6524 { "(bad)", { XX } },
d5d7db8e
L		 6525 { "(bad)", { XX } },
6526 { "(bad)", { XX } },
6527 { "(bad)", { XX } },
6528 { "(bad)", { XX } },
6529 { "(bad)", { XX } },
c0f3af97 6530 /* a0 */
d5d7db8e
L		 6531 { "(bad)", { XX } },
6532 { "(bad)", { XX } },
6533 { "(bad)", { XX } },
6534 { "(bad)", { XX } },
6535 { "(bad)", { XX } },
6536 { "(bad)", { XX } },
6537 { "(bad)", { XX } },
6538 { "(bad)", { XX } },
c0f3af97 6539 /* a8 */
d5d7db8e
L		 6540 { "(bad)", { XX } },
6541 { "(bad)", { XX } },
6542 { "(bad)", { XX } },
6543 { "(bad)", { XX } },
6544 { "(bad)", { XX } },
6545 { "(bad)", { XX } },
c0f3af97 6546 { REG_TABLE (REG_VEX_AE) },
d5d7db8e 6547 { "(bad)", { XX } },
c0f3af97 6548 /* b0 */
d5d7db8e 6549 { "(bad)", { XX } },
d5d7db8e
L		 6550 { "(bad)", { XX } },
6551 { "(bad)", { XX } },
6552 { "(bad)", { XX } },
6553 { "(bad)", { XX } },
6554 { "(bad)", { XX } },
6555 { "(bad)", { XX } },
6556 { "(bad)", { XX } },
c0f3af97 6557 /* b8 */
d5d7db8e 6558 { "(bad)", { XX } },
d5d7db8e
L		 6559 { "(bad)", { XX } },
6560 { "(bad)", { XX } },
6561 { "(bad)", { XX } },
6562 { "(bad)", { XX } },
6563 { "(bad)", { XX } },
6564 { "(bad)", { XX } },
6565 { "(bad)", { XX } },
c0f3af97 6566 /* c0 */
d5d7db8e 6567 { "(bad)", { XX } },
d5d7db8e 6568 { "(bad)", { XX } },
c0f3af97 6569 { PREFIX_TABLE (PREFIX_VEX_C2) },
d5d7db8e 6570 { "(bad)", { XX } },
c0f3af97
L		 6571 { PREFIX_TABLE (PREFIX_VEX_C4) },
6572 { PREFIX_TABLE (PREFIX_VEX_C5) },
6573 { "vshufpX", { XM, Vex, EXx, Ib } },
d5d7db8e 6574 { "(bad)", { XX } },
c0f3af97 6575 /* c8 */
d5d7db8e
L		 6576 { "(bad)", { XX } },
6577 { "(bad)", { XX } },
6578 { "(bad)", { XX } },
6579 { "(bad)", { XX } },
6580 { "(bad)", { XX } },
d5d7db8e
L		 6581 { "(bad)", { XX } },
6582 { "(bad)", { XX } },
6583 { "(bad)", { XX } },
c0f3af97
L		 6584 /* d0 */
6585 { PREFIX_TABLE (PREFIX_VEX_D0) },
6586 { PREFIX_TABLE (PREFIX_VEX_D1) },
6587 { PREFIX_TABLE (PREFIX_VEX_D2) },
6588 { PREFIX_TABLE (PREFIX_VEX_D3) },
6589 { PREFIX_TABLE (PREFIX_VEX_D4) },
6590 { PREFIX_TABLE (PREFIX_VEX_D5) },
6591 { PREFIX_TABLE (PREFIX_VEX_D6) },
6592 { PREFIX_TABLE (PREFIX_VEX_D7) },
6593 /* d8 */
6594 { PREFIX_TABLE (PREFIX_VEX_D8) },
6595 { PREFIX_TABLE (PREFIX_VEX_D9) },
6596 { PREFIX_TABLE (PREFIX_VEX_DA) },
6597 { PREFIX_TABLE (PREFIX_VEX_DB) },
6598 { PREFIX_TABLE (PREFIX_VEX_DC) },
6599 { PREFIX_TABLE (PREFIX_VEX_DD) },
6600 { PREFIX_TABLE (PREFIX_VEX_DE) },
6601 { PREFIX_TABLE (PREFIX_VEX_DF) },
6602 /* e0 */
6603 { PREFIX_TABLE (PREFIX_VEX_E0) },
6604 { PREFIX_TABLE (PREFIX_VEX_E1) },
6605 { PREFIX_TABLE (PREFIX_VEX_E2) },
6606 { PREFIX_TABLE (PREFIX_VEX_E3) },
6607 { PREFIX_TABLE (PREFIX_VEX_E4) },
6608 { PREFIX_TABLE (PREFIX_VEX_E5) },
6609 { PREFIX_TABLE (PREFIX_VEX_E6) },
6610 { PREFIX_TABLE (PREFIX_VEX_E7) },
6611 /* e8 */
6612 { PREFIX_TABLE (PREFIX_VEX_E8) },
6613 { PREFIX_TABLE (PREFIX_VEX_E9) },
6614 { PREFIX_TABLE (PREFIX_VEX_EA) },
6615 { PREFIX_TABLE (PREFIX_VEX_EB) },
6616 { PREFIX_TABLE (PREFIX_VEX_EC) },
6617 { PREFIX_TABLE (PREFIX_VEX_ED) },
6618 { PREFIX_TABLE (PREFIX_VEX_EE) },
6619 { PREFIX_TABLE (PREFIX_VEX_EF) },
6620 /* f0 */
6621 { PREFIX_TABLE (PREFIX_VEX_F0) },
6622 { PREFIX_TABLE (PREFIX_VEX_F1) },
6623 { PREFIX_TABLE (PREFIX_VEX_F2) },
6624 { PREFIX_TABLE (PREFIX_VEX_F3) },
6625 { PREFIX_TABLE (PREFIX_VEX_F4) },
6626 { PREFIX_TABLE (PREFIX_VEX_F5) },
6627 { PREFIX_TABLE (PREFIX_VEX_F6) },
6628 { PREFIX_TABLE (PREFIX_VEX_F7) },
6629 /* f8 */
6630 { PREFIX_TABLE (PREFIX_VEX_F8) },
6631 { PREFIX_TABLE (PREFIX_VEX_F9) },
6632 { PREFIX_TABLE (PREFIX_VEX_FA) },
6633 { PREFIX_TABLE (PREFIX_VEX_FB) },
6634 { PREFIX_TABLE (PREFIX_VEX_FC) },
6635 { PREFIX_TABLE (PREFIX_VEX_FD) },
6636 { PREFIX_TABLE (PREFIX_VEX_FE) },
d5d7db8e 6637 { "(bad)", { XX } },
c0f3af97
L		 6638 },
6639 /* VEX_0F38 */
6640 {
6641 /* 00 */
6642 { PREFIX_TABLE (PREFIX_VEX_3800) },
6643 { PREFIX_TABLE (PREFIX_VEX_3801) },
6644 { PREFIX_TABLE (PREFIX_VEX_3802) },
6645 { PREFIX_TABLE (PREFIX_VEX_3803) },
6646 { PREFIX_TABLE (PREFIX_VEX_3804) },
6647 { PREFIX_TABLE (PREFIX_VEX_3805) },
6648 { PREFIX_TABLE (PREFIX_VEX_3806) },
6649 { PREFIX_TABLE (PREFIX_VEX_3807) },
6650 /* 08 */
6651 { PREFIX_TABLE (PREFIX_VEX_3808) },
6652 { PREFIX_TABLE (PREFIX_VEX_3809) },
6653 { PREFIX_TABLE (PREFIX_VEX_380A) },
6654 { PREFIX_TABLE (PREFIX_VEX_380B) },
6655 { PREFIX_TABLE (PREFIX_VEX_380C) },
6656 { PREFIX_TABLE (PREFIX_VEX_380D) },
6657 { PREFIX_TABLE (PREFIX_VEX_380E) },
6658 { PREFIX_TABLE (PREFIX_VEX_380F) },
6659 /* 10 */
d5d7db8e
L		 6660 { "(bad)", { XX } },
6661 { "(bad)", { XX } },
6662 { "(bad)", { XX } },
6663 { "(bad)", { XX } },
d5d7db8e
L		 6664 { "(bad)", { XX } },
6665 { "(bad)", { XX } },
6666 { "(bad)", { XX } },
c0f3af97
L		 6667 { PREFIX_TABLE (PREFIX_VEX_3817) },
6668 /* 18 */
6669 { PREFIX_TABLE (PREFIX_VEX_3818) },
6670 { PREFIX_TABLE (PREFIX_VEX_3819) },
6671 { PREFIX_TABLE (PREFIX_VEX_381A) },
d5d7db8e 6672 { "(bad)", { XX } },
c0f3af97
L		 6673 { PREFIX_TABLE (PREFIX_VEX_381C) },
6674 { PREFIX_TABLE (PREFIX_VEX_381D) },
6675 { PREFIX_TABLE (PREFIX_VEX_381E) },
d5d7db8e 6676 { "(bad)", { XX } },
c0f3af97
L		 6677 /* 20 */
6678 { PREFIX_TABLE (PREFIX_VEX_3820) },
6679 { PREFIX_TABLE (PREFIX_VEX_3821) },
6680 { PREFIX_TABLE (PREFIX_VEX_3822) },
6681 { PREFIX_TABLE (PREFIX_VEX_3823) },
6682 { PREFIX_TABLE (PREFIX_VEX_3824) },
6683 { PREFIX_TABLE (PREFIX_VEX_3825) },
d5d7db8e
L		 6684 { "(bad)", { XX } },
6685 { "(bad)", { XX } },
c0f3af97
L		 6686 /* 28 */
6687 { PREFIX_TABLE (PREFIX_VEX_3828) },
6688 { PREFIX_TABLE (PREFIX_VEX_3829) },
6689 { PREFIX_TABLE (PREFIX_VEX_382A) },
6690 { PREFIX_TABLE (PREFIX_VEX_382B) },
6691 { PREFIX_TABLE (PREFIX_VEX_382C) },
6692 { PREFIX_TABLE (PREFIX_VEX_382D) },
6693 { PREFIX_TABLE (PREFIX_VEX_382E) },
6694 { PREFIX_TABLE (PREFIX_VEX_382F) },
6695 /* 30 */
6696 { PREFIX_TABLE (PREFIX_VEX_3830) },
6697 { PREFIX_TABLE (PREFIX_VEX_3831) },
6698 { PREFIX_TABLE (PREFIX_VEX_3832) },
6699 { PREFIX_TABLE (PREFIX_VEX_3833) },
6700 { PREFIX_TABLE (PREFIX_VEX_3834) },
6701 { PREFIX_TABLE (PREFIX_VEX_3835) },
6702 { "(bad)", { XX } },
6703 { PREFIX_TABLE (PREFIX_VEX_3837) },
6704 /* 38 */
6705 { PREFIX_TABLE (PREFIX_VEX_3838) },
6706 { PREFIX_TABLE (PREFIX_VEX_3839) },
6707 { PREFIX_TABLE (PREFIX_VEX_383A) },
6708 { PREFIX_TABLE (PREFIX_VEX_383B) },
6709 { PREFIX_TABLE (PREFIX_VEX_383C) },
6710 { PREFIX_TABLE (PREFIX_VEX_383D) },
6711 { PREFIX_TABLE (PREFIX_VEX_383E) },
6712 { PREFIX_TABLE (PREFIX_VEX_383F) },
6713 /* 40 */
6714 { PREFIX_TABLE (PREFIX_VEX_3840) },
6715 { PREFIX_TABLE (PREFIX_VEX_3841) },
d5d7db8e 6716 { "(bad)", { XX } },
d5d7db8e
L		 6717 { "(bad)", { XX } },
6718 { "(bad)", { XX } },
6719 { "(bad)", { XX } },
6720 { "(bad)", { XX } },
6721 { "(bad)", { XX } },
c0f3af97 6722 /* 48 */
d5d7db8e
L		 6723 { "(bad)", { XX } },
6724 { "(bad)", { XX } },
6725 { "(bad)", { XX } },
d5d7db8e
L		 6726 { "(bad)", { XX } },
6727 { "(bad)", { XX } },
6728 { "(bad)", { XX } },
6729 { "(bad)", { XX } },
6730 { "(bad)", { XX } },
c0f3af97 6731 /* 50 */
d5d7db8e
L		 6732 { "(bad)", { XX } },
6733 { "(bad)", { XX } },
6734 { "(bad)", { XX } },
d5d7db8e
L		 6735 { "(bad)", { XX } },
6736 { "(bad)", { XX } },
6737 { "(bad)", { XX } },
6738 { "(bad)", { XX } },
6739 { "(bad)", { XX } },
c0f3af97 6740 /* 58 */
d5d7db8e
L		 6741 { "(bad)", { XX } },
6742 { "(bad)", { XX } },
6743 { "(bad)", { XX } },
d5d7db8e
L		 6744 { "(bad)", { XX } },
6745 { "(bad)", { XX } },
6746 { "(bad)", { XX } },
6747 { "(bad)", { XX } },
6748 { "(bad)", { XX } },
c0f3af97 6749 /* 60 */
d5d7db8e
L		 6750 { "(bad)", { XX } },
6751 { "(bad)", { XX } },
6752 { "(bad)", { XX } },
d5d7db8e
L		 6753 { "(bad)", { XX } },
6754 { "(bad)", { XX } },
6755 { "(bad)", { XX } },
6756 { "(bad)", { XX } },
6757 { "(bad)", { XX } },
c0f3af97 6758 /* 68 */
d5d7db8e
L		 6759 { "(bad)", { XX } },
6760 { "(bad)", { XX } },
6761 { "(bad)", { XX } },
d5d7db8e
L		 6762 { "(bad)", { XX } },
6763 { "(bad)", { XX } },
6764 { "(bad)", { XX } },
6765 { "(bad)", { XX } },
6766 { "(bad)", { XX } },
c0f3af97 6767 /* 70 */
d5d7db8e
L		 6768 { "(bad)", { XX } },
6769 { "(bad)", { XX } },
6770 { "(bad)", { XX } },
d5d7db8e
L		 6771 { "(bad)", { XX } },
6772 { "(bad)", { XX } },
6773 { "(bad)", { XX } },
6774 { "(bad)", { XX } },
6775 { "(bad)", { XX } },
c0f3af97 6776 /* 78 */
d5d7db8e
L		 6777 { "(bad)", { XX } },
6778 { "(bad)", { XX } },
6779 { "(bad)", { XX } },
d5d7db8e
L		 6780 { "(bad)", { XX } },
6781 { "(bad)", { XX } },
6782 { "(bad)", { XX } },
6783 { "(bad)", { XX } },
6784 { "(bad)", { XX } },
c0f3af97 6785 /* 80 */
d5d7db8e
L		 6786 { "(bad)", { XX } },
6787 { "(bad)", { XX } },
6788 { "(bad)", { XX } },
d5d7db8e
L		 6789 { "(bad)", { XX } },
6790 { "(bad)", { XX } },
6791 { "(bad)", { XX } },
6792 { "(bad)", { XX } },
6793 { "(bad)", { XX } },
c0f3af97 6794 /* 88 */
d5d7db8e
L		 6795 { "(bad)", { XX } },
6796 { "(bad)", { XX } },
6797 { "(bad)", { XX } },
d5d7db8e
L		 6798 { "(bad)", { XX } },
6799 { "(bad)", { XX } },
6800 { "(bad)", { XX } },
6801 { "(bad)", { XX } },
6802 { "(bad)", { XX } },
c0f3af97 6803 /* 90 */
d5d7db8e
L		 6804 { "(bad)", { XX } },
6805 { "(bad)", { XX } },
6806 { "(bad)", { XX } },
d5d7db8e
L		 6807 { "(bad)", { XX } },
6808 { "(bad)", { XX } },
6809 { "(bad)", { XX } },
0bfee649
L		 6810 { PREFIX_TABLE (PREFIX_VEX_3896) },
6811 { PREFIX_TABLE (PREFIX_VEX_3897) },
c0f3af97 6812 /* 98 */
0bfee649
L		 6813 { PREFIX_TABLE (PREFIX_VEX_3898) },
6814 { PREFIX_TABLE (PREFIX_VEX_3899) },
6815 { PREFIX_TABLE (PREFIX_VEX_389A) },
6816 { PREFIX_TABLE (PREFIX_VEX_389B) },
6817 { PREFIX_TABLE (PREFIX_VEX_389C) },
6818 { PREFIX_TABLE (PREFIX_VEX_389D) },
6819 { PREFIX_TABLE (PREFIX_VEX_389E) },
6820 { PREFIX_TABLE (PREFIX_VEX_389F) },
c0f3af97 6821 /* a0 */
d5d7db8e
L		 6822 { "(bad)", { XX } },
6823 { "(bad)", { XX } },
6824 { "(bad)", { XX } },
d5d7db8e
L		 6825 { "(bad)", { XX } },
6826 { "(bad)", { XX } },
6827 { "(bad)", { XX } },
0bfee649
L		 6828 { PREFIX_TABLE (PREFIX_VEX_38A6) },
6829 { PREFIX_TABLE (PREFIX_VEX_38A7) },
c0f3af97 6830 /* a8 */
0bfee649
L		 6831 { PREFIX_TABLE (PREFIX_VEX_38A8) },
6832 { PREFIX_TABLE (PREFIX_VEX_38A9) },
6833 { PREFIX_TABLE (PREFIX_VEX_38AA) },
6834 { PREFIX_TABLE (PREFIX_VEX_38AB) },
6835 { PREFIX_TABLE (PREFIX_VEX_38AC) },
6836 { PREFIX_TABLE (PREFIX_VEX_38AD) },
6837 { PREFIX_TABLE (PREFIX_VEX_38AE) },
6838 { PREFIX_TABLE (PREFIX_VEX_38AF) },
c0f3af97 6839 /* b0 */
d5d7db8e
L		 6840 { "(bad)", { XX } },
6841 { "(bad)", { XX } },
6842 { "(bad)", { XX } },
6843 { "(bad)", { XX } },
6844 { "(bad)", { XX } },
6845 { "(bad)", { XX } },
0bfee649
L		 6846 { PREFIX_TABLE (PREFIX_VEX_38B6) },
6847 { PREFIX_TABLE (PREFIX_VEX_38B7) },
c0f3af97 6848 /* b8 */
0bfee649
L		 6849 { PREFIX_TABLE (PREFIX_VEX_38B8) },
6850 { PREFIX_TABLE (PREFIX_VEX_38B9) },
6851 { PREFIX_TABLE (PREFIX_VEX_38BA) },
6852 { PREFIX_TABLE (PREFIX_VEX_38BB) },
6853 { PREFIX_TABLE (PREFIX_VEX_38BC) },
6854 { PREFIX_TABLE (PREFIX_VEX_38BD) },
6855 { PREFIX_TABLE (PREFIX_VEX_38BE) },
6856 { PREFIX_TABLE (PREFIX_VEX_38BF) },
c0f3af97 6857 /* c0 */
d5d7db8e
L		 6858 { "(bad)", { XX } },
6859 { "(bad)", { XX } },
6860 { "(bad)", { XX } },
6861 { "(bad)", { XX } },
d5d7db8e
L		 6862 { "(bad)", { XX } },
6863 { "(bad)", { XX } },
6864 { "(bad)", { XX } },
6865 { "(bad)", { XX } },
c0f3af97 6866 /* c8 */
d5d7db8e
L		 6867 { "(bad)", { XX } },
6868 { "(bad)", { XX } },
6869 { "(bad)", { XX } },
6870 { "(bad)", { XX } },
d5d7db8e 6871 { "(bad)", { XX } },
d5d7db8e
L		 6872 { "(bad)", { XX } },
6873 { "(bad)", { XX } },
d5d7db8e 6874 { "(bad)", { XX } },
c0f3af97 6875 /* d0 */
d5d7db8e
L		 6876 { "(bad)", { XX } },
6877 { "(bad)", { XX } },
d5d7db8e
L		 6878 { "(bad)", { XX } },
6879 { "(bad)", { XX } },
6880 { "(bad)", { XX } },
6881 { "(bad)", { XX } },
d5d7db8e 6882 { "(bad)", { XX } },
d5d7db8e 6883 { "(bad)", { XX } },
c0f3af97 6884 /* d8 */
d5d7db8e 6885 { "(bad)", { XX } },
d5d7db8e
L		 6886 { "(bad)", { XX } },
6887 { "(bad)", { XX } },
a5ff0eb2
L		 6888 { PREFIX_TABLE (PREFIX_VEX_38DB) },
6889 { PREFIX_TABLE (PREFIX_VEX_38DC) },
6890 { PREFIX_TABLE (PREFIX_VEX_38DD) },
6891 { PREFIX_TABLE (PREFIX_VEX_38DE) },
6892 { PREFIX_TABLE (PREFIX_VEX_38DF) },
c0f3af97 6893 /* e0 */
d5d7db8e 6894 { "(bad)", { XX } },
d5d7db8e
L		 6895 { "(bad)", { XX } },
6896 { "(bad)", { XX } },
6897 { "(bad)", { XX } },
6898 { "(bad)", { XX } },
d5d7db8e
L		 6899 { "(bad)", { XX } },
6900 { "(bad)", { XX } },
6901 { "(bad)", { XX } },
c0f3af97 6902 /* e8 */
d5d7db8e
L		 6903 { "(bad)", { XX } },
6904 { "(bad)", { XX } },
6905 { "(bad)", { XX } },
6906 { "(bad)", { XX } },
6907 { "(bad)", { XX } },
d5d7db8e
L		 6908 { "(bad)", { XX } },
6909 { "(bad)", { XX } },
6910 { "(bad)", { XX } },
c0f3af97 6911 /* f0 */
d5d7db8e
L		 6912 { "(bad)", { XX } },
6913 { "(bad)", { XX } },
6914 { "(bad)", { XX } },
6915 { "(bad)", { XX } },
6916 { "(bad)", { XX } },
d5d7db8e
L		 6917 { "(bad)", { XX } },
6918 { "(bad)", { XX } },
6919 { "(bad)", { XX } },
c0f3af97 6920 /* f8 */
d5d7db8e
L		 6921 { "(bad)", { XX } },
6922 { "(bad)", { XX } },
6923 { "(bad)", { XX } },
6924 { "(bad)", { XX } },
6925 { "(bad)", { XX } },
d5d7db8e
L		 6926 { "(bad)", { XX } },
6927 { "(bad)", { XX } },
6928 { "(bad)", { XX } },
c0f3af97
L		 6929 },
6930 /* VEX_0F3A */
6931 {
6932 /* 00 */
d5d7db8e
L		 6933 { "(bad)", { XX } },
6934 { "(bad)", { XX } },
6935 { "(bad)", { XX } },
6936 { "(bad)", { XX } },
c0f3af97
L		 6937 { PREFIX_TABLE (PREFIX_VEX_3A04) },
6938 { PREFIX_TABLE (PREFIX_VEX_3A05) },
6939 { PREFIX_TABLE (PREFIX_VEX_3A06) },
d5d7db8e 6940 { "(bad)", { XX } },
c0f3af97
L		 6941 /* 08 */
6942 { PREFIX_TABLE (PREFIX_VEX_3A08) },
6943 { PREFIX_TABLE (PREFIX_VEX_3A09) },
6944 { PREFIX_TABLE (PREFIX_VEX_3A0A) },
6945 { PREFIX_TABLE (PREFIX_VEX_3A0B) },
6946 { PREFIX_TABLE (PREFIX_VEX_3A0C) },
6947 { PREFIX_TABLE (PREFIX_VEX_3A0D) },
6948 { PREFIX_TABLE (PREFIX_VEX_3A0E) },
6949 { PREFIX_TABLE (PREFIX_VEX_3A0F) },
6950 /* 10 */
d5d7db8e
L		 6951 { "(bad)", { XX } },
6952 { "(bad)", { XX } },
6953 { "(bad)", { XX } },
6954 { "(bad)", { XX } },
c0f3af97
L		 6955 { PREFIX_TABLE (PREFIX_VEX_3A14) },
6956 { PREFIX_TABLE (PREFIX_VEX_3A15) },
6957 { PREFIX_TABLE (PREFIX_VEX_3A16) },
6958 { PREFIX_TABLE (PREFIX_VEX_3A17) },
6959 /* 18 */
6960 { PREFIX_TABLE (PREFIX_VEX_3A18) },
6961 { PREFIX_TABLE (PREFIX_VEX_3A19) },
d5d7db8e
L		 6962 { "(bad)", { XX } },
6963 { "(bad)", { XX } },
6964 { "(bad)", { XX } },
6965 { "(bad)", { XX } },
d5d7db8e
L		 6966 { "(bad)", { XX } },
6967 { "(bad)", { XX } },
c0f3af97
L		 6968 /* 20 */
6969 { PREFIX_TABLE (PREFIX_VEX_3A20) },
6970 { PREFIX_TABLE (PREFIX_VEX_3A21) },
6971 { PREFIX_TABLE (PREFIX_VEX_3A22) },
d5d7db8e
L		 6972 { "(bad)", { XX } },
6973 { "(bad)", { XX } },
6974 { "(bad)", { XX } },
6975 { "(bad)", { XX } },
6976 { "(bad)", { XX } },
c0f3af97 6977 /* 28 */
d5d7db8e 6978 { "(bad)", { XX } },
d5d7db8e
L		 6979 { "(bad)", { XX } },
6980 { "(bad)", { XX } },
6981 { "(bad)", { XX } },
6982 { "(bad)", { XX } },
6983 { "(bad)", { XX } },
6984 { "(bad)", { XX } },
6985 { "(bad)", { XX } },
c0f3af97 6986 /* 30 */
d5d7db8e 6987 { "(bad)", { XX } },
d5d7db8e
L		 6988 { "(bad)", { XX } },
6989 { "(bad)", { XX } },
6990 { "(bad)", { XX } },
6991 { "(bad)", { XX } },
6992 { "(bad)", { XX } },
6993 { "(bad)", { XX } },
6994 { "(bad)", { XX } },
c0f3af97 6995 /* 38 */
d5d7db8e 6996 { "(bad)", { XX } },
d5d7db8e
L		 6997 { "(bad)", { XX } },
6998 { "(bad)", { XX } },
6999 { "(bad)", { XX } },
7000 { "(bad)", { XX } },
7001 { "(bad)", { XX } },
7002 { "(bad)", { XX } },
7003 { "(bad)", { XX } },
c0f3af97
L		 7004 /* 40 */
7005 { PREFIX_TABLE (PREFIX_VEX_3A40) },
7006 { PREFIX_TABLE (PREFIX_VEX_3A41) },
7007 { PREFIX_TABLE (PREFIX_VEX_3A42) },
d5d7db8e 7008 { "(bad)", { XX } },
ce2f5b3c 7009 { PREFIX_TABLE (PREFIX_VEX_3A44) },
d5d7db8e
L		 7010 { "(bad)", { XX } },
7011 { "(bad)", { XX } },
7012 { "(bad)", { XX } },
c0f3af97 7013 /* 48 */
0bfee649
L		 7014 { "(bad)", { XX } },
7015 { "(bad)", { XX } },
c0f3af97
L		 7016 { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7017 { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7018 { PREFIX_TABLE (PREFIX_VEX_3A4C) },
d5d7db8e
L		 7019 { "(bad)", { XX } },
7020 { "(bad)", { XX } },
7021 { "(bad)", { XX } },
c0f3af97 7022 /* 50 */
d5d7db8e 7023 { "(bad)", { XX } },
d5d7db8e
L		 7024 { "(bad)", { XX } },
7025 { "(bad)", { XX } },
7026 { "(bad)", { XX } },
7027 { "(bad)", { XX } },
7028 { "(bad)", { XX } },
7029 { "(bad)", { XX } },
7030 { "(bad)", { XX } },
c0f3af97 7031 /* 58 */
d5d7db8e 7032 { "(bad)", { XX } },
d5d7db8e
L		 7033 { "(bad)", { XX } },
7034 { "(bad)", { XX } },
7035 { "(bad)", { XX } },
922d8de8
DR		 7036 { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7037 { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7038 { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7039 { PREFIX_TABLE (PREFIX_VEX_3A5F) },
c0f3af97
L		 7040 /* 60 */
7041 { PREFIX_TABLE (PREFIX_VEX_3A60) },
7042 { PREFIX_TABLE (PREFIX_VEX_3A61) },
7043 { PREFIX_TABLE (PREFIX_VEX_3A62) },
7044 { PREFIX_TABLE (PREFIX_VEX_3A63) },
d5d7db8e
L		 7045 { "(bad)", { XX } },
7046 { "(bad)", { XX } },
7047 { "(bad)", { XX } },
7048 { "(bad)", { XX } },
c0f3af97 7049 /* 68 */
922d8de8
DR		 7050 { PREFIX_TABLE (PREFIX_VEX_3A68) },
7051 { PREFIX_TABLE (PREFIX_VEX_3A69) },
7052 { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7053 { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7054 { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7055 { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7056 { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7057 { PREFIX_TABLE (PREFIX_VEX_3A6F) },
c0f3af97 7058 /* 70 */
d5d7db8e 7059 { "(bad)", { XX } },
d5d7db8e
L		 7060 { "(bad)", { XX } },
7061 { "(bad)", { XX } },
7062 { "(bad)", { XX } },
7063 { "(bad)", { XX } },
7064 { "(bad)", { XX } },
7065 { "(bad)", { XX } },
7066 { "(bad)", { XX } },
c0f3af97 7067 /* 78 */
922d8de8
DR		 7068 { PREFIX_TABLE (PREFIX_VEX_3A78) },
7069 { PREFIX_TABLE (PREFIX_VEX_3A79) },
7070 { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7071 { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7072 { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7073 { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7074 { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7075 { PREFIX_TABLE (PREFIX_VEX_3A7F) },
c0f3af97 7076 /* 80 */
d5d7db8e 7077 { "(bad)", { XX } },
d5d7db8e
L		 7078 { "(bad)", { XX } },
7079 { "(bad)", { XX } },
7080 { "(bad)", { XX } },
7081 { "(bad)", { XX } },
7082 { "(bad)", { XX } },
7083 { "(bad)", { XX } },
7084 { "(bad)", { XX } },
c0f3af97 7085 /* 88 */
d5d7db8e 7086 { "(bad)", { XX } },
d5d7db8e
L		 7087 { "(bad)", { XX } },
7088 { "(bad)", { XX } },
7089 { "(bad)", { XX } },
7090 { "(bad)", { XX } },
7091 { "(bad)", { XX } },
7092 { "(bad)", { XX } },
7093 { "(bad)", { XX } },
c0f3af97 7094 /* 90 */
d5d7db8e 7095 { "(bad)", { XX } },
d5d7db8e
L		 7096 { "(bad)", { XX } },
7097 { "(bad)", { XX } },
7098 { "(bad)", { XX } },
7099 { "(bad)", { XX } },
7100 { "(bad)", { XX } },
7101 { "(bad)", { XX } },
7102 { "(bad)", { XX } },
c0f3af97 7103 /* 98 */
d5d7db8e 7104 { "(bad)", { XX } },
d5d7db8e
L		 7105 { "(bad)", { XX } },
7106 { "(bad)", { XX } },
7107 { "(bad)", { XX } },
7108 { "(bad)", { XX } },
7109 { "(bad)", { XX } },
7110 { "(bad)", { XX } },
7111 { "(bad)", { XX } },
c0f3af97 7112 /* a0 */
d5d7db8e 7113 { "(bad)", { XX } },
85f10a01
MM		 7114 { "(bad)", { XX } },
7115 { "(bad)", { XX } },
d5d7db8e
L		 7116 { "(bad)", { XX } },
7117 { "(bad)", { XX } },
7118 { "(bad)", { XX } },
7119 { "(bad)", { XX } },
7120 { "(bad)", { XX } },
c0f3af97 7121 /* a8 */
d5d7db8e 7122 { "(bad)", { XX } },
d5d7db8e
L		 7123 { "(bad)", { XX } },
7124 { "(bad)", { XX } },
7125 { "(bad)", { XX } },
7126 { "(bad)", { XX } },
7127 { "(bad)", { XX } },
7128 { "(bad)", { XX } },
7129 { "(bad)", { XX } },
c0f3af97
L		 7130 /* b0 */
7131 { "(bad)", { XX } },
7132 { "(bad)", { XX } },
7133 { "(bad)", { XX } },
7134 { "(bad)", { XX } },
7135 { "(bad)", { XX } },
7136 { "(bad)", { XX } },
7137 { "(bad)", { XX } },
7138 { "(bad)", { XX } },
7139 /* b8 */
7140 { "(bad)", { XX } },
7141 { "(bad)", { XX } },
7142 { "(bad)", { XX } },
7143 { "(bad)", { XX } },
7144 { "(bad)", { XX } },
7145 { "(bad)", { XX } },
7146 { "(bad)", { XX } },
7147 { "(bad)", { XX } },
7148 /* c0 */
7149 { "(bad)", { XX } },
7150 { "(bad)", { XX } },
7151 { "(bad)", { XX } },
7152 { "(bad)", { XX } },
7153 { "(bad)", { XX } },
7154 { "(bad)", { XX } },
7155 { "(bad)", { XX } },
7156 { "(bad)", { XX } },
7157 /* c8 */
7158 { "(bad)", { XX } },
7159 { "(bad)", { XX } },
d5d7db8e 7160 { "(bad)", { XX } },
d5d7db8e
L		 7161 { "(bad)", { XX } },
7162 { "(bad)", { XX } },
7163 { "(bad)", { XX } },
7164 { "(bad)", { XX } },
7165 { "(bad)", { XX } },
c0f3af97
L		 7166 /* d0 */
7167 { "(bad)", { XX } },
7168 { "(bad)", { XX } },
7169 { "(bad)", { XX } },
d5d7db8e
L		 7170 { "(bad)", { XX } },
7171 { "(bad)", { XX } },
7172 { "(bad)", { XX } },
c0f3af97
L		 7173 { "(bad)", { XX } },
7174 { "(bad)", { XX } },
7175 /* d8 */
7176 { "(bad)", { XX } },
d5d7db8e
L		 7177 { "(bad)", { XX } },
7178 { "(bad)", { XX } },
7179 { "(bad)", { XX } },
7180 { "(bad)", { XX } },
7181 { "(bad)", { XX } },
7182 { "(bad)", { XX } },
a5ff0eb2 7183 { PREFIX_TABLE (PREFIX_VEX_3ADF) },
c0f3af97 7184 /* e0 */
d5d7db8e 7185 { "(bad)", { XX } },
d5d7db8e
L		 7186 { "(bad)", { XX } },
7187 { "(bad)", { XX } },
7188 { "(bad)", { XX } },
7189 { "(bad)", { XX } },
7190 { "(bad)", { XX } },
7191 { "(bad)", { XX } },
7192 { "(bad)", { XX } },
c0f3af97 7193 /* e8 */
d5d7db8e 7194 { "(bad)", { XX } },
d5d7db8e
L		 7195 { "(bad)", { XX } },
7196 { "(bad)", { XX } },
7197 { "(bad)", { XX } },
7198 { "(bad)", { XX } },
7199 { "(bad)", { XX } },
7200 { "(bad)", { XX } },
7201 { "(bad)", { XX } },
c0f3af97 7202 /* f0 */
d5d7db8e 7203 { "(bad)", { XX } },
d5d7db8e
L		 7204 { "(bad)", { XX } },
7205 { "(bad)", { XX } },
7206 { "(bad)", { XX } },
7207 { "(bad)", { XX } },
7208 { "(bad)", { XX } },
7209 { "(bad)", { XX } },
7210 { "(bad)", { XX } },
c0f3af97 7211 /* f8 */
d5d7db8e 7212 { "(bad)", { XX } },
d5d7db8e
L		 7213 { "(bad)", { XX } },
7214 { "(bad)", { XX } },
7215 { "(bad)", { XX } },
7216 { "(bad)", { XX } },
7217 { "(bad)", { XX } },
7218 { "(bad)", { XX } },
7219 { "(bad)", { XX } },
c0f3af97
L		 7220 },
7221};
7222
7223static const struct dis386 vex_len_table[][2] = {
7224 /* VEX_LEN_10_P_1 */
7225 {
7226 { "vmovss", { XMVex, Vex128, EXd } },
d5d7db8e 7227 { "(bad)", { XX } },
c0f3af97
L		 7228 },
7229
7230 /* VEX_LEN_10_P_3 */
7231 {
7232 { "vmovsd", { XMVex, Vex128, EXq } },
d5d7db8e 7233 { "(bad)", { XX } },
c0f3af97
L		 7234 },
7235
7236 /* VEX_LEN_11_P_1 */
7237 {
fa99fab2 7238 { "vmovss", { EXdVexS, Vex128, XM } },
d5d7db8e 7239 { "(bad)", { XX } },
c0f3af97
L		 7240 },
7241
7242 /* VEX_LEN_11_P_3 */
7243 {
fa99fab2 7244 { "vmovsd", { EXqVexS, Vex128, XM } },
d5d7db8e 7245 { "(bad)", { XX } },
c0f3af97
L		 7246 },
7247
7248 /* VEX_LEN_12_P_0_M_0 */
7249 {
7250 { "vmovlps", { XM, Vex128, EXq } },
d5d7db8e 7251 { "(bad)", { XX } },
c0f3af97
L		 7252 },
7253
7254 /* VEX_LEN_12_P_0_M_1 */
7255 {
7256 { "vmovhlps", { XM, Vex128, EXq } },
d5d7db8e 7257 { "(bad)", { XX } },
c0f3af97
L		 7258 },
7259
7260 /* VEX_LEN_12_P_2 */
7261 {
7262 { "vmovlpd", { XM, Vex128, EXq } },
d5d7db8e 7263 { "(bad)", { XX } },
c0f3af97
L		 7264 },
7265
7266 /* VEX_LEN_13_M_0 */
7267 {
7268 { "vmovlpX", { EXq, XM } },
85f10a01 7269 { "(bad)", { XX } },
c0f3af97
L		 7270 },
7271
7272 /* VEX_LEN_16_P_0_M_0 */
7273 {
7274 { "vmovhps", { XM, Vex128, EXq } },
85f10a01 7275 { "(bad)", { XX } },
c0f3af97
L		 7276 },
7277
7278 /* VEX_LEN_16_P_0_M_1 */
7279 {
7280 { "vmovlhps", { XM, Vex128, EXq } },
85f10a01 7281 { "(bad)", { XX } },
c0f3af97
L		 7282 },
7283
7284 /* VEX_LEN_16_P_2 */
7285 {
7286 { "vmovhpd", { XM, Vex128, EXq } },
85f10a01 7287 { "(bad)", { XX } },
c0f3af97
L		 7288 },
7289
7290 /* VEX_LEN_17_M_0 */
7291 {
7292 { "vmovhpX", { EXq, XM } },
85f10a01 7293 { "(bad)", { XX } },
c0f3af97
L		 7294 },
7295
7296 /* VEX_LEN_2A_P_1 */
7297 {
7298 { "vcvtsi2ss%LQ", { XM, Vex128, Ev } },
d5d7db8e 7299 { "(bad)", { XX } },
c0f3af97
L		 7300 },
7301
7302 /* VEX_LEN_2A_P_3 */
7303 {
7304 { "vcvtsi2sd%LQ", { XM, Vex128, Ev } },
d5d7db8e 7305 { "(bad)", { XX } },
c0f3af97
L		 7306 },
7307
c0f3af97
L		 7308 /* VEX_LEN_2C_P_1 */
7309 {
7310 { "vcvttss2siY", { Gv, EXd } },
d5d7db8e 7311 { "(bad)", { XX } },
c0f3af97
L		 7312 },
7313
7314 /* VEX_LEN_2C_P_3 */
7315 {
7316 { "vcvttsd2siY", { Gv, EXq } },
d5d7db8e 7317 { "(bad)", { XX } },
c0f3af97
L		 7318 },
7319
7320 /* VEX_LEN_2D_P_1 */
7321 {
7322 { "vcvtss2siY", { Gv, EXd } },
85f10a01 7323 { "(bad)", { XX } },
c0f3af97
L		 7324 },
7325
7326 /* VEX_LEN_2D_P_3 */
7327 {
7328 { "vcvtsd2siY", { Gv, EXq } },
d5d7db8e 7329 { "(bad)", { XX } },
c0f3af97
L		 7330 },
7331
7332 /* VEX_LEN_2E_P_0 */
7333 {
7334 { "vucomiss", { XM, EXd } },
d5d7db8e 7335 { "(bad)", { XX } },
c0f3af97
L		 7336 },
7337
7338 /* VEX_LEN_2E_P_2 */
7339 {
7340 { "vucomisd", { XM, EXq } },
d5d7db8e 7341 { "(bad)", { XX } },
c0f3af97
L		 7342 },
7343
7344 /* VEX_LEN_2F_P_0 */
7345 {
7346 { "vcomiss", { XM, EXd } },
d5d7db8e 7347 { "(bad)", { XX } },
c0f3af97
L		 7348 },
7349
7350 /* VEX_LEN_2F_P_2 */
7351 {
7352 { "vcomisd", { XM, EXq } },
d5d7db8e 7353 { "(bad)", { XX } },
c0f3af97
L		 7354 },
7355
7356 /* VEX_LEN_51_P_1 */
7357 {
7358 { "vsqrtss", { XM, Vex128, EXd } },
d5d7db8e 7359 { "(bad)", { XX } },
c0f3af97
L		 7360 },
7361
7362 /* VEX_LEN_51_P_3 */
7363 {
7364 { "vsqrtsd", { XM, Vex128, EXq } },
d5d7db8e 7365 { "(bad)", { XX } },
c0f3af97
L		 7366 },
7367
7368 /* VEX_LEN_52_P_1 */
7369 {
7370 { "vrsqrtss", { XM, Vex128, EXd } },
d5d7db8e 7371 { "(bad)", { XX } },
c0f3af97
L		 7372 },
7373
7374 /* VEX_LEN_53_P_1 */
7375 {
7376 { "vrcpss", { XM, Vex128, EXd } },
d5d7db8e 7377 { "(bad)", { XX } },
c0f3af97
L		 7378 },
7379
7380 /* VEX_LEN_58_P_1 */
7381 {
7382 { "vaddss", { XM, Vex128, EXd } },
d5d7db8e 7383 { "(bad)", { XX } },
c0f3af97
L		 7384 },
7385
7386 /* VEX_LEN_58_P_3 */
7387 {
7388 { "vaddsd", { XM, Vex128, EXq } },
d5d7db8e 7389 { "(bad)", { XX } },
c0f3af97
L		 7390 },
7391
7392 /* VEX_LEN_59_P_1 */
7393 {
7394 { "vmulss", { XM, Vex128, EXd } },
d5d7db8e 7395 { "(bad)", { XX } },
c0f3af97
L		 7396 },
7397
7398 /* VEX_LEN_59_P_3 */
7399 {
7400 { "vmulsd", { XM, Vex128, EXq } },
d5d7db8e 7401 { "(bad)", { XX } },
c0f3af97
L		 7402 },
7403
7404 /* VEX_LEN_5A_P_1 */
7405 {
7406 { "vcvtss2sd", { XM, Vex128, EXd } },
d5d7db8e 7407 { "(bad)", { XX } },
c0f3af97
L		 7408 },
7409
7410 /* VEX_LEN_5A_P_3 */
7411 {
7412 { "vcvtsd2ss", { XM, Vex128, EXq } },
d5d7db8e 7413 { "(bad)", { XX } },
c0f3af97
L		 7414 },
7415
7416 /* VEX_LEN_5C_P_1 */
7417 {
7418 { "vsubss", { XM, Vex128, EXd } },
d5d7db8e 7419 { "(bad)", { XX } },
c0f3af97
L		 7420 },
7421
7422 /* VEX_LEN_5C_P_3 */
7423 {
7424 { "vsubsd", { XM, Vex128, EXq } },
d5d7db8e 7425 { "(bad)", { XX } },
c0f3af97
L		 7426 },
7427
7428 /* VEX_LEN_5D_P_1 */
7429 {
7430 { "vminss", { XM, Vex128, EXd } },
d5d7db8e 7431 { "(bad)", { XX } },
c0f3af97
L		 7432 },
7433
7434 /* VEX_LEN_5D_P_3 */
7435 {
7436 { "vminsd", { XM, Vex128, EXq } },
d5d7db8e 7437 { "(bad)", { XX } },
c0f3af97
L		 7438 },
7439
7440 /* VEX_LEN_5E_P_1 */
7441 {
7442 { "vdivss", { XM, Vex128, EXd } },
85f10a01 7443 { "(bad)", { XX } },
c0f3af97
L		 7444 },
7445
7446 /* VEX_LEN_5E_P_3 */
7447 {
7448 { "vdivsd", { XM, Vex128, EXq } },
85f10a01 7449 { "(bad)", { XX } },
c0f3af97
L		 7450 },
7451
7452 /* VEX_LEN_5F_P_1 */
7453 {
7454 { "vmaxss", { XM, Vex128, EXd } },
85f10a01 7455 { "(bad)", { XX } },
c0f3af97
L		 7456 },
7457
7458 /* VEX_LEN_5F_P_3 */
7459 {
7460 { "vmaxsd", { XM, Vex128, EXq } },
85f10a01 7461 { "(bad)", { XX } },
c0f3af97
L		 7462 },
7463
7464 /* VEX_LEN_60_P_2 */
7465 {
7466 { "vpunpcklbw", { XM, Vex128, EXx } },
d5d7db8e 7467 { "(bad)", { XX } },
c0f3af97
L		 7468 },
7469
7470 /* VEX_LEN_61_P_2 */
7471 {
7472 { "vpunpcklwd", { XM, Vex128, EXx } },
d5d7db8e 7473 { "(bad)", { XX } },
c0f3af97
L		 7474 },
7475
7476 /* VEX_LEN_62_P_2 */
7477 {
7478 { "vpunpckldq", { XM, Vex128, EXx } },
d5d7db8e 7479 { "(bad)", { XX } },
c0f3af97
L		 7480 },
7481
7482 /* VEX_LEN_63_P_2 */
7483 {
7484 { "vpacksswb", { XM, Vex128, EXx } },
d5d7db8e 7485 { "(bad)", { XX } },
c0f3af97
L		 7486 },
7487
7488 /* VEX_LEN_64_P_2 */
7489 {
7490 { "vpcmpgtb", { XM, Vex128, EXx } },
d5d7db8e 7491 { "(bad)", { XX } },
c0f3af97
L		 7492 },
7493
7494 /* VEX_LEN_65_P_2 */
7495 {
7496 { "vpcmpgtw", { XM, Vex128, EXx } },
d5d7db8e 7497 { "(bad)", { XX } },
c0f3af97
L		 7498 },
7499
7500 /* VEX_LEN_66_P_2 */
7501 {
7502 { "vpcmpgtd", { XM, Vex128, EXx } },
d5d7db8e 7503 { "(bad)", { XX } },
c0f3af97
L		 7504 },
7505
7506 /* VEX_LEN_67_P_2 */
7507 {
7508 { "vpackuswb", { XM, Vex128, EXx } },
d5d7db8e 7509 { "(bad)", { XX } },
c0f3af97
L		 7510 },
7511
7512 /* VEX_LEN_68_P_2 */
7513 {
7514 { "vpunpckhbw", { XM, Vex128, EXx } },
d5d7db8e 7515 { "(bad)", { XX } },
c0f3af97
L		 7516 },
7517
7518 /* VEX_LEN_69_P_2 */
7519 {
7520 { "vpunpckhwd", { XM, Vex128, EXx } },
d5d7db8e 7521 { "(bad)", { XX } },
c0f3af97
L		 7522 },
7523
7524 /* VEX_LEN_6A_P_2 */
7525 {
7526 { "vpunpckhdq", { XM, Vex128, EXx } },
d5d7db8e 7527 { "(bad)", { XX } },
c0f3af97
L		 7528 },
7529
7530 /* VEX_LEN_6B_P_2 */
7531 {
7532 { "vpackssdw", { XM, Vex128, EXx } },
d5d7db8e 7533 { "(bad)", { XX } },
c0f3af97
L		 7534 },
7535
7536 /* VEX_LEN_6C_P_2 */
7537 {
7538 { "vpunpcklqdq", { XM, Vex128, EXx } },
d5d7db8e 7539 { "(bad)", { XX } },
c0f3af97
L		 7540 },
7541
7542 /* VEX_LEN_6D_P_2 */
7543 {
7544 { "vpunpckhqdq", { XM, Vex128, EXx } },
d5d7db8e 7545 { "(bad)", { XX } },
c0f3af97
L		 7546 },
7547
7548 /* VEX_LEN_6E_P_2 */
7549 {
7550 { "vmovK", { XM, Edq } },
d5d7db8e 7551 { "(bad)", { XX } },
c0f3af97
L		 7552 },
7553
7554 /* VEX_LEN_70_P_1 */
7555 {
7556 { "vpshufhw", { XM, EXx, Ib } },
d5d7db8e 7557 { "(bad)", { XX } },
c0f3af97
L		 7558 },
7559
7560 /* VEX_LEN_70_P_2 */
7561 {
7562 { "vpshufd", { XM, EXx, Ib } },
d5d7db8e 7563 { "(bad)", { XX } },
c0f3af97
L		 7564 },
7565
7566 /* VEX_LEN_70_P_3 */
7567 {
7568 { "vpshuflw", { XM, EXx, Ib } },
d5d7db8e 7569 { "(bad)", { XX } },
c0f3af97
L		 7570 },
7571
7572 /* VEX_LEN_71_R_2_P_2 */
7573 {
7574 { "vpsrlw", { Vex128, XS, Ib } },
d5d7db8e 7575 { "(bad)", { XX } },
c0f3af97
L		 7576 },
7577
7578 /* VEX_LEN_71_R_4_P_2 */
7579 {
7580 { "vpsraw", { Vex128, XS, Ib } },
d5d7db8e 7581 { "(bad)", { XX } },
c0f3af97
L		 7582 },
7583
7584 /* VEX_LEN_71_R_6_P_2 */
7585 {
7586 { "vpsllw", { Vex128, XS, Ib } },
d5d7db8e 7587 { "(bad)", { XX } },
c0f3af97
L		 7588 },
7589
7590 /* VEX_LEN_72_R_2_P_2 */
7591 {
7592 { "vpsrld", { Vex128, XS, Ib } },
d5d7db8e 7593 { "(bad)", { XX } },
c0f3af97
L		 7594 },
7595
7596 /* VEX_LEN_72_R_4_P_2 */
7597 {
7598 { "vpsrad", { Vex128, XS, Ib } },
d5d7db8e 7599 { "(bad)", { XX } },
c0f3af97
L		 7600 },
7601
7602 /* VEX_LEN_72_R_6_P_2 */
7603 {
7604 { "vpslld", { Vex128, XS, Ib } },
d5d7db8e 7605 { "(bad)", { XX } },
c0f3af97
L		 7606 },
7607
7608 /* VEX_LEN_73_R_2_P_2 */
7609 {
7610 { "vpsrlq", { Vex128, XS, Ib } },
d5d7db8e 7611 { "(bad)", { XX } },
c0f3af97
L		 7612 },
7613
7614 /* VEX_LEN_73_R_3_P_2 */
7615 {
7616 { "vpsrldq", { Vex128, XS, Ib } },
d5d7db8e 7617 { "(bad)", { XX } },
c0f3af97
L		 7618 },
7619
7620 /* VEX_LEN_73_R_6_P_2 */
7621 {
7622 { "vpsllq", { Vex128, XS, Ib } },
d5d7db8e 7623 { "(bad)", { XX } },
c0f3af97
L		 7624 },
7625
7626 /* VEX_LEN_73_R_7_P_2 */
7627 {
7628 { "vpslldq", { Vex128, XS, Ib } },
d5d7db8e 7629 { "(bad)", { XX } },
c0f3af97
L		 7630 },
7631
7632 /* VEX_LEN_74_P_2 */
7633 {
7634 { "vpcmpeqb", { XM, Vex128, EXx } },
d5d7db8e 7635 { "(bad)", { XX } },
c0f3af97
L		 7636 },
7637
7638 /* VEX_LEN_75_P_2 */
7639 {
7640 { "vpcmpeqw", { XM, Vex128, EXx } },
d5d7db8e 7641 { "(bad)", { XX } },
c0f3af97
L		 7642 },
7643
7644 /* VEX_LEN_76_P_2 */
7645 {
7646 { "vpcmpeqd", { XM, Vex128, EXx } },
d5d7db8e 7647 { "(bad)", { XX } },
c0f3af97
L		 7648 },
7649
7650 /* VEX_LEN_7E_P_1 */
7651 {
7652 { "vmovq", { XM, EXq } },
d5d7db8e 7653 { "(bad)", { XX } },
c0f3af97
L		 7654 },
7655
7656 /* VEX_LEN_7E_P_2 */
7657 {
7658 { "vmovK", { Edq, XM } },
d5d7db8e 7659 { "(bad)", { XX } },
c0f3af97
L		 7660 },
7661
9daa0d29 7662 /* VEX_LEN_AE_R_2_M_0 */
c0f3af97
L		 7663 {
7664 { "vldmxcsr", { Md } },
d5d7db8e 7665 { "(bad)", { XX } },
c0f3af97
L		 7666 },
7667
9daa0d29 7668 /* VEX_LEN_AE_R_3_M_0 */
c0f3af97
L		 7669 {
7670 { "vstmxcsr", { Md } },
d5d7db8e 7671 { "(bad)", { XX } },
c0f3af97
L		 7672 },
7673
7674 /* VEX_LEN_C2_P_1 */
7675 {
7676 { "vcmpss", { XM, Vex128, EXd, VCMP } },
d5d7db8e 7677 { "(bad)", { XX } },
c0f3af97
L		 7678 },
7679
7680 /* VEX_LEN_C2_P_3 */
7681 {
7682 { "vcmpsd", { XM, Vex128, EXq, VCMP } },
d5d7db8e 7683 { "(bad)", { XX } },
c0f3af97
L		 7684 },
7685
7686 /* VEX_LEN_C4_P_2 */
7687 {
7688 { "vpinsrw", { XM, Vex128, Edqw, Ib } },
d5d7db8e 7689 { "(bad)", { XX } },
c0f3af97
L		 7690 },
7691
7692 /* VEX_LEN_C5_P_2 */
7693 {
7694 { "vpextrw", { Gdq, XS, Ib } },
d5d7db8e 7695 { "(bad)", { XX } },
c0f3af97
L		 7696 },
7697
7698 /* VEX_LEN_D1_P_2 */
7699 {
7700 { "vpsrlw", { XM, Vex128, EXx } },
d5d7db8e 7701 { "(bad)", { XX } },
c0f3af97
L		 7702 },
7703
7704 /* VEX_LEN_D2_P_2 */
7705 {
7706 { "vpsrld", { XM, Vex128, EXx } },
d5d7db8e 7707 { "(bad)", { XX } },
c0f3af97
L		 7708 },
7709
7710 /* VEX_LEN_D3_P_2 */
7711 {
7712 { "vpsrlq", { XM, Vex128, EXx } },
d5d7db8e 7713 { "(bad)", { XX } },
c0f3af97
L		 7714 },
7715
7716 /* VEX_LEN_D4_P_2 */
7717 {
7718 { "vpaddq", { XM, Vex128, EXx } },
d5d7db8e 7719 { "(bad)", { XX } },
c0f3af97
L		 7720 },
7721
7722 /* VEX_LEN_D5_P_2 */
7723 {
7724 { "vpmullw", { XM, Vex128, EXx } },
d5d7db8e 7725 { "(bad)", { XX } },
c0f3af97
L		 7726 },
7727
7728 /* VEX_LEN_D6_P_2 */
7729 {
b6169b20 7730 { "vmovq", { EXqS, XM } },
d5d7db8e 7731 { "(bad)", { XX } },
c0f3af97
L		 7732 },
7733
7734 /* VEX_LEN_D7_P_2_M_1 */
7735 {
7736 { "vpmovmskb", { Gdq, XS } },
d5d7db8e 7737 { "(bad)", { XX } },
c0f3af97
L		 7738 },
7739
7740 /* VEX_LEN_D8_P_2 */
7741 {
7742 { "vpsubusb", { XM, Vex128, EXx } },
d5d7db8e 7743 { "(bad)", { XX } },
c0f3af97
L		 7744 },
7745
7746 /* VEX_LEN_D9_P_2 */
7747 {
7748 { "vpsubusw", { XM, Vex128, EXx } },
d5d7db8e 7749 { "(bad)", { XX } },
c0f3af97
L		 7750 },
7751
7752 /* VEX_LEN_DA_P_2 */
7753 {
7754 { "vpminub", { XM, Vex128, EXx } },
d5d7db8e 7755 { "(bad)", { XX } },
c0f3af97
L		 7756 },
7757
7758 /* VEX_LEN_DB_P_2 */
7759 {
7760 { "vpand", { XM, Vex128, EXx } },
d5d7db8e 7761 { "(bad)", { XX } },
c0f3af97
L		 7762 },
7763
7764 /* VEX_LEN_DC_P_2 */
7765 {
7766 { "vpaddusb", { XM, Vex128, EXx } },
d5d7db8e 7767 { "(bad)", { XX } },
c0f3af97
L		 7768 },
7769
7770 /* VEX_LEN_DD_P_2 */
7771 {
7772 { "vpaddusw", { XM, Vex128, EXx } },
d5d7db8e 7773 { "(bad)", { XX } },
c0f3af97
L		 7774 },
7775
7776 /* VEX_LEN_DE_P_2 */
7777 {
7778 { "vpmaxub", { XM, Vex128, EXx } },
d5d7db8e 7779 { "(bad)", { XX } },
c0f3af97
L		 7780 },
7781
7782 /* VEX_LEN_DF_P_2 */
7783 {
7784 { "vpandn", { XM, Vex128, EXx } },
d5d7db8e 7785 { "(bad)", { XX } },
c0f3af97
L		 7786 },
7787
7788 /* VEX_LEN_E0_P_2 */
7789 {
7790 { "vpavgb", { XM, Vex128, EXx } },
d5d7db8e 7791 { "(bad)", { XX } },
c0f3af97
L		 7792 },
7793
7794 /* VEX_LEN_E1_P_2 */
7795 {
7796 { "vpsraw", { XM, Vex128, EXx } },
d5d7db8e 7797 { "(bad)", { XX } },
c0f3af97
L		 7798 },
7799
7800 /* VEX_LEN_E2_P_2 */
7801 {
7802 { "vpsrad", { XM, Vex128, EXx } },
d5d7db8e 7803 { "(bad)", { XX } },
c0f3af97
L		 7804 },
7805
7806 /* VEX_LEN_E3_P_2 */
7807 {
7808 { "vpavgw", { XM, Vex128, EXx } },
d5d7db8e 7809 { "(bad)", { XX } },
c0f3af97
L		 7810 },
7811
7812 /* VEX_LEN_E4_P_2 */
7813 {
7814 { "vpmulhuw", { XM, Vex128, EXx } },
d5d7db8e 7815 { "(bad)", { XX } },
c0f3af97
L		 7816 },
7817
7818 /* VEX_LEN_E5_P_2 */
7819 {
7820 { "vpmulhw", { XM, Vex128, EXx } },
d5d7db8e 7821 { "(bad)", { XX } },
c0f3af97
L		 7822 },
7823
c0f3af97
L		 7824 /* VEX_LEN_E8_P_2 */
7825 {
7826 { "vpsubsb", { XM, Vex128, EXx } },
d5d7db8e 7827 { "(bad)", { XX } },
c0f3af97
L		 7828 },
7829
7830 /* VEX_LEN_E9_P_2 */
7831 {
7832 { "vpsubsw", { XM, Vex128, EXx } },
d5d7db8e 7833 { "(bad)", { XX } },
c0f3af97
L		 7834 },
7835
7836 /* VEX_LEN_EA_P_2 */
7837 {
7838 { "vpminsw", { XM, Vex128, EXx } },
d5d7db8e 7839 { "(bad)", { XX } },
c0f3af97
L		 7840 },
7841
7842 /* VEX_LEN_EB_P_2 */
7843 {
7844 { "vpor", { XM, Vex128, EXx } },
d5d7db8e 7845 { "(bad)", { XX } },
c0f3af97
L		 7846 },
7847
7848 /* VEX_LEN_EC_P_2 */
7849 {
7850 { "vpaddsb", { XM, Vex128, EXx } },
d5d7db8e 7851 { "(bad)", { XX } },
c0f3af97
L		 7852 },
7853
7854 /* VEX_LEN_ED_P_2 */
7855 {
7856 { "vpaddsw", { XM, Vex128, EXx } },
d5d7db8e 7857 { "(bad)", { XX } },
c0f3af97
L		 7858 },
7859
7860 /* VEX_LEN_EE_P_2 */
7861 {
7862 { "vpmaxsw", { XM, Vex128, EXx } },
d5d7db8e 7863 { "(bad)", { XX } },
c0f3af97
L		 7864 },
7865
7866 /* VEX_LEN_EF_P_2 */
7867 {
7868 { "vpxor", { XM, Vex128, EXx } },
d5d7db8e 7869 { "(bad)", { XX } },
c0f3af97
L		 7870 },
7871
7872 /* VEX_LEN_F1_P_2 */
7873 {
7874 { "vpsllw", { XM, Vex128, EXx } },
d5d7db8e 7875 { "(bad)", { XX } },
c0f3af97
L		 7876 },
7877
7878 /* VEX_LEN_F2_P_2 */
7879 {
7880 { "vpslld", { XM, Vex128, EXx } },
d5d7db8e 7881 { "(bad)", { XX } },
c0f3af97
L		 7882 },
7883
7884 /* VEX_LEN_F3_P_2 */
7885 {
7886 { "vpsllq", { XM, Vex128, EXx } },
d5d7db8e 7887 { "(bad)", { XX } },
c0f3af97
L		 7888 },
7889
7890 /* VEX_LEN_F4_P_2 */
7891 {
7892 { "vpmuludq", { XM, Vex128, EXx } },
d5d7db8e 7893 { "(bad)", { XX } },
c0f3af97
L		 7894 },
7895
7896 /* VEX_LEN_F5_P_2 */
7897 {
7898 { "vpmaddwd", { XM, Vex128, EXx } },
d5d7db8e 7899 { "(bad)", { XX } },
c0f3af97
L		 7900 },
7901
7902 /* VEX_LEN_F6_P_2 */
7903 {
7904 { "vpsadbw", { XM, Vex128, EXx } },
d5d7db8e 7905 { "(bad)", { XX } },
c0f3af97
L		 7906 },
7907
7908 /* VEX_LEN_F7_P_2 */
7909 {
7910 { "vmaskmovdqu", { XM, XS } },
d5d7db8e 7911 { "(bad)", { XX } },
c0f3af97
L		 7912 },
7913
7914 /* VEX_LEN_F8_P_2 */
7915 {
7916 { "vpsubb", { XM, Vex128, EXx } },
d5d7db8e 7917 { "(bad)", { XX } },
c0f3af97
L		 7918 },
7919
7920 /* VEX_LEN_F9_P_2 */
7921 {
7922 { "vpsubw", { XM, Vex128, EXx } },
d5d7db8e 7923 { "(bad)", { XX } },
c0f3af97
L		 7924 },
7925
7926 /* VEX_LEN_FA_P_2 */
7927 {
7928 { "vpsubd", { XM, Vex128, EXx } },
d5d7db8e 7929 { "(bad)", { XX } },
c0f3af97
L		 7930 },
7931
7932 /* VEX_LEN_FB_P_2 */
7933 {
7934 { "vpsubq", { XM, Vex128, EXx } },
d5d7db8e 7935 { "(bad)", { XX } },
c0f3af97
L		 7936 },
7937
7938 /* VEX_LEN_FC_P_2 */
7939 {
7940 { "vpaddb", { XM, Vex128, EXx } },
d5d7db8e 7941 { "(bad)", { XX } },
c0f3af97
L		 7942 },
7943
7944 /* VEX_LEN_FD_P_2 */
7945 {
7946 { "vpaddw", { XM, Vex128, EXx } },
d5d7db8e 7947 { "(bad)", { XX } },
c0f3af97
L		 7948 },
7949
7950 /* VEX_LEN_FE_P_2 */
7951 {
7952 { "vpaddd", { XM, Vex128, EXx } },
d5d7db8e 7953 { "(bad)", { XX } },
c0f3af97
L		 7954 },
7955
7956 /* VEX_LEN_3800_P_2 */
7957 {
7958 { "vpshufb", { XM, Vex128, EXx } },
d5d7db8e 7959 { "(bad)", { XX } },
c0f3af97
L		 7960 },
7961
7962 /* VEX_LEN_3801_P_2 */
7963 {
7964 { "vphaddw", { XM, Vex128, EXx } },
d5d7db8e 7965 { "(bad)", { XX } },
c0f3af97
L		 7966 },
7967
7968 /* VEX_LEN_3802_P_2 */
7969 {
7970 { "vphaddd", { XM, Vex128, EXx } },
d5d7db8e 7971 { "(bad)", { XX } },
c0f3af97
L		 7972 },
7973
7974 /* VEX_LEN_3803_P_2 */
7975 {
7976 { "vphaddsw", { XM, Vex128, EXx } },
d5d7db8e 7977 { "(bad)", { XX } },
c0f3af97
L		 7978 },
7979
7980 /* VEX_LEN_3804_P_2 */
7981 {
7982 { "vpmaddubsw", { XM, Vex128, EXx } },
d5d7db8e 7983 { "(bad)", { XX } },
c0f3af97
L		 7984 },
7985
7986 /* VEX_LEN_3805_P_2 */
7987 {
7988 { "vphsubw", { XM, Vex128, EXx } },
d5d7db8e 7989 { "(bad)", { XX } },
c0f3af97
L		 7990 },
7991
7992 /* VEX_LEN_3806_P_2 */
7993 {
7994 { "vphsubd", { XM, Vex128, EXx } },
d5d7db8e 7995 { "(bad)", { XX } },
c0f3af97
L		 7996 },
7997
7998 /* VEX_LEN_3807_P_2 */
7999 {
8000 { "vphsubsw", { XM, Vex128, EXx } },
d5d7db8e 8001 { "(bad)", { XX } },
c0f3af97
L		 8002 },
8003
8004 /* VEX_LEN_3808_P_2 */
8005 {
8006 { "vpsignb", { XM, Vex128, EXx } },
d5d7db8e 8007 { "(bad)", { XX } },
c0f3af97
L		 8008 },
8009
8010 /* VEX_LEN_3809_P_2 */
8011 {
8012 { "vpsignw", { XM, Vex128, EXx } },
d5d7db8e 8013 { "(bad)", { XX } },
c0f3af97
L		 8014 },
8015
8016 /* VEX_LEN_380A_P_2 */
8017 {
8018 { "vpsignd", { XM, Vex128, EXx } },
d5d7db8e 8019 { "(bad)", { XX } },
c0f3af97
L		 8020 },
8021
8022 /* VEX_LEN_380B_P_2 */
8023 {
8024 { "vpmulhrsw", { XM, Vex128, EXx } },
d5d7db8e 8025 { "(bad)", { XX } },
c0f3af97
L		 8026 },
8027
8028 /* VEX_LEN_3819_P_2_M_0 */
8029 {
d5d7db8e 8030 { "(bad)", { XX } },
c0f3af97
L		 8031 { "vbroadcastsd", { XM, Mq } },
8032 },
8033
8034 /* VEX_LEN_381A_P_2_M_0 */
8035 {
d5d7db8e 8036 { "(bad)", { XX } },
c0f3af97
L		 8037 { "vbroadcastf128", { XM, Mxmm } },
8038 },
8039
8040 /* VEX_LEN_381C_P_2 */
8041 {
8042 { "vpabsb", { XM, EXx } },
d5d7db8e 8043 { "(bad)", { XX } },
c0f3af97
L		 8044 },
8045
8046 /* VEX_LEN_381D_P_2 */
8047 {
8048 { "vpabsw", { XM, EXx } },
d5d7db8e 8049 { "(bad)", { XX } },
c0f3af97
L		 8050 },
8051
8052 /* VEX_LEN_381E_P_2 */
8053 {
8054 { "vpabsd", { XM, EXx } },
d5d7db8e 8055 { "(bad)", { XX } },
c0f3af97
L		 8056 },
8057
8058 /* VEX_LEN_3820_P_2 */
8059 {
8060 { "vpmovsxbw", { XM, EXq } },
d5d7db8e 8061 { "(bad)", { XX } },
c0f3af97
L		 8062 },
8063
8064 /* VEX_LEN_3821_P_2 */
8065 {
8066 { "vpmovsxbd", { XM, EXd } },
d5d7db8e 8067 { "(bad)", { XX } },
c0f3af97
L		 8068 },
8069
8070 /* VEX_LEN_3822_P_2 */
8071 {
8072 { "vpmovsxbq", { XM, EXw } },
d5d7db8e 8073 { "(bad)", { XX } },
c0f3af97
L		 8074 },
8075
8076 /* VEX_LEN_3823_P_2 */
8077 {
8078 { "vpmovsxwd", { XM, EXq } },
d5d7db8e 8079 { "(bad)", { XX } },
c0f3af97
L		 8080 },
8081
8082 /* VEX_LEN_3824_P_2 */
8083 {
8084 { "vpmovsxwq", { XM, EXd } },
d5d7db8e 8085 { "(bad)", { XX } },
c0f3af97
L		 8086 },
8087
8088 /* VEX_LEN_3825_P_2 */
8089 {
8090 { "vpmovsxdq", { XM, EXq } },
d5d7db8e 8091 { "(bad)", { XX } },
c0f3af97
L		 8092 },
8093
8094 /* VEX_LEN_3828_P_2 */
8095 {
8096 { "vpmuldq", { XM, Vex128, EXx } },
d5d7db8e 8097 { "(bad)", { XX } },
c0f3af97
L		 8098 },
8099
8100 /* VEX_LEN_3829_P_2 */
8101 {
8102 { "vpcmpeqq", { XM, Vex128, EXx } },
d5d7db8e 8103 { "(bad)", { XX } },
c0f3af97
L		 8104 },
8105
8106 /* VEX_LEN_382A_P_2_M_0 */
8107 {
8108 { "vmovntdqa", { XM, Mx } },
d5d7db8e 8109 { "(bad)", { XX } },
c0f3af97
L		 8110 },
8111
8112 /* VEX_LEN_382B_P_2 */
8113 {
8114 { "vpackusdw", { XM, Vex128, EXx } },
d5d7db8e 8115 { "(bad)", { XX } },
c0f3af97
L		 8116 },
8117
8118 /* VEX_LEN_3830_P_2 */
8119 {
8120 { "vpmovzxbw", { XM, EXq } },
d5d7db8e 8121 { "(bad)", { XX } },
c0f3af97
L		 8122 },
8123
8124 /* VEX_LEN_3831_P_2 */
8125 {
8126 { "vpmovzxbd", { XM, EXd } },
d5d7db8e 8127 { "(bad)", { XX } },
c0f3af97
L		 8128 },
8129
8130 /* VEX_LEN_3832_P_2 */
8131 {
8132 { "vpmovzxbq", { XM, EXw } },
d5d7db8e 8133 { "(bad)", { XX } },
c0f3af97
L		 8134 },
8135
8136 /* VEX_LEN_3833_P_2 */
8137 {
8138 { "vpmovzxwd", { XM, EXq } },
d5d7db8e 8139 { "(bad)", { XX } },
c0f3af97
L		 8140 },
8141
8142 /* VEX_LEN_3834_P_2 */
8143 {
8144 { "vpmovzxwq", { XM, EXd } },
d5d7db8e 8145 { "(bad)", { XX } },
c0f3af97
L		 8146 },
8147
8148 /* VEX_LEN_3835_P_2 */
8149 {
8150 { "vpmovzxdq", { XM, EXq } },
d5d7db8e 8151 { "(bad)", { XX } },
c0f3af97
L		 8152 },
8153
8154 /* VEX_LEN_3837_P_2 */
8155 {
8156 { "vpcmpgtq", { XM, Vex128, EXx } },
d5d7db8e 8157 { "(bad)", { XX } },
c0f3af97
L		 8158 },
8159
8160 /* VEX_LEN_3838_P_2 */
8161 {
8162 { "vpminsb", { XM, Vex128, EXx } },
d5d7db8e 8163 { "(bad)", { XX } },
c0f3af97
L		 8164 },
8165
8166 /* VEX_LEN_3839_P_2 */
8167 {
8168 { "vpminsd", { XM, Vex128, EXx } },
d5d7db8e 8169 { "(bad)", { XX } },
c0f3af97
L		 8170 },
8171
8172 /* VEX_LEN_383A_P_2 */
8173 {
8174 { "vpminuw", { XM, Vex128, EXx } },
d5d7db8e 8175 { "(bad)", { XX } },
c0f3af97
L		 8176 },
8177
8178 /* VEX_LEN_383B_P_2 */
8179 {
8180 { "vpminud", { XM, Vex128, EXx } },
d5d7db8e 8181 { "(bad)", { XX } },
c0f3af97
L		 8182 },
8183
8184 /* VEX_LEN_383C_P_2 */
8185 {
8186 { "vpmaxsb", { XM, Vex128, EXx } },
d5d7db8e 8187 { "(bad)", { XX } },
c0f3af97
L		 8188 },
8189
8190 /* VEX_LEN_383D_P_2 */
8191 {
8192 { "vpmaxsd", { XM, Vex128, EXx } },
d5d7db8e 8193 { "(bad)", { XX } },
c0f3af97
L		 8194 },
8195
8196 /* VEX_LEN_383E_P_2 */
8197 {
8198 { "vpmaxuw", { XM, Vex128, EXx } },
d5d7db8e 8199 { "(bad)", { XX } },
c0f3af97
L		 8200 },
8201
8202 /* VEX_LEN_383F_P_2 */
8203 {
8204 { "vpmaxud", { XM, Vex128, EXx } },
d5d7db8e 8205 { "(bad)", { XX } },
c0f3af97
L		 8206 },
8207
8208 /* VEX_LEN_3840_P_2 */
8209 {
8210 { "vpmulld", { XM, Vex128, EXx } },
d5d7db8e 8211 { "(bad)", { XX } },
c0f3af97
L		 8212 },
8213
8214 /* VEX_LEN_3841_P_2 */
8215 {
8216 { "vphminposuw", { XM, EXx } },
d5d7db8e 8217 { "(bad)", { XX } },
c0f3af97
L		 8218 },
8219
a5ff0eb2
L		 8220 /* VEX_LEN_38DB_P_2 */
8221 {
8222 { "vaesimc", { XM, EXx } },
8223 { "(bad)", { XX } },
8224 },
8225
8226 /* VEX_LEN_38DC_P_2 */
8227 {
8228 { "vaesenc", { XM, Vex128, EXx } },
8229 { "(bad)", { XX } },
8230 },
8231
8232 /* VEX_LEN_38DD_P_2 */
8233 {
8234 { "vaesenclast", { XM, Vex128, EXx } },
8235 { "(bad)", { XX } },
8236 },
8237
8238 /* VEX_LEN_38DE_P_2 */
8239 {
8240 { "vaesdec", { XM, Vex128, EXx } },
8241 { "(bad)", { XX } },
8242 },
8243
8244 /* VEX_LEN_38DF_P_2 */
8245 {
8246 { "vaesdeclast", { XM, Vex128, EXx } },
8247 { "(bad)", { XX } },
8248 },
8249
c0f3af97
L		 8250 /* VEX_LEN_3A06_P_2 */
8251 {
d5d7db8e 8252 { "(bad)", { XX } },
c0f3af97
L		 8253 { "vperm2f128", { XM, Vex256, EXx, Ib } },
8254 },
8255
8256 /* VEX_LEN_3A0A_P_2 */
8257 {
8258 { "vroundss", { XM, Vex128, EXd, Ib } },
d5d7db8e 8259 { "(bad)", { XX } },
c0f3af97
L		 8260 },
8261
8262 /* VEX_LEN_3A0B_P_2 */
8263 {
8264 { "vroundsd", { XM, Vex128, EXq, Ib } },
d5d7db8e 8265 { "(bad)", { XX } },
c0f3af97
L		 8266 },
8267
8268 /* VEX_LEN_3A0E_P_2 */
8269 {
8270 { "vpblendw", { XM, Vex128, EXx, Ib } },
d5d7db8e 8271 { "(bad)", { XX } },
c0f3af97
L		 8272 },
8273
8274 /* VEX_LEN_3A0F_P_2 */
8275 {
8276 { "vpalignr", { XM, Vex128, EXx, Ib } },
d5d7db8e 8277 { "(bad)", { XX } },
c0f3af97
L		 8278 },
8279
8280 /* VEX_LEN_3A14_P_2 */
8281 {
8282 { "vpextrb", { Edqb, XM, Ib } },
d5d7db8e 8283 { "(bad)", { XX } },
c0f3af97
L		 8284 },
8285
8286 /* VEX_LEN_3A15_P_2 */
8287 {
8288 { "vpextrw", { Edqw, XM, Ib } },
d5d7db8e 8289 { "(bad)", { XX } },
c0f3af97
L		 8290 },
8291
8292 /* VEX_LEN_3A16_P_2 */
8293 {
8294 { "vpextrK", { Edq, XM, Ib } },
d5d7db8e 8295 { "(bad)", { XX } },
c0f3af97
L		 8296 },
8297
8298 /* VEX_LEN_3A17_P_2 */
8299 {
8300 { "vextractps", { Edqd, XM, Ib } },
d5d7db8e 8301 { "(bad)", { XX } },
c0f3af97
L		 8302 },
8303
8304 /* VEX_LEN_3A18_P_2 */
8305 {
d5d7db8e 8306 { "(bad)", { XX } },
c0f3af97
L		 8307 { "vinsertf128", { XM, Vex256, EXxmm, Ib } },
8308 },
8309
8310 /* VEX_LEN_3A19_P_2 */
8311 {
d5d7db8e 8312 { "(bad)", { XX } },
c0f3af97
L		 8313 { "vextractf128", { EXxmm, XM, Ib } },
8314 },
8315
8316 /* VEX_LEN_3A20_P_2 */
8317 {
8318 { "vpinsrb", { XM, Vex128, Edqb, Ib } },
d5d7db8e 8319 { "(bad)", { XX } },
c0f3af97
L		 8320 },
8321
8322 /* VEX_LEN_3A21_P_2 */
8323 {
8324 { "vinsertps", { XM, Vex128, EXd, Ib } },
d5d7db8e 8325 { "(bad)", { XX } },
c0f3af97
L		 8326 },
8327
8328 /* VEX_LEN_3A22_P_2 */
8329 {
8330 { "vpinsrK", { XM, Vex128, Edq, Ib } },
d5d7db8e 8331 { "(bad)", { XX } },
c0f3af97
L		 8332 },
8333
8334 /* VEX_LEN_3A41_P_2 */
8335 {
8336 { "vdppd", { XM, Vex128, EXx, Ib } },
d5d7db8e 8337 { "(bad)", { XX } },
c0f3af97
L		 8338 },
8339
8340 /* VEX_LEN_3A42_P_2 */
8341 {
8342 { "vmpsadbw", { XM, Vex128, EXx, Ib } },
d5d7db8e 8343 { "(bad)", { XX } },
c0f3af97
L		 8344 },
8345
ce2f5b3c
L		 8346 /* VEX_LEN_3A44_P_2 */
8347 {
8348 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } },
8349 { "(bad)", { XX } },
8350 },
8351
c0f3af97
L		 8352 /* VEX_LEN_3A4C_P_2 */
8353 {
8354 { "vpblendvb", { XM, Vex128, EXx, XMVexI4 } },
d5d7db8e 8355 { "(bad)", { XX } },
c0f3af97
L		 8356 },
8357
8358 /* VEX_LEN_3A60_P_2 */
8359 {
8360 { "vpcmpestrm", { XM, EXx, Ib } },
d5d7db8e 8361 { "(bad)", { XX } },
c0f3af97
L		 8362 },
8363
8364 /* VEX_LEN_3A61_P_2 */
8365 {
8366 { "vpcmpestri", { XM, EXx, Ib } },
d5d7db8e 8367 { "(bad)", { XX } },
c0f3af97
L		 8368 },
8369
8370 /* VEX_LEN_3A62_P_2 */
8371 {
8372 { "vpcmpistrm", { XM, EXx, Ib } },
d5d7db8e 8373 { "(bad)", { XX } },
c0f3af97
L		 8374 },
8375
8376 /* VEX_LEN_3A63_P_2 */
8377 {
8378 { "vpcmpistri", { XM, EXx, Ib } },
d5d7db8e 8379 { "(bad)", { XX } },
c0f3af97
L		 8380 },
8381
922d8de8
DR		 8382 /* VEX_LEN_3A6A_P_2 */
8383 {
206c2556 8384 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
922d8de8
DR		 8385 { "(bad)", { XX } },
8386 },
8387
8388 /* VEX_LEN_3A6B_P_2 */
8389 {
206c2556 8390 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
922d8de8
DR		 8391 { "(bad)", { XX } },
8392 },
8393
8394 /* VEX_LEN_3A6E_P_2 */
8395 {
206c2556 8396 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
922d8de8
DR		 8397 { "(bad)", { XX } },
8398 },
8399
8400 /* VEX_LEN_3A6F_P_2 */
8401 {
206c2556 8402 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
922d8de8
DR		 8403 { "(bad)", { XX } },
8404 },
8405
8406 /* VEX_LEN_3A7A_P_2 */
8407 {
206c2556 8408 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
922d8de8
DR		 8409 { "(bad)", { XX } },
8410 },
8411
8412 /* VEX_LEN_3A7B_P_2 */
8413 {
206c2556 8414 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
922d8de8
DR		 8415 { "(bad)", { XX } },
8416 },
8417
8418 /* VEX_LEN_3A7E_P_2 */
8419 {
206c2556 8420 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
922d8de8
DR		 8421 { "(bad)", { XX } },
8422 },
8423
8424 /* VEX_LEN_3A7F_P_2 */
8425 {
206c2556 8426 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
922d8de8
DR		 8427 { "(bad)", { XX } },
8428 },
8429
a5ff0eb2
L		 8430 /* VEX_LEN_3ADF_P_2 */
8431 {
8432 { "vaeskeygenassist", { XM, EXx, Ib } },
8433 { "(bad)", { XX } },
8434 },
331d2d0d
L		 8435};
8436
1ceb70f8 8437static const struct dis386 mod_table[][2] = {
b844680a 8438 {
1ceb70f8 8439 /* MOD_8D */
d8faab4e
L		 8440 { "leaS", { Gv, M } },
8441 { "(bad)", { XX } },
8442 },
8443 {
92fddf8e
L		 8444 /* MOD_0F01_REG_0 */
8445 { X86_64_TABLE (X86_64_0F01_REG_0) },
8446 { RM_TABLE (RM_0F01_REG_0) },
d8faab4e
L		 8447 },
8448 {
92fddf8e
L		 8449 /* MOD_0F01_REG_1 */
8450 { X86_64_TABLE (X86_64_0F01_REG_1) },
8451 { RM_TABLE (RM_0F01_REG_1) },
d8faab4e
L		 8452 },
8453 {
92fddf8e
L		 8454 /* MOD_0F01_REG_2 */
8455 { X86_64_TABLE (X86_64_0F01_REG_2) },
475a2301 8456 { RM_TABLE (RM_0F01_REG_2) },
d8faab4e
L		 8457 },
8458 {
92fddf8e
L		 8459 /* MOD_0F01_REG_3 */
8460 { X86_64_TABLE (X86_64_0F01_REG_3) },
8461 { RM_TABLE (RM_0F01_REG_3) },
d8faab4e
L		 8462 },
8463 {
92fddf8e
L		 8464 /* MOD_0F01_REG_7 */
8465 { "invlpg", { Mb } },
8466 { RM_TABLE (RM_0F01_REG_7) },
b844680a
L		 8467 },
8468 {
92fddf8e
L		 8469 /* MOD_0F12_PREFIX_0 */
8470 { "movlps", { XM, EXq } },
8471 { "movhlps", { XM, EXq } },
b844680a
L		 8472 },
8473 {
92fddf8e
L		 8474 /* MOD_0F13 */
8475 { "movlpX", { EXq, XM } },
d8faab4e
L		 8476 { "(bad)", { XX } },
8477 },
8478 {
92fddf8e
L		 8479 /* MOD_0F16_PREFIX_0 */
8480 { "movhps", { XM, EXq } },
8481 { "movlhps", { XM, EXq } },
b844680a
L		 8482 },
8483 {
92fddf8e
L		 8484 /* MOD_0F17 */
8485 { "movhpX", { EXq, XM } },
b844680a
L		 8486 { "(bad)", { XX } },
8487 },
8488 {
92fddf8e
L		 8489 /* MOD_0F18_REG_0 */
8490 { "prefetchnta", { Mb } },
b844680a 8491 { "(bad)", { XX } },
b844680a
L		 8492 },
8493 {
92fddf8e
L		 8494 /* MOD_0F18_REG_1 */
8495 { "prefetcht0", { Mb } },
8496 { "(bad)", { XX } },
b844680a
L		 8497 },
8498 {
92fddf8e
L		 8499 /* MOD_0F18_REG_2 */
8500 { "prefetcht1", { Mb } },
8501 { "(bad)", { XX } },
b844680a
L		 8502 },
8503 {
92fddf8e
L		 8504 /* MOD_0F18_REG_3 */
8505 { "prefetcht2", { Mb } },
b844680a 8506 { "(bad)", { XX } },
b844680a
L		 8507 },
8508 {
92fddf8e
L		 8509 /* MOD_0F20 */
8510 { "(bad)", { XX } },
8511 { "movZ", { Rm, Cm } },
b844680a
L		 8512 },
8513 {
92fddf8e
L		 8514 /* MOD_0F21 */
8515 { "(bad)", { XX } },
8516 { "movZ", { Rm, Dm } },
b844680a
L		 8517 },
8518 {
92fddf8e 8519 /* MOD_0F22 */
b844680a 8520 { "(bad)", { XX } },
92fddf8e 8521 { "movZ", { Cm, Rm } },
b844680a
L		 8522 },
8523 {
92fddf8e 8524 /* MOD_0F23 */
b844680a 8525 { "(bad)", { XX } },
92fddf8e 8526 { "movZ", { Dm, Rm } },
b844680a
L		 8527 },
8528 {
92fddf8e 8529 /* MOD_0F24 */
c1e679ec 8530 { "(bad)", { XX } },
92fddf8e 8531 { "movL", { Rd, Td } },
b844680a
L		 8532 },
8533 {
92fddf8e 8534 /* MOD_0F26 */
b844680a 8535 { "(bad)", { XX } },
92fddf8e 8536 { "movL", { Td, Rd } },
b844680a 8537 },
75c135a8
L		 8538 {
8539 /* MOD_0F2B_PREFIX_0 */
4ee52178 8540 {"movntps", { Mx, XM } },
75c135a8
L		 8541 { "(bad)", { XX } },
8542 },
8543 {
8544 /* MOD_0F2B_PREFIX_1 */
4ee52178 8545 {"movntss", { Md, XM } },
75c135a8
L		 8546 { "(bad)", { XX } },
8547 },
8548 {
8549 /* MOD_0F2B_PREFIX_2 */
4ee52178 8550 {"movntpd", { Mx, XM } },
75c135a8
L		 8551 { "(bad)", { XX } },
8552 },
8553 {
8554 /* MOD_0F2B_PREFIX_3 */
4ee52178 8555 {"movntsd", { Mq, XM } },
75c135a8
L		 8556 { "(bad)", { XX } },
8557 },
8558 {
8559 /* MOD_0F51 */
8560 { "(bad)", { XX } },
8561 { "movmskpX", { Gdq, XS } },
8562 },
b844680a 8563 {
1ceb70f8 8564 /* MOD_0F71_REG_2 */
b844680a 8565 { "(bad)", { XX } },
4e7d34a6 8566 { "psrlw", { MS, Ib } },
b844680a
L		 8567 },
8568 {
1ceb70f8 8569 /* MOD_0F71_REG_4 */
b844680a 8570 { "(bad)", { XX } },
4e7d34a6 8571 { "psraw", { MS, Ib } },
b844680a
L		 8572 },
8573 {
1ceb70f8 8574 /* MOD_0F71_REG_6 */
b844680a 8575 { "(bad)", { XX } },
4e7d34a6 8576 { "psllw", { MS, Ib } },
b844680a
L		 8577 },
8578 {
1ceb70f8 8579 /* MOD_0F72_REG_2 */
b844680a 8580 { "(bad)", { XX } },
4e7d34a6 8581 { "psrld", { MS, Ib } },
b844680a
L		 8582 },
8583 {
1ceb70f8 8584 /* MOD_0F72_REG_4 */
b844680a 8585 { "(bad)", { XX } },
4e7d34a6 8586 { "psrad", { MS, Ib } },
b844680a
L		 8587 },
8588 {
1ceb70f8 8589 /* MOD_0F72_REG_6 */
b844680a 8590 { "(bad)", { XX } },
4e7d34a6 8591 { "pslld", { MS, Ib } },
b844680a
L		 8592 },
8593 {
1ceb70f8 8594 /* MOD_0F73_REG_2 */
4e7d34a6
L		 8595 { "(bad)", { XX } },
8596 { "psrlq", { MS, Ib } },
b844680a
L		 8597 },
8598 {
1ceb70f8 8599 /* MOD_0F73_REG_3 */
b844680a 8600 { "(bad)", { XX } },
c0f3af97
L		 8601 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
8602 },
8603 {
8604 /* MOD_0F73_REG_6 */
8605 { "(bad)", { XX } },
8606 { "psllq", { MS, Ib } },
8607 },
8608 {
8609 /* MOD_0F73_REG_7 */
8610 { "(bad)", { XX } },
8611 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
8612 },
8613 {
8614 /* MOD_0FAE_REG_0 */
8615 { "fxsave", { M } },
8616 { "(bad)", { XX } },
8617 },
8618 {
8619 /* MOD_0FAE_REG_1 */
8620 { "fxrstor", { M } },
8621 { "(bad)", { XX } },
8622 },
8623 {
8624 /* MOD_0FAE_REG_2 */
8625 { "ldmxcsr", { Md } },
8626 { "(bad)", { XX } },
8627 },
8628 {
8629 /* MOD_0FAE_REG_3 */
8630 { "stmxcsr", { Md } },
8631 { "(bad)", { XX } },
8632 },
8633 {
8634 /* MOD_0FAE_REG_4 */
8635 { "xsave", { M } },
8636 { "(bad)", { XX } },
8637 },
8638 {
8639 /* MOD_0FAE_REG_5 */
8640 { "xrstor", { M } },
8641 { RM_TABLE (RM_0FAE_REG_5) },
8642 },
8643 {
8644 /* MOD_0FAE_REG_6 */
8645 { "xsaveopt", { M } },
8646 { RM_TABLE (RM_0FAE_REG_6) },
8647 },
8648 {
8649 /* MOD_0FAE_REG_7 */
8650 { "clflush", { Mb } },
8651 { RM_TABLE (RM_0FAE_REG_7) },
8652 },
8653 {
8654 /* MOD_0FB2 */
8655 { "lssS", { Gv, Mp } },
8656 { "(bad)", { XX } },
8657 },
8658 {
8659 /* MOD_0FB4 */
8660 { "lfsS", { Gv, Mp } },
8661 { "(bad)", { XX } },
8662 },
8663 {
8664 /* MOD_0FB5 */
8665 { "lgsS", { Gv, Mp } },
8666 { "(bad)", { XX } },
8667 },
8668 {
8669 /* MOD_0FC7_REG_6 */
8670 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
8671 { "(bad)", { XX } },
8672 },
8673 {
8674 /* MOD_0FC7_REG_7 */
8675 { "vmptrst", { Mq } },
8676 { "(bad)", { XX } },
8677 },
8678 {
8679 /* MOD_0FD7 */
8680 { "(bad)", { XX } },
8681 { "pmovmskb", { Gdq, MS } },
8682 },
8683 {
8684 /* MOD_0FE7_PREFIX_2 */
8685 { "movntdq", { Mx, XM } },
8686 { "(bad)", { XX } },
8687 },
8688 {
8689 /* MOD_0FF0_PREFIX_3 */
8690 { "lddqu", { XM, M } },
8691 { "(bad)", { XX } },
8692 },
8693 {
8694 /* MOD_0F382A_PREFIX_2 */
8695 { "movntdqa", { XM, Mx } },
8696 { "(bad)", { XX } },
8697 },
8698 {
8699 /* MOD_62_32BIT */
8700 { "bound{S|}", { Gv, Ma } },
8701 { "(bad)", { XX } },
8702 },
8703 {
8704 /* MOD_C4_32BIT */
8705 { "lesS", { Gv, Mp } },
8706 { VEX_C4_TABLE (VEX_0F) },
8707 },
8708 {
8709 /* MOD_C5_32BIT */
8710 { "ldsS", { Gv, Mp } },
8711 { VEX_C5_TABLE (VEX_0F) },
8712 },
8713 {
8714 /* MOD_VEX_12_PREFIX_0 */
8715 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
8716 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
8717 },
8718 {
8719 /* MOD_VEX_13 */
8720 { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
8721 { "(bad)", { XX } },
8722 },
8723 {
8724 /* MOD_VEX_16_PREFIX_0 */
8725 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
8726 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
8727 },
8728 {
8729 /* MOD_VEX_17 */
8730 { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
8731 { "(bad)", { XX } },
8732 },
8733 {
8734 /* MOD_VEX_2B */
168e3097 8735 { "vmovntpX", { Mx, XM } },
c0f3af97
L		 8736 { "(bad)", { XX } },
8737 },
8738 {
8739 /* MOD_VEX_51 */
8740 { "(bad)", { XX } },
8741 { "vmovmskpX", { Gdq, XS } },
8742 },
8743 {
8744 /* MOD_VEX_71_REG_2 */
8745 { "(bad)", { XX } },
8746 { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
b844680a
L		 8747 },
8748 {
c0f3af97 8749 /* MOD_VEX_71_REG_4 */
b844680a 8750 { "(bad)", { XX } },
c0f3af97 8751 { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
b844680a
L		 8752 },
8753 {
c0f3af97 8754 /* MOD_VEX_71_REG_6 */
b844680a 8755 { "(bad)", { XX } },
c0f3af97 8756 { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
b844680a
L		 8757 },
8758 {
c0f3af97 8759 /* MOD_VEX_72_REG_2 */
b844680a 8760 { "(bad)", { XX } },
c0f3af97 8761 { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
b844680a 8762 },
d8faab4e 8763 {
c0f3af97 8764 /* MOD_VEX_72_REG_4 */
d8faab4e 8765 { "(bad)", { XX } },
c0f3af97 8766 { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
d8faab4e
L		 8767 },
8768 {
c0f3af97 8769 /* MOD_VEX_72_REG_6 */
d8faab4e 8770 { "(bad)", { XX } },
c0f3af97 8771 { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
d8faab4e 8772 },
876d4bfa 8773 {
c0f3af97 8774 /* MOD_VEX_73_REG_2 */
876d4bfa 8775 { "(bad)", { XX } },
c0f3af97 8776 { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
876d4bfa
L		 8777 },
8778 {
c0f3af97 8779 /* MOD_VEX_73_REG_3 */
876d4bfa 8780 { "(bad)", { XX } },
c0f3af97 8781 { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
475a2301
L		 8782 },
8783 {
c0f3af97
L		 8784 /* MOD_VEX_73_REG_6 */
8785 { "(bad)", { XX } },
8786 { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
876d4bfa
L		 8787 },
8788 {
c0f3af97 8789 /* MOD_VEX_73_REG_7 */
4e7d34a6 8790 { "(bad)", { XX } },
c0f3af97 8791 { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
876d4bfa
L		 8792 },
8793 {
c0f3af97
L		 8794 /* MOD_VEX_AE_REG_2 */
8795 { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
8796 { "(bad)", { XX } },
876d4bfa 8797 },
bbedc832 8798 {
c0f3af97
L		 8799 /* MOD_VEX_AE_REG_3 */
8800 { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
4e7d34a6 8801 { "(bad)", { XX } },
bbedc832 8802 },
144c41d9 8803 {
c0f3af97 8804 /* MOD_VEX_D7_PREFIX_2 */
4e7d34a6 8805 { "(bad)", { XX } },
c0f3af97 8806 { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
144c41d9 8807 },
1afd85e3 8808 {
c0f3af97 8809 /* MOD_VEX_E7_PREFIX_2 */
168e3097 8810 { "vmovntdq", { Mx, XM } },
92fddf8e 8811 { "(bad)", { XX } },
1afd85e3
L		 8812 },
8813 {
c0f3af97
L		 8814 /* MOD_VEX_F0_PREFIX_3 */
8815 { "vlddqu", { XM, M } },
92fddf8e
L		 8816 { "(bad)", { XX } },
8817 },
8818 {
c0f3af97
L		 8819 /* MOD_VEX_3818_PREFIX_2 */
8820 { "vbroadcastss", { XM, Md } },
92fddf8e 8821 { "(bad)", { XX } },
1afd85e3 8822 },
75c135a8 8823 {
c0f3af97
L		 8824 /* MOD_VEX_3819_PREFIX_2 */
8825 { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
75c135a8 8826 { "(bad)", { XX } },
75c135a8
L		 8827 },
8828 {
c0f3af97
L		 8829 /* MOD_VEX_381A_PREFIX_2 */
8830 { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
75c135a8
L		 8831 { "(bad)", { XX } },
8832 },
1afd85e3 8833 {
c0f3af97
L		 8834 /* MOD_VEX_382A_PREFIX_2 */
8835 { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
1afd85e3 8836 { "(bad)", { XX } },
1afd85e3 8837 },
75c135a8 8838 {
c0f3af97
L		 8839 /* MOD_VEX_382C_PREFIX_2 */
8840 { "vmaskmovps", { XM, Vex, Mx } },
75c135a8
L		 8841 { "(bad)", { XX } },
8842 },
1afd85e3 8843 {
c0f3af97
L		 8844 /* MOD_VEX_382D_PREFIX_2 */
8845 { "vmaskmovpd", { XM, Vex, Mx } },
1afd85e3 8846 { "(bad)", { XX } },
1afd85e3
L		 8847 },
8848 {
c0f3af97
L		 8849 /* MOD_VEX_382E_PREFIX_2 */
8850 { "vmaskmovps", { Mx, Vex, XM } },
4e7d34a6 8851 { "(bad)", { XX } },
1afd85e3
L		 8852 },
8853 {
c0f3af97
L		 8854 /* MOD_VEX_382F_PREFIX_2 */
8855 { "vmaskmovpd", { Mx, Vex, XM } },
1afd85e3 8856 { "(bad)", { XX } },
1afd85e3 8857 },
b844680a
L		 8858};
8859
1ceb70f8 8860static const struct dis386 rm_table[][8] = {
b844680a 8861 {
1ceb70f8 8862 /* RM_0F01_REG_0 */
b844680a
L		 8863 { "(bad)", { XX } },
8864 { "vmcall", { Skip_MODRM } },
8865 { "vmlaunch", { Skip_MODRM } },
8866 { "vmresume", { Skip_MODRM } },
8867 { "vmxoff", { Skip_MODRM } },
8868 { "(bad)", { XX } },
8869 { "(bad)", { XX } },
8870 { "(bad)", { XX } },
8871 },
8872 {
1ceb70f8 8873 /* RM_0F01_REG_1 */
b844680a
L		 8874 { "monitor", { { OP_Monitor, 0 } } },
8875 { "mwait", { { OP_Mwait, 0 } } },
8876 { "(bad)", { XX } },
8877 { "(bad)", { XX } },
8878 { "(bad)", { XX } },
8879 { "(bad)", { XX } },
8880 { "(bad)", { XX } },
8881 { "(bad)", { XX } },
8882 },
475a2301
L		 8883 {
8884 /* RM_0F01_REG_2 */
8885 { "xgetbv", { Skip_MODRM } },
8886 { "xsetbv", { Skip_MODRM } },
8887 { "(bad)", { XX } },
8888 { "(bad)", { XX } },
8889 { "(bad)", { XX } },
8890 { "(bad)", { XX } },
8891 { "(bad)", { XX } },
8892 { "(bad)", { XX } },
8893 },
b844680a 8894 {
1ceb70f8 8895 /* RM_0F01_REG_3 */
4e7d34a6
L		 8896 { "vmrun", { Skip_MODRM } },
8897 { "vmmcall", { Skip_MODRM } },
8898 { "vmload", { Skip_MODRM } },
8899 { "vmsave", { Skip_MODRM } },
8900 { "stgi", { Skip_MODRM } },
8901 { "clgi", { Skip_MODRM } },
8902 { "skinit", { Skip_MODRM } },
8903 { "invlpga", { Skip_MODRM } },
8904 },
8905 {
1ceb70f8 8906 /* RM_0F01_REG_7 */
4e7d34a6
L		 8907 { "swapgs", { Skip_MODRM } },
8908 { "rdtscp", { Skip_MODRM } },
b844680a
L		 8909 { "(bad)", { XX } },
8910 { "(bad)", { XX } },
8911 { "(bad)", { XX } },
8912 { "(bad)", { XX } },
8913 { "(bad)", { XX } },
8914 { "(bad)", { XX } },
8915 },
8916 {
1ceb70f8 8917 /* RM_0FAE_REG_5 */
4e7d34a6 8918 { "lfence", { Skip_MODRM } },
b844680a
L		 8919 { "(bad)", { XX } },
8920 { "(bad)", { XX } },
8921 { "(bad)", { XX } },
8922 { "(bad)", { XX } },
8923 { "(bad)", { XX } },
8924 { "(bad)", { XX } },
8925 { "(bad)", { XX } },
8926 },
8927 {
1ceb70f8 8928 /* RM_0FAE_REG_6 */
4e7d34a6 8929 { "mfence", { Skip_MODRM } },
b844680a
L		 8930 { "(bad)", { XX } },
8931 { "(bad)", { XX } },
8932 { "(bad)", { XX } },
8933 { "(bad)", { XX } },
8934 { "(bad)", { XX } },
8935 { "(bad)", { XX } },
8936 { "(bad)", { XX } },
8937 },
bbedc832 8938 {
1ceb70f8 8939 /* RM_0FAE_REG_7 */
4e7d34a6
L		 8940 { "sfence", { Skip_MODRM } },
8941 { "(bad)", { XX } },
bbedc832
L		 8942 { "(bad)", { XX } },
8943 { "(bad)", { XX } },
8944 { "(bad)", { XX } },
8945 { "(bad)", { XX } },
8946 { "(bad)", { XX } },
8947 { "(bad)", { XX } },
144c41d9 8948 },
b844680a
L		 8949};
8950
c608c12e
AM		 8951#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8952
252b5132 8953static void
26ca5450 8954ckprefix (void)
252b5132 8955{
52b15da3
JH		 8956 int newrex;
8957 rex = 0;
c0f3af97
L		 8958 rex_original = 0;
8959 rex_ignored = 0;
252b5132 8960 prefixes = 0;
7d421014 8961 used_prefixes = 0;
52b15da3 8962 rex_used = 0;
252b5132
RH		 8963 while (1)
8964 {
8965 FETCH_DATA (the_info, codep + 1);
52b15da3 8966 newrex = 0;
252b5132
RH		 8967 switch (*codep)
8968 {
52b15da3
JH		 8969 /* REX prefixes family. */
8970 case 0x40:
8971 case 0x41:
8972 case 0x42:
8973 case 0x43:
8974 case 0x44:
8975 case 0x45:
8976 case 0x46:
8977 case 0x47:
8978 case 0x48:
8979 case 0x49:
8980 case 0x4a:
8981 case 0x4b:
8982 case 0x4c:
8983 case 0x4d:
8984 case 0x4e:
8985 case 0x4f:
cb712a9e 8986 if (address_mode == mode_64bit)
52b15da3
JH		 8987 newrex = *codep;
8988 else
8989 return;
8990 break;
252b5132
RH		 8991 case 0xf3:
8992 prefixes |= PREFIX_REPZ;
8993 break;
8994 case 0xf2:
8995 prefixes |= PREFIX_REPNZ;
8996 break;
8997 case 0xf0:
8998 prefixes |= PREFIX_LOCK;
8999 break;
9000 case 0x2e:
9001 prefixes |= PREFIX_CS;
9002 break;
9003 case 0x36:
9004 prefixes |= PREFIX_SS;
9005 break;
9006 case 0x3e:
9007 prefixes |= PREFIX_DS;
9008 break;
9009 case 0x26:
9010 prefixes |= PREFIX_ES;
9011 break;
9012 case 0x64:
9013 prefixes |= PREFIX_FS;
9014 break;
9015 case 0x65:
9016 prefixes |= PREFIX_GS;
9017 break;
9018 case 0x66:
9019 prefixes |= PREFIX_DATA;
9020 break;
9021 case 0x67:
9022 prefixes |= PREFIX_ADDR;
9023 break;
5076851f 9024 case FWAIT_OPCODE:
252b5132
RH		 9025 /* fwait is really an instruction. If there are prefixes
9026 before the fwait, they belong to the fwait, *not* to the
9027 following instruction. */
3e7d61b2 9028 if (prefixes || rex)
252b5132
RH		 9029 {
9030 prefixes |= PREFIX_FWAIT;
9031 codep++;
9032 return;
9033 }
9034 prefixes = PREFIX_FWAIT;
9035 break;
9036 default:
9037 return;
9038 }
52b15da3
JH		 9039 /* Rex is ignored when followed by another prefix. */
9040 if (rex)
9041 {
3e7d61b2
AM		 9042 rex_used = rex;
9043 return;
52b15da3
JH		 9044 }
9045 rex = newrex;
c0f3af97 9046 rex_original = rex;
252b5132
RH		 9047 codep++;
9048 }
9049}
9050
7d421014
ILT		 9051/* Return the name of the prefix byte PREF, or NULL if PREF is not a
9052 prefix byte. */
9053
9054static const char *
26ca5450 9055prefix_name (int pref, int sizeflag)
7d421014 9056{
0003779b
L		 9057 static const char *rexes [16] =
9058 {
9059 "rex", /* 0x40 */
9060 "rex.B", /* 0x41 */
9061 "rex.X", /* 0x42 */
9062 "rex.XB", /* 0x43 */
9063 "rex.R", /* 0x44 */
9064 "rex.RB", /* 0x45 */
9065 "rex.RX", /* 0x46 */
9066 "rex.RXB", /* 0x47 */
9067 "rex.W", /* 0x48 */
9068 "rex.WB", /* 0x49 */
9069 "rex.WX", /* 0x4a */
9070 "rex.WXB", /* 0x4b */
9071 "rex.WR", /* 0x4c */
9072 "rex.WRB", /* 0x4d */
9073 "rex.WRX", /* 0x4e */
9074 "rex.WRXB", /* 0x4f */
9075 };
9076
7d421014
ILT		 9077 switch (pref)
9078 {
52b15da3
JH		 9079 /* REX prefixes family. */
9080 case 0x40:
52b15da3 9081 case 0x41:
52b15da3 9082 case 0x42:
52b15da3 9083 case 0x43:
52b15da3 9084 case 0x44:
52b15da3 9085 case 0x45:
52b15da3 9086 case 0x46:
52b15da3 9087 case 0x47:
52b15da3 9088 case 0x48:
52b15da3 9089 case 0x49:
52b15da3 9090 case 0x4a:
52b15da3 9091 case 0x4b:
52b15da3 9092 case 0x4c:
52b15da3 9093 case 0x4d:
52b15da3 9094 case 0x4e:
52b15da3 9095 case 0x4f:
0003779b 9096 return rexes [pref - 0x40];
7d421014
ILT		 9097 case 0xf3:
9098 return "repz";
9099 case 0xf2:
9100 return "repnz";
9101 case 0xf0:
9102 return "lock";
9103 case 0x2e:
9104 return "cs";
9105 case 0x36:
9106 return "ss";
9107 case 0x3e:
9108 return "ds";
9109 case 0x26:
9110 return "es";
9111 case 0x64:
9112 return "fs";
9113 case 0x65:
9114 return "gs";
9115 case 0x66:
9116 return (sizeflag & DFLAG) ? "data16" : "data32";
9117 case 0x67:
cb712a9e 9118 if (address_mode == mode_64bit)
db6eb5be 9119 return (sizeflag & AFLAG) ? "addr32" : "addr64";
c1a64871 9120 else
2888cb7a 9121 return (sizeflag & AFLAG) ? "addr16" : "addr32";
7d421014
ILT		 9122 case FWAIT_OPCODE:
9123 return "fwait";
9124 default:
9125 return NULL;
9126 }
9127}
9128
ce518a5f
L		 9129static char op_out[MAX_OPERANDS][100];
9130static int op_ad, op_index[MAX_OPERANDS];
1d9f512f 9131static int two_source_ops;
ce518a5f
L		 9132static bfd_vma op_address[MAX_OPERANDS];
9133static bfd_vma op_riprel[MAX_OPERANDS];
52b15da3 9134static bfd_vma start_pc;
ce518a5f 9135
252b5132
RH		 9136/*
9137 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9138 * (see topic "Redundant prefixes" in the "Differences from 8086"
9139 * section of the "Virtual 8086 Mode" chapter.)
9140 * 'pc' should be the address of this instruction, it will
9141 * be used to print the target address if this is a relative jump or call
9142 * The function returns the length of this instruction in bytes.
9143 */
9144
252b5132 9145static char intel_syntax;
9d141669 9146static char intel_mnemonic = !SYSV386_COMPAT;
252b5132
RH		 9147static char open_char;
9148static char close_char;
9149static char separator_char;
9150static char scale_char;
9151
e396998b
AM		 9152/* Here for backwards compatibility. When gdb stops using
9153 print_insn_i386_att and print_insn_i386_intel these functions can
9154 disappear, and print_insn_i386 be merged into print_insn. */
252b5132 9155int
26ca5450 9156print_insn_i386_att (bfd_vma pc, disassemble_info *info)
252b5132
RH		 9157{
9158 intel_syntax = 0;
e396998b
AM		 9159
9160 return print_insn (pc, info);
252b5132
RH		 9161}
9162
9163int
26ca5450 9164print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
252b5132
RH		 9165{
9166 intel_syntax = 1;
e396998b
AM		 9167
9168 return print_insn (pc, info);
252b5132
RH		 9169}
9170
e396998b 9171int
26ca5450 9172print_insn_i386 (bfd_vma pc, disassemble_info *info)
e396998b
AM		 9173{
9174 intel_syntax = -1;
9175
9176 return print_insn (pc, info);
9177}
9178
f59a29b9
L		 9179void
9180print_i386_disassembler_options (FILE *stream)
9181{
9182 fprintf (stream, _("\n\
9183The following i386/x86-64 specific disassembler options are supported for use\n\
9184with the -M switch (multiple options should be separated by commas):\n"));
9185
9186 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
9187 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
9188 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
9189 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
9190 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
9d141669
L		 9191 fprintf (stream, _(" att-mnemonic\n"
9192 " Display instruction in AT&T mnemonic\n"));
9193 fprintf (stream, _(" intel-mnemonic\n"
9194 " Display instruction in Intel mnemonic\n"));
f59a29b9
L		 9195 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
9196 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
9197 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
9198 fprintf (stream, _(" data32 Assume 32bit data size\n"));
9199 fprintf (stream, _(" data16 Assume 16bit data size\n"));
9200 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
9201}
9202
b844680a
L		 9203/* Get a pointer to struct dis386 with a valid name. */
9204
9205static const struct dis386 *
8bb15339 9206get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
b844680a 9207{
c0f3af97 9208 int index, vex_table_index;
b844680a
L		 9209
9210 if (dp->name != NULL)
9211 return dp;
9212
9213 switch (dp->op[0].bytemode)
9214 {
1ceb70f8
L		 9215 case USE_REG_TABLE:
9216 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9217 break;
9218
9219 case USE_MOD_TABLE:
9220 index = modrm.mod == 0x3 ? 1 : 0;
9221 dp = &mod_table[dp->op[1].bytemode][index];
9222 break;
9223
9224 case USE_RM_TABLE:
9225 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
b844680a
L		 9226 break;
9227
4e7d34a6 9228 case USE_PREFIX_TABLE:
c0f3af97 9229 if (need_vex)
b844680a 9230 {
c0f3af97
L		 9231 /* The prefix in VEX is implicit. */
9232 switch (vex.prefix)
9233 {
9234 case 0:
9235 index = 0;
9236 break;
9237 case REPE_PREFIX_OPCODE:
9238 index = 1;
9239 break;
9240 case DATA_PREFIX_OPCODE:
9241 index = 2;
9242 break;
9243 case REPNE_PREFIX_OPCODE:
9244 index = 3;
9245 break;
9246 default:
9247 abort ();
9248 break;
9249 }
b844680a 9250 }
c0f3af97 9251 else
b844680a 9252 {
c0f3af97
L		 9253 index = 0;
9254 used_prefixes |= (prefixes & PREFIX_REPZ);
9255 if (prefixes & PREFIX_REPZ)
b844680a 9256 {
c0f3af97
L		 9257 index = 1;
9258 repz_prefix = NULL;
b844680a
L		 9259 }
9260 else
9261 {
c0f3af97
L		 9262 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
9263 PREFIX_DATA. */
9264 used_prefixes |= (prefixes & PREFIX_REPNZ);
9265 if (prefixes & PREFIX_REPNZ)
9266 {
9267 index = 3;
9268 repnz_prefix = NULL;
9269 }
9270 else
b844680a 9271 {
c0f3af97
L		 9272 used_prefixes |= (prefixes & PREFIX_DATA);
9273 if (prefixes & PREFIX_DATA)
9274 {
9275 index = 2;
9276 data_prefix = NULL;
9277 }
b844680a
L		 9278 }
9279 }
9280 }
1ceb70f8 9281 dp = &prefix_table[dp->op[1].bytemode][index];
b844680a
L		 9282 break;
9283
4e7d34a6 9284 case USE_X86_64_TABLE:
b844680a
L		 9285 index = address_mode == mode_64bit ? 1 : 0;
9286 dp = &x86_64_table[dp->op[1].bytemode][index];
9287 break;
9288
4e7d34a6 9289 case USE_3BYTE_TABLE:
8bb15339
L		 9290 FETCH_DATA (info, codep + 2);
9291 index = *codep++;
9292 dp = &three_byte_table[dp->op[1].bytemode][index];
9293 modrm.mod = (*codep >> 6) & 3;
9294 modrm.reg = (*codep >> 3) & 7;
9295 modrm.rm = *codep & 7;
9296 break;
9297
c0f3af97
L		 9298 case USE_VEX_LEN_TABLE:
9299 if (!need_vex)
9300 abort ();
9301
9302 switch (vex.length)
9303 {
9304 case 128:
9305 index = 0;
9306 break;
9307 case 256:
9308 index = 1;
9309 break;
9310 default:
9311 abort ();
9312 break;
9313 }
9314
9315 dp = &vex_len_table[dp->op[1].bytemode][index];
9316 break;
9317
9318 case USE_VEX_C4_TABLE:
9319 FETCH_DATA (info, codep + 3);
9320 /* All bits in the REX prefix are ignored. */
9321 rex_ignored = rex;
9322 rex = ~(*codep >> 5) & 0x7;
9323 switch ((*codep & 0x1f))
9324 {
9325 default:
9326 BadOp ();
9327 case 0x1:
9328 vex_table_index = 0;
9329 break;
9330 case 0x2:
9331 vex_table_index = 1;
9332 break;
9333 case 0x3:
9334 vex_table_index = 2;
9335 break;
9336 }
9337 codep++;
9338 vex.w = *codep & 0x80;
9339 if (vex.w && address_mode == mode_64bit)
9340 rex |= REX_W;
9341
9342 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9343 if (address_mode != mode_64bit
9344 && vex.register_specifier > 0x7)
9345 BadOp ();
9346
9347 vex.length = (*codep & 0x4) ? 256 : 128;
9348 switch ((*codep & 0x3))
9349 {
9350 case 0:
9351 vex.prefix = 0;
9352 break;
9353 case 1:
9354 vex.prefix = DATA_PREFIX_OPCODE;
9355 break;
9356 case 2:
9357 vex.prefix = REPE_PREFIX_OPCODE;
9358 break;
9359 case 3:
9360 vex.prefix = REPNE_PREFIX_OPCODE;
9361 break;
9362 }
9363 need_vex = 1;
9364 need_vex_reg = 1;
9365 codep++;
9366 index = *codep++;
9367 dp = &vex_table[vex_table_index][index];
9368 /* There is no MODRM byte for VEX [82|77]. */
9369 if (index != 0x77 && index != 0x82)
9370 {
9371 FETCH_DATA (info, codep + 1);
9372 modrm.mod = (*codep >> 6) & 3;
9373 modrm.reg = (*codep >> 3) & 7;
9374 modrm.rm = *codep & 7;
9375 }
9376 break;
9377
9378 case USE_VEX_C5_TABLE:
9379 FETCH_DATA (info, codep + 2);
9380 /* All bits in the REX prefix are ignored. */
9381 rex_ignored = rex;
9382 rex = (*codep & 0x80) ? 0 : REX_R;
9383
9384 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9385 if (address_mode != mode_64bit
9386 && vex.register_specifier > 0x7)
9387 BadOp ();
9388
9389 vex.length = (*codep & 0x4) ? 256 : 128;
9390 switch ((*codep & 0x3))
9391 {
9392 case 0:
9393 vex.prefix = 0;
9394 break;
9395 case 1:
9396 vex.prefix = DATA_PREFIX_OPCODE;
9397 break;
9398 case 2:
9399 vex.prefix = REPE_PREFIX_OPCODE;
9400 break;
9401 case 3:
9402 vex.prefix = REPNE_PREFIX_OPCODE;
9403 break;
9404 }
9405 need_vex = 1;
9406 need_vex_reg = 1;
9407 codep++;
9408 index = *codep++;
9409 dp = &vex_table[dp->op[1].bytemode][index];
9410 /* There is no MODRM byte for VEX [82|77]. */
9411 if (index != 0x77 && index != 0x82)
9412 {
9413 FETCH_DATA (info, codep + 1);
9414 modrm.mod = (*codep >> 6) & 3;
9415 modrm.reg = (*codep >> 3) & 7;
9416 modrm.rm = *codep & 7;
9417 }
9418 break;
9419
b844680a 9420 default:
d34b5006 9421 abort ();
b844680a
L		 9422 }
9423
9424 if (dp->name != NULL)
9425 return dp;
9426 else
8bb15339 9427 return get_valid_dis386 (dp, info);
b844680a
L		 9428}
9429
e396998b 9430static int
26ca5450 9431print_insn (bfd_vma pc, disassemble_info *info)
252b5132 9432{
2da11e11 9433 const struct dis386 *dp;
252b5132 9434 int i;
ce518a5f 9435 char *op_txt[MAX_OPERANDS];
252b5132 9436 int needcomma;
e396998b
AM		 9437 int sizeflag;
9438 const char *p;
252b5132 9439 struct dis_private priv;
eec0f4ca 9440 unsigned char op;
b844680a
L		 9441 char prefix_obuf[32];
9442 char *prefix_obufp;
252b5132 9443
cb712a9e 9444 if (info->mach == bfd_mach_x86_64_intel_syntax
8a9036a4
L		 9445 || info->mach == bfd_mach_x86_64
9446 || info->mach == bfd_mach_l1om
9447 || info->mach == bfd_mach_l1om_intel_syntax)
cb712a9e
L		 9448 address_mode = mode_64bit;
9449 else
9450 address_mode = mode_32bit;
52b15da3 9451
8373f971 9452 if (intel_syntax == (char) -1)
e396998b 9453 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
8a9036a4
L		 9454 || info->mach == bfd_mach_x86_64_intel_syntax
9455 || info->mach == bfd_mach_l1om_intel_syntax);
e396998b 9456
2da11e11 9457 if (info->mach == bfd_mach_i386_i386
52b15da3 9458 || info->mach == bfd_mach_x86_64
8a9036a4 9459 || info->mach == bfd_mach_l1om
52b15da3 9460 || info->mach == bfd_mach_i386_i386_intel_syntax
8a9036a4
L		 9461 || info->mach == bfd_mach_x86_64_intel_syntax
9462 || info->mach == bfd_mach_l1om_intel_syntax)
e396998b 9463 priv.orig_sizeflag = AFLAG | DFLAG;
2da11e11 9464 else if (info->mach == bfd_mach_i386_i8086)
e396998b 9465 priv.orig_sizeflag = 0;
2da11e11
AM		 9466 else
9467 abort ();
e396998b
AM		 9468
9469 for (p = info->disassembler_options; p != NULL; )
9470 {
0112cd26 9471 if (CONST_STRNEQ (p, "x86-64"))
e396998b 9472 {
cb712a9e 9473 address_mode = mode_64bit;
e396998b
AM		 9474 priv.orig_sizeflag = AFLAG | DFLAG;
9475 }
0112cd26 9476 else if (CONST_STRNEQ (p, "i386"))
e396998b 9477 {
cb712a9e 9478 address_mode = mode_32bit;
e396998b
AM		 9479 priv.orig_sizeflag = AFLAG | DFLAG;
9480 }
0112cd26 9481 else if (CONST_STRNEQ (p, "i8086"))
e396998b 9482 {
cb712a9e 9483 address_mode = mode_16bit;
e396998b
AM		 9484 priv.orig_sizeflag = 0;
9485 }
0112cd26 9486 else if (CONST_STRNEQ (p, "intel"))
e396998b
AM		 9487 {
9488 intel_syntax = 1;
9d141669
L		 9489 if (CONST_STRNEQ (p + 5, "-mnemonic"))
9490 intel_mnemonic = 1;
e396998b 9491 }
0112cd26 9492 else if (CONST_STRNEQ (p, "att"))
e396998b
AM		 9493 {
9494 intel_syntax = 0;
9d141669
L		 9495 if (CONST_STRNEQ (p + 3, "-mnemonic"))
9496 intel_mnemonic = 0;
e396998b 9497 }
0112cd26 9498 else if (CONST_STRNEQ (p, "addr"))
e396998b 9499 {
f59a29b9
L		 9500 if (address_mode == mode_64bit)
9501 {
9502 if (p[4] == '3' && p[5] == '2')
9503 priv.orig_sizeflag &= ~AFLAG;
9504 else if (p[4] == '6' && p[5] == '4')
9505 priv.orig_sizeflag |= AFLAG;
9506 }
9507 else
9508 {
9509 if (p[4] == '1' && p[5] == '6')
9510 priv.orig_sizeflag &= ~AFLAG;
9511 else if (p[4] == '3' && p[5] == '2')
9512 priv.orig_sizeflag |= AFLAG;
9513 }
e396998b 9514 }
0112cd26 9515 else if (CONST_STRNEQ (p, "data"))
e396998b
AM		 9516 {
9517 if (p[4] == '1' && p[5] == '6')
9518 priv.orig_sizeflag &= ~DFLAG;
9519 else if (p[4] == '3' && p[5] == '2')
9520 priv.orig_sizeflag |= DFLAG;
9521 }
0112cd26 9522 else if (CONST_STRNEQ (p, "suffix"))
e396998b
AM		 9523 priv.orig_sizeflag |= SUFFIX_ALWAYS;
9524
9525 p = strchr (p, ',');
9526 if (p != NULL)
9527 p++;
9528 }
9529
9530 if (intel_syntax)
9531 {
9532 names64 = intel_names64;
9533 names32 = intel_names32;
9534 names16 = intel_names16;
9535 names8 = intel_names8;
9536 names8rex = intel_names8rex;
9537 names_seg = intel_names_seg;
db51cc60
L		 9538 index64 = intel_index64;
9539 index32 = intel_index32;
e396998b
AM		 9540 index16 = intel_index16;
9541 open_char = '[';
9542 close_char = ']';
9543 separator_char = '+';
9544 scale_char = '*';
9545 }
9546 else
9547 {
9548 names64 = att_names64;
9549 names32 = att_names32;
9550 names16 = att_names16;
9551 names8 = att_names8;
9552 names8rex = att_names8rex;
9553 names_seg = att_names_seg;
db51cc60
L		 9554 index64 = att_index64;
9555 index32 = att_index32;
e396998b
AM		 9556 index16 = att_index16;
9557 open_char = '(';
9558 close_char = ')';
9559 separator_char = ',';
9560 scale_char = ',';
9561 }
2da11e11 9562
4fe53c98 9563 /* The output looks better if we put 7 bytes on a line, since that
8a9036a4
L		 9564 puts most long word instructions on a single line. Use 8 bytes
9565 for Intel L1OM. */
9566 if (info->mach == bfd_mach_l1om
9567 || info->mach == bfd_mach_l1om_intel_syntax)
9568 info->bytes_per_line = 8;
9569 else
9570 info->bytes_per_line = 7;
252b5132 9571
26ca5450 9572 info->private_data = &priv;
252b5132
RH		 9573 priv.max_fetched = priv.the_buffer;
9574 priv.insn_start = pc;
252b5132
RH		 9575
9576 obuf[0] = 0;
ce518a5f
L		 9577 for (i = 0; i < MAX_OPERANDS; ++i)
9578 {
9579 op_out[i][0] = 0;
9580 op_index[i] = -1;
9581 }
252b5132
RH		 9582
9583 the_info = info;
9584 start_pc = pc;
e396998b
AM		 9585 start_codep = priv.the_buffer;
9586 codep = priv.the_buffer;
252b5132 9587
5076851f
ILT		 9588 if (setjmp (priv.bailout) != 0)
9589 {
7d421014
ILT		 9590 const char *name;
9591
5076851f 9592 /* Getting here means we tried for data but didn't get it. That
e396998b
AM		 9593 means we have an incomplete instruction of some sort. Just
9594 print the first byte as a prefix or a .byte pseudo-op. */
9595 if (codep > priv.the_buffer)
5076851f 9596 {
e396998b 9597 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 9598 if (name != NULL)
9599 (*info->fprintf_func) (info->stream, "%s", name);
9600 else
5076851f 9601 {
7d421014
ILT		 9602 /* Just print the first byte as a .byte instruction. */
9603 (*info->fprintf_func) (info->stream, ".byte 0x%x",
e396998b 9604 (unsigned int) priv.the_buffer[0]);
5076851f 9605 }
5076851f 9606
7d421014 9607 return 1;
5076851f
ILT		 9608 }
9609
9610 return -1;
9611 }
9612
52b15da3 9613 obufp = obuf;
252b5132
RH		 9614 ckprefix ();
9615
9616 insn_codep = codep;
e396998b 9617 sizeflag = priv.orig_sizeflag;
252b5132
RH		 9618
9619 FETCH_DATA (info, codep + 1);
9620 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
9621
3e7d61b2
AM		 9622 if (((prefixes & PREFIX_FWAIT)
9623 && ((*codep < 0xd8) || (*codep > 0xdf)))
9624 || (rex && rex_used))
252b5132 9625 {
7d421014
ILT		 9626 const char *name;
9627
3e7d61b2
AM		 9628 /* fwait not followed by floating point instruction, or rex followed
9629 by other prefixes. Print the first prefix. */
e396998b 9630 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 9631 if (name == NULL)
9632 name = INTERNAL_DISASSEMBLER_ERROR;
9633 (*info->fprintf_func) (info->stream, "%s", name);
9634 return 1;
252b5132
RH		 9635 }
9636
eec0f4ca 9637 op = 0;
c1e679ec 9638
252b5132
RH		 9639 if (*codep == 0x0f)
9640 {
eec0f4ca 9641 unsigned char threebyte;
252b5132 9642 FETCH_DATA (info, codep + 2);
eec0f4ca
L		 9643 threebyte = *++codep;
9644 dp = &dis386_twobyte[threebyte];
252b5132 9645 need_modrm = twobyte_has_modrm[*codep];
eec0f4ca 9646 codep++;
252b5132
RH		 9647 }
9648 else
9649 {
6439fc28 9650 dp = &dis386[*codep];
252b5132 9651 need_modrm = onebyte_has_modrm[*codep];
eec0f4ca 9652 codep++;
252b5132 9653 }
246c51aa 9654
b844680a 9655 if ((prefixes & PREFIX_REPZ))
7d421014 9656 {
b844680a 9657 repz_prefix = "repz ";
7d421014
ILT		 9658 used_prefixes |= PREFIX_REPZ;
9659 }
b844680a
L		 9660 else
9661 repz_prefix = NULL;
9662
9663 if ((prefixes & PREFIX_REPNZ))
7d421014 9664 {
b844680a 9665 repnz_prefix = "repnz ";
7d421014
ILT		 9666 used_prefixes |= PREFIX_REPNZ;
9667 }
b844680a
L		 9668 else
9669 repnz_prefix = NULL;
050dfa73 9670
b844680a 9671 if ((prefixes & PREFIX_LOCK))
7d421014 9672 {
b844680a 9673 lock_prefix = "lock ";
7d421014
ILT		 9674 used_prefixes |= PREFIX_LOCK;
9675 }
b844680a
L		 9676 else
9677 lock_prefix = NULL;
c608c12e 9678
b844680a 9679 addr_prefix = NULL;
c608c12e
AM		 9680 if (prefixes & PREFIX_ADDR)
9681 {
9682 sizeflag ^= AFLAG;
ce518a5f 9683 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
3ffd33cf 9684 {
cb712a9e 9685 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
b844680a 9686 addr_prefix = "addr32 ";
3ffd33cf 9687 else
b844680a 9688 addr_prefix = "addr16 ";
3ffd33cf
AM		 9689 used_prefixes |= PREFIX_ADDR;
9690 }
9691 }
9692
b844680a
L		 9693 data_prefix = NULL;
9694 if ((prefixes & PREFIX_DATA))
3ffd33cf
AM		 9695 {
9696 sizeflag ^= DFLAG;
ce518a5f
L		 9697 if (dp->op[2].bytemode == cond_jump_mode
9698 && dp->op[0].bytemode == v_mode
6439fc28 9699 && !intel_syntax)
3ffd33cf
AM		 9700 {
9701 if (sizeflag & DFLAG)
b844680a 9702 data_prefix = "data32 ";
3ffd33cf 9703 else
b844680a 9704 data_prefix = "data16 ";
3ffd33cf
AM		 9705 used_prefixes |= PREFIX_DATA;
9706 }
9707 }
9708
8bb15339 9709 if (need_modrm)
252b5132
RH		 9710 {
9711 FETCH_DATA (info, codep + 1);
7967e09e
L		 9712 modrm.mod = (*codep >> 6) & 3;
9713 modrm.reg = (*codep >> 3) & 7;
9714 modrm.rm = *codep & 7;
252b5132
RH		 9715 }
9716
55b126d4
L		 9717 need_vex = 0;
9718 need_vex_reg = 0;
9719 vex_w_done = 0;
9720
ce518a5f 9721 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
252b5132
RH		 9722 {
9723 dofloat (sizeflag);
9724 }
9725 else
9726 {
8bb15339 9727 dp = get_valid_dis386 (dp, info);
b844680a 9728 if (dp != NULL && putop (dp->name, sizeflag) == 0)
ce518a5f
L		 9729 {
9730 for (i = 0; i < MAX_OPERANDS; ++i)
9731 {
246c51aa 9732 obufp = op_out[i];
ce518a5f
L		 9733 op_ad = MAX_OPERANDS - 1 - i;
9734 if (dp->op[i].rtn)
9735 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
9736 }
6439fc28 9737 }
252b5132
RH		 9738 }
9739
7d421014
ILT		 9740 /* See if any prefixes were not used. If so, print the first one
9741 separately. If we don't do this, we'll wind up printing an
9742 instruction stream which does not precisely correspond to the
9743 bytes we are disassembling. */
9744 if ((prefixes & ~used_prefixes) != 0)
9745 {
9746 const char *name;
9747
e396998b 9748 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 9749 if (name == NULL)
9750 name = INTERNAL_DISASSEMBLER_ERROR;
9751 (*info->fprintf_func) (info->stream, "%s", name);
9752 return 1;
9753 }
c0f3af97 9754 if ((rex_original & ~rex_used) || rex_ignored)
52b15da3
JH		 9755 {
9756 const char *name;
c0f3af97 9757 name = prefix_name (rex_original, priv.orig_sizeflag);
52b15da3
JH		 9758 if (name == NULL)
9759 name = INTERNAL_DISASSEMBLER_ERROR;
9760 (*info->fprintf_func) (info->stream, "%s ", name);
9761 }
7d421014 9762
b844680a
L		 9763 prefix_obuf[0] = 0;
9764 prefix_obufp = prefix_obuf;
9765 if (lock_prefix)
9766 prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
9767 if (repz_prefix)
9768 prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
9769 if (repnz_prefix)
9770 prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
9771 if (addr_prefix)
9772 prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
9773 if (data_prefix)
9774 prefix_obufp = stpcpy (prefix_obufp, data_prefix);
9775
9776 if (prefix_obuf[0] != 0)
9777 (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
9778
ea397f5b 9779 obufp = mnemonicendp;
b844680a 9780 for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
252b5132
RH		 9781 oappend (" ");
9782 oappend (" ");
9783 (*info->fprintf_func) (info->stream, "%s", obuf);
9784
9785 /* The enter and bound instructions are printed with operands in the same
9786 order as the intel book; everything else is printed in reverse order. */
2da11e11 9787 if (intel_syntax || two_source_ops)
252b5132 9788 {
185b1163
L		 9789 bfd_vma riprel;
9790
ce518a5f
L		 9791 for (i = 0; i < MAX_OPERANDS; ++i)
9792 op_txt[i] = op_out[i];
246c51aa 9793
ce518a5f
L		 9794 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9795 {
9796 op_ad = op_index[i];
9797 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
9798 op_index[MAX_OPERANDS - 1 - i] = op_ad;
185b1163
L		 9799 riprel = op_riprel[i];
9800 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
9801 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
ce518a5f 9802 }
252b5132
RH		 9803 }
9804 else
9805 {
ce518a5f
L		 9806 for (i = 0; i < MAX_OPERANDS; ++i)
9807 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
050dfa73
MM		 9808 }
9809
ce518a5f
L		 9810 needcomma = 0;
9811 for (i = 0; i < MAX_OPERANDS; ++i)
9812 if (*op_txt[i])
9813 {
9814 if (needcomma)
9815 (*info->fprintf_func) (info->stream, ",");
9816 if (op_index[i] != -1 && !op_riprel[i])
9817 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
9818 else
9819 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
9820 needcomma = 1;
9821 }
050dfa73 9822
ce518a5f 9823 for (i = 0; i < MAX_OPERANDS; i++)
52b15da3
JH		 9824 if (op_index[i] != -1 && op_riprel[i])
9825 {
9826 (*info->fprintf_func) (info->stream, " # ");
9827 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
9828 + op_address[op_index[i]]), info);
185b1163 9829 break;
52b15da3 9830 }
e396998b 9831 return codep - priv.the_buffer;
252b5132
RH		 9832}
9833
6439fc28 9834static const char *float_mem[] = {
252b5132 9835 /* d8 */
7c52e0e8
L		 9836 "fadd{s|}",
9837 "fmul{s|}",
9838 "fcom{s|}",
9839 "fcomp{s|}",
9840 "fsub{s|}",
9841 "fsubr{s|}",
9842 "fdiv{s|}",
9843 "fdivr{s|}",
db6eb5be 9844 /* d9 */
7c52e0e8 9845 "fld{s|}",
252b5132 9846 "(bad)",
7c52e0e8
L		 9847 "fst{s|}",
9848 "fstp{s|}",
9306ca4a 9849 "fldenvIC",
252b5132 9850 "fldcw",
9306ca4a 9851 "fNstenvIC",
252b5132
RH		 9852 "fNstcw",
9853 /* da */
7c52e0e8
L		 9854 "fiadd{l|}",
9855 "fimul{l|}",
9856 "ficom{l|}",
9857 "ficomp{l|}",
9858 "fisub{l|}",
9859 "fisubr{l|}",
9860 "fidiv{l|}",
9861 "fidivr{l|}",
252b5132 9862 /* db */
7c52e0e8
L		 9863 "fild{l|}",
9864 "fisttp{l|}",
9865 "fist{l|}",
9866 "fistp{l|}",
252b5132 9867 "(bad)",
6439fc28 9868 "fld{t||t|}",
252b5132 9869 "(bad)",
6439fc28 9870 "fstp{t||t|}",
252b5132 9871 /* dc */
7c52e0e8
L		 9872 "fadd{l|}",
9873 "fmul{l|}",
9874 "fcom{l|}",
9875 "fcomp{l|}",
9876 "fsub{l|}",
9877 "fsubr{l|}",
9878 "fdiv{l|}",
9879 "fdivr{l|}",
252b5132 9880 /* dd */
7c52e0e8
L		 9881 "fld{l|}",
9882 "fisttp{ll|}",
9883 "fst{l||}",
9884 "fstp{l|}",
9306ca4a 9885 "frstorIC",
252b5132 9886 "(bad)",
9306ca4a 9887 "fNsaveIC",
252b5132
RH		 9888 "fNstsw",
9889 /* de */
9890 "fiadd",
9891 "fimul",
9892 "ficom",
9893 "ficomp",
9894 "fisub",
9895 "fisubr",
9896 "fidiv",
9897 "fidivr",
9898 /* df */
9899 "fild",
ca164297 9900 "fisttp",
252b5132
RH		 9901 "fist",
9902 "fistp",
9903 "fbld",
7c52e0e8 9904 "fild{ll|}",
252b5132 9905 "fbstp",
7c52e0e8 9906 "fistp{ll|}",
1d9f512f
AM		 9907};
9908
9909static const unsigned char float_mem_mode[] = {
9910 /* d8 */
9911 d_mode,
9912 d_mode,
9913 d_mode,
9914 d_mode,
9915 d_mode,
9916 d_mode,
9917 d_mode,
9918 d_mode,
9919 /* d9 */
9920 d_mode,
9921 0,
9922 d_mode,
9923 d_mode,
9924 0,
9925 w_mode,
9926 0,
9927 w_mode,
9928 /* da */
9929 d_mode,
9930 d_mode,
9931 d_mode,
9932 d_mode,
9933 d_mode,
9934 d_mode,
9935 d_mode,
9936 d_mode,
9937 /* db */
9938 d_mode,
9939 d_mode,
9940 d_mode,
9941 d_mode,
9942 0,
9306ca4a 9943 t_mode,
1d9f512f 9944 0,
9306ca4a 9945 t_mode,
1d9f512f
AM		 9946 /* dc */
9947 q_mode,
9948 q_mode,
9949 q_mode,
9950 q_mode,
9951 q_mode,
9952 q_mode,
9953 q_mode,
9954 q_mode,
9955 /* dd */
9956 q_mode,
9957 q_mode,
9958 q_mode,
9959 q_mode,
9960 0,
9961 0,
9962 0,
9963 w_mode,
9964 /* de */
9965 w_mode,
9966 w_mode,
9967 w_mode,
9968 w_mode,
9969 w_mode,
9970 w_mode,
9971 w_mode,
9972 w_mode,
9973 /* df */
9974 w_mode,
9975 w_mode,
9976 w_mode,
9977 w_mode,
9306ca4a 9978 t_mode,
1d9f512f 9979 q_mode,
9306ca4a 9980 t_mode,
1d9f512f 9981 q_mode
252b5132
RH		 9982};
9983
ce518a5f
L		 9984#define ST { OP_ST, 0 }
9985#define STi { OP_STi, 0 }
252b5132 9986
4efba78c
L		 9987#define FGRPd9_2 NULL, { { NULL, 0 } }
9988#define FGRPd9_4 NULL, { { NULL, 1 } }
9989#define FGRPd9_5 NULL, { { NULL, 2 } }
9990#define FGRPd9_6 NULL, { { NULL, 3 } }
9991#define FGRPd9_7 NULL, { { NULL, 4 } }
9992#define FGRPda_5 NULL, { { NULL, 5 } }
9993#define FGRPdb_4 NULL, { { NULL, 6 } }
9994#define FGRPde_3 NULL, { { NULL, 7 } }
9995#define FGRPdf_4 NULL, { { NULL, 8 } }
252b5132 9996
2da11e11 9997static const struct dis386 float_reg[][8] = {
252b5132
RH		 9998 /* d8 */
9999 {
ce518a5f
L		 10000 { "fadd", { ST, STi } },
10001 { "fmul", { ST, STi } },
10002 { "fcom", { STi } },
10003 { "fcomp", { STi } },
10004 { "fsub", { ST, STi } },
10005 { "fsubr", { ST, STi } },
10006 { "fdiv", { ST, STi } },
10007 { "fdivr", { ST, STi } },
252b5132
RH		 10008 },
10009 /* d9 */
10010 {
ce518a5f
L		 10011 { "fld", { STi } },
10012 { "fxch", { STi } },
252b5132 10013 { FGRPd9_2 },
ce518a5f 10014 { "(bad)", { XX } },
252b5132
RH		 10015 { FGRPd9_4 },
10016 { FGRPd9_5 },
10017 { FGRPd9_6 },
10018 { FGRPd9_7 },
10019 },
10020 /* da */
10021 {
ce518a5f
L		 10022 { "fcmovb", { ST, STi } },
10023 { "fcmove", { ST, STi } },
10024 { "fcmovbe",{ ST, STi } },
10025 { "fcmovu", { ST, STi } },
10026 { "(bad)", { XX } },
252b5132 10027 { FGRPda_5 },
ce518a5f
L		 10028 { "(bad)", { XX } },
10029 { "(bad)", { XX } },
252b5132
RH		 10030 },
10031 /* db */
10032 {
ce518a5f
L		 10033 { "fcmovnb",{ ST, STi } },
10034 { "fcmovne",{ ST, STi } },
10035 { "fcmovnbe",{ ST, STi } },
10036 { "fcmovnu",{ ST, STi } },
252b5132 10037 { FGRPdb_4 },
ce518a5f
L		 10038 { "fucomi", { ST, STi } },
10039 { "fcomi", { ST, STi } },
10040 { "(bad)", { XX } },
252b5132
RH		 10041 },
10042 /* dc */
10043 {
ce518a5f
L		 10044 { "fadd", { STi, ST } },
10045 { "fmul", { STi, ST } },
10046 { "(bad)", { XX } },
10047 { "(bad)", { XX } },
9d141669
L		 10048 { "fsub!M", { STi, ST } },
10049 { "fsubM", { STi, ST } },
10050 { "fdiv!M", { STi, ST } },
10051 { "fdivM", { STi, ST } },
252b5132
RH		 10052 },
10053 /* dd */
10054 {
ce518a5f
L		 10055 { "ffree", { STi } },
10056 { "(bad)", { XX } },
10057 { "fst", { STi } },
10058 { "fstp", { STi } },
10059 { "fucom", { STi } },
10060 { "fucomp", { STi } },
10061 { "(bad)", { XX } },
10062 { "(bad)", { XX } },
252b5132
RH		 10063 },
10064 /* de */
10065 {
ce518a5f
L		 10066 { "faddp", { STi, ST } },
10067 { "fmulp", { STi, ST } },
10068 { "(bad)", { XX } },
252b5132 10069 { FGRPde_3 },
9d141669
L		 10070 { "fsub!Mp", { STi, ST } },
10071 { "fsubMp", { STi, ST } },
10072 { "fdiv!Mp", { STi, ST } },
10073 { "fdivMp", { STi, ST } },
252b5132
RH		 10074 },
10075 /* df */
10076 {
ce518a5f
L		 10077 { "ffreep", { STi } },
10078 { "(bad)", { XX } },
10079 { "(bad)", { XX } },
10080 { "(bad)", { XX } },
252b5132 10081 { FGRPdf_4 },
ce518a5f
L		 10082 { "fucomip", { ST, STi } },
10083 { "fcomip", { ST, STi } },
10084 { "(bad)", { XX } },
252b5132
RH		 10085 },
10086};
10087
252b5132
RH		 10088static char *fgrps[][8] = {
10089 /* d9_2 0 */
10090 {
10091 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10092 },
10093
10094 /* d9_4 1 */
10095 {
10096 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10097 },
10098
10099 /* d9_5 2 */
10100 {
10101 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10102 },
10103
10104 /* d9_6 3 */
10105 {
10106 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10107 },
10108
10109 /* d9_7 4 */
10110 {
10111 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10112 },
10113
10114 /* da_5 5 */
10115 {
10116 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10117 },
10118
10119 /* db_4 6 */
10120 {
309d3373
JB		 10121 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10122 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
252b5132
RH		 10123 },
10124
10125 /* de_3 7 */
10126 {
10127 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10128 },
10129
10130 /* df_4 8 */
10131 {
10132 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10133 },
10134};
10135
b6169b20
L		 10136static void
10137swap_operand (void)
10138{
10139 mnemonicendp[0] = '.';
10140 mnemonicendp[1] = 's';
10141 mnemonicendp += 2;
10142}
10143
b844680a
L		 10144static void
10145OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10146 int sizeflag ATTRIBUTE_UNUSED)
10147{
10148 /* Skip mod/rm byte. */
10149 MODRM_CHECK;
10150 codep++;
10151}
10152
252b5132 10153static void
26ca5450 10154dofloat (int sizeflag)
252b5132 10155{
2da11e11 10156 const struct dis386 *dp;
252b5132
RH		 10157 unsigned char floatop;
10158
10159 floatop = codep[-1];
10160
7967e09e 10161 if (modrm.mod != 3)
252b5132 10162 {
7967e09e 10163 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
1d9f512f
AM		 10164
10165 putop (float_mem[fp_indx], sizeflag);
ce518a5f 10166 obufp = op_out[0];
6e50d963 10167 op_ad = 2;
1d9f512f 10168 OP_E (float_mem_mode[fp_indx], sizeflag);
252b5132
RH		 10169 return;
10170 }
6608db57 10171 /* Skip mod/rm byte. */
4bba6815 10172 MODRM_CHECK;
252b5132
RH		 10173 codep++;
10174
7967e09e 10175 dp = &float_reg[floatop - 0xd8][modrm.reg];
252b5132
RH		 10176 if (dp->name == NULL)
10177 {
7967e09e 10178 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
252b5132 10179
6608db57 10180 /* Instruction fnstsw is only one with strange arg. */
252b5132 10181 if (floatop == 0xdf && codep[-1] == 0xe0)
ce518a5f 10182 strcpy (op_out[0], names16[0]);
252b5132
RH		 10183 }
10184 else
10185 {
10186 putop (dp->name, sizeflag);
10187
ce518a5f 10188 obufp = op_out[0];
6e50d963 10189 op_ad = 2;
ce518a5f
L		 10190 if (dp->op[0].rtn)
10191 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
6e50d963 10192
ce518a5f 10193 obufp = op_out[1];
6e50d963 10194 op_ad = 1;
ce518a5f
L		 10195 if (dp->op[1].rtn)
10196 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
252b5132
RH		 10197 }
10198}
10199
252b5132 10200static void
26ca5450 10201OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 10202{
422673a9 10203 oappend ("%st" + intel_syntax);
252b5132
RH		 10204}
10205
252b5132 10206static void
26ca5450 10207OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 10208{
7967e09e 10209 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
d708bcba 10210 oappend (scratchbuf + intel_syntax);
252b5132
RH		 10211}
10212
6608db57 10213/* Capital letters in template are macros. */
6439fc28 10214static int
d3ce72d0 10215putop (const char *in_template, int sizeflag)
252b5132 10216{
2da11e11 10217 const char *p;
9306ca4a 10218 int alt = 0;
9d141669 10219 int cond = 1;
98b528ac
L		 10220 unsigned int l = 0, len = 1;
10221 char last[4];
10222
10223#define SAVE_LAST(c) \
10224 if (l < len && l < sizeof (last)) \
10225 last[l++] = c; \
10226 else \
10227 abort ();
252b5132 10228
d3ce72d0 10229 for (p = in_template; *p; p++)
252b5132
RH		 10230 {
10231 switch (*p)
10232 {
10233 default:
10234 *obufp++ = *p;
10235 break;
98b528ac
L		 10236 case '%':
10237 len++;
10238 break;
9d141669
L		 10239 case '!':
10240 cond = 0;
10241 break;
6439fc28
AM		 10242 case '{':
10243 alt = 0;
10244 if (intel_syntax)
6439fc28
AM		 10245 {
10246 while (*++p != '|')
7c52e0e8
L		 10247 if (*p == '}' || *p == '\0')
10248 abort ();
6439fc28 10249 }
9306ca4a
JB		 10250 /* Fall through. */
10251 case 'I':
10252 alt = 1;
10253 continue;
6439fc28
AM		 10254 case '|':
10255 while (*++p != '}')
10256 {
10257 if (*p == '\0')
10258 abort ();
10259 }
10260 break;
10261 case '}':
10262 break;
252b5132 10263 case 'A':
db6eb5be
AM		 10264 if (intel_syntax)
10265 break;
7967e09e 10266 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
252b5132
RH		 10267 *obufp++ = 'b';
10268 break;
10269 case 'B':
4b06377f
L		 10270 if (l == 0 && len == 1)
10271 {
10272case_B:
10273 if (intel_syntax)
10274 break;
10275 if (sizeflag & SUFFIX_ALWAYS)
10276 *obufp++ = 'b';
10277 }
10278 else
10279 {
10280 if (l != 1
10281 || len != 2
10282 || last[0] != 'L')
10283 {
10284 SAVE_LAST (*p);
10285 break;
10286 }
10287
10288 if (address_mode == mode_64bit
10289 && !(prefixes & PREFIX_ADDR))
10290 {
10291 *obufp++ = 'a';
10292 *obufp++ = 'b';
10293 *obufp++ = 's';
10294 }
10295
10296 goto case_B;
10297 }
252b5132 10298 break;
9306ca4a
JB		 10299 case 'C':
10300 if (intel_syntax && !alt)
10301 break;
10302 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10303 {
10304 if (sizeflag & DFLAG)
10305 *obufp++ = intel_syntax ? 'd' : 'l';
10306 else
10307 *obufp++ = intel_syntax ? 'w' : 's';
10308 used_prefixes |= (prefixes & PREFIX_DATA);
10309 }
10310 break;
ed7841b3
JB		 10311 case 'D':
10312 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10313 break;
161a04f6 10314 USED_REX (REX_W);
7967e09e 10315 if (modrm.mod == 3)
ed7841b3 10316 {
161a04f6 10317 if (rex & REX_W)
ed7841b3
JB		 10318 *obufp++ = 'q';
10319 else if (sizeflag & DFLAG)
10320 *obufp++ = intel_syntax ? 'd' : 'l';
10321 else
10322 *obufp++ = 'w';
10323 used_prefixes |= (prefixes & PREFIX_DATA);
10324 }
10325 else
10326 *obufp++ = 'w';
10327 break;
252b5132 10328 case 'E': /* For jcxz/jecxz */
cb712a9e 10329 if (address_mode == mode_64bit)
c1a64871
JH		 10330 {
10331 if (sizeflag & AFLAG)
10332 *obufp++ = 'r';
10333 else
10334 *obufp++ = 'e';
10335 }
10336 else
10337 if (sizeflag & AFLAG)
10338 *obufp++ = 'e';
3ffd33cf
AM		 10339 used_prefixes |= (prefixes & PREFIX_ADDR);
10340 break;
10341 case 'F':
db6eb5be
AM		 10342 if (intel_syntax)
10343 break;
e396998b 10344 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
3ffd33cf
AM		 10345 {
10346 if (sizeflag & AFLAG)
cb712a9e 10347 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
3ffd33cf 10348 else
cb712a9e 10349 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
3ffd33cf
AM		 10350 used_prefixes |= (prefixes & PREFIX_ADDR);
10351 }
252b5132 10352 break;
52fd6d94
JB		 10353 case 'G':
10354 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10355 break;
161a04f6 10356 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 10357 *obufp++ = 'l';
10358 else
10359 *obufp++ = 'w';
161a04f6 10360 if (!(rex & REX_W))
52fd6d94
JB		 10361 used_prefixes |= (prefixes & PREFIX_DATA);
10362 break;
5dd0794d 10363 case 'H':
db6eb5be
AM		 10364 if (intel_syntax)
10365 break;
5dd0794d
AM		 10366 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10367 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10368 {
10369 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10370 *obufp++ = ',';
10371 *obufp++ = 'p';
10372 if (prefixes & PREFIX_DS)
10373 *obufp++ = 't';
10374 else
10375 *obufp++ = 'n';
10376 }
10377 break;
9306ca4a
JB		 10378 case 'J':
10379 if (intel_syntax)
10380 break;
10381 *obufp++ = 'l';
10382 break;
42903f7f
L		 10383 case 'K':
10384 USED_REX (REX_W);
10385 if (rex & REX_W)
10386 *obufp++ = 'q';
10387 else
10388 *obufp++ = 'd';
10389 break;
6dd5059a
L		 10390 case 'Z':
10391 if (intel_syntax)
10392 break;
10393 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
10394 {
10395 *obufp++ = 'q';
10396 break;
10397 }
10398 /* Fall through. */
98b528ac 10399 goto case_L;
252b5132 10400 case 'L':
98b528ac
L		 10401 if (l != 0 || len != 1)
10402 {
10403 SAVE_LAST (*p);
10404 break;
10405 }
10406case_L:
db6eb5be
AM		 10407 if (intel_syntax)
10408 break;
252b5132
RH		 10409 if (sizeflag & SUFFIX_ALWAYS)
10410 *obufp++ = 'l';
252b5132 10411 break;
9d141669
L		 10412 case 'M':
10413 if (intel_mnemonic != cond)
10414 *obufp++ = 'r';
10415 break;
252b5132
RH		 10416 case 'N':
10417 if ((prefixes & PREFIX_FWAIT) == 0)
10418 *obufp++ = 'n';
7d421014
ILT		 10419 else
10420 used_prefixes |= PREFIX_FWAIT;
252b5132 10421 break;
52b15da3 10422 case 'O':
161a04f6
L		 10423 USED_REX (REX_W);
10424 if (rex & REX_W)
6439fc28 10425 *obufp++ = 'o';
a35ca55a
JB		 10426 else if (intel_syntax && (sizeflag & DFLAG))
10427 *obufp++ = 'q';
52b15da3
JH		 10428 else
10429 *obufp++ = 'd';
161a04f6 10430 if (!(rex & REX_W))
a35ca55a 10431 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 10432 break;
6439fc28 10433 case 'T':
db6eb5be
AM		 10434 if (intel_syntax)
10435 break;
cb712a9e 10436 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 10437 {
10438 *obufp++ = 'q';
10439 break;
10440 }
6608db57 10441 /* Fall through. */
252b5132 10442 case 'P':
db6eb5be
AM		 10443 if (intel_syntax)
10444 break;
252b5132 10445 if ((prefixes & PREFIX_DATA)
161a04f6 10446 || (rex & REX_W)
e396998b 10447 || (sizeflag & SUFFIX_ALWAYS))
252b5132 10448 {
161a04f6
L		 10449 USED_REX (REX_W);
10450 if (rex & REX_W)
52b15da3 10451 *obufp++ = 'q';
c2419411 10452 else
52b15da3
JH		 10453 {
10454 if (sizeflag & DFLAG)
10455 *obufp++ = 'l';
10456 else
10457 *obufp++ = 'w';
52b15da3 10458 }
1a114b12 10459 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 10460 }
10461 break;
6439fc28 10462 case 'U':
db6eb5be
AM		 10463 if (intel_syntax)
10464 break;
cb712a9e 10465 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28 10466 {
7967e09e 10467 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
1a114b12 10468 *obufp++ = 'q';
6439fc28
AM		 10469 break;
10470 }
6608db57 10471 /* Fall through. */
98b528ac 10472 goto case_Q;
252b5132 10473 case 'Q':
98b528ac 10474 if (l == 0 && len == 1)
252b5132 10475 {
98b528ac
L		 10476case_Q:
10477 if (intel_syntax && !alt)
10478 break;
10479 USED_REX (REX_W);
10480 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
52b15da3 10481 {
98b528ac
L		 10482 if (rex & REX_W)
10483 *obufp++ = 'q';
52b15da3 10484 else
98b528ac
L		 10485 {
10486 if (sizeflag & DFLAG)
10487 *obufp++ = intel_syntax ? 'd' : 'l';
10488 else
10489 *obufp++ = 'w';
10490 }
10491 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 10492 }
98b528ac
L		 10493 }
10494 else
10495 {
10496 if (l != 1 || len != 2 || last[0] != 'L')
10497 {
10498 SAVE_LAST (*p);
10499 break;
10500 }
10501 if (intel_syntax
10502 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
10503 break;
10504 if ((rex & REX_W))
10505 {
10506 USED_REX (REX_W);
10507 *obufp++ = 'q';
10508 }
10509 else
10510 *obufp++ = 'l';
252b5132
RH		 10511 }
10512 break;
10513 case 'R':
161a04f6
L		 10514 USED_REX (REX_W);
10515 if (rex & REX_W)
a35ca55a
JB		 10516 *obufp++ = 'q';
10517 else if (sizeflag & DFLAG)
c608c12e 10518 {
a35ca55a 10519 if (intel_syntax)
c608c12e 10520 *obufp++ = 'd';
c608c12e 10521 else
a35ca55a 10522 *obufp++ = 'l';
c608c12e 10523 }
252b5132 10524 else
a35ca55a
JB		 10525 *obufp++ = 'w';
10526 if (intel_syntax && !p[1]
161a04f6 10527 && ((rex & REX_W) || (sizeflag & DFLAG)))
a35ca55a 10528 *obufp++ = 'e';
161a04f6 10529 if (!(rex & REX_W))
52b15da3 10530 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 10531 break;
1a114b12 10532 case 'V':
4b06377f 10533 if (l == 0 && len == 1)
1a114b12 10534 {
4b06377f
L		 10535 if (intel_syntax)
10536 break;
10537 if (address_mode == mode_64bit && (sizeflag & DFLAG))
10538 {
10539 if (sizeflag & SUFFIX_ALWAYS)
10540 *obufp++ = 'q';
10541 break;
10542 }
10543 }
10544 else
10545 {
10546 if (l != 1
10547 || len != 2
10548 || last[0] != 'L')
10549 {
10550 SAVE_LAST (*p);
10551 break;
10552 }
10553
10554 if (rex & REX_W)
10555 {
10556 *obufp++ = 'a';
10557 *obufp++ = 'b';
10558 *obufp++ = 's';
10559 }
1a114b12
JB		 10560 }
10561 /* Fall through. */
4b06377f 10562 goto case_S;
252b5132 10563 case 'S':
4b06377f 10564 if (l == 0 && len == 1)
252b5132 10565 {
4b06377f
L		 10566case_S:
10567 if (intel_syntax)
10568 break;
10569 if (sizeflag & SUFFIX_ALWAYS)
52b15da3 10570 {
4b06377f
L		 10571 if (rex & REX_W)
10572 *obufp++ = 'q';
52b15da3 10573 else
4b06377f
L		 10574 {
10575 if (sizeflag & DFLAG)
10576 *obufp++ = 'l';
10577 else
10578 *obufp++ = 'w';
10579 used_prefixes |= (prefixes & PREFIX_DATA);
10580 }
10581 }
10582 }
10583 else
10584 {
10585 if (l != 1
10586 || len != 2
10587 || last[0] != 'L')
10588 {
10589 SAVE_LAST (*p);
10590 break;
52b15da3 10591 }
4b06377f
L		 10592
10593 if (address_mode == mode_64bit
10594 && !(prefixes & PREFIX_ADDR))
10595 {
10596 *obufp++ = 'a';
10597 *obufp++ = 'b';
10598 *obufp++ = 's';
10599 }
10600
10601 goto case_S;
252b5132 10602 }
252b5132 10603 break;
041bd2e0 10604 case 'X':
c0f3af97
L		 10605 if (l != 0 || len != 1)
10606 {
10607 SAVE_LAST (*p);
10608 break;
10609 }
10610 if (need_vex && vex.prefix)
10611 {
10612 if (vex.prefix == DATA_PREFIX_OPCODE)
10613 *obufp++ = 'd';
10614 else
10615 *obufp++ = 's';
10616 }
10617 else if (prefixes & PREFIX_DATA)
041bd2e0
JH		 10618 *obufp++ = 'd';
10619 else
10620 *obufp++ = 's';
db6eb5be 10621 used_prefixes |= (prefixes & PREFIX_DATA);
041bd2e0 10622 break;
76f227a5 10623 case 'Y':
c0f3af97 10624 if (l == 0 && len == 1)
76f227a5 10625 {
c0f3af97
L		 10626 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10627 break;
10628 if (rex & REX_W)
10629 {
10630 USED_REX (REX_W);
10631 *obufp++ = 'q';
10632 }
10633 break;
10634 }
10635 else
10636 {
10637 if (l != 1 || len != 2 || last[0] != 'X')
10638 {
10639 SAVE_LAST (*p);
10640 break;
10641 }
10642 if (!need_vex)
10643 abort ();
10644 if (intel_syntax
10645 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
10646 break;
10647 switch (vex.length)
10648 {
10649 case 128:
10650 *obufp++ = 'x';
10651 break;
10652 case 256:
10653 *obufp++ = 'y';
10654 break;
10655 default:
10656 abort ();
10657 }
76f227a5
JH		 10658 }
10659 break;
252b5132 10660 case 'W':
0bfee649 10661 if (l == 0 && len == 1)
a35ca55a 10662 {
0bfee649
L		 10663 /* operand size flag for cwtl, cbtw */
10664 USED_REX (REX_W);
10665 if (rex & REX_W)
10666 {
10667 if (intel_syntax)
10668 *obufp++ = 'd';
10669 else
10670 *obufp++ = 'l';
10671 }
10672 else if (sizeflag & DFLAG)
10673 *obufp++ = 'w';
a35ca55a 10674 else
0bfee649
L		 10675 *obufp++ = 'b';
10676 if (!(rex & REX_W))
10677 used_prefixes |= (prefixes & PREFIX_DATA);
a35ca55a 10678 }
252b5132 10679 else
0bfee649
L		 10680 {
10681 if (l != 1 || len != 2 || last[0] != 'X')
10682 {
10683 SAVE_LAST (*p);
10684 break;
10685 }
10686 if (!need_vex)
10687 abort ();
10688 *obufp++ = vex.w ? 'd': 's';
10689 }
252b5132
RH		 10690 break;
10691 }
9306ca4a 10692 alt = 0;
252b5132
RH		 10693 }
10694 *obufp = 0;
ea397f5b 10695 mnemonicendp = obufp;
6439fc28 10696 return 0;
252b5132
RH		 10697}
10698
10699static void
26ca5450 10700oappend (const char *s)
252b5132 10701{
ea397f5b 10702 obufp = stpcpy (obufp, s);
252b5132
RH		 10703}
10704
10705static void
26ca5450 10706append_seg (void)
252b5132
RH		 10707{
10708 if (prefixes & PREFIX_CS)
7d421014 10709 {
7d421014 10710 used_prefixes |= PREFIX_CS;
d708bcba 10711 oappend ("%cs:" + intel_syntax);
7d421014 10712 }
252b5132 10713 if (prefixes & PREFIX_DS)
7d421014 10714 {
7d421014 10715 used_prefixes |= PREFIX_DS;
d708bcba 10716 oappend ("%ds:" + intel_syntax);
7d421014 10717 }
252b5132 10718 if (prefixes & PREFIX_SS)
7d421014 10719 {
7d421014 10720 used_prefixes |= PREFIX_SS;
d708bcba 10721 oappend ("%ss:" + intel_syntax);
7d421014 10722 }
252b5132 10723 if (prefixes & PREFIX_ES)
7d421014 10724 {
7d421014 10725 used_prefixes |= PREFIX_ES;
d708bcba 10726 oappend ("%es:" + intel_syntax);
7d421014 10727 }
252b5132 10728 if (prefixes & PREFIX_FS)
7d421014 10729 {
7d421014 10730 used_prefixes |= PREFIX_FS;
d708bcba 10731 oappend ("%fs:" + intel_syntax);
7d421014 10732 }
252b5132 10733 if (prefixes & PREFIX_GS)
7d421014 10734 {
7d421014 10735 used_prefixes |= PREFIX_GS;
d708bcba 10736 oappend ("%gs:" + intel_syntax);
7d421014 10737 }
252b5132
RH		 10738}
10739
10740static void
26ca5450 10741OP_indirE (int bytemode, int sizeflag)
252b5132
RH		 10742{
10743 if (!intel_syntax)
10744 oappend ("*");
10745 OP_E (bytemode, sizeflag);
10746}
10747
52b15da3 10748static void
26ca5450 10749print_operand_value (char *buf, int hex, bfd_vma disp)
52b15da3 10750{
cb712a9e 10751 if (address_mode == mode_64bit)
52b15da3
JH		 10752 {
10753 if (hex)
10754 {
10755 char tmp[30];
10756 int i;
10757 buf[0] = '0';
10758 buf[1] = 'x';
10759 sprintf_vma (tmp, disp);
6608db57 10760 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
52b15da3
JH		 10761 strcpy (buf + 2, tmp + i);
10762 }
10763 else
10764 {
10765 bfd_signed_vma v = disp;
10766 char tmp[30];
10767 int i;
10768 if (v < 0)
10769 {
10770 *(buf++) = '-';
10771 v = -disp;
6608db57 10772 /* Check for possible overflow on 0x8000000000000000. */
52b15da3
JH		 10773 if (v < 0)
10774 {
10775 strcpy (buf, "9223372036854775808");
10776 return;
10777 }
10778 }
10779 if (!v)
10780 {
10781 strcpy (buf, "0");
10782 return;
10783 }
10784
10785 i = 0;
10786 tmp[29] = 0;
10787 while (v)
10788 {
6608db57 10789 tmp[28 - i] = (v % 10) + '0';
52b15da3
JH		 10790 v /= 10;
10791 i++;
10792 }
10793 strcpy (buf, tmp + 29 - i);
10794 }
10795 }
10796 else
10797 {
10798 if (hex)
10799 sprintf (buf, "0x%x", (unsigned int) disp);
10800 else
10801 sprintf (buf, "%d", (int) disp);
10802 }
10803}
10804
5d669648
L		 10805/* Put DISP in BUF as signed hex number. */
10806
10807static void
10808print_displacement (char *buf, bfd_vma disp)
10809{
10810 bfd_signed_vma val = disp;
10811 char tmp[30];
10812 int i, j = 0;
10813
10814 if (val < 0)
10815 {
10816 buf[j++] = '-';
10817 val = -disp;
10818
10819 /* Check for possible overflow. */
10820 if (val < 0)
10821 {
10822 switch (address_mode)
10823 {
10824 case mode_64bit:
10825 strcpy (buf + j, "0x8000000000000000");
10826 break;
10827 case mode_32bit:
10828 strcpy (buf + j, "0x80000000");
10829 break;
10830 case mode_16bit:
10831 strcpy (buf + j, "0x8000");
10832 break;
10833 }
10834 return;
10835 }
10836 }
10837
10838 buf[j++] = '0';
10839 buf[j++] = 'x';
10840
0af1713e 10841 sprintf_vma (tmp, (bfd_vma) val);
5d669648
L		 10842 for (i = 0; tmp[i] == '0'; i++)
10843 continue;
10844 if (tmp[i] == '\0')
10845 i--;
10846 strcpy (buf + j, tmp + i);
10847}
10848
3f31e633
JB		 10849static void
10850intel_operand_size (int bytemode, int sizeflag)
10851{
10852 switch (bytemode)
10853 {
10854 case b_mode:
b6169b20 10855 case b_swap_mode:
42903f7f 10856 case dqb_mode:
3f31e633
JB		 10857 oappend ("BYTE PTR ");
10858 break;
10859 case w_mode:
10860 case dqw_mode:
10861 oappend ("WORD PTR ");
10862 break;
1a114b12 10863 case stack_v_mode:
cb712a9e 10864 if (address_mode == mode_64bit && (sizeflag & DFLAG))
3f31e633
JB		 10865 {
10866 oappend ("QWORD PTR ");
10867 used_prefixes |= (prefixes & PREFIX_DATA);
10868 break;
10869 }
10870 /* FALLTHRU */
10871 case v_mode:
b6169b20 10872 case v_swap_mode:
3f31e633 10873 case dq_mode:
161a04f6
L		 10874 USED_REX (REX_W);
10875 if (rex & REX_W)
3f31e633
JB		 10876 oappend ("QWORD PTR ");
10877 else if ((sizeflag & DFLAG) || bytemode == dq_mode)
10878 oappend ("DWORD PTR ");
10879 else
10880 oappend ("WORD PTR ");
10881 used_prefixes |= (prefixes & PREFIX_DATA);
10882 break;
52fd6d94 10883 case z_mode:
161a04f6 10884 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 10885 *obufp++ = 'D';
10886 oappend ("WORD PTR ");
161a04f6 10887 if (!(rex & REX_W))
52fd6d94
JB		 10888 used_prefixes |= (prefixes & PREFIX_DATA);
10889 break;
34b772a6
JB		 10890 case a_mode:
10891 if (sizeflag & DFLAG)
10892 oappend ("QWORD PTR ");
10893 else
10894 oappend ("DWORD PTR ");
10895 used_prefixes |= (prefixes & PREFIX_DATA);
10896 break;
3f31e633 10897 case d_mode:
fa99fab2 10898 case d_swap_mode:
42903f7f 10899 case dqd_mode:
3f31e633
JB		 10900 oappend ("DWORD PTR ");
10901 break;
10902 case q_mode:
b6169b20 10903 case q_swap_mode:
3f31e633
JB		 10904 oappend ("QWORD PTR ");
10905 break;
10906 case m_mode:
cb712a9e 10907 if (address_mode == mode_64bit)
3f31e633
JB		 10908 oappend ("QWORD PTR ");
10909 else
10910 oappend ("DWORD PTR ");
10911 break;
10912 case f_mode:
10913 if (sizeflag & DFLAG)
10914 oappend ("FWORD PTR ");
10915 else
10916 oappend ("DWORD PTR ");
10917 used_prefixes |= (prefixes & PREFIX_DATA);
10918 break;
10919 case t_mode:
10920 oappend ("TBYTE PTR ");
10921 break;
10922 case x_mode:
b6169b20 10923 case x_swap_mode:
c0f3af97
L		 10924 if (need_vex)
10925 {
10926 switch (vex.length)
10927 {
10928 case 128:
10929 oappend ("XMMWORD PTR ");
10930 break;
10931 case 256:
10932 oappend ("YMMWORD PTR ");
10933 break;
10934 default:
10935 abort ();
10936 }
10937 }
10938 else
10939 oappend ("XMMWORD PTR ");
10940 break;
10941 case xmm_mode:
3f31e633
JB		 10942 oappend ("XMMWORD PTR ");
10943 break;
c0f3af97
L		 10944 case xmmq_mode:
10945 if (!need_vex)
10946 abort ();
10947
10948 switch (vex.length)
10949 {
10950 case 128:
10951 oappend ("QWORD PTR ");
10952 break;
10953 case 256:
10954 oappend ("XMMWORD PTR ");
10955 break;
10956 default:
10957 abort ();
10958 }
10959 break;
10960 case ymmq_mode:
10961 if (!need_vex)
10962 abort ();
10963
10964 switch (vex.length)
10965 {
10966 case 128:
10967 oappend ("QWORD PTR ");
10968 break;
10969 case 256:
10970 oappend ("YMMWORD PTR ");
10971 break;
10972 default:
10973 abort ();
10974 }
10975 break;
fb9c77c7
L		 10976 case o_mode:
10977 oappend ("OWORD PTR ");
10978 break;
0bfee649
L		 10979 case vex_w_dq_mode:
10980 if (!need_vex)
10981 abort ();
10982
10983 if (vex.w)
10984 oappend ("QWORD PTR ");
10985 else
10986 oappend ("DWORD PTR ");
10987 break;
3f31e633
JB		 10988 default:
10989 break;
10990 }
10991}
10992
252b5132 10993static void
c0f3af97 10994OP_E_register (int bytemode, int sizeflag)
252b5132 10995{
c0f3af97
L		 10996 int reg = modrm.rm;
10997 const char **names;
252b5132 10998
c0f3af97
L		 10999 USED_REX (REX_B);
11000 if ((rex & REX_B))
11001 reg += 8;
252b5132 11002
b6169b20
L		 11003 if ((sizeflag & SUFFIX_ALWAYS)
11004 && (bytemode == b_swap_mode || bytemode == v_swap_mode))
11005 swap_operand ();
11006
c0f3af97 11007 switch (bytemode)
252b5132 11008 {
c0f3af97 11009 case b_mode:
b6169b20 11010 case b_swap_mode:
c0f3af97
L		 11011 USED_REX (0);
11012 if (rex)
11013 names = names8rex;
11014 else
11015 names = names8;
11016 break;
11017 case w_mode:
11018 names = names16;
11019 break;
11020 case d_mode:
11021 names = names32;
11022 break;
11023 case q_mode:
11024 names = names64;
11025 break;
11026 case m_mode:
11027 names = address_mode == mode_64bit ? names64 : names32;
11028 break;
11029 case stack_v_mode:
11030 if (address_mode == mode_64bit && (sizeflag & DFLAG))
252b5132 11031 {
c0f3af97 11032 names = names64;
7d421014 11033 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 11034 break;
252b5132 11035 }
c0f3af97
L		 11036 bytemode = v_mode;
11037 /* FALLTHRU */
11038 case v_mode:
b6169b20 11039 case v_swap_mode:
c0f3af97
L		 11040 case dq_mode:
11041 case dqb_mode:
11042 case dqd_mode:
11043 case dqw_mode:
11044 USED_REX (REX_W);
11045 if (rex & REX_W)
11046 names = names64;
b6169b20
L		 11047 else if ((sizeflag & DFLAG)
11048 || (bytemode != v_mode
11049 && bytemode != v_swap_mode))
c0f3af97
L		 11050 names = names32;
11051 else
11052 names = names16;
11053 used_prefixes |= (prefixes & PREFIX_DATA);
11054 break;
11055 case 0:
11056 return;
11057 default:
11058 oappend (INTERNAL_DISASSEMBLER_ERROR);
252b5132
RH		 11059 return;
11060 }
c0f3af97
L		 11061 oappend (names[reg]);
11062}
11063
11064static void
c1e679ec 11065OP_E_memory (int bytemode, int sizeflag)
c0f3af97
L		 11066{
11067 bfd_vma disp = 0;
11068 int add = (rex & REX_B) ? 8 : 0;
11069 int riprel = 0;
252b5132 11070
c0f3af97 11071 USED_REX (REX_B);
3f31e633
JB		 11072 if (intel_syntax)
11073 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 11074 append_seg ();
11075
5d669648 11076 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132 11077 {
5d669648
L		 11078 /* 32/64 bit address mode */
11079 int havedisp;
252b5132
RH		 11080 int havesib;
11081 int havebase;
0f7da397 11082 int haveindex;
20afcfb7 11083 int needindex;
82c18208 11084 int base, rbase;
252b5132
RH		 11085 int index = 0;
11086 int scale = 0;
11087
11088 havesib = 0;
11089 havebase = 1;
0f7da397 11090 haveindex = 0;
7967e09e 11091 base = modrm.rm;
252b5132
RH		 11092
11093 if (base == 4)
11094 {
11095 havesib = 1;
11096 FETCH_DATA (the_info, codep + 1);
252b5132 11097 index = (*codep >> 3) & 7;
db51cc60 11098 scale = (*codep >> 6) & 3;
252b5132 11099 base = *codep & 7;
161a04f6
L		 11100 USED_REX (REX_X);
11101 if (rex & REX_X)
52b15da3 11102 index += 8;
0f7da397 11103 haveindex = index != 4;
252b5132
RH		 11104 codep++;
11105 }
82c18208 11106 rbase = base + add;
252b5132 11107
7967e09e 11108 switch (modrm.mod)
252b5132
RH		 11109 {
11110 case 0:
82c18208 11111 if (base == 5)
252b5132
RH		 11112 {
11113 havebase = 0;
cb712a9e 11114 if (address_mode == mode_64bit && !havesib)
52b15da3
JH		 11115 riprel = 1;
11116 disp = get32s ();
252b5132
RH		 11117 }
11118 break;
11119 case 1:
11120 FETCH_DATA (the_info, codep + 1);
11121 disp = *codep++;
11122 if ((disp & 0x80) != 0)
11123 disp -= 0x100;
11124 break;
11125 case 2:
52b15da3 11126 disp = get32s ();
252b5132
RH		 11127 break;
11128 }
11129
20afcfb7
L		 11130 /* In 32bit mode, we need index register to tell [offset] from
11131 [eiz*1 + offset]. */
11132 needindex = (havesib
11133 && !havebase
11134 && !haveindex
11135 && address_mode == mode_32bit);
11136 havedisp = (havebase
11137 || needindex
11138 || (havesib && (haveindex || scale != 0)));
5d669648 11139
252b5132 11140 if (!intel_syntax)
82c18208 11141 if (modrm.mod != 0 || base == 5)
db6eb5be 11142 {
5d669648
L		 11143 if (havedisp || riprel)
11144 print_displacement (scratchbuf, disp);
11145 else
11146 print_operand_value (scratchbuf, 1, disp);
db6eb5be 11147 oappend (scratchbuf);
52b15da3
JH		 11148 if (riprel)
11149 {
11150 set_op (disp, 1);
87767711 11151 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
52b15da3 11152 }
db6eb5be 11153 }
2da11e11 11154
87767711
JB		 11155 if (havebase || haveindex || riprel)
11156 used_prefixes |= PREFIX_ADDR;
11157
5d669648 11158 if (havedisp || (intel_syntax && riprel))
252b5132 11159 {
252b5132 11160 *obufp++ = open_char;
52b15da3 11161 if (intel_syntax && riprel)
185b1163
L		 11162 {
11163 set_op (disp, 1);
87767711 11164 oappend (sizeflag & AFLAG ? "rip" : "eip");
185b1163 11165 }
db6eb5be 11166 *obufp = '\0';
252b5132 11167 if (havebase)
cb712a9e 11168 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
82c18208 11169 ? names64[rbase] : names32[rbase]);
252b5132
RH		 11170 if (havesib)
11171 {
db51cc60
L		 11172 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
11173 print index to tell base + index from base. */
11174 if (scale != 0
20afcfb7 11175 || needindex
db51cc60
L		 11176 || haveindex
11177 || (havebase && base != ESP_REG_NUM))
252b5132 11178 {
9306ca4a 11179 if (!intel_syntax || havebase)
db6eb5be 11180 {
9306ca4a
JB		 11181 *obufp++ = separator_char;
11182 *obufp = '\0';
db6eb5be 11183 }
db51cc60
L		 11184 if (haveindex)
11185 oappend (address_mode == mode_64bit
11186 && (sizeflag & AFLAG)
11187 ? names64[index] : names32[index]);
11188 else
11189 oappend (address_mode == mode_64bit
11190 && (sizeflag & AFLAG)
11191 ? index64 : index32);
11192
db6eb5be
AM		 11193 *obufp++ = scale_char;
11194 *obufp = '\0';
11195 sprintf (scratchbuf, "%d", 1 << scale);
11196 oappend (scratchbuf);
11197 }
252b5132 11198 }
185b1163 11199 if (intel_syntax
82c18208 11200 && (disp || modrm.mod != 0 || base == 5))
3d456fa1 11201 {
db51cc60 11202 if (!havedisp || (bfd_signed_vma) disp >= 0)
3d456fa1
JB		 11203 {
11204 *obufp++ = '+';
11205 *obufp = '\0';
11206 }
05203043 11207 else if (modrm.mod != 1 && disp != -disp)
3d456fa1
JB		 11208 {
11209 *obufp++ = '-';
11210 *obufp = '\0';
11211 disp = - (bfd_signed_vma) disp;
11212 }
11213
db51cc60
L		 11214 if (havedisp)
11215 print_displacement (scratchbuf, disp);
11216 else
11217 print_operand_value (scratchbuf, 1, disp);
3d456fa1
JB		 11218 oappend (scratchbuf);
11219 }
252b5132
RH		 11220
11221 *obufp++ = close_char;
db6eb5be 11222 *obufp = '\0';
252b5132
RH		 11223 }
11224 else if (intel_syntax)
db6eb5be 11225 {
82c18208 11226 if (modrm.mod != 0 || base == 5)
db6eb5be 11227 {
252b5132
RH		 11228 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11229 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11230 ;
11231 else
11232 {
d708bcba 11233 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 11234 oappend (":");
11235 }
52b15da3 11236 print_operand_value (scratchbuf, 1, disp);
db6eb5be
AM		 11237 oappend (scratchbuf);
11238 }
11239 }
252b5132
RH		 11240 }
11241 else
11242 { /* 16 bit address mode */
7967e09e 11243 switch (modrm.mod)
252b5132
RH		 11244 {
11245 case 0:
7967e09e 11246 if (modrm.rm == 6)
252b5132
RH		 11247 {
11248 disp = get16 ();
11249 if ((disp & 0x8000) != 0)
11250 disp -= 0x10000;
11251 }
11252 break;
11253 case 1:
11254 FETCH_DATA (the_info, codep + 1);
11255 disp = *codep++;
11256 if ((disp & 0x80) != 0)
11257 disp -= 0x100;
11258 break;
11259 case 2:
11260 disp = get16 ();
11261 if ((disp & 0x8000) != 0)
11262 disp -= 0x10000;
11263 break;
11264 }
11265
11266 if (!intel_syntax)
7967e09e 11267 if (modrm.mod != 0 || modrm.rm == 6)
db6eb5be 11268 {
5d669648 11269 print_displacement (scratchbuf, disp);
db6eb5be
AM		 11270 oappend (scratchbuf);
11271 }
252b5132 11272
7967e09e 11273 if (modrm.mod != 0 || modrm.rm != 6)
252b5132
RH		 11274 {
11275 *obufp++ = open_char;
db6eb5be 11276 *obufp = '\0';
7967e09e 11277 oappend (index16[modrm.rm]);
5d669648
L		 11278 if (intel_syntax
11279 && (disp || modrm.mod != 0 || modrm.rm == 6))
3d456fa1 11280 {
5d669648 11281 if ((bfd_signed_vma) disp >= 0)
3d456fa1
JB		 11282 {
11283 *obufp++ = '+';
11284 *obufp = '\0';
11285 }
7967e09e 11286 else if (modrm.mod != 1)
3d456fa1
JB		 11287 {
11288 *obufp++ = '-';
11289 *obufp = '\0';
11290 disp = - (bfd_signed_vma) disp;
11291 }
11292
5d669648 11293 print_displacement (scratchbuf, disp);
3d456fa1
JB		 11294 oappend (scratchbuf);
11295 }
11296
db6eb5be
AM		 11297 *obufp++ = close_char;
11298 *obufp = '\0';
252b5132 11299 }
3d456fa1
JB		 11300 else if (intel_syntax)
11301 {
11302 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11303 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11304 ;
11305 else
11306 {
11307 oappend (names_seg[ds_reg - es_reg]);
11308 oappend (":");
11309 }
11310 print_operand_value (scratchbuf, 1, disp & 0xffff);
11311 oappend (scratchbuf);
11312 }
252b5132
RH		 11313 }
11314}
11315
c0f3af97 11316static void
c1e679ec 11317OP_E_extended (int bytemode, int sizeflag)
c0f3af97
L		 11318{
11319 /* Skip mod/rm byte. */
11320 MODRM_CHECK;
11321 codep++;
11322
11323 if (modrm.mod == 3)
11324 OP_E_register (bytemode, sizeflag);
11325 else
c1e679ec 11326 OP_E_memory (bytemode, sizeflag);
c0f3af97
L		 11327}
11328
85f10a01
MM		 11329static void
11330OP_E (int bytemode, int sizeflag)
11331{
c1e679ec 11332 OP_E_extended (bytemode, sizeflag);
85f10a01
MM		 11333}
11334
11335
252b5132 11336static void
26ca5450 11337OP_G (int bytemode, int sizeflag)
252b5132 11338{
52b15da3 11339 int add = 0;
161a04f6
L		 11340 USED_REX (REX_R);
11341 if (rex & REX_R)
52b15da3 11342 add += 8;
252b5132
RH		 11343 switch (bytemode)
11344 {
11345 case b_mode:
52b15da3
JH		 11346 USED_REX (0);
11347 if (rex)
7967e09e 11348 oappend (names8rex[modrm.reg + add]);
52b15da3 11349 else
7967e09e 11350 oappend (names8[modrm.reg + add]);
252b5132
RH		 11351 break;
11352 case w_mode:
7967e09e 11353 oappend (names16[modrm.reg + add]);
252b5132
RH		 11354 break;
11355 case d_mode:
7967e09e 11356 oappend (names32[modrm.reg + add]);
52b15da3
JH		 11357 break;
11358 case q_mode:
7967e09e 11359 oappend (names64[modrm.reg + add]);
252b5132
RH		 11360 break;
11361 case v_mode:
9306ca4a 11362 case dq_mode:
42903f7f
L		 11363 case dqb_mode:
11364 case dqd_mode:
9306ca4a 11365 case dqw_mode:
161a04f6
L		 11366 USED_REX (REX_W);
11367 if (rex & REX_W)
7967e09e 11368 oappend (names64[modrm.reg + add]);
9306ca4a 11369 else if ((sizeflag & DFLAG) || bytemode != v_mode)
7967e09e 11370 oappend (names32[modrm.reg + add]);
252b5132 11371 else
7967e09e 11372 oappend (names16[modrm.reg + add]);
7d421014 11373 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 11374 break;
90700ea2 11375 case m_mode:
cb712a9e 11376 if (address_mode == mode_64bit)
7967e09e 11377 oappend (names64[modrm.reg + add]);
90700ea2 11378 else
7967e09e 11379 oappend (names32[modrm.reg + add]);
90700ea2 11380 break;
252b5132
RH		 11381 default:
11382 oappend (INTERNAL_DISASSEMBLER_ERROR);
11383 break;
11384 }
11385}
11386
52b15da3 11387static bfd_vma
26ca5450 11388get64 (void)
52b15da3 11389{
5dd0794d 11390 bfd_vma x;
52b15da3 11391#ifdef BFD64
5dd0794d
AM		 11392 unsigned int a;
11393 unsigned int b;
11394
52b15da3
JH		 11395 FETCH_DATA (the_info, codep + 8);
11396 a = *codep++ & 0xff;
11397 a |= (*codep++ & 0xff) << 8;
11398 a |= (*codep++ & 0xff) << 16;
11399 a |= (*codep++ & 0xff) << 24;
5dd0794d 11400 b = *codep++ & 0xff;
52b15da3
JH		 11401 b |= (*codep++ & 0xff) << 8;
11402 b |= (*codep++ & 0xff) << 16;
11403 b |= (*codep++ & 0xff) << 24;
11404 x = a + ((bfd_vma) b << 32);
11405#else
6608db57 11406 abort ();
5dd0794d 11407 x = 0;
52b15da3
JH		 11408#endif
11409 return x;
11410}
11411
11412static bfd_signed_vma
26ca5450 11413get32 (void)
252b5132 11414{
52b15da3 11415 bfd_signed_vma x = 0;
252b5132
RH		 11416
11417 FETCH_DATA (the_info, codep + 4);
52b15da3
JH		 11418 x = *codep++ & (bfd_signed_vma) 0xff;
11419 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11420 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11421 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11422 return x;
11423}
11424
11425static bfd_signed_vma
26ca5450 11426get32s (void)
52b15da3
JH		 11427{
11428 bfd_signed_vma x = 0;
11429
11430 FETCH_DATA (the_info, codep + 4);
11431 x = *codep++ & (bfd_signed_vma) 0xff;
11432 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11433 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11434 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11435
11436 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
11437
252b5132
RH		 11438 return x;
11439}
11440
11441static int
26ca5450 11442get16 (void)
252b5132
RH		 11443{
11444 int x = 0;
11445
11446 FETCH_DATA (the_info, codep + 2);
11447 x = *codep++ & 0xff;
11448 x |= (*codep++ & 0xff) << 8;
11449 return x;
11450}
11451
11452static void
26ca5450 11453set_op (bfd_vma op, int riprel)
252b5132
RH		 11454{
11455 op_index[op_ad] = op_ad;
cb712a9e 11456 if (address_mode == mode_64bit)
7081ff04
AJ		 11457 {
11458 op_address[op_ad] = op;
11459 op_riprel[op_ad] = riprel;
11460 }
11461 else
11462 {
11463 /* Mask to get a 32-bit address. */
11464 op_address[op_ad] = op & 0xffffffff;
11465 op_riprel[op_ad] = riprel & 0xffffffff;
11466 }
252b5132
RH		 11467}
11468
11469static void
26ca5450 11470OP_REG (int code, int sizeflag)
252b5132 11471{
2da11e11 11472 const char *s;
9b60702d 11473 int add;
161a04f6
L		 11474 USED_REX (REX_B);
11475 if (rex & REX_B)
52b15da3 11476 add = 8;
9b60702d
L		 11477 else
11478 add = 0;
52b15da3
JH		 11479
11480 switch (code)
11481 {
52b15da3
JH		 11482 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
11483 case sp_reg: case bp_reg: case si_reg: case di_reg:
11484 s = names16[code - ax_reg + add];
11485 break;
11486 case es_reg: case ss_reg: case cs_reg:
11487 case ds_reg: case fs_reg: case gs_reg:
11488 s = names_seg[code - es_reg + add];
11489 break;
11490 case al_reg: case ah_reg: case cl_reg: case ch_reg:
11491 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
11492 USED_REX (0);
11493 if (rex)
11494 s = names8rex[code - al_reg + add];
11495 else
11496 s = names8[code - al_reg];
11497 break;
6439fc28
AM		 11498 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
11499 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
cb712a9e 11500 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 11501 {
11502 s = names64[code - rAX_reg + add];
11503 break;
11504 }
11505 code += eAX_reg - rAX_reg;
6608db57 11506 /* Fall through. */
52b15da3
JH		 11507 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
11508 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 11509 USED_REX (REX_W);
11510 if (rex & REX_W)
52b15da3
JH		 11511 s = names64[code - eAX_reg + add];
11512 else if (sizeflag & DFLAG)
11513 s = names32[code - eAX_reg + add];
11514 else
11515 s = names16[code - eAX_reg + add];
11516 used_prefixes |= (prefixes & PREFIX_DATA);
11517 break;
52b15da3
JH		 11518 default:
11519 s = INTERNAL_DISASSEMBLER_ERROR;
11520 break;
11521 }
11522 oappend (s);
11523}
11524
11525static void
26ca5450 11526OP_IMREG (int code, int sizeflag)
52b15da3
JH		 11527{
11528 const char *s;
252b5132
RH		 11529
11530 switch (code)
11531 {
11532 case indir_dx_reg:
d708bcba 11533 if (intel_syntax)
52fd6d94 11534 s = "dx";
d708bcba 11535 else
db6eb5be 11536 s = "(%dx)";
252b5132
RH		 11537 break;
11538 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
11539 case sp_reg: case bp_reg: case si_reg: case di_reg:
11540 s = names16[code - ax_reg];
11541 break;
11542 case es_reg: case ss_reg: case cs_reg:
11543 case ds_reg: case fs_reg: case gs_reg:
11544 s = names_seg[code - es_reg];
11545 break;
11546 case al_reg: case ah_reg: case cl_reg: case ch_reg:
11547 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
52b15da3
JH		 11548 USED_REX (0);
11549 if (rex)
11550 s = names8rex[code - al_reg];
11551 else
11552 s = names8[code - al_reg];
252b5132
RH		 11553 break;
11554 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
11555 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 11556 USED_REX (REX_W);
11557 if (rex & REX_W)
52b15da3
JH		 11558 s = names64[code - eAX_reg];
11559 else if (sizeflag & DFLAG)
252b5132
RH		 11560 s = names32[code - eAX_reg];
11561 else
11562 s = names16[code - eAX_reg];
7d421014 11563 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 11564 break;
52fd6d94 11565 case z_mode_ax_reg:
161a04f6 11566 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 11567 s = *names32;
11568 else
11569 s = *names16;
161a04f6 11570 if (!(rex & REX_W))
52fd6d94
JB		 11571 used_prefixes |= (prefixes & PREFIX_DATA);
11572 break;
252b5132
RH		 11573 default:
11574 s = INTERNAL_DISASSEMBLER_ERROR;
11575 break;
11576 }
11577 oappend (s);
11578}
11579
11580static void
26ca5450 11581OP_I (int bytemode, int sizeflag)
252b5132 11582{
52b15da3
JH		 11583 bfd_signed_vma op;
11584 bfd_signed_vma mask = -1;
252b5132
RH		 11585
11586 switch (bytemode)
11587 {
11588 case b_mode:
11589 FETCH_DATA (the_info, codep + 1);
52b15da3
JH		 11590 op = *codep++;
11591 mask = 0xff;
11592 break;
11593 case q_mode:
cb712a9e 11594 if (address_mode == mode_64bit)
6439fc28
AM		 11595 {
11596 op = get32s ();
11597 break;
11598 }
6608db57 11599 /* Fall through. */
252b5132 11600 case v_mode:
161a04f6
L		 11601 USED_REX (REX_W);
11602 if (rex & REX_W)
52b15da3
JH		 11603 op = get32s ();
11604 else if (sizeflag & DFLAG)
11605 {
11606 op = get32 ();
11607 mask = 0xffffffff;
11608 }
252b5132 11609 else
52b15da3
JH		 11610 {
11611 op = get16 ();
11612 mask = 0xfffff;
11613 }
7d421014 11614 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 11615 break;
11616 case w_mode:
52b15da3 11617 mask = 0xfffff;
252b5132
RH		 11618 op = get16 ();
11619 break;
9306ca4a
JB		 11620 case const_1_mode:
11621 if (intel_syntax)
11622 oappend ("1");
11623 return;
252b5132
RH		 11624 default:
11625 oappend (INTERNAL_DISASSEMBLER_ERROR);
11626 return;
11627 }
11628
52b15da3
JH		 11629 op &= mask;
11630 scratchbuf[0] = '$';
d708bcba
AM		 11631 print_operand_value (scratchbuf + 1, 1, op);
11632 oappend (scratchbuf + intel_syntax);
52b15da3
JH		 11633 scratchbuf[0] = '\0';
11634}
11635
11636static void
26ca5450 11637OP_I64 (int bytemode, int sizeflag)
52b15da3
JH		 11638{
11639 bfd_signed_vma op;
11640 bfd_signed_vma mask = -1;
11641
cb712a9e 11642 if (address_mode != mode_64bit)
6439fc28
AM		 11643 {
11644 OP_I (bytemode, sizeflag);
11645 return;
11646 }
11647
52b15da3
JH		 11648 switch (bytemode)
11649 {
11650 case b_mode:
11651 FETCH_DATA (the_info, codep + 1);
11652 op = *codep++;
11653 mask = 0xff;
11654 break;
11655 case v_mode:
161a04f6
L		 11656 USED_REX (REX_W);
11657 if (rex & REX_W)
52b15da3
JH		 11658 op = get64 ();
11659 else if (sizeflag & DFLAG)
11660 {
11661 op = get32 ();
11662 mask = 0xffffffff;
11663 }
11664 else
11665 {
11666 op = get16 ();
11667 mask = 0xfffff;
11668 }
11669 used_prefixes |= (prefixes & PREFIX_DATA);
11670 break;
11671 case w_mode:
11672 mask = 0xfffff;
11673 op = get16 ();
11674 break;
11675 default:
11676 oappend (INTERNAL_DISASSEMBLER_ERROR);
11677 return;
11678 }
11679
11680 op &= mask;
11681 scratchbuf[0] = '$';
d708bcba
AM		 11682 print_operand_value (scratchbuf + 1, 1, op);
11683 oappend (scratchbuf + intel_syntax);
252b5132
RH		 11684 scratchbuf[0] = '\0';
11685}
11686
11687static void
26ca5450 11688OP_sI (int bytemode, int sizeflag)
252b5132 11689{
52b15da3
JH		 11690 bfd_signed_vma op;
11691 bfd_signed_vma mask = -1;
252b5132
RH		 11692
11693 switch (bytemode)
11694 {
11695 case b_mode:
11696 FETCH_DATA (the_info, codep + 1);
11697 op = *codep++;
11698 if ((op & 0x80) != 0)
11699 op -= 0x100;
52b15da3 11700 mask = 0xffffffff;
252b5132
RH		 11701 break;
11702 case v_mode:
161a04f6
L		 11703 USED_REX (REX_W);
11704 if (rex & REX_W)
52b15da3
JH		 11705 op = get32s ();
11706 else if (sizeflag & DFLAG)
11707 {
11708 op = get32s ();
11709 mask = 0xffffffff;
11710 }
252b5132
RH		 11711 else
11712 {
52b15da3 11713 mask = 0xffffffff;
6608db57 11714 op = get16 ();
252b5132
RH		 11715 if ((op & 0x8000) != 0)
11716 op -= 0x10000;
11717 }
7d421014 11718 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 11719 break;
11720 case w_mode:
11721 op = get16 ();
52b15da3 11722 mask = 0xffffffff;
252b5132
RH		 11723 if ((op & 0x8000) != 0)
11724 op -= 0x10000;
11725 break;
11726 default:
11727 oappend (INTERNAL_DISASSEMBLER_ERROR);
11728 return;
11729 }
52b15da3
JH		 11730
11731 scratchbuf[0] = '$';
11732 print_operand_value (scratchbuf + 1, 1, op);
d708bcba 11733 oappend (scratchbuf + intel_syntax);
252b5132
RH		 11734}
11735
11736static void
26ca5450 11737OP_J (int bytemode, int sizeflag)
252b5132 11738{
52b15da3 11739 bfd_vma disp;
7081ff04 11740 bfd_vma mask = -1;
65ca155d 11741 bfd_vma segment = 0;
252b5132
RH		 11742
11743 switch (bytemode)
11744 {
11745 case b_mode:
11746 FETCH_DATA (the_info, codep + 1);
11747 disp = *codep++;
11748 if ((disp & 0x80) != 0)
11749 disp -= 0x100;
11750 break;
11751 case v_mode:
161a04f6 11752 if ((sizeflag & DFLAG) || (rex & REX_W))
52b15da3 11753 disp = get32s ();
252b5132
RH		 11754 else
11755 {
11756 disp = get16 ();
206717e8
L		 11757 if ((disp & 0x8000) != 0)
11758 disp -= 0x10000;
65ca155d
L		 11759 /* In 16bit mode, address is wrapped around at 64k within
11760 the same segment. Otherwise, a data16 prefix on a jump
11761 instruction means that the pc is masked to 16 bits after
11762 the displacement is added! */
11763 mask = 0xffff;
11764 if ((prefixes & PREFIX_DATA) == 0)
11765 segment = ((start_pc + codep - start_codep)
11766 & ~((bfd_vma) 0xffff));
252b5132 11767 }
d807a492 11768 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 11769 break;
11770 default:
11771 oappend (INTERNAL_DISASSEMBLER_ERROR);
11772 return;
11773 }
65ca155d 11774 disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
52b15da3
JH		 11775 set_op (disp, 0);
11776 print_operand_value (scratchbuf, 1, disp);
252b5132
RH		 11777 oappend (scratchbuf);
11778}
11779
252b5132 11780static void
ed7841b3 11781OP_SEG (int bytemode, int sizeflag)
252b5132 11782{
ed7841b3 11783 if (bytemode == w_mode)
7967e09e 11784 oappend (names_seg[modrm.reg]);
ed7841b3 11785 else
7967e09e 11786 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
252b5132
RH		 11787}
11788
11789static void
26ca5450 11790OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
252b5132
RH		 11791{
11792 int seg, offset;
11793
c608c12e 11794 if (sizeflag & DFLAG)
252b5132 11795 {
c608c12e
AM		 11796 offset = get32 ();
11797 seg = get16 ();
252b5132 11798 }
c608c12e
AM		 11799 else
11800 {
11801 offset = get16 ();
11802 seg = get16 ();
11803 }
7d421014 11804 used_prefixes |= (prefixes & PREFIX_DATA);
d708bcba 11805 if (intel_syntax)
3f31e633 11806 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
d708bcba
AM		 11807 else
11808 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
c608c12e 11809 oappend (scratchbuf);
252b5132
RH		 11810}
11811
252b5132 11812static void
3f31e633 11813OP_OFF (int bytemode, int sizeflag)
252b5132 11814{
52b15da3 11815 bfd_vma off;
252b5132 11816
3f31e633
JB		 11817 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
11818 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 11819 append_seg ();
11820
cb712a9e 11821 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132
RH		 11822 off = get32 ();
11823 else
11824 off = get16 ();
11825
11826 if (intel_syntax)
11827 {
11828 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 11829 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
252b5132 11830 {
d708bcba 11831 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 11832 oappend (":");
11833 }
11834 }
52b15da3
JH		 11835 print_operand_value (scratchbuf, 1, off);
11836 oappend (scratchbuf);
11837}
6439fc28 11838
52b15da3 11839static void
3f31e633 11840OP_OFF64 (int bytemode, int sizeflag)
52b15da3
JH		 11841{
11842 bfd_vma off;
11843
539e75ad
L		 11844 if (address_mode != mode_64bit
11845 || (prefixes & PREFIX_ADDR))
6439fc28
AM		 11846 {
11847 OP_OFF (bytemode, sizeflag);
11848 return;
11849 }
11850
3f31e633
JB		 11851 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
11852 intel_operand_size (bytemode, sizeflag);
52b15da3
JH		 11853 append_seg ();
11854
6608db57 11855 off = get64 ();
52b15da3
JH		 11856
11857 if (intel_syntax)
11858 {
11859 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 11860 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
52b15da3 11861 {
d708bcba 11862 oappend (names_seg[ds_reg - es_reg]);
52b15da3
JH		 11863 oappend (":");
11864 }
11865 }
11866 print_operand_value (scratchbuf, 1, off);
252b5132
RH		 11867 oappend (scratchbuf);
11868}
11869
11870static void
26ca5450 11871ptr_reg (int code, int sizeflag)
252b5132 11872{
2da11e11 11873 const char *s;
d708bcba 11874
1d9f512f 11875 *obufp++ = open_char;
20f0a1fc 11876 used_prefixes |= (prefixes & PREFIX_ADDR);
cb712a9e 11877 if (address_mode == mode_64bit)
c1a64871
JH		 11878 {
11879 if (!(sizeflag & AFLAG))
db6eb5be 11880 s = names32[code - eAX_reg];
c1a64871 11881 else
db6eb5be 11882 s = names64[code - eAX_reg];
c1a64871 11883 }
52b15da3 11884 else if (sizeflag & AFLAG)
252b5132
RH		 11885 s = names32[code - eAX_reg];
11886 else
11887 s = names16[code - eAX_reg];
11888 oappend (s);
1d9f512f
AM		 11889 *obufp++ = close_char;
11890 *obufp = 0;
252b5132
RH		 11891}
11892
11893static void
26ca5450 11894OP_ESreg (int code, int sizeflag)
252b5132 11895{
9306ca4a 11896 if (intel_syntax)
52fd6d94
JB		 11897 {
11898 switch (codep[-1])
11899 {
11900 case 0x6d: /* insw/insl */
11901 intel_operand_size (z_mode, sizeflag);
11902 break;
11903 case 0xa5: /* movsw/movsl/movsq */
11904 case 0xa7: /* cmpsw/cmpsl/cmpsq */
11905 case 0xab: /* stosw/stosl */
11906 case 0xaf: /* scasw/scasl */
11907 intel_operand_size (v_mode, sizeflag);
11908 break;
11909 default:
11910 intel_operand_size (b_mode, sizeflag);
11911 }
11912 }
d708bcba 11913 oappend ("%es:" + intel_syntax);
252b5132
RH		 11914 ptr_reg (code, sizeflag);
11915}
11916
11917static void
26ca5450 11918OP_DSreg (int code, int sizeflag)
252b5132 11919{
9306ca4a 11920 if (intel_syntax)
52fd6d94
JB		 11921 {
11922 switch (codep[-1])
11923 {
11924 case 0x6f: /* outsw/outsl */
11925 intel_operand_size (z_mode, sizeflag);
11926 break;
11927 case 0xa5: /* movsw/movsl/movsq */
11928 case 0xa7: /* cmpsw/cmpsl/cmpsq */
11929 case 0xad: /* lodsw/lodsl/lodsq */
11930 intel_operand_size (v_mode, sizeflag);
11931 break;
11932 default:
11933 intel_operand_size (b_mode, sizeflag);
11934 }
11935 }
252b5132
RH		 11936 if ((prefixes
11937 & (PREFIX_CS
11938 | PREFIX_DS
11939 | PREFIX_SS
11940 | PREFIX_ES
11941 | PREFIX_FS
11942 | PREFIX_GS)) == 0)
11943 prefixes |= PREFIX_DS;
6608db57 11944 append_seg ();
252b5132
RH		 11945 ptr_reg (code, sizeflag);
11946}
11947
252b5132 11948static void
26ca5450 11949OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 11950{
9b60702d 11951 int add;
161a04f6 11952 if (rex & REX_R)
c4a530c5 11953 {
161a04f6 11954 USED_REX (REX_R);
c4a530c5
JB		 11955 add = 8;
11956 }
cb712a9e 11957 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
c4a530c5 11958 {
b844680a 11959 lock_prefix = NULL;
c4a530c5
JB		 11960 used_prefixes |= PREFIX_LOCK;
11961 add = 8;
11962 }
9b60702d
L		 11963 else
11964 add = 0;
7967e09e 11965 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
d708bcba 11966 oappend (scratchbuf + intel_syntax);
252b5132
RH		 11967}
11968
252b5132 11969static void
26ca5450 11970OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 11971{
9b60702d 11972 int add;
161a04f6
L		 11973 USED_REX (REX_R);
11974 if (rex & REX_R)
52b15da3 11975 add = 8;
9b60702d
L		 11976 else
11977 add = 0;
d708bcba 11978 if (intel_syntax)
7967e09e 11979 sprintf (scratchbuf, "db%d", modrm.reg + add);
d708bcba 11980 else
7967e09e 11981 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
252b5132
RH		 11982 oappend (scratchbuf);
11983}
11984
252b5132 11985static void
26ca5450 11986OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 11987{
7967e09e 11988 sprintf (scratchbuf, "%%tr%d", modrm.reg);
d708bcba 11989 oappend (scratchbuf + intel_syntax);
252b5132
RH		 11990}
11991
11992static void
6f74c397 11993OP_R (int bytemode, int sizeflag)
252b5132 11994{
7967e09e 11995 if (modrm.mod == 3)
2da11e11
AM		 11996 OP_E (bytemode, sizeflag);
11997 else
6608db57 11998 BadOp ();
252b5132
RH		 11999}
12000
12001static void
26ca5450 12002OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 12003{
041bd2e0
JH		 12004 used_prefixes |= (prefixes & PREFIX_DATA);
12005 if (prefixes & PREFIX_DATA)
20f0a1fc 12006 {
9b60702d 12007 int add;
161a04f6
L		 12008 USED_REX (REX_R);
12009 if (rex & REX_R)
20f0a1fc 12010 add = 8;
9b60702d
L		 12011 else
12012 add = 0;
7967e09e 12013 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
20f0a1fc 12014 }
041bd2e0 12015 else
7967e09e 12016 sprintf (scratchbuf, "%%mm%d", modrm.reg);
d708bcba 12017 oappend (scratchbuf + intel_syntax);
252b5132
RH		 12018}
12019
c608c12e 12020static void
c0f3af97 12021OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
c608c12e 12022{
9b60702d 12023 int add;
161a04f6
L		 12024 USED_REX (REX_R);
12025 if (rex & REX_R)
041bd2e0 12026 add = 8;
9b60702d
L		 12027 else
12028 add = 0;
c0f3af97
L		 12029 if (need_vex && bytemode != xmm_mode)
12030 {
12031 switch (vex.length)
12032 {
12033 case 128:
12034 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12035 break;
12036 case 256:
12037 sprintf (scratchbuf, "%%ymm%d", modrm.reg + add);
12038 break;
12039 default:
12040 abort ();
12041 }
12042 }
12043 else
12044 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
d708bcba 12045 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 12046}
12047
252b5132 12048static void
26ca5450 12049OP_EM (int bytemode, int sizeflag)
252b5132 12050{
7967e09e 12051 if (modrm.mod != 3)
252b5132 12052 {
b6169b20
L		 12053 if (intel_syntax
12054 && (bytemode == v_mode || bytemode == v_swap_mode))
9306ca4a
JB		 12055 {
12056 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12057 used_prefixes |= (prefixes & PREFIX_DATA);
12058 }
252b5132
RH		 12059 OP_E (bytemode, sizeflag);
12060 return;
12061 }
12062
b6169b20
L		 12063 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12064 swap_operand ();
12065
6608db57 12066 /* Skip mod/rm byte. */
4bba6815 12067 MODRM_CHECK;
252b5132 12068 codep++;
041bd2e0
JH		 12069 used_prefixes |= (prefixes & PREFIX_DATA);
12070 if (prefixes & PREFIX_DATA)
20f0a1fc 12071 {
9b60702d 12072 int add;
20f0a1fc 12073
161a04f6
L		 12074 USED_REX (REX_B);
12075 if (rex & REX_B)
20f0a1fc 12076 add = 8;
9b60702d
L		 12077 else
12078 add = 0;
7967e09e 12079 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
20f0a1fc 12080 }
041bd2e0 12081 else
7967e09e 12082 sprintf (scratchbuf, "%%mm%d", modrm.rm);
d708bcba 12083 oappend (scratchbuf + intel_syntax);
252b5132
RH		 12084}
12085
246c51aa
L		 12086/* cvt* are the only instructions in sse2 which have
12087 both SSE and MMX operands and also have 0x66 prefix
12088 in their opcode. 0x66 was originally used to differentiate
12089 between SSE and MMX instruction(operands). So we have to handle the
4d9567e0
MM		 12090 cvt* separately using OP_EMC and OP_MXC */
12091static void
12092OP_EMC (int bytemode, int sizeflag)
12093{
7967e09e 12094 if (modrm.mod != 3)
4d9567e0
MM		 12095 {
12096 if (intel_syntax && bytemode == v_mode)
12097 {
12098 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12099 used_prefixes |= (prefixes & PREFIX_DATA);
12100 }
12101 OP_E (bytemode, sizeflag);
12102 return;
12103 }
246c51aa 12104
4d9567e0
MM		 12105 /* Skip mod/rm byte. */
12106 MODRM_CHECK;
12107 codep++;
12108 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 12109 sprintf (scratchbuf, "%%mm%d", modrm.rm);
4d9567e0
MM		 12110 oappend (scratchbuf + intel_syntax);
12111}
12112
12113static void
12114OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12115{
12116 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 12117 sprintf (scratchbuf, "%%mm%d", modrm.reg);
4d9567e0
MM		 12118 oappend (scratchbuf + intel_syntax);
12119}
12120
c608c12e 12121static void
26ca5450 12122OP_EX (int bytemode, int sizeflag)
c608c12e 12123{
9b60702d 12124 int add;
d6f574e0
L		 12125
12126 /* Skip mod/rm byte. */
12127 MODRM_CHECK;
12128 codep++;
12129
7967e09e 12130 if (modrm.mod != 3)
c608c12e 12131 {
c1e679ec 12132 OP_E_memory (bytemode, sizeflag);
c608c12e
AM		 12133 return;
12134 }
d6f574e0 12135
161a04f6
L		 12136 USED_REX (REX_B);
12137 if (rex & REX_B)
041bd2e0 12138 add = 8;
9b60702d
L		 12139 else
12140 add = 0;
c608c12e 12141
b6169b20 12142 if ((sizeflag & SUFFIX_ALWAYS)
fa99fab2
L		 12143 && (bytemode == x_swap_mode
12144 || bytemode == d_swap_mode
12145 || bytemode == q_swap_mode))
b6169b20
L		 12146 swap_operand ();
12147
c0f3af97
L		 12148 if (need_vex
12149 && bytemode != xmm_mode
12150 && bytemode != xmmq_mode)
12151 {
12152 switch (vex.length)
12153 {
12154 case 128:
12155 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12156 break;
12157 case 256:
12158 sprintf (scratchbuf, "%%ymm%d", modrm.rm + add);
12159 break;
12160 default:
12161 abort ();
12162 }
12163 }
12164 else
12165 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
d708bcba 12166 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 12167}
12168
252b5132 12169static void
26ca5450 12170OP_MS (int bytemode, int sizeflag)
252b5132 12171{
7967e09e 12172 if (modrm.mod == 3)
2da11e11
AM		 12173 OP_EM (bytemode, sizeflag);
12174 else
6608db57 12175 BadOp ();
252b5132
RH		 12176}
12177
992aaec9 12178static void
26ca5450 12179OP_XS (int bytemode, int sizeflag)
992aaec9 12180{
7967e09e 12181 if (modrm.mod == 3)
992aaec9
AM		 12182 OP_EX (bytemode, sizeflag);
12183 else
6608db57 12184 BadOp ();
992aaec9
AM		 12185}
12186
cc0ec051
AM		 12187static void
12188OP_M (int bytemode, int sizeflag)
12189{
7967e09e 12190 if (modrm.mod == 3)
75413a22
L		 12191 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12192 BadOp ();
cc0ec051
AM		 12193 else
12194 OP_E (bytemode, sizeflag);
12195}
12196
12197static void
12198OP_0f07 (int bytemode, int sizeflag)
12199{
7967e09e 12200 if (modrm.mod != 3 || modrm.rm != 0)
cc0ec051
AM		 12201 BadOp ();
12202 else
12203 OP_E (bytemode, sizeflag);
12204}
12205
46e883c5 12206/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
246c51aa 12207 32bit mode and "xchg %rax,%rax" in 64bit mode. */
46e883c5 12208
cc0ec051 12209static void
46e883c5 12210NOP_Fixup1 (int bytemode, int sizeflag)
cc0ec051 12211{
8b38ad71
L		 12212 if ((prefixes & PREFIX_DATA) != 0
12213 || (rex != 0
12214 && rex != 0x48
12215 && address_mode == mode_64bit))
46e883c5
L		 12216 OP_REG (bytemode, sizeflag);
12217 else
12218 strcpy (obuf, "nop");
12219}
12220
12221static void
12222NOP_Fixup2 (int bytemode, int sizeflag)
12223{
8b38ad71
L		 12224 if ((prefixes & PREFIX_DATA) != 0
12225 || (rex != 0
12226 && rex != 0x48
12227 && address_mode == mode_64bit))
46e883c5 12228 OP_IMREG (bytemode, sizeflag);
cc0ec051
AM		 12229}
12230
84037f8c 12231static const char *const Suffix3DNow[] = {
252b5132
RH		 12232/* 00 */ NULL, NULL, NULL, NULL,
12233/* 04 */ NULL, NULL, NULL, NULL,
12234/* 08 */ NULL, NULL, NULL, NULL,
9e525108 12235/* 0C */ "pi2fw", "pi2fd", NULL, NULL,
252b5132
RH		 12236/* 10 */ NULL, NULL, NULL, NULL,
12237/* 14 */ NULL, NULL, NULL, NULL,
12238/* 18 */ NULL, NULL, NULL, NULL,
9e525108 12239/* 1C */ "pf2iw", "pf2id", NULL, NULL,
252b5132
RH		 12240/* 20 */ NULL, NULL, NULL, NULL,
12241/* 24 */ NULL, NULL, NULL, NULL,
12242/* 28 */ NULL, NULL, NULL, NULL,
12243/* 2C */ NULL, NULL, NULL, NULL,
12244/* 30 */ NULL, NULL, NULL, NULL,
12245/* 34 */ NULL, NULL, NULL, NULL,
12246/* 38 */ NULL, NULL, NULL, NULL,
12247/* 3C */ NULL, NULL, NULL, NULL,
12248/* 40 */ NULL, NULL, NULL, NULL,
12249/* 44 */ NULL, NULL, NULL, NULL,
12250/* 48 */ NULL, NULL, NULL, NULL,
12251/* 4C */ NULL, NULL, NULL, NULL,
12252/* 50 */ NULL, NULL, NULL, NULL,
12253/* 54 */ NULL, NULL, NULL, NULL,
12254/* 58 */ NULL, NULL, NULL, NULL,
12255/* 5C */ NULL, NULL, NULL, NULL,
12256/* 60 */ NULL, NULL, NULL, NULL,
12257/* 64 */ NULL, NULL, NULL, NULL,
12258/* 68 */ NULL, NULL, NULL, NULL,
12259/* 6C */ NULL, NULL, NULL, NULL,
12260/* 70 */ NULL, NULL, NULL, NULL,
12261/* 74 */ NULL, NULL, NULL, NULL,
12262/* 78 */ NULL, NULL, NULL, NULL,
12263/* 7C */ NULL, NULL, NULL, NULL,
12264/* 80 */ NULL, NULL, NULL, NULL,
12265/* 84 */ NULL, NULL, NULL, NULL,
9e525108
AM		 12266/* 88 */ NULL, NULL, "pfnacc", NULL,
12267/* 8C */ NULL, NULL, "pfpnacc", NULL,
252b5132
RH		 12268/* 90 */ "pfcmpge", NULL, NULL, NULL,
12269/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
12270/* 98 */ NULL, NULL, "pfsub", NULL,
12271/* 9C */ NULL, NULL, "pfadd", NULL,
12272/* A0 */ "pfcmpgt", NULL, NULL, NULL,
12273/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
12274/* A8 */ NULL, NULL, "pfsubr", NULL,
12275/* AC */ NULL, NULL, "pfacc", NULL,
12276/* B0 */ "pfcmpeq", NULL, NULL, NULL,
9beff690 12277/* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
9e525108 12278/* B8 */ NULL, NULL, NULL, "pswapd",
252b5132
RH		 12279/* BC */ NULL, NULL, NULL, "pavgusb",
12280/* C0 */ NULL, NULL, NULL, NULL,
12281/* C4 */ NULL, NULL, NULL, NULL,
12282/* C8 */ NULL, NULL, NULL, NULL,
12283/* CC */ NULL, NULL, NULL, NULL,
12284/* D0 */ NULL, NULL, NULL, NULL,
12285/* D4 */ NULL, NULL, NULL, NULL,
12286/* D8 */ NULL, NULL, NULL, NULL,
12287/* DC */ NULL, NULL, NULL, NULL,
12288/* E0 */ NULL, NULL, NULL, NULL,
12289/* E4 */ NULL, NULL, NULL, NULL,
12290/* E8 */ NULL, NULL, NULL, NULL,
12291/* EC */ NULL, NULL, NULL, NULL,
12292/* F0 */ NULL, NULL, NULL, NULL,
12293/* F4 */ NULL, NULL, NULL, NULL,
12294/* F8 */ NULL, NULL, NULL, NULL,
12295/* FC */ NULL, NULL, NULL, NULL,
12296};
12297
12298static void
26ca5450 12299OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132
RH		 12300{
12301 const char *mnemonic;
12302
12303 FETCH_DATA (the_info, codep + 1);
12304 /* AMD 3DNow! instructions are specified by an opcode suffix in the
12305 place where an 8-bit immediate would normally go. ie. the last
12306 byte of the instruction. */
ea397f5b 12307 obufp = mnemonicendp;
c608c12e 12308 mnemonic = Suffix3DNow[*codep++ & 0xff];
252b5132 12309 if (mnemonic)
2da11e11 12310 oappend (mnemonic);
252b5132
RH		 12311 else
12312 {
12313 /* Since a variable sized modrm/sib chunk is between the start
12314 of the opcode (0x0f0f) and the opcode suffix, we need to do
12315 all the modrm processing first, and don't know until now that
12316 we have a bad opcode. This necessitates some cleaning up. */
ce518a5f
L		 12317 op_out[0][0] = '\0';
12318 op_out[1][0] = '\0';
6608db57 12319 BadOp ();
252b5132 12320 }
ea397f5b 12321 mnemonicendp = obufp;
252b5132 12322}
c608c12e 12323
ea397f5b
L		 12324static struct op simd_cmp_op[] =
12325{
12326 { STRING_COMMA_LEN ("eq") },
12327 { STRING_COMMA_LEN ("lt") },
12328 { STRING_COMMA_LEN ("le") },
12329 { STRING_COMMA_LEN ("unord") },
12330 { STRING_COMMA_LEN ("neq") },
12331 { STRING_COMMA_LEN ("nlt") },
12332 { STRING_COMMA_LEN ("nle") },
12333 { STRING_COMMA_LEN ("ord") }
c608c12e
AM		 12334};
12335
12336static void
ad19981d 12337CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e
AM		 12338{
12339 unsigned int cmp_type;
12340
12341 FETCH_DATA (the_info, codep + 1);
12342 cmp_type = *codep++ & 0xff;
c0f3af97 12343 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
c608c12e 12344 {
ad19981d 12345 char suffix [3];
ea397f5b 12346 char *p = mnemonicendp - 2;
ad19981d
L		 12347 suffix[0] = p[0];
12348 suffix[1] = p[1];
12349 suffix[2] = '\0';
ea397f5b
L		 12350 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
12351 mnemonicendp += simd_cmp_op[cmp_type].len;
c608c12e
AM		 12352 }
12353 else
12354 {
ad19981d
L		 12355 /* We have a reserved extension byte. Output it directly. */
12356 scratchbuf[0] = '$';
12357 print_operand_value (scratchbuf + 1, 1, cmp_type);
12358 oappend (scratchbuf + intel_syntax);
12359 scratchbuf[0] = '\0';
c608c12e
AM		 12360 }
12361}
12362
ca164297 12363static void
b844680a
L		 12364OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
12365 int sizeflag ATTRIBUTE_UNUSED)
12366{
12367 /* mwait %eax,%ecx */
12368 if (!intel_syntax)
12369 {
12370 const char **names = (address_mode == mode_64bit
12371 ? names64 : names32);
12372 strcpy (op_out[0], names[0]);
12373 strcpy (op_out[1], names[1]);
12374 two_source_ops = 1;
12375 }
12376 /* Skip mod/rm byte. */
12377 MODRM_CHECK;
12378 codep++;
12379}
12380
12381static void
12382OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
12383 int sizeflag ATTRIBUTE_UNUSED)
ca164297 12384{
b844680a
L		 12385 /* monitor %eax,%ecx,%edx" */
12386 if (!intel_syntax)
ca164297 12387 {
b844680a 12388 const char **op1_names;
cb712a9e
L		 12389 const char **names = (address_mode == mode_64bit
12390 ? names64 : names32);
1d9f512f 12391
b844680a
L		 12392 if (!(prefixes & PREFIX_ADDR))
12393 op1_names = (address_mode == mode_16bit
12394 ? names16 : names);
ca164297
L		 12395 else
12396 {
b844680a
L		 12397 /* Remove "addr16/addr32". */
12398 addr_prefix = NULL;
12399 op1_names = (address_mode != mode_32bit
12400 ? names32 : names16);
12401 used_prefixes |= PREFIX_ADDR;
ca164297 12402 }
b844680a
L		 12403 strcpy (op_out[0], op1_names[0]);
12404 strcpy (op_out[1], names[1]);
12405 strcpy (op_out[2], names[2]);
12406 two_source_ops = 1;
ca164297 12407 }
b844680a
L		 12408 /* Skip mod/rm byte. */
12409 MODRM_CHECK;
12410 codep++;
30123838
JB		 12411}
12412
6608db57
KH		 12413static void
12414BadOp (void)
2da11e11 12415{
6608db57
KH		 12416 /* Throw away prefixes and 1st. opcode byte. */
12417 codep = insn_codep + 1;
2da11e11
AM		 12418 oappend ("(bad)");
12419}
4cc91dba 12420
35c52694
L		 12421static void
12422REP_Fixup (int bytemode, int sizeflag)
12423{
12424 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
12425 lods and stos. */
35c52694 12426 if (prefixes & PREFIX_REPZ)
b844680a 12427 repz_prefix = "rep ";
35c52694
L		 12428
12429 switch (bytemode)
12430 {
12431 case al_reg:
12432 case eAX_reg:
12433 case indir_dx_reg:
12434 OP_IMREG (bytemode, sizeflag);
12435 break;
12436 case eDI_reg:
12437 OP_ESreg (bytemode, sizeflag);
12438 break;
12439 case eSI_reg:
12440 OP_DSreg (bytemode, sizeflag);
12441 break;
12442 default:
12443 abort ();
12444 break;
12445 }
12446}
f5804c90
L		 12447
12448static void
12449CMPXCHG8B_Fixup (int bytemode, int sizeflag)
12450{
161a04f6
L		 12451 USED_REX (REX_W);
12452 if (rex & REX_W)
f5804c90
L		 12453 {
12454 /* Change cmpxchg8b to cmpxchg16b. */
ea397f5b
L		 12455 char *p = mnemonicendp - 2;
12456 mnemonicendp = stpcpy (p, "16b");
fb9c77c7 12457 bytemode = o_mode;
f5804c90
L		 12458 }
12459 OP_M (bytemode, sizeflag);
12460}
42903f7f
L		 12461
12462static void
12463XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
12464{
c0f3af97
L		 12465 if (need_vex)
12466 {
12467 switch (vex.length)
12468 {
12469 case 128:
12470 sprintf (scratchbuf, "%%xmm%d", reg);
12471 break;
12472 case 256:
12473 sprintf (scratchbuf, "%%ymm%d", reg);
12474 break;
12475 default:
12476 abort ();
12477 }
12478 }
12479 else
12480 sprintf (scratchbuf, "%%xmm%d", reg);
42903f7f
L		 12481 oappend (scratchbuf + intel_syntax);
12482}
381d071f
L		 12483
12484static void
12485CRC32_Fixup (int bytemode, int sizeflag)
12486{
12487 /* Add proper suffix to "crc32". */
ea397f5b 12488 char *p = mnemonicendp;
381d071f
L		 12489
12490 switch (bytemode)
12491 {
12492 case b_mode:
20592a94 12493 if (intel_syntax)
ea397f5b 12494 goto skip;
20592a94 12495
381d071f
L		 12496 *p++ = 'b';
12497 break;
12498 case v_mode:
20592a94 12499 if (intel_syntax)
ea397f5b 12500 goto skip;
20592a94 12501
381d071f
L		 12502 USED_REX (REX_W);
12503 if (rex & REX_W)
12504 *p++ = 'q';
9344ff29 12505 else if (sizeflag & DFLAG)
20592a94 12506 *p++ = 'l';
381d071f 12507 else
9344ff29
L		 12508 *p++ = 'w';
12509 used_prefixes |= (prefixes & PREFIX_DATA);
381d071f
L		 12510 break;
12511 default:
12512 oappend (INTERNAL_DISASSEMBLER_ERROR);
12513 break;
12514 }
ea397f5b 12515 mnemonicendp = p;
381d071f
L		 12516 *p = '\0';
12517
ea397f5b 12518skip:
381d071f
L		 12519 if (modrm.mod == 3)
12520 {
12521 int add;
12522
12523 /* Skip mod/rm byte. */
12524 MODRM_CHECK;
12525 codep++;
12526
12527 USED_REX (REX_B);
12528 add = (rex & REX_B) ? 8 : 0;
12529 if (bytemode == b_mode)
12530 {
12531 USED_REX (0);
12532 if (rex)
12533 oappend (names8rex[modrm.rm + add]);
12534 else
12535 oappend (names8[modrm.rm + add]);
12536 }
12537 else
12538 {
12539 USED_REX (REX_W);
12540 if (rex & REX_W)
12541 oappend (names64[modrm.rm + add]);
12542 else if ((prefixes & PREFIX_DATA))
12543 oappend (names16[modrm.rm + add]);
12544 else
12545 oappend (names32[modrm.rm + add]);
12546 }
12547 }
12548 else
9344ff29 12549 OP_E (bytemode, sizeflag);
381d071f 12550}
85f10a01 12551
c0f3af97
L		 12552/* Display the destination register operand for instructions with
12553 VEX. */
12554
12555static void
12556OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12557{
12558 if (!need_vex)
12559 abort ();
12560
12561 if (!need_vex_reg)
12562 return;
12563
12564 switch (vex.length)
12565 {
12566 case 128:
12567 switch (bytemode)
12568 {
12569 case vex_mode:
12570 case vex128_mode:
12571 break;
12572 default:
12573 abort ();
12574 return;
12575 }
12576
12577 sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
12578 break;
12579 case 256:
12580 switch (bytemode)
12581 {
12582 case vex_mode:
12583 case vex256_mode:
12584 break;
12585 default:
12586 abort ();
12587 return;
12588 }
12589
12590 sprintf (scratchbuf, "%%ymm%d", vex.register_specifier);
12591 break;
12592 default:
12593 abort ();
12594 break;
12595 }
12596 oappend (scratchbuf + intel_syntax);
12597}
12598
922d8de8
DR		 12599/* Get the VEX immediate byte without moving codep. */
12600
12601static unsigned char
12602get_vex_imm8 (int sizeflag)
12603{
12604 int bytes_before_imm = 0;
12605
12606 /* Skip mod/rm byte. */
12607 MODRM_CHECK;
12608 codep++;
12609
12610 if (modrm.mod != 3)
12611 {
12612 /* There are SIB/displacement bytes. */
12613 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12614 {
12615 /* 32/64 bit address mode */
12616 int base = modrm.rm;
12617
12618 /* Check SIB byte. */
12619 if (base == 4)
12620 {
12621 FETCH_DATA (the_info, codep + 1);
12622 base = *codep & 7;
12623 bytes_before_imm++;
12624 }
12625
12626 switch (modrm.mod)
12627 {
12628 case 0:
12629 /* When modrm.rm == 5 or modrm.rm == 4 and base in
12630 SIB == 5, there is a 4 byte displacement. */
12631 if (base != 5)
12632 /* No displacement. */
12633 break;
12634 case 2:
12635 /* 4 byte displacement. */
12636 bytes_before_imm += 4;
12637 break;
12638 case 1:
12639 /* 1 byte displacement. */
12640 bytes_before_imm++;
12641 break;
12642 }
12643 }
12644 else
12645 { /* 16 bit address mode */
12646 switch (modrm.mod)
12647 {
12648 case 0:
12649 /* When modrm.rm == 6, there is a 2 byte displacement. */
12650 if (modrm.rm != 6)
12651 /* No displacement. */
12652 break;
12653 case 2:
12654 /* 2 byte displacement. */
12655 bytes_before_imm += 2;
12656 break;
12657 case 1:
12658 /* 1 byte displacement. */
12659 bytes_before_imm++;
12660 break;
12661 }
12662 }
12663 }
12664
12665 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
12666 return codep [bytes_before_imm];
12667}
12668
12669static void
12670OP_EX_VexReg (int bytemode, int sizeflag, int reg)
12671{
12672 if (reg == -1 && modrm.mod != 3)
12673 {
12674 OP_E_memory (bytemode, sizeflag);
12675 return;
12676 }
12677 else
12678 {
12679 if (reg == -1)
12680 {
12681 reg = modrm.rm;
12682 USED_REX (REX_B);
12683 if (rex & REX_B)
12684 reg += 8;
12685 }
12686 else if (reg > 7 && address_mode != mode_64bit)
12687 BadOp ();
12688 }
12689
12690 switch (vex.length)
12691 {
12692 case 128:
12693 sprintf (scratchbuf, "%%xmm%d", reg);
12694 break;
12695 case 256:
12696 sprintf (scratchbuf, "%%ymm%d", reg);
12697 break;
12698 default:
12699 abort ();
12700 }
12701 oappend (scratchbuf + intel_syntax);
12702}
12703
12704static void
12705OP_EX_VexW (int bytemode, int sizeflag)
12706{
12707 int reg = -1;
12708
12709 if (!vex_w_done)
12710 {
12711 vex_w_done = 1;
12712 if (vex.w)
206c2556 12713 reg = get_vex_imm8 (sizeflag) >> 4;
922d8de8
DR		 12714 }
12715 else
12716 {
12717 if (!vex.w)
206c2556 12718 reg = get_vex_imm8 (sizeflag) >> 4;
922d8de8
DR		 12719 }
12720
12721 OP_EX_VexReg (bytemode, sizeflag, reg);
12722}
12723
922d8de8
DR		 12724static void
12725VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
12726 int sizeflag ATTRIBUTE_UNUSED)
12727{
12728 /* Skip the immediate byte and check for invalid bits. */
12729 FETCH_DATA (the_info, codep + 1);
12730 if (*codep++ & 0xf)
12731 BadOp ();
12732}
12733
c0f3af97
L		 12734static void
12735OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12736{
12737 int reg;
12738 FETCH_DATA (the_info, codep + 1);
12739 reg = *codep++;
12740
12741 if (bytemode != x_mode)
12742 abort ();
12743
12744 if (reg & 0xf)
12745 BadOp ();
12746
12747 reg >>= 4;
dae39acc
L		 12748 if (reg > 7 && address_mode != mode_64bit)
12749 BadOp ();
12750
c0f3af97
L		 12751 switch (vex.length)
12752 {
12753 case 128:
12754 sprintf (scratchbuf, "%%xmm%d", reg);
12755 break;
12756 case 256:
12757 sprintf (scratchbuf, "%%ymm%d", reg);
12758 break;
12759 default:
12760 abort ();
12761 }
12762 oappend (scratchbuf + intel_syntax);
12763}
12764
922d8de8
DR		 12765static void
12766OP_XMM_VexW (int bytemode, int sizeflag)
12767{
12768 /* Turn off the REX.W bit since it is used for swapping operands
12769 now. */
12770 rex &= ~REX_W;
12771 OP_XMM (bytemode, sizeflag);
12772}
12773
c0f3af97
L		 12774static void
12775OP_EX_Vex (int bytemode, int sizeflag)
12776{
12777 if (modrm.mod != 3)
12778 {
12779 if (vex.register_specifier != 0)
12780 BadOp ();
12781 need_vex_reg = 0;
12782 }
12783 OP_EX (bytemode, sizeflag);
12784}
12785
12786static void
12787OP_XMM_Vex (int bytemode, int sizeflag)
12788{
12789 if (modrm.mod != 3)
12790 {
12791 if (vex.register_specifier != 0)
12792 BadOp ();
12793 need_vex_reg = 0;
12794 }
12795 OP_XMM (bytemode, sizeflag);
12796}
12797
12798static void
12799VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12800{
12801 switch (vex.length)
12802 {
12803 case 128:
ea397f5b 12804 mnemonicendp = stpcpy (obuf, "vzeroupper");
c0f3af97
L		 12805 break;
12806 case 256:
ea397f5b 12807 mnemonicendp = stpcpy (obuf, "vzeroall");
c0f3af97
L		 12808 break;
12809 default:
12810 abort ();
12811 }
12812}
12813
ea397f5b
L		 12814static struct op vex_cmp_op[] =
12815{
12816 { STRING_COMMA_LEN ("eq") },
12817 { STRING_COMMA_LEN ("lt") },
12818 { STRING_COMMA_LEN ("le") },
12819 { STRING_COMMA_LEN ("unord") },
12820 { STRING_COMMA_LEN ("neq") },
12821 { STRING_COMMA_LEN ("nlt") },
12822 { STRING_COMMA_LEN ("nle") },
12823 { STRING_COMMA_LEN ("ord") },
12824 { STRING_COMMA_LEN ("eq_uq") },
12825 { STRING_COMMA_LEN ("nge") },
12826 { STRING_COMMA_LEN ("ngt") },
12827 { STRING_COMMA_LEN ("false") },
12828 { STRING_COMMA_LEN ("neq_oq") },
12829 { STRING_COMMA_LEN ("ge") },
12830 { STRING_COMMA_LEN ("gt") },
12831 { STRING_COMMA_LEN ("true") },
12832 { STRING_COMMA_LEN ("eq_os") },
12833 { STRING_COMMA_LEN ("lt_oq") },
12834 { STRING_COMMA_LEN ("le_oq") },
12835 { STRING_COMMA_LEN ("unord_s") },
12836 { STRING_COMMA_LEN ("neq_us") },
12837 { STRING_COMMA_LEN ("nlt_uq") },
12838 { STRING_COMMA_LEN ("nle_uq") },
12839 { STRING_COMMA_LEN ("ord_s") },
12840 { STRING_COMMA_LEN ("eq_us") },
12841 { STRING_COMMA_LEN ("nge_uq") },
12842 { STRING_COMMA_LEN ("ngt_uq") },
12843 { STRING_COMMA_LEN ("false_os") },
12844 { STRING_COMMA_LEN ("neq_os") },
12845 { STRING_COMMA_LEN ("ge_oq") },
12846 { STRING_COMMA_LEN ("gt_oq") },
12847 { STRING_COMMA_LEN ("true_us") },
c0f3af97
L		 12848};
12849
12850static void
12851VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12852{
12853 unsigned int cmp_type;
12854
12855 FETCH_DATA (the_info, codep + 1);
12856 cmp_type = *codep++ & 0xff;
12857 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
12858 {
12859 char suffix [3];
ea397f5b 12860 char *p = mnemonicendp - 2;
c0f3af97
L		 12861 suffix[0] = p[0];
12862 suffix[1] = p[1];
12863 suffix[2] = '\0';
ea397f5b
L		 12864 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
12865 mnemonicendp += vex_cmp_op[cmp_type].len;
c0f3af97
L		 12866 }
12867 else
12868 {
12869 /* We have a reserved extension byte. Output it directly. */
12870 scratchbuf[0] = '$';
12871 print_operand_value (scratchbuf + 1, 1, cmp_type);
12872 oappend (scratchbuf + intel_syntax);
12873 scratchbuf[0] = '\0';
12874 }
12875}
12876
ea397f5b
L		 12877static const struct op pclmul_op[] =
12878{
12879 { STRING_COMMA_LEN ("lql") },
12880 { STRING_COMMA_LEN ("hql") },
12881 { STRING_COMMA_LEN ("lqh") },
12882 { STRING_COMMA_LEN ("hqh") }
c0f3af97
L		 12883};
12884
12885static void
12886PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
12887 int sizeflag ATTRIBUTE_UNUSED)
12888{
12889 unsigned int pclmul_type;
12890
12891 FETCH_DATA (the_info, codep + 1);
12892 pclmul_type = *codep++ & 0xff;
12893 switch (pclmul_type)
12894 {
12895 case 0x10:
12896 pclmul_type = 2;
12897 break;
12898 case 0x11:
12899 pclmul_type = 3;
12900 break;
12901 default:
12902 break;
12903 }
12904 if (pclmul_type < ARRAY_SIZE (pclmul_op))
12905 {
12906 char suffix [4];
ea397f5b 12907 char *p = mnemonicendp - 3;
c0f3af97
L		 12908 suffix[0] = p[0];
12909 suffix[1] = p[1];
12910 suffix[2] = p[2];
12911 suffix[3] = '\0';
ea397f5b
L		 12912 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
12913 mnemonicendp += pclmul_op[pclmul_type].len;
c0f3af97
L		 12914 }
12915 else
12916 {
12917 /* We have a reserved extension byte. Output it directly. */
12918 scratchbuf[0] = '$';
12919 print_operand_value (scratchbuf + 1, 1, pclmul_type);
12920 oappend (scratchbuf + intel_syntax);
12921 scratchbuf[0] = '\0';
12922 }
12923}
12924
f1f8f695
L		 12925static void
12926MOVBE_Fixup (int bytemode, int sizeflag)
12927{
12928 /* Add proper suffix to "movbe". */
ea397f5b 12929 char *p = mnemonicendp;
f1f8f695
L		 12930
12931 switch (bytemode)
12932 {
12933 case v_mode:
12934 if (intel_syntax)
ea397f5b 12935 goto skip;
f1f8f695
L		 12936
12937 USED_REX (REX_W);
12938 if (sizeflag & SUFFIX_ALWAYS)
12939 {
12940 if (rex & REX_W)
12941 *p++ = 'q';
12942 else if (sizeflag & DFLAG)
12943 *p++ = 'l';
12944 else
12945 *p++ = 'w';
12946 }
12947 used_prefixes |= (prefixes & PREFIX_DATA);
12948 break;
12949 default:
12950 oappend (INTERNAL_DISASSEMBLER_ERROR);
12951 break;
12952 }
ea397f5b 12953 mnemonicendp = p;
f1f8f695
L		 12954 *p = '\0';
12955
ea397f5b 12956skip:
f1f8f695
L		 12957 OP_M (bytemode, sizeflag);
12958}
GDB Binutils - Deliverables
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