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[deliverable/binutils-gdb.git] / opcodes / i386-dis.c
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252b5132 1/* Print i386 instructions for GDB, the GNU debugger.
060d22b0 2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
9b201bb5 3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
252b5132 4
9b201bb5 5 This file is part of the GNU opcodes library.
20f0a1fc 6
9b201bb5 7 This library is free software; you can redistribute it and/or modify
20f0a1fc 8 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
20f0a1fc 11
9b201bb5
NC		 12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
20f0a1fc
NC		 16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
9b201bb5
NC		 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
20f0a1fc
NC		 22
23/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 July 1988
25 modified by John Hassey (hassey@dg-rtp.dg.com)
26 x86-64 support added by Jan Hubicka (jh@suse.cz)
27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28
29/* The main tables describing the instructions is essentially a copy
30 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
31 Programmers Manual. Usually, there is a capital letter, followed
32 by a small letter. The capital letter tell the addressing mode,
33 and the small letter tells about the operand size. Refer to
34 the Intel manual for details. */
252b5132 35
252b5132 36#include "sysdep.h"
dabbade6 37#include "dis-asm.h"
252b5132 38#include "opintl.h"
0b1cf022 39#include "opcode/i386.h"
85f10a01 40#include "libiberty.h"
252b5132
RH		 41
42#include <setjmp.h>
43
26ca5450
AJ		 44static int fetch_data (struct disassemble_info *, bfd_byte *);
45static void ckprefix (void);
46static const char *prefix_name (int, int);
47static int print_insn (bfd_vma, disassemble_info *);
48static void dofloat (int);
49static void OP_ST (int, int);
50static void OP_STi (int, int);
51static int putop (const char *, int);
52static void oappend (const char *);
53static void append_seg (void);
54static void OP_indirE (int, int);
55static void print_operand_value (char *, int, bfd_vma);
c0f3af97
L		 56static void OP_E_register (int, int);
57static void OP_E_memory (int, int, int);
85f10a01 58static void OP_E_extended (int, int, int);
5d669648 59static void print_displacement (char *, bfd_vma);
26ca5450
AJ		 60static void OP_E (int, int);
61static void OP_G (int, int);
62static bfd_vma get64 (void);
63static bfd_signed_vma get32 (void);
64static bfd_signed_vma get32s (void);
65static int get16 (void);
66static void set_op (bfd_vma, int);
b844680a 67static void OP_Skip_MODRM (int, int);
26ca5450
AJ		 68static void OP_REG (int, int);
69static void OP_IMREG (int, int);
70static void OP_I (int, int);
71static void OP_I64 (int, int);
72static void OP_sI (int, int);
73static void OP_J (int, int);
74static void OP_SEG (int, int);
75static void OP_DIR (int, int);
76static void OP_OFF (int, int);
77static void OP_OFF64 (int, int);
78static void ptr_reg (int, int);
79static void OP_ESreg (int, int);
80static void OP_DSreg (int, int);
81static void OP_C (int, int);
82static void OP_D (int, int);
83static void OP_T (int, int);
6f74c397 84static void OP_R (int, int);
26ca5450
AJ		 85static void OP_MMX (int, int);
86static void OP_XMM (int, int);
87static void OP_EM (int, int);
88static void OP_EX (int, int);
4d9567e0
MM		 89static void OP_EMC (int,int);
90static void OP_MXC (int,int);
26ca5450
AJ		 91static void OP_MS (int, int);
92static void OP_XS (int, int);
cc0ec051 93static void OP_M (int, int);
c0f3af97 94static void OP_VEX (int, int);
dae39acc 95static void OP_VEX_FMA (int, int);
c0f3af97
L		 96static void OP_EX_Vex (int, int);
97static void OP_EX_VexW (int, int);
dae39acc 98static void OP_EX_VexImmW (int, int);
c0f3af97
L		 99static void OP_XMM_Vex (int, int);
100static void OP_XMM_VexW (int, int);
101static void OP_REG_VexI4 (int, int);
102static void PCLMUL_Fixup (int, int);
103static void VEXI4_Fixup (int, int);
104static void VZERO_Fixup (int, int);
105static void VCMP_Fixup (int, int);
106static void VPERMIL2_Fixup (int, int);
cc0ec051 107static void OP_0f07 (int, int);
b844680a
L		 108static void OP_Monitor (int, int);
109static void OP_Mwait (int, int);
46e883c5
L		 110static void NOP_Fixup1 (int, int);
111static void NOP_Fixup2 (int, int);
26ca5450 112static void OP_3DNowSuffix (int, int);
ad19981d 113static void CMP_Fixup (int, int);
26ca5450 114static void BadOp (void);
35c52694 115static void REP_Fixup (int, int);
f5804c90 116static void CMPXCHG8B_Fixup (int, int);
42903f7f 117static void XMM_Fixup (int, int);
381d071f 118static void CRC32_Fixup (int, int);
85f10a01
MM		 119static void print_drex_arg (unsigned int, int, int);
120static void OP_DREX4 (int, int);
121static void OP_DREX3 (int, int);
122static void OP_DREX_ICMP (int, int);
123static void OP_DREX_FCMP (int, int);
f1f8f695 124static void MOVBE_Fixup (int, int);
252b5132 125
6608db57 126struct dis_private {
252b5132
RH		 127 /* Points to first byte not fetched. */
128 bfd_byte *max_fetched;
0b1cf022 129 bfd_byte the_buffer[MAX_MNEM_SIZE];
252b5132 130 bfd_vma insn_start;
e396998b 131 int orig_sizeflag;
252b5132
RH		 132 jmp_buf bailout;
133};
134
cb712a9e
L		 135enum address_mode
136{
137 mode_16bit,
138 mode_32bit,
139 mode_64bit
140};
141
142enum address_mode address_mode;
52b15da3 143
5076851f
ILT		 144/* Flags for the prefixes for the current instruction. See below. */
145static int prefixes;
146
52b15da3
JH		 147/* REX prefix the current instruction. See below. */
148static int rex;
149/* Bits of REX we've already used. */
150static int rex_used;
c0f3af97
L		 151/* Original REX prefix. */
152static int rex_original;
153/* REX bits in original REX prefix ignored. It may not be the same
154 as rex_original since some bits may not be ignored. */
155static int rex_ignored;
52b15da3
JH		 156/* Mark parts used in the REX prefix. When we are testing for
157 empty prefix (for 8bit register REX extension), just mask it
158 out. Otherwise test for REX bit is excuse for existence of REX
159 only in case value is nonzero. */
160#define USED_REX(value) \
161 { \
162 if (value) \
161a04f6
L		 163 { \
164 if ((rex & value)) \
165 rex_used |= (value) | REX_OPCODE; \
166 } \
52b15da3 167 else \
161a04f6 168 rex_used |= REX_OPCODE; \
52b15da3
JH		 169 }
170
85f10a01
MM		 171/* Special 'registers' for DREX handling */
172#define DREX_REG_UNKNOWN 1000 /* not initialized */
173#define DREX_REG_MEMORY 1001 /* use MODRM/SIB/OFFSET memory */
174
175/* The DREX byte has the following fields:
176 Bits 7-4 -- DREX.Dest, xmm destination register
177 Bit 3 -- DREX.OC0, operand config bit defines operand order
178 Bit 2 -- DREX.R, equivalent to REX_R bit, to extend ModRM register
179 Bit 1 -- DREX.X, equivalent to REX_X bit, to extend SIB index field
180 Bit 0 -- DREX.W, equivalent to REX_B bit, to extend ModRM r/m field,
181 SIB base field, or opcode reg field. */
182#define DREX_XMM(drex) ((drex >> 4) & 0xf)
183#define DREX_OC0(drex) ((drex >> 3) & 0x1)
184
7d421014
ILT		 185/* Flags for prefixes which we somehow handled when printing the
186 current instruction. */
187static int used_prefixes;
188
5076851f
ILT		 189/* Flags stored in PREFIXES. */
190#define PREFIX_REPZ 1
191#define PREFIX_REPNZ 2
192#define PREFIX_LOCK 4
193#define PREFIX_CS 8
194#define PREFIX_SS 0x10
195#define PREFIX_DS 0x20
196#define PREFIX_ES 0x40
197#define PREFIX_FS 0x80
198#define PREFIX_GS 0x100
199#define PREFIX_DATA 0x200
200#define PREFIX_ADDR 0x400
201#define PREFIX_FWAIT 0x800
202
252b5132
RH		 203/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
204 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
205 on error. */
206#define FETCH_DATA(info, addr) \
6608db57 207 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
252b5132
RH		 208 ? 1 : fetch_data ((info), (addr)))
209
210static int
26ca5450 211fetch_data (struct disassemble_info *info, bfd_byte *addr)
252b5132
RH		 212{
213 int status;
6608db57 214 struct dis_private *priv = (struct dis_private *) info->private_data;
252b5132
RH		 215 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
216
0b1cf022 217 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
272c9217
JB		 218 status = (*info->read_memory_func) (start,
219 priv->max_fetched,
220 addr - priv->max_fetched,
221 info);
222 else
223 status = -1;
252b5132
RH		 224 if (status != 0)
225 {
7d421014 226 /* If we did manage to read at least one byte, then
db6eb5be
AM		 227 print_insn_i386 will do something sensible. Otherwise, print
228 an error. We do that here because this is where we know
229 STATUS. */
7d421014 230 if (priv->max_fetched == priv->the_buffer)
5076851f 231 (*info->memory_error_func) (status, start, info);
252b5132
RH		 232 longjmp (priv->bailout, 1);
233 }
234 else
235 priv->max_fetched = addr;
236 return 1;
237}
238
ce518a5f
L		 239#define XX { NULL, 0 }
240
241#define Eb { OP_E, b_mode }
242#define Ev { OP_E, v_mode }
243#define Ed { OP_E, d_mode }
244#define Edq { OP_E, dq_mode }
245#define Edqw { OP_E, dqw_mode }
42903f7f
L		 246#define Edqb { OP_E, dqb_mode }
247#define Edqd { OP_E, dqd_mode }
09335d05 248#define Eq { OP_E, q_mode }
ce518a5f
L		 249#define indirEv { OP_indirE, stack_v_mode }
250#define indirEp { OP_indirE, f_mode }
251#define stackEv { OP_E, stack_v_mode }
252#define Em { OP_E, m_mode }
253#define Ew { OP_E, w_mode }
254#define M { OP_M, 0 } /* lea, lgdt, etc. */
34b772a6 255#define Ma { OP_M, a_mode }
b844680a 256#define Mb { OP_M, b_mode }
d9a5e5e5 257#define Md { OP_M, d_mode }
f1f8f695 258#define Mo { OP_M, o_mode }
ce518a5f
L		 259#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
260#define Mq { OP_M, q_mode }
4ee52178 261#define Mx { OP_M, x_mode }
c0f3af97 262#define Mxmm { OP_M, xmm_mode }
ce518a5f
L		 263#define Gb { OP_G, b_mode }
264#define Gv { OP_G, v_mode }
265#define Gd { OP_G, d_mode }
266#define Gdq { OP_G, dq_mode }
267#define Gm { OP_G, m_mode }
268#define Gw { OP_G, w_mode }
6f74c397
L		 269#define Rd { OP_R, d_mode }
270#define Rm { OP_R, m_mode }
ce518a5f
L		 271#define Ib { OP_I, b_mode }
272#define sIb { OP_sI, b_mode } /* sign extened byte */
273#define Iv { OP_I, v_mode }
274#define Iq { OP_I, q_mode }
275#define Iv64 { OP_I64, v_mode }
276#define Iw { OP_I, w_mode }
277#define I1 { OP_I, const_1_mode }
278#define Jb { OP_J, b_mode }
279#define Jv { OP_J, v_mode }
280#define Cm { OP_C, m_mode }
281#define Dm { OP_D, m_mode }
282#define Td { OP_T, d_mode }
b844680a 283#define Skip_MODRM { OP_Skip_MODRM, 0 }
ce518a5f
L		 284
285#define RMeAX { OP_REG, eAX_reg }
286#define RMeBX { OP_REG, eBX_reg }
287#define RMeCX { OP_REG, eCX_reg }
288#define RMeDX { OP_REG, eDX_reg }
289#define RMeSP { OP_REG, eSP_reg }
290#define RMeBP { OP_REG, eBP_reg }
291#define RMeSI { OP_REG, eSI_reg }
292#define RMeDI { OP_REG, eDI_reg }
293#define RMrAX { OP_REG, rAX_reg }
294#define RMrBX { OP_REG, rBX_reg }
295#define RMrCX { OP_REG, rCX_reg }
296#define RMrDX { OP_REG, rDX_reg }
297#define RMrSP { OP_REG, rSP_reg }
298#define RMrBP { OP_REG, rBP_reg }
299#define RMrSI { OP_REG, rSI_reg }
300#define RMrDI { OP_REG, rDI_reg }
301#define RMAL { OP_REG, al_reg }
302#define RMAL { OP_REG, al_reg }
303#define RMCL { OP_REG, cl_reg }
304#define RMDL { OP_REG, dl_reg }
305#define RMBL { OP_REG, bl_reg }
306#define RMAH { OP_REG, ah_reg }
307#define RMCH { OP_REG, ch_reg }
308#define RMDH { OP_REG, dh_reg }
309#define RMBH { OP_REG, bh_reg }
310#define RMAX { OP_REG, ax_reg }
311#define RMDX { OP_REG, dx_reg }
312
313#define eAX { OP_IMREG, eAX_reg }
314#define eBX { OP_IMREG, eBX_reg }
315#define eCX { OP_IMREG, eCX_reg }
316#define eDX { OP_IMREG, eDX_reg }
317#define eSP { OP_IMREG, eSP_reg }
318#define eBP { OP_IMREG, eBP_reg }
319#define eSI { OP_IMREG, eSI_reg }
320#define eDI { OP_IMREG, eDI_reg }
321#define AL { OP_IMREG, al_reg }
322#define CL { OP_IMREG, cl_reg }
323#define DL { OP_IMREG, dl_reg }
324#define BL { OP_IMREG, bl_reg }
325#define AH { OP_IMREG, ah_reg }
326#define CH { OP_IMREG, ch_reg }
327#define DH { OP_IMREG, dh_reg }
328#define BH { OP_IMREG, bh_reg }
329#define AX { OP_IMREG, ax_reg }
330#define DX { OP_IMREG, dx_reg }
331#define zAX { OP_IMREG, z_mode_ax_reg }
332#define indirDX { OP_IMREG, indir_dx_reg }
333
334#define Sw { OP_SEG, w_mode }
335#define Sv { OP_SEG, v_mode }
336#define Ap { OP_DIR, 0 }
337#define Ob { OP_OFF64, b_mode }
338#define Ov { OP_OFF64, v_mode }
339#define Xb { OP_DSreg, eSI_reg }
340#define Xv { OP_DSreg, eSI_reg }
341#define Xz { OP_DSreg, eSI_reg }
342#define Yb { OP_ESreg, eDI_reg }
343#define Yv { OP_ESreg, eDI_reg }
344#define DSBX { OP_DSreg, eBX_reg }
345
346#define es { OP_REG, es_reg }
347#define ss { OP_REG, ss_reg }
348#define cs { OP_REG, cs_reg }
349#define ds { OP_REG, ds_reg }
350#define fs { OP_REG, fs_reg }
351#define gs { OP_REG, gs_reg }
352
353#define MX { OP_MMX, 0 }
354#define XM { OP_XMM, 0 }
c0f3af97 355#define XMM { OP_XMM, xmm_mode }
ce518a5f 356#define EM { OP_EM, v_mode }
09a2c6cf 357#define EMd { OP_EM, d_mode }
14051056 358#define EMx { OP_EM, x_mode }
8976381e 359#define EXw { OP_EX, w_mode }
09a2c6cf
L		 360#define EXd { OP_EX, d_mode }
361#define EXq { OP_EX, q_mode }
362#define EXx { OP_EX, x_mode }
c0f3af97
L		 363#define EXxmm { OP_EX, xmm_mode }
364#define EXxmmq { OP_EX, xmmq_mode }
365#define EXymmq { OP_EX, ymmq_mode }
ce518a5f
L		 366#define MS { OP_MS, v_mode }
367#define XS { OP_XS, v_mode }
09335d05 368#define EMCq { OP_EMC, q_mode }
ce518a5f 369#define MXC { OP_MXC, 0 }
ce518a5f 370#define OPSUF { OP_3DNowSuffix, 0 }
ad19981d 371#define CMP { CMP_Fixup, 0 }
42903f7f 372#define XMM0 { XMM_Fixup, 0 }
252b5132 373
c0f3af97
L		 374#define Vex { OP_VEX, vex_mode }
375#define Vex128 { OP_VEX, vex128_mode }
376#define Vex256 { OP_VEX, vex256_mode }
377#define VexI4 { VEXI4_Fixup, 0}
dae39acc
L		 378#define VexFMA { OP_VEX_FMA, vex_mode }
379#define Vex128FMA { OP_VEX_FMA, vex128_mode }
c0f3af97
L		 380#define EXdVex { OP_EX_Vex, d_mode }
381#define EXqVex { OP_EX_Vex, q_mode }
382#define EXVexW { OP_EX_VexW, x_mode }
383#define EXdVexW { OP_EX_VexW, d_mode }
384#define EXqVexW { OP_EX_VexW, q_mode }
dae39acc 385#define EXVexImmW { OP_EX_VexImmW, x_mode }
c0f3af97
L		 386#define XMVex { OP_XMM_Vex, 0 }
387#define XMVexW { OP_XMM_VexW, 0 }
388#define XMVexI4 { OP_REG_VexI4, x_mode }
389#define PCLMUL { PCLMUL_Fixup, 0 }
390#define VZERO { VZERO_Fixup, 0 }
391#define VCMP { VCMP_Fixup, 0 }
392#define VPERMIL2 { VPERMIL2_Fixup, 0 }
393
35c52694 394/* Used handle "rep" prefix for string instructions. */
ce518a5f
L		 395#define Xbr { REP_Fixup, eSI_reg }
396#define Xvr { REP_Fixup, eSI_reg }
397#define Ybr { REP_Fixup, eDI_reg }
398#define Yvr { REP_Fixup, eDI_reg }
399#define Yzr { REP_Fixup, eDI_reg }
400#define indirDXr { REP_Fixup, indir_dx_reg }
401#define ALr { REP_Fixup, al_reg }
402#define eAXr { REP_Fixup, eAX_reg }
403
404#define cond_jump_flag { NULL, cond_jump_mode }
405#define loop_jcxz_flag { NULL, loop_jcxz_mode }
3ffd33cf 406
252b5132 407/* bits in sizeflag */
252b5132 408#define SUFFIX_ALWAYS 4
252b5132
RH		 409#define AFLAG 2
410#define DFLAG 1
411
d55ee72f
L		 412/* byte operand */
413#define b_mode 1
414/* operand size depends on prefixes */
630c2cc5 415#define v_mode (b_mode + 1)
d55ee72f
L		 416/* word operand */
417#define w_mode (v_mode + 1)
418/* double word operand */
419#define d_mode (w_mode + 1)
420/* quad word operand */
421#define q_mode (d_mode + 1)
422/* ten-byte operand */
423#define t_mode (q_mode + 1)
c0f3af97 424/* 16-byte XMM or 32-byte YMM operand */
d55ee72f 425#define x_mode (t_mode + 1)
c0f3af97
L		 426/* 16-byte XMM operand */
427#define xmm_mode (x_mode + 1)
428/* 16-byte XMM or quad word operand */
429#define xmmq_mode (xmm_mode + 1)
430/* 32-byte YMM or quad word operand */
431#define ymmq_mode (xmmq_mode + 1)
d55ee72f 432/* d_mode in 32bit, q_mode in 64bit mode. */
c0f3af97 433#define m_mode (ymmq_mode + 1)
34b772a6
JB		 434/* pair of v_mode operands */
435#define a_mode (m_mode + 1)
436#define cond_jump_mode (a_mode + 1)
d55ee72f
L		 437#define loop_jcxz_mode (cond_jump_mode + 1)
438/* operand size depends on REX prefixes. */
439#define dq_mode (loop_jcxz_mode + 1)
440/* registers like dq_mode, memory like w_mode. */
441#define dqw_mode (dq_mode + 1)
442/* 4- or 6-byte pointer operand */
443#define f_mode (dqw_mode + 1)
444#define const_1_mode (f_mode + 1)
445/* v_mode for stack-related opcodes. */
446#define stack_v_mode (const_1_mode + 1)
447/* non-quad operand size depends on prefixes */
448#define z_mode (stack_v_mode + 1)
449/* 16-byte operand */
450#define o_mode (z_mode + 1)
451/* registers like dq_mode, memory like b_mode. */
452#define dqb_mode (o_mode + 1)
453/* registers like dq_mode, memory like d_mode. */
454#define dqd_mode (dqb_mode + 1)
c0f3af97
L		 455/* normal vex mode */
456#define vex_mode (dqd_mode + 1)
457/* 128bit vex mode */
458#define vex128_mode (vex_mode + 1)
459/* 256bit vex mode */
460#define vex256_mode (vex128_mode + 1)
461
462#define es_reg (vex256_mode + 1)
d55ee72f
L		 463#define cs_reg (es_reg + 1)
464#define ss_reg (cs_reg + 1)
465#define ds_reg (ss_reg + 1)
466#define fs_reg (ds_reg + 1)
467#define gs_reg (fs_reg + 1)
468
469#define eAX_reg (gs_reg + 1)
470#define eCX_reg (eAX_reg + 1)
471#define eDX_reg (eCX_reg + 1)
472#define eBX_reg (eDX_reg + 1)
473#define eSP_reg (eBX_reg + 1)
474#define eBP_reg (eSP_reg + 1)
475#define eSI_reg (eBP_reg + 1)
476#define eDI_reg (eSI_reg + 1)
477
478#define al_reg (eDI_reg + 1)
479#define cl_reg (al_reg + 1)
480#define dl_reg (cl_reg + 1)
481#define bl_reg (dl_reg + 1)
482#define ah_reg (bl_reg + 1)
483#define ch_reg (ah_reg + 1)
484#define dh_reg (ch_reg + 1)
485#define bh_reg (dh_reg + 1)
486
487#define ax_reg (bh_reg + 1)
488#define cx_reg (ax_reg + 1)
489#define dx_reg (cx_reg + 1)
490#define bx_reg (dx_reg + 1)
491#define sp_reg (bx_reg + 1)
492#define bp_reg (sp_reg + 1)
493#define si_reg (bp_reg + 1)
494#define di_reg (si_reg + 1)
495
496#define rAX_reg (di_reg + 1)
497#define rCX_reg (rAX_reg + 1)
498#define rDX_reg (rCX_reg + 1)
499#define rBX_reg (rDX_reg + 1)
500#define rSP_reg (rBX_reg + 1)
501#define rBP_reg (rSP_reg + 1)
502#define rSI_reg (rBP_reg + 1)
503#define rDI_reg (rSI_reg + 1)
504
505#define z_mode_ax_reg (rDI_reg + 1)
506#define indir_dx_reg (z_mode_ax_reg + 1)
507
508#define MAX_BYTEMODE indir_dx_reg
509
510/* Flags that are OR'ed into the bytemode field to pass extra
511 information. */
512#define DREX_OC1 0x10000 /* OC1 bit set */
513#define DREX_NO_OC0 0x20000 /* OC0 bit not used */
514#define DREX_MASK 0x40000 /* mask to delete */
515
516#if MAX_BYTEMODE >= DREX_OC1
517#error MAX_BYTEMODE must be less than DREX_OC1
518#endif
252b5132 519
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L		 520#define FLOATCODE 1
521#define USE_REG_TABLE (FLOATCODE + 1)
522#define USE_MOD_TABLE (USE_REG_TABLE + 1)
523#define USE_RM_TABLE (USE_MOD_TABLE + 1)
524#define USE_PREFIX_TABLE (USE_RM_TABLE + 1)
525#define USE_X86_64_TABLE (USE_PREFIX_TABLE + 1)
526#define USE_3BYTE_TABLE (USE_X86_64_TABLE + 1)
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L		 527#define USE_VEX_C4_TABLE (USE_3BYTE_TABLE + 1)
528#define USE_VEX_C5_TABLE (USE_VEX_C4_TABLE + 1)
529#define USE_VEX_LEN_TABLE (USE_VEX_C5_TABLE + 1)
6439fc28 530
1ceb70f8 531#define FLOAT NULL, { { NULL, FLOATCODE } }
4efba78c 532
4e7d34a6 533#define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
1ceb70f8
L		 534#define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
535#define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
536#define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
537#define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
4e7d34a6
L		 538#define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
539#define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
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L		 540#define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
541#define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
542#define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
1ceb70f8
L		 543
544#define REG_80 0
545#define REG_81 (REG_80 + 1)
546#define REG_82 (REG_81 + 1)
547#define REG_8F (REG_82 + 1)
548#define REG_C0 (REG_8F + 1)
549#define REG_C1 (REG_C0 + 1)
550#define REG_C6 (REG_C1 + 1)
551#define REG_C7 (REG_C6 + 1)
552#define REG_D0 (REG_C7 + 1)
553#define REG_D1 (REG_D0 + 1)
554#define REG_D2 (REG_D1 + 1)
555#define REG_D3 (REG_D2 + 1)
556#define REG_F6 (REG_D3 + 1)
557#define REG_F7 (REG_F6 + 1)
558#define REG_FE (REG_F7 + 1)
559#define REG_FF (REG_FE + 1)
560#define REG_0F00 (REG_FF + 1)
561#define REG_0F01 (REG_0F00 + 1)
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L		 562#define REG_0F0D (REG_0F01 + 1)
563#define REG_0F18 (REG_0F0D + 1)
1ceb70f8
L		 564#define REG_0F71 (REG_0F18 + 1)
565#define REG_0F72 (REG_0F71 + 1)
566#define REG_0F73 (REG_0F72 + 1)
567#define REG_0FA6 (REG_0F73 + 1)
568#define REG_0FA7 (REG_0FA6 + 1)
569#define REG_0FAE (REG_0FA7 + 1)
570#define REG_0FBA (REG_0FAE + 1)
571#define REG_0FC7 (REG_0FBA + 1)
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L		 572#define REG_VEX_71 (REG_0FC7 + 1)
573#define REG_VEX_72 (REG_VEX_71 + 1)
574#define REG_VEX_73 (REG_VEX_72 + 1)
575#define REG_VEX_AE (REG_VEX_73 + 1)
1ceb70f8
L		 576
577#define MOD_8D 0
92fddf8e 578#define MOD_0F01_REG_0 (MOD_8D + 1)
1ceb70f8
L		 579#define MOD_0F01_REG_1 (MOD_0F01_REG_0 + 1)
580#define MOD_0F01_REG_2 (MOD_0F01_REG_1 + 1)
581#define MOD_0F01_REG_3 (MOD_0F01_REG_2 + 1)
582#define MOD_0F01_REG_7 (MOD_0F01_REG_3 + 1)
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L		 583#define MOD_0F12_PREFIX_0 (MOD_0F01_REG_7 + 1)
584#define MOD_0F13 (MOD_0F12_PREFIX_0 + 1)
585#define MOD_0F16_PREFIX_0 (MOD_0F13 + 1)
586#define MOD_0F17 (MOD_0F16_PREFIX_0 + 1)
587#define MOD_0F18_REG_0 (MOD_0F17 + 1)
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L		 588#define MOD_0F18_REG_1 (MOD_0F18_REG_0 + 1)
589#define MOD_0F18_REG_2 (MOD_0F18_REG_1 + 1)
590#define MOD_0F18_REG_3 (MOD_0F18_REG_2 + 1)
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L		 591#define MOD_0F20 (MOD_0F18_REG_3 + 1)
592#define MOD_0F21 (MOD_0F20 + 1)
593#define MOD_0F22 (MOD_0F21 + 1)
594#define MOD_0F23 (MOD_0F22 + 1)
595#define MOD_0F24 (MOD_0F23 + 1)
596#define MOD_0F26 (MOD_0F24 + 1)
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L		 597#define MOD_0F2B_PREFIX_0 (MOD_0F26 + 1)
598#define MOD_0F2B_PREFIX_1 (MOD_0F2B_PREFIX_0 + 1)
599#define MOD_0F2B_PREFIX_2 (MOD_0F2B_PREFIX_1 + 1)
600#define MOD_0F2B_PREFIX_3 (MOD_0F2B_PREFIX_2 + 1)
601#define MOD_0F51 (MOD_0F2B_PREFIX_3 + 1)
602#define MOD_0F71_REG_2 (MOD_0F51 + 1)
1ceb70f8
L		 603#define MOD_0F71_REG_4 (MOD_0F71_REG_2 + 1)
604#define MOD_0F71_REG_6 (MOD_0F71_REG_4 + 1)
605#define MOD_0F72_REG_2 (MOD_0F71_REG_6 + 1)
606#define MOD_0F72_REG_4 (MOD_0F72_REG_2 + 1)
607#define MOD_0F72_REG_6 (MOD_0F72_REG_4 + 1)
608#define MOD_0F73_REG_2 (MOD_0F72_REG_6 + 1)
609#define MOD_0F73_REG_3 (MOD_0F73_REG_2 + 1)
610#define MOD_0F73_REG_6 (MOD_0F73_REG_3 + 1)
611#define MOD_0F73_REG_7 (MOD_0F73_REG_6 + 1)
612#define MOD_0FAE_REG_0 (MOD_0F73_REG_7 + 1)
613#define MOD_0FAE_REG_1 (MOD_0FAE_REG_0 + 1)
614#define MOD_0FAE_REG_2 (MOD_0FAE_REG_1 + 1)
615#define MOD_0FAE_REG_3 (MOD_0FAE_REG_2 + 1)
475a2301
L		 616#define MOD_0FAE_REG_4 (MOD_0FAE_REG_3 + 1)
617#define MOD_0FAE_REG_5 (MOD_0FAE_REG_4 + 1)
1ceb70f8
L		 618#define MOD_0FAE_REG_6 (MOD_0FAE_REG_5 + 1)
619#define MOD_0FAE_REG_7 (MOD_0FAE_REG_6 + 1)
92fddf8e
L		 620#define MOD_0FB2 (MOD_0FAE_REG_7 + 1)
621#define MOD_0FB4 (MOD_0FB2 + 1)
622#define MOD_0FB5 (MOD_0FB4 + 1)
623#define MOD_0FC7_REG_6 (MOD_0FB5 + 1)
1ceb70f8 624#define MOD_0FC7_REG_7 (MOD_0FC7_REG_6 + 1)
75c135a8
L		 625#define MOD_0FD7 (MOD_0FC7_REG_7 + 1)
626#define MOD_0FE7_PREFIX_2 (MOD_0FD7 + 1)
627#define MOD_0FF0_PREFIX_3 (MOD_0FE7_PREFIX_2 + 1)
628#define MOD_0F382A_PREFIX_2 (MOD_0FF0_PREFIX_3 + 1)
629#define MOD_62_32BIT (MOD_0F382A_PREFIX_2 + 1)
1ceb70f8
L		 630#define MOD_C4_32BIT (MOD_62_32BIT + 1)
631#define MOD_C5_32BIT (MOD_C4_32BIT + 1)
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L		 632#define MOD_VEX_12_PREFIX_0 (MOD_C5_32BIT + 1)
633#define MOD_VEX_13 (MOD_VEX_12_PREFIX_0 + 1)
634#define MOD_VEX_16_PREFIX_0 (MOD_VEX_13 + 1)
635#define MOD_VEX_17 (MOD_VEX_16_PREFIX_0 + 1)
636#define MOD_VEX_2B (MOD_VEX_17 + 1)
637#define MOD_VEX_51 (MOD_VEX_2B + 1)
638#define MOD_VEX_71_REG_2 (MOD_VEX_51 + 1)
639#define MOD_VEX_71_REG_4 (MOD_VEX_71_REG_2 + 1)
640#define MOD_VEX_71_REG_6 (MOD_VEX_71_REG_4 + 1)
641#define MOD_VEX_72_REG_2 (MOD_VEX_71_REG_6 + 1)
642#define MOD_VEX_72_REG_4 (MOD_VEX_72_REG_2 + 1)
643#define MOD_VEX_72_REG_6 (MOD_VEX_72_REG_4 + 1)
644#define MOD_VEX_73_REG_2 (MOD_VEX_72_REG_6 + 1)
645#define MOD_VEX_73_REG_3 (MOD_VEX_73_REG_2 + 1)
646#define MOD_VEX_73_REG_6 (MOD_VEX_73_REG_3 + 1)
647#define MOD_VEX_73_REG_7 (MOD_VEX_73_REG_6 + 1)
648#define MOD_VEX_AE_REG_2 (MOD_VEX_73_REG_7 + 1)
649#define MOD_VEX_AE_REG_3 (MOD_VEX_AE_REG_2 + 1)
650#define MOD_VEX_D7_PREFIX_2 (MOD_VEX_AE_REG_3 + 1)
651#define MOD_VEX_E7_PREFIX_2 (MOD_VEX_D7_PREFIX_2 + 1)
652#define MOD_VEX_F0_PREFIX_3 (MOD_VEX_E7_PREFIX_2 + 1)
653#define MOD_VEX_3818_PREFIX_2 (MOD_VEX_F0_PREFIX_3 + 1)
654#define MOD_VEX_3819_PREFIX_2 (MOD_VEX_3818_PREFIX_2 + 1)
655#define MOD_VEX_381A_PREFIX_2 (MOD_VEX_3819_PREFIX_2 + 1)
656#define MOD_VEX_382A_PREFIX_2 (MOD_VEX_381A_PREFIX_2 + 1)
657#define MOD_VEX_382C_PREFIX_2 (MOD_VEX_382A_PREFIX_2 + 1)
658#define MOD_VEX_382D_PREFIX_2 (MOD_VEX_382C_PREFIX_2 + 1)
659#define MOD_VEX_382E_PREFIX_2 (MOD_VEX_382D_PREFIX_2 + 1)
660#define MOD_VEX_382F_PREFIX_2 (MOD_VEX_382E_PREFIX_2 + 1)
1ceb70f8
L		 661
662#define RM_0F01_REG_0 0
663#define RM_0F01_REG_1 (RM_0F01_REG_0 + 1)
475a2301
L		 664#define RM_0F01_REG_2 (RM_0F01_REG_1 + 1)
665#define RM_0F01_REG_3 (RM_0F01_REG_2 + 1)
1ceb70f8
L		 666#define RM_0F01_REG_7 (RM_0F01_REG_3 + 1)
667#define RM_0FAE_REG_5 (RM_0F01_REG_7 + 1)
668#define RM_0FAE_REG_6 (RM_0FAE_REG_5 + 1)
669#define RM_0FAE_REG_7 (RM_0FAE_REG_6 + 1)
670
671#define PREFIX_90 0
672#define PREFIX_0F10 (PREFIX_90 + 1)
673#define PREFIX_0F11 (PREFIX_0F10 + 1)
674#define PREFIX_0F12 (PREFIX_0F11 + 1)
675#define PREFIX_0F16 (PREFIX_0F12 + 1)
676#define PREFIX_0F2A (PREFIX_0F16 + 1)
677#define PREFIX_0F2B (PREFIX_0F2A + 1)
678#define PREFIX_0F2C (PREFIX_0F2B + 1)
679#define PREFIX_0F2D (PREFIX_0F2C + 1)
680#define PREFIX_0F2E (PREFIX_0F2D + 1)
681#define PREFIX_0F2F (PREFIX_0F2E + 1)
682#define PREFIX_0F51 (PREFIX_0F2F + 1)
683#define PREFIX_0F52 (PREFIX_0F51 + 1)
684#define PREFIX_0F53 (PREFIX_0F52 + 1)
685#define PREFIX_0F58 (PREFIX_0F53 + 1)
686#define PREFIX_0F59 (PREFIX_0F58 + 1)
687#define PREFIX_0F5A (PREFIX_0F59 + 1)
688#define PREFIX_0F5B (PREFIX_0F5A + 1)
689#define PREFIX_0F5C (PREFIX_0F5B + 1)
690#define PREFIX_0F5D (PREFIX_0F5C + 1)
691#define PREFIX_0F5E (PREFIX_0F5D + 1)
692#define PREFIX_0F5F (PREFIX_0F5E + 1)
693#define PREFIX_0F60 (PREFIX_0F5F + 1)
694#define PREFIX_0F61 (PREFIX_0F60 + 1)
695#define PREFIX_0F62 (PREFIX_0F61 + 1)
696#define PREFIX_0F6C (PREFIX_0F62 + 1)
697#define PREFIX_0F6D (PREFIX_0F6C + 1)
698#define PREFIX_0F6F (PREFIX_0F6D + 1)
699#define PREFIX_0F70 (PREFIX_0F6F + 1)
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L		 700#define PREFIX_0F73_REG_3 (PREFIX_0F70 + 1)
701#define PREFIX_0F73_REG_7 (PREFIX_0F73_REG_3 + 1)
702#define PREFIX_0F78 (PREFIX_0F73_REG_7 + 1)
1ceb70f8
L		 703#define PREFIX_0F79 (PREFIX_0F78 + 1)
704#define PREFIX_0F7C (PREFIX_0F79 + 1)
705#define PREFIX_0F7D (PREFIX_0F7C + 1)
706#define PREFIX_0F7E (PREFIX_0F7D + 1)
707#define PREFIX_0F7F (PREFIX_0F7E + 1)
708#define PREFIX_0FB8 (PREFIX_0F7F + 1)
709#define PREFIX_0FBD (PREFIX_0FB8 + 1)
710#define PREFIX_0FC2 (PREFIX_0FBD + 1)
4ee52178
L		 711#define PREFIX_0FC3 (PREFIX_0FC2 + 1)
712#define PREFIX_0FC7_REG_6 (PREFIX_0FC3 + 1)
92fddf8e 713#define PREFIX_0FD0 (PREFIX_0FC7_REG_6 + 1)
1ceb70f8
L		 714#define PREFIX_0FD6 (PREFIX_0FD0 + 1)
715#define PREFIX_0FE6 (PREFIX_0FD6 + 1)
716#define PREFIX_0FE7 (PREFIX_0FE6 + 1)
717#define PREFIX_0FF0 (PREFIX_0FE7 + 1)
718#define PREFIX_0FF7 (PREFIX_0FF0 + 1)
719#define PREFIX_0F3810 (PREFIX_0FF7 + 1)
720#define PREFIX_0F3814 (PREFIX_0F3810 + 1)
721#define PREFIX_0F3815 (PREFIX_0F3814 + 1)
722#define PREFIX_0F3817 (PREFIX_0F3815 + 1)
723#define PREFIX_0F3820 (PREFIX_0F3817 + 1)
724#define PREFIX_0F3821 (PREFIX_0F3820 + 1)
725#define PREFIX_0F3822 (PREFIX_0F3821 + 1)
726#define PREFIX_0F3823 (PREFIX_0F3822 + 1)
727#define PREFIX_0F3824 (PREFIX_0F3823 + 1)
728#define PREFIX_0F3825 (PREFIX_0F3824 + 1)
729#define PREFIX_0F3828 (PREFIX_0F3825 + 1)
730#define PREFIX_0F3829 (PREFIX_0F3828 + 1)
731#define PREFIX_0F382A (PREFIX_0F3829 + 1)
732#define PREFIX_0F382B (PREFIX_0F382A + 1)
733#define PREFIX_0F3830 (PREFIX_0F382B + 1)
734#define PREFIX_0F3831 (PREFIX_0F3830 + 1)
735#define PREFIX_0F3832 (PREFIX_0F3831 + 1)
736#define PREFIX_0F3833 (PREFIX_0F3832 + 1)
737#define PREFIX_0F3834 (PREFIX_0F3833 + 1)
738#define PREFIX_0F3835 (PREFIX_0F3834 + 1)
739#define PREFIX_0F3837 (PREFIX_0F3835 + 1)
740#define PREFIX_0F3838 (PREFIX_0F3837 + 1)
741#define PREFIX_0F3839 (PREFIX_0F3838 + 1)
742#define PREFIX_0F383A (PREFIX_0F3839 + 1)
743#define PREFIX_0F383B (PREFIX_0F383A + 1)
744#define PREFIX_0F383C (PREFIX_0F383B + 1)
745#define PREFIX_0F383D (PREFIX_0F383C + 1)
746#define PREFIX_0F383E (PREFIX_0F383D + 1)
747#define PREFIX_0F383F (PREFIX_0F383E + 1)
748#define PREFIX_0F3840 (PREFIX_0F383F + 1)
749#define PREFIX_0F3841 (PREFIX_0F3840 + 1)
f1f8f695
L		 750#define PREFIX_0F3880 (PREFIX_0F3841 + 1)
751#define PREFIX_0F3881 (PREFIX_0F3880 + 1)
752#define PREFIX_0F38DB (PREFIX_0F3881 + 1)
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L		 753#define PREFIX_0F38DC (PREFIX_0F38DB + 1)
754#define PREFIX_0F38DD (PREFIX_0F38DC + 1)
755#define PREFIX_0F38DE (PREFIX_0F38DD + 1)
756#define PREFIX_0F38DF (PREFIX_0F38DE + 1)
757#define PREFIX_0F38F0 (PREFIX_0F38DF + 1)
1ceb70f8
L		 758#define PREFIX_0F38F1 (PREFIX_0F38F0 + 1)
759#define PREFIX_0F3A08 (PREFIX_0F38F1 + 1)
760#define PREFIX_0F3A09 (PREFIX_0F3A08 + 1)
761#define PREFIX_0F3A0A (PREFIX_0F3A09 + 1)
762#define PREFIX_0F3A0B (PREFIX_0F3A0A + 1)
763#define PREFIX_0F3A0C (PREFIX_0F3A0B + 1)
764#define PREFIX_0F3A0D (PREFIX_0F3A0C + 1)
765#define PREFIX_0F3A0E (PREFIX_0F3A0D + 1)
766#define PREFIX_0F3A14 (PREFIX_0F3A0E + 1)
767#define PREFIX_0F3A15 (PREFIX_0F3A14 + 1)
768#define PREFIX_0F3A16 (PREFIX_0F3A15 + 1)
769#define PREFIX_0F3A17 (PREFIX_0F3A16 + 1)
770#define PREFIX_0F3A20 (PREFIX_0F3A17 + 1)
771#define PREFIX_0F3A21 (PREFIX_0F3A20 + 1)
772#define PREFIX_0F3A22 (PREFIX_0F3A21 + 1)
773#define PREFIX_0F3A40 (PREFIX_0F3A22 + 1)
774#define PREFIX_0F3A41 (PREFIX_0F3A40 + 1)
775#define PREFIX_0F3A42 (PREFIX_0F3A41 + 1)
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L		 776#define PREFIX_0F3A44 (PREFIX_0F3A42 + 1)
777#define PREFIX_0F3A60 (PREFIX_0F3A44 + 1)
1ceb70f8
L		 778#define PREFIX_0F3A61 (PREFIX_0F3A60 + 1)
779#define PREFIX_0F3A62 (PREFIX_0F3A61 + 1)
780#define PREFIX_0F3A63 (PREFIX_0F3A62 + 1)
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L		 781#define PREFIX_0F3ADF (PREFIX_0F3A63 + 1)
782#define PREFIX_VEX_10 (PREFIX_0F3ADF + 1)
783#define PREFIX_VEX_11 (PREFIX_VEX_10 + 1)
784#define PREFIX_VEX_12 (PREFIX_VEX_11 + 1)
785#define PREFIX_VEX_16 (PREFIX_VEX_12 + 1)
786#define PREFIX_VEX_2A (PREFIX_VEX_16 + 1)
787#define PREFIX_VEX_2C (PREFIX_VEX_2A + 1)
788#define PREFIX_VEX_2D (PREFIX_VEX_2C + 1)
789#define PREFIX_VEX_2E (PREFIX_VEX_2D + 1)
790#define PREFIX_VEX_2F (PREFIX_VEX_2E + 1)
791#define PREFIX_VEX_51 (PREFIX_VEX_2F + 1)
792#define PREFIX_VEX_52 (PREFIX_VEX_51 + 1)
793#define PREFIX_VEX_53 (PREFIX_VEX_52 + 1)
794#define PREFIX_VEX_58 (PREFIX_VEX_53 + 1)
795#define PREFIX_VEX_59 (PREFIX_VEX_58 + 1)
796#define PREFIX_VEX_5A (PREFIX_VEX_59 + 1)
797#define PREFIX_VEX_5B (PREFIX_VEX_5A + 1)
798#define PREFIX_VEX_5C (PREFIX_VEX_5B + 1)
799#define PREFIX_VEX_5D (PREFIX_VEX_5C + 1)
800#define PREFIX_VEX_5E (PREFIX_VEX_5D + 1)
801#define PREFIX_VEX_5F (PREFIX_VEX_5E + 1)
802#define PREFIX_VEX_60 (PREFIX_VEX_5F + 1)
803#define PREFIX_VEX_61 (PREFIX_VEX_60 + 1)
804#define PREFIX_VEX_62 (PREFIX_VEX_61 + 1)
805#define PREFIX_VEX_63 (PREFIX_VEX_62 + 1)
806#define PREFIX_VEX_64 (PREFIX_VEX_63 + 1)
807#define PREFIX_VEX_65 (PREFIX_VEX_64 + 1)
808#define PREFIX_VEX_66 (PREFIX_VEX_65 + 1)
809#define PREFIX_VEX_67 (PREFIX_VEX_66 + 1)
810#define PREFIX_VEX_68 (PREFIX_VEX_67 + 1)
811#define PREFIX_VEX_69 (PREFIX_VEX_68 + 1)
812#define PREFIX_VEX_6A (PREFIX_VEX_69 + 1)
813#define PREFIX_VEX_6B (PREFIX_VEX_6A + 1)
814#define PREFIX_VEX_6C (PREFIX_VEX_6B + 1)
815#define PREFIX_VEX_6D (PREFIX_VEX_6C + 1)
816#define PREFIX_VEX_6E (PREFIX_VEX_6D + 1)
817#define PREFIX_VEX_6F (PREFIX_VEX_6E + 1)
818#define PREFIX_VEX_70 (PREFIX_VEX_6F + 1)
819#define PREFIX_VEX_71_REG_2 (PREFIX_VEX_70 + 1)
820#define PREFIX_VEX_71_REG_4 (PREFIX_VEX_71_REG_2 + 1)
821#define PREFIX_VEX_71_REG_6 (PREFIX_VEX_71_REG_4 + 1)
822#define PREFIX_VEX_72_REG_2 (PREFIX_VEX_71_REG_6 + 1)
823#define PREFIX_VEX_72_REG_4 (PREFIX_VEX_72_REG_2 + 1)
824#define PREFIX_VEX_72_REG_6 (PREFIX_VEX_72_REG_4 + 1)
825#define PREFIX_VEX_73_REG_2 (PREFIX_VEX_72_REG_6 + 1)
826#define PREFIX_VEX_73_REG_3 (PREFIX_VEX_73_REG_2 + 1)
827#define PREFIX_VEX_73_REG_6 (PREFIX_VEX_73_REG_3 + 1)
828#define PREFIX_VEX_73_REG_7 (PREFIX_VEX_73_REG_6 + 1)
829#define PREFIX_VEX_74 (PREFIX_VEX_73_REG_7 + 1)
830#define PREFIX_VEX_75 (PREFIX_VEX_74 + 1)
831#define PREFIX_VEX_76 (PREFIX_VEX_75 + 1)
832#define PREFIX_VEX_77 (PREFIX_VEX_76 + 1)
833#define PREFIX_VEX_7C (PREFIX_VEX_77 + 1)
834#define PREFIX_VEX_7D (PREFIX_VEX_7C + 1)
835#define PREFIX_VEX_7E (PREFIX_VEX_7D + 1)
836#define PREFIX_VEX_7F (PREFIX_VEX_7E + 1)
837#define PREFIX_VEX_C2 (PREFIX_VEX_7F + 1)
838#define PREFIX_VEX_C4 (PREFIX_VEX_C2 + 1)
839#define PREFIX_VEX_C5 (PREFIX_VEX_C4 + 1)
840#define PREFIX_VEX_D0 (PREFIX_VEX_C5 + 1)
841#define PREFIX_VEX_D1 (PREFIX_VEX_D0 + 1)
842#define PREFIX_VEX_D2 (PREFIX_VEX_D1 + 1)
843#define PREFIX_VEX_D3 (PREFIX_VEX_D2 + 1)
844#define PREFIX_VEX_D4 (PREFIX_VEX_D3 + 1)
845#define PREFIX_VEX_D5 (PREFIX_VEX_D4 + 1)
846#define PREFIX_VEX_D6 (PREFIX_VEX_D5 + 1)
847#define PREFIX_VEX_D7 (PREFIX_VEX_D6 + 1)
848#define PREFIX_VEX_D8 (PREFIX_VEX_D7 + 1)
849#define PREFIX_VEX_D9 (PREFIX_VEX_D8 + 1)
850#define PREFIX_VEX_DA (PREFIX_VEX_D9 + 1)
851#define PREFIX_VEX_DB (PREFIX_VEX_DA + 1)
852#define PREFIX_VEX_DC (PREFIX_VEX_DB + 1)
853#define PREFIX_VEX_DD (PREFIX_VEX_DC + 1)
854#define PREFIX_VEX_DE (PREFIX_VEX_DD + 1)
855#define PREFIX_VEX_DF (PREFIX_VEX_DE + 1)
856#define PREFIX_VEX_E0 (PREFIX_VEX_DF + 1)
857#define PREFIX_VEX_E1 (PREFIX_VEX_E0 + 1)
858#define PREFIX_VEX_E2 (PREFIX_VEX_E1 + 1)
859#define PREFIX_VEX_E3 (PREFIX_VEX_E2 + 1)
860#define PREFIX_VEX_E4 (PREFIX_VEX_E3 + 1)
861#define PREFIX_VEX_E5 (PREFIX_VEX_E4 + 1)
862#define PREFIX_VEX_E6 (PREFIX_VEX_E5 + 1)
863#define PREFIX_VEX_E7 (PREFIX_VEX_E6 + 1)
864#define PREFIX_VEX_E8 (PREFIX_VEX_E7 + 1)
865#define PREFIX_VEX_E9 (PREFIX_VEX_E8 + 1)
866#define PREFIX_VEX_EA (PREFIX_VEX_E9 + 1)
867#define PREFIX_VEX_EB (PREFIX_VEX_EA + 1)
868#define PREFIX_VEX_EC (PREFIX_VEX_EB + 1)
869#define PREFIX_VEX_ED (PREFIX_VEX_EC + 1)
870#define PREFIX_VEX_EE (PREFIX_VEX_ED + 1)
871#define PREFIX_VEX_EF (PREFIX_VEX_EE + 1)
872#define PREFIX_VEX_F0 (PREFIX_VEX_EF + 1)
873#define PREFIX_VEX_F1 (PREFIX_VEX_F0 + 1)
874#define PREFIX_VEX_F2 (PREFIX_VEX_F1 + 1)
875#define PREFIX_VEX_F3 (PREFIX_VEX_F2 + 1)
876#define PREFIX_VEX_F4 (PREFIX_VEX_F3 + 1)
877#define PREFIX_VEX_F5 (PREFIX_VEX_F4 + 1)
878#define PREFIX_VEX_F6 (PREFIX_VEX_F5 + 1)
879#define PREFIX_VEX_F7 (PREFIX_VEX_F6 + 1)
880#define PREFIX_VEX_F8 (PREFIX_VEX_F7 + 1)
881#define PREFIX_VEX_F9 (PREFIX_VEX_F8 + 1)
882#define PREFIX_VEX_FA (PREFIX_VEX_F9 + 1)
883#define PREFIX_VEX_FB (PREFIX_VEX_FA + 1)
884#define PREFIX_VEX_FC (PREFIX_VEX_FB + 1)
885#define PREFIX_VEX_FD (PREFIX_VEX_FC + 1)
886#define PREFIX_VEX_FE (PREFIX_VEX_FD + 1)
06c8514a
L		 887#define PREFIX_VEX_3800 (PREFIX_VEX_FE + 1)
888#define PREFIX_VEX_3801 (PREFIX_VEX_3800 + 1)
889#define PREFIX_VEX_3802 (PREFIX_VEX_3801 + 1)
890#define PREFIX_VEX_3803 (PREFIX_VEX_3802 + 1)
891#define PREFIX_VEX_3804 (PREFIX_VEX_3803 + 1)
892#define PREFIX_VEX_3805 (PREFIX_VEX_3804 + 1)
893#define PREFIX_VEX_3806 (PREFIX_VEX_3805 + 1)
894#define PREFIX_VEX_3807 (PREFIX_VEX_3806 + 1)
895#define PREFIX_VEX_3808 (PREFIX_VEX_3807 + 1)
896#define PREFIX_VEX_3809 (PREFIX_VEX_3808 + 1)
897#define PREFIX_VEX_380A (PREFIX_VEX_3809 + 1)
898#define PREFIX_VEX_380B (PREFIX_VEX_380A + 1)
899#define PREFIX_VEX_380C (PREFIX_VEX_380B + 1)
900#define PREFIX_VEX_380D (PREFIX_VEX_380C + 1)
901#define PREFIX_VEX_380E (PREFIX_VEX_380D + 1)
902#define PREFIX_VEX_380F (PREFIX_VEX_380E + 1)
903#define PREFIX_VEX_3817 (PREFIX_VEX_380F + 1)
904#define PREFIX_VEX_3818 (PREFIX_VEX_3817 + 1)
905#define PREFIX_VEX_3819 (PREFIX_VEX_3818 + 1)
906#define PREFIX_VEX_381A (PREFIX_VEX_3819 + 1)
907#define PREFIX_VEX_381C (PREFIX_VEX_381A + 1)
908#define PREFIX_VEX_381D (PREFIX_VEX_381C + 1)
909#define PREFIX_VEX_381E (PREFIX_VEX_381D + 1)
910#define PREFIX_VEX_3820 (PREFIX_VEX_381E + 1)
911#define PREFIX_VEX_3821 (PREFIX_VEX_3820 + 1)
912#define PREFIX_VEX_3822 (PREFIX_VEX_3821 + 1)
913#define PREFIX_VEX_3823 (PREFIX_VEX_3822 + 1)
914#define PREFIX_VEX_3824 (PREFIX_VEX_3823 + 1)
915#define PREFIX_VEX_3825 (PREFIX_VEX_3824 + 1)
916#define PREFIX_VEX_3828 (PREFIX_VEX_3825 + 1)
917#define PREFIX_VEX_3829 (PREFIX_VEX_3828 + 1)
918#define PREFIX_VEX_382A (PREFIX_VEX_3829 + 1)
919#define PREFIX_VEX_382B (PREFIX_VEX_382A + 1)
920#define PREFIX_VEX_382C (PREFIX_VEX_382B + 1)
921#define PREFIX_VEX_382D (PREFIX_VEX_382C + 1)
922#define PREFIX_VEX_382E (PREFIX_VEX_382D + 1)
923#define PREFIX_VEX_382F (PREFIX_VEX_382E + 1)
924#define PREFIX_VEX_3830 (PREFIX_VEX_382F + 1)
925#define PREFIX_VEX_3831 (PREFIX_VEX_3830 + 1)
926#define PREFIX_VEX_3832 (PREFIX_VEX_3831 + 1)
927#define PREFIX_VEX_3833 (PREFIX_VEX_3832 + 1)
928#define PREFIX_VEX_3834 (PREFIX_VEX_3833 + 1)
929#define PREFIX_VEX_3835 (PREFIX_VEX_3834 + 1)
930#define PREFIX_VEX_3837 (PREFIX_VEX_3835 + 1)
931#define PREFIX_VEX_3838 (PREFIX_VEX_3837 + 1)
932#define PREFIX_VEX_3839 (PREFIX_VEX_3838 + 1)
933#define PREFIX_VEX_383A (PREFIX_VEX_3839 + 1)
934#define PREFIX_VEX_383B (PREFIX_VEX_383A + 1)
935#define PREFIX_VEX_383C (PREFIX_VEX_383B + 1)
936#define PREFIX_VEX_383D (PREFIX_VEX_383C + 1)
937#define PREFIX_VEX_383E (PREFIX_VEX_383D + 1)
938#define PREFIX_VEX_383F (PREFIX_VEX_383E + 1)
939#define PREFIX_VEX_3840 (PREFIX_VEX_383F + 1)
940#define PREFIX_VEX_3841 (PREFIX_VEX_3840 + 1)
941#define PREFIX_VEX_3A04 (PREFIX_VEX_3841 + 1)
942#define PREFIX_VEX_3A05 (PREFIX_VEX_3A04 + 1)
943#define PREFIX_VEX_3A06 (PREFIX_VEX_3A05 + 1)
944#define PREFIX_VEX_3A08 (PREFIX_VEX_3A06 + 1)
945#define PREFIX_VEX_3A09 (PREFIX_VEX_3A08 + 1)
946#define PREFIX_VEX_3A0A (PREFIX_VEX_3A09 + 1)
947#define PREFIX_VEX_3A0B (PREFIX_VEX_3A0A + 1)
948#define PREFIX_VEX_3A0C (PREFIX_VEX_3A0B + 1)
949#define PREFIX_VEX_3A0D (PREFIX_VEX_3A0C + 1)
950#define PREFIX_VEX_3A0E (PREFIX_VEX_3A0D + 1)
951#define PREFIX_VEX_3A0F (PREFIX_VEX_3A0E + 1)
952#define PREFIX_VEX_3A14 (PREFIX_VEX_3A0F + 1)
953#define PREFIX_VEX_3A15 (PREFIX_VEX_3A14 + 1)
954#define PREFIX_VEX_3A16 (PREFIX_VEX_3A15 + 1)
955#define PREFIX_VEX_3A17 (PREFIX_VEX_3A16 + 1)
956#define PREFIX_VEX_3A18 (PREFIX_VEX_3A17 + 1)
957#define PREFIX_VEX_3A19 (PREFIX_VEX_3A18 + 1)
958#define PREFIX_VEX_3A20 (PREFIX_VEX_3A19 + 1)
959#define PREFIX_VEX_3A21 (PREFIX_VEX_3A20 + 1)
960#define PREFIX_VEX_3A22 (PREFIX_VEX_3A21 + 1)
961#define PREFIX_VEX_3A40 (PREFIX_VEX_3A22 + 1)
962#define PREFIX_VEX_3A41 (PREFIX_VEX_3A40 + 1)
963#define PREFIX_VEX_3A42 (PREFIX_VEX_3A41 + 1)
964#define PREFIX_VEX_3A48 (PREFIX_VEX_3A42 + 1)
965#define PREFIX_VEX_3A49 (PREFIX_VEX_3A48 + 1)
966#define PREFIX_VEX_3A4A (PREFIX_VEX_3A49 + 1)
967#define PREFIX_VEX_3A4B (PREFIX_VEX_3A4A + 1)
968#define PREFIX_VEX_3A4C (PREFIX_VEX_3A4B + 1)
969#define PREFIX_VEX_3A5C (PREFIX_VEX_3A4C + 1)
970#define PREFIX_VEX_3A5D (PREFIX_VEX_3A5C + 1)
971#define PREFIX_VEX_3A5E (PREFIX_VEX_3A5D + 1)
972#define PREFIX_VEX_3A5F (PREFIX_VEX_3A5E + 1)
973#define PREFIX_VEX_3A60 (PREFIX_VEX_3A5F + 1)
974#define PREFIX_VEX_3A61 (PREFIX_VEX_3A60 + 1)
975#define PREFIX_VEX_3A62 (PREFIX_VEX_3A61 + 1)
976#define PREFIX_VEX_3A63 (PREFIX_VEX_3A62 + 1)
977#define PREFIX_VEX_3A68 (PREFIX_VEX_3A63 + 1)
978#define PREFIX_VEX_3A69 (PREFIX_VEX_3A68 + 1)
979#define PREFIX_VEX_3A6A (PREFIX_VEX_3A69 + 1)
980#define PREFIX_VEX_3A6B (PREFIX_VEX_3A6A + 1)
981#define PREFIX_VEX_3A6C (PREFIX_VEX_3A6B + 1)
982#define PREFIX_VEX_3A6D (PREFIX_VEX_3A6C + 1)
983#define PREFIX_VEX_3A6E (PREFIX_VEX_3A6D + 1)
984#define PREFIX_VEX_3A6F (PREFIX_VEX_3A6E + 1)
985#define PREFIX_VEX_3A78 (PREFIX_VEX_3A6F + 1)
986#define PREFIX_VEX_3A79 (PREFIX_VEX_3A78 + 1)
987#define PREFIX_VEX_3A7A (PREFIX_VEX_3A79 + 1)
988#define PREFIX_VEX_3A7B (PREFIX_VEX_3A7A + 1)
989#define PREFIX_VEX_3A7C (PREFIX_VEX_3A7B + 1)
990#define PREFIX_VEX_3A7D (PREFIX_VEX_3A7C + 1)
991#define PREFIX_VEX_3A7E (PREFIX_VEX_3A7D + 1)
992#define PREFIX_VEX_3A7F (PREFIX_VEX_3A7E + 1)
4e7d34a6
L		 993
994#define X86_64_06 0
995#define X86_64_07 (X86_64_06 + 1)
996#define X86_64_0D (X86_64_07 + 1)
997#define X86_64_16 (X86_64_0D + 1)
998#define X86_64_17 (X86_64_16 + 1)
999#define X86_64_1E (X86_64_17 + 1)
1000#define X86_64_1F (X86_64_1E + 1)
1001#define X86_64_27 (X86_64_1F + 1)
1002#define X86_64_2F (X86_64_27 + 1)
1003#define X86_64_37 (X86_64_2F + 1)
1004#define X86_64_3F (X86_64_37 + 1)
1005#define X86_64_60 (X86_64_3F + 1)
1006#define X86_64_61 (X86_64_60 + 1)
1007#define X86_64_62 (X86_64_61 + 1)
1008#define X86_64_63 (X86_64_62 + 1)
1009#define X86_64_6D (X86_64_63 + 1)
1010#define X86_64_6F (X86_64_6D + 1)
1011#define X86_64_9A (X86_64_6F + 1)
1012#define X86_64_C4 (X86_64_9A + 1)
1013#define X86_64_C5 (X86_64_C4 + 1)
1014#define X86_64_CE (X86_64_C5 + 1)
1015#define X86_64_D4 (X86_64_CE + 1)
1016#define X86_64_D5 (X86_64_D4 + 1)
1017#define X86_64_EA (X86_64_D5 + 1)
1018#define X86_64_0F01_REG_0 (X86_64_EA + 1)
1019#define X86_64_0F01_REG_1 (X86_64_0F01_REG_0 + 1)
1020#define X86_64_0F01_REG_2 (X86_64_0F01_REG_1 + 1)
1021#define X86_64_0F01_REG_3 (X86_64_0F01_REG_2 + 1)
1022
1023#define THREE_BYTE_0F24 0
1024#define THREE_BYTE_0F25 (THREE_BYTE_0F24 + 1)
1025#define THREE_BYTE_0F38 (THREE_BYTE_0F25 + 1)
1026#define THREE_BYTE_0F3A (THREE_BYTE_0F38 + 1)
1027#define THREE_BYTE_0F7A (THREE_BYTE_0F3A + 1)
89b66d55 1028#define THREE_BYTE_0F7B (THREE_BYTE_0F7A + 1)
4e7d34a6 1029
c0f3af97
L		 1030#define VEX_0F 0
1031#define VEX_0F38 (VEX_0F + 1)
1032#define VEX_0F3A (VEX_0F38 + 1)
1033
1034#define VEX_LEN_10_P_1 0
1035#define VEX_LEN_10_P_3 (VEX_LEN_10_P_1 + 1)
1036#define VEX_LEN_11_P_1 (VEX_LEN_10_P_3 + 1)
1037#define VEX_LEN_11_P_3 (VEX_LEN_11_P_1 + 1)
1038#define VEX_LEN_12_P_0_M_0 (VEX_LEN_11_P_3 + 1)
1039#define VEX_LEN_12_P_0_M_1 (VEX_LEN_12_P_0_M_0 + 1)
1040#define VEX_LEN_12_P_2 (VEX_LEN_12_P_0_M_1 + 1)
1041#define VEX_LEN_13_M_0 (VEX_LEN_12_P_2 + 1)
1042#define VEX_LEN_16_P_0_M_0 (VEX_LEN_13_M_0 + 1)
1043#define VEX_LEN_16_P_0_M_1 (VEX_LEN_16_P_0_M_0 + 1)
1044#define VEX_LEN_16_P_2 (VEX_LEN_16_P_0_M_1 + 1)
1045#define VEX_LEN_17_M_0 (VEX_LEN_16_P_2 + 1)
1046#define VEX_LEN_2A_P_1 (VEX_LEN_17_M_0 + 1)
1047#define VEX_LEN_2A_P_3 (VEX_LEN_2A_P_1 + 1)
1048#define VEX_LEN_2B_M_0 (VEX_LEN_2A_P_3 + 1)
1049#define VEX_LEN_2C_P_1 (VEX_LEN_2B_M_0 + 1)
1050#define VEX_LEN_2C_P_3 (VEX_LEN_2C_P_1 + 1)
1051#define VEX_LEN_2D_P_1 (VEX_LEN_2C_P_3 + 1)
1052#define VEX_LEN_2D_P_3 (VEX_LEN_2D_P_1 + 1)
1053#define VEX_LEN_2E_P_0 (VEX_LEN_2D_P_3 + 1)
1054#define VEX_LEN_2E_P_2 (VEX_LEN_2E_P_0 + 1)
1055#define VEX_LEN_2F_P_0 (VEX_LEN_2E_P_2 + 1)
1056#define VEX_LEN_2F_P_2 (VEX_LEN_2F_P_0 + 1)
1057#define VEX_LEN_51_P_1 (VEX_LEN_2F_P_2 + 1)
1058#define VEX_LEN_51_P_3 (VEX_LEN_51_P_1 + 1)
1059#define VEX_LEN_52_P_1 (VEX_LEN_51_P_3 + 1)
1060#define VEX_LEN_53_P_1 (VEX_LEN_52_P_1 + 1)
1061#define VEX_LEN_58_P_1 (VEX_LEN_53_P_1 + 1)
1062#define VEX_LEN_58_P_3 (VEX_LEN_58_P_1 + 1)
1063#define VEX_LEN_59_P_1 (VEX_LEN_58_P_3 + 1)
1064#define VEX_LEN_59_P_3 (VEX_LEN_59_P_1 + 1)
1065#define VEX_LEN_5A_P_1 (VEX_LEN_59_P_3 + 1)
1066#define VEX_LEN_5A_P_3 (VEX_LEN_5A_P_1 + 1)
1067#define VEX_LEN_5C_P_1 (VEX_LEN_5A_P_3 + 1)
1068#define VEX_LEN_5C_P_3 (VEX_LEN_5C_P_1 + 1)
1069#define VEX_LEN_5D_P_1 (VEX_LEN_5C_P_3 + 1)
1070#define VEX_LEN_5D_P_3 (VEX_LEN_5D_P_1 + 1)
1071#define VEX_LEN_5E_P_1 (VEX_LEN_5D_P_3 + 1)
1072#define VEX_LEN_5E_P_3 (VEX_LEN_5E_P_1 + 1)
1073#define VEX_LEN_5F_P_1 (VEX_LEN_5E_P_3 + 1)
1074#define VEX_LEN_5F_P_3 (VEX_LEN_5F_P_1 + 1)
1075#define VEX_LEN_60_P_2 (VEX_LEN_5F_P_3 + 1)
1076#define VEX_LEN_61_P_2 (VEX_LEN_60_P_2 + 1)
1077#define VEX_LEN_62_P_2 (VEX_LEN_61_P_2 + 1)
1078#define VEX_LEN_63_P_2 (VEX_LEN_62_P_2 + 1)
1079#define VEX_LEN_64_P_2 (VEX_LEN_63_P_2 + 1)
1080#define VEX_LEN_65_P_2 (VEX_LEN_64_P_2 + 1)
1081#define VEX_LEN_66_P_2 (VEX_LEN_65_P_2 + 1)
1082#define VEX_LEN_67_P_2 (VEX_LEN_66_P_2 + 1)
1083#define VEX_LEN_68_P_2 (VEX_LEN_67_P_2 + 1)
1084#define VEX_LEN_69_P_2 (VEX_LEN_68_P_2 + 1)
1085#define VEX_LEN_6A_P_2 (VEX_LEN_69_P_2 + 1)
1086#define VEX_LEN_6B_P_2 (VEX_LEN_6A_P_2 + 1)
1087#define VEX_LEN_6C_P_2 (VEX_LEN_6B_P_2 + 1)
1088#define VEX_LEN_6D_P_2 (VEX_LEN_6C_P_2 + 1)
1089#define VEX_LEN_6E_P_2 (VEX_LEN_6D_P_2 + 1)
1090#define VEX_LEN_70_P_1 (VEX_LEN_6E_P_2 + 1)
1091#define VEX_LEN_70_P_2 (VEX_LEN_70_P_1 + 1)
1092#define VEX_LEN_70_P_3 (VEX_LEN_70_P_2 + 1)
1093#define VEX_LEN_71_R_2_P_2 (VEX_LEN_70_P_3 + 1)
1094#define VEX_LEN_71_R_4_P_2 (VEX_LEN_71_R_2_P_2 + 1)
1095#define VEX_LEN_71_R_6_P_2 (VEX_LEN_71_R_4_P_2 + 1)
1096#define VEX_LEN_72_R_2_P_2 (VEX_LEN_71_R_6_P_2 + 1)
1097#define VEX_LEN_72_R_4_P_2 (VEX_LEN_72_R_2_P_2 + 1)
1098#define VEX_LEN_72_R_6_P_2 (VEX_LEN_72_R_4_P_2 + 1)
1099#define VEX_LEN_73_R_2_P_2 (VEX_LEN_72_R_6_P_2 + 1)
1100#define VEX_LEN_73_R_3_P_2 (VEX_LEN_73_R_2_P_2 + 1)
1101#define VEX_LEN_73_R_6_P_2 (VEX_LEN_73_R_3_P_2 + 1)
1102#define VEX_LEN_73_R_7_P_2 (VEX_LEN_73_R_6_P_2 + 1)
1103#define VEX_LEN_74_P_2 (VEX_LEN_73_R_7_P_2 + 1)
1104#define VEX_LEN_75_P_2 (VEX_LEN_74_P_2 + 1)
1105#define VEX_LEN_76_P_2 (VEX_LEN_75_P_2 + 1)
1106#define VEX_LEN_7E_P_1 (VEX_LEN_76_P_2 + 1)
1107#define VEX_LEN_7E_P_2 (VEX_LEN_7E_P_1 + 1)
1108#define VEX_LEN_AE_R_2_M_0 (VEX_LEN_7E_P_2 + 1)
1109#define VEX_LEN_AE_R_3_M_0 (VEX_LEN_AE_R_2_M_0 + 1)
1110#define VEX_LEN_C2_P_1 (VEX_LEN_AE_R_3_M_0 + 1)
1111#define VEX_LEN_C2_P_3 (VEX_LEN_C2_P_1 + 1)
1112#define VEX_LEN_C4_P_2 (VEX_LEN_C2_P_3 + 1)
1113#define VEX_LEN_C5_P_2 (VEX_LEN_C4_P_2 + 1)
1114#define VEX_LEN_D1_P_2 (VEX_LEN_C5_P_2 + 1)
1115#define VEX_LEN_D2_P_2 (VEX_LEN_D1_P_2 + 1)
1116#define VEX_LEN_D3_P_2 (VEX_LEN_D2_P_2 + 1)
1117#define VEX_LEN_D4_P_2 (VEX_LEN_D3_P_2 + 1)
1118#define VEX_LEN_D5_P_2 (VEX_LEN_D4_P_2 + 1)
1119#define VEX_LEN_D6_P_2 (VEX_LEN_D5_P_2 + 1)
1120#define VEX_LEN_D7_P_2_M_1 (VEX_LEN_D6_P_2 + 1)
1121#define VEX_LEN_D8_P_2 (VEX_LEN_D7_P_2_M_1 + 1)
1122#define VEX_LEN_D9_P_2 (VEX_LEN_D8_P_2 + 1)
1123#define VEX_LEN_DA_P_2 (VEX_LEN_D9_P_2 + 1)
1124#define VEX_LEN_DB_P_2 (VEX_LEN_DA_P_2 + 1)
1125#define VEX_LEN_DC_P_2 (VEX_LEN_DB_P_2 + 1)
1126#define VEX_LEN_DD_P_2 (VEX_LEN_DC_P_2 + 1)
1127#define VEX_LEN_DE_P_2 (VEX_LEN_DD_P_2 + 1)
1128#define VEX_LEN_DF_P_2 (VEX_LEN_DE_P_2 + 1)
1129#define VEX_LEN_E0_P_2 (VEX_LEN_DF_P_2 + 1)
1130#define VEX_LEN_E1_P_2 (VEX_LEN_E0_P_2 + 1)
1131#define VEX_LEN_E2_P_2 (VEX_LEN_E1_P_2 + 1)
1132#define VEX_LEN_E3_P_2 (VEX_LEN_E2_P_2 + 1)
1133#define VEX_LEN_E4_P_2 (VEX_LEN_E3_P_2 + 1)
1134#define VEX_LEN_E5_P_2 (VEX_LEN_E4_P_2 + 1)
1135#define VEX_LEN_E7_P_2_M_0 (VEX_LEN_E5_P_2 + 1)
1136#define VEX_LEN_E8_P_2 (VEX_LEN_E7_P_2_M_0 + 1)
1137#define VEX_LEN_E9_P_2 (VEX_LEN_E8_P_2 + 1)
1138#define VEX_LEN_EA_P_2 (VEX_LEN_E9_P_2 + 1)
1139#define VEX_LEN_EB_P_2 (VEX_LEN_EA_P_2 + 1)
1140#define VEX_LEN_EC_P_2 (VEX_LEN_EB_P_2 + 1)
1141#define VEX_LEN_ED_P_2 (VEX_LEN_EC_P_2 + 1)
1142#define VEX_LEN_EE_P_2 (VEX_LEN_ED_P_2 + 1)
1143#define VEX_LEN_EF_P_2 (VEX_LEN_EE_P_2 + 1)
1144#define VEX_LEN_F1_P_2 (VEX_LEN_EF_P_2 + 1)
1145#define VEX_LEN_F2_P_2 (VEX_LEN_F1_P_2 + 1)
1146#define VEX_LEN_F3_P_2 (VEX_LEN_F2_P_2 + 1)
1147#define VEX_LEN_F4_P_2 (VEX_LEN_F3_P_2 + 1)
1148#define VEX_LEN_F5_P_2 (VEX_LEN_F4_P_2 + 1)
1149#define VEX_LEN_F6_P_2 (VEX_LEN_F5_P_2 + 1)
1150#define VEX_LEN_F7_P_2 (VEX_LEN_F6_P_2 + 1)
1151#define VEX_LEN_F8_P_2 (VEX_LEN_F7_P_2 + 1)
1152#define VEX_LEN_F9_P_2 (VEX_LEN_F8_P_2 + 1)
1153#define VEX_LEN_FA_P_2 (VEX_LEN_F9_P_2 + 1)
1154#define VEX_LEN_FB_P_2 (VEX_LEN_FA_P_2 + 1)
1155#define VEX_LEN_FC_P_2 (VEX_LEN_FB_P_2 + 1)
1156#define VEX_LEN_FD_P_2 (VEX_LEN_FC_P_2 + 1)
1157#define VEX_LEN_FE_P_2 (VEX_LEN_FD_P_2 + 1)
1158#define VEX_LEN_3800_P_2 (VEX_LEN_FE_P_2 + 1)
1159#define VEX_LEN_3801_P_2 (VEX_LEN_3800_P_2 + 1)
1160#define VEX_LEN_3802_P_2 (VEX_LEN_3801_P_2 + 1)
1161#define VEX_LEN_3803_P_2 (VEX_LEN_3802_P_2 + 1)
1162#define VEX_LEN_3804_P_2 (VEX_LEN_3803_P_2 + 1)
1163#define VEX_LEN_3805_P_2 (VEX_LEN_3804_P_2 + 1)
1164#define VEX_LEN_3806_P_2 (VEX_LEN_3805_P_2 + 1)
1165#define VEX_LEN_3807_P_2 (VEX_LEN_3806_P_2 + 1)
1166#define VEX_LEN_3808_P_2 (VEX_LEN_3807_P_2 + 1)
1167#define VEX_LEN_3809_P_2 (VEX_LEN_3808_P_2 + 1)
1168#define VEX_LEN_380A_P_2 (VEX_LEN_3809_P_2 + 1)
1169#define VEX_LEN_380B_P_2 (VEX_LEN_380A_P_2 + 1)
1170#define VEX_LEN_3819_P_2_M_0 (VEX_LEN_380B_P_2 + 1)
1171#define VEX_LEN_381A_P_2_M_0 (VEX_LEN_3819_P_2_M_0 + 1)
1172#define VEX_LEN_381C_P_2 (VEX_LEN_381A_P_2_M_0 + 1)
1173#define VEX_LEN_381D_P_2 (VEX_LEN_381C_P_2 + 1)
1174#define VEX_LEN_381E_P_2 (VEX_LEN_381D_P_2 + 1)
1175#define VEX_LEN_3820_P_2 (VEX_LEN_381E_P_2 + 1)
1176#define VEX_LEN_3821_P_2 (VEX_LEN_3820_P_2 + 1)
1177#define VEX_LEN_3822_P_2 (VEX_LEN_3821_P_2 + 1)
1178#define VEX_LEN_3823_P_2 (VEX_LEN_3822_P_2 + 1)
1179#define VEX_LEN_3824_P_2 (VEX_LEN_3823_P_2 + 1)
1180#define VEX_LEN_3825_P_2 (VEX_LEN_3824_P_2 + 1)
1181#define VEX_LEN_3828_P_2 (VEX_LEN_3825_P_2 + 1)
1182#define VEX_LEN_3829_P_2 (VEX_LEN_3828_P_2 + 1)
1183#define VEX_LEN_382A_P_2_M_0 (VEX_LEN_3829_P_2 + 1)
1184#define VEX_LEN_382B_P_2 (VEX_LEN_382A_P_2_M_0 + 1)
1185#define VEX_LEN_3830_P_2 (VEX_LEN_382B_P_2 + 1)
1186#define VEX_LEN_3831_P_2 (VEX_LEN_3830_P_2 + 1)
1187#define VEX_LEN_3832_P_2 (VEX_LEN_3831_P_2 + 1)
1188#define VEX_LEN_3833_P_2 (VEX_LEN_3832_P_2 + 1)
1189#define VEX_LEN_3834_P_2 (VEX_LEN_3833_P_2 + 1)
1190#define VEX_LEN_3835_P_2 (VEX_LEN_3834_P_2 + 1)
1191#define VEX_LEN_3837_P_2 (VEX_LEN_3835_P_2 + 1)
1192#define VEX_LEN_3838_P_2 (VEX_LEN_3837_P_2 + 1)
1193#define VEX_LEN_3839_P_2 (VEX_LEN_3838_P_2 + 1)
1194#define VEX_LEN_383A_P_2 (VEX_LEN_3839_P_2 + 1)
1195#define VEX_LEN_383B_P_2 (VEX_LEN_383A_P_2 + 1)
1196#define VEX_LEN_383C_P_2 (VEX_LEN_383B_P_2 + 1)
1197#define VEX_LEN_383D_P_2 (VEX_LEN_383C_P_2 + 1)
1198#define VEX_LEN_383E_P_2 (VEX_LEN_383D_P_2 + 1)
1199#define VEX_LEN_383F_P_2 (VEX_LEN_383E_P_2 + 1)
1200#define VEX_LEN_3840_P_2 (VEX_LEN_383F_P_2 + 1)
1201#define VEX_LEN_3841_P_2 (VEX_LEN_3840_P_2 + 1)
1202#define VEX_LEN_3A06_P_2 (VEX_LEN_3841_P_2 + 1)
1203#define VEX_LEN_3A0A_P_2 (VEX_LEN_3A06_P_2 + 1)
1204#define VEX_LEN_3A0B_P_2 (VEX_LEN_3A0A_P_2 + 1)
1205#define VEX_LEN_3A0E_P_2 (VEX_LEN_3A0B_P_2 + 1)
1206#define VEX_LEN_3A0F_P_2 (VEX_LEN_3A0E_P_2 + 1)
1207#define VEX_LEN_3A14_P_2 (VEX_LEN_3A0F_P_2 + 1)
1208#define VEX_LEN_3A15_P_2 (VEX_LEN_3A14_P_2 + 1)
1209#define VEX_LEN_3A16_P_2 (VEX_LEN_3A15_P_2 + 1)
1210#define VEX_LEN_3A17_P_2 (VEX_LEN_3A16_P_2 + 1)
1211#define VEX_LEN_3A18_P_2 (VEX_LEN_3A17_P_2 + 1)
1212#define VEX_LEN_3A19_P_2 (VEX_LEN_3A18_P_2 + 1)
1213#define VEX_LEN_3A20_P_2 (VEX_LEN_3A19_P_2 + 1)
1214#define VEX_LEN_3A21_P_2 (VEX_LEN_3A20_P_2 + 1)
1215#define VEX_LEN_3A22_P_2 (VEX_LEN_3A21_P_2 + 1)
1216#define VEX_LEN_3A41_P_2 (VEX_LEN_3A22_P_2 + 1)
1217#define VEX_LEN_3A42_P_2 (VEX_LEN_3A41_P_2 + 1)
1218#define VEX_LEN_3A4C_P_2 (VEX_LEN_3A42_P_2 + 1)
1219#define VEX_LEN_3A60_P_2 (VEX_LEN_3A4C_P_2 + 1)
1220#define VEX_LEN_3A61_P_2 (VEX_LEN_3A60_P_2 + 1)
1221#define VEX_LEN_3A62_P_2 (VEX_LEN_3A61_P_2 + 1)
1222#define VEX_LEN_3A63_P_2 (VEX_LEN_3A62_P_2 + 1)
1223#define VEX_LEN_3A6A_P_2 (VEX_LEN_3A63_P_2 + 1)
1224#define VEX_LEN_3A6B_P_2 (VEX_LEN_3A6A_P_2 + 1)
1225#define VEX_LEN_3A6E_P_2 (VEX_LEN_3A6B_P_2 + 1)
1226#define VEX_LEN_3A6F_P_2 (VEX_LEN_3A6E_P_2 + 1)
1227#define VEX_LEN_3A7A_P_2 (VEX_LEN_3A6F_P_2 + 1)
1228#define VEX_LEN_3A7B_P_2 (VEX_LEN_3A7A_P_2 + 1)
1229#define VEX_LEN_3A7E_P_2 (VEX_LEN_3A7B_P_2 + 1)
1230#define VEX_LEN_3A7F_P_2 (VEX_LEN_3A7E_P_2 + 1)
1231
26ca5450 1232typedef void (*op_rtn) (int bytemode, int sizeflag);
252b5132
RH		 1233
1234struct dis386 {
2da11e11 1235 const char *name;
ce518a5f
L		 1236 struct
1237 {
1238 op_rtn rtn;
1239 int bytemode;
1240 } op[MAX_OPERANDS];
252b5132
RH		 1241};
1242
1243/* Upper case letters in the instruction names here are macros.
1244 'A' => print 'b' if no register operands or suffix_always is true
1245 'B' => print 'b' if suffix_always is true
9306ca4a 1246 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
98b528ac 1247 size prefix
ed7841b3 1248 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
98b528ac 1249 suffix_always is true
252b5132 1250 'E' => print 'e' if 32-bit form of jcxz
3ffd33cf 1251 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
52fd6d94 1252 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
5dd0794d 1253 'H' => print ",pt" or ",pn" branch hint
9306ca4a 1254 'I' => honor following macro letter even in Intel mode (implemented only
98b528ac 1255 for some of the macro letters)
9306ca4a 1256 'J' => print 'l'
42903f7f 1257 'K' => print 'd' or 'q' if rex prefix is present.
252b5132 1258 'L' => print 'l' if suffix_always is true
9d141669 1259 'M' => print 'r' if intel_mnemonic is false.
252b5132 1260 'N' => print 'n' if instruction has no wait "prefix"
a35ca55a 1261 'O' => print 'd' or 'o' (or 'q' in Intel mode)
52b15da3 1262 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
98b528ac
L		 1263 or suffix_always is true. print 'q' if rex prefix is present.
1264 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1265 is true
a35ca55a 1266 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
52b15da3 1267 'S' => print 'w', 'l' or 'q' if suffix_always is true
6439fc28
AM		 1268 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1269 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1a114b12 1270 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
a35ca55a 1271 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
9306ca4a 1272 'X' => print 's', 'd' depending on data16 prefix (for XMM)
8a72226a
L		 1273 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1274 suffix_always is true.
6dd5059a 1275 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
9d141669 1276 '!' => change condition from true to false or from false to true.
98b528ac
L		 1277 '%' => add 1 upper case letter to the macro.
1278
1279 2 upper case letter macros:
c0f3af97
L		 1280 "XY" => print 'x' or 'y' if no register operands or suffix_always
1281 is true.
98b528ac
L		 1282 'LQ' => print 'l' ('d' in Intel mode) or 'q' for memory operand
1283 or suffix_always is true
52b15da3 1284
6439fc28
AM		 1285 Many of the above letters print nothing in Intel mode. See "putop"
1286 for the details.
52b15da3 1287
6439fc28 1288 Braces '{' and '}', and vertical bars '|', indicate alternative
7c52e0e8 1289 mnemonic strings for AT&T and Intel. */
252b5132 1290
6439fc28 1291static const struct dis386 dis386[] = {
252b5132 1292 /* 00 */
ce518a5f
L		 1293 { "addB", { Eb, Gb } },
1294 { "addS", { Ev, Gv } },
1295 { "addB", { Gb, Eb } },
1296 { "addS", { Gv, Ev } },
1297 { "addB", { AL, Ib } },
1298 { "addS", { eAX, Iv } },
4e7d34a6
L		 1299 { X86_64_TABLE (X86_64_06) },
1300 { X86_64_TABLE (X86_64_07) },
252b5132 1301 /* 08 */
ce518a5f
L		 1302 { "orB", { Eb, Gb } },
1303 { "orS", { Ev, Gv } },
1304 { "orB", { Gb, Eb } },
1305 { "orS", { Gv, Ev } },
1306 { "orB", { AL, Ib } },
1307 { "orS", { eAX, Iv } },
4e7d34a6 1308 { X86_64_TABLE (X86_64_0D) },
ce518a5f 1309 { "(bad)", { XX } }, /* 0x0f extended opcode escape */
252b5132 1310 /* 10 */
ce518a5f
L		 1311 { "adcB", { Eb, Gb } },
1312 { "adcS", { Ev, Gv } },
1313 { "adcB", { Gb, Eb } },
1314 { "adcS", { Gv, Ev } },
1315 { "adcB", { AL, Ib } },
1316 { "adcS", { eAX, Iv } },
4e7d34a6
L		 1317 { X86_64_TABLE (X86_64_16) },
1318 { X86_64_TABLE (X86_64_17) },
252b5132 1319 /* 18 */
ce518a5f
L		 1320 { "sbbB", { Eb, Gb } },
1321 { "sbbS", { Ev, Gv } },
1322 { "sbbB", { Gb, Eb } },
1323 { "sbbS", { Gv, Ev } },
1324 { "sbbB", { AL, Ib } },
1325 { "sbbS", { eAX, Iv } },
4e7d34a6
L		 1326 { X86_64_TABLE (X86_64_1E) },
1327 { X86_64_TABLE (X86_64_1F) },
252b5132 1328 /* 20 */
ce518a5f
L		 1329 { "andB", { Eb, Gb } },
1330 { "andS", { Ev, Gv } },
1331 { "andB", { Gb, Eb } },
1332 { "andS", { Gv, Ev } },
1333 { "andB", { AL, Ib } },
1334 { "andS", { eAX, Iv } },
1335 { "(bad)", { XX } }, /* SEG ES prefix */
4e7d34a6 1336 { X86_64_TABLE (X86_64_27) },
252b5132 1337 /* 28 */
ce518a5f
L		 1338 { "subB", { Eb, Gb } },
1339 { "subS", { Ev, Gv } },
1340 { "subB", { Gb, Eb } },
1341 { "subS", { Gv, Ev } },
1342 { "subB", { AL, Ib } },
1343 { "subS", { eAX, Iv } },
1344 { "(bad)", { XX } }, /* SEG CS prefix */
4e7d34a6 1345 { X86_64_TABLE (X86_64_2F) },
252b5132 1346 /* 30 */
ce518a5f
L		 1347 { "xorB", { Eb, Gb } },
1348 { "xorS", { Ev, Gv } },
1349 { "xorB", { Gb, Eb } },
1350 { "xorS", { Gv, Ev } },
1351 { "xorB", { AL, Ib } },
1352 { "xorS", { eAX, Iv } },
1353 { "(bad)", { XX } }, /* SEG SS prefix */
4e7d34a6 1354 { X86_64_TABLE (X86_64_37) },
252b5132 1355 /* 38 */
ce518a5f
L		 1356 { "cmpB", { Eb, Gb } },
1357 { "cmpS", { Ev, Gv } },
1358 { "cmpB", { Gb, Eb } },
1359 { "cmpS", { Gv, Ev } },
1360 { "cmpB", { AL, Ib } },
1361 { "cmpS", { eAX, Iv } },
1362 { "(bad)", { XX } }, /* SEG DS prefix */
4e7d34a6 1363 { X86_64_TABLE (X86_64_3F) },
252b5132 1364 /* 40 */
ce518a5f
L		 1365 { "inc{S|}", { RMeAX } },
1366 { "inc{S|}", { RMeCX } },
1367 { "inc{S|}", { RMeDX } },
1368 { "inc{S|}", { RMeBX } },
1369 { "inc{S|}", { RMeSP } },
1370 { "inc{S|}", { RMeBP } },
1371 { "inc{S|}", { RMeSI } },
1372 { "inc{S|}", { RMeDI } },
252b5132 1373 /* 48 */
ce518a5f
L		 1374 { "dec{S|}", { RMeAX } },
1375 { "dec{S|}", { RMeCX } },
1376 { "dec{S|}", { RMeDX } },
1377 { "dec{S|}", { RMeBX } },
1378 { "dec{S|}", { RMeSP } },
1379 { "dec{S|}", { RMeBP } },
1380 { "dec{S|}", { RMeSI } },
1381 { "dec{S|}", { RMeDI } },
252b5132 1382 /* 50 */
ce518a5f
L		 1383 { "pushV", { RMrAX } },
1384 { "pushV", { RMrCX } },
1385 { "pushV", { RMrDX } },
1386 { "pushV", { RMrBX } },
1387 { "pushV", { RMrSP } },
1388 { "pushV", { RMrBP } },
1389 { "pushV", { RMrSI } },
1390 { "pushV", { RMrDI } },
252b5132 1391 /* 58 */
ce518a5f
L		 1392 { "popV", { RMrAX } },
1393 { "popV", { RMrCX } },
1394 { "popV", { RMrDX } },
1395 { "popV", { RMrBX } },
1396 { "popV", { RMrSP } },
1397 { "popV", { RMrBP } },
1398 { "popV", { RMrSI } },
1399 { "popV", { RMrDI } },
252b5132 1400 /* 60 */
4e7d34a6
L		 1401 { X86_64_TABLE (X86_64_60) },
1402 { X86_64_TABLE (X86_64_61) },
1403 { X86_64_TABLE (X86_64_62) },
1404 { X86_64_TABLE (X86_64_63) },
ce518a5f
L		 1405 { "(bad)", { XX } }, /* seg fs */
1406 { "(bad)", { XX } }, /* seg gs */
1407 { "(bad)", { XX } }, /* op size prefix */
1408 { "(bad)", { XX } }, /* adr size prefix */
252b5132 1409 /* 68 */
ce518a5f
L		 1410 { "pushT", { Iq } },
1411 { "imulS", { Gv, Ev, Iv } },
1412 { "pushT", { sIb } },
1413 { "imulS", { Gv, Ev, sIb } },
7c52e0e8 1414 { "ins{b|}", { Ybr, indirDX } },
4e7d34a6 1415 { X86_64_TABLE (X86_64_6D) },
7c52e0e8 1416 { "outs{b|}", { indirDXr, Xb } },
4e7d34a6 1417 { X86_64_TABLE (X86_64_6F) },
252b5132 1418 /* 70 */
ce518a5f
L		 1419 { "joH", { Jb, XX, cond_jump_flag } },
1420 { "jnoH", { Jb, XX, cond_jump_flag } },
1421 { "jbH", { Jb, XX, cond_jump_flag } },
1422 { "jaeH", { Jb, XX, cond_jump_flag } },
1423 { "jeH", { Jb, XX, cond_jump_flag } },
1424 { "jneH", { Jb, XX, cond_jump_flag } },
1425 { "jbeH", { Jb, XX, cond_jump_flag } },
1426 { "jaH", { Jb, XX, cond_jump_flag } },
252b5132 1427 /* 78 */
ce518a5f
L		 1428 { "jsH", { Jb, XX, cond_jump_flag } },
1429 { "jnsH", { Jb, XX, cond_jump_flag } },
1430 { "jpH", { Jb, XX, cond_jump_flag } },
1431 { "jnpH", { Jb, XX, cond_jump_flag } },
1432 { "jlH", { Jb, XX, cond_jump_flag } },
1433 { "jgeH", { Jb, XX, cond_jump_flag } },
1434 { "jleH", { Jb, XX, cond_jump_flag } },
1435 { "jgH", { Jb, XX, cond_jump_flag } },
252b5132 1436 /* 80 */
1ceb70f8
L		 1437 { REG_TABLE (REG_80) },
1438 { REG_TABLE (REG_81) },
ce518a5f 1439 { "(bad)", { XX } },
1ceb70f8 1440 { REG_TABLE (REG_82) },
ce518a5f
L		 1441 { "testB", { Eb, Gb } },
1442 { "testS", { Ev, Gv } },
1443 { "xchgB", { Eb, Gb } },
1444 { "xchgS", { Ev, Gv } },
252b5132 1445 /* 88 */
ce518a5f
L		 1446 { "movB", { Eb, Gb } },
1447 { "movS", { Ev, Gv } },
1448 { "movB", { Gb, Eb } },
1449 { "movS", { Gv, Ev } },
1450 { "movD", { Sv, Sw } },
1ceb70f8 1451 { MOD_TABLE (MOD_8D) },
ce518a5f 1452 { "movD", { Sw, Sv } },
1ceb70f8 1453 { REG_TABLE (REG_8F) },
252b5132 1454 /* 90 */
1ceb70f8 1455 { PREFIX_TABLE (PREFIX_90) },
ce518a5f
L		 1456 { "xchgS", { RMeCX, eAX } },
1457 { "xchgS", { RMeDX, eAX } },
1458 { "xchgS", { RMeBX, eAX } },
1459 { "xchgS", { RMeSP, eAX } },
1460 { "xchgS", { RMeBP, eAX } },
1461 { "xchgS", { RMeSI, eAX } },
1462 { "xchgS", { RMeDI, eAX } },
252b5132 1463 /* 98 */
7c52e0e8
L		 1464 { "cW{t|}R", { XX } },
1465 { "cR{t|}O", { XX } },
4e7d34a6 1466 { X86_64_TABLE (X86_64_9A) },
ce518a5f
L		 1467 { "(bad)", { XX } }, /* fwait */
1468 { "pushfT", { XX } },
1469 { "popfT", { XX } },
7c52e0e8
L		 1470 { "sahf", { XX } },
1471 { "lahf", { XX } },
252b5132 1472 /* a0 */
ce518a5f
L		 1473 { "movB", { AL, Ob } },
1474 { "movS", { eAX, Ov } },
1475 { "movB", { Ob, AL } },
1476 { "movS", { Ov, eAX } },
7c52e0e8
L		 1477 { "movs{b|}", { Ybr, Xb } },
1478 { "movs{R|}", { Yvr, Xv } },
1479 { "cmps{b|}", { Xb, Yb } },
1480 { "cmps{R|}", { Xv, Yv } },
252b5132 1481 /* a8 */
ce518a5f
L		 1482 { "testB", { AL, Ib } },
1483 { "testS", { eAX, Iv } },
1484 { "stosB", { Ybr, AL } },
1485 { "stosS", { Yvr, eAX } },
1486 { "lodsB", { ALr, Xb } },
1487 { "lodsS", { eAXr, Xv } },
1488 { "scasB", { AL, Yb } },
1489 { "scasS", { eAX, Yv } },
252b5132 1490 /* b0 */
ce518a5f
L		 1491 { "movB", { RMAL, Ib } },
1492 { "movB", { RMCL, Ib } },
1493 { "movB", { RMDL, Ib } },
1494 { "movB", { RMBL, Ib } },
1495 { "movB", { RMAH, Ib } },
1496 { "movB", { RMCH, Ib } },
1497 { "movB", { RMDH, Ib } },
1498 { "movB", { RMBH, Ib } },
252b5132 1499 /* b8 */
ce518a5f
L		 1500 { "movS", { RMeAX, Iv64 } },
1501 { "movS", { RMeCX, Iv64 } },
1502 { "movS", { RMeDX, Iv64 } },
1503 { "movS", { RMeBX, Iv64 } },
1504 { "movS", { RMeSP, Iv64 } },
1505 { "movS", { RMeBP, Iv64 } },
1506 { "movS", { RMeSI, Iv64 } },
1507 { "movS", { RMeDI, Iv64 } },
252b5132 1508 /* c0 */
1ceb70f8
L		 1509 { REG_TABLE (REG_C0) },
1510 { REG_TABLE (REG_C1) },
ce518a5f
L		 1511 { "retT", { Iw } },
1512 { "retT", { XX } },
4e7d34a6
L		 1513 { X86_64_TABLE (X86_64_C4) },
1514 { X86_64_TABLE (X86_64_C5) },
1ceb70f8
L		 1515 { REG_TABLE (REG_C6) },
1516 { REG_TABLE (REG_C7) },
252b5132 1517 /* c8 */
ce518a5f
L		 1518 { "enterT", { Iw, Ib } },
1519 { "leaveT", { XX } },
1520 { "lretP", { Iw } },
1521 { "lretP", { XX } },
1522 { "int3", { XX } },
1523 { "int", { Ib } },
4e7d34a6 1524 { X86_64_TABLE (X86_64_CE) },
ce518a5f 1525 { "iretP", { XX } },
252b5132 1526 /* d0 */
1ceb70f8
L		 1527 { REG_TABLE (REG_D0) },
1528 { REG_TABLE (REG_D1) },
1529 { REG_TABLE (REG_D2) },
1530 { REG_TABLE (REG_D3) },
4e7d34a6
L		 1531 { X86_64_TABLE (X86_64_D4) },
1532 { X86_64_TABLE (X86_64_D5) },
ce518a5f
L		 1533 { "(bad)", { XX } },
1534 { "xlat", { DSBX } },
252b5132
RH		 1535 /* d8 */
1536 { FLOAT },
1537 { FLOAT },
1538 { FLOAT },
1539 { FLOAT },
1540 { FLOAT },
1541 { FLOAT },
1542 { FLOAT },
1543 { FLOAT },
1544 /* e0 */
ce518a5f
L		 1545 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
1546 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
1547 { "loopFH", { Jb, XX, loop_jcxz_flag } },
1548 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
1549 { "inB", { AL, Ib } },
1550 { "inG", { zAX, Ib } },
1551 { "outB", { Ib, AL } },
1552 { "outG", { Ib, zAX } },
252b5132 1553 /* e8 */
ce518a5f
L		 1554 { "callT", { Jv } },
1555 { "jmpT", { Jv } },
4e7d34a6 1556 { X86_64_TABLE (X86_64_EA) },
ce518a5f
L		 1557 { "jmp", { Jb } },
1558 { "inB", { AL, indirDX } },
1559 { "inG", { zAX, indirDX } },
1560 { "outB", { indirDX, AL } },
1561 { "outG", { indirDX, zAX } },
252b5132 1562 /* f0 */
ce518a5f
L		 1563 { "(bad)", { XX } }, /* lock prefix */
1564 { "icebp", { XX } },
1565 { "(bad)", { XX } }, /* repne */
1566 { "(bad)", { XX } }, /* repz */
1567 { "hlt", { XX } },
1568 { "cmc", { XX } },
1ceb70f8
L		 1569 { REG_TABLE (REG_F6) },
1570 { REG_TABLE (REG_F7) },
252b5132 1571 /* f8 */
ce518a5f
L		 1572 { "clc", { XX } },
1573 { "stc", { XX } },
1574 { "cli", { XX } },
1575 { "sti", { XX } },
1576 { "cld", { XX } },
1577 { "std", { XX } },
1ceb70f8
L		 1578 { REG_TABLE (REG_FE) },
1579 { REG_TABLE (REG_FF) },
252b5132
RH		 1580};
1581
6439fc28 1582static const struct dis386 dis386_twobyte[] = {
252b5132 1583 /* 00 */
1ceb70f8
L		 1584 { REG_TABLE (REG_0F00 ) },
1585 { REG_TABLE (REG_0F01 ) },
ce518a5f
L		 1586 { "larS", { Gv, Ew } },
1587 { "lslS", { Gv, Ew } },
1588 { "(bad)", { XX } },
1589 { "syscall", { XX } },
1590 { "clts", { XX } },
1591 { "sysretP", { XX } },
252b5132 1592 /* 08 */
ce518a5f
L		 1593 { "invd", { XX } },
1594 { "wbinvd", { XX } },
1595 { "(bad)", { XX } },
1596 { "ud2a", { XX } },
1597 { "(bad)", { XX } },
b5b1fc4f 1598 { REG_TABLE (REG_0F0D) },
ce518a5f
L		 1599 { "femms", { XX } },
1600 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
252b5132 1601 /* 10 */
1ceb70f8
L		 1602 { PREFIX_TABLE (PREFIX_0F10) },
1603 { PREFIX_TABLE (PREFIX_0F11) },
1604 { PREFIX_TABLE (PREFIX_0F12) },
1605 { MOD_TABLE (MOD_0F13) },
f2a421c4
L		 1606 { "unpcklpX", { XM, EXx } },
1607 { "unpckhpX", { XM, EXx } },
1ceb70f8
L		 1608 { PREFIX_TABLE (PREFIX_0F16) },
1609 { MOD_TABLE (MOD_0F17) },
252b5132 1610 /* 18 */
1ceb70f8 1611 { REG_TABLE (REG_0F18) },
b5b1fc4f
L		 1612 { "nopQ", { Ev } },
1613 { "nopQ", { Ev } },
1614 { "nopQ", { Ev } },
1615 { "nopQ", { Ev } },
1616 { "nopQ", { Ev } },
1617 { "nopQ", { Ev } },
ce518a5f 1618 { "nopQ", { Ev } },
252b5132 1619 /* 20 */
1ceb70f8
L		 1620 { MOD_TABLE (MOD_0F20) },
1621 { MOD_TABLE (MOD_0F21) },
1622 { MOD_TABLE (MOD_0F22) },
1623 { MOD_TABLE (MOD_0F23) },
1624 { MOD_TABLE (MOD_0F24) },
4e7d34a6 1625 { THREE_BYTE_TABLE (THREE_BYTE_0F25) },
1ceb70f8 1626 { MOD_TABLE (MOD_0F26) },
ce518a5f 1627 { "(bad)", { XX } },
252b5132 1628 /* 28 */
09a2c6cf 1629 { "movapX", { XM, EXx } },
d5d7db8e 1630 { "movapX", { EXx, XM } },
1ceb70f8
L		 1631 { PREFIX_TABLE (PREFIX_0F2A) },
1632 { PREFIX_TABLE (PREFIX_0F2B) },
1633 { PREFIX_TABLE (PREFIX_0F2C) },
1634 { PREFIX_TABLE (PREFIX_0F2D) },
1635 { PREFIX_TABLE (PREFIX_0F2E) },
1636 { PREFIX_TABLE (PREFIX_0F2F) },
252b5132 1637 /* 30 */
ce518a5f
L		 1638 { "wrmsr", { XX } },
1639 { "rdtsc", { XX } },
1640 { "rdmsr", { XX } },
1641 { "rdpmc", { XX } },
1642 { "sysenter", { XX } },
1643 { "sysexit", { XX } },
1644 { "(bad)", { XX } },
47dd174c 1645 { "getsec", { XX } },
252b5132 1646 /* 38 */
4e7d34a6 1647 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
ce518a5f 1648 { "(bad)", { XX } },
4e7d34a6 1649 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
ce518a5f
L		 1650 { "(bad)", { XX } },
1651 { "(bad)", { XX } },
1652 { "(bad)", { XX } },
1653 { "(bad)", { XX } },
1654 { "(bad)", { XX } },
252b5132 1655 /* 40 */
ce518a5f
L		 1656 { "cmovo", { Gv, Ev } },
1657 { "cmovno", { Gv, Ev } },
1658 { "cmovb", { Gv, Ev } },
1659 { "cmovae", { Gv, Ev } },
1660 { "cmove", { Gv, Ev } },
1661 { "cmovne", { Gv, Ev } },
1662 { "cmovbe", { Gv, Ev } },
1663 { "cmova", { Gv, Ev } },
252b5132 1664 /* 48 */
ce518a5f
L		 1665 { "cmovs", { Gv, Ev } },
1666 { "cmovns", { Gv, Ev } },
1667 { "cmovp", { Gv, Ev } },
1668 { "cmovnp", { Gv, Ev } },
1669 { "cmovl", { Gv, Ev } },
1670 { "cmovge", { Gv, Ev } },
1671 { "cmovle", { Gv, Ev } },
1672 { "cmovg", { Gv, Ev } },
252b5132 1673 /* 50 */
75c135a8 1674 { MOD_TABLE (MOD_0F51) },
1ceb70f8
L		 1675 { PREFIX_TABLE (PREFIX_0F51) },
1676 { PREFIX_TABLE (PREFIX_0F52) },
1677 { PREFIX_TABLE (PREFIX_0F53) },
09a2c6cf
L		 1678 { "andpX", { XM, EXx } },
1679 { "andnpX", { XM, EXx } },
1680 { "orpX", { XM, EXx } },
1681 { "xorpX", { XM, EXx } },
252b5132 1682 /* 58 */
1ceb70f8
L		 1683 { PREFIX_TABLE (PREFIX_0F58) },
1684 { PREFIX_TABLE (PREFIX_0F59) },
1685 { PREFIX_TABLE (PREFIX_0F5A) },
1686 { PREFIX_TABLE (PREFIX_0F5B) },
1687 { PREFIX_TABLE (PREFIX_0F5C) },
1688 { PREFIX_TABLE (PREFIX_0F5D) },
1689 { PREFIX_TABLE (PREFIX_0F5E) },
1690 { PREFIX_TABLE (PREFIX_0F5F) },
252b5132 1691 /* 60 */
1ceb70f8
L		 1692 { PREFIX_TABLE (PREFIX_0F60) },
1693 { PREFIX_TABLE (PREFIX_0F61) },
1694 { PREFIX_TABLE (PREFIX_0F62) },
ce518a5f
L		 1695 { "packsswb", { MX, EM } },
1696 { "pcmpgtb", { MX, EM } },
1697 { "pcmpgtw", { MX, EM } },
1698 { "pcmpgtd", { MX, EM } },
1699 { "packuswb", { MX, EM } },
252b5132 1700 /* 68 */
ce518a5f
L		 1701 { "punpckhbw", { MX, EM } },
1702 { "punpckhwd", { MX, EM } },
1703 { "punpckhdq", { MX, EM } },
1704 { "packssdw", { MX, EM } },
1ceb70f8
L		 1705 { PREFIX_TABLE (PREFIX_0F6C) },
1706 { PREFIX_TABLE (PREFIX_0F6D) },
231af070 1707 { "movK", { MX, Edq } },
1ceb70f8 1708 { PREFIX_TABLE (PREFIX_0F6F) },
252b5132 1709 /* 70 */
1ceb70f8
L		 1710 { PREFIX_TABLE (PREFIX_0F70) },
1711 { REG_TABLE (REG_0F71) },
1712 { REG_TABLE (REG_0F72) },
1713 { REG_TABLE (REG_0F73) },
ce518a5f
L		 1714 { "pcmpeqb", { MX, EM } },
1715 { "pcmpeqw", { MX, EM } },
1716 { "pcmpeqd", { MX, EM } },
1717 { "emms", { XX } },
252b5132 1718 /* 78 */
1ceb70f8
L		 1719 { PREFIX_TABLE (PREFIX_0F78) },
1720 { PREFIX_TABLE (PREFIX_0F79) },
4e7d34a6 1721 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
89b66d55 1722 { THREE_BYTE_TABLE (THREE_BYTE_0F7B) },
1ceb70f8
L		 1723 { PREFIX_TABLE (PREFIX_0F7C) },
1724 { PREFIX_TABLE (PREFIX_0F7D) },
1725 { PREFIX_TABLE (PREFIX_0F7E) },
1726 { PREFIX_TABLE (PREFIX_0F7F) },
252b5132 1727 /* 80 */
ce518a5f
L		 1728 { "joH", { Jv, XX, cond_jump_flag } },
1729 { "jnoH", { Jv, XX, cond_jump_flag } },
1730 { "jbH", { Jv, XX, cond_jump_flag } },
1731 { "jaeH", { Jv, XX, cond_jump_flag } },
1732 { "jeH", { Jv, XX, cond_jump_flag } },
1733 { "jneH", { Jv, XX, cond_jump_flag } },
1734 { "jbeH", { Jv, XX, cond_jump_flag } },
1735 { "jaH", { Jv, XX, cond_jump_flag } },
252b5132 1736 /* 88 */
ce518a5f
L		 1737 { "jsH", { Jv, XX, cond_jump_flag } },
1738 { "jnsH", { Jv, XX, cond_jump_flag } },
1739 { "jpH", { Jv, XX, cond_jump_flag } },
1740 { "jnpH", { Jv, XX, cond_jump_flag } },
1741 { "jlH", { Jv, XX, cond_jump_flag } },
1742 { "jgeH", { Jv, XX, cond_jump_flag } },
1743 { "jleH", { Jv, XX, cond_jump_flag } },
1744 { "jgH", { Jv, XX, cond_jump_flag } },
252b5132 1745 /* 90 */
ce518a5f
L		 1746 { "seto", { Eb } },
1747 { "setno", { Eb } },
1748 { "setb", { Eb } },
1749 { "setae", { Eb } },
1750 { "sete", { Eb } },
1751 { "setne", { Eb } },
1752 { "setbe", { Eb } },
1753 { "seta", { Eb } },
252b5132 1754 /* 98 */
ce518a5f
L		 1755 { "sets", { Eb } },
1756 { "setns", { Eb } },
1757 { "setp", { Eb } },
1758 { "setnp", { Eb } },
1759 { "setl", { Eb } },
1760 { "setge", { Eb } },
1761 { "setle", { Eb } },
1762 { "setg", { Eb } },
252b5132 1763 /* a0 */
ce518a5f
L		 1764 { "pushT", { fs } },
1765 { "popT", { fs } },
1766 { "cpuid", { XX } },
1767 { "btS", { Ev, Gv } },
1768 { "shldS", { Ev, Gv, Ib } },
1769 { "shldS", { Ev, Gv, CL } },
1ceb70f8
L		 1770 { REG_TABLE (REG_0FA6) },
1771 { REG_TABLE (REG_0FA7) },
252b5132 1772 /* a8 */
ce518a5f
L		 1773 { "pushT", { gs } },
1774 { "popT", { gs } },
1775 { "rsm", { XX } },
1776 { "btsS", { Ev, Gv } },
1777 { "shrdS", { Ev, Gv, Ib } },
1778 { "shrdS", { Ev, Gv, CL } },
1ceb70f8 1779 { REG_TABLE (REG_0FAE) },
ce518a5f 1780 { "imulS", { Gv, Ev } },
252b5132 1781 /* b0 */
ce518a5f
L		 1782 { "cmpxchgB", { Eb, Gb } },
1783 { "cmpxchgS", { Ev, Gv } },
1ceb70f8 1784 { MOD_TABLE (MOD_0FB2) },
ce518a5f 1785 { "btrS", { Ev, Gv } },
1ceb70f8
L		 1786 { MOD_TABLE (MOD_0FB4) },
1787 { MOD_TABLE (MOD_0FB5) },
7c52e0e8
L		 1788 { "movz{bR|x}", { Gv, Eb } },
1789 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
252b5132 1790 /* b8 */
1ceb70f8 1791 { PREFIX_TABLE (PREFIX_0FB8) },
ce518a5f 1792 { "ud2b", { XX } },
1ceb70f8 1793 { REG_TABLE (REG_0FBA) },
ce518a5f
L		 1794 { "btcS", { Ev, Gv } },
1795 { "bsfS", { Gv, Ev } },
1ceb70f8 1796 { PREFIX_TABLE (PREFIX_0FBD) },
7c52e0e8
L		 1797 { "movs{bR|x}", { Gv, Eb } },
1798 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
252b5132 1799 /* c0 */
ce518a5f
L		 1800 { "xaddB", { Eb, Gb } },
1801 { "xaddS", { Ev, Gv } },
1ceb70f8 1802 { PREFIX_TABLE (PREFIX_0FC2) },
4ee52178 1803 { PREFIX_TABLE (PREFIX_0FC3) },
ce518a5f
L		 1804 { "pinsrw", { MX, Edqw, Ib } },
1805 { "pextrw", { Gdq, MS, Ib } },
09a2c6cf 1806 { "shufpX", { XM, EXx, Ib } },
1ceb70f8 1807 { REG_TABLE (REG_0FC7) },
252b5132 1808 /* c8 */
ce518a5f
L		 1809 { "bswap", { RMeAX } },
1810 { "bswap", { RMeCX } },
1811 { "bswap", { RMeDX } },
1812 { "bswap", { RMeBX } },
1813 { "bswap", { RMeSP } },
1814 { "bswap", { RMeBP } },
1815 { "bswap", { RMeSI } },
1816 { "bswap", { RMeDI } },
252b5132 1817 /* d0 */
1ceb70f8 1818 { PREFIX_TABLE (PREFIX_0FD0) },
ce518a5f
L		 1819 { "psrlw", { MX, EM } },
1820 { "psrld", { MX, EM } },
1821 { "psrlq", { MX, EM } },
1822 { "paddq", { MX, EM } },
1823 { "pmullw", { MX, EM } },
1ceb70f8 1824 { PREFIX_TABLE (PREFIX_0FD6) },
75c135a8 1825 { MOD_TABLE (MOD_0FD7) },
252b5132 1826 /* d8 */
ce518a5f
L		 1827 { "psubusb", { MX, EM } },
1828 { "psubusw", { MX, EM } },
1829 { "pminub", { MX, EM } },
1830 { "pand", { MX, EM } },
1831 { "paddusb", { MX, EM } },
1832 { "paddusw", { MX, EM } },
1833 { "pmaxub", { MX, EM } },
1834 { "pandn", { MX, EM } },
252b5132 1835 /* e0 */
ce518a5f
L		 1836 { "pavgb", { MX, EM } },
1837 { "psraw", { MX, EM } },
1838 { "psrad", { MX, EM } },
1839 { "pavgw", { MX, EM } },
1840 { "pmulhuw", { MX, EM } },
1841 { "pmulhw", { MX, EM } },
1ceb70f8
L		 1842 { PREFIX_TABLE (PREFIX_0FE6) },
1843 { PREFIX_TABLE (PREFIX_0FE7) },
252b5132 1844 /* e8 */
ce518a5f
L		 1845 { "psubsb", { MX, EM } },
1846 { "psubsw", { MX, EM } },
1847 { "pminsw", { MX, EM } },
1848 { "por", { MX, EM } },
1849 { "paddsb", { MX, EM } },
1850 { "paddsw", { MX, EM } },
1851 { "pmaxsw", { MX, EM } },
1852 { "pxor", { MX, EM } },
252b5132 1853 /* f0 */
1ceb70f8 1854 { PREFIX_TABLE (PREFIX_0FF0) },
ce518a5f
L		 1855 { "psllw", { MX, EM } },
1856 { "pslld", { MX, EM } },
1857 { "psllq", { MX, EM } },
1858 { "pmuludq", { MX, EM } },
1859 { "pmaddwd", { MX, EM } },
1860 { "psadbw", { MX, EM } },
1ceb70f8 1861 { PREFIX_TABLE (PREFIX_0FF7) },
252b5132 1862 /* f8 */
ce518a5f
L		 1863 { "psubb", { MX, EM } },
1864 { "psubw", { MX, EM } },
1865 { "psubd", { MX, EM } },
1866 { "psubq", { MX, EM } },
1867 { "paddb", { MX, EM } },
1868 { "paddw", { MX, EM } },
1869 { "paddd", { MX, EM } },
1870 { "(bad)", { XX } },
252b5132
RH		 1871};
1872
1873static const unsigned char onebyte_has_modrm[256] = {
c608c12e
AM		 1874 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1875 /* ------------------------------- */
1876 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1877 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1878 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1879 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1880 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1881 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1882 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1883 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1884 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1885 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1886 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1887 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1888 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1889 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1890 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1891 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1892 /* ------------------------------- */
1893 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
252b5132
RH		 1894};
1895
1896static const unsigned char twobyte_has_modrm[256] = {
c608c12e
AM		 1897 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1898 /* ------------------------------- */
252b5132 1899 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
b5b1fc4f 1900 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
85f10a01 1901 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
331d2d0d 1902 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
252b5132 1903 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
4bba6815
AM		 1904 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1905 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
85f10a01 1906 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
252b5132
RH		 1907 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1908 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
30d1c836 1909 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
050dfa73 1910 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
252b5132 1911 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
ca164297 1912 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
4bba6815 1913 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
ca164297 1914 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
c608c12e
AM		 1915 /* ------------------------------- */
1916 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1917};
1918
252b5132
RH		 1919static char obuf[100];
1920static char *obufp;
1921static char scratchbuf[100];
1922static unsigned char *start_codep;
1923static unsigned char *insn_codep;
1924static unsigned char *codep;
b844680a
L		 1925static const char *lock_prefix;
1926static const char *data_prefix;
1927static const char *addr_prefix;
1928static const char *repz_prefix;
1929static const char *repnz_prefix;
252b5132 1930static disassemble_info *the_info;
7967e09e
L		 1931static struct
1932 {
1933 int mod;
7967e09e 1934 int reg;
484c222e 1935 int rm;
7967e09e
L		 1936 }
1937modrm;
4bba6815 1938static unsigned char need_modrm;
c0f3af97
L		 1939static struct
1940 {
1941 int register_specifier;
1942 int length;
1943 int prefix;
1944 int w;
1945 }
1946vex;
1947static unsigned char need_vex;
1948static unsigned char need_vex_reg;
dae39acc 1949static unsigned char vex_w_done;
252b5132 1950
4bba6815
AM		 1951/* If we are accessing mod/rm/reg without need_modrm set, then the
1952 values are stale. Hitting this abort likely indicates that you
1953 need to update onebyte_has_modrm or twobyte_has_modrm. */
1954#define MODRM_CHECK if (!need_modrm) abort ()
1955
d708bcba
AM		 1956static const char **names64;
1957static const char **names32;
1958static const char **names16;
1959static const char **names8;
1960static const char **names8rex;
1961static const char **names_seg;
db51cc60
L		 1962static const char *index64;
1963static const char *index32;
d708bcba
AM		 1964static const char **index16;
1965
1966static const char *intel_names64[] = {
1967 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
1968 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
1969};
1970static const char *intel_names32[] = {
1971 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
1972 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
1973};
1974static const char *intel_names16[] = {
1975 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
1976 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
1977};
1978static const char *intel_names8[] = {
1979 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
1980};
1981static const char *intel_names8rex[] = {
1982 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
1983 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
1984};
1985static const char *intel_names_seg[] = {
1986 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
1987};
db51cc60
L		 1988static const char *intel_index64 = "riz";
1989static const char *intel_index32 = "eiz";
d708bcba
AM		 1990static const char *intel_index16[] = {
1991 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
1992};
1993
1994static const char *att_names64[] = {
1995 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
52b15da3
JH		 1996 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
1997};
d708bcba
AM		 1998static const char *att_names32[] = {
1999 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
52b15da3 2000 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
252b5132 2001};
d708bcba
AM		 2002static const char *att_names16[] = {
2003 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
52b15da3 2004 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
252b5132 2005};
d708bcba
AM		 2006static const char *att_names8[] = {
2007 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
252b5132 2008};
d708bcba
AM		 2009static const char *att_names8rex[] = {
2010 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
52b15da3
JH		 2011 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2012};
d708bcba
AM		 2013static const char *att_names_seg[] = {
2014 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
252b5132 2015};
db51cc60
L		 2016static const char *att_index64 = "%riz";
2017static const char *att_index32 = "%eiz";
d708bcba
AM		 2018static const char *att_index16[] = {
2019 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
252b5132
RH		 2020};
2021
1ceb70f8
L		 2022static const struct dis386 reg_table[][8] = {
2023 /* REG_80 */
252b5132 2024 {
ce518a5f
L		 2025 { "addA", { Eb, Ib } },
2026 { "orA", { Eb, Ib } },
2027 { "adcA", { Eb, Ib } },
2028 { "sbbA", { Eb, Ib } },
2029 { "andA", { Eb, Ib } },
2030 { "subA", { Eb, Ib } },
2031 { "xorA", { Eb, Ib } },
2032 { "cmpA", { Eb, Ib } },
252b5132 2033 },
1ceb70f8 2034 /* REG_81 */
252b5132 2035 {
ce518a5f
L		 2036 { "addQ", { Ev, Iv } },
2037 { "orQ", { Ev, Iv } },
2038 { "adcQ", { Ev, Iv } },
2039 { "sbbQ", { Ev, Iv } },
2040 { "andQ", { Ev, Iv } },
2041 { "subQ", { Ev, Iv } },
2042 { "xorQ", { Ev, Iv } },
2043 { "cmpQ", { Ev, Iv } },
252b5132 2044 },
1ceb70f8 2045 /* REG_82 */
252b5132 2046 {
ce518a5f
L		 2047 { "addQ", { Ev, sIb } },
2048 { "orQ", { Ev, sIb } },
2049 { "adcQ", { Ev, sIb } },
2050 { "sbbQ", { Ev, sIb } },
2051 { "andQ", { Ev, sIb } },
2052 { "subQ", { Ev, sIb } },
2053 { "xorQ", { Ev, sIb } },
2054 { "cmpQ", { Ev, sIb } },
252b5132 2055 },
1ceb70f8 2056 /* REG_8F */
4e7d34a6
L		 2057 {
2058 { "popU", { stackEv } },
2059 { "(bad)", { XX } },
2060 { "(bad)", { XX } },
2061 { "(bad)", { XX } },
2062 { "(bad)", { XX } },
2063 { "(bad)", { XX } },
2064 { "(bad)", { XX } },
2065 { "(bad)", { XX } },
2066 },
1ceb70f8 2067 /* REG_C0 */
252b5132 2068 {
ce518a5f
L		 2069 { "rolA", { Eb, Ib } },
2070 { "rorA", { Eb, Ib } },
2071 { "rclA", { Eb, Ib } },
2072 { "rcrA", { Eb, Ib } },
2073 { "shlA", { Eb, Ib } },
2074 { "shrA", { Eb, Ib } },
2075 { "(bad)", { XX } },
2076 { "sarA", { Eb, Ib } },
252b5132 2077 },
1ceb70f8 2078 /* REG_C1 */
252b5132 2079 {
ce518a5f
L		 2080 { "rolQ", { Ev, Ib } },
2081 { "rorQ", { Ev, Ib } },
2082 { "rclQ", { Ev, Ib } },
2083 { "rcrQ", { Ev, Ib } },
2084 { "shlQ", { Ev, Ib } },
2085 { "shrQ", { Ev, Ib } },
2086 { "(bad)", { XX } },
2087 { "sarQ", { Ev, Ib } },
252b5132 2088 },
1ceb70f8 2089 /* REG_C6 */
4e7d34a6
L		 2090 {
2091 { "movA", { Eb, Ib } },
2092 { "(bad)", { XX } },
2093 { "(bad)", { XX } },
2094 { "(bad)", { XX } },
2095 { "(bad)", { XX } },
2096 { "(bad)", { XX } },
2097 { "(bad)", { XX } },
2098 { "(bad)", { XX } },
2099 },
1ceb70f8 2100 /* REG_C7 */
4e7d34a6
L		 2101 {
2102 { "movQ", { Ev, Iv } },
2103 { "(bad)", { XX } },
2104 { "(bad)", { XX } },
2105 { "(bad)", { XX } },
2106 { "(bad)", { XX } },
2107 { "(bad)", { XX } },
2108 { "(bad)", { XX } },
2109 { "(bad)", { XX } },
2110 },
1ceb70f8 2111 /* REG_D0 */
252b5132 2112 {
ce518a5f
L		 2113 { "rolA", { Eb, I1 } },
2114 { "rorA", { Eb, I1 } },
2115 { "rclA", { Eb, I1 } },
2116 { "rcrA", { Eb, I1 } },
2117 { "shlA", { Eb, I1 } },
2118 { "shrA", { Eb, I1 } },
2119 { "(bad)", { XX } },
2120 { "sarA", { Eb, I1 } },
252b5132 2121 },
1ceb70f8 2122 /* REG_D1 */
252b5132 2123 {
ce518a5f
L		 2124 { "rolQ", { Ev, I1 } },
2125 { "rorQ", { Ev, I1 } },
2126 { "rclQ", { Ev, I1 } },
2127 { "rcrQ", { Ev, I1 } },
2128 { "shlQ", { Ev, I1 } },
2129 { "shrQ", { Ev, I1 } },
2130 { "(bad)", { XX } },
2131 { "sarQ", { Ev, I1 } },
252b5132 2132 },
1ceb70f8 2133 /* REG_D2 */
252b5132 2134 {
ce518a5f
L		 2135 { "rolA", { Eb, CL } },
2136 { "rorA", { Eb, CL } },
2137 { "rclA", { Eb, CL } },
2138 { "rcrA", { Eb, CL } },
2139 { "shlA", { Eb, CL } },
2140 { "shrA", { Eb, CL } },
2141 { "(bad)", { XX } },
2142 { "sarA", { Eb, CL } },
252b5132 2143 },
1ceb70f8 2144 /* REG_D3 */
252b5132 2145 {
ce518a5f
L		 2146 { "rolQ", { Ev, CL } },
2147 { "rorQ", { Ev, CL } },
2148 { "rclQ", { Ev, CL } },
2149 { "rcrQ", { Ev, CL } },
2150 { "shlQ", { Ev, CL } },
2151 { "shrQ", { Ev, CL } },
2152 { "(bad)", { XX } },
2153 { "sarQ", { Ev, CL } },
252b5132 2154 },
1ceb70f8 2155 /* REG_F6 */
252b5132 2156 {
ce518a5f 2157 { "testA", { Eb, Ib } },
058f233b 2158 { "(bad)", { XX } },
ce518a5f
L		 2159 { "notA", { Eb } },
2160 { "negA", { Eb } },
2161 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
2162 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
2163 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
2164 { "idivA", { Eb } }, /* and idiv for consistency. */
252b5132 2165 },
1ceb70f8 2166 /* REG_F7 */
252b5132 2167 {
ce518a5f
L		 2168 { "testQ", { Ev, Iv } },
2169 { "(bad)", { XX } },
2170 { "notQ", { Ev } },
2171 { "negQ", { Ev } },
2172 { "mulQ", { Ev } }, /* Don't print the implicit register. */
2173 { "imulQ", { Ev } },
2174 { "divQ", { Ev } },
2175 { "idivQ", { Ev } },
252b5132 2176 },
1ceb70f8 2177 /* REG_FE */
252b5132 2178 {
ce518a5f
L		 2179 { "incA", { Eb } },
2180 { "decA", { Eb } },
2181 { "(bad)", { XX } },
2182 { "(bad)", { XX } },
2183 { "(bad)", { XX } },
2184 { "(bad)", { XX } },
2185 { "(bad)", { XX } },
2186 { "(bad)", { XX } },
252b5132 2187 },
1ceb70f8 2188 /* REG_FF */
252b5132 2189 {
ce518a5f
L		 2190 { "incQ", { Ev } },
2191 { "decQ", { Ev } },
2192 { "callT", { indirEv } },
2193 { "JcallT", { indirEp } },
2194 { "jmpT", { indirEv } },
2195 { "JjmpT", { indirEp } },
2196 { "pushU", { stackEv } },
2197 { "(bad)", { XX } },
252b5132 2198 },
1ceb70f8 2199 /* REG_0F00 */
252b5132 2200 {
ce518a5f
L		 2201 { "sldtD", { Sv } },
2202 { "strD", { Sv } },
2203 { "lldt", { Ew } },
2204 { "ltr", { Ew } },
2205 { "verr", { Ew } },
2206 { "verw", { Ew } },
2207 { "(bad)", { XX } },
2208 { "(bad)", { XX } },
252b5132 2209 },
1ceb70f8 2210 /* REG_0F01 */
252b5132 2211 {
1ceb70f8
L		 2212 { MOD_TABLE (MOD_0F01_REG_0) },
2213 { MOD_TABLE (MOD_0F01_REG_1) },
2214 { MOD_TABLE (MOD_0F01_REG_2) },
2215 { MOD_TABLE (MOD_0F01_REG_3) },
ce518a5f
L		 2216 { "smswD", { Sv } },
2217 { "(bad)", { XX } },
2218 { "lmsw", { Ew } },
1ceb70f8 2219 { MOD_TABLE (MOD_0F01_REG_7) },
252b5132 2220 },
b5b1fc4f 2221 /* REG_0F0D */
252b5132 2222 {
4e7d34a6
L		 2223 { "prefetch", { Eb } },
2224 { "prefetchw", { Eb } },
2225 { "(bad)", { XX } },
2226 { "(bad)", { XX } },
2227 { "(bad)", { XX } },
2228 { "(bad)", { XX } },
2229 { "(bad)", { XX } },
2230 { "(bad)", { XX } },
252b5132 2231 },
1ceb70f8 2232 /* REG_0F18 */
252b5132 2233 {
1ceb70f8
L		 2234 { MOD_TABLE (MOD_0F18_REG_0) },
2235 { MOD_TABLE (MOD_0F18_REG_1) },
2236 { MOD_TABLE (MOD_0F18_REG_2) },
2237 { MOD_TABLE (MOD_0F18_REG_3) },
ce518a5f
L		 2238 { "(bad)", { XX } },
2239 { "(bad)", { XX } },
2240 { "(bad)", { XX } },
2241 { "(bad)", { XX } },
252b5132 2242 },
1ceb70f8 2243 /* REG_0F71 */
a6bd098c 2244 {
ce518a5f
L		 2245 { "(bad)", { XX } },
2246 { "(bad)", { XX } },
1ceb70f8 2247 { MOD_TABLE (MOD_0F71_REG_2) },
ce518a5f 2248 { "(bad)", { XX } },
1ceb70f8 2249 { MOD_TABLE (MOD_0F71_REG_4) },
ce518a5f 2250 { "(bad)", { XX } },
1ceb70f8 2251 { MOD_TABLE (MOD_0F71_REG_6) },
ce518a5f 2252 { "(bad)", { XX } },
a6bd098c 2253 },
1ceb70f8 2254 /* REG_0F72 */
a6bd098c 2255 {
ce518a5f
L		 2256 { "(bad)", { XX } },
2257 { "(bad)", { XX } },
1ceb70f8 2258 { MOD_TABLE (MOD_0F72_REG_2) },
ce518a5f 2259 { "(bad)", { XX } },
1ceb70f8 2260 { MOD_TABLE (MOD_0F72_REG_4) },
ce518a5f 2261 { "(bad)", { XX } },
1ceb70f8 2262 { MOD_TABLE (MOD_0F72_REG_6) },
ce518a5f 2263 { "(bad)", { XX } },
a6bd098c 2264 },
1ceb70f8 2265 /* REG_0F73 */
252b5132 2266 {
ce518a5f
L		 2267 { "(bad)", { XX } },
2268 { "(bad)", { XX } },
1ceb70f8
L		 2269 { MOD_TABLE (MOD_0F73_REG_2) },
2270 { MOD_TABLE (MOD_0F73_REG_3) },
ce518a5f 2271 { "(bad)", { XX } },
ce518a5f 2272 { "(bad)", { XX } },
1ceb70f8
L		 2273 { MOD_TABLE (MOD_0F73_REG_6) },
2274 { MOD_TABLE (MOD_0F73_REG_7) },
252b5132 2275 },
1ceb70f8 2276 /* REG_0FA6 */
252b5132 2277 {
4e7d34a6
L		 2278 { "montmul", { { OP_0f07, 0 } } },
2279 { "xsha1", { { OP_0f07, 0 } } },
2280 { "xsha256", { { OP_0f07, 0 } } },
2281 { "(bad)", { { OP_0f07, 0 } } },
2282 { "(bad)", { { OP_0f07, 0 } } },
2283 { "(bad)", { { OP_0f07, 0 } } },
2284 { "(bad)", { { OP_0f07, 0 } } },
2285 { "(bad)", { { OP_0f07, 0 } } },
2286 },
1ceb70f8 2287 /* REG_0FA7 */
4e7d34a6
L		 2288 {
2289 { "xstore-rng", { { OP_0f07, 0 } } },
2290 { "xcrypt-ecb", { { OP_0f07, 0 } } },
2291 { "xcrypt-cbc", { { OP_0f07, 0 } } },
2292 { "xcrypt-ctr", { { OP_0f07, 0 } } },
2293 { "xcrypt-cfb", { { OP_0f07, 0 } } },
2294 { "xcrypt-ofb", { { OP_0f07, 0 } } },
2295 { "(bad)", { { OP_0f07, 0 } } },
2296 { "(bad)", { { OP_0f07, 0 } } },
2297 },
1ceb70f8 2298 /* REG_0FAE */
4e7d34a6 2299 {
1ceb70f8
L		 2300 { MOD_TABLE (MOD_0FAE_REG_0) },
2301 { MOD_TABLE (MOD_0FAE_REG_1) },
2302 { MOD_TABLE (MOD_0FAE_REG_2) },
2303 { MOD_TABLE (MOD_0FAE_REG_3) },
475a2301 2304 { MOD_TABLE (MOD_0FAE_REG_4) },
1ceb70f8
L		 2305 { MOD_TABLE (MOD_0FAE_REG_5) },
2306 { MOD_TABLE (MOD_0FAE_REG_6) },
2307 { MOD_TABLE (MOD_0FAE_REG_7) },
252b5132 2308 },
1ceb70f8 2309 /* REG_0FBA */
252b5132 2310 {
ce518a5f
L		 2311 { "(bad)", { XX } },
2312 { "(bad)", { XX } },
d8faab4e
L		 2313 { "(bad)", { XX } },
2314 { "(bad)", { XX } },
4e7d34a6
L		 2315 { "btQ", { Ev, Ib } },
2316 { "btsQ", { Ev, Ib } },
2317 { "btrQ", { Ev, Ib } },
2318 { "btcQ", { Ev, Ib } },
c608c12e 2319 },
1ceb70f8 2320 /* REG_0FC7 */
c608c12e 2321 {
b844680a 2322 { "(bad)", { XX } },
4e7d34a6 2323 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
d8faab4e 2324 { "(bad)", { XX } },
b844680a
L		 2325 { "(bad)", { XX } },
2326 { "(bad)", { XX } },
2327 { "(bad)", { XX } },
1ceb70f8
L		 2328 { MOD_TABLE (MOD_0FC7_REG_6) },
2329 { MOD_TABLE (MOD_0FC7_REG_7) },
252b5132 2330 },
c0f3af97
L		 2331 /* REG_VEX_71 */
2332 {
2333 { "(bad)", { XX } },
2334 { "(bad)", { XX } },
2335 { MOD_TABLE (MOD_VEX_71_REG_2) },
2336 { "(bad)", { XX } },
2337 { MOD_TABLE (MOD_VEX_71_REG_4) },
2338 { "(bad)", { XX } },
2339 { MOD_TABLE (MOD_VEX_71_REG_6) },
2340 { "(bad)", { XX } },
2341 },
2342 /* REG_VEX_72 */
2343 {
2344 { "(bad)", { XX } },
2345 { "(bad)", { XX } },
2346 { MOD_TABLE (MOD_VEX_72_REG_2) },
2347 { "(bad)", { XX } },
2348 { MOD_TABLE (MOD_VEX_72_REG_4) },
2349 { "(bad)", { XX } },
2350 { MOD_TABLE (MOD_VEX_72_REG_6) },
2351 { "(bad)", { XX } },
2352 },
2353 /* REG_VEX_73 */
2354 {
2355 { "(bad)", { XX } },
2356 { "(bad)", { XX } },
2357 { MOD_TABLE (MOD_VEX_73_REG_2) },
2358 { MOD_TABLE (MOD_VEX_73_REG_3) },
2359 { "(bad)", { XX } },
2360 { "(bad)", { XX } },
2361 { MOD_TABLE (MOD_VEX_73_REG_6) },
2362 { MOD_TABLE (MOD_VEX_73_REG_7) },
2363 },
2364 /* REG_VEX_AE */
2365 {
2366 { "(bad)", { XX } },
2367 { "(bad)", { XX } },
2368 { MOD_TABLE (MOD_VEX_AE_REG_2) },
2369 { MOD_TABLE (MOD_VEX_AE_REG_3) },
2370 { "(bad)", { XX } },
2371 { "(bad)", { XX } },
2372 { "(bad)", { XX } },
2373 { "(bad)", { XX } },
2374 },
4e7d34a6
L		 2375};
2376
1ceb70f8
L		 2377static const struct dis386 prefix_table[][4] = {
2378 /* PREFIX_90 */
252b5132 2379 {
4e7d34a6
L		 2380 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2381 { "pause", { XX } },
2382 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2383 { "(bad)", { XX } },
0f10071e 2384 },
4e7d34a6 2385
1ceb70f8 2386 /* PREFIX_0F10 */
cc0ec051 2387 {
4e7d34a6
L		 2388 { "movups", { XM, EXx } },
2389 { "movss", { XM, EXd } },
2390 { "movupd", { XM, EXx } },
2391 { "movsd", { XM, EXq } },
30d1c836 2392 },
4e7d34a6 2393
1ceb70f8 2394 /* PREFIX_0F11 */
30d1c836 2395 {
d5d7db8e
L		 2396 { "movups", { EXx, XM } },
2397 { "movss", { EXd, XM } },
2398 { "movupd", { EXx, XM } },
2399 { "movsd", { EXq, XM } },
4e7d34a6 2400 },
252b5132 2401
1ceb70f8 2402 /* PREFIX_0F12 */
c608c12e 2403 {
1ceb70f8 2404 { MOD_TABLE (MOD_0F12_PREFIX_0) },
4e7d34a6
L		 2405 { "movsldup", { XM, EXx } },
2406 { "movlpd", { XM, EXq } },
2407 { "movddup", { XM, EXq } },
c608c12e 2408 },
4e7d34a6 2409
1ceb70f8 2410 /* PREFIX_0F16 */
c608c12e 2411 {
1ceb70f8 2412 { MOD_TABLE (MOD_0F16_PREFIX_0) },
4e7d34a6
L		 2413 { "movshdup", { XM, EXx } },
2414 { "movhpd", { XM, EXq } },
058f233b 2415 { "(bad)", { XX } },
c608c12e 2416 },
4e7d34a6 2417
1ceb70f8 2418 /* PREFIX_0F2A */
c608c12e 2419 {
09335d05 2420 { "cvtpi2ps", { XM, EMCq } },
98b528ac 2421 { "cvtsi2ss%LQ", { XM, Ev } },
09335d05 2422 { "cvtpi2pd", { XM, EMCq } },
98b528ac 2423 { "cvtsi2sd%LQ", { XM, Ev } },
c608c12e 2424 },
4e7d34a6 2425
1ceb70f8 2426 /* PREFIX_0F2B */
c608c12e 2427 {
75c135a8
L		 2428 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2429 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2430 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2431 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
c608c12e 2432 },
4e7d34a6 2433
1ceb70f8 2434 /* PREFIX_0F2C */
c608c12e 2435 {
09335d05
L		 2436 { "cvttps2pi", { MXC, EXq } },
2437 { "cvttss2siY", { Gv, EXd } },
09a2c6cf 2438 { "cvttpd2pi", { MXC, EXx } },
09335d05 2439 { "cvttsd2siY", { Gv, EXq } },
c608c12e 2440 },
4e7d34a6 2441
1ceb70f8 2442 /* PREFIX_0F2D */
c608c12e 2443 {
4e7d34a6
L		 2444 { "cvtps2pi", { MXC, EXq } },
2445 { "cvtss2siY", { Gv, EXd } },
2446 { "cvtpd2pi", { MXC, EXx } },
2447 { "cvtsd2siY", { Gv, EXq } },
c608c12e 2448 },
4e7d34a6 2449
1ceb70f8 2450 /* PREFIX_0F2E */
c608c12e 2451 {
4e7d34a6
L		 2452 { "ucomiss",{ XM, EXd } },
2453 { "(bad)", { XX } },
2454 { "ucomisd",{ XM, EXq } },
2455 { "(bad)", { XX } },
c608c12e 2456 },
4e7d34a6 2457
1ceb70f8 2458 /* PREFIX_0F2F */
c608c12e 2459 {
4e7d34a6
L		 2460 { "comiss", { XM, EXd } },
2461 { "(bad)", { XX } },
2462 { "comisd", { XM, EXq } },
2463 { "(bad)", { XX } },
c608c12e 2464 },
4e7d34a6 2465
1ceb70f8 2466 /* PREFIX_0F51 */
c608c12e 2467 {
4e7d34a6
L		 2468 { "sqrtps", { XM, EXx } },
2469 { "sqrtss", { XM, EXd } },
2470 { "sqrtpd", { XM, EXx } },
2471 { "sqrtsd", { XM, EXq } },
c608c12e 2472 },
4e7d34a6 2473
1ceb70f8 2474 /* PREFIX_0F52 */
c608c12e 2475 {
4e7d34a6
L		 2476 { "rsqrtps",{ XM, EXx } },
2477 { "rsqrtss",{ XM, EXd } },
058f233b
L		 2478 { "(bad)", { XX } },
2479 { "(bad)", { XX } },
c608c12e 2480 },
4e7d34a6 2481
1ceb70f8 2482 /* PREFIX_0F53 */
c608c12e 2483 {
4e7d34a6
L		 2484 { "rcpps", { XM, EXx } },
2485 { "rcpss", { XM, EXd } },
058f233b
L		 2486 { "(bad)", { XX } },
2487 { "(bad)", { XX } },
c608c12e 2488 },
4e7d34a6 2489
1ceb70f8 2490 /* PREFIX_0F58 */
c608c12e 2491 {
4e7d34a6
L		 2492 { "addps", { XM, EXx } },
2493 { "addss", { XM, EXd } },
2494 { "addpd", { XM, EXx } },
2495 { "addsd", { XM, EXq } },
c608c12e 2496 },
4e7d34a6 2497
1ceb70f8 2498 /* PREFIX_0F59 */
c608c12e 2499 {
4e7d34a6
L		 2500 { "mulps", { XM, EXx } },
2501 { "mulss", { XM, EXd } },
2502 { "mulpd", { XM, EXx } },
2503 { "mulsd", { XM, EXq } },
041bd2e0 2504 },
4e7d34a6 2505
1ceb70f8 2506 /* PREFIX_0F5A */
041bd2e0 2507 {
4e7d34a6
L		 2508 { "cvtps2pd", { XM, EXq } },
2509 { "cvtss2sd", { XM, EXd } },
2510 { "cvtpd2ps", { XM, EXx } },
2511 { "cvtsd2ss", { XM, EXq } },
041bd2e0 2512 },
4e7d34a6 2513
1ceb70f8 2514 /* PREFIX_0F5B */
041bd2e0 2515 {
09a2c6cf
L		 2516 { "cvtdq2ps", { XM, EXx } },
2517 { "cvttps2dq", { XM, EXx } },
2518 { "cvtps2dq", { XM, EXx } },
058f233b 2519 { "(bad)", { XX } },
041bd2e0 2520 },
4e7d34a6 2521
1ceb70f8 2522 /* PREFIX_0F5C */
041bd2e0 2523 {
4e7d34a6
L		 2524 { "subps", { XM, EXx } },
2525 { "subss", { XM, EXd } },
2526 { "subpd", { XM, EXx } },
2527 { "subsd", { XM, EXq } },
041bd2e0 2528 },
4e7d34a6 2529
1ceb70f8 2530 /* PREFIX_0F5D */
041bd2e0 2531 {
4e7d34a6
L		 2532 { "minps", { XM, EXx } },
2533 { "minss", { XM, EXd } },
2534 { "minpd", { XM, EXx } },
2535 { "minsd", { XM, EXq } },
041bd2e0 2536 },
4e7d34a6 2537
1ceb70f8 2538 /* PREFIX_0F5E */
041bd2e0 2539 {
4e7d34a6
L		 2540 { "divps", { XM, EXx } },
2541 { "divss", { XM, EXd } },
2542 { "divpd", { XM, EXx } },
2543 { "divsd", { XM, EXq } },
041bd2e0 2544 },
4e7d34a6 2545
1ceb70f8 2546 /* PREFIX_0F5F */
041bd2e0 2547 {
4e7d34a6
L		 2548 { "maxps", { XM, EXx } },
2549 { "maxss", { XM, EXd } },
2550 { "maxpd", { XM, EXx } },
2551 { "maxsd", { XM, EXq } },
041bd2e0 2552 },
4e7d34a6 2553
1ceb70f8 2554 /* PREFIX_0F60 */
041bd2e0 2555 {
4e7d34a6
L		 2556 { "punpcklbw",{ MX, EMd } },
2557 { "(bad)", { XX } },
2558 { "punpcklbw",{ MX, EMx } },
2559 { "(bad)", { XX } },
041bd2e0 2560 },
4e7d34a6 2561
1ceb70f8 2562 /* PREFIX_0F61 */
041bd2e0 2563 {
4e7d34a6
L		 2564 { "punpcklwd",{ MX, EMd } },
2565 { "(bad)", { XX } },
2566 { "punpcklwd",{ MX, EMx } },
2567 { "(bad)", { XX } },
041bd2e0 2568 },
4e7d34a6 2569
1ceb70f8 2570 /* PREFIX_0F62 */
041bd2e0 2571 {
4e7d34a6
L		 2572 { "punpckldq",{ MX, EMd } },
2573 { "(bad)", { XX } },
2574 { "punpckldq",{ MX, EMx } },
2575 { "(bad)", { XX } },
041bd2e0 2576 },
4e7d34a6 2577
1ceb70f8 2578 /* PREFIX_0F6C */
041bd2e0 2579 {
058f233b
L		 2580 { "(bad)", { XX } },
2581 { "(bad)", { XX } },
4e7d34a6 2582 { "punpcklqdq", { XM, EXx } },
058f233b 2583 { "(bad)", { XX } },
0f17484f 2584 },
4e7d34a6 2585
1ceb70f8 2586 /* PREFIX_0F6D */
0f17484f 2587 {
058f233b
L		 2588 { "(bad)", { XX } },
2589 { "(bad)", { XX } },
4e7d34a6 2590 { "punpckhqdq", { XM, EXx } },
058f233b 2591 { "(bad)", { XX } },
041bd2e0 2592 },
4e7d34a6 2593
1ceb70f8 2594 /* PREFIX_0F6F */
ca164297 2595 {
4e7d34a6
L		 2596 { "movq", { MX, EM } },
2597 { "movdqu", { XM, EXx } },
2598 { "movdqa", { XM, EXx } },
058f233b 2599 { "(bad)", { XX } },
ca164297 2600 },
4e7d34a6 2601
1ceb70f8 2602 /* PREFIX_0F70 */
4e7d34a6
L		 2603 {
2604 { "pshufw", { MX, EM, Ib } },
2605 { "pshufhw",{ XM, EXx, Ib } },
2606 { "pshufd", { XM, EXx, Ib } },
2607 { "pshuflw",{ XM, EXx, Ib } },
2608 },
2609
92fddf8e
L		 2610 /* PREFIX_0F73_REG_3 */
2611 {
2612 { "(bad)", { XX } },
2613 { "(bad)", { XX } },
2614 { "psrldq", { XS, Ib } },
2615 { "(bad)", { XX } },
2616 },
2617
2618 /* PREFIX_0F73_REG_7 */
2619 {
2620 { "(bad)", { XX } },
2621 { "(bad)", { XX } },
2622 { "pslldq", { XS, Ib } },
2623 { "(bad)", { XX } },
2624 },
2625
1ceb70f8 2626 /* PREFIX_0F78 */
4e7d34a6
L		 2627 {
2628 {"vmread", { Em, Gm } },
2629 {"(bad)", { XX } },
2630 {"extrq", { XS, Ib, Ib } },
2631 {"insertq", { XM, XS, Ib, Ib } },
2632 },
2633
1ceb70f8 2634 /* PREFIX_0F79 */
4e7d34a6
L		 2635 {
2636 {"vmwrite", { Gm, Em } },
2637 {"(bad)", { XX } },
2638 {"extrq", { XM, XS } },
2639 {"insertq", { XM, XS } },
2640 },
2641
1ceb70f8 2642 /* PREFIX_0F7C */
ca164297 2643 {
058f233b
L		 2644 { "(bad)", { XX } },
2645 { "(bad)", { XX } },
09a2c6cf
L		 2646 { "haddpd", { XM, EXx } },
2647 { "haddps", { XM, EXx } },
ca164297 2648 },
4e7d34a6 2649
1ceb70f8 2650 /* PREFIX_0F7D */
ca164297 2651 {
058f233b
L		 2652 { "(bad)", { XX } },
2653 { "(bad)", { XX } },
09a2c6cf
L		 2654 { "hsubpd", { XM, EXx } },
2655 { "hsubps", { XM, EXx } },
ca164297 2656 },
4e7d34a6 2657
1ceb70f8 2658 /* PREFIX_0F7E */
ca164297 2659 {
4e7d34a6
L		 2660 { "movK", { Edq, MX } },
2661 { "movq", { XM, EXq } },
2662 { "movK", { Edq, XM } },
058f233b 2663 { "(bad)", { XX } },
ca164297 2664 },
4e7d34a6 2665
1ceb70f8 2666 /* PREFIX_0F7F */
ca164297 2667 {
4e7d34a6 2668 { "movq", { EM, MX } },
d5d7db8e
L		 2669 { "movdqu", { EXx, XM } },
2670 { "movdqa", { EXx, XM } },
058f233b 2671 { "(bad)", { XX } },
ca164297 2672 },
4e7d34a6 2673
1ceb70f8 2674 /* PREFIX_0FB8 */
ca164297 2675 {
4e7d34a6
L		 2676 { "(bad)", { XX } },
2677 { "popcntS", { Gv, Ev } },
2678 { "(bad)", { XX } },
2679 { "(bad)", { XX } },
ca164297 2680 },
4e7d34a6 2681
1ceb70f8 2682 /* PREFIX_0FBD */
050dfa73 2683 {
4e7d34a6
L		 2684 { "bsrS", { Gv, Ev } },
2685 { "lzcntS", { Gv, Ev } },
2686 { "bsrS", { Gv, Ev } },
2687 { "(bad)", { XX } },
050dfa73
MM		 2688 },
2689
1ceb70f8 2690 /* PREFIX_0FC2 */
050dfa73 2691 {
ad19981d
L		 2692 { "cmpps", { XM, EXx, CMP } },
2693 { "cmpss", { XM, EXd, CMP } },
2694 { "cmppd", { XM, EXx, CMP } },
2695 { "cmpsd", { XM, EXq, CMP } },
050dfa73 2696 },
246c51aa 2697
4ee52178
L		 2698 /* PREFIX_0FC3 */
2699 {
2700 { "movntiS", { Ma, Gv } },
2701 { "(bad)", { XX } },
2702 { "(bad)", { XX } },
2703 { "(bad)", { XX } },
2704 },
2705
92fddf8e
L		 2706 /* PREFIX_0FC7_REG_6 */
2707 {
2708 { "vmptrld",{ Mq } },
2709 { "vmxon", { Mq } },
2710 { "vmclear",{ Mq } },
2711 { "(bad)", { XX } },
2712 },
2713
1ceb70f8 2714 /* PREFIX_0FD0 */
050dfa73 2715 {
058f233b
L		 2716 { "(bad)", { XX } },
2717 { "(bad)", { XX } },
4e7d34a6
L		 2718 { "addsubpd", { XM, EXx } },
2719 { "addsubps", { XM, EXx } },
246c51aa 2720 },
050dfa73 2721
1ceb70f8 2722 /* PREFIX_0FD6 */
050dfa73 2723 {
058f233b 2724 { "(bad)", { XX } },
4e7d34a6
L		 2725 { "movq2dq",{ XM, MS } },
2726 { "movq", { EXq, XM } },
2727 { "movdq2q",{ MX, XS } },
050dfa73
MM		 2728 },
2729
1ceb70f8 2730 /* PREFIX_0FE6 */
7918206c 2731 {
058f233b 2732 { "(bad)", { XX } },
4e7d34a6
L		 2733 { "cvtdq2pd", { XM, EXq } },
2734 { "cvttpd2dq", { XM, EXx } },
2735 { "cvtpd2dq", { XM, EXx } },
7918206c 2736 },
8b38ad71 2737
1ceb70f8 2738 /* PREFIX_0FE7 */
8b38ad71 2739 {
4ee52178 2740 { "movntq", { Mq, MX } },
058f233b 2741 { "(bad)", { XX } },
75c135a8 2742 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
058f233b 2743 { "(bad)", { XX } },
4e7d34a6
L		 2744 },
2745
1ceb70f8 2746 /* PREFIX_0FF0 */
4e7d34a6 2747 {
058f233b
L		 2748 { "(bad)", { XX } },
2749 { "(bad)", { XX } },
2750 { "(bad)", { XX } },
1ceb70f8 2751 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4e7d34a6
L		 2752 },
2753
1ceb70f8 2754 /* PREFIX_0FF7 */
4e7d34a6
L		 2755 {
2756 { "maskmovq", { MX, MS } },
058f233b 2757 { "(bad)", { XX } },
4e7d34a6 2758 { "maskmovdqu", { XM, XS } },
058f233b 2759 { "(bad)", { XX } },
8b38ad71 2760 },
42903f7f 2761
1ceb70f8 2762 /* PREFIX_0F3810 */
42903f7f
L		 2763 {
2764 { "(bad)", { XX } },
2765 { "(bad)", { XX } },
88a94849 2766 { "pblendvb", { XM, EXx, XMM0 } },
42903f7f
L		 2767 { "(bad)", { XX } },
2768 },
2769
1ceb70f8 2770 /* PREFIX_0F3814 */
42903f7f
L		 2771 {
2772 { "(bad)", { XX } },
2773 { "(bad)", { XX } },
88a94849 2774 { "blendvps", { XM, EXx, XMM0 } },
42903f7f
L		 2775 { "(bad)", { XX } },
2776 },
2777
1ceb70f8 2778 /* PREFIX_0F3815 */
42903f7f
L		 2779 {
2780 { "(bad)", { XX } },
2781 { "(bad)", { XX } },
09a2c6cf 2782 { "blendvpd", { XM, EXx, XMM0 } },
42903f7f
L		 2783 { "(bad)", { XX } },
2784 },
2785
1ceb70f8 2786 /* PREFIX_0F3817 */
42903f7f
L		 2787 {
2788 { "(bad)", { XX } },
2789 { "(bad)", { XX } },
09a2c6cf 2790 { "ptest", { XM, EXx } },
42903f7f
L		 2791 { "(bad)", { XX } },
2792 },
2793
1ceb70f8 2794 /* PREFIX_0F3820 */
42903f7f
L		 2795 {
2796 { "(bad)", { XX } },
2797 { "(bad)", { XX } },
8976381e 2798 { "pmovsxbw", { XM, EXq } },
42903f7f
L		 2799 { "(bad)", { XX } },
2800 },
2801
1ceb70f8 2802 /* PREFIX_0F3821 */
42903f7f
L		 2803 {
2804 { "(bad)", { XX } },
2805 { "(bad)", { XX } },
8976381e 2806 { "pmovsxbd", { XM, EXd } },
42903f7f
L		 2807 { "(bad)", { XX } },
2808 },
2809
1ceb70f8 2810 /* PREFIX_0F3822 */
42903f7f
L		 2811 {
2812 { "(bad)", { XX } },
2813 { "(bad)", { XX } },
8976381e 2814 { "pmovsxbq", { XM, EXw } },
42903f7f
L		 2815 { "(bad)", { XX } },
2816 },
2817
1ceb70f8 2818 /* PREFIX_0F3823 */
42903f7f
L		 2819 {
2820 { "(bad)", { XX } },
2821 { "(bad)", { XX } },
8976381e 2822 { "pmovsxwd", { XM, EXq } },
42903f7f
L		 2823 { "(bad)", { XX } },
2824 },
2825
1ceb70f8 2826 /* PREFIX_0F3824 */
42903f7f
L		 2827 {
2828 { "(bad)", { XX } },
2829 { "(bad)", { XX } },
8976381e 2830 { "pmovsxwq", { XM, EXd } },
42903f7f
L		 2831 { "(bad)", { XX } },
2832 },
2833
1ceb70f8 2834 /* PREFIX_0F3825 */
42903f7f
L		 2835 {
2836 { "(bad)", { XX } },
2837 { "(bad)", { XX } },
8976381e 2838 { "pmovsxdq", { XM, EXq } },
42903f7f
L		 2839 { "(bad)", { XX } },
2840 },
2841
1ceb70f8 2842 /* PREFIX_0F3828 */
42903f7f
L		 2843 {
2844 { "(bad)", { XX } },
2845 { "(bad)", { XX } },
09a2c6cf 2846 { "pmuldq", { XM, EXx } },
42903f7f
L		 2847 { "(bad)", { XX } },
2848 },
2849
1ceb70f8 2850 /* PREFIX_0F3829 */
42903f7f
L		 2851 {
2852 { "(bad)", { XX } },
2853 { "(bad)", { XX } },
09a2c6cf 2854 { "pcmpeqq", { XM, EXx } },
42903f7f
L		 2855 { "(bad)", { XX } },
2856 },
2857
1ceb70f8 2858 /* PREFIX_0F382A */
42903f7f
L		 2859 {
2860 { "(bad)", { XX } },
2861 { "(bad)", { XX } },
75c135a8 2862 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
42903f7f
L		 2863 { "(bad)", { XX } },
2864 },
2865
1ceb70f8 2866 /* PREFIX_0F382B */
42903f7f
L		 2867 {
2868 { "(bad)", { XX } },
2869 { "(bad)", { XX } },
09a2c6cf 2870 { "packusdw", { XM, EXx } },
42903f7f
L		 2871 { "(bad)", { XX } },
2872 },
2873
1ceb70f8 2874 /* PREFIX_0F3830 */
42903f7f
L		 2875 {
2876 { "(bad)", { XX } },
2877 { "(bad)", { XX } },
8976381e 2878 { "pmovzxbw", { XM, EXq } },
42903f7f
L		 2879 { "(bad)", { XX } },
2880 },
2881
1ceb70f8 2882 /* PREFIX_0F3831 */
42903f7f
L		 2883 {
2884 { "(bad)", { XX } },
2885 { "(bad)", { XX } },
8976381e 2886 { "pmovzxbd", { XM, EXd } },
42903f7f
L		 2887 { "(bad)", { XX } },
2888 },
2889
1ceb70f8 2890 /* PREFIX_0F3832 */
42903f7f
L		 2891 {
2892 { "(bad)", { XX } },
2893 { "(bad)", { XX } },
8976381e 2894 { "pmovzxbq", { XM, EXw } },
42903f7f
L		 2895 { "(bad)", { XX } },
2896 },
2897
1ceb70f8 2898 /* PREFIX_0F3833 */
42903f7f
L		 2899 {
2900 { "(bad)", { XX } },
2901 { "(bad)", { XX } },
8976381e 2902 { "pmovzxwd", { XM, EXq } },
42903f7f
L		 2903 { "(bad)", { XX } },
2904 },
2905
1ceb70f8 2906 /* PREFIX_0F3834 */
42903f7f
L		 2907 {
2908 { "(bad)", { XX } },
2909 { "(bad)", { XX } },
8976381e 2910 { "pmovzxwq", { XM, EXd } },
42903f7f
L		 2911 { "(bad)", { XX } },
2912 },
2913
1ceb70f8 2914 /* PREFIX_0F3835 */
42903f7f
L		 2915 {
2916 { "(bad)", { XX } },
2917 { "(bad)", { XX } },
8976381e 2918 { "pmovzxdq", { XM, EXq } },
42903f7f
L		 2919 { "(bad)", { XX } },
2920 },
2921
1ceb70f8 2922 /* PREFIX_0F3837 */
4e7d34a6
L		 2923 {
2924 { "(bad)", { XX } },
2925 { "(bad)", { XX } },
2926 { "pcmpgtq", { XM, EXx } },
2927 { "(bad)", { XX } },
2928 },
2929
1ceb70f8 2930 /* PREFIX_0F3838 */
42903f7f
L		 2931 {
2932 { "(bad)", { XX } },
2933 { "(bad)", { XX } },
09a2c6cf 2934 { "pminsb", { XM, EXx } },
42903f7f
L		 2935 { "(bad)", { XX } },
2936 },
2937
1ceb70f8 2938 /* PREFIX_0F3839 */
42903f7f
L		 2939 {
2940 { "(bad)", { XX } },
2941 { "(bad)", { XX } },
09a2c6cf 2942 { "pminsd", { XM, EXx } },
42903f7f
L		 2943 { "(bad)", { XX } },
2944 },
2945
1ceb70f8 2946 /* PREFIX_0F383A */
42903f7f
L		 2947 {
2948 { "(bad)", { XX } },
2949 { "(bad)", { XX } },
09a2c6cf 2950 { "pminuw", { XM, EXx } },
42903f7f
L		 2951 { "(bad)", { XX } },
2952 },
2953
1ceb70f8 2954 /* PREFIX_0F383B */
42903f7f
L		 2955 {
2956 { "(bad)", { XX } },
2957 { "(bad)", { XX } },
09a2c6cf 2958 { "pminud", { XM, EXx } },
42903f7f
L		 2959 { "(bad)", { XX } },
2960 },
2961
1ceb70f8 2962 /* PREFIX_0F383C */
42903f7f
L		 2963 {
2964 { "(bad)", { XX } },
2965 { "(bad)", { XX } },
09a2c6cf 2966 { "pmaxsb", { XM, EXx } },
42903f7f
L		 2967 { "(bad)", { XX } },
2968 },
2969
1ceb70f8 2970 /* PREFIX_0F383D */
42903f7f
L		 2971 {
2972 { "(bad)", { XX } },
2973 { "(bad)", { XX } },
09a2c6cf 2974 { "pmaxsd", { XM, EXx } },
42903f7f
L		 2975 { "(bad)", { XX } },
2976 },
2977
1ceb70f8 2978 /* PREFIX_0F383E */
42903f7f
L		 2979 {
2980 { "(bad)", { XX } },
2981 { "(bad)", { XX } },
09a2c6cf 2982 { "pmaxuw", { XM, EXx } },
42903f7f
L		 2983 { "(bad)", { XX } },
2984 },
2985
1ceb70f8 2986 /* PREFIX_0F383F */
42903f7f
L		 2987 {
2988 { "(bad)", { XX } },
2989 { "(bad)", { XX } },
09a2c6cf 2990 { "pmaxud", { XM, EXx } },
42903f7f
L		 2991 { "(bad)", { XX } },
2992 },
2993
1ceb70f8 2994 /* PREFIX_0F3840 */
42903f7f
L		 2995 {
2996 { "(bad)", { XX } },
2997 { "(bad)", { XX } },
09a2c6cf 2998 { "pmulld", { XM, EXx } },
42903f7f
L		 2999 { "(bad)", { XX } },
3000 },
3001
1ceb70f8 3002 /* PREFIX_0F3841 */
42903f7f
L		 3003 {
3004 { "(bad)", { XX } },
3005 { "(bad)", { XX } },
09a2c6cf 3006 { "phminposuw", { XM, EXx } },
42903f7f
L		 3007 { "(bad)", { XX } },
3008 },
3009
f1f8f695
L		 3010 /* PREFIX_0F3880 */
3011 {
3012 { "(bad)", { XX } },
3013 { "(bad)", { XX } },
3014 { "invept", { Gm, Mo } },
3015 { "(bad)", { XX } },
3016 },
3017
3018 /* PREFIX_0F3881 */
3019 {
3020 { "(bad)", { XX } },
3021 { "(bad)", { XX } },
3022 { "invvpid", { Gm, Mo } },
3023 { "(bad)", { XX } },
3024 },
3025
c0f3af97
L		 3026 /* PREFIX_0F38DB */
3027 {
3028 { "(bad)", { XX } },
3029 { "(bad)", { XX } },
3030 { "aesimc", { XM, EXx } },
3031 { "(bad)", { XX } },
3032 },
3033
3034 /* PREFIX_0F38DC */
3035 {
3036 { "(bad)", { XX } },
3037 { "(bad)", { XX } },
3038 { "aesenc", { XM, EXx } },
3039 { "(bad)", { XX } },
3040 },
3041
3042 /* PREFIX_0F38DD */
3043 {
3044 { "(bad)", { XX } },
3045 { "(bad)", { XX } },
3046 { "aesenclast", { XM, EXx } },
3047 { "(bad)", { XX } },
3048 },
3049
3050 /* PREFIX_0F38DE */
3051 {
3052 { "(bad)", { XX } },
3053 { "(bad)", { XX } },
3054 { "aesdec", { XM, EXx } },
3055 { "(bad)", { XX } },
3056 },
3057
3058 /* PREFIX_0F38DF */
3059 {
3060 { "(bad)", { XX } },
3061 { "(bad)", { XX } },
3062 { "aesdeclast", { XM, EXx } },
3063 { "(bad)", { XX } },
3064 },
3065
1ceb70f8 3066 /* PREFIX_0F38F0 */
4e7d34a6 3067 {
f1f8f695 3068 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4e7d34a6 3069 { "(bad)", { XX } },
f1f8f695 3070 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4e7d34a6
L		 3071 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
3072 },
3073
1ceb70f8 3074 /* PREFIX_0F38F1 */
4e7d34a6 3075 {
f1f8f695 3076 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4e7d34a6 3077 { "(bad)", { XX } },
f1f8f695 3078 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4e7d34a6
L		 3079 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
3080 },
3081
1ceb70f8 3082 /* PREFIX_0F3A08 */
42903f7f
L		 3083 {
3084 { "(bad)", { XX } },
3085 { "(bad)", { XX } },
09a2c6cf 3086 { "roundps", { XM, EXx, Ib } },
42903f7f
L		 3087 { "(bad)", { XX } },
3088 },
3089
1ceb70f8 3090 /* PREFIX_0F3A09 */
42903f7f
L		 3091 {
3092 { "(bad)", { XX } },
3093 { "(bad)", { XX } },
09a2c6cf 3094 { "roundpd", { XM, EXx, Ib } },
42903f7f
L		 3095 { "(bad)", { XX } },
3096 },
3097
1ceb70f8 3098 /* PREFIX_0F3A0A */
42903f7f
L		 3099 {
3100 { "(bad)", { XX } },
3101 { "(bad)", { XX } },
09335d05 3102 { "roundss", { XM, EXd, Ib } },
42903f7f
L		 3103 { "(bad)", { XX } },
3104 },
3105
1ceb70f8 3106 /* PREFIX_0F3A0B */
42903f7f
L		 3107 {
3108 { "(bad)", { XX } },
3109 { "(bad)", { XX } },
09335d05 3110 { "roundsd", { XM, EXq, Ib } },
42903f7f
L		 3111 { "(bad)", { XX } },
3112 },
3113
1ceb70f8 3114 /* PREFIX_0F3A0C */
42903f7f
L		 3115 {
3116 { "(bad)", { XX } },
3117 { "(bad)", { XX } },
09a2c6cf 3118 { "blendps", { XM, EXx, Ib } },
42903f7f
L		 3119 { "(bad)", { XX } },
3120 },
3121
1ceb70f8 3122 /* PREFIX_0F3A0D */
42903f7f
L		 3123 {
3124 { "(bad)", { XX } },
3125 { "(bad)", { XX } },
09a2c6cf 3126 { "blendpd", { XM, EXx, Ib } },
42903f7f
L		 3127 { "(bad)", { XX } },
3128 },
3129
1ceb70f8 3130 /* PREFIX_0F3A0E */
42903f7f
L		 3131 {
3132 { "(bad)", { XX } },
3133 { "(bad)", { XX } },
09a2c6cf 3134 { "pblendw", { XM, EXx, Ib } },
42903f7f
L		 3135 { "(bad)", { XX } },
3136 },
3137
1ceb70f8 3138 /* PREFIX_0F3A14 */
42903f7f
L		 3139 {
3140 { "(bad)", { XX } },
3141 { "(bad)", { XX } },
3142 { "pextrb", { Edqb, XM, Ib } },
3143 { "(bad)", { XX } },
3144 },
3145
1ceb70f8 3146 /* PREFIX_0F3A15 */
42903f7f
L		 3147 {
3148 { "(bad)", { XX } },
3149 { "(bad)", { XX } },
3150 { "pextrw", { Edqw, XM, Ib } },
3151 { "(bad)", { XX } },
3152 },
3153
1ceb70f8 3154 /* PREFIX_0F3A16 */
42903f7f
L		 3155 {
3156 { "(bad)", { XX } },
3157 { "(bad)", { XX } },
3158 { "pextrK", { Edq, XM, Ib } },
3159 { "(bad)", { XX } },
3160 },
3161
1ceb70f8 3162 /* PREFIX_0F3A17 */
42903f7f
L		 3163 {
3164 { "(bad)", { XX } },
3165 { "(bad)", { XX } },
3166 { "extractps", { Edqd, XM, Ib } },
3167 { "(bad)", { XX } },
3168 },
3169
1ceb70f8 3170 /* PREFIX_0F3A20 */
42903f7f
L		 3171 {
3172 { "(bad)", { XX } },
3173 { "(bad)", { XX } },
3174 { "pinsrb", { XM, Edqb, Ib } },
3175 { "(bad)", { XX } },
3176 },
3177
1ceb70f8 3178 /* PREFIX_0F3A21 */
42903f7f
L		 3179 {
3180 { "(bad)", { XX } },
3181 { "(bad)", { XX } },
8976381e 3182 { "insertps", { XM, EXd, Ib } },
42903f7f
L		 3183 { "(bad)", { XX } },
3184 },
3185
1ceb70f8 3186 /* PREFIX_0F3A22 */
42903f7f
L		 3187 {
3188 { "(bad)", { XX } },
3189 { "(bad)", { XX } },
3190 { "pinsrK", { XM, Edq, Ib } },
3191 { "(bad)", { XX } },
3192 },
3193
1ceb70f8 3194 /* PREFIX_0F3A40 */
42903f7f
L		 3195 {
3196 { "(bad)", { XX } },
3197 { "(bad)", { XX } },
09a2c6cf 3198 { "dpps", { XM, EXx, Ib } },
42903f7f
L		 3199 { "(bad)", { XX } },
3200 },
3201
1ceb70f8 3202 /* PREFIX_0F3A41 */
42903f7f
L		 3203 {
3204 { "(bad)", { XX } },
3205 { "(bad)", { XX } },
09a2c6cf 3206 { "dppd", { XM, EXx, Ib } },
42903f7f
L		 3207 { "(bad)", { XX } },
3208 },
3209
1ceb70f8 3210 /* PREFIX_0F3A42 */
42903f7f
L		 3211 {
3212 { "(bad)", { XX } },
3213 { "(bad)", { XX } },
09a2c6cf 3214 { "mpsadbw", { XM, EXx, Ib } },
42903f7f
L		 3215 { "(bad)", { XX } },
3216 },
381d071f 3217
c0f3af97
L		 3218 /* PREFIX_0F3A44 */
3219 {
3220 { "(bad)", { XX } },
3221 { "(bad)", { XX } },
3222 { "pclmulqdq", { XM, EXx, PCLMUL } },
3223 { "(bad)", { XX } },
3224 },
3225
1ceb70f8 3226 /* PREFIX_0F3A60 */
381d071f
L		 3227 {
3228 { "(bad)", { XX } },
3229 { "(bad)", { XX } },
4e7d34a6 3230 { "pcmpestrm", { XM, EXx, Ib } },
381d071f
L		 3231 { "(bad)", { XX } },
3232 },
3233
1ceb70f8 3234 /* PREFIX_0F3A61 */
381d071f
L		 3235 {
3236 { "(bad)", { XX } },
3237 { "(bad)", { XX } },
4e7d34a6 3238 { "pcmpestri", { XM, EXx, Ib } },
381d071f 3239 { "(bad)", { XX } },
381d071f
L		 3240 },
3241
1ceb70f8 3242 /* PREFIX_0F3A62 */
381d071f
L		 3243 {
3244 { "(bad)", { XX } },
3245 { "(bad)", { XX } },
4e7d34a6 3246 { "pcmpistrm", { XM, EXx, Ib } },
381d071f 3247 { "(bad)", { XX } },
381d071f
L		 3248 },
3249
1ceb70f8 3250 /* PREFIX_0F3A63 */
381d071f
L		 3251 {
3252 { "(bad)", { XX } },
3253 { "(bad)", { XX } },
4e7d34a6 3254 { "pcmpistri", { XM, EXx, Ib } },
381d071f
L		 3255 { "(bad)", { XX } },
3256 },
09a2c6cf 3257
c0f3af97 3258 /* PREFIX_0F3ADF */
09a2c6cf 3259 {
c0f3af97
L		 3260 { "(bad)", { XX } },
3261 { "(bad)", { XX } },
3262 { "aeskeygenassist", { XM, EXx, Ib } },
3263 { "(bad)", { XX } },
09a2c6cf
L		 3264 },
3265
c0f3af97 3266 /* PREFIX_VEX_10 */
09a2c6cf 3267 {
c0f3af97
L		 3268 { "vmovups", { XM, EXx } },
3269 { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3270 { "vmovupd", { XM, EXx } },
3271 { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
09a2c6cf
L		 3272 },
3273
c0f3af97 3274 /* PREFIX_VEX_11 */
09a2c6cf 3275 {
c0f3af97
L		 3276 { "vmovups", { EXx, XM } },
3277 { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3278 { "vmovupd", { EXx, XM } },
3279 { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
09a2c6cf
L		 3280 },
3281
c0f3af97 3282 /* PREFIX_VEX_12 */
09a2c6cf 3283 {
c0f3af97
L		 3284 { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3285 { "vmovsldup", { XM, EXx } },
3286 { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3287 { "vmovddup", { XM, EXymmq } },
09a2c6cf
L		 3288 },
3289
c0f3af97 3290 /* PREFIX_VEX_16 */
09a2c6cf 3291 {
c0f3af97
L		 3292 { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3293 { "vmovshdup", { XM, EXx } },
3294 { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3295 { "(bad)", { XX } },
5f754f58 3296 },
7c52e0e8 3297
c0f3af97 3298 /* PREFIX_VEX_2A */
5f754f58 3299 {
c0f3af97
L		 3300 { "(bad)", { XX } },
3301 { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3302 { "(bad)", { XX } },
3303 { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
5f754f58 3304 },
7c52e0e8 3305
c0f3af97 3306 /* PREFIX_VEX_2C */
5f754f58 3307 {
c0f3af97
L		 3308 { "(bad)", { XX } },
3309 { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3310 { "(bad)", { XX } },
3311 { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
5f754f58 3312 },
7c52e0e8 3313
c0f3af97 3314 /* PREFIX_VEX_2D */
7c52e0e8 3315 {
c0f3af97
L		 3316 { "(bad)", { XX } },
3317 { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3318 { "(bad)", { XX } },
3319 { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
7c52e0e8
L		 3320 },
3321
c0f3af97 3322 /* PREFIX_VEX_2E */
7c52e0e8 3323 {
c0f3af97
L		 3324 { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3325 { "(bad)", { XX } },
3326 { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3327 { "(bad)", { XX } },
7c52e0e8
L		 3328 },
3329
c0f3af97 3330 /* PREFIX_VEX_2F */
7c52e0e8 3331 {
c0f3af97
L		 3332 { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3333 { "(bad)", { XX } },
3334 { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3335 { "(bad)", { XX } },
7c52e0e8
L		 3336 },
3337
c0f3af97 3338 /* PREFIX_VEX_51 */
7c52e0e8 3339 {
c0f3af97
L		 3340 { "vsqrtps", { XM, EXx } },
3341 { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3342 { "vsqrtpd", { XM, EXx } },
3343 { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
7c52e0e8
L		 3344 },
3345
c0f3af97 3346 /* PREFIX_VEX_52 */
7c52e0e8 3347 {
c0f3af97
L		 3348 { "vrsqrtps", { XM, EXx } },
3349 { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3350 { "(bad)", { XX } },
3351 { "(bad)", { XX } },
7c52e0e8
L		 3352 },
3353
c0f3af97 3354 /* PREFIX_VEX_53 */
7c52e0e8 3355 {
c0f3af97
L		 3356 { "vrcpps", { XM, EXx } },
3357 { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3358 { "(bad)", { XX } },
3359 { "(bad)", { XX } },
7c52e0e8
L		 3360 },
3361
c0f3af97 3362 /* PREFIX_VEX_58 */
7c52e0e8 3363 {
c0f3af97
L		 3364 { "vaddps", { XM, Vex, EXx } },
3365 { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3366 { "vaddpd", { XM, Vex, EXx } },
3367 { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
7c52e0e8
L		 3368 },
3369
c0f3af97 3370 /* PREFIX_VEX_59 */
7c52e0e8 3371 {
c0f3af97
L		 3372 { "vmulps", { XM, Vex, EXx } },
3373 { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3374 { "vmulpd", { XM, Vex, EXx } },
3375 { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
7c52e0e8
L		 3376 },
3377
c0f3af97 3378 /* PREFIX_VEX_5A */
7c52e0e8 3379 {
c0f3af97
L		 3380 { "vcvtps2pd", { XM, EXxmmq } },
3381 { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3382 { "vcvtpd2ps%XY", { XMM, EXx } },
3383 { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
7c52e0e8
L		 3384 },
3385
c0f3af97 3386 /* PREFIX_VEX_5B */
7c52e0e8 3387 {
c0f3af97
L		 3388 { "vcvtdq2ps", { XM, EXx } },
3389 { "vcvttps2dq", { XM, EXx } },
3390 { "vcvtps2dq", { XM, EXx } },
3391 { "(bad)", { XX } },
7c52e0e8
L		 3392 },
3393
c0f3af97 3394 /* PREFIX_VEX_5C */
7c52e0e8 3395 {
c0f3af97
L		 3396 { "vsubps", { XM, Vex, EXx } },
3397 { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3398 { "vsubpd", { XM, Vex, EXx } },
3399 { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
7c52e0e8
L		 3400 },
3401
c0f3af97 3402 /* PREFIX_VEX_5D */
7c52e0e8 3403 {
c0f3af97
L		 3404 { "vminps", { XM, Vex, EXx } },
3405 { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3406 { "vminpd", { XM, Vex, EXx } },
3407 { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
7c52e0e8
L		 3408 },
3409
c0f3af97 3410 /* PREFIX_VEX_5E */
7c52e0e8 3411 {
c0f3af97
L		 3412 { "vdivps", { XM, Vex, EXx } },
3413 { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3414 { "vdivpd", { XM, Vex, EXx } },
3415 { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
7c52e0e8
L		 3416 },
3417
c0f3af97 3418 /* PREFIX_VEX_5F */
7c52e0e8 3419 {
c0f3af97
L		 3420 { "vmaxps", { XM, Vex, EXx } },
3421 { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3422 { "vmaxpd", { XM, Vex, EXx } },
3423 { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
7c52e0e8
L		 3424 },
3425
c0f3af97 3426 /* PREFIX_VEX_60 */
7c52e0e8 3427 {
c0f3af97
L		 3428 { "(bad)", { XX } },
3429 { "(bad)", { XX } },
3430 { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3431 { "(bad)", { XX } },
7c52e0e8
L		 3432 },
3433
c0f3af97 3434 /* PREFIX_VEX_61 */
7c52e0e8 3435 {
c0f3af97
L		 3436 { "(bad)", { XX } },
3437 { "(bad)", { XX } },
3438 { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3439 { "(bad)", { XX } },
7c52e0e8
L		 3440 },
3441
c0f3af97 3442 /* PREFIX_VEX_62 */
7c52e0e8 3443 {
c0f3af97
L		 3444 { "(bad)", { XX } },
3445 { "(bad)", { XX } },
3446 { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3447 { "(bad)", { XX } },
7c52e0e8
L		 3448 },
3449
c0f3af97 3450 /* PREFIX_VEX_63 */
7c52e0e8 3451 {
c0f3af97
L		 3452 { "(bad)", { XX } },
3453 { "(bad)", { XX } },
3454 { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3455 { "(bad)", { XX } },
7c52e0e8
L		 3456 },
3457
c0f3af97 3458 /* PREFIX_VEX_64 */
7c52e0e8 3459 {
c0f3af97
L		 3460 { "(bad)", { XX } },
3461 { "(bad)", { XX } },
3462 { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3463 { "(bad)", { XX } },
7c52e0e8
L		 3464 },
3465
c0f3af97 3466 /* PREFIX_VEX_65 */
7c52e0e8 3467 {
c0f3af97
L		 3468 { "(bad)", { XX } },
3469 { "(bad)", { XX } },
3470 { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3471 { "(bad)", { XX } },
7c52e0e8
L		 3472 },
3473
c0f3af97 3474 /* PREFIX_VEX_66 */
7c52e0e8 3475 {
c0f3af97
L		 3476 { "(bad)", { XX } },
3477 { "(bad)", { XX } },
3478 { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3479 { "(bad)", { XX } },
7c52e0e8 3480 },
6439fc28 3481
c0f3af97 3482 /* PREFIX_VEX_67 */
331d2d0d 3483 {
c0f3af97
L		 3484 { "(bad)", { XX } },
3485 { "(bad)", { XX } },
3486 { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3487 { "(bad)", { XX } },
3488 },
3489
3490 /* PREFIX_VEX_68 */
3491 {
3492 { "(bad)", { XX } },
3493 { "(bad)", { XX } },
3494 { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3495 { "(bad)", { XX } },
3496 },
3497
3498 /* PREFIX_VEX_69 */
3499 {
3500 { "(bad)", { XX } },
3501 { "(bad)", { XX } },
3502 { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3503 { "(bad)", { XX } },
3504 },
3505
3506 /* PREFIX_VEX_6A */
3507 {
3508 { "(bad)", { XX } },
3509 { "(bad)", { XX } },
3510 { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3511 { "(bad)", { XX } },
3512 },
3513
3514 /* PREFIX_VEX_6B */
3515 {
3516 { "(bad)", { XX } },
3517 { "(bad)", { XX } },
3518 { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3519 { "(bad)", { XX } },
3520 },
3521
3522 /* PREFIX_VEX_6C */
3523 {
3524 { "(bad)", { XX } },
3525 { "(bad)", { XX } },
3526 { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3527 { "(bad)", { XX } },
3528 },
3529
3530 /* PREFIX_VEX_6D */
3531 {
3532 { "(bad)", { XX } },
3533 { "(bad)", { XX } },
3534 { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3535 { "(bad)", { XX } },
3536 },
3537
3538 /* PREFIX_VEX_6E */
3539 {
3540 { "(bad)", { XX } },
3541 { "(bad)", { XX } },
3542 { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3543 { "(bad)", { XX } },
3544 },
3545
3546 /* PREFIX_VEX_6F */
3547 {
3548 { "(bad)", { XX } },
3549 { "vmovdqu", { XM, EXx } },
3550 { "vmovdqa", { XM, EXx } },
3551 { "(bad)", { XX } },
3552 },
3553
3554 /* PREFIX_VEX_70 */
3555 {
3556 { "(bad)", { XX } },
3557 { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3558 { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3559 { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3560 },
3561
3562 /* PREFIX_VEX_71_REG_2 */
3563 {
3564 { "(bad)", { XX } },
3565 { "(bad)", { XX } },
3566 { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3567 { "(bad)", { XX } },
3568 },
3569
3570 /* PREFIX_VEX_71_REG_4 */
3571 {
3572 { "(bad)", { XX } },
3573 { "(bad)", { XX } },
3574 { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3575 { "(bad)", { XX } },
3576 },
3577
3578 /* PREFIX_VEX_71_REG_6 */
3579 {
3580 { "(bad)", { XX } },
3581 { "(bad)", { XX } },
3582 { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3583 { "(bad)", { XX } },
3584 },
3585
3586 /* PREFIX_VEX_72_REG_2 */
3587 {
3588 { "(bad)", { XX } },
3589 { "(bad)", { XX } },
3590 { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3591 { "(bad)", { XX } },
3592 },
3593
3594 /* PREFIX_VEX_72_REG_4 */
3595 {
3596 { "(bad)", { XX } },
3597 { "(bad)", { XX } },
3598 { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3599 { "(bad)", { XX } },
3600 },
3601
3602 /* PREFIX_VEX_72_REG_6 */
3603 {
3604 { "(bad)", { XX } },
3605 { "(bad)", { XX } },
3606 { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3607 { "(bad)", { XX } },
3608 },
3609
3610 /* PREFIX_VEX_73_REG_2 */
3611 {
3612 { "(bad)", { XX } },
3613 { "(bad)", { XX } },
3614 { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3615 { "(bad)", { XX } },
3616 },
3617
3618 /* PREFIX_VEX_73_REG_3 */
3619 {
3620 { "(bad)", { XX } },
3621 { "(bad)", { XX } },
3622 { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3623 { "(bad)", { XX } },
3624 },
3625
3626 /* PREFIX_VEX_73_REG_6 */
3627 {
3628 { "(bad)", { XX } },
3629 { "(bad)", { XX } },
3630 { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3631 { "(bad)", { XX } },
3632 },
3633
3634 /* PREFIX_VEX_73_REG_7 */
3635 {
3636 { "(bad)", { XX } },
3637 { "(bad)", { XX } },
3638 { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3639 { "(bad)", { XX } },
3640 },
3641
3642 /* PREFIX_VEX_74 */
3643 {
3644 { "(bad)", { XX } },
3645 { "(bad)", { XX } },
3646 { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3647 { "(bad)", { XX } },
3648 },
3649
3650 /* PREFIX_VEX_75 */
3651 {
3652 { "(bad)", { XX } },
3653 { "(bad)", { XX } },
3654 { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3655 { "(bad)", { XX } },
3656 },
3657
3658 /* PREFIX_VEX_76 */
3659 {
3660 { "(bad)", { XX } },
3661 { "(bad)", { XX } },
3662 { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3663 { "(bad)", { XX } },
3664 },
3665
3666 /* PREFIX_VEX_77 */
3667 {
3668 { "", { VZERO } },
3669 { "(bad)", { XX } },
3670 { "(bad)", { XX } },
3671 { "(bad)", { XX } },
3672 },
3673
3674 /* PREFIX_VEX_7C */
3675 {
3676 { "(bad)", { XX } },
3677 { "(bad)", { XX } },
3678 { "vhaddpd", { XM, Vex, EXx } },
3679 { "vhaddps", { XM, Vex, EXx } },
3680 },
3681
3682 /* PREFIX_VEX_7D */
3683 {
3684 { "(bad)", { XX } },
3685 { "(bad)", { XX } },
3686 { "vhsubpd", { XM, Vex, EXx } },
3687 { "vhsubps", { XM, Vex, EXx } },
3688 },
3689
3690 /* PREFIX_VEX_7E */
3691 {
3692 { "(bad)", { XX } },
3693 { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3694 { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3695 { "(bad)", { XX } },
3696 },
3697
3698 /* PREFIX_VEX_7F */
3699 {
3700 { "(bad)", { XX } },
3701 { "vmovdqu", { EXx, XM } },
3702 { "vmovdqa", { EXx, XM } },
3703 { "(bad)", { XX } },
3704 },
3705
3706 /* PREFIX_VEX_C2 */
3707 {
3708 { "vcmpps", { XM, Vex, EXx, VCMP } },
3709 { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3710 { "vcmppd", { XM, Vex, EXx, VCMP } },
3711 { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3712 },
3713
3714 /* PREFIX_VEX_C4 */
3715 {
3716 { "(bad)", { XX } },
3717 { "(bad)", { XX } },
3718 { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3719 { "(bad)", { XX } },
3720 },
3721
3722 /* PREFIX_VEX_C5 */
3723 {
3724 { "(bad)", { XX } },
3725 { "(bad)", { XX } },
3726 { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3727 { "(bad)", { XX } },
3728 },
3729
3730 /* PREFIX_VEX_D0 */
3731 {
3732 { "(bad)", { XX } },
3733 { "(bad)", { XX } },
3734 { "vaddsubpd", { XM, Vex, EXx } },
3735 { "vaddsubps", { XM, Vex, EXx } },
3736 },
3737
3738 /* PREFIX_VEX_D1 */
3739 {
3740 { "(bad)", { XX } },
3741 { "(bad)", { XX } },
3742 { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3743 { "(bad)", { XX } },
3744 },
3745
3746 /* PREFIX_VEX_D2 */
3747 {
3748 { "(bad)", { XX } },
3749 { "(bad)", { XX } },
3750 { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3751 { "(bad)", { XX } },
3752 },
3753
3754 /* PREFIX_VEX_D3 */
3755 {
3756 { "(bad)", { XX } },
3757 { "(bad)", { XX } },
3758 { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3759 { "(bad)", { XX } },
3760 },
3761
3762 /* PREFIX_VEX_D4 */
3763 {
3764 { "(bad)", { XX } },
3765 { "(bad)", { XX } },
3766 { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
3767 { "(bad)", { XX } },
3768 },
3769
3770 /* PREFIX_VEX_D5 */
3771 {
3772 { "(bad)", { XX } },
3773 { "(bad)", { XX } },
3774 { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
3775 { "(bad)", { XX } },
3776 },
3777
3778 /* PREFIX_VEX_D6 */
3779 {
3780 { "(bad)", { XX } },
3781 { "(bad)", { XX } },
3782 { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
3783 { "(bad)", { XX } },
3784 },
3785
3786 /* PREFIX_VEX_D7 */
3787 {
3788 { "(bad)", { XX } },
3789 { "(bad)", { XX } },
3790 { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
3791 { "(bad)", { XX } },
3792 },
3793
3794 /* PREFIX_VEX_D8 */
3795 {
3796 { "(bad)", { XX } },
3797 { "(bad)", { XX } },
3798 { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
3799 { "(bad)", { XX } },
3800 },
3801
3802 /* PREFIX_VEX_D9 */
3803 {
3804 { "(bad)", { XX } },
3805 { "(bad)", { XX } },
3806 { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
3807 { "(bad)", { XX } },
3808 },
3809
3810 /* PREFIX_VEX_DA */
3811 {
3812 { "(bad)", { XX } },
3813 { "(bad)", { XX } },
3814 { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
3815 { "(bad)", { XX } },
3816 },
3817
3818 /* PREFIX_VEX_DB */
3819 {
3820 { "(bad)", { XX } },
3821 { "(bad)", { XX } },
3822 { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
3823 { "(bad)", { XX } },
3824 },
3825
3826 /* PREFIX_VEX_DC */
3827 {
3828 { "(bad)", { XX } },
3829 { "(bad)", { XX } },
3830 { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
3831 { "(bad)", { XX } },
3832 },
3833
3834 /* PREFIX_VEX_DD */
3835 {
3836 { "(bad)", { XX } },
3837 { "(bad)", { XX } },
3838 { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
3839 { "(bad)", { XX } },
3840 },
3841
3842 /* PREFIX_VEX_DE */
3843 {
3844 { "(bad)", { XX } },
3845 { "(bad)", { XX } },
3846 { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
3847 { "(bad)", { XX } },
3848 },
3849
3850 /* PREFIX_VEX_DF */
3851 {
3852 { "(bad)", { XX } },
3853 { "(bad)", { XX } },
3854 { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
3855 { "(bad)", { XX } },
3856 },
3857
3858 /* PREFIX_VEX_E0 */
3859 {
3860 { "(bad)", { XX } },
3861 { "(bad)", { XX } },
3862 { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
3863 { "(bad)", { XX } },
3864 },
3865
3866 /* PREFIX_VEX_E1 */
3867 {
3868 { "(bad)", { XX } },
3869 { "(bad)", { XX } },
3870 { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
3871 { "(bad)", { XX } },
3872 },
3873
3874 /* PREFIX_VEX_E2 */
3875 {
3876 { "(bad)", { XX } },
3877 { "(bad)", { XX } },
3878 { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
3879 { "(bad)", { XX } },
3880 },
3881
3882 /* PREFIX_VEX_E3 */
3883 {
3884 { "(bad)", { XX } },
3885 { "(bad)", { XX } },
3886 { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
3887 { "(bad)", { XX } },
3888 },
3889
3890 /* PREFIX_VEX_E4 */
3891 {
3892 { "(bad)", { XX } },
3893 { "(bad)", { XX } },
3894 { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
3895 { "(bad)", { XX } },
3896 },
3897
3898 /* PREFIX_VEX_E5 */
3899 {
3900 { "(bad)", { XX } },
3901 { "(bad)", { XX } },
3902 { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
3903 { "(bad)", { XX } },
3904 },
3905
3906 /* PREFIX_VEX_E6 */
3907 {
3908 { "(bad)", { XX } },
3909 { "vcvtdq2pd", { XM, EXxmmq } },
3910 { "vcvttpd2dq%XY", { XMM, EXx } },
3911 { "vcvtpd2dq%XY", { XMM, EXx } },
3912 },
3913
3914 /* PREFIX_VEX_E7 */
3915 {
3916 { "(bad)", { XX } },
3917 { "(bad)", { XX } },
3918 { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
3919 { "(bad)", { XX } },
3920 },
3921
3922 /* PREFIX_VEX_E8 */
3923 {
3924 { "(bad)", { XX } },
3925 { "(bad)", { XX } },
3926 { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
3927 { "(bad)", { XX } },
3928 },
3929
3930 /* PREFIX_VEX_E9 */
3931 {
3932 { "(bad)", { XX } },
3933 { "(bad)", { XX } },
3934 { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
3935 { "(bad)", { XX } },
3936 },
3937
3938 /* PREFIX_VEX_EA */
3939 {
3940 { "(bad)", { XX } },
3941 { "(bad)", { XX } },
3942 { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
3943 { "(bad)", { XX } },
3944 },
3945
3946 /* PREFIX_VEX_EB */
3947 {
3948 { "(bad)", { XX } },
3949 { "(bad)", { XX } },
3950 { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
3951 { "(bad)", { XX } },
3952 },
3953
3954 /* PREFIX_VEX_EC */
3955 {
3956 { "(bad)", { XX } },
3957 { "(bad)", { XX } },
3958 { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
3959 { "(bad)", { XX } },
3960 },
3961
3962 /* PREFIX_VEX_ED */
3963 {
3964 { "(bad)", { XX } },
3965 { "(bad)", { XX } },
3966 { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
3967 { "(bad)", { XX } },
3968 },
3969
3970 /* PREFIX_VEX_EE */
3971 {
3972 { "(bad)", { XX } },
3973 { "(bad)", { XX } },
3974 { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
3975 { "(bad)", { XX } },
3976 },
3977
3978 /* PREFIX_VEX_EF */
3979 {
3980 { "(bad)", { XX } },
3981 { "(bad)", { XX } },
3982 { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
3983 { "(bad)", { XX } },
3984 },
3985
3986 /* PREFIX_VEX_F0 */
3987 {
3988 { "(bad)", { XX } },
3989 { "(bad)", { XX } },
3990 { "(bad)", { XX } },
3991 { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
3992 },
3993
3994 /* PREFIX_VEX_F1 */
3995 {
3996 { "(bad)", { XX } },
3997 { "(bad)", { XX } },
3998 { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
3999 { "(bad)", { XX } },
4000 },
4001
4002 /* PREFIX_VEX_F2 */
4003 {
4004 { "(bad)", { XX } },
4005 { "(bad)", { XX } },
4006 { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4007 { "(bad)", { XX } },
4008 },
4009
4010 /* PREFIX_VEX_F3 */
4011 {
4012 { "(bad)", { XX } },
4013 { "(bad)", { XX } },
4014 { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4015 { "(bad)", { XX } },
4016 },
4017
4018 /* PREFIX_VEX_F4 */
4019 {
4020 { "(bad)", { XX } },
4021 { "(bad)", { XX } },
4022 { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4023 { "(bad)", { XX } },
4024 },
4025
4026 /* PREFIX_VEX_F5 */
4027 {
4028 { "(bad)", { XX } },
4029 { "(bad)", { XX } },
4030 { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4031 { "(bad)", { XX } },
4032 },
4033
4034 /* PREFIX_VEX_F6 */
4035 {
4036 { "(bad)", { XX } },
4037 { "(bad)", { XX } },
4038 { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4039 { "(bad)", { XX } },
4040 },
4041
4042 /* PREFIX_VEX_F7 */
4043 {
4044 { "(bad)", { XX } },
4045 { "(bad)", { XX } },
4046 { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4047 { "(bad)", { XX } },
4048 },
4049
4050 /* PREFIX_VEX_F8 */
4051 {
4052 { "(bad)", { XX } },
4053 { "(bad)", { XX } },
4054 { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4055 { "(bad)", { XX } },
4056 },
4057
4058 /* PREFIX_VEX_F9 */
4059 {
4060 { "(bad)", { XX } },
4061 { "(bad)", { XX } },
4062 { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4063 { "(bad)", { XX } },
4064 },
4065
4066 /* PREFIX_VEX_FA */
4067 {
4068 { "(bad)", { XX } },
4069 { "(bad)", { XX } },
4070 { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4071 { "(bad)", { XX } },
4072 },
4073
4074 /* PREFIX_VEX_FB */
4075 {
4076 { "(bad)", { XX } },
4077 { "(bad)", { XX } },
4078 { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4079 { "(bad)", { XX } },
4080 },
4081
4082 /* PREFIX_VEX_FC */
4083 {
4084 { "(bad)", { XX } },
4085 { "(bad)", { XX } },
4086 { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4087 { "(bad)", { XX } },
4088 },
4089
4090 /* PREFIX_VEX_FD */
4091 {
4092 { "(bad)", { XX } },
4093 { "(bad)", { XX } },
4094 { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4095 { "(bad)", { XX } },
4096 },
4097
4098 /* PREFIX_VEX_FE */
4099 {
4100 { "(bad)", { XX } },
4101 { "(bad)", { XX } },
4102 { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4103 { "(bad)", { XX } },
4104 },
4105
4106 /* PREFIX_VEX_3800 */
4107 {
4108 { "(bad)", { XX } },
4109 { "(bad)", { XX } },
4110 { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4111 { "(bad)", { XX } },
4112 },
4113
4114 /* PREFIX_VEX_3801 */
4115 {
4116 { "(bad)", { XX } },
4117 { "(bad)", { XX } },
4118 { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4119 { "(bad)", { XX } },
4120 },
4121
4122 /* PREFIX_VEX_3802 */
4123 {
4124 { "(bad)", { XX } },
4125 { "(bad)", { XX } },
4126 { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4127 { "(bad)", { XX } },
4128 },
4129
4130 /* PREFIX_VEX_3803 */
4131 {
4132 { "(bad)", { XX } },
4133 { "(bad)", { XX } },
4134 { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4135 { "(bad)", { XX } },
4136 },
4137
4138 /* PREFIX_VEX_3804 */
4139 {
4140 { "(bad)", { XX } },
4141 { "(bad)", { XX } },
4142 { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4143 { "(bad)", { XX } },
4144 },
4145
4146 /* PREFIX_VEX_3805 */
4147 {
4148 { "(bad)", { XX } },
4149 { "(bad)", { XX } },
4150 { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4151 { "(bad)", { XX } },
4152 },
4153
4154 /* PREFIX_VEX_3806 */
4155 {
4156 { "(bad)", { XX } },
4157 { "(bad)", { XX } },
4158 { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4159 { "(bad)", { XX } },
4160 },
4161
4162 /* PREFIX_VEX_3807 */
4163 {
4164 { "(bad)", { XX } },
4165 { "(bad)", { XX } },
4166 { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4167 { "(bad)", { XX } },
4168 },
4169
4170 /* PREFIX_VEX_3808 */
4171 {
4172 { "(bad)", { XX } },
4173 { "(bad)", { XX } },
4174 { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4175 { "(bad)", { XX } },
4176 },
4177
4178 /* PREFIX_VEX_3809 */
4179 {
4180 { "(bad)", { XX } },
4181 { "(bad)", { XX } },
4182 { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4183 { "(bad)", { XX } },
4184 },
4185
4186 /* PREFIX_VEX_380A */
4187 {
4188 { "(bad)", { XX } },
4189 { "(bad)", { XX } },
4190 { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4191 { "(bad)", { XX } },
4192 },
4193
4194 /* PREFIX_VEX_380B */
4195 {
4196 { "(bad)", { XX } },
4197 { "(bad)", { XX } },
4198 { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4199 { "(bad)", { XX } },
4200 },
4201
4202 /* PREFIX_VEX_380C */
4203 {
4204 { "(bad)", { XX } },
4205 { "(bad)", { XX } },
4206 { "vpermilps", { XM, Vex, EXx } },
4207 { "(bad)", { XX } },
4208 },
4209
4210 /* PREFIX_VEX_380D */
4211 {
4212 { "(bad)", { XX } },
4213 { "(bad)", { XX } },
4214 { "vpermilpd", { XM, Vex, EXx } },
4215 { "(bad)", { XX } },
4216 },
4217
4218 /* PREFIX_VEX_380E */
4219 {
4220 { "(bad)", { XX } },
4221 { "(bad)", { XX } },
4222 { "vtestps", { XM, EXx } },
4223 { "(bad)", { XX } },
4224 },
4225
4226 /* PREFIX_VEX_380F */
4227 {
4228 { "(bad)", { XX } },
4229 { "(bad)", { XX } },
4230 { "vtestpd", { XM, EXx } },
4231 { "(bad)", { XX } },
4232 },
4233
4234 /* PREFIX_VEX_3817 */
4235 {
4236 { "(bad)", { XX } },
4237 { "(bad)", { XX } },
4238 { "vptest", { XM, EXx } },
4239 { "(bad)", { XX } },
4240 },
4241
4242 /* PREFIX_VEX_3818 */
4243 {
4244 { "(bad)", { XX } },
4245 { "(bad)", { XX } },
4246 { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4247 { "(bad)", { XX } },
4248 },
4249
4250 /* PREFIX_VEX_3819 */
4251 {
4252 { "(bad)", { XX } },
4253 { "(bad)", { XX } },
4254 { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4255 { "(bad)", { XX } },
4256 },
4257
4258 /* PREFIX_VEX_381A */
4259 {
4260 { "(bad)", { XX } },
4261 { "(bad)", { XX } },
4262 { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4263 { "(bad)", { XX } },
4264 },
4265
4266 /* PREFIX_VEX_381C */
4267 {
4268 { "(bad)", { XX } },
4269 { "(bad)", { XX } },
4270 { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4271 { "(bad)", { XX } },
4272 },
4273
4274 /* PREFIX_VEX_381D */
4275 {
4276 { "(bad)", { XX } },
4277 { "(bad)", { XX } },
4278 { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4279 { "(bad)", { XX } },
4280 },
4281
4282 /* PREFIX_VEX_381E */
4283 {
4284 { "(bad)", { XX } },
4285 { "(bad)", { XX } },
4286 { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4287 { "(bad)", { XX } },
4288 },
4289
4290 /* PREFIX_VEX_3820 */
4291 {
4292 { "(bad)", { XX } },
4293 { "(bad)", { XX } },
4294 { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4295 { "(bad)", { XX } },
4296 },
4297
4298 /* PREFIX_VEX_3821 */
4299 {
4300 { "(bad)", { XX } },
4301 { "(bad)", { XX } },
4302 { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4303 { "(bad)", { XX } },
4304 },
4305
4306 /* PREFIX_VEX_3822 */
4307 {
4308 { "(bad)", { XX } },
4309 { "(bad)", { XX } },
4310 { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4311 { "(bad)", { XX } },
4312 },
4313
4314 /* PREFIX_VEX_3823 */
4315 {
4316 { "(bad)", { XX } },
4317 { "(bad)", { XX } },
4318 { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4319 { "(bad)", { XX } },
4320 },
4321
4322 /* PREFIX_VEX_3824 */
4323 {
4324 { "(bad)", { XX } },
4325 { "(bad)", { XX } },
4326 { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4327 { "(bad)", { XX } },
4328 },
4329
4330 /* PREFIX_VEX_3825 */
4331 {
4332 { "(bad)", { XX } },
4333 { "(bad)", { XX } },
4334 { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4335 { "(bad)", { XX } },
4336 },
4337
4338 /* PREFIX_VEX_3828 */
4339 {
4340 { "(bad)", { XX } },
4341 { "(bad)", { XX } },
4342 { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4343 { "(bad)", { XX } },
4344 },
4345
4346 /* PREFIX_VEX_3829 */
4347 {
4348 { "(bad)", { XX } },
4349 { "(bad)", { XX } },
4350 { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4351 { "(bad)", { XX } },
4352 },
4353
4354 /* PREFIX_VEX_382A */
4355 {
4356 { "(bad)", { XX } },
4357 { "(bad)", { XX } },
4358 { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4359 { "(bad)", { XX } },
4360 },
4361
4362 /* PREFIX_VEX_382B */
4363 {
4364 { "(bad)", { XX } },
4365 { "(bad)", { XX } },
4366 { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4367 { "(bad)", { XX } },
4368 },
4369
4370 /* PREFIX_VEX_382C */
4371 {
4372 { "(bad)", { XX } },
4373 { "(bad)", { XX } },
4374 { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4375 { "(bad)", { XX } },
4376 },
4377
4378 /* PREFIX_VEX_382D */
4379 {
4380 { "(bad)", { XX } },
4381 { "(bad)", { XX } },
4382 { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4383 { "(bad)", { XX } },
4384 },
4385
4386 /* PREFIX_VEX_382E */
4387 {
4388 { "(bad)", { XX } },
4389 { "(bad)", { XX } },
4390 { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4391 { "(bad)", { XX } },
4392 },
4393
4394 /* PREFIX_VEX_382F */
4395 {
4396 { "(bad)", { XX } },
4397 { "(bad)", { XX } },
4398 { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4399 { "(bad)", { XX } },
4400 },
4401
4402 /* PREFIX_VEX_3830 */
4403 {
4404 { "(bad)", { XX } },
4405 { "(bad)", { XX } },
4406 { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4407 { "(bad)", { XX } },
4408 },
4409
4410 /* PREFIX_VEX_3831 */
4411 {
4412 { "(bad)", { XX } },
4413 { "(bad)", { XX } },
4414 { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4415 { "(bad)", { XX } },
4416 },
4417
4418 /* PREFIX_VEX_3832 */
4419 {
4420 { "(bad)", { XX } },
4421 { "(bad)", { XX } },
4422 { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4423 { "(bad)", { XX } },
4424 },
4425
4426 /* PREFIX_VEX_3833 */
4427 {
4428 { "(bad)", { XX } },
4429 { "(bad)", { XX } },
4430 { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4431 { "(bad)", { XX } },
4432 },
4433
4434 /* PREFIX_VEX_3834 */
4435 {
4436 { "(bad)", { XX } },
4437 { "(bad)", { XX } },
4438 { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4439 { "(bad)", { XX } },
4440 },
4441
4442 /* PREFIX_VEX_3835 */
4443 {
4444 { "(bad)", { XX } },
4445 { "(bad)", { XX } },
4446 { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4447 { "(bad)", { XX } },
4448 },
4449
4450 /* PREFIX_VEX_3837 */
4451 {
4452 { "(bad)", { XX } },
4453 { "(bad)", { XX } },
4454 { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4455 { "(bad)", { XX } },
4456 },
4457
4458 /* PREFIX_VEX_3838 */
4459 {
4460 { "(bad)", { XX } },
4461 { "(bad)", { XX } },
4462 { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4463 { "(bad)", { XX } },
4464 },
4465
4466 /* PREFIX_VEX_3839 */
4467 {
4468 { "(bad)", { XX } },
4469 { "(bad)", { XX } },
4470 { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4471 { "(bad)", { XX } },
4472 },
4473
4474 /* PREFIX_VEX_383A */
4475 {
4476 { "(bad)", { XX } },
4477 { "(bad)", { XX } },
4478 { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4479 { "(bad)", { XX } },
4480 },
4481
4482 /* PREFIX_VEX_383B */
4483 {
4484 { "(bad)", { XX } },
4485 { "(bad)", { XX } },
4486 { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4487 { "(bad)", { XX } },
4488 },
4489
4490 /* PREFIX_VEX_383C */
4491 {
4492 { "(bad)", { XX } },
4493 { "(bad)", { XX } },
4494 { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4495 { "(bad)", { XX } },
4496 },
4497
4498 /* PREFIX_VEX_383D */
4499 {
4500 { "(bad)", { XX } },
4501 { "(bad)", { XX } },
4502 { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4503 { "(bad)", { XX } },
4504 },
4505
4506 /* PREFIX_VEX_383E */
4507 {
4508 { "(bad)", { XX } },
4509 { "(bad)", { XX } },
4510 { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4511 { "(bad)", { XX } },
4512 },
4513
4514 /* PREFIX_VEX_383F */
4515 {
4516 { "(bad)", { XX } },
4517 { "(bad)", { XX } },
4518 { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4519 { "(bad)", { XX } },
4520 },
4521
4522 /* PREFIX_VEX_3840 */
4523 {
4524 { "(bad)", { XX } },
4525 { "(bad)", { XX } },
4526 { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4527 { "(bad)", { XX } },
4528 },
4529
4530 /* PREFIX_VEX_3841 */
4531 {
4532 { "(bad)", { XX } },
4533 { "(bad)", { XX } },
4534 { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4535 { "(bad)", { XX } },
4536 },
4537
4538 /* PREFIX_VEX_3A04 */
4539 {
4540 { "(bad)", { XX } },
4541 { "(bad)", { XX } },
4542 { "vpermilps", { XM, EXx, Ib } },
4543 { "(bad)", { XX } },
4544 },
4545
4546 /* PREFIX_VEX_3A05 */
4547 {
4548 { "(bad)", { XX } },
4549 { "(bad)", { XX } },
4550 { "vpermilpd", { XM, EXx, Ib } },
4551 { "(bad)", { XX } },
4552 },
4553
4554 /* PREFIX_VEX_3A06 */
4555 {
4556 { "(bad)", { XX } },
4557 { "(bad)", { XX } },
4558 { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4559 { "(bad)", { XX } },
4560 },
4561
4562 /* PREFIX_VEX_3A08 */
4563 {
4564 { "(bad)", { XX } },
4565 { "(bad)", { XX } },
4566 { "vroundps", { XM, EXx, Ib } },
4567 { "(bad)", { XX } },
4568 },
4569
4570 /* PREFIX_VEX_3A09 */
4571 {
4572 { "(bad)", { XX } },
4573 { "(bad)", { XX } },
4574 { "vroundpd", { XM, EXx, Ib } },
4575 { "(bad)", { XX } },
4576 },
4577
4578 /* PREFIX_VEX_3A0A */
4579 {
4580 { "(bad)", { XX } },
4581 { "(bad)", { XX } },
4582 { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4583 { "(bad)", { XX } },
4584 },
4585
4586 /* PREFIX_VEX_3A0B */
4587 {
4588 { "(bad)", { XX } },
4589 { "(bad)", { XX } },
4590 { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4591 { "(bad)", { XX } },
4592 },
4593
4594 /* PREFIX_VEX_3A0C */
4595 {
4596 { "(bad)", { XX } },
4597 { "(bad)", { XX } },
4598 { "vblendps", { XM, Vex, EXx, Ib } },
4599 { "(bad)", { XX } },
4600 },
4601
4602 /* PREFIX_VEX_3A0D */
4603 {
4604 { "(bad)", { XX } },
4605 { "(bad)", { XX } },
4606 { "vblendpd", { XM, Vex, EXx, Ib } },
4607 { "(bad)", { XX } },
4608 },
4609
4610 /* PREFIX_VEX_3A0E */
4611 {
4612 { "(bad)", { XX } },
4613 { "(bad)", { XX } },
4614 { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4615 { "(bad)", { XX } },
4616 },
4617
4618 /* PREFIX_VEX_3A0F */
4619 {
4620 { "(bad)", { XX } },
4621 { "(bad)", { XX } },
4622 { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
4623 { "(bad)", { XX } },
4624 },
4625
4626 /* PREFIX_VEX_3A14 */
4627 {
4628 { "(bad)", { XX } },
4629 { "(bad)", { XX } },
4630 { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
4631 { "(bad)", { XX } },
4632 },
4633
4634 /* PREFIX_VEX_3A15 */
4635 {
4636 { "(bad)", { XX } },
4637 { "(bad)", { XX } },
4638 { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
4639 { "(bad)", { XX } },
4640 },
4641
4642 /* PREFIX_VEX_3A16 */
4643 {
4644 { "(bad)", { XX } },
4645 { "(bad)", { XX } },
4646 { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
4647 { "(bad)", { XX } },
4648 },
4649
4650 /* PREFIX_VEX_3A17 */
4651 {
4652 { "(bad)", { XX } },
4653 { "(bad)", { XX } },
4654 { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
4655 { "(bad)", { XX } },
4656 },
4657
4658 /* PREFIX_VEX_3A18 */
4659 {
4660 { "(bad)", { XX } },
4661 { "(bad)", { XX } },
4662 { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
4663 { "(bad)", { XX } },
4664 },
4665
4666 /* PREFIX_VEX_3A19 */
4667 {
4668 { "(bad)", { XX } },
4669 { "(bad)", { XX } },
4670 { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
4671 { "(bad)", { XX } },
4672 },
4673
4674 /* PREFIX_VEX_3A20 */
4675 {
4676 { "(bad)", { XX } },
4677 { "(bad)", { XX } },
4678 { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
4679 { "(bad)", { XX } },
4680 },
4681
4682 /* PREFIX_VEX_3A21 */
4683 {
4684 { "(bad)", { XX } },
4685 { "(bad)", { XX } },
4686 { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
4687 { "(bad)", { XX } },
4688 },
4689
4690 /* PREFIX_VEX_3A22 */
4691 {
4692 { "(bad)", { XX } },
4693 { "(bad)", { XX } },
4694 { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
4695 { "(bad)", { XX } },
4696 },
4697
4698 /* PREFIX_VEX_3A40 */
4699 {
4700 { "(bad)", { XX } },
4701 { "(bad)", { XX } },
4702 { "vdpps", { XM, Vex, EXx, Ib } },
4703 { "(bad)", { XX } },
4704 },
4705
4706 /* PREFIX_VEX_3A41 */
4707 {
4708 { "(bad)", { XX } },
4709 { "(bad)", { XX } },
4710 { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
4711 { "(bad)", { XX } },
4712 },
4713
4714 /* PREFIX_VEX_3A42 */
4715 {
4716 { "(bad)", { XX } },
4717 { "(bad)", { XX } },
4718 { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
4719 { "(bad)", { XX } },
4720 },
4721
4722 /* PREFIX_VEX_3A48 */
4723 {
4724 { "(bad)", { XX } },
4725 { "(bad)", { XX } },
dae39acc 4726 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, VPERMIL2 } },
c0f3af97
L		 4727 { "(bad)", { XX } },
4728 },
4729
4730 /* PREFIX_VEX_3A49 */
4731 {
4732 { "(bad)", { XX } },
4733 { "(bad)", { XX } },
dae39acc 4734 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, VPERMIL2 } },
c0f3af97
L		 4735 { "(bad)", { XX } },
4736 },
4737
4738 /* PREFIX_VEX_3A4A */
4739 {
4740 { "(bad)", { XX } },
4741 { "(bad)", { XX } },
4742 { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
4743 { "(bad)", { XX } },
4744 },
4745
4746 /* PREFIX_VEX_3A4B */
4747 {
4748 { "(bad)", { XX } },
4749 { "(bad)", { XX } },
4750 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
4751 { "(bad)", { XX } },
4752 },
4753
4754 /* PREFIX_VEX_3A4C */
4755 {
4756 { "(bad)", { XX } },
4757 { "(bad)", { XX } },
4758 { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
4759 { "(bad)", { XX } },
4760 },
4761
4762 /* PREFIX_VEX_3A5C */
4763 {
4764 { "(bad)", { XX } },
4765 { "(bad)", { XX } },
dae39acc 4766 { "vfmaddsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
c0f3af97
L		 4767 { "(bad)", { XX } },
4768 },
4769
4770 /* PREFIX_VEX_3A5D */
4771 {
4772 { "(bad)", { XX } },
4773 { "(bad)", { XX } },
dae39acc 4774 { "vfmaddsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
c0f3af97
L		 4775 { "(bad)", { XX } },
4776 },
4777
4778 /* PREFIX_VEX_3A5E */
4779 {
4780 { "(bad)", { XX } },
4781 { "(bad)", { XX } },
dae39acc 4782 { "vfmsubaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
c0f3af97
L		 4783 { "(bad)", { XX } },
4784 },
4785
4786 /* PREFIX_VEX_3A5F */
4787 {
4788 { "(bad)", { XX } },
4789 { "(bad)", { XX } },
dae39acc 4790 { "vfmsubaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
c0f3af97
L		 4791 { "(bad)", { XX } },
4792 },
4793
4794 /* PREFIX_VEX_3A60 */
4795 {
4796 { "(bad)", { XX } },
4797 { "(bad)", { XX } },
4798 { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
4799 { "(bad)", { XX } },
4800 },
4801
4802 /* PREFIX_VEX_3A61 */
4803 {
4804 { "(bad)", { XX } },
4805 { "(bad)", { XX } },
4806 { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
4807 { "(bad)", { XX } },
4808 },
4809
4810 /* PREFIX_VEX_3A62 */
4811 {
4812 { "(bad)", { XX } },
4813 { "(bad)", { XX } },
4814 { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
4815 { "(bad)", { XX } },
4816 },
4817
4818 /* PREFIX_VEX_3A63 */
4819 {
4820 { "(bad)", { XX } },
4821 { "(bad)", { XX } },
4822 { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
4823 { "(bad)", { XX } },
4824 },
4825
4826 /* PREFIX_VEX_3A68 */
4827 {
4828 { "(bad)", { XX } },
4829 { "(bad)", { XX } },
dae39acc 4830 { "vfmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
c0f3af97
L		 4831 { "(bad)", { XX } },
4832 },
4833
4834 /* PREFIX_VEX_3A69 */
4835 {
4836 { "(bad)", { XX } },
4837 { "(bad)", { XX } },
dae39acc 4838 { "vfmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
c0f3af97
L		 4839 { "(bad)", { XX } },
4840 },
4841
4842 /* PREFIX_VEX_3A6A */
4843 {
4844 { "(bad)", { XX } },
4845 { "(bad)", { XX } },
4846 { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
4847 { "(bad)", { XX } },
4848 },
4849
4850 /* PREFIX_VEX_3A6B */
4851 {
4852 { "(bad)", { XX } },
4853 { "(bad)", { XX } },
4854 { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
4855 { "(bad)", { XX } },
4856 },
4857
4858 /* PREFIX_VEX_3A6C */
4859 {
4860 { "(bad)", { XX } },
4861 { "(bad)", { XX } },
dae39acc 4862 { "vfmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
c0f3af97
L		 4863 { "(bad)", { XX } },
4864 },
4865
4866 /* PREFIX_VEX_3A6D */
4867 {
4868 { "(bad)", { XX } },
4869 { "(bad)", { XX } },
dae39acc 4870 { "vfmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
c0f3af97
L		 4871 { "(bad)", { XX } },
4872 },
4873
4874 /* PREFIX_VEX_3A6E */
4875 {
4876 { "(bad)", { XX } },
4877 { "(bad)", { XX } },
4878 { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
4879 { "(bad)", { XX } },
4880 },
4881
4882 /* PREFIX_VEX_3A6F */
4883 {
4884 { "(bad)", { XX } },
4885 { "(bad)", { XX } },
4886 { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
4887 { "(bad)", { XX } },
4888 },
4889
4890 /* PREFIX_VEX_3A78 */
4891 {
4892 { "(bad)", { XX } },
4893 { "(bad)", { XX } },
dae39acc 4894 { "vfnmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
c0f3af97
L		 4895 { "(bad)", { XX } },
4896 },
4897
4898 /* PREFIX_VEX_3A79 */
4899 {
4900 { "(bad)", { XX } },
4901 { "(bad)", { XX } },
dae39acc 4902 { "vfnmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
c0f3af97
L		 4903 { "(bad)", { XX } },
4904 },
4905
4906 /* PREFIX_VEX_3A7A */
4907 {
4908 { "(bad)", { XX } },
4909 { "(bad)", { XX } },
4910 { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
4911 { "(bad)", { XX } },
4912 },
4913
4914 /* PREFIX_VEX_3A7B */
4915 {
4916 { "(bad)", { XX } },
4917 { "(bad)", { XX } },
4918 { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
4919 { "(bad)", { XX } },
4920 },
4921
4922 /* PREFIX_VEX_3A7C */
4923 {
4924 { "(bad)", { XX } },
4925 { "(bad)", { XX } },
dae39acc 4926 { "vfnmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
c0f3af97
L		 4927 { "(bad)", { XX } },
4928 },
4929
4930 /* PREFIX_VEX_3A7D */
4931 {
4932 { "(bad)", { XX } },
4933 { "(bad)", { XX } },
dae39acc 4934 { "vfnmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
c0f3af97
L		 4935 { "(bad)", { XX } },
4936 },
4937
4938 /* PREFIX_VEX_3A7E */
4939 {
4940 { "(bad)", { XX } },
4941 { "(bad)", { XX } },
4942 { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
4943 { "(bad)", { XX } },
4944 },
4945
4946 /* PREFIX_VEX_3A7F */
4947 {
4948 { "(bad)", { XX } },
4949 { "(bad)", { XX } },
4950 { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
4951 { "(bad)", { XX } },
4952 },
4953};
4954
4955static const struct dis386 x86_64_table[][2] = {
4956 /* X86_64_06 */
4957 {
4958 { "push{T|}", { es } },
4959 { "(bad)", { XX } },
4960 },
4961
4962 /* X86_64_07 */
4963 {
4964 { "pop{T|}", { es } },
4965 { "(bad)", { XX } },
4966 },
4967
4968 /* X86_64_0D */
4969 {
4970 { "push{T|}", { cs } },
4971 { "(bad)", { XX } },
4972 },
4973
4974 /* X86_64_16 */
4975 {
4976 { "push{T|}", { ss } },
4977 { "(bad)", { XX } },
4978 },
4979
4980 /* X86_64_17 */
4981 {
4982 { "pop{T|}", { ss } },
4983 { "(bad)", { XX } },
4984 },
4985
4986 /* X86_64_1E */
4987 {
4988 { "push{T|}", { ds } },
4989 { "(bad)", { XX } },
4990 },
4991
4992 /* X86_64_1F */
4993 {
4994 { "pop{T|}", { ds } },
4995 { "(bad)", { XX } },
4996 },
4997
4998 /* X86_64_27 */
4999 {
5000 { "daa", { XX } },
5001 { "(bad)", { XX } },
5002 },
5003
5004 /* X86_64_2F */
5005 {
5006 { "das", { XX } },
5007 { "(bad)", { XX } },
5008 },
5009
5010 /* X86_64_37 */
5011 {
5012 { "aaa", { XX } },
5013 { "(bad)", { XX } },
5014 },
5015
5016 /* X86_64_3F */
5017 {
5018 { "aas", { XX } },
5019 { "(bad)", { XX } },
5020 },
5021
5022 /* X86_64_60 */
5023 {
5024 { "pusha{P|}", { XX } },
5025 { "(bad)", { XX } },
5026 },
5027
5028 /* X86_64_61 */
5029 {
5030 { "popa{P|}", { XX } },
5031 { "(bad)", { XX } },
5032 },
5033
5034 /* X86_64_62 */
5035 {
5036 { MOD_TABLE (MOD_62_32BIT) },
5037 { "(bad)", { XX } },
5038 },
5039
5040 /* X86_64_63 */
5041 {
5042 { "arpl", { Ew, Gw } },
5043 { "movs{lq|xd}", { Gv, Ed } },
5044 },
5045
5046 /* X86_64_6D */
5047 {
5048 { "ins{R|}", { Yzr, indirDX } },
5049 { "ins{G|}", { Yzr, indirDX } },
5050 },
5051
5052 /* X86_64_6F */
5053 {
5054 { "outs{R|}", { indirDXr, Xz } },
5055 { "outs{G|}", { indirDXr, Xz } },
5056 },
5057
5058 /* X86_64_9A */
5059 {
5060 { "Jcall{T|}", { Ap } },
5061 { "(bad)", { XX } },
5062 },
5063
5064 /* X86_64_C4 */
5065 {
5066 { MOD_TABLE (MOD_C4_32BIT) },
5067 { VEX_C4_TABLE (VEX_0F) },
5068 },
5069
5070 /* X86_64_C5 */
5071 {
5072 { MOD_TABLE (MOD_C5_32BIT) },
5073 { VEX_C5_TABLE (VEX_0F) },
5074 },
5075
5076 /* X86_64_CE */
5077 {
5078 { "into", { XX } },
5079 { "(bad)", { XX } },
5080 },
5081
5082 /* X86_64_D4 */
5083 {
5084 { "aam", { sIb } },
5085 { "(bad)", { XX } },
5086 },
5087
5088 /* X86_64_D5 */
5089 {
5090 { "aad", { sIb } },
5091 { "(bad)", { XX } },
5092 },
5093
5094 /* X86_64_EA */
5095 {
5096 { "Jjmp{T|}", { Ap } },
5097 { "(bad)", { XX } },
5098 },
5099
5100 /* X86_64_0F01_REG_0 */
5101 {
5102 { "sgdt{Q|IQ}", { M } },
5103 { "sgdt", { M } },
5104 },
5105
5106 /* X86_64_0F01_REG_1 */
5107 {
5108 { "sidt{Q|IQ}", { M } },
5109 { "sidt", { M } },
5110 },
5111
5112 /* X86_64_0F01_REG_2 */
5113 {
5114 { "lgdt{Q|Q}", { M } },
5115 { "lgdt", { M } },
5116 },
5117
5118 /* X86_64_0F01_REG_3 */
5119 {
5120 { "lidt{Q|Q}", { M } },
5121 { "lidt", { M } },
5122 },
5123};
5124
5125static const struct dis386 three_byte_table[][256] = {
5126 /* THREE_BYTE_0F24 */
5127 {
5128 /* 00 */
5129 { "fmaddps", { { OP_DREX4, q_mode } } },
5130 { "fmaddpd", { { OP_DREX4, q_mode } } },
5131 { "fmaddss", { { OP_DREX4, w_mode } } },
5132 { "fmaddsd", { { OP_DREX4, d_mode } } },
5133 { "fmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
5134 { "fmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
5135 { "fmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
5136 { "fmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
5137 /* 08 */
5138 { "fmsubps", { { OP_DREX4, q_mode } } },
5139 { "fmsubpd", { { OP_DREX4, q_mode } } },
5140 { "fmsubss", { { OP_DREX4, w_mode } } },
5141 { "fmsubsd", { { OP_DREX4, d_mode } } },
5142 { "fmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
5143 { "fmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
5144 { "fmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
5145 { "fmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
5146 /* 10 */
5147 { "fnmaddps", { { OP_DREX4, q_mode } } },
5148 { "fnmaddpd", { { OP_DREX4, q_mode } } },
5149 { "fnmaddss", { { OP_DREX4, w_mode } } },
5150 { "fnmaddsd", { { OP_DREX4, d_mode } } },
5151 { "fnmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
5152 { "fnmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
5153 { "fnmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
5154 { "fnmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
5155 /* 18 */
5156 { "fnmsubps", { { OP_DREX4, q_mode } } },
5157 { "fnmsubpd", { { OP_DREX4, q_mode } } },
5158 { "fnmsubss", { { OP_DREX4, w_mode } } },
5159 { "fnmsubsd", { { OP_DREX4, d_mode } } },
5160 { "fnmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
5161 { "fnmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
5162 { "fnmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
5163 { "fnmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
5164 /* 20 */
5165 { "permps", { { OP_DREX4, q_mode } } },
5166 { "permpd", { { OP_DREX4, q_mode } } },
5167 { "pcmov", { { OP_DREX4, q_mode } } },
5168 { "pperm", { { OP_DREX4, q_mode } } },
5169 { "permps", { { OP_DREX4, DREX_OC1 + q_mode } } },
5170 { "permpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
5171 { "pcmov", { { OP_DREX4, DREX_OC1 + w_mode } } },
5172 { "pperm", { { OP_DREX4, DREX_OC1 + d_mode } } },
5173 /* 28 */
5174 { "(bad)", { XX } },
5175 { "(bad)", { XX } },
5176 { "(bad)", { XX } },
5177 { "(bad)", { XX } },
5178 { "(bad)", { XX } },
5179 { "(bad)", { XX } },
5180 { "(bad)", { XX } },
5181 { "(bad)", { XX } },
5182 /* 30 */
5183 { "(bad)", { XX } },
5184 { "(bad)", { XX } },
5185 { "(bad)", { XX } },
5186 { "(bad)", { XX } },
5187 { "(bad)", { XX } },
5188 { "(bad)", { XX } },
5189 { "(bad)", { XX } },
5190 { "(bad)", { XX } },
5191 /* 38 */
5192 { "(bad)", { XX } },
5193 { "(bad)", { XX } },
5194 { "(bad)", { XX } },
5195 { "(bad)", { XX } },
5196 { "(bad)", { XX } },
5197 { "(bad)", { XX } },
5198 { "(bad)", { XX } },
5199 { "(bad)", { XX } },
5200 /* 40 */
5201 { "protb", { { OP_DREX3, q_mode } } },
5202 { "protw", { { OP_DREX3, q_mode } } },
5203 { "protd", { { OP_DREX3, q_mode } } },
5204 { "protq", { { OP_DREX3, q_mode } } },
5205 { "pshlb", { { OP_DREX3, q_mode } } },
5206 { "pshlw", { { OP_DREX3, q_mode } } },
5207 { "pshld", { { OP_DREX3, q_mode } } },
5208 { "pshlq", { { OP_DREX3, q_mode } } },
5209 /* 48 */
5210 { "pshab", { { OP_DREX3, q_mode } } },
5211 { "pshaw", { { OP_DREX3, q_mode } } },
5212 { "pshad", { { OP_DREX3, q_mode } } },
5213 { "pshaq", { { OP_DREX3, q_mode } } },
5214 { "(bad)", { XX } },
5215 { "(bad)", { XX } },
5216 { "(bad)", { XX } },
5217 { "(bad)", { XX } },
5218 /* 50 */
5219 { "(bad)", { XX } },
5220 { "(bad)", { XX } },
5221 { "(bad)", { XX } },
5222 { "(bad)", { XX } },
5223 { "(bad)", { XX } },
5224 { "(bad)", { XX } },
5225 { "(bad)", { XX } },
5226 { "(bad)", { XX } },
5227 /* 58 */
5228 { "(bad)", { XX } },
5229 { "(bad)", { XX } },
5230 { "(bad)", { XX } },
5231 { "(bad)", { XX } },
5232 { "(bad)", { XX } },
5233 { "(bad)", { XX } },
5234 { "(bad)", { XX } },
5235 { "(bad)", { XX } },
5236 /* 60 */
5237 { "(bad)", { XX } },
5238 { "(bad)", { XX } },
5239 { "(bad)", { XX } },
5240 { "(bad)", { XX } },
5241 { "(bad)", { XX } },
5242 { "(bad)", { XX } },
5243 { "(bad)", { XX } },
5244 { "(bad)", { XX } },
5245 /* 68 */
5246 { "(bad)", { XX } },
5247 { "(bad)", { XX } },
5248 { "(bad)", { XX } },
5249 { "(bad)", { XX } },
5250 { "(bad)", { XX } },
5251 { "(bad)", { XX } },
5252 { "(bad)", { XX } },
5253 { "(bad)", { XX } },
5254 /* 70 */
5255 { "(bad)", { XX } },
5256 { "(bad)", { XX } },
5257 { "(bad)", { XX } },
5258 { "(bad)", { XX } },
5259 { "(bad)", { XX } },
5260 { "(bad)", { XX } },
5261 { "(bad)", { XX } },
5262 { "(bad)", { XX } },
5263 /* 78 */
5264 { "(bad)", { XX } },
5265 { "(bad)", { XX } },
5266 { "(bad)", { XX } },
5267 { "(bad)", { XX } },
5268 { "(bad)", { XX } },
5269 { "(bad)", { XX } },
5270 { "(bad)", { XX } },
5271 { "(bad)", { XX } },
5272 /* 80 */
5273 { "(bad)", { XX } },
5274 { "(bad)", { XX } },
5275 { "(bad)", { XX } },
5276 { "(bad)", { XX } },
5277 { "(bad)", { XX } },
5278 { "pmacssww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5279 { "pmacsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5280 { "pmacssdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5281 /* 88 */
5282 { "(bad)", { XX } },
5283 { "(bad)", { XX } },
5284 { "(bad)", { XX } },
5285 { "(bad)", { XX } },
5286 { "(bad)", { XX } },
5287 { "(bad)", { XX } },
5288 { "pmacssdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5289 { "pmacssdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5290 /* 90 */
5291 { "(bad)", { XX } },
5292 { "(bad)", { XX } },
5293 { "(bad)", { XX } },
5294 { "(bad)", { XX } },
5295 { "(bad)", { XX } },
5296 { "pmacsww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5297 { "pmacswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5298 { "pmacsdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5299 /* 98 */
5300 { "(bad)", { XX } },
5301 { "(bad)", { XX } },
5302 { "(bad)", { XX } },
5303 { "(bad)", { XX } },
5304 { "(bad)", { XX } },
5305 { "(bad)", { XX } },
5306 { "pmacsdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5307 { "pmacsdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5308 /* a0 */
5309 { "(bad)", { XX } },
5310 { "(bad)", { XX } },
5311 { "(bad)", { XX } },
5312 { "(bad)", { XX } },
5313 { "(bad)", { XX } },
5314 { "(bad)", { XX } },
5315 { "pmadcsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5316 { "(bad)", { XX } },
5317 /* a8 */
5318 { "(bad)", { XX } },
5319 { "(bad)", { XX } },
5320 { "(bad)", { XX } },
5321 { "(bad)", { XX } },
5322 { "(bad)", { XX } },
5323 { "(bad)", { XX } },
5324 { "(bad)", { XX } },
5325 { "(bad)", { XX } },
5326 /* b0 */
5327 { "(bad)", { XX } },
5328 { "(bad)", { XX } },
5329 { "(bad)", { XX } },
5330 { "(bad)", { XX } },
5331 { "(bad)", { XX } },
5332 { "(bad)", { XX } },
5333 { "pmadcswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5334 { "(bad)", { XX } },
5335 /* b8 */
5336 { "(bad)", { XX } },
5337 { "(bad)", { XX } },
5338 { "(bad)", { XX } },
5339 { "(bad)", { XX } },
5340 { "(bad)", { XX } },
5341 { "(bad)", { XX } },
5342 { "(bad)", { XX } },
5343 { "(bad)", { XX } },
5344 /* c0 */
5345 { "(bad)", { XX } },
5346 { "(bad)", { XX } },
5347 { "(bad)", { XX } },
5348 { "(bad)", { XX } },
5349 { "(bad)", { XX } },
5350 { "(bad)", { XX } },
5351 { "(bad)", { XX } },
5352 { "(bad)", { XX } },
5353 /* c8 */
5354 { "(bad)", { XX } },
5355 { "(bad)", { XX } },
5356 { "(bad)", { XX } },
5357 { "(bad)", { XX } },
5358 { "(bad)", { XX } },
5359 { "(bad)", { XX } },
5360 { "(bad)", { XX } },
5361 { "(bad)", { XX } },
5362 /* d0 */
5363 { "(bad)", { XX } },
5364 { "(bad)", { XX } },
5365 { "(bad)", { XX } },
5366 { "(bad)", { XX } },
5367 { "(bad)", { XX } },
5368 { "(bad)", { XX } },
5369 { "(bad)", { XX } },
5370 { "(bad)", { XX } },
5371 /* d8 */
5372 { "(bad)", { XX } },
5373 { "(bad)", { XX } },
5374 { "(bad)", { XX } },
5375 { "(bad)", { XX } },
5376 { "(bad)", { XX } },
5377 { "(bad)", { XX } },
5378 { "(bad)", { XX } },
5379 { "(bad)", { XX } },
5380 /* e0 */
5381 { "(bad)", { XX } },
5382 { "(bad)", { XX } },
5383 { "(bad)", { XX } },
5384 { "(bad)", { XX } },
5385 { "(bad)", { XX } },
5386 { "(bad)", { XX } },
5387 { "(bad)", { XX } },
5388 { "(bad)", { XX } },
5389 /* e8 */
5390 { "(bad)", { XX } },
5391 { "(bad)", { XX } },
5392 { "(bad)", { XX } },
5393 { "(bad)", { XX } },
5394 { "(bad)", { XX } },
5395 { "(bad)", { XX } },
5396 { "(bad)", { XX } },
5397 { "(bad)", { XX } },
5398 /* f0 */
5399 { "(bad)", { XX } },
5400 { "(bad)", { XX } },
5401 { "(bad)", { XX } },
5402 { "(bad)", { XX } },
5403 { "(bad)", { XX } },
5404 { "(bad)", { XX } },
5405 { "(bad)", { XX } },
5406 { "(bad)", { XX } },
5407 /* f8 */
5408 { "(bad)", { XX } },
5409 { "(bad)", { XX } },
5410 { "(bad)", { XX } },
5411 { "(bad)", { XX } },
5412 { "(bad)", { XX } },
5413 { "(bad)", { XX } },
5414 { "(bad)", { XX } },
5415 { "(bad)", { XX } },
5416 },
5417 /* THREE_BYTE_0F25 */
5418 {
5419 /* 00 */
5420 { "(bad)", { XX } },
5421 { "(bad)", { XX } },
5422 { "(bad)", { XX } },
5423 { "(bad)", { XX } },
5424 { "(bad)", { XX } },
5425 { "(bad)", { XX } },
5426 { "(bad)", { XX } },
5427 { "(bad)", { XX } },
5428 /* 08 */
5429 { "(bad)", { XX } },
5430 { "(bad)", { XX } },
5431 { "(bad)", { XX } },
5432 { "(bad)", { XX } },
5433 { "(bad)", { XX } },
5434 { "(bad)", { XX } },
5435 { "(bad)", { XX } },
5436 { "(bad)", { XX } },
5437 /* 10 */
5438 { "(bad)", { XX } },
5439 { "(bad)", { XX } },
5440 { "(bad)", { XX } },
5441 { "(bad)", { XX } },
5442 { "(bad)", { XX } },
5443 { "(bad)", { XX } },
5444 { "(bad)", { XX } },
5445 { "(bad)", { XX } },
5446 /* 18 */
5447 { "(bad)", { XX } },
5448 { "(bad)", { XX } },
5449 { "(bad)", { XX } },
5450 { "(bad)", { XX } },
5451 { "(bad)", { XX } },
5452 { "(bad)", { XX } },
5453 { "(bad)", { XX } },
5454 { "(bad)", { XX } },
5455 /* 20 */
5456 { "(bad)", { XX } },
5457 { "(bad)", { XX } },
5458 { "(bad)", { XX } },
5459 { "(bad)", { XX } },
5460 { "(bad)", { XX } },
5461 { "(bad)", { XX } },
5462 { "(bad)", { XX } },
5463 { "(bad)", { XX } },
5464 /* 28 */
5465 { "(bad)", { XX } },
5466 { "(bad)", { XX } },
5467 { "(bad)", { XX } },
5468 { "(bad)", { XX } },
5469 { "comps", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
5470 { "compd", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
5471 { "comss", { { OP_DREX3, w_mode }, { OP_DREX_FCMP, b_mode } } },
5472 { "comsd", { { OP_DREX3, d_mode }, { OP_DREX_FCMP, b_mode } } },
5473 /* 30 */
5474 { "(bad)", { XX } },
5475 { "(bad)", { XX } },
5476 { "(bad)", { XX } },
5477 { "(bad)", { XX } },
5478 { "(bad)", { XX } },
5479 { "(bad)", { XX } },
5480 { "(bad)", { XX } },
5481 { "(bad)", { XX } },
5482 /* 38 */
5483 { "(bad)", { XX } },
5484 { "(bad)", { XX } },
5485 { "(bad)", { XX } },
5486 { "(bad)", { XX } },
5487 { "(bad)", { XX } },
5488 { "(bad)", { XX } },
5489 { "(bad)", { XX } },
5490 { "(bad)", { XX } },
5491 /* 40 */
5492 { "(bad)", { XX } },
5493 { "(bad)", { XX } },
5494 { "(bad)", { XX } },
5495 { "(bad)", { XX } },
5496 { "(bad)", { XX } },
5497 { "(bad)", { XX } },
5498 { "(bad)", { XX } },
5499 { "(bad)", { XX } },
5500 /* 48 */
5501 { "(bad)", { XX } },
5502 { "(bad)", { XX } },
5503 { "(bad)", { XX } },
5504 { "(bad)", { XX } },
5505 { "pcomb", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5506 { "pcomw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5507 { "pcomd", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5508 { "pcomq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5509 /* 50 */
5510 { "(bad)", { XX } },
5511 { "(bad)", { XX } },
5512 { "(bad)", { XX } },
5513 { "(bad)", { XX } },
5514 { "(bad)", { XX } },
5515 { "(bad)", { XX } },
5516 { "(bad)", { XX } },
5517 { "(bad)", { XX } },
5518 /* 58 */
5519 { "(bad)", { XX } },
5520 { "(bad)", { XX } },
5521 { "(bad)", { XX } },
5522 { "(bad)", { XX } },
5523 { "(bad)", { XX } },
5524 { "(bad)", { XX } },
5525 { "(bad)", { XX } },
5526 { "(bad)", { XX } },
5527 /* 60 */
5528 { "(bad)", { XX } },
5529 { "(bad)", { XX } },
5530 { "(bad)", { XX } },
5531 { "(bad)", { XX } },
5532 { "(bad)", { XX } },
5533 { "(bad)", { XX } },
5534 { "(bad)", { XX } },
5535 { "(bad)", { XX } },
5536 /* 68 */
5537 { "(bad)", { XX } },
5538 { "(bad)", { XX } },
5539 { "(bad)", { XX } },
5540 { "(bad)", { XX } },
5541 { "pcomub", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5542 { "pcomuw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5543 { "pcomud", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5544 { "pcomuq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5545 /* 70 */
5546 { "(bad)", { XX } },
5547 { "(bad)", { XX } },
5548 { "(bad)", { XX } },
5549 { "(bad)", { XX } },
5550 { "(bad)", { XX } },
5551 { "(bad)", { XX } },
5552 { "(bad)", { XX } },
5553 { "(bad)", { XX } },
5554 /* 78 */
5555 { "(bad)", { XX } },
5556 { "(bad)", { XX } },
5557 { "(bad)", { XX } },
5558 { "(bad)", { XX } },
5559 { "(bad)", { XX } },
5560 { "(bad)", { XX } },
5561 { "(bad)", { XX } },
5562 { "(bad)", { XX } },
5563 /* 80 */
5564 { "(bad)", { XX } },
5565 { "(bad)", { XX } },
5566 { "(bad)", { XX } },
5567 { "(bad)", { XX } },
5568 { "(bad)", { XX } },
5569 { "(bad)", { XX } },
5570 { "(bad)", { XX } },
5571 { "(bad)", { XX } },
5572 /* 88 */
5573 { "(bad)", { XX } },
5574 { "(bad)", { XX } },
5575 { "(bad)", { XX } },
5576 { "(bad)", { XX } },
5577 { "(bad)", { XX } },
5578 { "(bad)", { XX } },
5579 { "(bad)", { XX } },
5580 { "(bad)", { XX } },
5581 /* 90 */
5582 { "(bad)", { XX } },
5583 { "(bad)", { XX } },
5584 { "(bad)", { XX } },
5585 { "(bad)", { XX } },
5586 { "(bad)", { XX } },
5587 { "(bad)", { XX } },
5588 { "(bad)", { XX } },
5589 { "(bad)", { XX } },
5590 /* 98 */
5591 { "(bad)", { XX } },
5592 { "(bad)", { XX } },
5593 { "(bad)", { XX } },
5594 { "(bad)", { XX } },
5595 { "(bad)", { XX } },
5596 { "(bad)", { XX } },
5597 { "(bad)", { XX } },
5598 { "(bad)", { XX } },
5599 /* a0 */
5600 { "(bad)", { XX } },
5601 { "(bad)", { XX } },
5602 { "(bad)", { XX } },
5603 { "(bad)", { XX } },
5604 { "(bad)", { XX } },
5605 { "(bad)", { XX } },
5606 { "(bad)", { XX } },
5607 { "(bad)", { XX } },
5608 /* a8 */
5609 { "(bad)", { XX } },
5610 { "(bad)", { XX } },
5611 { "(bad)", { XX } },
5612 { "(bad)", { XX } },
5613 { "(bad)", { XX } },
5614 { "(bad)", { XX } },
5615 { "(bad)", { XX } },
5616 { "(bad)", { XX } },
5617 /* b0 */
5618 { "(bad)", { XX } },
5619 { "(bad)", { XX } },
5620 { "(bad)", { XX } },
5621 { "(bad)", { XX } },
5622 { "(bad)", { XX } },
5623 { "(bad)", { XX } },
5624 { "(bad)", { XX } },
5625 { "(bad)", { XX } },
5626 /* b8 */
5627 { "(bad)", { XX } },
5628 { "(bad)", { XX } },
5629 { "(bad)", { XX } },
5630 { "(bad)", { XX } },
5631 { "(bad)", { XX } },
5632 { "(bad)", { XX } },
5633 { "(bad)", { XX } },
5634 { "(bad)", { XX } },
5635 /* c0 */
5636 { "(bad)", { XX } },
5637 { "(bad)", { XX } },
5638 { "(bad)", { XX } },
5639 { "(bad)", { XX } },
5640 { "(bad)", { XX } },
5641 { "(bad)", { XX } },
5642 { "(bad)", { XX } },
5643 { "(bad)", { XX } },
5644 /* c8 */
5645 { "(bad)", { XX } },
5646 { "(bad)", { XX } },
5647 { "(bad)", { XX } },
5648 { "(bad)", { XX } },
5649 { "(bad)", { XX } },
5650 { "(bad)", { XX } },
5651 { "(bad)", { XX } },
5652 { "(bad)", { XX } },
5653 /* d0 */
5654 { "(bad)", { XX } },
5655 { "(bad)", { XX } },
5656 { "(bad)", { XX } },
5657 { "(bad)", { XX } },
5658 { "(bad)", { XX } },
5659 { "(bad)", { XX } },
5660 { "(bad)", { XX } },
5661 { "(bad)", { XX } },
5662 /* d8 */
5663 { "(bad)", { XX } },
5664 { "(bad)", { XX } },
5665 { "(bad)", { XX } },
5666 { "(bad)", { XX } },
5667 { "(bad)", { XX } },
5668 { "(bad)", { XX } },
5669 { "(bad)", { XX } },
5670 { "(bad)", { XX } },
5671 /* e0 */
5672 { "(bad)", { XX } },
5673 { "(bad)", { XX } },
5674 { "(bad)", { XX } },
5675 { "(bad)", { XX } },
5676 { "(bad)", { XX } },
5677 { "(bad)", { XX } },
5678 { "(bad)", { XX } },
5679 { "(bad)", { XX } },
5680 /* e8 */
5681 { "(bad)", { XX } },
5682 { "(bad)", { XX } },
5683 { "(bad)", { XX } },
5684 { "(bad)", { XX } },
5685 { "(bad)", { XX } },
5686 { "(bad)", { XX } },
5687 { "(bad)", { XX } },
5688 { "(bad)", { XX } },
5689 /* f0 */
5690 { "(bad)", { XX } },
5691 { "(bad)", { XX } },
5692 { "(bad)", { XX } },
5693 { "(bad)", { XX } },
5694 { "(bad)", { XX } },
5695 { "(bad)", { XX } },
5696 { "(bad)", { XX } },
5697 { "(bad)", { XX } },
5698 /* f8 */
5699 { "(bad)", { XX } },
5700 { "(bad)", { XX } },
5701 { "(bad)", { XX } },
5702 { "(bad)", { XX } },
5703 { "(bad)", { XX } },
5704 { "(bad)", { XX } },
5705 { "(bad)", { XX } },
5706 { "(bad)", { XX } },
5707 },
5708 /* THREE_BYTE_0F38 */
5709 {
5710 /* 00 */
5711 { "pshufb", { MX, EM } },
5712 { "phaddw", { MX, EM } },
5713 { "phaddd", { MX, EM } },
5714 { "phaddsw", { MX, EM } },
5715 { "pmaddubsw", { MX, EM } },
5716 { "phsubw", { MX, EM } },
5717 { "phsubd", { MX, EM } },
5718 { "phsubsw", { MX, EM } },
5719 /* 08 */
5720 { "psignb", { MX, EM } },
5721 { "psignw", { MX, EM } },
5722 { "psignd", { MX, EM } },
5723 { "pmulhrsw", { MX, EM } },
5724 { "(bad)", { XX } },
5725 { "(bad)", { XX } },
5726 { "(bad)", { XX } },
5727 { "(bad)", { XX } },
5728 /* 10 */
5729 { PREFIX_TABLE (PREFIX_0F3810) },
5730 { "(bad)", { XX } },
5731 { "(bad)", { XX } },
5732 { "(bad)", { XX } },
5733 { PREFIX_TABLE (PREFIX_0F3814) },
5734 { PREFIX_TABLE (PREFIX_0F3815) },
5735 { "(bad)", { XX } },
5736 { PREFIX_TABLE (PREFIX_0F3817) },
5737 /* 18 */
5738 { "(bad)", { XX } },
5739 { "(bad)", { XX } },
5740 { "(bad)", { XX } },
5741 { "(bad)", { XX } },
5742 { "pabsb", { MX, EM } },
5743 { "pabsw", { MX, EM } },
5744 { "pabsd", { MX, EM } },
5745 { "(bad)", { XX } },
5746 /* 20 */
5747 { PREFIX_TABLE (PREFIX_0F3820) },
5748 { PREFIX_TABLE (PREFIX_0F3821) },
5749 { PREFIX_TABLE (PREFIX_0F3822) },
5750 { PREFIX_TABLE (PREFIX_0F3823) },
5751 { PREFIX_TABLE (PREFIX_0F3824) },
5752 { PREFIX_TABLE (PREFIX_0F3825) },
5753 { "(bad)", { XX } },
5754 { "(bad)", { XX } },
5755 /* 28 */
5756 { PREFIX_TABLE (PREFIX_0F3828) },
5757 { PREFIX_TABLE (PREFIX_0F3829) },
5758 { PREFIX_TABLE (PREFIX_0F382A) },
5759 { PREFIX_TABLE (PREFIX_0F382B) },
5760 { "(bad)", { XX } },
5761 { "(bad)", { XX } },
5762 { "(bad)", { XX } },
5763 { "(bad)", { XX } },
5764 /* 30 */
5765 { PREFIX_TABLE (PREFIX_0F3830) },
5766 { PREFIX_TABLE (PREFIX_0F3831) },
5767 { PREFIX_TABLE (PREFIX_0F3832) },
5768 { PREFIX_TABLE (PREFIX_0F3833) },
5769 { PREFIX_TABLE (PREFIX_0F3834) },
5770 { PREFIX_TABLE (PREFIX_0F3835) },
5771 { "(bad)", { XX } },
5772 { PREFIX_TABLE (PREFIX_0F3837) },
5773 /* 38 */
5774 { PREFIX_TABLE (PREFIX_0F3838) },
5775 { PREFIX_TABLE (PREFIX_0F3839) },
5776 { PREFIX_TABLE (PREFIX_0F383A) },
5777 { PREFIX_TABLE (PREFIX_0F383B) },
5778 { PREFIX_TABLE (PREFIX_0F383C) },
5779 { PREFIX_TABLE (PREFIX_0F383D) },
5780 { PREFIX_TABLE (PREFIX_0F383E) },
5781 { PREFIX_TABLE (PREFIX_0F383F) },
5782 /* 40 */
5783 { PREFIX_TABLE (PREFIX_0F3840) },
5784 { PREFIX_TABLE (PREFIX_0F3841) },
5785 { "(bad)", { XX } },
5786 { "(bad)", { XX } },
5787 { "(bad)", { XX } },
5788 { "(bad)", { XX } },
5789 { "(bad)", { XX } },
5790 { "(bad)", { XX } },
5791 /* 48 */
5792 { "(bad)", { XX } },
5793 { "(bad)", { XX } },
5794 { "(bad)", { XX } },
5795 { "(bad)", { XX } },
5796 { "(bad)", { XX } },
5797 { "(bad)", { XX } },
5798 { "(bad)", { XX } },
5799 { "(bad)", { XX } },
5800 /* 50 */
5801 { "(bad)", { XX } },
5802 { "(bad)", { XX } },
5803 { "(bad)", { XX } },
5804 { "(bad)", { XX } },
5805 { "(bad)", { XX } },
5806 { "(bad)", { XX } },
5807 { "(bad)", { XX } },
5808 { "(bad)", { XX } },
5809 /* 58 */
5810 { "(bad)", { XX } },
5811 { "(bad)", { XX } },
5812 { "(bad)", { XX } },
5813 { "(bad)", { XX } },
5814 { "(bad)", { XX } },
5815 { "(bad)", { XX } },
5816 { "(bad)", { XX } },
5817 { "(bad)", { XX } },
5818 /* 60 */
5819 { "(bad)", { XX } },
5820 { "(bad)", { XX } },
5821 { "(bad)", { XX } },
5822 { "(bad)", { XX } },
5823 { "(bad)", { XX } },
5824 { "(bad)", { XX } },
5825 { "(bad)", { XX } },
5826 { "(bad)", { XX } },
5827 /* 68 */
5828 { "(bad)", { XX } },
5829 { "(bad)", { XX } },
5830 { "(bad)", { XX } },
5831 { "(bad)", { XX } },
5832 { "(bad)", { XX } },
5833 { "(bad)", { XX } },
5834 { "(bad)", { XX } },
5835 { "(bad)", { XX } },
5836 /* 70 */
5837 { "(bad)", { XX } },
5838 { "(bad)", { XX } },
5839 { "(bad)", { XX } },
5840 { "(bad)", { XX } },
5841 { "(bad)", { XX } },
5842 { "(bad)", { XX } },
5843 { "(bad)", { XX } },
5844 { "(bad)", { XX } },
5845 /* 78 */
5846 { "(bad)", { XX } },
5847 { "(bad)", { XX } },
5848 { "(bad)", { XX } },
5849 { "(bad)", { XX } },
5850 { "(bad)", { XX } },
5851 { "(bad)", { XX } },
5852 { "(bad)", { XX } },
5853 { "(bad)", { XX } },
5854 /* 80 */
f1f8f695
L		 5855 { PREFIX_TABLE (PREFIX_0F3880) },
5856 { PREFIX_TABLE (PREFIX_0F3881) },
c0f3af97
L		 5857 { "(bad)", { XX } },
5858 { "(bad)", { XX } },
5859 { "(bad)", { XX } },
5860 { "(bad)", { XX } },
5861 { "(bad)", { XX } },
5862 { "(bad)", { XX } },
5863 /* 88 */
5864 { "(bad)", { XX } },
5865 { "(bad)", { XX } },
5866 { "(bad)", { XX } },
5867 { "(bad)", { XX } },
5868 { "(bad)", { XX } },
5869 { "(bad)", { XX } },
5870 { "(bad)", { XX } },
5871 { "(bad)", { XX } },
5872 /* 90 */
5873 { "(bad)", { XX } },
5874 { "(bad)", { XX } },
5875 { "(bad)", { XX } },
5876 { "(bad)", { XX } },
5877 { "(bad)", { XX } },
5878 { "(bad)", { XX } },
5879 { "(bad)", { XX } },
5880 { "(bad)", { XX } },
5881 /* 98 */
5882 { "(bad)", { XX } },
5883 { "(bad)", { XX } },
5884 { "(bad)", { XX } },
5885 { "(bad)", { XX } },
5886 { "(bad)", { XX } },
5887 { "(bad)", { XX } },
5888 { "(bad)", { XX } },
5889 { "(bad)", { XX } },
5890 /* a0 */
5891 { "(bad)", { XX } },
5892 { "(bad)", { XX } },
5893 { "(bad)", { XX } },
5894 { "(bad)", { XX } },
5895 { "(bad)", { XX } },
5896 { "(bad)", { XX } },
5897 { "(bad)", { XX } },
5898 { "(bad)", { XX } },
5899 /* a8 */
5900 { "(bad)", { XX } },
5901 { "(bad)", { XX } },
5902 { "(bad)", { XX } },
5903 { "(bad)", { XX } },
5904 { "(bad)", { XX } },
5905 { "(bad)", { XX } },
5906 { "(bad)", { XX } },
5907 { "(bad)", { XX } },
5908 /* b0 */
5909 { "(bad)", { XX } },
5910 { "(bad)", { XX } },
5911 { "(bad)", { XX } },
5912 { "(bad)", { XX } },
5913 { "(bad)", { XX } },
5914 { "(bad)", { XX } },
5915 { "(bad)", { XX } },
5916 { "(bad)", { XX } },
5917 /* b8 */
5918 { "(bad)", { XX } },
5919 { "(bad)", { XX } },
5920 { "(bad)", { XX } },
5921 { "(bad)", { XX } },
5922 { "(bad)", { XX } },
5923 { "(bad)", { XX } },
5924 { "(bad)", { XX } },
5925 { "(bad)", { XX } },
5926 /* c0 */
5927 { "(bad)", { XX } },
5928 { "(bad)", { XX } },
5929 { "(bad)", { XX } },
5930 { "(bad)", { XX } },
5931 { "(bad)", { XX } },
5932 { "(bad)", { XX } },
5933 { "(bad)", { XX } },
5934 { "(bad)", { XX } },
5935 /* c8 */
5936 { "(bad)", { XX } },
5937 { "(bad)", { XX } },
5938 { "(bad)", { XX } },
5939 { "(bad)", { XX } },
5940 { "(bad)", { XX } },
5941 { "(bad)", { XX } },
5942 { "(bad)", { XX } },
5943 { "(bad)", { XX } },
5944 /* d0 */
5945 { "(bad)", { XX } },
5946 { "(bad)", { XX } },
5947 { "(bad)", { XX } },
5948 { "(bad)", { XX } },
5949 { "(bad)", { XX } },
5950 { "(bad)", { XX } },
5951 { "(bad)", { XX } },
5952 { "(bad)", { XX } },
5953 /* d8 */
5954 { "(bad)", { XX } },
5955 { "(bad)", { XX } },
5956 { "(bad)", { XX } },
5957 { PREFIX_TABLE (PREFIX_0F38DB) },
5958 { PREFIX_TABLE (PREFIX_0F38DC) },
5959 { PREFIX_TABLE (PREFIX_0F38DD) },
5960 { PREFIX_TABLE (PREFIX_0F38DE) },
5961 { PREFIX_TABLE (PREFIX_0F38DF) },
5962 /* e0 */
5963 { "(bad)", { XX } },
5964 { "(bad)", { XX } },
5965 { "(bad)", { XX } },
5966 { "(bad)", { XX } },
5967 { "(bad)", { XX } },
5968 { "(bad)", { XX } },
5969 { "(bad)", { XX } },
5970 { "(bad)", { XX } },
5971 /* e8 */
5972 { "(bad)", { XX } },
5973 { "(bad)", { XX } },
5974 { "(bad)", { XX } },
5975 { "(bad)", { XX } },
5976 { "(bad)", { XX } },
5977 { "(bad)", { XX } },
5978 { "(bad)", { XX } },
5979 { "(bad)", { XX } },
5980 /* f0 */
5981 { PREFIX_TABLE (PREFIX_0F38F0) },
5982 { PREFIX_TABLE (PREFIX_0F38F1) },
5983 { "(bad)", { XX } },
5984 { "(bad)", { XX } },
5985 { "(bad)", { XX } },
5986 { "(bad)", { XX } },
5987 { "(bad)", { XX } },
5988 { "(bad)", { XX } },
5989 /* f8 */
5990 { "(bad)", { XX } },
5991 { "(bad)", { XX } },
5992 { "(bad)", { XX } },
5993 { "(bad)", { XX } },
5994 { "(bad)", { XX } },
5995 { "(bad)", { XX } },
5996 { "(bad)", { XX } },
5997 { "(bad)", { XX } },
5998 },
5999 /* THREE_BYTE_0F3A */
6000 {
6001 /* 00 */
6002 { "(bad)", { XX } },
6003 { "(bad)", { XX } },
6004 { "(bad)", { XX } },
6005 { "(bad)", { XX } },
6006 { "(bad)", { XX } },
6007 { "(bad)", { XX } },
6008 { "(bad)", { XX } },
6009 { "(bad)", { XX } },
6010 /* 08 */
6011 { PREFIX_TABLE (PREFIX_0F3A08) },
6012 { PREFIX_TABLE (PREFIX_0F3A09) },
6013 { PREFIX_TABLE (PREFIX_0F3A0A) },
6014 { PREFIX_TABLE (PREFIX_0F3A0B) },
6015 { PREFIX_TABLE (PREFIX_0F3A0C) },
6016 { PREFIX_TABLE (PREFIX_0F3A0D) },
6017 { PREFIX_TABLE (PREFIX_0F3A0E) },
6018 { "palignr", { MX, EM, Ib } },
6019 /* 10 */
6020 { "(bad)", { XX } },
6021 { "(bad)", { XX } },
6022 { "(bad)", { XX } },
6023 { "(bad)", { XX } },
6024 { PREFIX_TABLE (PREFIX_0F3A14) },
6025 { PREFIX_TABLE (PREFIX_0F3A15) },
6026 { PREFIX_TABLE (PREFIX_0F3A16) },
6027 { PREFIX_TABLE (PREFIX_0F3A17) },
6028 /* 18 */
6029 { "(bad)", { XX } },
6030 { "(bad)", { XX } },
6031 { "(bad)", { XX } },
6032 { "(bad)", { XX } },
6033 { "(bad)", { XX } },
6034 { "(bad)", { XX } },
6035 { "(bad)", { XX } },
6036 { "(bad)", { XX } },
6037 /* 20 */
6038 { PREFIX_TABLE (PREFIX_0F3A20) },
6039 { PREFIX_TABLE (PREFIX_0F3A21) },
6040 { PREFIX_TABLE (PREFIX_0F3A22) },
6041 { "(bad)", { XX } },
6042 { "(bad)", { XX } },
6043 { "(bad)", { XX } },
6044 { "(bad)", { XX } },
6045 { "(bad)", { XX } },
6046 /* 28 */
6047 { "(bad)", { XX } },
6048 { "(bad)", { XX } },
6049 { "(bad)", { XX } },
6050 { "(bad)", { XX } },
6051 { "(bad)", { XX } },
6052 { "(bad)", { XX } },
6053 { "(bad)", { XX } },
6054 { "(bad)", { XX } },
6055 /* 30 */
4e7d34a6
L		 6056 { "(bad)", { XX } },
6057 { "(bad)", { XX } },
6058 { "(bad)", { XX } },
6059 { "(bad)", { XX } },
6060 { "(bad)", { XX } },
6061 { "(bad)", { XX } },
6062 { "(bad)", { XX } },
6063 { "(bad)", { XX } },
85f10a01 6064 /* 38 */
4e7d34a6
L		 6065 { "(bad)", { XX } },
6066 { "(bad)", { XX } },
6067 { "(bad)", { XX } },
6068 { "(bad)", { XX } },
6069 { "(bad)", { XX } },
6070 { "(bad)", { XX } },
6071 { "(bad)", { XX } },
6072 { "(bad)", { XX } },
85f10a01 6073 /* 40 */
c0f3af97
L		 6074 { PREFIX_TABLE (PREFIX_0F3A40) },
6075 { PREFIX_TABLE (PREFIX_0F3A41) },
6076 { PREFIX_TABLE (PREFIX_0F3A42) },
6077 { "(bad)", { XX } },
6078 { PREFIX_TABLE (PREFIX_0F3A44) },
6079 { "(bad)", { XX } },
6080 { "(bad)", { XX } },
6081 { "(bad)", { XX } },
85f10a01 6082 /* 48 */
4e7d34a6
L		 6083 { "(bad)", { XX } },
6084 { "(bad)", { XX } },
6085 { "(bad)", { XX } },
6086 { "(bad)", { XX } },
4e7d34a6
L		 6087 { "(bad)", { XX } },
6088 { "(bad)", { XX } },
6089 { "(bad)", { XX } },
6090 { "(bad)", { XX } },
c0f3af97 6091 /* 50 */
4e7d34a6
L		 6092 { "(bad)", { XX } },
6093 { "(bad)", { XX } },
6094 { "(bad)", { XX } },
6095 { "(bad)", { XX } },
4e7d34a6
L		 6096 { "(bad)", { XX } },
6097 { "(bad)", { XX } },
6098 { "(bad)", { XX } },
6099 { "(bad)", { XX } },
c0f3af97 6100 /* 58 */
4e7d34a6
L		 6101 { "(bad)", { XX } },
6102 { "(bad)", { XX } },
6103 { "(bad)", { XX } },
6104 { "(bad)", { XX } },
4e7d34a6
L		 6105 { "(bad)", { XX } },
6106 { "(bad)", { XX } },
6107 { "(bad)", { XX } },
6108 { "(bad)", { XX } },
c0f3af97
L		 6109 /* 60 */
6110 { PREFIX_TABLE (PREFIX_0F3A60) },
6111 { PREFIX_TABLE (PREFIX_0F3A61) },
6112 { PREFIX_TABLE (PREFIX_0F3A62) },
6113 { PREFIX_TABLE (PREFIX_0F3A63) },
4e7d34a6
L		 6114 { "(bad)", { XX } },
6115 { "(bad)", { XX } },
6116 { "(bad)", { XX } },
6117 { "(bad)", { XX } },
6118 /* 68 */
6119 { "(bad)", { XX } },
6120 { "(bad)", { XX } },
6121 { "(bad)", { XX } },
6122 { "(bad)", { XX } },
6123 { "(bad)", { XX } },
6124 { "(bad)", { XX } },
6125 { "(bad)", { XX } },
6126 { "(bad)", { XX } },
85f10a01 6127 /* 70 */
4e7d34a6
L		 6128 { "(bad)", { XX } },
6129 { "(bad)", { XX } },
6130 { "(bad)", { XX } },
6131 { "(bad)", { XX } },
6132 { "(bad)", { XX } },
6133 { "(bad)", { XX } },
6134 { "(bad)", { XX } },
6135 { "(bad)", { XX } },
85f10a01 6136 /* 78 */
4e7d34a6
L		 6137 { "(bad)", { XX } },
6138 { "(bad)", { XX } },
6139 { "(bad)", { XX } },
6140 { "(bad)", { XX } },
6141 { "(bad)", { XX } },
6142 { "(bad)", { XX } },
6143 { "(bad)", { XX } },
6144 { "(bad)", { XX } },
85f10a01 6145 /* 80 */
4e7d34a6
L		 6146 { "(bad)", { XX } },
6147 { "(bad)", { XX } },
6148 { "(bad)", { XX } },
6149 { "(bad)", { XX } },
6150 { "(bad)", { XX } },
c0f3af97
L		 6151 { "(bad)", { XX } },
6152 { "(bad)", { XX } },
6153 { "(bad)", { XX } },
85f10a01 6154 /* 88 */
4e7d34a6
L		 6155 { "(bad)", { XX } },
6156 { "(bad)", { XX } },
6157 { "(bad)", { XX } },
6158 { "(bad)", { XX } },
6159 { "(bad)", { XX } },
6160 { "(bad)", { XX } },
c0f3af97
L		 6161 { "(bad)", { XX } },
6162 { "(bad)", { XX } },
85f10a01 6163 /* 90 */
4e7d34a6
L		 6164 { "(bad)", { XX } },
6165 { "(bad)", { XX } },
6166 { "(bad)", { XX } },
6167 { "(bad)", { XX } },
6168 { "(bad)", { XX } },
c0f3af97
L		 6169 { "(bad)", { XX } },
6170 { "(bad)", { XX } },
6171 { "(bad)", { XX } },
85f10a01 6172 /* 98 */
4e7d34a6
L		 6173 { "(bad)", { XX } },
6174 { "(bad)", { XX } },
6175 { "(bad)", { XX } },
6176 { "(bad)", { XX } },
6177 { "(bad)", { XX } },
6178 { "(bad)", { XX } },
c0f3af97
L		 6179 { "(bad)", { XX } },
6180 { "(bad)", { XX } },
85f10a01 6181 /* a0 */
4e7d34a6
L		 6182 { "(bad)", { XX } },
6183 { "(bad)", { XX } },
6184 { "(bad)", { XX } },
6185 { "(bad)", { XX } },
6186 { "(bad)", { XX } },
6187 { "(bad)", { XX } },
c0f3af97 6188 { "(bad)", { XX } },
4e7d34a6 6189 { "(bad)", { XX } },
85f10a01 6190 /* a8 */
4e7d34a6
L		 6191 { "(bad)", { XX } },
6192 { "(bad)", { XX } },
6193 { "(bad)", { XX } },
6194 { "(bad)", { XX } },
6195 { "(bad)", { XX } },
6196 { "(bad)", { XX } },
6197 { "(bad)", { XX } },
6198 { "(bad)", { XX } },
85f10a01 6199 /* b0 */
4e7d34a6
L		 6200 { "(bad)", { XX } },
6201 { "(bad)", { XX } },
6202 { "(bad)", { XX } },
6203 { "(bad)", { XX } },
6204 { "(bad)", { XX } },
6205 { "(bad)", { XX } },
c0f3af97 6206 { "(bad)", { XX } },
4e7d34a6 6207 { "(bad)", { XX } },
85f10a01 6208 /* b8 */
4e7d34a6
L		 6209 { "(bad)", { XX } },
6210 { "(bad)", { XX } },
6211 { "(bad)", { XX } },
6212 { "(bad)", { XX } },
6213 { "(bad)", { XX } },
6214 { "(bad)", { XX } },
6215 { "(bad)", { XX } },
6216 { "(bad)", { XX } },
85f10a01 6217 /* c0 */
4e7d34a6
L		 6218 { "(bad)", { XX } },
6219 { "(bad)", { XX } },
6220 { "(bad)", { XX } },
6221 { "(bad)", { XX } },
6222 { "(bad)", { XX } },
6223 { "(bad)", { XX } },
6224 { "(bad)", { XX } },
6225 { "(bad)", { XX } },
85f10a01 6226 /* c8 */
4e7d34a6
L		 6227 { "(bad)", { XX } },
6228 { "(bad)", { XX } },
6229 { "(bad)", { XX } },
6230 { "(bad)", { XX } },
6231 { "(bad)", { XX } },
6232 { "(bad)", { XX } },
6233 { "(bad)", { XX } },
6234 { "(bad)", { XX } },
85f10a01 6235 /* d0 */
4e7d34a6
L		 6236 { "(bad)", { XX } },
6237 { "(bad)", { XX } },
6238 { "(bad)", { XX } },
6239 { "(bad)", { XX } },
6240 { "(bad)", { XX } },
6241 { "(bad)", { XX } },
6242 { "(bad)", { XX } },
6243 { "(bad)", { XX } },
85f10a01 6244 /* d8 */
4e7d34a6
L		 6245 { "(bad)", { XX } },
6246 { "(bad)", { XX } },
6247 { "(bad)", { XX } },
6248 { "(bad)", { XX } },
6249 { "(bad)", { XX } },
6250 { "(bad)", { XX } },
6251 { "(bad)", { XX } },
c0f3af97 6252 { PREFIX_TABLE (PREFIX_0F3ADF) },
85f10a01 6253 /* e0 */
4e7d34a6
L		 6254 { "(bad)", { XX } },
6255 { "(bad)", { XX } },
6256 { "(bad)", { XX } },
6257 { "(bad)", { XX } },
6258 { "(bad)", { XX } },
6259 { "(bad)", { XX } },
6260 { "(bad)", { XX } },
6261 { "(bad)", { XX } },
85f10a01 6262 /* e8 */
4e7d34a6
L		 6263 { "(bad)", { XX } },
6264 { "(bad)", { XX } },
6265 { "(bad)", { XX } },
6266 { "(bad)", { XX } },
6267 { "(bad)", { XX } },
6268 { "(bad)", { XX } },
6269 { "(bad)", { XX } },
6270 { "(bad)", { XX } },
85f10a01 6271 /* f0 */
4e7d34a6
L		 6272 { "(bad)", { XX } },
6273 { "(bad)", { XX } },
6274 { "(bad)", { XX } },
6275 { "(bad)", { XX } },
6276 { "(bad)", { XX } },
6277 { "(bad)", { XX } },
6278 { "(bad)", { XX } },
6279 { "(bad)", { XX } },
85f10a01 6280 /* f8 */
4e7d34a6
L		 6281 { "(bad)", { XX } },
6282 { "(bad)", { XX } },
6283 { "(bad)", { XX } },
6284 { "(bad)", { XX } },
6285 { "(bad)", { XX } },
6286 { "(bad)", { XX } },
6287 { "(bad)", { XX } },
6288 { "(bad)", { XX } },
85f10a01 6289 },
c0f3af97 6290 /* THREE_BYTE_0F7A */
85f10a01
MM		 6291 {
6292 /* 00 */
4e7d34a6
L		 6293 { "(bad)", { XX } },
6294 { "(bad)", { XX } },
6295 { "(bad)", { XX } },
6296 { "(bad)", { XX } },
6297 { "(bad)", { XX } },
6298 { "(bad)", { XX } },
6299 { "(bad)", { XX } },
6300 { "(bad)", { XX } },
85f10a01 6301 /* 08 */
4e7d34a6
L		 6302 { "(bad)", { XX } },
6303 { "(bad)", { XX } },
6304 { "(bad)", { XX } },
6305 { "(bad)", { XX } },
6306 { "(bad)", { XX } },
6307 { "(bad)", { XX } },
6308 { "(bad)", { XX } },
6309 { "(bad)", { XX } },
85f10a01 6310 /* 10 */
c0f3af97
L		 6311 { "frczps", { XM, EXq } },
6312 { "frczpd", { XM, EXq } },
6313 { "frczss", { XM, EXq } },
6314 { "frczsd", { XM, EXq } },
4e7d34a6
L		 6315 { "(bad)", { XX } },
6316 { "(bad)", { XX } },
6317 { "(bad)", { XX } },
6318 { "(bad)", { XX } },
85f10a01 6319 /* 18 */
4e7d34a6
L		 6320 { "(bad)", { XX } },
6321 { "(bad)", { XX } },
6322 { "(bad)", { XX } },
6323 { "(bad)", { XX } },
6324 { "(bad)", { XX } },
6325 { "(bad)", { XX } },
6326 { "(bad)", { XX } },
6327 { "(bad)", { XX } },
85f10a01 6328 /* 20 */
c0f3af97 6329 { "ptest", { XX } },
4e7d34a6
L		 6330 { "(bad)", { XX } },
6331 { "(bad)", { XX } },
6332 { "(bad)", { XX } },
6333 { "(bad)", { XX } },
6334 { "(bad)", { XX } },
6335 { "(bad)", { XX } },
6336 { "(bad)", { XX } },
85f10a01 6337 /* 28 */
4e7d34a6
L		 6338 { "(bad)", { XX } },
6339 { "(bad)", { XX } },
6340 { "(bad)", { XX } },
6341 { "(bad)", { XX } },
4e7d34a6
L		 6342 { "(bad)", { XX } },
6343 { "(bad)", { XX } },
6344 { "(bad)", { XX } },
6345 { "(bad)", { XX } },
c0f3af97
L		 6346 /* 30 */
6347 { "cvtph2ps", { XM, EXd } },
6348 { "cvtps2ph", { EXd, XM } },
4e7d34a6 6349 { "(bad)", { XX } },
4e7d34a6
L		 6350 { "(bad)", { XX } },
6351 { "(bad)", { XX } },
6352 { "(bad)", { XX } },
6353 { "(bad)", { XX } },
6354 { "(bad)", { XX } },
c0f3af97 6355 /* 38 */
4e7d34a6
L		 6356 { "(bad)", { XX } },
6357 { "(bad)", { XX } },
6358 { "(bad)", { XX } },
4e7d34a6
L		 6359 { "(bad)", { XX } },
6360 { "(bad)", { XX } },
6361 { "(bad)", { XX } },
6362 { "(bad)", { XX } },
6363 { "(bad)", { XX } },
c0f3af97 6364 /* 40 */
4e7d34a6 6365 { "(bad)", { XX } },
c0f3af97
L		 6366 { "phaddbw", { XM, EXq } },
6367 { "phaddbd", { XM, EXq } },
6368 { "phaddbq", { XM, EXq } },
4e7d34a6
L		 6369 { "(bad)", { XX } },
6370 { "(bad)", { XX } },
c0f3af97
L		 6371 { "phaddwd", { XM, EXq } },
6372 { "phaddwq", { XM, EXq } },
85f10a01 6373 /* 48 */
4e7d34a6
L		 6374 { "(bad)", { XX } },
6375 { "(bad)", { XX } },
6376 { "(bad)", { XX } },
c0f3af97 6377 { "phadddq", { XM, EXq } },
4e7d34a6
L		 6378 { "(bad)", { XX } },
6379 { "(bad)", { XX } },
6380 { "(bad)", { XX } },
6381 { "(bad)", { XX } },
c0f3af97 6382 /* 50 */
4e7d34a6 6383 { "(bad)", { XX } },
c0f3af97
L		 6384 { "phaddubw", { XM, EXq } },
6385 { "phaddubd", { XM, EXq } },
6386 { "phaddubq", { XM, EXq } },
4e7d34a6
L		 6387 { "(bad)", { XX } },
6388 { "(bad)", { XX } },
c0f3af97
L		 6389 { "phadduwd", { XM, EXq } },
6390 { "phadduwq", { XM, EXq } },
85f10a01 6391 /* 58 */
4e7d34a6
L		 6392 { "(bad)", { XX } },
6393 { "(bad)", { XX } },
6394 { "(bad)", { XX } },
c0f3af97 6395 { "phaddudq", { XM, EXq } },
4e7d34a6
L		 6396 { "(bad)", { XX } },
6397 { "(bad)", { XX } },
6398 { "(bad)", { XX } },
6399 { "(bad)", { XX } },
85f10a01 6400 /* 60 */
4e7d34a6 6401 { "(bad)", { XX } },
c0f3af97
L		 6402 { "phsubbw", { XM, EXq } },
6403 { "phsubbd", { XM, EXq } },
6404 { "phsubbq", { XM, EXq } },
4e7d34a6
L		 6405 { "(bad)", { XX } },
6406 { "(bad)", { XX } },
6407 { "(bad)", { XX } },
6408 { "(bad)", { XX } },
c0f3af97
L		 6409 /* 68 */
6410 { "(bad)", { XX } },
4e7d34a6
L		 6411 { "(bad)", { XX } },
6412 { "(bad)", { XX } },
6413 { "(bad)", { XX } },
4e7d34a6
L		 6414 { "(bad)", { XX } },
6415 { "(bad)", { XX } },
6416 { "(bad)", { XX } },
6417 { "(bad)", { XX } },
85f10a01 6418 /* 70 */
4e7d34a6
L		 6419 { "(bad)", { XX } },
6420 { "(bad)", { XX } },
6421 { "(bad)", { XX } },
6422 { "(bad)", { XX } },
6423 { "(bad)", { XX } },
6424 { "(bad)", { XX } },
6425 { "(bad)", { XX } },
6426 { "(bad)", { XX } },
85f10a01 6427 /* 78 */
4e7d34a6
L		 6428 { "(bad)", { XX } },
6429 { "(bad)", { XX } },
6430 { "(bad)", { XX } },
6431 { "(bad)", { XX } },
6432 { "(bad)", { XX } },
6433 { "(bad)", { XX } },
6434 { "(bad)", { XX } },
6435 { "(bad)", { XX } },
85f10a01 6436 /* 80 */
4e7d34a6
L		 6437 { "(bad)", { XX } },
6438 { "(bad)", { XX } },
6439 { "(bad)", { XX } },
6440 { "(bad)", { XX } },
6441 { "(bad)", { XX } },
6442 { "(bad)", { XX } },
6443 { "(bad)", { XX } },
6444 { "(bad)", { XX } },
6445 /* 88 */
6446 { "(bad)", { XX } },
6447 { "(bad)", { XX } },
6448 { "(bad)", { XX } },
6449 { "(bad)", { XX } },
6450 { "(bad)", { XX } },
6451 { "(bad)", { XX } },
6452 { "(bad)", { XX } },
6453 { "(bad)", { XX } },
6454 /* 90 */
6455 { "(bad)", { XX } },
6456 { "(bad)", { XX } },
6457 { "(bad)", { XX } },
6458 { "(bad)", { XX } },
6459 { "(bad)", { XX } },
6460 { "(bad)", { XX } },
6461 { "(bad)", { XX } },
6462 { "(bad)", { XX } },
6463 /* 98 */
6464 { "(bad)", { XX } },
6465 { "(bad)", { XX } },
6466 { "(bad)", { XX } },
6467 { "(bad)", { XX } },
6468 { "(bad)", { XX } },
6469 { "(bad)", { XX } },
6470 { "(bad)", { XX } },
6471 { "(bad)", { XX } },
6472 /* a0 */
6473 { "(bad)", { XX } },
6474 { "(bad)", { XX } },
6475 { "(bad)", { XX } },
6476 { "(bad)", { XX } },
6477 { "(bad)", { XX } },
6478 { "(bad)", { XX } },
6479 { "(bad)", { XX } },
6480 { "(bad)", { XX } },
6481 /* a8 */
6482 { "(bad)", { XX } },
6483 { "(bad)", { XX } },
6484 { "(bad)", { XX } },
6485 { "(bad)", { XX } },
6486 { "(bad)", { XX } },
6487 { "(bad)", { XX } },
6488 { "(bad)", { XX } },
6489 { "(bad)", { XX } },
6490 /* b0 */
6491 { "(bad)", { XX } },
6492 { "(bad)", { XX } },
6493 { "(bad)", { XX } },
6494 { "(bad)", { XX } },
6495 { "(bad)", { XX } },
6496 { "(bad)", { XX } },
6497 { "(bad)", { XX } },
6498 { "(bad)", { XX } },
6499 /* b8 */
6500 { "(bad)", { XX } },
6501 { "(bad)", { XX } },
6502 { "(bad)", { XX } },
6503 { "(bad)", { XX } },
6504 { "(bad)", { XX } },
6505 { "(bad)", { XX } },
6506 { "(bad)", { XX } },
6507 { "(bad)", { XX } },
6508 /* c0 */
6509 { "(bad)", { XX } },
6510 { "(bad)", { XX } },
6511 { "(bad)", { XX } },
6512 { "(bad)", { XX } },
6513 { "(bad)", { XX } },
6514 { "(bad)", { XX } },
6515 { "(bad)", { XX } },
6516 { "(bad)", { XX } },
6517 /* c8 */
6518 { "(bad)", { XX } },
6519 { "(bad)", { XX } },
6520 { "(bad)", { XX } },
6521 { "(bad)", { XX } },
6522 { "(bad)", { XX } },
6523 { "(bad)", { XX } },
6524 { "(bad)", { XX } },
6525 { "(bad)", { XX } },
6526 /* d0 */
6527 { "(bad)", { XX } },
6528 { "(bad)", { XX } },
6529 { "(bad)", { XX } },
6530 { "(bad)", { XX } },
6531 { "(bad)", { XX } },
6532 { "(bad)", { XX } },
6533 { "(bad)", { XX } },
6534 { "(bad)", { XX } },
6535 /* d8 */
6536 { "(bad)", { XX } },
6537 { "(bad)", { XX } },
6538 { "(bad)", { XX } },
6539 { "(bad)", { XX } },
6540 { "(bad)", { XX } },
6541 { "(bad)", { XX } },
6542 { "(bad)", { XX } },
6543 { "(bad)", { XX } },
6544 /* e0 */
6545 { "(bad)", { XX } },
6546 { "(bad)", { XX } },
6547 { "(bad)", { XX } },
6548 { "(bad)", { XX } },
6549 { "(bad)", { XX } },
6550 { "(bad)", { XX } },
6551 { "(bad)", { XX } },
6552 { "(bad)", { XX } },
6553 /* e8 */
6554 { "(bad)", { XX } },
6555 { "(bad)", { XX } },
6556 { "(bad)", { XX } },
6557 { "(bad)", { XX } },
6558 { "(bad)", { XX } },
6559 { "(bad)", { XX } },
6560 { "(bad)", { XX } },
6561 { "(bad)", { XX } },
6562 /* f0 */
6563 { "(bad)", { XX } },
6564 { "(bad)", { XX } },
6565 { "(bad)", { XX } },
6566 { "(bad)", { XX } },
6567 { "(bad)", { XX } },
6568 { "(bad)", { XX } },
6569 { "(bad)", { XX } },
6570 { "(bad)", { XX } },
6571 /* f8 */
6572 { "(bad)", { XX } },
6573 { "(bad)", { XX } },
6574 { "(bad)", { XX } },
6575 { "(bad)", { XX } },
6576 { "(bad)", { XX } },
6577 { "(bad)", { XX } },
6578 { "(bad)", { XX } },
6579 { "(bad)", { XX } },
6580 },
c0f3af97 6581 /* THREE_BYTE_0F7B */
4e7d34a6
L		 6582 {
6583 /* 00 */
c0f3af97
L		 6584 { "(bad)", { XX } },
6585 { "(bad)", { XX } },
6586 { "(bad)", { XX } },
6587 { "(bad)", { XX } },
6588 { "(bad)", { XX } },
6589 { "(bad)", { XX } },
6590 { "(bad)", { XX } },
6591 { "(bad)", { XX } },
4e7d34a6 6592 /* 08 */
c0f3af97
L		 6593 { "(bad)", { XX } },
6594 { "(bad)", { XX } },
6595 { "(bad)", { XX } },
6596 { "(bad)", { XX } },
d5d7db8e
L		 6597 { "(bad)", { XX } },
6598 { "(bad)", { XX } },
6599 { "(bad)", { XX } },
6600 { "(bad)", { XX } },
4e7d34a6 6601 /* 10 */
d5d7db8e
L		 6602 { "(bad)", { XX } },
6603 { "(bad)", { XX } },
6604 { "(bad)", { XX } },
d5d7db8e 6605 { "(bad)", { XX } },
c0f3af97
L		 6606 { "(bad)", { XX } },
6607 { "(bad)", { XX } },
6608 { "(bad)", { XX } },
6609 { "(bad)", { XX } },
4e7d34a6 6610 /* 18 */
d5d7db8e
L		 6611 { "(bad)", { XX } },
6612 { "(bad)", { XX } },
6613 { "(bad)", { XX } },
6614 { "(bad)", { XX } },
c0f3af97
L		 6615 { "(bad)", { XX } },
6616 { "(bad)", { XX } },
6617 { "(bad)", { XX } },
d5d7db8e 6618 { "(bad)", { XX } },
4e7d34a6 6619 /* 20 */
c0f3af97
L		 6620 { "(bad)", { XX } },
6621 { "(bad)", { XX } },
6622 { "(bad)", { XX } },
6623 { "(bad)", { XX } },
6624 { "(bad)", { XX } },
6625 { "(bad)", { XX } },
d5d7db8e
L		 6626 { "(bad)", { XX } },
6627 { "(bad)", { XX } },
4e7d34a6 6628 /* 28 */
c0f3af97
L		 6629 { "(bad)", { XX } },
6630 { "(bad)", { XX } },
6631 { "(bad)", { XX } },
6632 { "(bad)", { XX } },
d5d7db8e
L		 6633 { "(bad)", { XX } },
6634 { "(bad)", { XX } },
6635 { "(bad)", { XX } },
6636 { "(bad)", { XX } },
4e7d34a6 6637 /* 30 */
d5d7db8e 6638 { "(bad)", { XX } },
d5d7db8e
L		 6639 { "(bad)", { XX } },
6640 { "(bad)", { XX } },
6641 { "(bad)", { XX } },
6642 { "(bad)", { XX } },
6643 { "(bad)", { XX } },
6644 { "(bad)", { XX } },
c0f3af97
L		 6645 { "(bad)", { XX } },
6646 /* 38 */
6647 { "(bad)", { XX } },
6648 { "(bad)", { XX } },
6649 { "(bad)", { XX } },
6650 { "(bad)", { XX } },
d5d7db8e
L		 6651 { "(bad)", { XX } },
6652 { "(bad)", { XX } },
6653 { "(bad)", { XX } },
6654 { "(bad)", { XX } },
c0f3af97
L		 6655 /* 40 */
6656 { "protb", { XM, EXq, Ib } },
6657 { "protw", { XM, EXq, Ib } },
6658 { "protd", { XM, EXq, Ib } },
6659 { "protq", { XM, EXq, Ib } },
6660 { "pshlb", { XM, EXq, Ib } },
6661 { "pshlw", { XM, EXq, Ib } },
6662 { "pshld", { XM, EXq, Ib } },
6663 { "pshlq", { XM, EXq, Ib } },
6664 /* 48 */
6665 { "pshab", { XM, EXq, Ib } },
6666 { "pshaw", { XM, EXq, Ib } },
6667 { "pshad", { XM, EXq, Ib } },
6668 { "pshaq", { XM, EXq, Ib } },
d5d7db8e
L		 6669 { "(bad)", { XX } },
6670 { "(bad)", { XX } },
6671 { "(bad)", { XX } },
6672 { "(bad)", { XX } },
4e7d34a6 6673 /* 50 */
d5d7db8e
L		 6674 { "(bad)", { XX } },
6675 { "(bad)", { XX } },
6676 { "(bad)", { XX } },
6677 { "(bad)", { XX } },
6678 { "(bad)", { XX } },
6679 { "(bad)", { XX } },
6680 { "(bad)", { XX } },
6681 { "(bad)", { XX } },
4e7d34a6 6682 /* 58 */
d5d7db8e
L		 6683 { "(bad)", { XX } },
6684 { "(bad)", { XX } },
6685 { "(bad)", { XX } },
6686 { "(bad)", { XX } },
6687 { "(bad)", { XX } },
6688 { "(bad)", { XX } },
6689 { "(bad)", { XX } },
6690 { "(bad)", { XX } },
4e7d34a6 6691 /* 60 */
d5d7db8e
L		 6692 { "(bad)", { XX } },
6693 { "(bad)", { XX } },
6694 { "(bad)", { XX } },
6695 { "(bad)", { XX } },
6696 { "(bad)", { XX } },
6697 { "(bad)", { XX } },
6698 { "(bad)", { XX } },
6699 { "(bad)", { XX } },
4e7d34a6 6700 /* 68 */
d5d7db8e
L		 6701 { "(bad)", { XX } },
6702 { "(bad)", { XX } },
6703 { "(bad)", { XX } },
6704 { "(bad)", { XX } },
6705 { "(bad)", { XX } },
6706 { "(bad)", { XX } },
6707 { "(bad)", { XX } },
6708 { "(bad)", { XX } },
4e7d34a6 6709 /* 70 */
d5d7db8e
L		 6710 { "(bad)", { XX } },
6711 { "(bad)", { XX } },
6712 { "(bad)", { XX } },
6713 { "(bad)", { XX } },
6714 { "(bad)", { XX } },
6715 { "(bad)", { XX } },
6716 { "(bad)", { XX } },
6717 { "(bad)", { XX } },
4e7d34a6 6718 /* 78 */
d5d7db8e
L		 6719 { "(bad)", { XX } },
6720 { "(bad)", { XX } },
6721 { "(bad)", { XX } },
6722 { "(bad)", { XX } },
6723 { "(bad)", { XX } },
6724 { "(bad)", { XX } },
6725 { "(bad)", { XX } },
6726 { "(bad)", { XX } },
4e7d34a6 6727 /* 80 */
d5d7db8e
L		 6728 { "(bad)", { XX } },
6729 { "(bad)", { XX } },
6730 { "(bad)", { XX } },
6731 { "(bad)", { XX } },
6732 { "(bad)", { XX } },
6733 { "(bad)", { XX } },
6734 { "(bad)", { XX } },
6735 { "(bad)", { XX } },
4e7d34a6 6736 /* 88 */
d5d7db8e
L		 6737 { "(bad)", { XX } },
6738 { "(bad)", { XX } },
6739 { "(bad)", { XX } },
6740 { "(bad)", { XX } },
6741 { "(bad)", { XX } },
6742 { "(bad)", { XX } },
6743 { "(bad)", { XX } },
6744 { "(bad)", { XX } },
4e7d34a6 6745 /* 90 */
d5d7db8e
L		 6746 { "(bad)", { XX } },
6747 { "(bad)", { XX } },
6748 { "(bad)", { XX } },
6749 { "(bad)", { XX } },
6750 { "(bad)", { XX } },
6751 { "(bad)", { XX } },
6752 { "(bad)", { XX } },
6753 { "(bad)", { XX } },
4e7d34a6 6754 /* 98 */
d5d7db8e
L		 6755 { "(bad)", { XX } },
6756 { "(bad)", { XX } },
6757 { "(bad)", { XX } },
6758 { "(bad)", { XX } },
6759 { "(bad)", { XX } },
6760 { "(bad)", { XX } },
6761 { "(bad)", { XX } },
6762 { "(bad)", { XX } },
4e7d34a6 6763 /* a0 */
d5d7db8e
L		 6764 { "(bad)", { XX } },
6765 { "(bad)", { XX } },
6766 { "(bad)", { XX } },
6767 { "(bad)", { XX } },
6768 { "(bad)", { XX } },
6769 { "(bad)", { XX } },
6770 { "(bad)", { XX } },
6771 { "(bad)", { XX } },
4e7d34a6 6772 /* a8 */
d5d7db8e
L		 6773 { "(bad)", { XX } },
6774 { "(bad)", { XX } },
6775 { "(bad)", { XX } },
6776 { "(bad)", { XX } },
6777 { "(bad)", { XX } },
6778 { "(bad)", { XX } },
6779 { "(bad)", { XX } },
6780 { "(bad)", { XX } },
6781 /* b0 */
6782 { "(bad)", { XX } },
6783 { "(bad)", { XX } },
6784 { "(bad)", { XX } },
6785 { "(bad)", { XX } },
6786 { "(bad)", { XX } },
6787 { "(bad)", { XX } },
6788 { "(bad)", { XX } },
6789 { "(bad)", { XX } },
85f10a01 6790 /* b8 */
d5d7db8e
L		 6791 { "(bad)", { XX } },
6792 { "(bad)", { XX } },
6793 { "(bad)", { XX } },
6794 { "(bad)", { XX } },
6795 { "(bad)", { XX } },
6796 { "(bad)", { XX } },
6797 { "(bad)", { XX } },
6798 { "(bad)", { XX } },
85f10a01 6799 /* c0 */
d5d7db8e
L		 6800 { "(bad)", { XX } },
6801 { "(bad)", { XX } },
6802 { "(bad)", { XX } },
6803 { "(bad)", { XX } },
6804 { "(bad)", { XX } },
6805 { "(bad)", { XX } },
6806 { "(bad)", { XX } },
6807 { "(bad)", { XX } },
85f10a01 6808 /* c8 */
d5d7db8e
L		 6809 { "(bad)", { XX } },
6810 { "(bad)", { XX } },
6811 { "(bad)", { XX } },
6812 { "(bad)", { XX } },
6813 { "(bad)", { XX } },
6814 { "(bad)", { XX } },
6815 { "(bad)", { XX } },
6816 { "(bad)", { XX } },
85f10a01 6817 /* d0 */
d5d7db8e
L		 6818 { "(bad)", { XX } },
6819 { "(bad)", { XX } },
6820 { "(bad)", { XX } },
6821 { "(bad)", { XX } },
6822 { "(bad)", { XX } },
6823 { "(bad)", { XX } },
6824 { "(bad)", { XX } },
6825 { "(bad)", { XX } },
85f10a01 6826 /* d8 */
d5d7db8e
L		 6827 { "(bad)", { XX } },
6828 { "(bad)", { XX } },
6829 { "(bad)", { XX } },
6830 { "(bad)", { XX } },
6831 { "(bad)", { XX } },
6832 { "(bad)", { XX } },
6833 { "(bad)", { XX } },
6834 { "(bad)", { XX } },
85f10a01 6835 /* e0 */
d5d7db8e
L		 6836 { "(bad)", { XX } },
6837 { "(bad)", { XX } },
6838 { "(bad)", { XX } },
6839 { "(bad)", { XX } },
6840 { "(bad)", { XX } },
6841 { "(bad)", { XX } },
6842 { "(bad)", { XX } },
6843 { "(bad)", { XX } },
85f10a01 6844 /* e8 */
d5d7db8e
L		 6845 { "(bad)", { XX } },
6846 { "(bad)", { XX } },
6847 { "(bad)", { XX } },
6848 { "(bad)", { XX } },
6849 { "(bad)", { XX } },
6850 { "(bad)", { XX } },
6851 { "(bad)", { XX } },
6852 { "(bad)", { XX } },
85f10a01 6853 /* f0 */
c0f3af97
L		 6854 { "(bad)", { XX } },
6855 { "(bad)", { XX } },
d5d7db8e
L		 6856 { "(bad)", { XX } },
6857 { "(bad)", { XX } },
6858 { "(bad)", { XX } },
6859 { "(bad)", { XX } },
6860 { "(bad)", { XX } },
6861 { "(bad)", { XX } },
85f10a01 6862 /* f8 */
d5d7db8e
L		 6863 { "(bad)", { XX } },
6864 { "(bad)", { XX } },
6865 { "(bad)", { XX } },
6866 { "(bad)", { XX } },
6867 { "(bad)", { XX } },
6868 { "(bad)", { XX } },
6869 { "(bad)", { XX } },
6870 { "(bad)", { XX } },
85f10a01 6871 },
c0f3af97
L		 6872};
6873
6874static const struct dis386 vex_table[][256] = {
6875 /* VEX_0F */
85f10a01
MM		 6876 {
6877 /* 00 */
d5d7db8e
L		 6878 { "(bad)", { XX } },
6879 { "(bad)", { XX } },
6880 { "(bad)", { XX } },
6881 { "(bad)", { XX } },
6882 { "(bad)", { XX } },
6883 { "(bad)", { XX } },
6884 { "(bad)", { XX } },
6885 { "(bad)", { XX } },
85f10a01 6886 /* 08 */
d5d7db8e
L		 6887 { "(bad)", { XX } },
6888 { "(bad)", { XX } },
6889 { "(bad)", { XX } },
6890 { "(bad)", { XX } },
d5d7db8e
L		 6891 { "(bad)", { XX } },
6892 { "(bad)", { XX } },
6893 { "(bad)", { XX } },
6894 { "(bad)", { XX } },
c0f3af97
L		 6895 /* 10 */
6896 { PREFIX_TABLE (PREFIX_VEX_10) },
6897 { PREFIX_TABLE (PREFIX_VEX_11) },
6898 { PREFIX_TABLE (PREFIX_VEX_12) },
6899 { MOD_TABLE (MOD_VEX_13) },
6900 { "vunpcklpX", { XM, Vex, EXx } },
6901 { "vunpckhpX", { XM, Vex, EXx } },
6902 { PREFIX_TABLE (PREFIX_VEX_16) },
6903 { MOD_TABLE (MOD_VEX_17) },
6904 /* 18 */
d5d7db8e
L		 6905 { "(bad)", { XX } },
6906 { "(bad)", { XX } },
6907 { "(bad)", { XX } },
d5d7db8e
L		 6908 { "(bad)", { XX } },
6909 { "(bad)", { XX } },
6910 { "(bad)", { XX } },
6911 { "(bad)", { XX } },
6912 { "(bad)", { XX } },
c0f3af97 6913 /* 20 */
d5d7db8e
L		 6914 { "(bad)", { XX } },
6915 { "(bad)", { XX } },
6916 { "(bad)", { XX } },
6917 { "(bad)", { XX } },
6918 { "(bad)", { XX } },
6919 { "(bad)", { XX } },
6920 { "(bad)", { XX } },
6921 { "(bad)", { XX } },
c0f3af97
L		 6922 /* 28 */
6923 { "vmovapX", { XM, EXx } },
6924 { "vmovapX", { EXx, XM } },
6925 { PREFIX_TABLE (PREFIX_VEX_2A) },
6926 { MOD_TABLE (MOD_VEX_2B) },
6927 { PREFIX_TABLE (PREFIX_VEX_2C) },
6928 { PREFIX_TABLE (PREFIX_VEX_2D) },
6929 { PREFIX_TABLE (PREFIX_VEX_2E) },
6930 { PREFIX_TABLE (PREFIX_VEX_2F) },
85f10a01 6931 /* 30 */
d5d7db8e
L		 6932 { "(bad)", { XX } },
6933 { "(bad)", { XX } },
6934 { "(bad)", { XX } },
6935 { "(bad)", { XX } },
6936 { "(bad)", { XX } },
6937 { "(bad)", { XX } },
6938 { "(bad)", { XX } },
6939 { "(bad)", { XX } },
4e7d34a6 6940 /* 38 */
d5d7db8e
L		 6941 { "(bad)", { XX } },
6942 { "(bad)", { XX } },
6943 { "(bad)", { XX } },
6944 { "(bad)", { XX } },
6945 { "(bad)", { XX } },
6946 { "(bad)", { XX } },
6947 { "(bad)", { XX } },
6948 { "(bad)", { XX } },
6949 /* 40 */
c0f3af97
L		 6950 { "(bad)", { XX } },
6951 { "(bad)", { XX } },
6952 { "(bad)", { XX } },
d5d7db8e
L		 6953 { "(bad)", { XX } },
6954 { "(bad)", { XX } },
6955 { "(bad)", { XX } },
6956 { "(bad)", { XX } },
6957 { "(bad)", { XX } },
85f10a01 6958 /* 48 */
85f10a01
MM		 6959 { "(bad)", { XX } },
6960 { "(bad)", { XX } },
6961 { "(bad)", { XX } },
6962 { "(bad)", { XX } },
6963 { "(bad)", { XX } },
6964 { "(bad)", { XX } },
6965 { "(bad)", { XX } },
6966 { "(bad)", { XX } },
d5d7db8e 6967 /* 50 */
c0f3af97
L		 6968 { MOD_TABLE (MOD_VEX_51) },
6969 { PREFIX_TABLE (PREFIX_VEX_51) },
6970 { PREFIX_TABLE (PREFIX_VEX_52) },
6971 { PREFIX_TABLE (PREFIX_VEX_53) },
6972 { "vandpX", { XM, Vex, EXx } },
6973 { "vandnpX", { XM, Vex, EXx } },
6974 { "vorpX", { XM, Vex, EXx } },
6975 { "vxorpX", { XM, Vex, EXx } },
6976 /* 58 */
6977 { PREFIX_TABLE (PREFIX_VEX_58) },
6978 { PREFIX_TABLE (PREFIX_VEX_59) },
6979 { PREFIX_TABLE (PREFIX_VEX_5A) },
6980 { PREFIX_TABLE (PREFIX_VEX_5B) },
6981 { PREFIX_TABLE (PREFIX_VEX_5C) },
6982 { PREFIX_TABLE (PREFIX_VEX_5D) },
6983 { PREFIX_TABLE (PREFIX_VEX_5E) },
6984 { PREFIX_TABLE (PREFIX_VEX_5F) },
6985 /* 60 */
6986 { PREFIX_TABLE (PREFIX_VEX_60) },
6987 { PREFIX_TABLE (PREFIX_VEX_61) },
6988 { PREFIX_TABLE (PREFIX_VEX_62) },
6989 { PREFIX_TABLE (PREFIX_VEX_63) },
6990 { PREFIX_TABLE (PREFIX_VEX_64) },
6991 { PREFIX_TABLE (PREFIX_VEX_65) },
6992 { PREFIX_TABLE (PREFIX_VEX_66) },
6993 { PREFIX_TABLE (PREFIX_VEX_67) },
6994 /* 68 */
6995 { PREFIX_TABLE (PREFIX_VEX_68) },
6996 { PREFIX_TABLE (PREFIX_VEX_69) },
6997 { PREFIX_TABLE (PREFIX_VEX_6A) },
6998 { PREFIX_TABLE (PREFIX_VEX_6B) },
6999 { PREFIX_TABLE (PREFIX_VEX_6C) },
7000 { PREFIX_TABLE (PREFIX_VEX_6D) },
7001 { PREFIX_TABLE (PREFIX_VEX_6E) },
7002 { PREFIX_TABLE (PREFIX_VEX_6F) },
7003 /* 70 */
7004 { PREFIX_TABLE (PREFIX_VEX_70) },
7005 { REG_TABLE (REG_VEX_71) },
7006 { REG_TABLE (REG_VEX_72) },
7007 { REG_TABLE (REG_VEX_73) },
7008 { PREFIX_TABLE (PREFIX_VEX_74) },
7009 { PREFIX_TABLE (PREFIX_VEX_75) },
7010 { PREFIX_TABLE (PREFIX_VEX_76) },
7011 { PREFIX_TABLE (PREFIX_VEX_77) },
7012 /* 78 */
85f10a01
MM		 7013 { "(bad)", { XX } },
7014 { "(bad)", { XX } },
7015 { "(bad)", { XX } },
7016 { "(bad)", { XX } },
c0f3af97
L		 7017 { PREFIX_TABLE (PREFIX_VEX_7C) },
7018 { PREFIX_TABLE (PREFIX_VEX_7D) },
7019 { PREFIX_TABLE (PREFIX_VEX_7E) },
7020 { PREFIX_TABLE (PREFIX_VEX_7F) },
7021 /* 80 */
85f10a01
MM		 7022 { "(bad)", { XX } },
7023 { "(bad)", { XX } },
7024 { "(bad)", { XX } },
7025 { "(bad)", { XX } },
85f10a01
MM		 7026 { "(bad)", { XX } },
7027 { "(bad)", { XX } },
7028 { "(bad)", { XX } },
7029 { "(bad)", { XX } },
c0f3af97 7030 /* 88 */
85f10a01
MM		 7031 { "(bad)", { XX } },
7032 { "(bad)", { XX } },
7033 { "(bad)", { XX } },
7034 { "(bad)", { XX } },
7035 { "(bad)", { XX } },
7036 { "(bad)", { XX } },
7037 { "(bad)", { XX } },
7038 { "(bad)", { XX } },
c0f3af97 7039 /* 90 */
85f10a01
MM		 7040 { "(bad)", { XX } },
7041 { "(bad)", { XX } },
7042 { "(bad)", { XX } },
7043 { "(bad)", { XX } },
7044 { "(bad)", { XX } },
7045 { "(bad)", { XX } },
7046 { "(bad)", { XX } },
85f10a01 7047 { "(bad)", { XX } },
c0f3af97 7048 /* 98 */
85f10a01
MM		 7049 { "(bad)", { XX } },
7050 { "(bad)", { XX } },
7051 { "(bad)", { XX } },
d5d7db8e
L		 7052 { "(bad)", { XX } },
7053 { "(bad)", { XX } },
7054 { "(bad)", { XX } },
7055 { "(bad)", { XX } },
7056 { "(bad)", { XX } },
c0f3af97 7057 /* a0 */
d5d7db8e
L		 7058 { "(bad)", { XX } },
7059 { "(bad)", { XX } },
7060 { "(bad)", { XX } },
7061 { "(bad)", { XX } },
7062 { "(bad)", { XX } },
7063 { "(bad)", { XX } },
7064 { "(bad)", { XX } },
7065 { "(bad)", { XX } },
c0f3af97 7066 /* a8 */
d5d7db8e
L		 7067 { "(bad)", { XX } },
7068 { "(bad)", { XX } },
7069 { "(bad)", { XX } },
7070 { "(bad)", { XX } },
7071 { "(bad)", { XX } },
7072 { "(bad)", { XX } },
c0f3af97 7073 { REG_TABLE (REG_VEX_AE) },
d5d7db8e 7074 { "(bad)", { XX } },
c0f3af97 7075 /* b0 */
d5d7db8e 7076 { "(bad)", { XX } },
d5d7db8e
L		 7077 { "(bad)", { XX } },
7078 { "(bad)", { XX } },
7079 { "(bad)", { XX } },
7080 { "(bad)", { XX } },
7081 { "(bad)", { XX } },
7082 { "(bad)", { XX } },
7083 { "(bad)", { XX } },
c0f3af97 7084 /* b8 */
d5d7db8e 7085 { "(bad)", { XX } },
d5d7db8e
L		 7086 { "(bad)", { XX } },
7087 { "(bad)", { XX } },
7088 { "(bad)", { XX } },
7089 { "(bad)", { XX } },
7090 { "(bad)", { XX } },
7091 { "(bad)", { XX } },
7092 { "(bad)", { XX } },
c0f3af97 7093 /* c0 */
d5d7db8e 7094 { "(bad)", { XX } },
d5d7db8e 7095 { "(bad)", { XX } },
c0f3af97 7096 { PREFIX_TABLE (PREFIX_VEX_C2) },
d5d7db8e 7097 { "(bad)", { XX } },
c0f3af97
L		 7098 { PREFIX_TABLE (PREFIX_VEX_C4) },
7099 { PREFIX_TABLE (PREFIX_VEX_C5) },
7100 { "vshufpX", { XM, Vex, EXx, Ib } },
d5d7db8e 7101 { "(bad)", { XX } },
c0f3af97 7102 /* c8 */
d5d7db8e
L		 7103 { "(bad)", { XX } },
7104 { "(bad)", { XX } },
7105 { "(bad)", { XX } },
7106 { "(bad)", { XX } },
7107 { "(bad)", { XX } },
d5d7db8e
L		 7108 { "(bad)", { XX } },
7109 { "(bad)", { XX } },
7110 { "(bad)", { XX } },
c0f3af97
L		 7111 /* d0 */
7112 { PREFIX_TABLE (PREFIX_VEX_D0) },
7113 { PREFIX_TABLE (PREFIX_VEX_D1) },
7114 { PREFIX_TABLE (PREFIX_VEX_D2) },
7115 { PREFIX_TABLE (PREFIX_VEX_D3) },
7116 { PREFIX_TABLE (PREFIX_VEX_D4) },
7117 { PREFIX_TABLE (PREFIX_VEX_D5) },
7118 { PREFIX_TABLE (PREFIX_VEX_D6) },
7119 { PREFIX_TABLE (PREFIX_VEX_D7) },
7120 /* d8 */
7121 { PREFIX_TABLE (PREFIX_VEX_D8) },
7122 { PREFIX_TABLE (PREFIX_VEX_D9) },
7123 { PREFIX_TABLE (PREFIX_VEX_DA) },
7124 { PREFIX_TABLE (PREFIX_VEX_DB) },
7125 { PREFIX_TABLE (PREFIX_VEX_DC) },
7126 { PREFIX_TABLE (PREFIX_VEX_DD) },
7127 { PREFIX_TABLE (PREFIX_VEX_DE) },
7128 { PREFIX_TABLE (PREFIX_VEX_DF) },
7129 /* e0 */
7130 { PREFIX_TABLE (PREFIX_VEX_E0) },
7131 { PREFIX_TABLE (PREFIX_VEX_E1) },
7132 { PREFIX_TABLE (PREFIX_VEX_E2) },
7133 { PREFIX_TABLE (PREFIX_VEX_E3) },
7134 { PREFIX_TABLE (PREFIX_VEX_E4) },
7135 { PREFIX_TABLE (PREFIX_VEX_E5) },
7136 { PREFIX_TABLE (PREFIX_VEX_E6) },
7137 { PREFIX_TABLE (PREFIX_VEX_E7) },
7138 /* e8 */
7139 { PREFIX_TABLE (PREFIX_VEX_E8) },
7140 { PREFIX_TABLE (PREFIX_VEX_E9) },
7141 { PREFIX_TABLE (PREFIX_VEX_EA) },
7142 { PREFIX_TABLE (PREFIX_VEX_EB) },
7143 { PREFIX_TABLE (PREFIX_VEX_EC) },
7144 { PREFIX_TABLE (PREFIX_VEX_ED) },
7145 { PREFIX_TABLE (PREFIX_VEX_EE) },
7146 { PREFIX_TABLE (PREFIX_VEX_EF) },
7147 /* f0 */
7148 { PREFIX_TABLE (PREFIX_VEX_F0) },
7149 { PREFIX_TABLE (PREFIX_VEX_F1) },
7150 { PREFIX_TABLE (PREFIX_VEX_F2) },
7151 { PREFIX_TABLE (PREFIX_VEX_F3) },
7152 { PREFIX_TABLE (PREFIX_VEX_F4) },
7153 { PREFIX_TABLE (PREFIX_VEX_F5) },
7154 { PREFIX_TABLE (PREFIX_VEX_F6) },
7155 { PREFIX_TABLE (PREFIX_VEX_F7) },
7156 /* f8 */
7157 { PREFIX_TABLE (PREFIX_VEX_F8) },
7158 { PREFIX_TABLE (PREFIX_VEX_F9) },
7159 { PREFIX_TABLE (PREFIX_VEX_FA) },
7160 { PREFIX_TABLE (PREFIX_VEX_FB) },
7161 { PREFIX_TABLE (PREFIX_VEX_FC) },
7162 { PREFIX_TABLE (PREFIX_VEX_FD) },
7163 { PREFIX_TABLE (PREFIX_VEX_FE) },
d5d7db8e 7164 { "(bad)", { XX } },
c0f3af97
L		 7165 },
7166 /* VEX_0F38 */
7167 {
7168 /* 00 */
7169 { PREFIX_TABLE (PREFIX_VEX_3800) },
7170 { PREFIX_TABLE (PREFIX_VEX_3801) },
7171 { PREFIX_TABLE (PREFIX_VEX_3802) },
7172 { PREFIX_TABLE (PREFIX_VEX_3803) },
7173 { PREFIX_TABLE (PREFIX_VEX_3804) },
7174 { PREFIX_TABLE (PREFIX_VEX_3805) },
7175 { PREFIX_TABLE (PREFIX_VEX_3806) },
7176 { PREFIX_TABLE (PREFIX_VEX_3807) },
7177 /* 08 */
7178 { PREFIX_TABLE (PREFIX_VEX_3808) },
7179 { PREFIX_TABLE (PREFIX_VEX_3809) },
7180 { PREFIX_TABLE (PREFIX_VEX_380A) },
7181 { PREFIX_TABLE (PREFIX_VEX_380B) },
7182 { PREFIX_TABLE (PREFIX_VEX_380C) },
7183 { PREFIX_TABLE (PREFIX_VEX_380D) },
7184 { PREFIX_TABLE (PREFIX_VEX_380E) },
7185 { PREFIX_TABLE (PREFIX_VEX_380F) },
7186 /* 10 */
d5d7db8e
L		 7187 { "(bad)", { XX } },
7188 { "(bad)", { XX } },
7189 { "(bad)", { XX } },
7190 { "(bad)", { XX } },
d5d7db8e
L		 7191 { "(bad)", { XX } },
7192 { "(bad)", { XX } },
7193 { "(bad)", { XX } },
c0f3af97
L		 7194 { PREFIX_TABLE (PREFIX_VEX_3817) },
7195 /* 18 */
7196 { PREFIX_TABLE (PREFIX_VEX_3818) },
7197 { PREFIX_TABLE (PREFIX_VEX_3819) },
7198 { PREFIX_TABLE (PREFIX_VEX_381A) },
d5d7db8e 7199 { "(bad)", { XX } },
c0f3af97
L		 7200 { PREFIX_TABLE (PREFIX_VEX_381C) },
7201 { PREFIX_TABLE (PREFIX_VEX_381D) },
7202 { PREFIX_TABLE (PREFIX_VEX_381E) },
d5d7db8e 7203 { "(bad)", { XX } },
c0f3af97
L		 7204 /* 20 */
7205 { PREFIX_TABLE (PREFIX_VEX_3820) },
7206 { PREFIX_TABLE (PREFIX_VEX_3821) },
7207 { PREFIX_TABLE (PREFIX_VEX_3822) },
7208 { PREFIX_TABLE (PREFIX_VEX_3823) },
7209 { PREFIX_TABLE (PREFIX_VEX_3824) },
7210 { PREFIX_TABLE (PREFIX_VEX_3825) },
d5d7db8e
L		 7211 { "(bad)", { XX } },
7212 { "(bad)", { XX } },
c0f3af97
L		 7213 /* 28 */
7214 { PREFIX_TABLE (PREFIX_VEX_3828) },
7215 { PREFIX_TABLE (PREFIX_VEX_3829) },
7216 { PREFIX_TABLE (PREFIX_VEX_382A) },
7217 { PREFIX_TABLE (PREFIX_VEX_382B) },
7218 { PREFIX_TABLE (PREFIX_VEX_382C) },
7219 { PREFIX_TABLE (PREFIX_VEX_382D) },
7220 { PREFIX_TABLE (PREFIX_VEX_382E) },
7221 { PREFIX_TABLE (PREFIX_VEX_382F) },
7222 /* 30 */
7223 { PREFIX_TABLE (PREFIX_VEX_3830) },
7224 { PREFIX_TABLE (PREFIX_VEX_3831) },
7225 { PREFIX_TABLE (PREFIX_VEX_3832) },
7226 { PREFIX_TABLE (PREFIX_VEX_3833) },
7227 { PREFIX_TABLE (PREFIX_VEX_3834) },
7228 { PREFIX_TABLE (PREFIX_VEX_3835) },
7229 { "(bad)", { XX } },
7230 { PREFIX_TABLE (PREFIX_VEX_3837) },
7231 /* 38 */
7232 { PREFIX_TABLE (PREFIX_VEX_3838) },
7233 { PREFIX_TABLE (PREFIX_VEX_3839) },
7234 { PREFIX_TABLE (PREFIX_VEX_383A) },
7235 { PREFIX_TABLE (PREFIX_VEX_383B) },
7236 { PREFIX_TABLE (PREFIX_VEX_383C) },
7237 { PREFIX_TABLE (PREFIX_VEX_383D) },
7238 { PREFIX_TABLE (PREFIX_VEX_383E) },
7239 { PREFIX_TABLE (PREFIX_VEX_383F) },
7240 /* 40 */
7241 { PREFIX_TABLE (PREFIX_VEX_3840) },
7242 { PREFIX_TABLE (PREFIX_VEX_3841) },
d5d7db8e 7243 { "(bad)", { XX } },
d5d7db8e
L		 7244 { "(bad)", { XX } },
7245 { "(bad)", { XX } },
7246 { "(bad)", { XX } },
7247 { "(bad)", { XX } },
7248 { "(bad)", { XX } },
c0f3af97 7249 /* 48 */
d5d7db8e
L		 7250 { "(bad)", { XX } },
7251 { "(bad)", { XX } },
7252 { "(bad)", { XX } },
d5d7db8e
L		 7253 { "(bad)", { XX } },
7254 { "(bad)", { XX } },
7255 { "(bad)", { XX } },
7256 { "(bad)", { XX } },
7257 { "(bad)", { XX } },
c0f3af97 7258 /* 50 */
d5d7db8e
L		 7259 { "(bad)", { XX } },
7260 { "(bad)", { XX } },
7261 { "(bad)", { XX } },
d5d7db8e
L		 7262 { "(bad)", { XX } },
7263 { "(bad)", { XX } },
7264 { "(bad)", { XX } },
7265 { "(bad)", { XX } },
7266 { "(bad)", { XX } },
c0f3af97 7267 /* 58 */
d5d7db8e
L		 7268 { "(bad)", { XX } },
7269 { "(bad)", { XX } },
7270 { "(bad)", { XX } },
d5d7db8e
L		 7271 { "(bad)", { XX } },
7272 { "(bad)", { XX } },
7273 { "(bad)", { XX } },
7274 { "(bad)", { XX } },
7275 { "(bad)", { XX } },
c0f3af97 7276 /* 60 */
d5d7db8e
L		 7277 { "(bad)", { XX } },
7278 { "(bad)", { XX } },
7279 { "(bad)", { XX } },
d5d7db8e
L		 7280 { "(bad)", { XX } },
7281 { "(bad)", { XX } },
7282 { "(bad)", { XX } },
7283 { "(bad)", { XX } },
7284 { "(bad)", { XX } },
c0f3af97 7285 /* 68 */
d5d7db8e
L		 7286 { "(bad)", { XX } },
7287 { "(bad)", { XX } },
7288 { "(bad)", { XX } },
d5d7db8e
L		 7289 { "(bad)", { XX } },
7290 { "(bad)", { XX } },
7291 { "(bad)", { XX } },
7292 { "(bad)", { XX } },
7293 { "(bad)", { XX } },
c0f3af97 7294 /* 70 */
d5d7db8e
L		 7295 { "(bad)", { XX } },
7296 { "(bad)", { XX } },
7297 { "(bad)", { XX } },
d5d7db8e
L		 7298 { "(bad)", { XX } },
7299 { "(bad)", { XX } },
7300 { "(bad)", { XX } },
7301 { "(bad)", { XX } },
7302 { "(bad)", { XX } },
c0f3af97 7303 /* 78 */
d5d7db8e
L		 7304 { "(bad)", { XX } },
7305 { "(bad)", { XX } },
7306 { "(bad)", { XX } },
d5d7db8e
L		 7307 { "(bad)", { XX } },
7308 { "(bad)", { XX } },
7309 { "(bad)", { XX } },
7310 { "(bad)", { XX } },
7311 { "(bad)", { XX } },
c0f3af97 7312 /* 80 */
d5d7db8e
L		 7313 { "(bad)", { XX } },
7314 { "(bad)", { XX } },
7315 { "(bad)", { XX } },
d5d7db8e
L		 7316 { "(bad)", { XX } },
7317 { "(bad)", { XX } },
7318 { "(bad)", { XX } },
7319 { "(bad)", { XX } },
7320 { "(bad)", { XX } },
c0f3af97 7321 /* 88 */
d5d7db8e
L		 7322 { "(bad)", { XX } },
7323 { "(bad)", { XX } },
7324 { "(bad)", { XX } },
d5d7db8e
L		 7325 { "(bad)", { XX } },
7326 { "(bad)", { XX } },
7327 { "(bad)", { XX } },
7328 { "(bad)", { XX } },
7329 { "(bad)", { XX } },
c0f3af97 7330 /* 90 */
d5d7db8e
L		 7331 { "(bad)", { XX } },
7332 { "(bad)", { XX } },
7333 { "(bad)", { XX } },
d5d7db8e
L		 7334 { "(bad)", { XX } },
7335 { "(bad)", { XX } },
7336 { "(bad)", { XX } },
7337 { "(bad)", { XX } },
7338 { "(bad)", { XX } },
c0f3af97 7339 /* 98 */
d5d7db8e
L		 7340 { "(bad)", { XX } },
7341 { "(bad)", { XX } },
7342 { "(bad)", { XX } },
d5d7db8e
L		 7343 { "(bad)", { XX } },
7344 { "(bad)", { XX } },
7345 { "(bad)", { XX } },
7346 { "(bad)", { XX } },
7347 { "(bad)", { XX } },
c0f3af97 7348 /* a0 */
d5d7db8e
L		 7349 { "(bad)", { XX } },
7350 { "(bad)", { XX } },
7351 { "(bad)", { XX } },
d5d7db8e
L		 7352 { "(bad)", { XX } },
7353 { "(bad)", { XX } },
7354 { "(bad)", { XX } },
7355 { "(bad)", { XX } },
d5d7db8e 7356 { "(bad)", { XX } },
c0f3af97 7357 /* a8 */
d5d7db8e
L		 7358 { "(bad)", { XX } },
7359 { "(bad)", { XX } },
7360 { "(bad)", { XX } },
7361 { "(bad)", { XX } },
7362 { "(bad)", { XX } },
7363 { "(bad)", { XX } },
7364 { "(bad)", { XX } },
d5d7db8e 7365 { "(bad)", { XX } },
c0f3af97 7366 /* b0 */
d5d7db8e
L		 7367 { "(bad)", { XX } },
7368 { "(bad)", { XX } },
7369 { "(bad)", { XX } },
7370 { "(bad)", { XX } },
7371 { "(bad)", { XX } },
7372 { "(bad)", { XX } },
d5d7db8e
L		 7373 { "(bad)", { XX } },
7374 { "(bad)", { XX } },
c0f3af97 7375 /* b8 */
d5d7db8e
L		 7376 { "(bad)", { XX } },
7377 { "(bad)", { XX } },
7378 { "(bad)", { XX } },
7379 { "(bad)", { XX } },
7380 { "(bad)", { XX } },
7381 { "(bad)", { XX } },
d5d7db8e
L		 7382 { "(bad)", { XX } },
7383 { "(bad)", { XX } },
c0f3af97 7384 /* c0 */
d5d7db8e
L		 7385 { "(bad)", { XX } },
7386 { "(bad)", { XX } },
7387 { "(bad)", { XX } },
7388 { "(bad)", { XX } },
d5d7db8e
L		 7389 { "(bad)", { XX } },
7390 { "(bad)", { XX } },
7391 { "(bad)", { XX } },
7392 { "(bad)", { XX } },
c0f3af97 7393 /* c8 */
d5d7db8e
L		 7394 { "(bad)", { XX } },
7395 { "(bad)", { XX } },
7396 { "(bad)", { XX } },
7397 { "(bad)", { XX } },
d5d7db8e 7398 { "(bad)", { XX } },
d5d7db8e
L		 7399 { "(bad)", { XX } },
7400 { "(bad)", { XX } },
d5d7db8e 7401 { "(bad)", { XX } },
c0f3af97 7402 /* d0 */
d5d7db8e
L		 7403 { "(bad)", { XX } },
7404 { "(bad)", { XX } },
d5d7db8e
L		 7405 { "(bad)", { XX } },
7406 { "(bad)", { XX } },
7407 { "(bad)", { XX } },
7408 { "(bad)", { XX } },
d5d7db8e 7409 { "(bad)", { XX } },
d5d7db8e 7410 { "(bad)", { XX } },
c0f3af97 7411 /* d8 */
d5d7db8e 7412 { "(bad)", { XX } },
d5d7db8e
L		 7413 { "(bad)", { XX } },
7414 { "(bad)", { XX } },
7415 { "(bad)", { XX } },
d5d7db8e
L		 7416 { "(bad)", { XX } },
7417 { "(bad)", { XX } },
7418 { "(bad)", { XX } },
7419 { "(bad)", { XX } },
c0f3af97 7420 /* e0 */
d5d7db8e 7421 { "(bad)", { XX } },
d5d7db8e
L		 7422 { "(bad)", { XX } },
7423 { "(bad)", { XX } },
7424 { "(bad)", { XX } },
7425 { "(bad)", { XX } },
d5d7db8e
L		 7426 { "(bad)", { XX } },
7427 { "(bad)", { XX } },
7428 { "(bad)", { XX } },
c0f3af97 7429 /* e8 */
d5d7db8e
L		 7430 { "(bad)", { XX } },
7431 { "(bad)", { XX } },
7432 { "(bad)", { XX } },
7433 { "(bad)", { XX } },
7434 { "(bad)", { XX } },
d5d7db8e
L		 7435 { "(bad)", { XX } },
7436 { "(bad)", { XX } },
7437 { "(bad)", { XX } },
c0f3af97 7438 /* f0 */
d5d7db8e
L		 7439 { "(bad)", { XX } },
7440 { "(bad)", { XX } },
7441 { "(bad)", { XX } },
7442 { "(bad)", { XX } },
7443 { "(bad)", { XX } },
d5d7db8e
L		 7444 { "(bad)", { XX } },
7445 { "(bad)", { XX } },
7446 { "(bad)", { XX } },
c0f3af97 7447 /* f8 */
d5d7db8e
L		 7448 { "(bad)", { XX } },
7449 { "(bad)", { XX } },
7450 { "(bad)", { XX } },
7451 { "(bad)", { XX } },
7452 { "(bad)", { XX } },
d5d7db8e
L		 7453 { "(bad)", { XX } },
7454 { "(bad)", { XX } },
7455 { "(bad)", { XX } },
c0f3af97
L		 7456 },
7457 /* VEX_0F3A */
7458 {
7459 /* 00 */
d5d7db8e
L		 7460 { "(bad)", { XX } },
7461 { "(bad)", { XX } },
7462 { "(bad)", { XX } },
7463 { "(bad)", { XX } },
c0f3af97
L		 7464 { PREFIX_TABLE (PREFIX_VEX_3A04) },
7465 { PREFIX_TABLE (PREFIX_VEX_3A05) },
7466 { PREFIX_TABLE (PREFIX_VEX_3A06) },
d5d7db8e 7467 { "(bad)", { XX } },
c0f3af97
L		 7468 /* 08 */
7469 { PREFIX_TABLE (PREFIX_VEX_3A08) },
7470 { PREFIX_TABLE (PREFIX_VEX_3A09) },
7471 { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7472 { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7473 { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7474 { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7475 { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7476 { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7477 /* 10 */
d5d7db8e
L		 7478 { "(bad)", { XX } },
7479 { "(bad)", { XX } },
7480 { "(bad)", { XX } },
7481 { "(bad)", { XX } },
c0f3af97
L		 7482 { PREFIX_TABLE (PREFIX_VEX_3A14) },
7483 { PREFIX_TABLE (PREFIX_VEX_3A15) },
7484 { PREFIX_TABLE (PREFIX_VEX_3A16) },
7485 { PREFIX_TABLE (PREFIX_VEX_3A17) },
7486 /* 18 */
7487 { PREFIX_TABLE (PREFIX_VEX_3A18) },
7488 { PREFIX_TABLE (PREFIX_VEX_3A19) },
d5d7db8e
L		 7489 { "(bad)", { XX } },
7490 { "(bad)", { XX } },
7491 { "(bad)", { XX } },
7492 { "(bad)", { XX } },
d5d7db8e
L		 7493 { "(bad)", { XX } },
7494 { "(bad)", { XX } },
c0f3af97
L		 7495 /* 20 */
7496 { PREFIX_TABLE (PREFIX_VEX_3A20) },
7497 { PREFIX_TABLE (PREFIX_VEX_3A21) },
7498 { PREFIX_TABLE (PREFIX_VEX_3A22) },
d5d7db8e
L		 7499 { "(bad)", { XX } },
7500 { "(bad)", { XX } },
7501 { "(bad)", { XX } },
7502 { "(bad)", { XX } },
7503 { "(bad)", { XX } },
c0f3af97 7504 /* 28 */
d5d7db8e 7505 { "(bad)", { XX } },
d5d7db8e
L		 7506 { "(bad)", { XX } },
7507 { "(bad)", { XX } },
7508 { "(bad)", { XX } },
7509 { "(bad)", { XX } },
7510 { "(bad)", { XX } },
7511 { "(bad)", { XX } },
7512 { "(bad)", { XX } },
c0f3af97 7513 /* 30 */
d5d7db8e 7514 { "(bad)", { XX } },
d5d7db8e
L		 7515 { "(bad)", { XX } },
7516 { "(bad)", { XX } },
7517 { "(bad)", { XX } },
7518 { "(bad)", { XX } },
7519 { "(bad)", { XX } },
7520 { "(bad)", { XX } },
7521 { "(bad)", { XX } },
c0f3af97 7522 /* 38 */
d5d7db8e 7523 { "(bad)", { XX } },
d5d7db8e
L		 7524 { "(bad)", { XX } },
7525 { "(bad)", { XX } },
7526 { "(bad)", { XX } },
7527 { "(bad)", { XX } },
7528 { "(bad)", { XX } },
7529 { "(bad)", { XX } },
7530 { "(bad)", { XX } },
c0f3af97
L		 7531 /* 40 */
7532 { PREFIX_TABLE (PREFIX_VEX_3A40) },
7533 { PREFIX_TABLE (PREFIX_VEX_3A41) },
7534 { PREFIX_TABLE (PREFIX_VEX_3A42) },
d5d7db8e 7535 { "(bad)", { XX } },
d5d7db8e
L		 7536 { "(bad)", { XX } },
7537 { "(bad)", { XX } },
7538 { "(bad)", { XX } },
7539 { "(bad)", { XX } },
c0f3af97
L		 7540 /* 48 */
7541 { PREFIX_TABLE (PREFIX_VEX_3A48) },
7542 { PREFIX_TABLE (PREFIX_VEX_3A49) },
7543 { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7544 { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7545 { PREFIX_TABLE (PREFIX_VEX_3A4C) },
d5d7db8e
L		 7546 { "(bad)", { XX } },
7547 { "(bad)", { XX } },
7548 { "(bad)", { XX } },
c0f3af97 7549 /* 50 */
d5d7db8e 7550 { "(bad)", { XX } },
d5d7db8e
L		 7551 { "(bad)", { XX } },
7552 { "(bad)", { XX } },
7553 { "(bad)", { XX } },
7554 { "(bad)", { XX } },
7555 { "(bad)", { XX } },
7556 { "(bad)", { XX } },
7557 { "(bad)", { XX } },
c0f3af97 7558 /* 58 */
d5d7db8e 7559 { "(bad)", { XX } },
d5d7db8e
L		 7560 { "(bad)", { XX } },
7561 { "(bad)", { XX } },
7562 { "(bad)", { XX } },
c0f3af97
L		 7563 { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7564 { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7565 { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7566 { PREFIX_TABLE (PREFIX_VEX_3A5F) },
7567 /* 60 */
7568 { PREFIX_TABLE (PREFIX_VEX_3A60) },
7569 { PREFIX_TABLE (PREFIX_VEX_3A61) },
7570 { PREFIX_TABLE (PREFIX_VEX_3A62) },
7571 { PREFIX_TABLE (PREFIX_VEX_3A63) },
d5d7db8e
L		 7572 { "(bad)", { XX } },
7573 { "(bad)", { XX } },
7574 { "(bad)", { XX } },
7575 { "(bad)", { XX } },
c0f3af97
L		 7576 /* 68 */
7577 { PREFIX_TABLE (PREFIX_VEX_3A68) },
7578 { PREFIX_TABLE (PREFIX_VEX_3A69) },
7579 { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7580 { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7581 { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7582 { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7583 { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7584 { PREFIX_TABLE (PREFIX_VEX_3A6F) },
7585 /* 70 */
d5d7db8e 7586 { "(bad)", { XX } },
d5d7db8e
L		 7587 { "(bad)", { XX } },
7588 { "(bad)", { XX } },
7589 { "(bad)", { XX } },
7590 { "(bad)", { XX } },
7591 { "(bad)", { XX } },
7592 { "(bad)", { XX } },
7593 { "(bad)", { XX } },
c0f3af97
L		 7594 /* 78 */
7595 { PREFIX_TABLE (PREFIX_VEX_3A78) },
7596 { PREFIX_TABLE (PREFIX_VEX_3A79) },
7597 { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7598 { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7599 { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7600 { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7601 { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7602 { PREFIX_TABLE (PREFIX_VEX_3A7F) },
7603 /* 80 */
d5d7db8e 7604 { "(bad)", { XX } },
d5d7db8e
L		 7605 { "(bad)", { XX } },
7606 { "(bad)", { XX } },
7607 { "(bad)", { XX } },
7608 { "(bad)", { XX } },
7609 { "(bad)", { XX } },
7610 { "(bad)", { XX } },
7611 { "(bad)", { XX } },
c0f3af97 7612 /* 88 */
d5d7db8e 7613 { "(bad)", { XX } },
d5d7db8e
L		 7614 { "(bad)", { XX } },
7615 { "(bad)", { XX } },
7616 { "(bad)", { XX } },
7617 { "(bad)", { XX } },
7618 { "(bad)", { XX } },
7619 { "(bad)", { XX } },
7620 { "(bad)", { XX } },
c0f3af97 7621 /* 90 */
d5d7db8e 7622 { "(bad)", { XX } },
d5d7db8e
L		 7623 { "(bad)", { XX } },
7624 { "(bad)", { XX } },
7625 { "(bad)", { XX } },
7626 { "(bad)", { XX } },
7627 { "(bad)", { XX } },
7628 { "(bad)", { XX } },
7629 { "(bad)", { XX } },
c0f3af97 7630 /* 98 */
d5d7db8e 7631 { "(bad)", { XX } },
d5d7db8e
L		 7632 { "(bad)", { XX } },
7633 { "(bad)", { XX } },
7634 { "(bad)", { XX } },
7635 { "(bad)", { XX } },
7636 { "(bad)", { XX } },
7637 { "(bad)", { XX } },
7638 { "(bad)", { XX } },
c0f3af97 7639 /* a0 */
d5d7db8e 7640 { "(bad)", { XX } },
85f10a01
MM		 7641 { "(bad)", { XX } },
7642 { "(bad)", { XX } },
d5d7db8e
L		 7643 { "(bad)", { XX } },
7644 { "(bad)", { XX } },
7645 { "(bad)", { XX } },
7646 { "(bad)", { XX } },
7647 { "(bad)", { XX } },
c0f3af97 7648 /* a8 */
d5d7db8e 7649 { "(bad)", { XX } },
d5d7db8e
L		 7650 { "(bad)", { XX } },
7651 { "(bad)", { XX } },
7652 { "(bad)", { XX } },
7653 { "(bad)", { XX } },
7654 { "(bad)", { XX } },
7655 { "(bad)", { XX } },
7656 { "(bad)", { XX } },
c0f3af97
L		 7657 /* b0 */
7658 { "(bad)", { XX } },
7659 { "(bad)", { XX } },
7660 { "(bad)", { XX } },
7661 { "(bad)", { XX } },
7662 { "(bad)", { XX } },
7663 { "(bad)", { XX } },
7664 { "(bad)", { XX } },
7665 { "(bad)", { XX } },
7666 /* b8 */
7667 { "(bad)", { XX } },
7668 { "(bad)", { XX } },
7669 { "(bad)", { XX } },
7670 { "(bad)", { XX } },
7671 { "(bad)", { XX } },
7672 { "(bad)", { XX } },
7673 { "(bad)", { XX } },
7674 { "(bad)", { XX } },
7675 /* c0 */
7676 { "(bad)", { XX } },
7677 { "(bad)", { XX } },
7678 { "(bad)", { XX } },
7679 { "(bad)", { XX } },
7680 { "(bad)", { XX } },
7681 { "(bad)", { XX } },
7682 { "(bad)", { XX } },
7683 { "(bad)", { XX } },
7684 /* c8 */
7685 { "(bad)", { XX } },
7686 { "(bad)", { XX } },
d5d7db8e 7687 { "(bad)", { XX } },
d5d7db8e
L		 7688 { "(bad)", { XX } },
7689 { "(bad)", { XX } },
7690 { "(bad)", { XX } },
7691 { "(bad)", { XX } },
7692 { "(bad)", { XX } },
c0f3af97
L		 7693 /* d0 */
7694 { "(bad)", { XX } },
7695 { "(bad)", { XX } },
7696 { "(bad)", { XX } },
d5d7db8e
L		 7697 { "(bad)", { XX } },
7698 { "(bad)", { XX } },
7699 { "(bad)", { XX } },
c0f3af97
L		 7700 { "(bad)", { XX } },
7701 { "(bad)", { XX } },
7702 /* d8 */
7703 { "(bad)", { XX } },
d5d7db8e
L		 7704 { "(bad)", { XX } },
7705 { "(bad)", { XX } },
7706 { "(bad)", { XX } },
7707 { "(bad)", { XX } },
7708 { "(bad)", { XX } },
7709 { "(bad)", { XX } },
7710 { "(bad)", { XX } },
c0f3af97 7711 /* e0 */
d5d7db8e 7712 { "(bad)", { XX } },
d5d7db8e
L		 7713 { "(bad)", { XX } },
7714 { "(bad)", { XX } },
7715 { "(bad)", { XX } },
7716 { "(bad)", { XX } },
7717 { "(bad)", { XX } },
7718 { "(bad)", { XX } },
7719 { "(bad)", { XX } },
c0f3af97 7720 /* e8 */
d5d7db8e 7721 { "(bad)", { XX } },
d5d7db8e
L		 7722 { "(bad)", { XX } },
7723 { "(bad)", { XX } },
7724 { "(bad)", { XX } },
7725 { "(bad)", { XX } },
7726 { "(bad)", { XX } },
7727 { "(bad)", { XX } },
7728 { "(bad)", { XX } },
c0f3af97 7729 /* f0 */
d5d7db8e 7730 { "(bad)", { XX } },
d5d7db8e
L		 7731 { "(bad)", { XX } },
7732 { "(bad)", { XX } },
7733 { "(bad)", { XX } },
7734 { "(bad)", { XX } },
7735 { "(bad)", { XX } },
7736 { "(bad)", { XX } },
7737 { "(bad)", { XX } },
c0f3af97 7738 /* f8 */
d5d7db8e 7739 { "(bad)", { XX } },
d5d7db8e
L		 7740 { "(bad)", { XX } },
7741 { "(bad)", { XX } },
7742 { "(bad)", { XX } },
7743 { "(bad)", { XX } },
7744 { "(bad)", { XX } },
7745 { "(bad)", { XX } },
7746 { "(bad)", { XX } },
c0f3af97
L		 7747 },
7748};
7749
7750static const struct dis386 vex_len_table[][2] = {
7751 /* VEX_LEN_10_P_1 */
7752 {
7753 { "vmovss", { XMVex, Vex128, EXd } },
d5d7db8e 7754 { "(bad)", { XX } },
c0f3af97
L		 7755 },
7756
7757 /* VEX_LEN_10_P_3 */
7758 {
7759 { "vmovsd", { XMVex, Vex128, EXq } },
d5d7db8e 7760 { "(bad)", { XX } },
c0f3af97
L		 7761 },
7762
7763 /* VEX_LEN_11_P_1 */
7764 {
7765 { "vmovss", { EXdVex, Vex128, XM } },
d5d7db8e 7766 { "(bad)", { XX } },
c0f3af97
L		 7767 },
7768
7769 /* VEX_LEN_11_P_3 */
7770 {
7771 { "vmovsd", { EXqVex, Vex128, XM } },
d5d7db8e 7772 { "(bad)", { XX } },
c0f3af97
L		 7773 },
7774
7775 /* VEX_LEN_12_P_0_M_0 */
7776 {
7777 { "vmovlps", { XM, Vex128, EXq } },
d5d7db8e 7778 { "(bad)", { XX } },
c0f3af97
L		 7779 },
7780
7781 /* VEX_LEN_12_P_0_M_1 */
7782 {
7783 { "vmovhlps", { XM, Vex128, EXq } },
d5d7db8e 7784 { "(bad)", { XX } },
c0f3af97
L		 7785 },
7786
7787 /* VEX_LEN_12_P_2 */
7788 {
7789 { "vmovlpd", { XM, Vex128, EXq } },
d5d7db8e 7790 { "(bad)", { XX } },
c0f3af97
L		 7791 },
7792
7793 /* VEX_LEN_13_M_0 */
7794 {
7795 { "vmovlpX", { EXq, XM } },
85f10a01 7796 { "(bad)", { XX } },
c0f3af97
L		 7797 },
7798
7799 /* VEX_LEN_16_P_0_M_0 */
7800 {
7801 { "vmovhps", { XM, Vex128, EXq } },
85f10a01 7802 { "(bad)", { XX } },
c0f3af97
L		 7803 },
7804
7805 /* VEX_LEN_16_P_0_M_1 */
7806 {
7807 { "vmovlhps", { XM, Vex128, EXq } },
85f10a01 7808 { "(bad)", { XX } },
c0f3af97
L		 7809 },
7810
7811 /* VEX_LEN_16_P_2 */
7812 {
7813 { "vmovhpd", { XM, Vex128, EXq } },
85f10a01 7814 { "(bad)", { XX } },
c0f3af97
L		 7815 },
7816
7817 /* VEX_LEN_17_M_0 */
7818 {
7819 { "vmovhpX", { EXq, XM } },
85f10a01 7820 { "(bad)", { XX } },
c0f3af97
L		 7821 },
7822
7823 /* VEX_LEN_2A_P_1 */
7824 {
7825 { "vcvtsi2ss%LQ", { XM, Vex128, Ev } },
d5d7db8e 7826 { "(bad)", { XX } },
c0f3af97
L		 7827 },
7828
7829 /* VEX_LEN_2A_P_3 */
7830 {
7831 { "vcvtsi2sd%LQ", { XM, Vex128, Ev } },
d5d7db8e 7832 { "(bad)", { XX } },
c0f3af97
L		 7833 },
7834
7835 /* VEX_LEN_2B_M_0 */
7836 {
7837 { "vmovntpX", { Mx, XM } },
d5d7db8e 7838 { "(bad)", { XX } },
c0f3af97
L		 7839 },
7840
7841 /* VEX_LEN_2C_P_1 */
7842 {
7843 { "vcvttss2siY", { Gv, EXd } },
d5d7db8e 7844 { "(bad)", { XX } },
c0f3af97
L		 7845 },
7846
7847 /* VEX_LEN_2C_P_3 */
7848 {
7849 { "vcvttsd2siY", { Gv, EXq } },
d5d7db8e 7850 { "(bad)", { XX } },
c0f3af97
L		 7851 },
7852
7853 /* VEX_LEN_2D_P_1 */
7854 {
7855 { "vcvtss2siY", { Gv, EXd } },
85f10a01 7856 { "(bad)", { XX } },
c0f3af97
L		 7857 },
7858
7859 /* VEX_LEN_2D_P_3 */
7860 {
7861 { "vcvtsd2siY", { Gv, EXq } },
d5d7db8e 7862 { "(bad)", { XX } },
c0f3af97
L		 7863 },
7864
7865 /* VEX_LEN_2E_P_0 */
7866 {
7867 { "vucomiss", { XM, EXd } },
d5d7db8e 7868 { "(bad)", { XX } },
c0f3af97
L		 7869 },
7870
7871 /* VEX_LEN_2E_P_2 */
7872 {
7873 { "vucomisd", { XM, EXq } },
d5d7db8e 7874 { "(bad)", { XX } },
c0f3af97
L		 7875 },
7876
7877 /* VEX_LEN_2F_P_0 */
7878 {
7879 { "vcomiss", { XM, EXd } },
d5d7db8e 7880 { "(bad)", { XX } },
c0f3af97
L		 7881 },
7882
7883 /* VEX_LEN_2F_P_2 */
7884 {
7885 { "vcomisd", { XM, EXq } },
d5d7db8e 7886 { "(bad)", { XX } },
c0f3af97
L		 7887 },
7888
7889 /* VEX_LEN_51_P_1 */
7890 {
7891 { "vsqrtss", { XM, Vex128, EXd } },
d5d7db8e 7892 { "(bad)", { XX } },
c0f3af97
L		 7893 },
7894
7895 /* VEX_LEN_51_P_3 */
7896 {
7897 { "vsqrtsd", { XM, Vex128, EXq } },
d5d7db8e 7898 { "(bad)", { XX } },
c0f3af97
L		 7899 },
7900
7901 /* VEX_LEN_52_P_1 */
7902 {
7903 { "vrsqrtss", { XM, Vex128, EXd } },
d5d7db8e 7904 { "(bad)", { XX } },
c0f3af97
L		 7905 },
7906
7907 /* VEX_LEN_53_P_1 */
7908 {
7909 { "vrcpss", { XM, Vex128, EXd } },
d5d7db8e 7910 { "(bad)", { XX } },
c0f3af97
L		 7911 },
7912
7913 /* VEX_LEN_58_P_1 */
7914 {
7915 { "vaddss", { XM, Vex128, EXd } },
d5d7db8e 7916 { "(bad)", { XX } },
c0f3af97
L		 7917 },
7918
7919 /* VEX_LEN_58_P_3 */
7920 {
7921 { "vaddsd", { XM, Vex128, EXq } },
d5d7db8e 7922 { "(bad)", { XX } },
c0f3af97
L		 7923 },
7924
7925 /* VEX_LEN_59_P_1 */
7926 {
7927 { "vmulss", { XM, Vex128, EXd } },
d5d7db8e 7928 { "(bad)", { XX } },
c0f3af97
L		 7929 },
7930
7931 /* VEX_LEN_59_P_3 */
7932 {
7933 { "vmulsd", { XM, Vex128, EXq } },
d5d7db8e 7934 { "(bad)", { XX } },
c0f3af97
L		 7935 },
7936
7937 /* VEX_LEN_5A_P_1 */
7938 {
7939 { "vcvtss2sd", { XM, Vex128, EXd } },
d5d7db8e 7940 { "(bad)", { XX } },
c0f3af97
L		 7941 },
7942
7943 /* VEX_LEN_5A_P_3 */
7944 {
7945 { "vcvtsd2ss", { XM, Vex128, EXq } },
d5d7db8e 7946 { "(bad)", { XX } },
c0f3af97
L		 7947 },
7948
7949 /* VEX_LEN_5C_P_1 */
7950 {
7951 { "vsubss", { XM, Vex128, EXd } },
d5d7db8e 7952 { "(bad)", { XX } },
c0f3af97
L		 7953 },
7954
7955 /* VEX_LEN_5C_P_3 */
7956 {
7957 { "vsubsd", { XM, Vex128, EXq } },
d5d7db8e 7958 { "(bad)", { XX } },
c0f3af97
L		 7959 },
7960
7961 /* VEX_LEN_5D_P_1 */
7962 {
7963 { "vminss", { XM, Vex128, EXd } },
d5d7db8e 7964 { "(bad)", { XX } },
c0f3af97
L		 7965 },
7966
7967 /* VEX_LEN_5D_P_3 */
7968 {
7969 { "vminsd", { XM, Vex128, EXq } },
d5d7db8e 7970 { "(bad)", { XX } },
c0f3af97
L		 7971 },
7972
7973 /* VEX_LEN_5E_P_1 */
7974 {
7975 { "vdivss", { XM, Vex128, EXd } },
85f10a01 7976 { "(bad)", { XX } },
c0f3af97
L		 7977 },
7978
7979 /* VEX_LEN_5E_P_3 */
7980 {
7981 { "vdivsd", { XM, Vex128, EXq } },
85f10a01 7982 { "(bad)", { XX } },
c0f3af97
L		 7983 },
7984
7985 /* VEX_LEN_5F_P_1 */
7986 {
7987 { "vmaxss", { XM, Vex128, EXd } },
85f10a01 7988 { "(bad)", { XX } },
c0f3af97
L		 7989 },
7990
7991 /* VEX_LEN_5F_P_3 */
7992 {
7993 { "vmaxsd", { XM, Vex128, EXq } },
85f10a01 7994 { "(bad)", { XX } },
c0f3af97
L		 7995 },
7996
7997 /* VEX_LEN_60_P_2 */
7998 {
7999 { "vpunpcklbw", { XM, Vex128, EXx } },
d5d7db8e 8000 { "(bad)", { XX } },
c0f3af97
L		 8001 },
8002
8003 /* VEX_LEN_61_P_2 */
8004 {
8005 { "vpunpcklwd", { XM, Vex128, EXx } },
d5d7db8e 8006 { "(bad)", { XX } },
c0f3af97
L		 8007 },
8008
8009 /* VEX_LEN_62_P_2 */
8010 {
8011 { "vpunpckldq", { XM, Vex128, EXx } },
d5d7db8e 8012 { "(bad)", { XX } },
c0f3af97
L		 8013 },
8014
8015 /* VEX_LEN_63_P_2 */
8016 {
8017 { "vpacksswb", { XM, Vex128, EXx } },
d5d7db8e 8018 { "(bad)", { XX } },
c0f3af97
L		 8019 },
8020
8021 /* VEX_LEN_64_P_2 */
8022 {
8023 { "vpcmpgtb", { XM, Vex128, EXx } },
d5d7db8e 8024 { "(bad)", { XX } },
c0f3af97
L		 8025 },
8026
8027 /* VEX_LEN_65_P_2 */
8028 {
8029 { "vpcmpgtw", { XM, Vex128, EXx } },
d5d7db8e 8030 { "(bad)", { XX } },
c0f3af97
L		 8031 },
8032
8033 /* VEX_LEN_66_P_2 */
8034 {
8035 { "vpcmpgtd", { XM, Vex128, EXx } },
d5d7db8e 8036 { "(bad)", { XX } },
c0f3af97
L		 8037 },
8038
8039 /* VEX_LEN_67_P_2 */
8040 {
8041 { "vpackuswb", { XM, Vex128, EXx } },
d5d7db8e 8042 { "(bad)", { XX } },
c0f3af97
L		 8043 },
8044
8045 /* VEX_LEN_68_P_2 */
8046 {
8047 { "vpunpckhbw", { XM, Vex128, EXx } },
d5d7db8e 8048 { "(bad)", { XX } },
c0f3af97
L		 8049 },
8050
8051 /* VEX_LEN_69_P_2 */
8052 {
8053 { "vpunpckhwd", { XM, Vex128, EXx } },
d5d7db8e 8054 { "(bad)", { XX } },
c0f3af97
L		 8055 },
8056
8057 /* VEX_LEN_6A_P_2 */
8058 {
8059 { "vpunpckhdq", { XM, Vex128, EXx } },
d5d7db8e 8060 { "(bad)", { XX } },
c0f3af97
L		 8061 },
8062
8063 /* VEX_LEN_6B_P_2 */
8064 {
8065 { "vpackssdw", { XM, Vex128, EXx } },
d5d7db8e 8066 { "(bad)", { XX } },
c0f3af97
L		 8067 },
8068
8069 /* VEX_LEN_6C_P_2 */
8070 {
8071 { "vpunpcklqdq", { XM, Vex128, EXx } },
d5d7db8e 8072 { "(bad)", { XX } },
c0f3af97
L		 8073 },
8074
8075 /* VEX_LEN_6D_P_2 */
8076 {
8077 { "vpunpckhqdq", { XM, Vex128, EXx } },
d5d7db8e 8078 { "(bad)", { XX } },
c0f3af97
L		 8079 },
8080
8081 /* VEX_LEN_6E_P_2 */
8082 {
8083 { "vmovK", { XM, Edq } },
d5d7db8e 8084 { "(bad)", { XX } },
c0f3af97
L		 8085 },
8086
8087 /* VEX_LEN_70_P_1 */
8088 {
8089 { "vpshufhw", { XM, EXx, Ib } },
d5d7db8e 8090 { "(bad)", { XX } },
c0f3af97
L		 8091 },
8092
8093 /* VEX_LEN_70_P_2 */
8094 {
8095 { "vpshufd", { XM, EXx, Ib } },
d5d7db8e 8096 { "(bad)", { XX } },
c0f3af97
L		 8097 },
8098
8099 /* VEX_LEN_70_P_3 */
8100 {
8101 { "vpshuflw", { XM, EXx, Ib } },
d5d7db8e 8102 { "(bad)", { XX } },
c0f3af97
L		 8103 },
8104
8105 /* VEX_LEN_71_R_2_P_2 */
8106 {
8107 { "vpsrlw", { Vex128, XS, Ib } },
d5d7db8e 8108 { "(bad)", { XX } },
c0f3af97
L		 8109 },
8110
8111 /* VEX_LEN_71_R_4_P_2 */
8112 {
8113 { "vpsraw", { Vex128, XS, Ib } },
d5d7db8e 8114 { "(bad)", { XX } },
c0f3af97
L		 8115 },
8116
8117 /* VEX_LEN_71_R_6_P_2 */
8118 {
8119 { "vpsllw", { Vex128, XS, Ib } },
d5d7db8e 8120 { "(bad)", { XX } },
c0f3af97
L		 8121 },
8122
8123 /* VEX_LEN_72_R_2_P_2 */
8124 {
8125 { "vpsrld", { Vex128, XS, Ib } },
d5d7db8e 8126 { "(bad)", { XX } },
c0f3af97
L		 8127 },
8128
8129 /* VEX_LEN_72_R_4_P_2 */
8130 {
8131 { "vpsrad", { Vex128, XS, Ib } },
d5d7db8e 8132 { "(bad)", { XX } },
c0f3af97
L		 8133 },
8134
8135 /* VEX_LEN_72_R_6_P_2 */
8136 {
8137 { "vpslld", { Vex128, XS, Ib } },
d5d7db8e 8138 { "(bad)", { XX } },
c0f3af97
L		 8139 },
8140
8141 /* VEX_LEN_73_R_2_P_2 */
8142 {
8143 { "vpsrlq", { Vex128, XS, Ib } },
d5d7db8e 8144 { "(bad)", { XX } },
c0f3af97
L		 8145 },
8146
8147 /* VEX_LEN_73_R_3_P_2 */
8148 {
8149 { "vpsrldq", { Vex128, XS, Ib } },
d5d7db8e 8150 { "(bad)", { XX } },
c0f3af97
L		 8151 },
8152
8153 /* VEX_LEN_73_R_6_P_2 */
8154 {
8155 { "vpsllq", { Vex128, XS, Ib } },
d5d7db8e 8156 { "(bad)", { XX } },
c0f3af97
L		 8157 },
8158
8159 /* VEX_LEN_73_R_7_P_2 */
8160 {
8161 { "vpslldq", { Vex128, XS, Ib } },
d5d7db8e 8162 { "(bad)", { XX } },
c0f3af97
L		 8163 },
8164
8165 /* VEX_LEN_74_P_2 */
8166 {
8167 { "vpcmpeqb", { XM, Vex128, EXx } },
d5d7db8e 8168 { "(bad)", { XX } },
c0f3af97
L		 8169 },
8170
8171 /* VEX_LEN_75_P_2 */
8172 {
8173 { "vpcmpeqw", { XM, Vex128, EXx } },
d5d7db8e 8174 { "(bad)", { XX } },
c0f3af97
L		 8175 },
8176
8177 /* VEX_LEN_76_P_2 */
8178 {
8179 { "vpcmpeqd", { XM, Vex128, EXx } },
d5d7db8e 8180 { "(bad)", { XX } },
c0f3af97
L		 8181 },
8182
8183 /* VEX_LEN_7E_P_1 */
8184 {
8185 { "vmovq", { XM, EXq } },
d5d7db8e 8186 { "(bad)", { XX } },
c0f3af97
L		 8187 },
8188
8189 /* VEX_LEN_7E_P_2 */
8190 {
8191 { "vmovK", { Edq, XM } },
d5d7db8e 8192 { "(bad)", { XX } },
c0f3af97
L		 8193 },
8194
8195 /* VEX_LEN_AE_R_2_M0 */
8196 {
8197 { "vldmxcsr", { Md } },
d5d7db8e 8198 { "(bad)", { XX } },
c0f3af97
L		 8199 },
8200
8201 /* VEX_LEN_AE_R_3_M0 */
8202 {
8203 { "vstmxcsr", { Md } },
d5d7db8e 8204 { "(bad)", { XX } },
c0f3af97
L		 8205 },
8206
8207 /* VEX_LEN_C2_P_1 */
8208 {
8209 { "vcmpss", { XM, Vex128, EXd, VCMP } },
d5d7db8e 8210 { "(bad)", { XX } },
c0f3af97
L		 8211 },
8212
8213 /* VEX_LEN_C2_P_3 */
8214 {
8215 { "vcmpsd", { XM, Vex128, EXq, VCMP } },
d5d7db8e 8216 { "(bad)", { XX } },
c0f3af97
L		 8217 },
8218
8219 /* VEX_LEN_C4_P_2 */
8220 {
8221 { "vpinsrw", { XM, Vex128, Edqw, Ib } },
d5d7db8e 8222 { "(bad)", { XX } },
c0f3af97
L		 8223 },
8224
8225 /* VEX_LEN_C5_P_2 */
8226 {
8227 { "vpextrw", { Gdq, XS, Ib } },
d5d7db8e 8228 { "(bad)", { XX } },
c0f3af97
L		 8229 },
8230
8231 /* VEX_LEN_D1_P_2 */
8232 {
8233 { "vpsrlw", { XM, Vex128, EXx } },
d5d7db8e 8234 { "(bad)", { XX } },
c0f3af97
L		 8235 },
8236
8237 /* VEX_LEN_D2_P_2 */
8238 {
8239 { "vpsrld", { XM, Vex128, EXx } },
d5d7db8e 8240 { "(bad)", { XX } },
c0f3af97
L		 8241 },
8242
8243 /* VEX_LEN_D3_P_2 */
8244 {
8245 { "vpsrlq", { XM, Vex128, EXx } },
d5d7db8e 8246 { "(bad)", { XX } },
c0f3af97
L		 8247 },
8248
8249 /* VEX_LEN_D4_P_2 */
8250 {
8251 { "vpaddq", { XM, Vex128, EXx } },
d5d7db8e 8252 { "(bad)", { XX } },
c0f3af97
L		 8253 },
8254
8255 /* VEX_LEN_D5_P_2 */
8256 {
8257 { "vpmullw", { XM, Vex128, EXx } },
d5d7db8e 8258 { "(bad)", { XX } },
c0f3af97
L		 8259 },
8260
8261 /* VEX_LEN_D6_P_2 */
8262 {
8263 { "vmovq", { EXq, XM } },
d5d7db8e 8264 { "(bad)", { XX } },
c0f3af97
L		 8265 },
8266
8267 /* VEX_LEN_D7_P_2_M_1 */
8268 {
8269 { "vpmovmskb", { Gdq, XS } },
d5d7db8e 8270 { "(bad)", { XX } },
c0f3af97
L		 8271 },
8272
8273 /* VEX_LEN_D8_P_2 */
8274 {
8275 { "vpsubusb", { XM, Vex128, EXx } },
d5d7db8e 8276 { "(bad)", { XX } },
c0f3af97
L		 8277 },
8278
8279 /* VEX_LEN_D9_P_2 */
8280 {
8281 { "vpsubusw", { XM, Vex128, EXx } },
d5d7db8e 8282 { "(bad)", { XX } },
c0f3af97
L		 8283 },
8284
8285 /* VEX_LEN_DA_P_2 */
8286 {
8287 { "vpminub", { XM, Vex128, EXx } },
d5d7db8e 8288 { "(bad)", { XX } },
c0f3af97
L		 8289 },
8290
8291 /* VEX_LEN_DB_P_2 */
8292 {
8293 { "vpand", { XM, Vex128, EXx } },
d5d7db8e 8294 { "(bad)", { XX } },
c0f3af97
L		 8295 },
8296
8297 /* VEX_LEN_DC_P_2 */
8298 {
8299 { "vpaddusb", { XM, Vex128, EXx } },
d5d7db8e 8300 { "(bad)", { XX } },
c0f3af97
L		 8301 },
8302
8303 /* VEX_LEN_DD_P_2 */
8304 {
8305 { "vpaddusw", { XM, Vex128, EXx } },
d5d7db8e 8306 { "(bad)", { XX } },
c0f3af97
L		 8307 },
8308
8309 /* VEX_LEN_DE_P_2 */
8310 {
8311 { "vpmaxub", { XM, Vex128, EXx } },
d5d7db8e 8312 { "(bad)", { XX } },
c0f3af97
L		 8313 },
8314
8315 /* VEX_LEN_DF_P_2 */
8316 {
8317 { "vpandn", { XM, Vex128, EXx } },
d5d7db8e 8318 { "(bad)", { XX } },
c0f3af97
L		 8319 },
8320
8321 /* VEX_LEN_E0_P_2 */
8322 {
8323 { "vpavgb", { XM, Vex128, EXx } },
d5d7db8e 8324 { "(bad)", { XX } },
c0f3af97
L		 8325 },
8326
8327 /* VEX_LEN_E1_P_2 */
8328 {
8329 { "vpsraw", { XM, Vex128, EXx } },
d5d7db8e 8330 { "(bad)", { XX } },
c0f3af97
L		 8331 },
8332
8333 /* VEX_LEN_E2_P_2 */
8334 {
8335 { "vpsrad", { XM, Vex128, EXx } },
d5d7db8e 8336 { "(bad)", { XX } },
c0f3af97
L		 8337 },
8338
8339 /* VEX_LEN_E3_P_2 */
8340 {
8341 { "vpavgw", { XM, Vex128, EXx } },
d5d7db8e 8342 { "(bad)", { XX } },
c0f3af97
L		 8343 },
8344
8345 /* VEX_LEN_E4_P_2 */
8346 {
8347 { "vpmulhuw", { XM, Vex128, EXx } },
d5d7db8e 8348 { "(bad)", { XX } },
c0f3af97
L		 8349 },
8350
8351 /* VEX_LEN_E5_P_2 */
8352 {
8353 { "vpmulhw", { XM, Vex128, EXx } },
d5d7db8e 8354 { "(bad)", { XX } },
c0f3af97
L		 8355 },
8356
8357 /* VEX_LEN_E7_P_2_M_0 */
8358 {
8359 { "vmovntdq", { Mx, XM } },
d5d7db8e 8360 { "(bad)", { XX } },
c0f3af97
L		 8361 },
8362
8363 /* VEX_LEN_E8_P_2 */
8364 {
8365 { "vpsubsb", { XM, Vex128, EXx } },
d5d7db8e 8366 { "(bad)", { XX } },
c0f3af97
L		 8367 },
8368
8369 /* VEX_LEN_E9_P_2 */
8370 {
8371 { "vpsubsw", { XM, Vex128, EXx } },
d5d7db8e 8372 { "(bad)", { XX } },
c0f3af97
L		 8373 },
8374
8375 /* VEX_LEN_EA_P_2 */
8376 {
8377 { "vpminsw", { XM, Vex128, EXx } },
d5d7db8e 8378 { "(bad)", { XX } },
c0f3af97
L		 8379 },
8380
8381 /* VEX_LEN_EB_P_2 */
8382 {
8383 { "vpor", { XM, Vex128, EXx } },
d5d7db8e 8384 { "(bad)", { XX } },
c0f3af97
L		 8385 },
8386
8387 /* VEX_LEN_EC_P_2 */
8388 {
8389 { "vpaddsb", { XM, Vex128, EXx } },
d5d7db8e 8390 { "(bad)", { XX } },
c0f3af97
L		 8391 },
8392
8393 /* VEX_LEN_ED_P_2 */
8394 {
8395 { "vpaddsw", { XM, Vex128, EXx } },
d5d7db8e 8396 { "(bad)", { XX } },
c0f3af97
L		 8397 },
8398
8399 /* VEX_LEN_EE_P_2 */
8400 {
8401 { "vpmaxsw", { XM, Vex128, EXx } },
d5d7db8e 8402 { "(bad)", { XX } },
c0f3af97
L		 8403 },
8404
8405 /* VEX_LEN_EF_P_2 */
8406 {
8407 { "vpxor", { XM, Vex128, EXx } },
d5d7db8e 8408 { "(bad)", { XX } },
c0f3af97
L		 8409 },
8410
8411 /* VEX_LEN_F1_P_2 */
8412 {
8413 { "vpsllw", { XM, Vex128, EXx } },
d5d7db8e 8414 { "(bad)", { XX } },
c0f3af97
L		 8415 },
8416
8417 /* VEX_LEN_F2_P_2 */
8418 {
8419 { "vpslld", { XM, Vex128, EXx } },
d5d7db8e 8420 { "(bad)", { XX } },
c0f3af97
L		 8421 },
8422
8423 /* VEX_LEN_F3_P_2 */
8424 {
8425 { "vpsllq", { XM, Vex128, EXx } },
d5d7db8e 8426 { "(bad)", { XX } },
c0f3af97
L		 8427 },
8428
8429 /* VEX_LEN_F4_P_2 */
8430 {
8431 { "vpmuludq", { XM, Vex128, EXx } },
d5d7db8e 8432 { "(bad)", { XX } },
c0f3af97
L		 8433 },
8434
8435 /* VEX_LEN_F5_P_2 */
8436 {
8437 { "vpmaddwd", { XM, Vex128, EXx } },
d5d7db8e 8438 { "(bad)", { XX } },
c0f3af97
L		 8439 },
8440
8441 /* VEX_LEN_F6_P_2 */
8442 {
8443 { "vpsadbw", { XM, Vex128, EXx } },
d5d7db8e 8444 { "(bad)", { XX } },
c0f3af97
L		 8445 },
8446
8447 /* VEX_LEN_F7_P_2 */
8448 {
8449 { "vmaskmovdqu", { XM, XS } },
d5d7db8e 8450 { "(bad)", { XX } },
c0f3af97
L		 8451 },
8452
8453 /* VEX_LEN_F8_P_2 */
8454 {
8455 { "vpsubb", { XM, Vex128, EXx } },
d5d7db8e 8456 { "(bad)", { XX } },
c0f3af97
L		 8457 },
8458
8459 /* VEX_LEN_F9_P_2 */
8460 {
8461 { "vpsubw", { XM, Vex128, EXx } },
d5d7db8e 8462 { "(bad)", { XX } },
c0f3af97
L		 8463 },
8464
8465 /* VEX_LEN_FA_P_2 */
8466 {
8467 { "vpsubd", { XM, Vex128, EXx } },
d5d7db8e 8468 { "(bad)", { XX } },
c0f3af97
L		 8469 },
8470
8471 /* VEX_LEN_FB_P_2 */
8472 {
8473 { "vpsubq", { XM, Vex128, EXx } },
d5d7db8e 8474 { "(bad)", { XX } },
c0f3af97
L		 8475 },
8476
8477 /* VEX_LEN_FC_P_2 */
8478 {
8479 { "vpaddb", { XM, Vex128, EXx } },
d5d7db8e 8480 { "(bad)", { XX } },
c0f3af97
L		 8481 },
8482
8483 /* VEX_LEN_FD_P_2 */
8484 {
8485 { "vpaddw", { XM, Vex128, EXx } },
d5d7db8e 8486 { "(bad)", { XX } },
c0f3af97
L		 8487 },
8488
8489 /* VEX_LEN_FE_P_2 */
8490 {
8491 { "vpaddd", { XM, Vex128, EXx } },
d5d7db8e 8492 { "(bad)", { XX } },
c0f3af97
L		 8493 },
8494
8495 /* VEX_LEN_3800_P_2 */
8496 {
8497 { "vpshufb", { XM, Vex128, EXx } },
d5d7db8e 8498 { "(bad)", { XX } },
c0f3af97
L		 8499 },
8500
8501 /* VEX_LEN_3801_P_2 */
8502 {
8503 { "vphaddw", { XM, Vex128, EXx } },
d5d7db8e 8504 { "(bad)", { XX } },
c0f3af97
L		 8505 },
8506
8507 /* VEX_LEN_3802_P_2 */
8508 {
8509 { "vphaddd", { XM, Vex128, EXx } },
d5d7db8e 8510 { "(bad)", { XX } },
c0f3af97
L		 8511 },
8512
8513 /* VEX_LEN_3803_P_2 */
8514 {
8515 { "vphaddsw", { XM, Vex128, EXx } },
d5d7db8e 8516 { "(bad)", { XX } },
c0f3af97
L		 8517 },
8518
8519 /* VEX_LEN_3804_P_2 */
8520 {
8521 { "vpmaddubsw", { XM, Vex128, EXx } },
d5d7db8e 8522 { "(bad)", { XX } },
c0f3af97
L		 8523 },
8524
8525 /* VEX_LEN_3805_P_2 */
8526 {
8527 { "vphsubw", { XM, Vex128, EXx } },
d5d7db8e 8528 { "(bad)", { XX } },
c0f3af97
L		 8529 },
8530
8531 /* VEX_LEN_3806_P_2 */
8532 {
8533 { "vphsubd", { XM, Vex128, EXx } },
d5d7db8e 8534 { "(bad)", { XX } },
c0f3af97
L		 8535 },
8536
8537 /* VEX_LEN_3807_P_2 */
8538 {
8539 { "vphsubsw", { XM, Vex128, EXx } },
d5d7db8e 8540 { "(bad)", { XX } },
c0f3af97
L		 8541 },
8542
8543 /* VEX_LEN_3808_P_2 */
8544 {
8545 { "vpsignb", { XM, Vex128, EXx } },
d5d7db8e 8546 { "(bad)", { XX } },
c0f3af97
L		 8547 },
8548
8549 /* VEX_LEN_3809_P_2 */
8550 {
8551 { "vpsignw", { XM, Vex128, EXx } },
d5d7db8e 8552 { "(bad)", { XX } },
c0f3af97
L		 8553 },
8554
8555 /* VEX_LEN_380A_P_2 */
8556 {
8557 { "vpsignd", { XM, Vex128, EXx } },
d5d7db8e 8558 { "(bad)", { XX } },
c0f3af97
L		 8559 },
8560
8561 /* VEX_LEN_380B_P_2 */
8562 {
8563 { "vpmulhrsw", { XM, Vex128, EXx } },
d5d7db8e 8564 { "(bad)", { XX } },
c0f3af97
L		 8565 },
8566
8567 /* VEX_LEN_3819_P_2_M_0 */
8568 {
d5d7db8e 8569 { "(bad)", { XX } },
c0f3af97
L		 8570 { "vbroadcastsd", { XM, Mq } },
8571 },
8572
8573 /* VEX_LEN_381A_P_2_M_0 */
8574 {
d5d7db8e 8575 { "(bad)", { XX } },
c0f3af97
L		 8576 { "vbroadcastf128", { XM, Mxmm } },
8577 },
8578
8579 /* VEX_LEN_381C_P_2 */
8580 {
8581 { "vpabsb", { XM, EXx } },
d5d7db8e 8582 { "(bad)", { XX } },
c0f3af97
L		 8583 },
8584
8585 /* VEX_LEN_381D_P_2 */
8586 {
8587 { "vpabsw", { XM, EXx } },
d5d7db8e 8588 { "(bad)", { XX } },
c0f3af97
L		 8589 },
8590
8591 /* VEX_LEN_381E_P_2 */
8592 {
8593 { "vpabsd", { XM, EXx } },
d5d7db8e 8594 { "(bad)", { XX } },
c0f3af97
L		 8595 },
8596
8597 /* VEX_LEN_3820_P_2 */
8598 {
8599 { "vpmovsxbw", { XM, EXq } },
d5d7db8e 8600 { "(bad)", { XX } },
c0f3af97
L		 8601 },
8602
8603 /* VEX_LEN_3821_P_2 */
8604 {
8605 { "vpmovsxbd", { XM, EXd } },
d5d7db8e 8606 { "(bad)", { XX } },
c0f3af97
L		 8607 },
8608
8609 /* VEX_LEN_3822_P_2 */
8610 {
8611 { "vpmovsxbq", { XM, EXw } },
d5d7db8e 8612 { "(bad)", { XX } },
c0f3af97
L		 8613 },
8614
8615 /* VEX_LEN_3823_P_2 */
8616 {
8617 { "vpmovsxwd", { XM, EXq } },
d5d7db8e 8618 { "(bad)", { XX } },
c0f3af97
L		 8619 },
8620
8621 /* VEX_LEN_3824_P_2 */
8622 {
8623 { "vpmovsxwq", { XM, EXd } },
d5d7db8e 8624 { "(bad)", { XX } },
c0f3af97
L		 8625 },
8626
8627 /* VEX_LEN_3825_P_2 */
8628 {
8629 { "vpmovsxdq", { XM, EXq } },
d5d7db8e 8630 { "(bad)", { XX } },
c0f3af97
L		 8631 },
8632
8633 /* VEX_LEN_3828_P_2 */
8634 {
8635 { "vpmuldq", { XM, Vex128, EXx } },
d5d7db8e 8636 { "(bad)", { XX } },
c0f3af97
L		 8637 },
8638
8639 /* VEX_LEN_3829_P_2 */
8640 {
8641 { "vpcmpeqq", { XM, Vex128, EXx } },
d5d7db8e 8642 { "(bad)", { XX } },
c0f3af97
L		 8643 },
8644
8645 /* VEX_LEN_382A_P_2_M_0 */
8646 {
8647 { "vmovntdqa", { XM, Mx } },
d5d7db8e 8648 { "(bad)", { XX } },
c0f3af97
L		 8649 },
8650
8651 /* VEX_LEN_382B_P_2 */
8652 {
8653 { "vpackusdw", { XM, Vex128, EXx } },
d5d7db8e 8654 { "(bad)", { XX } },
c0f3af97
L		 8655 },
8656
8657 /* VEX_LEN_3830_P_2 */
8658 {
8659 { "vpmovzxbw", { XM, EXq } },
d5d7db8e 8660 { "(bad)", { XX } },
c0f3af97
L		 8661 },
8662
8663 /* VEX_LEN_3831_P_2 */
8664 {
8665 { "vpmovzxbd", { XM, EXd } },
d5d7db8e 8666 { "(bad)", { XX } },
c0f3af97
L		 8667 },
8668
8669 /* VEX_LEN_3832_P_2 */
8670 {
8671 { "vpmovzxbq", { XM, EXw } },
d5d7db8e 8672 { "(bad)", { XX } },
c0f3af97
L		 8673 },
8674
8675 /* VEX_LEN_3833_P_2 */
8676 {
8677 { "vpmovzxwd", { XM, EXq } },
d5d7db8e 8678 { "(bad)", { XX } },
c0f3af97
L		 8679 },
8680
8681 /* VEX_LEN_3834_P_2 */
8682 {
8683 { "vpmovzxwq", { XM, EXd } },
d5d7db8e 8684 { "(bad)", { XX } },
c0f3af97
L		 8685 },
8686
8687 /* VEX_LEN_3835_P_2 */
8688 {
8689 { "vpmovzxdq", { XM, EXq } },
d5d7db8e 8690 { "(bad)", { XX } },
c0f3af97
L		 8691 },
8692
8693 /* VEX_LEN_3837_P_2 */
8694 {
8695 { "vpcmpgtq", { XM, Vex128, EXx } },
d5d7db8e 8696 { "(bad)", { XX } },
c0f3af97
L		 8697 },
8698
8699 /* VEX_LEN_3838_P_2 */
8700 {
8701 { "vpminsb", { XM, Vex128, EXx } },
d5d7db8e 8702 { "(bad)", { XX } },
c0f3af97
L		 8703 },
8704
8705 /* VEX_LEN_3839_P_2 */
8706 {
8707 { "vpminsd", { XM, Vex128, EXx } },
d5d7db8e 8708 { "(bad)", { XX } },
c0f3af97
L		 8709 },
8710
8711 /* VEX_LEN_383A_P_2 */
8712 {
8713 { "vpminuw", { XM, Vex128, EXx } },
d5d7db8e 8714 { "(bad)", { XX } },
c0f3af97
L		 8715 },
8716
8717 /* VEX_LEN_383B_P_2 */
8718 {
8719 { "vpminud", { XM, Vex128, EXx } },
d5d7db8e 8720 { "(bad)", { XX } },
c0f3af97
L		 8721 },
8722
8723 /* VEX_LEN_383C_P_2 */
8724 {
8725 { "vpmaxsb", { XM, Vex128, EXx } },
d5d7db8e 8726 { "(bad)", { XX } },
c0f3af97
L		 8727 },
8728
8729 /* VEX_LEN_383D_P_2 */
8730 {
8731 { "vpmaxsd", { XM, Vex128, EXx } },
d5d7db8e 8732 { "(bad)", { XX } },
c0f3af97
L		 8733 },
8734
8735 /* VEX_LEN_383E_P_2 */
8736 {
8737 { "vpmaxuw", { XM, Vex128, EXx } },
d5d7db8e 8738 { "(bad)", { XX } },
c0f3af97
L		 8739 },
8740
8741 /* VEX_LEN_383F_P_2 */
8742 {
8743 { "vpmaxud", { XM, Vex128, EXx } },
d5d7db8e 8744 { "(bad)", { XX } },
c0f3af97
L		 8745 },
8746
8747 /* VEX_LEN_3840_P_2 */
8748 {
8749 { "vpmulld", { XM, Vex128, EXx } },
d5d7db8e 8750 { "(bad)", { XX } },
c0f3af97
L		 8751 },
8752
8753 /* VEX_LEN_3841_P_2 */
8754 {
8755 { "vphminposuw", { XM, EXx } },
d5d7db8e 8756 { "(bad)", { XX } },
c0f3af97
L		 8757 },
8758
8759 /* VEX_LEN_3A06_P_2 */
8760 {
d5d7db8e 8761 { "(bad)", { XX } },
c0f3af97
L		 8762 { "vperm2f128", { XM, Vex256, EXx, Ib } },
8763 },
8764
8765 /* VEX_LEN_3A0A_P_2 */
8766 {
8767 { "vroundss", { XM, Vex128, EXd, Ib } },
d5d7db8e 8768 { "(bad)", { XX } },
c0f3af97
L		 8769 },
8770
8771 /* VEX_LEN_3A0B_P_2 */
8772 {
8773 { "vroundsd", { XM, Vex128, EXq, Ib } },
d5d7db8e 8774 { "(bad)", { XX } },
c0f3af97
L		 8775 },
8776
8777 /* VEX_LEN_3A0E_P_2 */
8778 {
8779 { "vpblendw", { XM, Vex128, EXx, Ib } },
d5d7db8e 8780 { "(bad)", { XX } },
c0f3af97
L		 8781 },
8782
8783 /* VEX_LEN_3A0F_P_2 */
8784 {
8785 { "vpalignr", { XM, Vex128, EXx, Ib } },
d5d7db8e 8786 { "(bad)", { XX } },
c0f3af97
L		 8787 },
8788
8789 /* VEX_LEN_3A14_P_2 */
8790 {
8791 { "vpextrb", { Edqb, XM, Ib } },
d5d7db8e 8792 { "(bad)", { XX } },
c0f3af97
L		 8793 },
8794
8795 /* VEX_LEN_3A15_P_2 */
8796 {
8797 { "vpextrw", { Edqw, XM, Ib } },
d5d7db8e 8798 { "(bad)", { XX } },
c0f3af97
L		 8799 },
8800
8801 /* VEX_LEN_3A16_P_2 */
8802 {
8803 { "vpextrK", { Edq, XM, Ib } },
d5d7db8e 8804 { "(bad)", { XX } },
c0f3af97
L		 8805 },
8806
8807 /* VEX_LEN_3A17_P_2 */
8808 {
8809 { "vextractps", { Edqd, XM, Ib } },
d5d7db8e 8810 { "(bad)", { XX } },
c0f3af97
L		 8811 },
8812
8813 /* VEX_LEN_3A18_P_2 */
8814 {
d5d7db8e 8815 { "(bad)", { XX } },
c0f3af97
L		 8816 { "vinsertf128", { XM, Vex256, EXxmm, Ib } },
8817 },
8818
8819 /* VEX_LEN_3A19_P_2 */
8820 {
d5d7db8e 8821 { "(bad)", { XX } },
c0f3af97
L		 8822 { "vextractf128", { EXxmm, XM, Ib } },
8823 },
8824
8825 /* VEX_LEN_3A20_P_2 */
8826 {
8827 { "vpinsrb", { XM, Vex128, Edqb, Ib } },
d5d7db8e 8828 { "(bad)", { XX } },
c0f3af97
L		 8829 },
8830
8831 /* VEX_LEN_3A21_P_2 */
8832 {
8833 { "vinsertps", { XM, Vex128, EXd, Ib } },
d5d7db8e 8834 { "(bad)", { XX } },
c0f3af97
L		 8835 },
8836
8837 /* VEX_LEN_3A22_P_2 */
8838 {
8839 { "vpinsrK", { XM, Vex128, Edq, Ib } },
d5d7db8e 8840 { "(bad)", { XX } },
c0f3af97
L		 8841 },
8842
8843 /* VEX_LEN_3A41_P_2 */
8844 {
8845 { "vdppd", { XM, Vex128, EXx, Ib } },
d5d7db8e 8846 { "(bad)", { XX } },
c0f3af97
L		 8847 },
8848
8849 /* VEX_LEN_3A42_P_2 */
8850 {
8851 { "vmpsadbw", { XM, Vex128, EXx, Ib } },
d5d7db8e 8852 { "(bad)", { XX } },
c0f3af97
L		 8853 },
8854
8855 /* VEX_LEN_3A4C_P_2 */
8856 {
8857 { "vpblendvb", { XM, Vex128, EXx, XMVexI4 } },
d5d7db8e 8858 { "(bad)", { XX } },
c0f3af97
L		 8859 },
8860
8861 /* VEX_LEN_3A60_P_2 */
8862 {
8863 { "vpcmpestrm", { XM, EXx, Ib } },
d5d7db8e 8864 { "(bad)", { XX } },
c0f3af97
L		 8865 },
8866
8867 /* VEX_LEN_3A61_P_2 */
8868 {
8869 { "vpcmpestri", { XM, EXx, Ib } },
d5d7db8e 8870 { "(bad)", { XX } },
c0f3af97
L		 8871 },
8872
8873 /* VEX_LEN_3A62_P_2 */
8874 {
8875 { "vpcmpistrm", { XM, EXx, Ib } },
d5d7db8e 8876 { "(bad)", { XX } },
c0f3af97
L		 8877 },
8878
8879 /* VEX_LEN_3A63_P_2 */
8880 {
8881 { "vpcmpistri", { XM, EXx, Ib } },
d5d7db8e 8882 { "(bad)", { XX } },
c0f3af97
L		 8883 },
8884
8885 /* VEX_LEN_3A6A_P_2 */
8886 {
dae39acc 8887 { "vfmaddss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
d5d7db8e 8888 { "(bad)", { XX } },
c0f3af97
L		 8889 },
8890
8891 /* VEX_LEN_3A6B_P_2 */
8892 {
dae39acc 8893 { "vfmaddsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
d5d7db8e 8894 { "(bad)", { XX } },
c0f3af97
L		 8895 },
8896
8897 /* VEX_LEN_3A6E_P_2 */
8898 {
dae39acc 8899 { "vfmsubss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
d5d7db8e 8900 { "(bad)", { XX } },
c0f3af97
L		 8901 },
8902
8903 /* VEX_LEN_3A6F_P_2 */
8904 {
dae39acc 8905 { "vfmsubsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
d5d7db8e 8906 { "(bad)", { XX } },
c0f3af97
L		 8907 },
8908
8909 /* VEX_LEN_3A7A_P_2 */
8910 {
dae39acc 8911 { "vfnmaddss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
d5d7db8e 8912 { "(bad)", { XX } },
c0f3af97
L		 8913 },
8914
8915 /* VEX_LEN_3A7B_P_2 */
8916 {
dae39acc 8917 { "vfnmaddsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
d5d7db8e 8918 { "(bad)", { XX } },
c0f3af97
L		 8919 },
8920
8921 /* VEX_LEN_3A7E_P_2 */
8922 {
dae39acc 8923 { "vfnmsubss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
d5d7db8e 8924 { "(bad)", { XX } },
c0f3af97
L		 8925 },
8926
8927 /* VEX_LEN_3A7F_P_2 */
8928 {
dae39acc 8929 { "vfnmsubsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
d5d7db8e 8930 { "(bad)", { XX } },
c0f3af97 8931 },
331d2d0d
L		 8932};
8933
1ceb70f8 8934static const struct dis386 mod_table[][2] = {
b844680a 8935 {
1ceb70f8 8936 /* MOD_8D */
d8faab4e
L		 8937 { "leaS", { Gv, M } },
8938 { "(bad)", { XX } },
8939 },
8940 {
92fddf8e
L		 8941 /* MOD_0F01_REG_0 */
8942 { X86_64_TABLE (X86_64_0F01_REG_0) },
8943 { RM_TABLE (RM_0F01_REG_0) },
d8faab4e
L		 8944 },
8945 {
92fddf8e
L		 8946 /* MOD_0F01_REG_1 */
8947 { X86_64_TABLE (X86_64_0F01_REG_1) },
8948 { RM_TABLE (RM_0F01_REG_1) },
d8faab4e
L		 8949 },
8950 {
92fddf8e
L		 8951 /* MOD_0F01_REG_2 */
8952 { X86_64_TABLE (X86_64_0F01_REG_2) },
475a2301 8953 { RM_TABLE (RM_0F01_REG_2) },
d8faab4e
L		 8954 },
8955 {
92fddf8e
L		 8956 /* MOD_0F01_REG_3 */
8957 { X86_64_TABLE (X86_64_0F01_REG_3) },
8958 { RM_TABLE (RM_0F01_REG_3) },
d8faab4e
L		 8959 },
8960 {
92fddf8e
L		 8961 /* MOD_0F01_REG_7 */
8962 { "invlpg", { Mb } },
8963 { RM_TABLE (RM_0F01_REG_7) },
b844680a
L		 8964 },
8965 {
92fddf8e
L		 8966 /* MOD_0F12_PREFIX_0 */
8967 { "movlps", { XM, EXq } },
8968 { "movhlps", { XM, EXq } },
b844680a
L		 8969 },
8970 {
92fddf8e
L		 8971 /* MOD_0F13 */
8972 { "movlpX", { EXq, XM } },
d8faab4e
L		 8973 { "(bad)", { XX } },
8974 },
8975 {
92fddf8e
L		 8976 /* MOD_0F16_PREFIX_0 */
8977 { "movhps", { XM, EXq } },
8978 { "movlhps", { XM, EXq } },
b844680a
L		 8979 },
8980 {
92fddf8e
L		 8981 /* MOD_0F17 */
8982 { "movhpX", { EXq, XM } },
b844680a
L		 8983 { "(bad)", { XX } },
8984 },
8985 {
92fddf8e
L		 8986 /* MOD_0F18_REG_0 */
8987 { "prefetchnta", { Mb } },
b844680a 8988 { "(bad)", { XX } },
b844680a
L		 8989 },
8990 {
92fddf8e
L		 8991 /* MOD_0F18_REG_1 */
8992 { "prefetcht0", { Mb } },
8993 { "(bad)", { XX } },
b844680a
L		 8994 },
8995 {
92fddf8e
L		 8996 /* MOD_0F18_REG_2 */
8997 { "prefetcht1", { Mb } },
8998 { "(bad)", { XX } },
b844680a
L		 8999 },
9000 {
92fddf8e
L		 9001 /* MOD_0F18_REG_3 */
9002 { "prefetcht2", { Mb } },
b844680a 9003 { "(bad)", { XX } },
b844680a
L		 9004 },
9005 {
92fddf8e
L		 9006 /* MOD_0F20 */
9007 { "(bad)", { XX } },
9008 { "movZ", { Rm, Cm } },
b844680a
L		 9009 },
9010 {
92fddf8e
L		 9011 /* MOD_0F21 */
9012 { "(bad)", { XX } },
9013 { "movZ", { Rm, Dm } },
b844680a
L		 9014 },
9015 {
92fddf8e 9016 /* MOD_0F22 */
b844680a 9017 { "(bad)", { XX } },
92fddf8e 9018 { "movZ", { Cm, Rm } },
b844680a
L		 9019 },
9020 {
92fddf8e 9021 /* MOD_0F23 */
b844680a 9022 { "(bad)", { XX } },
92fddf8e 9023 { "movZ", { Dm, Rm } },
b844680a
L		 9024 },
9025 {
92fddf8e
L		 9026 /* MOD_0F24 */
9027 { THREE_BYTE_TABLE (THREE_BYTE_0F24) },
9028 { "movL", { Rd, Td } },
b844680a
L		 9029 },
9030 {
92fddf8e 9031 /* MOD_0F26 */
b844680a 9032 { "(bad)", { XX } },
92fddf8e 9033 { "movL", { Td, Rd } },
b844680a 9034 },
75c135a8
L		 9035 {
9036 /* MOD_0F2B_PREFIX_0 */
4ee52178 9037 {"movntps", { Mx, XM } },
75c135a8
L		 9038 { "(bad)", { XX } },
9039 },
9040 {
9041 /* MOD_0F2B_PREFIX_1 */
4ee52178 9042 {"movntss", { Md, XM } },
75c135a8
L		 9043 { "(bad)", { XX } },
9044 },
9045 {
9046 /* MOD_0F2B_PREFIX_2 */
4ee52178 9047 {"movntpd", { Mx, XM } },
75c135a8
L		 9048 { "(bad)", { XX } },
9049 },
9050 {
9051 /* MOD_0F2B_PREFIX_3 */
4ee52178 9052 {"movntsd", { Mq, XM } },
75c135a8
L		 9053 { "(bad)", { XX } },
9054 },
9055 {
9056 /* MOD_0F51 */
9057 { "(bad)", { XX } },
9058 { "movmskpX", { Gdq, XS } },
9059 },
b844680a 9060 {
1ceb70f8 9061 /* MOD_0F71_REG_2 */
b844680a 9062 { "(bad)", { XX } },
4e7d34a6 9063 { "psrlw", { MS, Ib } },
b844680a
L		 9064 },
9065 {
1ceb70f8 9066 /* MOD_0F71_REG_4 */
b844680a 9067 { "(bad)", { XX } },
4e7d34a6 9068 { "psraw", { MS, Ib } },
b844680a
L		 9069 },
9070 {
1ceb70f8 9071 /* MOD_0F71_REG_6 */
b844680a 9072 { "(bad)", { XX } },
4e7d34a6 9073 { "psllw", { MS, Ib } },
b844680a
L		 9074 },
9075 {
1ceb70f8 9076 /* MOD_0F72_REG_2 */
b844680a 9077 { "(bad)", { XX } },
4e7d34a6 9078 { "psrld", { MS, Ib } },
b844680a
L		 9079 },
9080 {
1ceb70f8 9081 /* MOD_0F72_REG_4 */
b844680a 9082 { "(bad)", { XX } },
4e7d34a6 9083 { "psrad", { MS, Ib } },
b844680a
L		 9084 },
9085 {
1ceb70f8 9086 /* MOD_0F72_REG_6 */
b844680a 9087 { "(bad)", { XX } },
4e7d34a6 9088 { "pslld", { MS, Ib } },
b844680a
L		 9089 },
9090 {
1ceb70f8 9091 /* MOD_0F73_REG_2 */
4e7d34a6
L		 9092 { "(bad)", { XX } },
9093 { "psrlq", { MS, Ib } },
b844680a
L		 9094 },
9095 {
1ceb70f8 9096 /* MOD_0F73_REG_3 */
b844680a 9097 { "(bad)", { XX } },
c0f3af97
L		 9098 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
9099 },
9100 {
9101 /* MOD_0F73_REG_6 */
9102 { "(bad)", { XX } },
9103 { "psllq", { MS, Ib } },
9104 },
9105 {
9106 /* MOD_0F73_REG_7 */
9107 { "(bad)", { XX } },
9108 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
9109 },
9110 {
9111 /* MOD_0FAE_REG_0 */
9112 { "fxsave", { M } },
9113 { "(bad)", { XX } },
9114 },
9115 {
9116 /* MOD_0FAE_REG_1 */
9117 { "fxrstor", { M } },
9118 { "(bad)", { XX } },
9119 },
9120 {
9121 /* MOD_0FAE_REG_2 */
9122 { "ldmxcsr", { Md } },
9123 { "(bad)", { XX } },
9124 },
9125 {
9126 /* MOD_0FAE_REG_3 */
9127 { "stmxcsr", { Md } },
9128 { "(bad)", { XX } },
9129 },
9130 {
9131 /* MOD_0FAE_REG_4 */
9132 { "xsave", { M } },
9133 { "(bad)", { XX } },
9134 },
9135 {
9136 /* MOD_0FAE_REG_5 */
9137 { "xrstor", { M } },
9138 { RM_TABLE (RM_0FAE_REG_5) },
9139 },
9140 {
9141 /* MOD_0FAE_REG_6 */
9142 { "xsaveopt", { M } },
9143 { RM_TABLE (RM_0FAE_REG_6) },
9144 },
9145 {
9146 /* MOD_0FAE_REG_7 */
9147 { "clflush", { Mb } },
9148 { RM_TABLE (RM_0FAE_REG_7) },
9149 },
9150 {
9151 /* MOD_0FB2 */
9152 { "lssS", { Gv, Mp } },
9153 { "(bad)", { XX } },
9154 },
9155 {
9156 /* MOD_0FB4 */
9157 { "lfsS", { Gv, Mp } },
9158 { "(bad)", { XX } },
9159 },
9160 {
9161 /* MOD_0FB5 */
9162 { "lgsS", { Gv, Mp } },
9163 { "(bad)", { XX } },
9164 },
9165 {
9166 /* MOD_0FC7_REG_6 */
9167 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
9168 { "(bad)", { XX } },
9169 },
9170 {
9171 /* MOD_0FC7_REG_7 */
9172 { "vmptrst", { Mq } },
9173 { "(bad)", { XX } },
9174 },
9175 {
9176 /* MOD_0FD7 */
9177 { "(bad)", { XX } },
9178 { "pmovmskb", { Gdq, MS } },
9179 },
9180 {
9181 /* MOD_0FE7_PREFIX_2 */
9182 { "movntdq", { Mx, XM } },
9183 { "(bad)", { XX } },
9184 },
9185 {
9186 /* MOD_0FF0_PREFIX_3 */
9187 { "lddqu", { XM, M } },
9188 { "(bad)", { XX } },
9189 },
9190 {
9191 /* MOD_0F382A_PREFIX_2 */
9192 { "movntdqa", { XM, Mx } },
9193 { "(bad)", { XX } },
9194 },
9195 {
9196 /* MOD_62_32BIT */
9197 { "bound{S|}", { Gv, Ma } },
9198 { "(bad)", { XX } },
9199 },
9200 {
9201 /* MOD_C4_32BIT */
9202 { "lesS", { Gv, Mp } },
9203 { VEX_C4_TABLE (VEX_0F) },
9204 },
9205 {
9206 /* MOD_C5_32BIT */
9207 { "ldsS", { Gv, Mp } },
9208 { VEX_C5_TABLE (VEX_0F) },
9209 },
9210 {
9211 /* MOD_VEX_12_PREFIX_0 */
9212 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
9213 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
9214 },
9215 {
9216 /* MOD_VEX_13 */
9217 { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
9218 { "(bad)", { XX } },
9219 },
9220 {
9221 /* MOD_VEX_16_PREFIX_0 */
9222 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
9223 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
9224 },
9225 {
9226 /* MOD_VEX_17 */
9227 { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
9228 { "(bad)", { XX } },
9229 },
9230 {
9231 /* MOD_VEX_2B */
9232 { VEX_LEN_TABLE (VEX_LEN_2B_M_0) },
9233 { "(bad)", { XX } },
9234 },
9235 {
9236 /* MOD_VEX_51 */
9237 { "(bad)", { XX } },
9238 { "vmovmskpX", { Gdq, XS } },
9239 },
9240 {
9241 /* MOD_VEX_71_REG_2 */
9242 { "(bad)", { XX } },
9243 { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
b844680a
L		 9244 },
9245 {
c0f3af97 9246 /* MOD_VEX_71_REG_4 */
b844680a 9247 { "(bad)", { XX } },
c0f3af97 9248 { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
b844680a
L		 9249 },
9250 {
c0f3af97 9251 /* MOD_VEX_71_REG_6 */
b844680a 9252 { "(bad)", { XX } },
c0f3af97 9253 { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
b844680a
L		 9254 },
9255 {
c0f3af97 9256 /* MOD_VEX_72_REG_2 */
b844680a 9257 { "(bad)", { XX } },
c0f3af97 9258 { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
b844680a 9259 },
d8faab4e 9260 {
c0f3af97 9261 /* MOD_VEX_72_REG_4 */
d8faab4e 9262 { "(bad)", { XX } },
c0f3af97 9263 { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
d8faab4e
L		 9264 },
9265 {
c0f3af97 9266 /* MOD_VEX_72_REG_6 */
d8faab4e 9267 { "(bad)", { XX } },
c0f3af97 9268 { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
d8faab4e 9269 },
876d4bfa 9270 {
c0f3af97 9271 /* MOD_VEX_73_REG_2 */
876d4bfa 9272 { "(bad)", { XX } },
c0f3af97 9273 { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
876d4bfa
L		 9274 },
9275 {
c0f3af97 9276 /* MOD_VEX_73_REG_3 */
876d4bfa 9277 { "(bad)", { XX } },
c0f3af97 9278 { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
475a2301
L		 9279 },
9280 {
c0f3af97
L		 9281 /* MOD_VEX_73_REG_6 */
9282 { "(bad)", { XX } },
9283 { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
876d4bfa
L		 9284 },
9285 {
c0f3af97 9286 /* MOD_VEX_73_REG_7 */
4e7d34a6 9287 { "(bad)", { XX } },
c0f3af97 9288 { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
876d4bfa
L		 9289 },
9290 {
c0f3af97
L		 9291 /* MOD_VEX_AE_REG_2 */
9292 { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
9293 { "(bad)", { XX } },
876d4bfa 9294 },
bbedc832 9295 {
c0f3af97
L		 9296 /* MOD_VEX_AE_REG_3 */
9297 { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
4e7d34a6 9298 { "(bad)", { XX } },
bbedc832 9299 },
144c41d9 9300 {
c0f3af97 9301 /* MOD_VEX_D7_PREFIX_2 */
4e7d34a6 9302 { "(bad)", { XX } },
c0f3af97 9303 { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
144c41d9 9304 },
1afd85e3 9305 {
c0f3af97
L		 9306 /* MOD_VEX_E7_PREFIX_2 */
9307 { VEX_LEN_TABLE (VEX_LEN_E7_P_2_M_0) },
92fddf8e 9308 { "(bad)", { XX } },
1afd85e3
L		 9309 },
9310 {
c0f3af97
L		 9311 /* MOD_VEX_F0_PREFIX_3 */
9312 { "vlddqu", { XM, M } },
92fddf8e
L		 9313 { "(bad)", { XX } },
9314 },
9315 {
c0f3af97
L		 9316 /* MOD_VEX_3818_PREFIX_2 */
9317 { "vbroadcastss", { XM, Md } },
92fddf8e 9318 { "(bad)", { XX } },
1afd85e3 9319 },
75c135a8 9320 {
c0f3af97
L		 9321 /* MOD_VEX_3819_PREFIX_2 */
9322 { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
75c135a8 9323 { "(bad)", { XX } },
75c135a8
L		 9324 },
9325 {
c0f3af97
L		 9326 /* MOD_VEX_381A_PREFIX_2 */
9327 { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
75c135a8
L		 9328 { "(bad)", { XX } },
9329 },
1afd85e3 9330 {
c0f3af97
L		 9331 /* MOD_VEX_382A_PREFIX_2 */
9332 { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
1afd85e3 9333 { "(bad)", { XX } },
1afd85e3 9334 },
75c135a8 9335 {
c0f3af97
L		 9336 /* MOD_VEX_382C_PREFIX_2 */
9337 { "vmaskmovps", { XM, Vex, Mx } },
75c135a8
L		 9338 { "(bad)", { XX } },
9339 },
1afd85e3 9340 {
c0f3af97
L		 9341 /* MOD_VEX_382D_PREFIX_2 */
9342 { "vmaskmovpd", { XM, Vex, Mx } },
1afd85e3 9343 { "(bad)", { XX } },
1afd85e3
L		 9344 },
9345 {
c0f3af97
L		 9346 /* MOD_VEX_382E_PREFIX_2 */
9347 { "vmaskmovps", { Mx, Vex, XM } },
4e7d34a6 9348 { "(bad)", { XX } },
1afd85e3
L		 9349 },
9350 {
c0f3af97
L		 9351 /* MOD_VEX_382F_PREFIX_2 */
9352 { "vmaskmovpd", { Mx, Vex, XM } },
1afd85e3 9353 { "(bad)", { XX } },
1afd85e3 9354 },
b844680a
L		 9355};
9356
1ceb70f8 9357static const struct dis386 rm_table[][8] = {
b844680a 9358 {
1ceb70f8 9359 /* RM_0F01_REG_0 */
b844680a
L		 9360 { "(bad)", { XX } },
9361 { "vmcall", { Skip_MODRM } },
9362 { "vmlaunch", { Skip_MODRM } },
9363 { "vmresume", { Skip_MODRM } },
9364 { "vmxoff", { Skip_MODRM } },
9365 { "(bad)", { XX } },
9366 { "(bad)", { XX } },
9367 { "(bad)", { XX } },
9368 },
9369 {
1ceb70f8 9370 /* RM_0F01_REG_1 */
b844680a
L		 9371 { "monitor", { { OP_Monitor, 0 } } },
9372 { "mwait", { { OP_Mwait, 0 } } },
9373 { "(bad)", { XX } },
9374 { "(bad)", { XX } },
9375 { "(bad)", { XX } },
9376 { "(bad)", { XX } },
9377 { "(bad)", { XX } },
9378 { "(bad)", { XX } },
9379 },
475a2301
L		 9380 {
9381 /* RM_0F01_REG_2 */
9382 { "xgetbv", { Skip_MODRM } },
9383 { "xsetbv", { Skip_MODRM } },
9384 { "(bad)", { XX } },
9385 { "(bad)", { XX } },
9386 { "(bad)", { XX } },
9387 { "(bad)", { XX } },
9388 { "(bad)", { XX } },
9389 { "(bad)", { XX } },
9390 },
b844680a 9391 {
1ceb70f8 9392 /* RM_0F01_REG_3 */
4e7d34a6
L		 9393 { "vmrun", { Skip_MODRM } },
9394 { "vmmcall", { Skip_MODRM } },
9395 { "vmload", { Skip_MODRM } },
9396 { "vmsave", { Skip_MODRM } },
9397 { "stgi", { Skip_MODRM } },
9398 { "clgi", { Skip_MODRM } },
9399 { "skinit", { Skip_MODRM } },
9400 { "invlpga", { Skip_MODRM } },
9401 },
9402 {
1ceb70f8 9403 /* RM_0F01_REG_7 */
4e7d34a6
L		 9404 { "swapgs", { Skip_MODRM } },
9405 { "rdtscp", { Skip_MODRM } },
b844680a
L		 9406 { "(bad)", { XX } },
9407 { "(bad)", { XX } },
9408 { "(bad)", { XX } },
9409 { "(bad)", { XX } },
9410 { "(bad)", { XX } },
9411 { "(bad)", { XX } },
9412 },
9413 {
1ceb70f8 9414 /* RM_0FAE_REG_5 */
4e7d34a6 9415 { "lfence", { Skip_MODRM } },
b844680a
L		 9416 { "(bad)", { XX } },
9417 { "(bad)", { XX } },
9418 { "(bad)", { XX } },
9419 { "(bad)", { XX } },
9420 { "(bad)", { XX } },
9421 { "(bad)", { XX } },
9422 { "(bad)", { XX } },
9423 },
9424 {
1ceb70f8 9425 /* RM_0FAE_REG_6 */
4e7d34a6 9426 { "mfence", { Skip_MODRM } },
b844680a
L		 9427 { "(bad)", { XX } },
9428 { "(bad)", { XX } },
9429 { "(bad)", { XX } },
9430 { "(bad)", { XX } },
9431 { "(bad)", { XX } },
9432 { "(bad)", { XX } },
9433 { "(bad)", { XX } },
9434 },
bbedc832 9435 {
1ceb70f8 9436 /* RM_0FAE_REG_7 */
4e7d34a6
L		 9437 { "sfence", { Skip_MODRM } },
9438 { "(bad)", { XX } },
bbedc832
L		 9439 { "(bad)", { XX } },
9440 { "(bad)", { XX } },
9441 { "(bad)", { XX } },
9442 { "(bad)", { XX } },
9443 { "(bad)", { XX } },
9444 { "(bad)", { XX } },
144c41d9 9445 },
b844680a
L		 9446};
9447
c608c12e
AM		 9448#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
9449
252b5132 9450static void
26ca5450 9451ckprefix (void)
252b5132 9452{
52b15da3
JH		 9453 int newrex;
9454 rex = 0;
c0f3af97
L		 9455 rex_original = 0;
9456 rex_ignored = 0;
252b5132 9457 prefixes = 0;
7d421014 9458 used_prefixes = 0;
52b15da3 9459 rex_used = 0;
252b5132
RH		 9460 while (1)
9461 {
9462 FETCH_DATA (the_info, codep + 1);
52b15da3 9463 newrex = 0;
252b5132
RH		 9464 switch (*codep)
9465 {
52b15da3
JH		 9466 /* REX prefixes family. */
9467 case 0x40:
9468 case 0x41:
9469 case 0x42:
9470 case 0x43:
9471 case 0x44:
9472 case 0x45:
9473 case 0x46:
9474 case 0x47:
9475 case 0x48:
9476 case 0x49:
9477 case 0x4a:
9478 case 0x4b:
9479 case 0x4c:
9480 case 0x4d:
9481 case 0x4e:
9482 case 0x4f:
cb712a9e 9483 if (address_mode == mode_64bit)
52b15da3
JH		 9484 newrex = *codep;
9485 else
9486 return;
9487 break;
252b5132
RH		 9488 case 0xf3:
9489 prefixes |= PREFIX_REPZ;
9490 break;
9491 case 0xf2:
9492 prefixes |= PREFIX_REPNZ;
9493 break;
9494 case 0xf0:
9495 prefixes |= PREFIX_LOCK;
9496 break;
9497 case 0x2e:
9498 prefixes |= PREFIX_CS;
9499 break;
9500 case 0x36:
9501 prefixes |= PREFIX_SS;
9502 break;
9503 case 0x3e:
9504 prefixes |= PREFIX_DS;
9505 break;
9506 case 0x26:
9507 prefixes |= PREFIX_ES;
9508 break;
9509 case 0x64:
9510 prefixes |= PREFIX_FS;
9511 break;
9512 case 0x65:
9513 prefixes |= PREFIX_GS;
9514 break;
9515 case 0x66:
9516 prefixes |= PREFIX_DATA;
9517 break;
9518 case 0x67:
9519 prefixes |= PREFIX_ADDR;
9520 break;
5076851f 9521 case FWAIT_OPCODE:
252b5132
RH		 9522 /* fwait is really an instruction. If there are prefixes
9523 before the fwait, they belong to the fwait, *not* to the
9524 following instruction. */
3e7d61b2 9525 if (prefixes || rex)
252b5132
RH		 9526 {
9527 prefixes |= PREFIX_FWAIT;
9528 codep++;
9529 return;
9530 }
9531 prefixes = PREFIX_FWAIT;
9532 break;
9533 default:
9534 return;
9535 }
52b15da3
JH		 9536 /* Rex is ignored when followed by another prefix. */
9537 if (rex)
9538 {
3e7d61b2
AM		 9539 rex_used = rex;
9540 return;
52b15da3
JH		 9541 }
9542 rex = newrex;
c0f3af97 9543 rex_original = rex;
252b5132
RH		 9544 codep++;
9545 }
9546}
9547
7d421014
ILT		 9548/* Return the name of the prefix byte PREF, or NULL if PREF is not a
9549 prefix byte. */
9550
9551static const char *
26ca5450 9552prefix_name (int pref, int sizeflag)
7d421014 9553{
0003779b
L		 9554 static const char *rexes [16] =
9555 {
9556 "rex", /* 0x40 */
9557 "rex.B", /* 0x41 */
9558 "rex.X", /* 0x42 */
9559 "rex.XB", /* 0x43 */
9560 "rex.R", /* 0x44 */
9561 "rex.RB", /* 0x45 */
9562 "rex.RX", /* 0x46 */
9563 "rex.RXB", /* 0x47 */
9564 "rex.W", /* 0x48 */
9565 "rex.WB", /* 0x49 */
9566 "rex.WX", /* 0x4a */
9567 "rex.WXB", /* 0x4b */
9568 "rex.WR", /* 0x4c */
9569 "rex.WRB", /* 0x4d */
9570 "rex.WRX", /* 0x4e */
9571 "rex.WRXB", /* 0x4f */
9572 };
9573
7d421014
ILT		 9574 switch (pref)
9575 {
52b15da3
JH		 9576 /* REX prefixes family. */
9577 case 0x40:
52b15da3 9578 case 0x41:
52b15da3 9579 case 0x42:
52b15da3 9580 case 0x43:
52b15da3 9581 case 0x44:
52b15da3 9582 case 0x45:
52b15da3 9583 case 0x46:
52b15da3 9584 case 0x47:
52b15da3 9585 case 0x48:
52b15da3 9586 case 0x49:
52b15da3 9587 case 0x4a:
52b15da3 9588 case 0x4b:
52b15da3 9589 case 0x4c:
52b15da3 9590 case 0x4d:
52b15da3 9591 case 0x4e:
52b15da3 9592 case 0x4f:
0003779b 9593 return rexes [pref - 0x40];
7d421014
ILT		 9594 case 0xf3:
9595 return "repz";
9596 case 0xf2:
9597 return "repnz";
9598 case 0xf0:
9599 return "lock";
9600 case 0x2e:
9601 return "cs";
9602 case 0x36:
9603 return "ss";
9604 case 0x3e:
9605 return "ds";
9606 case 0x26:
9607 return "es";
9608 case 0x64:
9609 return "fs";
9610 case 0x65:
9611 return "gs";
9612 case 0x66:
9613 return (sizeflag & DFLAG) ? "data16" : "data32";
9614 case 0x67:
cb712a9e 9615 if (address_mode == mode_64bit)
db6eb5be 9616 return (sizeflag & AFLAG) ? "addr32" : "addr64";
c1a64871 9617 else
2888cb7a 9618 return (sizeflag & AFLAG) ? "addr16" : "addr32";
7d421014
ILT		 9619 case FWAIT_OPCODE:
9620 return "fwait";
9621 default:
9622 return NULL;
9623 }
9624}
9625
ce518a5f
L		 9626static char op_out[MAX_OPERANDS][100];
9627static int op_ad, op_index[MAX_OPERANDS];
1d9f512f 9628static int two_source_ops;
ce518a5f
L		 9629static bfd_vma op_address[MAX_OPERANDS];
9630static bfd_vma op_riprel[MAX_OPERANDS];
52b15da3 9631static bfd_vma start_pc;
ce518a5f 9632
252b5132
RH		 9633/*
9634 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9635 * (see topic "Redundant prefixes" in the "Differences from 8086"
9636 * section of the "Virtual 8086 Mode" chapter.)
9637 * 'pc' should be the address of this instruction, it will
9638 * be used to print the target address if this is a relative jump or call
9639 * The function returns the length of this instruction in bytes.
9640 */
9641
252b5132 9642static char intel_syntax;
9d141669 9643static char intel_mnemonic = !SYSV386_COMPAT;
252b5132
RH		 9644static char open_char;
9645static char close_char;
9646static char separator_char;
9647static char scale_char;
9648
e396998b
AM		 9649/* Here for backwards compatibility. When gdb stops using
9650 print_insn_i386_att and print_insn_i386_intel these functions can
9651 disappear, and print_insn_i386 be merged into print_insn. */
252b5132 9652int
26ca5450 9653print_insn_i386_att (bfd_vma pc, disassemble_info *info)
252b5132
RH		 9654{
9655 intel_syntax = 0;
e396998b
AM		 9656
9657 return print_insn (pc, info);
252b5132
RH		 9658}
9659
9660int
26ca5450 9661print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
252b5132
RH		 9662{
9663 intel_syntax = 1;
e396998b
AM		 9664
9665 return print_insn (pc, info);
252b5132
RH		 9666}
9667
e396998b 9668int
26ca5450 9669print_insn_i386 (bfd_vma pc, disassemble_info *info)
e396998b
AM		 9670{
9671 intel_syntax = -1;
9672
9673 return print_insn (pc, info);
9674}
9675
f59a29b9
L		 9676void
9677print_i386_disassembler_options (FILE *stream)
9678{
9679 fprintf (stream, _("\n\
9680The following i386/x86-64 specific disassembler options are supported for use\n\
9681with the -M switch (multiple options should be separated by commas):\n"));
9682
9683 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
9684 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
9685 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
9686 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
9687 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
9d141669
L		 9688 fprintf (stream, _(" att-mnemonic\n"
9689 " Display instruction in AT&T mnemonic\n"));
9690 fprintf (stream, _(" intel-mnemonic\n"
9691 " Display instruction in Intel mnemonic\n"));
f59a29b9
L		 9692 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
9693 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
9694 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
9695 fprintf (stream, _(" data32 Assume 32bit data size\n"));
9696 fprintf (stream, _(" data16 Assume 16bit data size\n"));
9697 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
9698}
9699
b844680a
L		 9700/* Get a pointer to struct dis386 with a valid name. */
9701
9702static const struct dis386 *
8bb15339 9703get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
b844680a 9704{
c0f3af97 9705 int index, vex_table_index;
b844680a
L		 9706
9707 if (dp->name != NULL)
9708 return dp;
9709
9710 switch (dp->op[0].bytemode)
9711 {
1ceb70f8
L		 9712 case USE_REG_TABLE:
9713 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9714 break;
9715
9716 case USE_MOD_TABLE:
9717 index = modrm.mod == 0x3 ? 1 : 0;
9718 dp = &mod_table[dp->op[1].bytemode][index];
9719 break;
9720
9721 case USE_RM_TABLE:
9722 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
b844680a
L		 9723 break;
9724
4e7d34a6 9725 case USE_PREFIX_TABLE:
c0f3af97 9726 if (need_vex)
b844680a 9727 {
c0f3af97
L		 9728 /* The prefix in VEX is implicit. */
9729 switch (vex.prefix)
9730 {
9731 case 0:
9732 index = 0;
9733 break;
9734 case REPE_PREFIX_OPCODE:
9735 index = 1;
9736 break;
9737 case DATA_PREFIX_OPCODE:
9738 index = 2;
9739 break;
9740 case REPNE_PREFIX_OPCODE:
9741 index = 3;
9742 break;
9743 default:
9744 abort ();
9745 break;
9746 }
b844680a 9747 }
c0f3af97 9748 else
b844680a 9749 {
c0f3af97
L		 9750 index = 0;
9751 used_prefixes |= (prefixes & PREFIX_REPZ);
9752 if (prefixes & PREFIX_REPZ)
b844680a 9753 {
c0f3af97
L		 9754 index = 1;
9755 repz_prefix = NULL;
b844680a
L		 9756 }
9757 else
9758 {
c0f3af97
L		 9759 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
9760 PREFIX_DATA. */
9761 used_prefixes |= (prefixes & PREFIX_REPNZ);
9762 if (prefixes & PREFIX_REPNZ)
9763 {
9764 index = 3;
9765 repnz_prefix = NULL;
9766 }
9767 else
b844680a 9768 {
c0f3af97
L		 9769 used_prefixes |= (prefixes & PREFIX_DATA);
9770 if (prefixes & PREFIX_DATA)
9771 {
9772 index = 2;
9773 data_prefix = NULL;
9774 }
b844680a
L		 9775 }
9776 }
9777 }
1ceb70f8 9778 dp = &prefix_table[dp->op[1].bytemode][index];
b844680a
L		 9779 break;
9780
4e7d34a6 9781 case USE_X86_64_TABLE:
b844680a
L		 9782 index = address_mode == mode_64bit ? 1 : 0;
9783 dp = &x86_64_table[dp->op[1].bytemode][index];
9784 break;
9785
4e7d34a6 9786 case USE_3BYTE_TABLE:
8bb15339
L		 9787 FETCH_DATA (info, codep + 2);
9788 index = *codep++;
9789 dp = &three_byte_table[dp->op[1].bytemode][index];
9790 modrm.mod = (*codep >> 6) & 3;
9791 modrm.reg = (*codep >> 3) & 7;
9792 modrm.rm = *codep & 7;
9793 break;
9794
c0f3af97
L		 9795 case USE_VEX_LEN_TABLE:
9796 if (!need_vex)
9797 abort ();
9798
9799 switch (vex.length)
9800 {
9801 case 128:
9802 index = 0;
9803 break;
9804 case 256:
9805 index = 1;
9806 break;
9807 default:
9808 abort ();
9809 break;
9810 }
9811
9812 dp = &vex_len_table[dp->op[1].bytemode][index];
9813 break;
9814
9815 case USE_VEX_C4_TABLE:
9816 FETCH_DATA (info, codep + 3);
9817 /* All bits in the REX prefix are ignored. */
9818 rex_ignored = rex;
9819 rex = ~(*codep >> 5) & 0x7;
9820 switch ((*codep & 0x1f))
9821 {
9822 default:
9823 BadOp ();
9824 case 0x1:
9825 vex_table_index = 0;
9826 break;
9827 case 0x2:
9828 vex_table_index = 1;
9829 break;
9830 case 0x3:
9831 vex_table_index = 2;
9832 break;
9833 }
9834 codep++;
9835 vex.w = *codep & 0x80;
9836 if (vex.w && address_mode == mode_64bit)
9837 rex |= REX_W;
9838
9839 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9840 if (address_mode != mode_64bit
9841 && vex.register_specifier > 0x7)
9842 BadOp ();
9843
9844 vex.length = (*codep & 0x4) ? 256 : 128;
9845 switch ((*codep & 0x3))
9846 {
9847 case 0:
9848 vex.prefix = 0;
9849 break;
9850 case 1:
9851 vex.prefix = DATA_PREFIX_OPCODE;
9852 break;
9853 case 2:
9854 vex.prefix = REPE_PREFIX_OPCODE;
9855 break;
9856 case 3:
9857 vex.prefix = REPNE_PREFIX_OPCODE;
9858 break;
9859 }
9860 need_vex = 1;
9861 need_vex_reg = 1;
9862 codep++;
9863 index = *codep++;
9864 dp = &vex_table[vex_table_index][index];
9865 /* There is no MODRM byte for VEX [82|77]. */
9866 if (index != 0x77 && index != 0x82)
9867 {
9868 FETCH_DATA (info, codep + 1);
9869 modrm.mod = (*codep >> 6) & 3;
9870 modrm.reg = (*codep >> 3) & 7;
9871 modrm.rm = *codep & 7;
9872 }
9873 break;
9874
9875 case USE_VEX_C5_TABLE:
9876 FETCH_DATA (info, codep + 2);
9877 /* All bits in the REX prefix are ignored. */
9878 rex_ignored = rex;
9879 rex = (*codep & 0x80) ? 0 : REX_R;
9880
9881 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9882 if (address_mode != mode_64bit
9883 && vex.register_specifier > 0x7)
9884 BadOp ();
9885
9886 vex.length = (*codep & 0x4) ? 256 : 128;
9887 switch ((*codep & 0x3))
9888 {
9889 case 0:
9890 vex.prefix = 0;
9891 break;
9892 case 1:
9893 vex.prefix = DATA_PREFIX_OPCODE;
9894 break;
9895 case 2:
9896 vex.prefix = REPE_PREFIX_OPCODE;
9897 break;
9898 case 3:
9899 vex.prefix = REPNE_PREFIX_OPCODE;
9900 break;
9901 }
9902 need_vex = 1;
9903 need_vex_reg = 1;
9904 codep++;
9905 index = *codep++;
9906 dp = &vex_table[dp->op[1].bytemode][index];
9907 /* There is no MODRM byte for VEX [82|77]. */
9908 if (index != 0x77 && index != 0x82)
9909 {
9910 FETCH_DATA (info, codep + 1);
9911 modrm.mod = (*codep >> 6) & 3;
9912 modrm.reg = (*codep >> 3) & 7;
9913 modrm.rm = *codep & 7;
9914 }
9915 break;
9916
b844680a
L		 9917 default:
9918 oappend (INTERNAL_DISASSEMBLER_ERROR);
9919 return NULL;
9920 }
9921
9922 if (dp->name != NULL)
9923 return dp;
9924 else
8bb15339 9925 return get_valid_dis386 (dp, info);
b844680a
L		 9926}
9927
e396998b 9928static int
26ca5450 9929print_insn (bfd_vma pc, disassemble_info *info)
252b5132 9930{
2da11e11 9931 const struct dis386 *dp;
252b5132 9932 int i;
ce518a5f 9933 char *op_txt[MAX_OPERANDS];
252b5132 9934 int needcomma;
e396998b
AM		 9935 int sizeflag;
9936 const char *p;
252b5132 9937 struct dis_private priv;
eec0f4ca 9938 unsigned char op;
b844680a
L		 9939 char prefix_obuf[32];
9940 char *prefix_obufp;
252b5132 9941
cb712a9e
L		 9942 if (info->mach == bfd_mach_x86_64_intel_syntax
9943 || info->mach == bfd_mach_x86_64)
9944 address_mode = mode_64bit;
9945 else
9946 address_mode = mode_32bit;
52b15da3 9947
8373f971 9948 if (intel_syntax == (char) -1)
e396998b
AM		 9949 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
9950 || info->mach == bfd_mach_x86_64_intel_syntax);
9951
2da11e11 9952 if (info->mach == bfd_mach_i386_i386
52b15da3
JH		 9953 || info->mach == bfd_mach_x86_64
9954 || info->mach == bfd_mach_i386_i386_intel_syntax
9955 || info->mach == bfd_mach_x86_64_intel_syntax)
e396998b 9956 priv.orig_sizeflag = AFLAG | DFLAG;
2da11e11 9957 else if (info->mach == bfd_mach_i386_i8086)
e396998b 9958 priv.orig_sizeflag = 0;
2da11e11
AM		 9959 else
9960 abort ();
e396998b
AM		 9961
9962 for (p = info->disassembler_options; p != NULL; )
9963 {
0112cd26 9964 if (CONST_STRNEQ (p, "x86-64"))
e396998b 9965 {
cb712a9e 9966 address_mode = mode_64bit;
e396998b
AM		 9967 priv.orig_sizeflag = AFLAG | DFLAG;
9968 }
0112cd26 9969 else if (CONST_STRNEQ (p, "i386"))
e396998b 9970 {
cb712a9e 9971 address_mode = mode_32bit;
e396998b
AM		 9972 priv.orig_sizeflag = AFLAG | DFLAG;
9973 }
0112cd26 9974 else if (CONST_STRNEQ (p, "i8086"))
e396998b 9975 {
cb712a9e 9976 address_mode = mode_16bit;
e396998b
AM		 9977 priv.orig_sizeflag = 0;
9978 }
0112cd26 9979 else if (CONST_STRNEQ (p, "intel"))
e396998b
AM		 9980 {
9981 intel_syntax = 1;
9d141669
L		 9982 if (CONST_STRNEQ (p + 5, "-mnemonic"))
9983 intel_mnemonic = 1;
e396998b 9984 }
0112cd26 9985 else if (CONST_STRNEQ (p, "att"))
e396998b
AM		 9986 {
9987 intel_syntax = 0;
9d141669
L		 9988 if (CONST_STRNEQ (p + 3, "-mnemonic"))
9989 intel_mnemonic = 0;
e396998b 9990 }
0112cd26 9991 else if (CONST_STRNEQ (p, "addr"))
e396998b 9992 {
f59a29b9
L		 9993 if (address_mode == mode_64bit)
9994 {
9995 if (p[4] == '3' && p[5] == '2')
9996 priv.orig_sizeflag &= ~AFLAG;
9997 else if (p[4] == '6' && p[5] == '4')
9998 priv.orig_sizeflag |= AFLAG;
9999 }
10000 else
10001 {
10002 if (p[4] == '1' && p[5] == '6')
10003 priv.orig_sizeflag &= ~AFLAG;
10004 else if (p[4] == '3' && p[5] == '2')
10005 priv.orig_sizeflag |= AFLAG;
10006 }
e396998b 10007 }
0112cd26 10008 else if (CONST_STRNEQ (p, "data"))
e396998b
AM		 10009 {
10010 if (p[4] == '1' && p[5] == '6')
10011 priv.orig_sizeflag &= ~DFLAG;
10012 else if (p[4] == '3' && p[5] == '2')
10013 priv.orig_sizeflag |= DFLAG;
10014 }
0112cd26 10015 else if (CONST_STRNEQ (p, "suffix"))
e396998b
AM		 10016 priv.orig_sizeflag |= SUFFIX_ALWAYS;
10017
10018 p = strchr (p, ',');
10019 if (p != NULL)
10020 p++;
10021 }
10022
10023 if (intel_syntax)
10024 {
10025 names64 = intel_names64;
10026 names32 = intel_names32;
10027 names16 = intel_names16;
10028 names8 = intel_names8;
10029 names8rex = intel_names8rex;
10030 names_seg = intel_names_seg;
db51cc60
L		 10031 index64 = intel_index64;
10032 index32 = intel_index32;
e396998b
AM		 10033 index16 = intel_index16;
10034 open_char = '[';
10035 close_char = ']';
10036 separator_char = '+';
10037 scale_char = '*';
10038 }
10039 else
10040 {
10041 names64 = att_names64;
10042 names32 = att_names32;
10043 names16 = att_names16;
10044 names8 = att_names8;
10045 names8rex = att_names8rex;
10046 names_seg = att_names_seg;
db51cc60
L		 10047 index64 = att_index64;
10048 index32 = att_index32;
e396998b
AM		 10049 index16 = att_index16;
10050 open_char = '(';
10051 close_char = ')';
10052 separator_char = ',';
10053 scale_char = ',';
10054 }
2da11e11 10055
4fe53c98 10056 /* The output looks better if we put 7 bytes on a line, since that
c608c12e 10057 puts most long word instructions on a single line. */
4fe53c98 10058 info->bytes_per_line = 7;
252b5132 10059
26ca5450 10060 info->private_data = &priv;
252b5132
RH		 10061 priv.max_fetched = priv.the_buffer;
10062 priv.insn_start = pc;
252b5132
RH		 10063
10064 obuf[0] = 0;
ce518a5f
L		 10065 for (i = 0; i < MAX_OPERANDS; ++i)
10066 {
10067 op_out[i][0] = 0;
10068 op_index[i] = -1;
10069 }
252b5132
RH		 10070
10071 the_info = info;
10072 start_pc = pc;
e396998b
AM		 10073 start_codep = priv.the_buffer;
10074 codep = priv.the_buffer;
252b5132 10075
5076851f
ILT		 10076 if (setjmp (priv.bailout) != 0)
10077 {
7d421014
ILT		 10078 const char *name;
10079
5076851f 10080 /* Getting here means we tried for data but didn't get it. That
e396998b
AM		 10081 means we have an incomplete instruction of some sort. Just
10082 print the first byte as a prefix or a .byte pseudo-op. */
10083 if (codep > priv.the_buffer)
5076851f 10084 {
e396998b 10085 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 10086 if (name != NULL)
10087 (*info->fprintf_func) (info->stream, "%s", name);
10088 else
5076851f 10089 {
7d421014
ILT		 10090 /* Just print the first byte as a .byte instruction. */
10091 (*info->fprintf_func) (info->stream, ".byte 0x%x",
e396998b 10092 (unsigned int) priv.the_buffer[0]);
5076851f 10093 }
5076851f 10094
7d421014 10095 return 1;
5076851f
ILT		 10096 }
10097
10098 return -1;
10099 }
10100
52b15da3 10101 obufp = obuf;
252b5132
RH		 10102 ckprefix ();
10103
10104 insn_codep = codep;
e396998b 10105 sizeflag = priv.orig_sizeflag;
252b5132
RH		 10106
10107 FETCH_DATA (info, codep + 1);
10108 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
10109
3e7d61b2
AM		 10110 if (((prefixes & PREFIX_FWAIT)
10111 && ((*codep < 0xd8) || (*codep > 0xdf)))
10112 || (rex && rex_used))
252b5132 10113 {
7d421014
ILT		 10114 const char *name;
10115
3e7d61b2
AM		 10116 /* fwait not followed by floating point instruction, or rex followed
10117 by other prefixes. Print the first prefix. */
e396998b 10118 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 10119 if (name == NULL)
10120 name = INTERNAL_DISASSEMBLER_ERROR;
10121 (*info->fprintf_func) (info->stream, "%s", name);
10122 return 1;
252b5132
RH		 10123 }
10124
eec0f4ca 10125 op = 0;
252b5132
RH		 10126 if (*codep == 0x0f)
10127 {
eec0f4ca 10128 unsigned char threebyte;
252b5132 10129 FETCH_DATA (info, codep + 2);
eec0f4ca
L		 10130 threebyte = *++codep;
10131 dp = &dis386_twobyte[threebyte];
252b5132 10132 need_modrm = twobyte_has_modrm[*codep];
eec0f4ca 10133 codep++;
252b5132
RH		 10134 }
10135 else
10136 {
6439fc28 10137 dp = &dis386[*codep];
252b5132 10138 need_modrm = onebyte_has_modrm[*codep];
eec0f4ca 10139 codep++;
252b5132 10140 }
246c51aa 10141
b844680a 10142 if ((prefixes & PREFIX_REPZ))
7d421014 10143 {
b844680a 10144 repz_prefix = "repz ";
7d421014
ILT		 10145 used_prefixes |= PREFIX_REPZ;
10146 }
b844680a
L		 10147 else
10148 repz_prefix = NULL;
10149
10150 if ((prefixes & PREFIX_REPNZ))
7d421014 10151 {
b844680a 10152 repnz_prefix = "repnz ";
7d421014
ILT		 10153 used_prefixes |= PREFIX_REPNZ;
10154 }
b844680a
L		 10155 else
10156 repnz_prefix = NULL;
050dfa73 10157
b844680a 10158 if ((prefixes & PREFIX_LOCK))
7d421014 10159 {
b844680a 10160 lock_prefix = "lock ";
7d421014
ILT		 10161 used_prefixes |= PREFIX_LOCK;
10162 }
b844680a
L		 10163 else
10164 lock_prefix = NULL;
c608c12e 10165
b844680a 10166 addr_prefix = NULL;
c608c12e
AM		 10167 if (prefixes & PREFIX_ADDR)
10168 {
10169 sizeflag ^= AFLAG;
ce518a5f 10170 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
3ffd33cf 10171 {
cb712a9e 10172 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
b844680a 10173 addr_prefix = "addr32 ";
3ffd33cf 10174 else
b844680a 10175 addr_prefix = "addr16 ";
3ffd33cf
AM		 10176 used_prefixes |= PREFIX_ADDR;
10177 }
10178 }
10179
b844680a
L		 10180 data_prefix = NULL;
10181 if ((prefixes & PREFIX_DATA))
3ffd33cf
AM		 10182 {
10183 sizeflag ^= DFLAG;
ce518a5f
L		 10184 if (dp->op[2].bytemode == cond_jump_mode
10185 && dp->op[0].bytemode == v_mode
6439fc28 10186 && !intel_syntax)
3ffd33cf
AM		 10187 {
10188 if (sizeflag & DFLAG)
b844680a 10189 data_prefix = "data32 ";
3ffd33cf 10190 else
b844680a 10191 data_prefix = "data16 ";
3ffd33cf
AM		 10192 used_prefixes |= PREFIX_DATA;
10193 }
10194 }
10195
8bb15339 10196 if (need_modrm)
252b5132
RH		 10197 {
10198 FETCH_DATA (info, codep + 1);
7967e09e
L		 10199 modrm.mod = (*codep >> 6) & 3;
10200 modrm.reg = (*codep >> 3) & 7;
10201 modrm.rm = *codep & 7;
252b5132
RH		 10202 }
10203
ce518a5f 10204 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
252b5132
RH		 10205 {
10206 dofloat (sizeflag);
10207 }
10208 else
10209 {
c0f3af97
L		 10210 need_vex = 0;
10211 need_vex_reg = 0;
dae39acc 10212 vex_w_done = 0;
8bb15339 10213 dp = get_valid_dis386 (dp, info);
b844680a 10214 if (dp != NULL && putop (dp->name, sizeflag) == 0)
ce518a5f
L		 10215 {
10216 for (i = 0; i < MAX_OPERANDS; ++i)
10217 {
246c51aa 10218 obufp = op_out[i];
ce518a5f
L		 10219 op_ad = MAX_OPERANDS - 1 - i;
10220 if (dp->op[i].rtn)
10221 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
10222 }
6439fc28 10223 }
252b5132
RH		 10224 }
10225
7d421014
ILT		 10226 /* See if any prefixes were not used. If so, print the first one
10227 separately. If we don't do this, we'll wind up printing an
10228 instruction stream which does not precisely correspond to the
10229 bytes we are disassembling. */
10230 if ((prefixes & ~used_prefixes) != 0)
10231 {
10232 const char *name;
10233
e396998b 10234 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 10235 if (name == NULL)
10236 name = INTERNAL_DISASSEMBLER_ERROR;
10237 (*info->fprintf_func) (info->stream, "%s", name);
10238 return 1;
10239 }
c0f3af97 10240 if ((rex_original & ~rex_used) || rex_ignored)
52b15da3
JH		 10241 {
10242 const char *name;
c0f3af97 10243 name = prefix_name (rex_original, priv.orig_sizeflag);
52b15da3
JH		 10244 if (name == NULL)
10245 name = INTERNAL_DISASSEMBLER_ERROR;
10246 (*info->fprintf_func) (info->stream, "%s ", name);
10247 }
7d421014 10248
b844680a
L		 10249 prefix_obuf[0] = 0;
10250 prefix_obufp = prefix_obuf;
10251 if (lock_prefix)
10252 prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
10253 if (repz_prefix)
10254 prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
10255 if (repnz_prefix)
10256 prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
10257 if (addr_prefix)
10258 prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
10259 if (data_prefix)
10260 prefix_obufp = stpcpy (prefix_obufp, data_prefix);
10261
10262 if (prefix_obuf[0] != 0)
10263 (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
10264
252b5132 10265 obufp = obuf + strlen (obuf);
b844680a 10266 for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
252b5132
RH		 10267 oappend (" ");
10268 oappend (" ");
10269 (*info->fprintf_func) (info->stream, "%s", obuf);
10270
10271 /* The enter and bound instructions are printed with operands in the same
10272 order as the intel book; everything else is printed in reverse order. */
2da11e11 10273 if (intel_syntax || two_source_ops)
252b5132 10274 {
185b1163
L		 10275 bfd_vma riprel;
10276
ce518a5f
L		 10277 for (i = 0; i < MAX_OPERANDS; ++i)
10278 op_txt[i] = op_out[i];
246c51aa 10279
ce518a5f
L		 10280 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10281 {
10282 op_ad = op_index[i];
10283 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10284 op_index[MAX_OPERANDS - 1 - i] = op_ad;
185b1163
L		 10285 riprel = op_riprel[i];
10286 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10287 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
ce518a5f 10288 }
252b5132
RH		 10289 }
10290 else
10291 {
ce518a5f
L		 10292 for (i = 0; i < MAX_OPERANDS; ++i)
10293 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
050dfa73
MM		 10294 }
10295
ce518a5f
L		 10296 needcomma = 0;
10297 for (i = 0; i < MAX_OPERANDS; ++i)
10298 if (*op_txt[i])
10299 {
10300 if (needcomma)
10301 (*info->fprintf_func) (info->stream, ",");
10302 if (op_index[i] != -1 && !op_riprel[i])
10303 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
10304 else
10305 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10306 needcomma = 1;
10307 }
050dfa73 10308
ce518a5f 10309 for (i = 0; i < MAX_OPERANDS; i++)
52b15da3
JH		 10310 if (op_index[i] != -1 && op_riprel[i])
10311 {
10312 (*info->fprintf_func) (info->stream, " # ");
10313 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
10314 + op_address[op_index[i]]), info);
185b1163 10315 break;
52b15da3 10316 }
e396998b 10317 return codep - priv.the_buffer;
252b5132
RH		 10318}
10319
6439fc28 10320static const char *float_mem[] = {
252b5132 10321 /* d8 */
7c52e0e8
L		 10322 "fadd{s|}",
10323 "fmul{s|}",
10324 "fcom{s|}",
10325 "fcomp{s|}",
10326 "fsub{s|}",
10327 "fsubr{s|}",
10328 "fdiv{s|}",
10329 "fdivr{s|}",
db6eb5be 10330 /* d9 */
7c52e0e8 10331 "fld{s|}",
252b5132 10332 "(bad)",
7c52e0e8
L		 10333 "fst{s|}",
10334 "fstp{s|}",
9306ca4a 10335 "fldenvIC",
252b5132 10336 "fldcw",
9306ca4a 10337 "fNstenvIC",
252b5132
RH		 10338 "fNstcw",
10339 /* da */
7c52e0e8
L		 10340 "fiadd{l|}",
10341 "fimul{l|}",
10342 "ficom{l|}",
10343 "ficomp{l|}",
10344 "fisub{l|}",
10345 "fisubr{l|}",
10346 "fidiv{l|}",
10347 "fidivr{l|}",
252b5132 10348 /* db */
7c52e0e8
L		 10349 "fild{l|}",
10350 "fisttp{l|}",
10351 "fist{l|}",
10352 "fistp{l|}",
252b5132 10353 "(bad)",
6439fc28 10354 "fld{t||t|}",
252b5132 10355 "(bad)",
6439fc28 10356 "fstp{t||t|}",
252b5132 10357 /* dc */
7c52e0e8
L		 10358 "fadd{l|}",
10359 "fmul{l|}",
10360 "fcom{l|}",
10361 "fcomp{l|}",
10362 "fsub{l|}",
10363 "fsubr{l|}",
10364 "fdiv{l|}",
10365 "fdivr{l|}",
252b5132 10366 /* dd */
7c52e0e8
L		 10367 "fld{l|}",
10368 "fisttp{ll|}",
10369 "fst{l||}",
10370 "fstp{l|}",
9306ca4a 10371 "frstorIC",
252b5132 10372 "(bad)",
9306ca4a 10373 "fNsaveIC",
252b5132
RH		 10374 "fNstsw",
10375 /* de */
10376 "fiadd",
10377 "fimul",
10378 "ficom",
10379 "ficomp",
10380 "fisub",
10381 "fisubr",
10382 "fidiv",
10383 "fidivr",
10384 /* df */
10385 "fild",
ca164297 10386 "fisttp",
252b5132
RH		 10387 "fist",
10388 "fistp",
10389 "fbld",
7c52e0e8 10390 "fild{ll|}",
252b5132 10391 "fbstp",
7c52e0e8 10392 "fistp{ll|}",
1d9f512f
AM		 10393};
10394
10395static const unsigned char float_mem_mode[] = {
10396 /* d8 */
10397 d_mode,
10398 d_mode,
10399 d_mode,
10400 d_mode,
10401 d_mode,
10402 d_mode,
10403 d_mode,
10404 d_mode,
10405 /* d9 */
10406 d_mode,
10407 0,
10408 d_mode,
10409 d_mode,
10410 0,
10411 w_mode,
10412 0,
10413 w_mode,
10414 /* da */
10415 d_mode,
10416 d_mode,
10417 d_mode,
10418 d_mode,
10419 d_mode,
10420 d_mode,
10421 d_mode,
10422 d_mode,
10423 /* db */
10424 d_mode,
10425 d_mode,
10426 d_mode,
10427 d_mode,
10428 0,
9306ca4a 10429 t_mode,
1d9f512f 10430 0,
9306ca4a 10431 t_mode,
1d9f512f
AM		 10432 /* dc */
10433 q_mode,
10434 q_mode,
10435 q_mode,
10436 q_mode,
10437 q_mode,
10438 q_mode,
10439 q_mode,
10440 q_mode,
10441 /* dd */
10442 q_mode,
10443 q_mode,
10444 q_mode,
10445 q_mode,
10446 0,
10447 0,
10448 0,
10449 w_mode,
10450 /* de */
10451 w_mode,
10452 w_mode,
10453 w_mode,
10454 w_mode,
10455 w_mode,
10456 w_mode,
10457 w_mode,
10458 w_mode,
10459 /* df */
10460 w_mode,
10461 w_mode,
10462 w_mode,
10463 w_mode,
9306ca4a 10464 t_mode,
1d9f512f 10465 q_mode,
9306ca4a 10466 t_mode,
1d9f512f 10467 q_mode
252b5132
RH		 10468};
10469
ce518a5f
L		 10470#define ST { OP_ST, 0 }
10471#define STi { OP_STi, 0 }
252b5132 10472
4efba78c
L		 10473#define FGRPd9_2 NULL, { { NULL, 0 } }
10474#define FGRPd9_4 NULL, { { NULL, 1 } }
10475#define FGRPd9_5 NULL, { { NULL, 2 } }
10476#define FGRPd9_6 NULL, { { NULL, 3 } }
10477#define FGRPd9_7 NULL, { { NULL, 4 } }
10478#define FGRPda_5 NULL, { { NULL, 5 } }
10479#define FGRPdb_4 NULL, { { NULL, 6 } }
10480#define FGRPde_3 NULL, { { NULL, 7 } }
10481#define FGRPdf_4 NULL, { { NULL, 8 } }
252b5132 10482
2da11e11 10483static const struct dis386 float_reg[][8] = {
252b5132
RH		 10484 /* d8 */
10485 {
ce518a5f
L		 10486 { "fadd", { ST, STi } },
10487 { "fmul", { ST, STi } },
10488 { "fcom", { STi } },
10489 { "fcomp", { STi } },
10490 { "fsub", { ST, STi } },
10491 { "fsubr", { ST, STi } },
10492 { "fdiv", { ST, STi } },
10493 { "fdivr", { ST, STi } },
252b5132
RH		 10494 },
10495 /* d9 */
10496 {
ce518a5f
L		 10497 { "fld", { STi } },
10498 { "fxch", { STi } },
252b5132 10499 { FGRPd9_2 },
ce518a5f 10500 { "(bad)", { XX } },
252b5132
RH		 10501 { FGRPd9_4 },
10502 { FGRPd9_5 },
10503 { FGRPd9_6 },
10504 { FGRPd9_7 },
10505 },
10506 /* da */
10507 {
ce518a5f
L		 10508 { "fcmovb", { ST, STi } },
10509 { "fcmove", { ST, STi } },
10510 { "fcmovbe",{ ST, STi } },
10511 { "fcmovu", { ST, STi } },
10512 { "(bad)", { XX } },
252b5132 10513 { FGRPda_5 },
ce518a5f
L		 10514 { "(bad)", { XX } },
10515 { "(bad)", { XX } },
252b5132
RH		 10516 },
10517 /* db */
10518 {
ce518a5f
L		 10519 { "fcmovnb",{ ST, STi } },
10520 { "fcmovne",{ ST, STi } },
10521 { "fcmovnbe",{ ST, STi } },
10522 { "fcmovnu",{ ST, STi } },
252b5132 10523 { FGRPdb_4 },
ce518a5f
L		 10524 { "fucomi", { ST, STi } },
10525 { "fcomi", { ST, STi } },
10526 { "(bad)", { XX } },
252b5132
RH		 10527 },
10528 /* dc */
10529 {
ce518a5f
L		 10530 { "fadd", { STi, ST } },
10531 { "fmul", { STi, ST } },
10532 { "(bad)", { XX } },
10533 { "(bad)", { XX } },
9d141669
L		 10534 { "fsub!M", { STi, ST } },
10535 { "fsubM", { STi, ST } },
10536 { "fdiv!M", { STi, ST } },
10537 { "fdivM", { STi, ST } },
252b5132
RH		 10538 },
10539 /* dd */
10540 {
ce518a5f
L		 10541 { "ffree", { STi } },
10542 { "(bad)", { XX } },
10543 { "fst", { STi } },
10544 { "fstp", { STi } },
10545 { "fucom", { STi } },
10546 { "fucomp", { STi } },
10547 { "(bad)", { XX } },
10548 { "(bad)", { XX } },
252b5132
RH		 10549 },
10550 /* de */
10551 {
ce518a5f
L		 10552 { "faddp", { STi, ST } },
10553 { "fmulp", { STi, ST } },
10554 { "(bad)", { XX } },
252b5132 10555 { FGRPde_3 },
9d141669
L		 10556 { "fsub!Mp", { STi, ST } },
10557 { "fsubMp", { STi, ST } },
10558 { "fdiv!Mp", { STi, ST } },
10559 { "fdivMp", { STi, ST } },
252b5132
RH		 10560 },
10561 /* df */
10562 {
ce518a5f
L		 10563 { "ffreep", { STi } },
10564 { "(bad)", { XX } },
10565 { "(bad)", { XX } },
10566 { "(bad)", { XX } },
252b5132 10567 { FGRPdf_4 },
ce518a5f
L		 10568 { "fucomip", { ST, STi } },
10569 { "fcomip", { ST, STi } },
10570 { "(bad)", { XX } },
252b5132
RH		 10571 },
10572};
10573
252b5132
RH		 10574static char *fgrps[][8] = {
10575 /* d9_2 0 */
10576 {
10577 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10578 },
10579
10580 /* d9_4 1 */
10581 {
10582 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10583 },
10584
10585 /* d9_5 2 */
10586 {
10587 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10588 },
10589
10590 /* d9_6 3 */
10591 {
10592 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10593 },
10594
10595 /* d9_7 4 */
10596 {
10597 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10598 },
10599
10600 /* da_5 5 */
10601 {
10602 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10603 },
10604
10605 /* db_4 6 */
10606 {
10607 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
10608 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
10609 },
10610
10611 /* de_3 7 */
10612 {
10613 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10614 },
10615
10616 /* df_4 8 */
10617 {
10618 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10619 },
10620};
10621
b844680a
L		 10622static void
10623OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10624 int sizeflag ATTRIBUTE_UNUSED)
10625{
10626 /* Skip mod/rm byte. */
10627 MODRM_CHECK;
10628 codep++;
10629}
10630
252b5132 10631static void
26ca5450 10632dofloat (int sizeflag)
252b5132 10633{
2da11e11 10634 const struct dis386 *dp;
252b5132
RH		 10635 unsigned char floatop;
10636
10637 floatop = codep[-1];
10638
7967e09e 10639 if (modrm.mod != 3)
252b5132 10640 {
7967e09e 10641 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
1d9f512f
AM		 10642
10643 putop (float_mem[fp_indx], sizeflag);
ce518a5f 10644 obufp = op_out[0];
6e50d963 10645 op_ad = 2;
1d9f512f 10646 OP_E (float_mem_mode[fp_indx], sizeflag);
252b5132
RH		 10647 return;
10648 }
6608db57 10649 /* Skip mod/rm byte. */
4bba6815 10650 MODRM_CHECK;
252b5132
RH		 10651 codep++;
10652
7967e09e 10653 dp = &float_reg[floatop - 0xd8][modrm.reg];
252b5132
RH		 10654 if (dp->name == NULL)
10655 {
7967e09e 10656 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
252b5132 10657
6608db57 10658 /* Instruction fnstsw is only one with strange arg. */
252b5132 10659 if (floatop == 0xdf && codep[-1] == 0xe0)
ce518a5f 10660 strcpy (op_out[0], names16[0]);
252b5132
RH		 10661 }
10662 else
10663 {
10664 putop (dp->name, sizeflag);
10665
ce518a5f 10666 obufp = op_out[0];
6e50d963 10667 op_ad = 2;
ce518a5f
L		 10668 if (dp->op[0].rtn)
10669 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
6e50d963 10670
ce518a5f 10671 obufp = op_out[1];
6e50d963 10672 op_ad = 1;
ce518a5f
L		 10673 if (dp->op[1].rtn)
10674 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
252b5132
RH		 10675 }
10676}
10677
252b5132 10678static void
26ca5450 10679OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 10680{
422673a9 10681 oappend ("%st" + intel_syntax);
252b5132
RH		 10682}
10683
252b5132 10684static void
26ca5450 10685OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 10686{
7967e09e 10687 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
d708bcba 10688 oappend (scratchbuf + intel_syntax);
252b5132
RH		 10689}
10690
6608db57 10691/* Capital letters in template are macros. */
6439fc28 10692static int
26ca5450 10693putop (const char *template, int sizeflag)
252b5132 10694{
2da11e11 10695 const char *p;
9306ca4a 10696 int alt = 0;
9d141669 10697 int cond = 1;
98b528ac
L		 10698 unsigned int l = 0, len = 1;
10699 char last[4];
10700
10701#define SAVE_LAST(c) \
10702 if (l < len && l < sizeof (last)) \
10703 last[l++] = c; \
10704 else \
10705 abort ();
252b5132
RH		 10706
10707 for (p = template; *p; p++)
10708 {
10709 switch (*p)
10710 {
10711 default:
10712 *obufp++ = *p;
10713 break;
98b528ac
L		 10714 case '%':
10715 len++;
10716 break;
9d141669
L		 10717 case '!':
10718 cond = 0;
10719 break;
6439fc28
AM		 10720 case '{':
10721 alt = 0;
10722 if (intel_syntax)
6439fc28
AM		 10723 {
10724 while (*++p != '|')
7c52e0e8
L		 10725 if (*p == '}' || *p == '\0')
10726 abort ();
6439fc28 10727 }
9306ca4a
JB		 10728 /* Fall through. */
10729 case 'I':
10730 alt = 1;
10731 continue;
6439fc28
AM		 10732 case '|':
10733 while (*++p != '}')
10734 {
10735 if (*p == '\0')
10736 abort ();
10737 }
10738 break;
10739 case '}':
10740 break;
252b5132 10741 case 'A':
db6eb5be
AM		 10742 if (intel_syntax)
10743 break;
7967e09e 10744 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
252b5132
RH		 10745 *obufp++ = 'b';
10746 break;
10747 case 'B':
db6eb5be
AM		 10748 if (intel_syntax)
10749 break;
252b5132
RH		 10750 if (sizeflag & SUFFIX_ALWAYS)
10751 *obufp++ = 'b';
252b5132 10752 break;
9306ca4a
JB		 10753 case 'C':
10754 if (intel_syntax && !alt)
10755 break;
10756 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10757 {
10758 if (sizeflag & DFLAG)
10759 *obufp++ = intel_syntax ? 'd' : 'l';
10760 else
10761 *obufp++ = intel_syntax ? 'w' : 's';
10762 used_prefixes |= (prefixes & PREFIX_DATA);
10763 }
10764 break;
ed7841b3
JB		 10765 case 'D':
10766 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10767 break;
161a04f6 10768 USED_REX (REX_W);
7967e09e 10769 if (modrm.mod == 3)
ed7841b3 10770 {
161a04f6 10771 if (rex & REX_W)
ed7841b3
JB		 10772 *obufp++ = 'q';
10773 else if (sizeflag & DFLAG)
10774 *obufp++ = intel_syntax ? 'd' : 'l';
10775 else
10776 *obufp++ = 'w';
10777 used_prefixes |= (prefixes & PREFIX_DATA);
10778 }
10779 else
10780 *obufp++ = 'w';
10781 break;
252b5132 10782 case 'E': /* For jcxz/jecxz */
cb712a9e 10783 if (address_mode == mode_64bit)
c1a64871
JH		 10784 {
10785 if (sizeflag & AFLAG)
10786 *obufp++ = 'r';
10787 else
10788 *obufp++ = 'e';
10789 }
10790 else
10791 if (sizeflag & AFLAG)
10792 *obufp++ = 'e';
3ffd33cf
AM		 10793 used_prefixes |= (prefixes & PREFIX_ADDR);
10794 break;
10795 case 'F':
db6eb5be
AM		 10796 if (intel_syntax)
10797 break;
e396998b 10798 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
3ffd33cf
AM		 10799 {
10800 if (sizeflag & AFLAG)
cb712a9e 10801 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
3ffd33cf 10802 else
cb712a9e 10803 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
3ffd33cf
AM		 10804 used_prefixes |= (prefixes & PREFIX_ADDR);
10805 }
252b5132 10806 break;
52fd6d94
JB		 10807 case 'G':
10808 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10809 break;
161a04f6 10810 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 10811 *obufp++ = 'l';
10812 else
10813 *obufp++ = 'w';
161a04f6 10814 if (!(rex & REX_W))
52fd6d94
JB		 10815 used_prefixes |= (prefixes & PREFIX_DATA);
10816 break;
5dd0794d 10817 case 'H':
db6eb5be
AM		 10818 if (intel_syntax)
10819 break;
5dd0794d
AM		 10820 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10821 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10822 {
10823 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10824 *obufp++ = ',';
10825 *obufp++ = 'p';
10826 if (prefixes & PREFIX_DS)
10827 *obufp++ = 't';
10828 else
10829 *obufp++ = 'n';
10830 }
10831 break;
9306ca4a
JB		 10832 case 'J':
10833 if (intel_syntax)
10834 break;
10835 *obufp++ = 'l';
10836 break;
42903f7f
L		 10837 case 'K':
10838 USED_REX (REX_W);
10839 if (rex & REX_W)
10840 *obufp++ = 'q';
10841 else
10842 *obufp++ = 'd';
10843 break;
6dd5059a
L		 10844 case 'Z':
10845 if (intel_syntax)
10846 break;
10847 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
10848 {
10849 *obufp++ = 'q';
10850 break;
10851 }
10852 /* Fall through. */
98b528ac 10853 goto case_L;
252b5132 10854 case 'L':
98b528ac
L		 10855 if (l != 0 || len != 1)
10856 {
10857 SAVE_LAST (*p);
10858 break;
10859 }
10860case_L:
db6eb5be
AM		 10861 if (intel_syntax)
10862 break;
252b5132
RH		 10863 if (sizeflag & SUFFIX_ALWAYS)
10864 *obufp++ = 'l';
252b5132 10865 break;
9d141669
L		 10866 case 'M':
10867 if (intel_mnemonic != cond)
10868 *obufp++ = 'r';
10869 break;
252b5132
RH		 10870 case 'N':
10871 if ((prefixes & PREFIX_FWAIT) == 0)
10872 *obufp++ = 'n';
7d421014
ILT		 10873 else
10874 used_prefixes |= PREFIX_FWAIT;
252b5132 10875 break;
52b15da3 10876 case 'O':
161a04f6
L		 10877 USED_REX (REX_W);
10878 if (rex & REX_W)
6439fc28 10879 *obufp++ = 'o';
a35ca55a
JB		 10880 else if (intel_syntax && (sizeflag & DFLAG))
10881 *obufp++ = 'q';
52b15da3
JH		 10882 else
10883 *obufp++ = 'd';
161a04f6 10884 if (!(rex & REX_W))
a35ca55a 10885 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 10886 break;
6439fc28 10887 case 'T':
db6eb5be
AM		 10888 if (intel_syntax)
10889 break;
cb712a9e 10890 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 10891 {
10892 *obufp++ = 'q';
10893 break;
10894 }
6608db57 10895 /* Fall through. */
252b5132 10896 case 'P':
db6eb5be
AM		 10897 if (intel_syntax)
10898 break;
252b5132 10899 if ((prefixes & PREFIX_DATA)
161a04f6 10900 || (rex & REX_W)
e396998b 10901 || (sizeflag & SUFFIX_ALWAYS))
252b5132 10902 {
161a04f6
L		 10903 USED_REX (REX_W);
10904 if (rex & REX_W)
52b15da3 10905 *obufp++ = 'q';
c2419411 10906 else
52b15da3
JH		 10907 {
10908 if (sizeflag & DFLAG)
10909 *obufp++ = 'l';
10910 else
10911 *obufp++ = 'w';
52b15da3 10912 }
1a114b12 10913 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 10914 }
10915 break;
6439fc28 10916 case 'U':
db6eb5be
AM		 10917 if (intel_syntax)
10918 break;
cb712a9e 10919 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28 10920 {
7967e09e 10921 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
1a114b12 10922 *obufp++ = 'q';
6439fc28
AM		 10923 break;
10924 }
6608db57 10925 /* Fall through. */
98b528ac 10926 goto case_Q;
252b5132 10927 case 'Q':
98b528ac 10928 if (l == 0 && len == 1)
252b5132 10929 {
98b528ac
L		 10930case_Q:
10931 if (intel_syntax && !alt)
10932 break;
10933 USED_REX (REX_W);
10934 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
52b15da3 10935 {
98b528ac
L		 10936 if (rex & REX_W)
10937 *obufp++ = 'q';
52b15da3 10938 else
98b528ac
L		 10939 {
10940 if (sizeflag & DFLAG)
10941 *obufp++ = intel_syntax ? 'd' : 'l';
10942 else
10943 *obufp++ = 'w';
10944 }
10945 used_prefixes |= (prefixes & PREFIX_DATA);
52b15da3 10946 }
98b528ac
L		 10947 }
10948 else
10949 {
10950 if (l != 1 || len != 2 || last[0] != 'L')
10951 {
10952 SAVE_LAST (*p);
10953 break;
10954 }
10955 if (intel_syntax
10956 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
10957 break;
10958 if ((rex & REX_W))
10959 {
10960 USED_REX (REX_W);
10961 *obufp++ = 'q';
10962 }
10963 else
10964 *obufp++ = 'l';
252b5132
RH		 10965 }
10966 break;
10967 case 'R':
161a04f6
L		 10968 USED_REX (REX_W);
10969 if (rex & REX_W)
a35ca55a
JB		 10970 *obufp++ = 'q';
10971 else if (sizeflag & DFLAG)
c608c12e 10972 {
a35ca55a 10973 if (intel_syntax)
c608c12e 10974 *obufp++ = 'd';
c608c12e 10975 else
a35ca55a 10976 *obufp++ = 'l';
c608c12e 10977 }
252b5132 10978 else
a35ca55a
JB		 10979 *obufp++ = 'w';
10980 if (intel_syntax && !p[1]
161a04f6 10981 && ((rex & REX_W) || (sizeflag & DFLAG)))
a35ca55a 10982 *obufp++ = 'e';
161a04f6 10983 if (!(rex & REX_W))
52b15da3 10984 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 10985 break;
1a114b12
JB		 10986 case 'V':
10987 if (intel_syntax)
10988 break;
cb712a9e 10989 if (address_mode == mode_64bit && (sizeflag & DFLAG))
1a114b12
JB		 10990 {
10991 if (sizeflag & SUFFIX_ALWAYS)
10992 *obufp++ = 'q';
10993 break;
10994 }
10995 /* Fall through. */
252b5132 10996 case 'S':
db6eb5be
AM		 10997 if (intel_syntax)
10998 break;
252b5132
RH		 10999 if (sizeflag & SUFFIX_ALWAYS)
11000 {
161a04f6 11001 if (rex & REX_W)
52b15da3 11002 *obufp++ = 'q';
252b5132 11003 else
52b15da3
JH		 11004 {
11005 if (sizeflag & DFLAG)
11006 *obufp++ = 'l';
11007 else
11008 *obufp++ = 'w';
11009 used_prefixes |= (prefixes & PREFIX_DATA);
11010 }
252b5132 11011 }
252b5132 11012 break;
041bd2e0 11013 case 'X':
c0f3af97
L		 11014 if (l != 0 || len != 1)
11015 {
11016 SAVE_LAST (*p);
11017 break;
11018 }
11019 if (need_vex && vex.prefix)
11020 {
11021 if (vex.prefix == DATA_PREFIX_OPCODE)
11022 *obufp++ = 'd';
11023 else
11024 *obufp++ = 's';
11025 }
11026 else if (prefixes & PREFIX_DATA)
041bd2e0
JH		 11027 *obufp++ = 'd';
11028 else
11029 *obufp++ = 's';
db6eb5be 11030 used_prefixes |= (prefixes & PREFIX_DATA);
041bd2e0 11031 break;
76f227a5 11032 case 'Y':
c0f3af97 11033 if (l == 0 && len == 1)
76f227a5 11034 {
c0f3af97
L		 11035 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
11036 break;
11037 if (rex & REX_W)
11038 {
11039 USED_REX (REX_W);
11040 *obufp++ = 'q';
11041 }
11042 break;
11043 }
11044 else
11045 {
11046 if (l != 1 || len != 2 || last[0] != 'X')
11047 {
11048 SAVE_LAST (*p);
11049 break;
11050 }
11051 if (!need_vex)
11052 abort ();
11053 if (intel_syntax
11054 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11055 break;
11056 switch (vex.length)
11057 {
11058 case 128:
11059 *obufp++ = 'x';
11060 break;
11061 case 256:
11062 *obufp++ = 'y';
11063 break;
11064 default:
11065 abort ();
11066 }
76f227a5
JH		 11067 }
11068 break;
52b15da3 11069 /* implicit operand size 'l' for i386 or 'q' for x86-64 */
252b5132 11070 case 'W':
252b5132 11071 /* operand size flag for cwtl, cbtw */
161a04f6
L		 11072 USED_REX (REX_W);
11073 if (rex & REX_W)
a35ca55a
JB		 11074 {
11075 if (intel_syntax)
11076 *obufp++ = 'd';
11077 else
11078 *obufp++ = 'l';
11079 }
52b15da3 11080 else if (sizeflag & DFLAG)
252b5132
RH		 11081 *obufp++ = 'w';
11082 else
11083 *obufp++ = 'b';
161a04f6 11084 if (!(rex & REX_W))
52b15da3 11085 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 11086 break;
11087 }
9306ca4a 11088 alt = 0;
252b5132
RH		 11089 }
11090 *obufp = 0;
6439fc28 11091 return 0;
252b5132
RH		 11092}
11093
11094static void
26ca5450 11095oappend (const char *s)
252b5132
RH		 11096{
11097 strcpy (obufp, s);
11098 obufp += strlen (s);
11099}
11100
11101static void
26ca5450 11102append_seg (void)
252b5132
RH		 11103{
11104 if (prefixes & PREFIX_CS)
7d421014 11105 {
7d421014 11106 used_prefixes |= PREFIX_CS;
d708bcba 11107 oappend ("%cs:" + intel_syntax);
7d421014 11108 }
252b5132 11109 if (prefixes & PREFIX_DS)
7d421014 11110 {
7d421014 11111 used_prefixes |= PREFIX_DS;
d708bcba 11112 oappend ("%ds:" + intel_syntax);
7d421014 11113 }
252b5132 11114 if (prefixes & PREFIX_SS)
7d421014 11115 {
7d421014 11116 used_prefixes |= PREFIX_SS;
d708bcba 11117 oappend ("%ss:" + intel_syntax);
7d421014 11118 }
252b5132 11119 if (prefixes & PREFIX_ES)
7d421014 11120 {
7d421014 11121 used_prefixes |= PREFIX_ES;
d708bcba 11122 oappend ("%es:" + intel_syntax);
7d421014 11123 }
252b5132 11124 if (prefixes & PREFIX_FS)
7d421014 11125 {
7d421014 11126 used_prefixes |= PREFIX_FS;
d708bcba 11127 oappend ("%fs:" + intel_syntax);
7d421014 11128 }
252b5132 11129 if (prefixes & PREFIX_GS)
7d421014 11130 {
7d421014 11131 used_prefixes |= PREFIX_GS;
d708bcba 11132 oappend ("%gs:" + intel_syntax);
7d421014 11133 }
252b5132
RH		 11134}
11135
11136static void
26ca5450 11137OP_indirE (int bytemode, int sizeflag)
252b5132
RH		 11138{
11139 if (!intel_syntax)
11140 oappend ("*");
11141 OP_E (bytemode, sizeflag);
11142}
11143
52b15da3 11144static void
26ca5450 11145print_operand_value (char *buf, int hex, bfd_vma disp)
52b15da3 11146{
cb712a9e 11147 if (address_mode == mode_64bit)
52b15da3
JH		 11148 {
11149 if (hex)
11150 {
11151 char tmp[30];
11152 int i;
11153 buf[0] = '0';
11154 buf[1] = 'x';
11155 sprintf_vma (tmp, disp);
6608db57 11156 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
52b15da3
JH		 11157 strcpy (buf + 2, tmp + i);
11158 }
11159 else
11160 {
11161 bfd_signed_vma v = disp;
11162 char tmp[30];
11163 int i;
11164 if (v < 0)
11165 {
11166 *(buf++) = '-';
11167 v = -disp;
6608db57 11168 /* Check for possible overflow on 0x8000000000000000. */
52b15da3
JH		 11169 if (v < 0)
11170 {
11171 strcpy (buf, "9223372036854775808");
11172 return;
11173 }
11174 }
11175 if (!v)
11176 {
11177 strcpy (buf, "0");
11178 return;
11179 }
11180
11181 i = 0;
11182 tmp[29] = 0;
11183 while (v)
11184 {
6608db57 11185 tmp[28 - i] = (v % 10) + '0';
52b15da3
JH		 11186 v /= 10;
11187 i++;
11188 }
11189 strcpy (buf, tmp + 29 - i);
11190 }
11191 }
11192 else
11193 {
11194 if (hex)
11195 sprintf (buf, "0x%x", (unsigned int) disp);
11196 else
11197 sprintf (buf, "%d", (int) disp);
11198 }
11199}
11200
5d669648
L		 11201/* Put DISP in BUF as signed hex number. */
11202
11203static void
11204print_displacement (char *buf, bfd_vma disp)
11205{
11206 bfd_signed_vma val = disp;
11207 char tmp[30];
11208 int i, j = 0;
11209
11210 if (val < 0)
11211 {
11212 buf[j++] = '-';
11213 val = -disp;
11214
11215 /* Check for possible overflow. */
11216 if (val < 0)
11217 {
11218 switch (address_mode)
11219 {
11220 case mode_64bit:
11221 strcpy (buf + j, "0x8000000000000000");
11222 break;
11223 case mode_32bit:
11224 strcpy (buf + j, "0x80000000");
11225 break;
11226 case mode_16bit:
11227 strcpy (buf + j, "0x8000");
11228 break;
11229 }
11230 return;
11231 }
11232 }
11233
11234 buf[j++] = '0';
11235 buf[j++] = 'x';
11236
11237 sprintf_vma (tmp, val);
11238 for (i = 0; tmp[i] == '0'; i++)
11239 continue;
11240 if (tmp[i] == '\0')
11241 i--;
11242 strcpy (buf + j, tmp + i);
11243}
11244
3f31e633
JB		 11245static void
11246intel_operand_size (int bytemode, int sizeflag)
11247{
11248 switch (bytemode)
11249 {
11250 case b_mode:
42903f7f 11251 case dqb_mode:
3f31e633
JB		 11252 oappend ("BYTE PTR ");
11253 break;
11254 case w_mode:
11255 case dqw_mode:
11256 oappend ("WORD PTR ");
11257 break;
1a114b12 11258 case stack_v_mode:
cb712a9e 11259 if (address_mode == mode_64bit && (sizeflag & DFLAG))
3f31e633
JB		 11260 {
11261 oappend ("QWORD PTR ");
11262 used_prefixes |= (prefixes & PREFIX_DATA);
11263 break;
11264 }
11265 /* FALLTHRU */
11266 case v_mode:
11267 case dq_mode:
161a04f6
L		 11268 USED_REX (REX_W);
11269 if (rex & REX_W)
3f31e633
JB		 11270 oappend ("QWORD PTR ");
11271 else if ((sizeflag & DFLAG) || bytemode == dq_mode)
11272 oappend ("DWORD PTR ");
11273 else
11274 oappend ("WORD PTR ");
11275 used_prefixes |= (prefixes & PREFIX_DATA);
11276 break;
52fd6d94 11277 case z_mode:
161a04f6 11278 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 11279 *obufp++ = 'D';
11280 oappend ("WORD PTR ");
161a04f6 11281 if (!(rex & REX_W))
52fd6d94
JB		 11282 used_prefixes |= (prefixes & PREFIX_DATA);
11283 break;
34b772a6
JB		 11284 case a_mode:
11285 if (sizeflag & DFLAG)
11286 oappend ("QWORD PTR ");
11287 else
11288 oappend ("DWORD PTR ");
11289 used_prefixes |= (prefixes & PREFIX_DATA);
11290 break;
3f31e633 11291 case d_mode:
42903f7f 11292 case dqd_mode:
3f31e633
JB		 11293 oappend ("DWORD PTR ");
11294 break;
11295 case q_mode:
11296 oappend ("QWORD PTR ");
11297 break;
11298 case m_mode:
cb712a9e 11299 if (address_mode == mode_64bit)
3f31e633
JB		 11300 oappend ("QWORD PTR ");
11301 else
11302 oappend ("DWORD PTR ");
11303 break;
11304 case f_mode:
11305 if (sizeflag & DFLAG)
11306 oappend ("FWORD PTR ");
11307 else
11308 oappend ("DWORD PTR ");
11309 used_prefixes |= (prefixes & PREFIX_DATA);
11310 break;
11311 case t_mode:
11312 oappend ("TBYTE PTR ");
11313 break;
11314 case x_mode:
c0f3af97
L		 11315 if (need_vex)
11316 {
11317 switch (vex.length)
11318 {
11319 case 128:
11320 oappend ("XMMWORD PTR ");
11321 break;
11322 case 256:
11323 oappend ("YMMWORD PTR ");
11324 break;
11325 default:
11326 abort ();
11327 }
11328 }
11329 else
11330 oappend ("XMMWORD PTR ");
11331 break;
11332 case xmm_mode:
3f31e633
JB		 11333 oappend ("XMMWORD PTR ");
11334 break;
c0f3af97
L		 11335 case xmmq_mode:
11336 if (!need_vex)
11337 abort ();
11338
11339 switch (vex.length)
11340 {
11341 case 128:
11342 oappend ("QWORD PTR ");
11343 break;
11344 case 256:
11345 oappend ("XMMWORD PTR ");
11346 break;
11347 default:
11348 abort ();
11349 }
11350 break;
11351 case ymmq_mode:
11352 if (!need_vex)
11353 abort ();
11354
11355 switch (vex.length)
11356 {
11357 case 128:
11358 oappend ("QWORD PTR ");
11359 break;
11360 case 256:
11361 oappend ("YMMWORD PTR ");
11362 break;
11363 default:
11364 abort ();
11365 }
11366 break;
fb9c77c7
L		 11367 case o_mode:
11368 oappend ("OWORD PTR ");
11369 break;
3f31e633
JB		 11370 default:
11371 break;
11372 }
11373}
11374
252b5132 11375static void
c0f3af97 11376OP_E_register (int bytemode, int sizeflag)
252b5132 11377{
c0f3af97
L		 11378 int reg = modrm.rm;
11379 const char **names;
252b5132 11380
c0f3af97
L		 11381 USED_REX (REX_B);
11382 if ((rex & REX_B))
11383 reg += 8;
252b5132 11384
c0f3af97 11385 switch (bytemode)
252b5132 11386 {
c0f3af97
L		 11387 case b_mode:
11388 USED_REX (0);
11389 if (rex)
11390 names = names8rex;
11391 else
11392 names = names8;
11393 break;
11394 case w_mode:
11395 names = names16;
11396 break;
11397 case d_mode:
11398 names = names32;
11399 break;
11400 case q_mode:
11401 names = names64;
11402 break;
11403 case m_mode:
11404 names = address_mode == mode_64bit ? names64 : names32;
11405 break;
11406 case stack_v_mode:
11407 if (address_mode == mode_64bit && (sizeflag & DFLAG))
252b5132 11408 {
c0f3af97 11409 names = names64;
7d421014 11410 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 11411 break;
252b5132 11412 }
c0f3af97
L		 11413 bytemode = v_mode;
11414 /* FALLTHRU */
11415 case v_mode:
11416 case dq_mode:
11417 case dqb_mode:
11418 case dqd_mode:
11419 case dqw_mode:
11420 USED_REX (REX_W);
11421 if (rex & REX_W)
11422 names = names64;
11423 else if ((sizeflag & DFLAG) || bytemode != v_mode)
11424 names = names32;
11425 else
11426 names = names16;
11427 used_prefixes |= (prefixes & PREFIX_DATA);
11428 break;
11429 case 0:
11430 return;
11431 default:
11432 oappend (INTERNAL_DISASSEMBLER_ERROR);
252b5132
RH		 11433 return;
11434 }
c0f3af97
L		 11435 oappend (names[reg]);
11436}
11437
11438static void
11439OP_E_memory (int bytemode, int sizeflag, int has_drex)
11440{
11441 bfd_vma disp = 0;
11442 int add = (rex & REX_B) ? 8 : 0;
11443 int riprel = 0;
252b5132 11444
c0f3af97 11445 USED_REX (REX_B);
3f31e633
JB		 11446 if (intel_syntax)
11447 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 11448 append_seg ();
11449
5d669648 11450 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132 11451 {
5d669648
L		 11452 /* 32/64 bit address mode */
11453 int havedisp;
252b5132
RH		 11454 int havesib;
11455 int havebase;
0f7da397 11456 int haveindex;
20afcfb7 11457 int needindex;
82c18208 11458 int base, rbase;
252b5132
RH		 11459 int index = 0;
11460 int scale = 0;
11461
11462 havesib = 0;
11463 havebase = 1;
0f7da397 11464 haveindex = 0;
7967e09e 11465 base = modrm.rm;
252b5132
RH		 11466
11467 if (base == 4)
11468 {
11469 havesib = 1;
11470 FETCH_DATA (the_info, codep + 1);
252b5132 11471 index = (*codep >> 3) & 7;
db51cc60 11472 scale = (*codep >> 6) & 3;
252b5132 11473 base = *codep & 7;
161a04f6
L		 11474 USED_REX (REX_X);
11475 if (rex & REX_X)
52b15da3 11476 index += 8;
0f7da397 11477 haveindex = index != 4;
252b5132
RH		 11478 codep++;
11479 }
82c18208 11480 rbase = base + add;
252b5132 11481
85f10a01
MM		 11482 /* If we have a DREX byte, skip it now
11483 (it has already been handled) */
11484 if (has_drex)
11485 {
11486 FETCH_DATA (the_info, codep + 1);
11487 codep++;
11488 }
11489
7967e09e 11490 switch (modrm.mod)
252b5132
RH		 11491 {
11492 case 0:
82c18208 11493 if (base == 5)
252b5132
RH		 11494 {
11495 havebase = 0;
cb712a9e 11496 if (address_mode == mode_64bit && !havesib)
52b15da3
JH		 11497 riprel = 1;
11498 disp = get32s ();
252b5132
RH		 11499 }
11500 break;
11501 case 1:
11502 FETCH_DATA (the_info, codep + 1);
11503 disp = *codep++;
11504 if ((disp & 0x80) != 0)
11505 disp -= 0x100;
11506 break;
11507 case 2:
52b15da3 11508 disp = get32s ();
252b5132
RH		 11509 break;
11510 }
11511
20afcfb7
L		 11512 /* In 32bit mode, we need index register to tell [offset] from
11513 [eiz*1 + offset]. */
11514 needindex = (havesib
11515 && !havebase
11516 && !haveindex
11517 && address_mode == mode_32bit);
11518 havedisp = (havebase
11519 || needindex
11520 || (havesib && (haveindex || scale != 0)));
5d669648 11521
252b5132 11522 if (!intel_syntax)
82c18208 11523 if (modrm.mod != 0 || base == 5)
db6eb5be 11524 {
5d669648
L		 11525 if (havedisp || riprel)
11526 print_displacement (scratchbuf, disp);
11527 else
11528 print_operand_value (scratchbuf, 1, disp);
db6eb5be 11529 oappend (scratchbuf);
52b15da3
JH		 11530 if (riprel)
11531 {
11532 set_op (disp, 1);
87767711 11533 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
52b15da3 11534 }
db6eb5be 11535 }
2da11e11 11536
87767711
JB		 11537 if (havebase || haveindex || riprel)
11538 used_prefixes |= PREFIX_ADDR;
11539
5d669648 11540 if (havedisp || (intel_syntax && riprel))
252b5132 11541 {
252b5132 11542 *obufp++ = open_char;
52b15da3 11543 if (intel_syntax && riprel)
185b1163
L		 11544 {
11545 set_op (disp, 1);
87767711 11546 oappend (sizeflag & AFLAG ? "rip" : "eip");
185b1163 11547 }
db6eb5be 11548 *obufp = '\0';
252b5132 11549 if (havebase)
cb712a9e 11550 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
82c18208 11551 ? names64[rbase] : names32[rbase]);
252b5132
RH		 11552 if (havesib)
11553 {
db51cc60
L		 11554 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
11555 print index to tell base + index from base. */
11556 if (scale != 0
20afcfb7 11557 || needindex
db51cc60
L		 11558 || haveindex
11559 || (havebase && base != ESP_REG_NUM))
252b5132 11560 {
9306ca4a 11561 if (!intel_syntax || havebase)
db6eb5be 11562 {
9306ca4a
JB		 11563 *obufp++ = separator_char;
11564 *obufp = '\0';
db6eb5be 11565 }
db51cc60
L		 11566 if (haveindex)
11567 oappend (address_mode == mode_64bit
11568 && (sizeflag & AFLAG)
11569 ? names64[index] : names32[index]);
11570 else
11571 oappend (address_mode == mode_64bit
11572 && (sizeflag & AFLAG)
11573 ? index64 : index32);
11574
db6eb5be
AM		 11575 *obufp++ = scale_char;
11576 *obufp = '\0';
11577 sprintf (scratchbuf, "%d", 1 << scale);
11578 oappend (scratchbuf);
11579 }
252b5132 11580 }
185b1163 11581 if (intel_syntax
82c18208 11582 && (disp || modrm.mod != 0 || base == 5))
3d456fa1 11583 {
db51cc60 11584 if (!havedisp || (bfd_signed_vma) disp >= 0)
3d456fa1
JB		 11585 {
11586 *obufp++ = '+';
11587 *obufp = '\0';
11588 }
7967e09e 11589 else if (modrm.mod != 1)
3d456fa1
JB		 11590 {
11591 *obufp++ = '-';
11592 *obufp = '\0';
11593 disp = - (bfd_signed_vma) disp;
11594 }
11595
db51cc60
L		 11596 if (havedisp)
11597 print_displacement (scratchbuf, disp);
11598 else
11599 print_operand_value (scratchbuf, 1, disp);
3d456fa1
JB		 11600 oappend (scratchbuf);
11601 }
252b5132
RH		 11602
11603 *obufp++ = close_char;
db6eb5be 11604 *obufp = '\0';
252b5132
RH		 11605 }
11606 else if (intel_syntax)
db6eb5be 11607 {
82c18208 11608 if (modrm.mod != 0 || base == 5)
db6eb5be 11609 {
252b5132
RH		 11610 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11611 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11612 ;
11613 else
11614 {
d708bcba 11615 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 11616 oappend (":");
11617 }
52b15da3 11618 print_operand_value (scratchbuf, 1, disp);
db6eb5be
AM		 11619 oappend (scratchbuf);
11620 }
11621 }
252b5132
RH		 11622 }
11623 else
11624 { /* 16 bit address mode */
7967e09e 11625 switch (modrm.mod)
252b5132
RH		 11626 {
11627 case 0:
7967e09e 11628 if (modrm.rm == 6)
252b5132
RH		 11629 {
11630 disp = get16 ();
11631 if ((disp & 0x8000) != 0)
11632 disp -= 0x10000;
11633 }
11634 break;
11635 case 1:
11636 FETCH_DATA (the_info, codep + 1);
11637 disp = *codep++;
11638 if ((disp & 0x80) != 0)
11639 disp -= 0x100;
11640 break;
11641 case 2:
11642 disp = get16 ();
11643 if ((disp & 0x8000) != 0)
11644 disp -= 0x10000;
11645 break;
11646 }
11647
11648 if (!intel_syntax)
7967e09e 11649 if (modrm.mod != 0 || modrm.rm == 6)
db6eb5be 11650 {
5d669648 11651 print_displacement (scratchbuf, disp);
db6eb5be
AM		 11652 oappend (scratchbuf);
11653 }
252b5132 11654
7967e09e 11655 if (modrm.mod != 0 || modrm.rm != 6)
252b5132
RH		 11656 {
11657 *obufp++ = open_char;
db6eb5be 11658 *obufp = '\0';
7967e09e 11659 oappend (index16[modrm.rm]);
5d669648
L		 11660 if (intel_syntax
11661 && (disp || modrm.mod != 0 || modrm.rm == 6))
3d456fa1 11662 {
5d669648 11663 if ((bfd_signed_vma) disp >= 0)
3d456fa1
JB		 11664 {
11665 *obufp++ = '+';
11666 *obufp = '\0';
11667 }
7967e09e 11668 else if (modrm.mod != 1)
3d456fa1
JB		 11669 {
11670 *obufp++ = '-';
11671 *obufp = '\0';
11672 disp = - (bfd_signed_vma) disp;
11673 }
11674
5d669648 11675 print_displacement (scratchbuf, disp);
3d456fa1
JB		 11676 oappend (scratchbuf);
11677 }
11678
db6eb5be
AM		 11679 *obufp++ = close_char;
11680 *obufp = '\0';
252b5132 11681 }
3d456fa1
JB		 11682 else if (intel_syntax)
11683 {
11684 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11685 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11686 ;
11687 else
11688 {
11689 oappend (names_seg[ds_reg - es_reg]);
11690 oappend (":");
11691 }
11692 print_operand_value (scratchbuf, 1, disp & 0xffff);
11693 oappend (scratchbuf);
11694 }
252b5132
RH		 11695 }
11696}
11697
c0f3af97
L		 11698static void
11699OP_E_extended (int bytemode, int sizeflag, int has_drex)
11700{
11701 /* Skip mod/rm byte. */
11702 MODRM_CHECK;
11703 codep++;
11704
11705 if (modrm.mod == 3)
11706 OP_E_register (bytemode, sizeflag);
11707 else
11708 OP_E_memory (bytemode, sizeflag, has_drex);
11709}
11710
85f10a01
MM		 11711static void
11712OP_E (int bytemode, int sizeflag)
11713{
11714 OP_E_extended (bytemode, sizeflag, 0);
11715}
11716
11717
252b5132 11718static void
26ca5450 11719OP_G (int bytemode, int sizeflag)
252b5132 11720{
52b15da3 11721 int add = 0;
161a04f6
L		 11722 USED_REX (REX_R);
11723 if (rex & REX_R)
52b15da3 11724 add += 8;
252b5132
RH		 11725 switch (bytemode)
11726 {
11727 case b_mode:
52b15da3
JH		 11728 USED_REX (0);
11729 if (rex)
7967e09e 11730 oappend (names8rex[modrm.reg + add]);
52b15da3 11731 else
7967e09e 11732 oappend (names8[modrm.reg + add]);
252b5132
RH		 11733 break;
11734 case w_mode:
7967e09e 11735 oappend (names16[modrm.reg + add]);
252b5132
RH		 11736 break;
11737 case d_mode:
7967e09e 11738 oappend (names32[modrm.reg + add]);
52b15da3
JH		 11739 break;
11740 case q_mode:
7967e09e 11741 oappend (names64[modrm.reg + add]);
252b5132
RH		 11742 break;
11743 case v_mode:
9306ca4a 11744 case dq_mode:
42903f7f
L		 11745 case dqb_mode:
11746 case dqd_mode:
9306ca4a 11747 case dqw_mode:
161a04f6
L		 11748 USED_REX (REX_W);
11749 if (rex & REX_W)
7967e09e 11750 oappend (names64[modrm.reg + add]);
9306ca4a 11751 else if ((sizeflag & DFLAG) || bytemode != v_mode)
7967e09e 11752 oappend (names32[modrm.reg + add]);
252b5132 11753 else
7967e09e 11754 oappend (names16[modrm.reg + add]);
7d421014 11755 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 11756 break;
90700ea2 11757 case m_mode:
cb712a9e 11758 if (address_mode == mode_64bit)
7967e09e 11759 oappend (names64[modrm.reg + add]);
90700ea2 11760 else
7967e09e 11761 oappend (names32[modrm.reg + add]);
90700ea2 11762 break;
252b5132
RH		 11763 default:
11764 oappend (INTERNAL_DISASSEMBLER_ERROR);
11765 break;
11766 }
11767}
11768
52b15da3 11769static bfd_vma
26ca5450 11770get64 (void)
52b15da3 11771{
5dd0794d 11772 bfd_vma x;
52b15da3 11773#ifdef BFD64
5dd0794d
AM		 11774 unsigned int a;
11775 unsigned int b;
11776
52b15da3
JH		 11777 FETCH_DATA (the_info, codep + 8);
11778 a = *codep++ & 0xff;
11779 a |= (*codep++ & 0xff) << 8;
11780 a |= (*codep++ & 0xff) << 16;
11781 a |= (*codep++ & 0xff) << 24;
5dd0794d 11782 b = *codep++ & 0xff;
52b15da3
JH		 11783 b |= (*codep++ & 0xff) << 8;
11784 b |= (*codep++ & 0xff) << 16;
11785 b |= (*codep++ & 0xff) << 24;
11786 x = a + ((bfd_vma) b << 32);
11787#else
6608db57 11788 abort ();
5dd0794d 11789 x = 0;
52b15da3
JH		 11790#endif
11791 return x;
11792}
11793
11794static bfd_signed_vma
26ca5450 11795get32 (void)
252b5132 11796{
52b15da3 11797 bfd_signed_vma x = 0;
252b5132
RH		 11798
11799 FETCH_DATA (the_info, codep + 4);
52b15da3
JH		 11800 x = *codep++ & (bfd_signed_vma) 0xff;
11801 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11802 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11803 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11804 return x;
11805}
11806
11807static bfd_signed_vma
26ca5450 11808get32s (void)
52b15da3
JH		 11809{
11810 bfd_signed_vma x = 0;
11811
11812 FETCH_DATA (the_info, codep + 4);
11813 x = *codep++ & (bfd_signed_vma) 0xff;
11814 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11815 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11816 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11817
11818 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
11819
252b5132
RH		 11820 return x;
11821}
11822
11823static int
26ca5450 11824get16 (void)
252b5132
RH		 11825{
11826 int x = 0;
11827
11828 FETCH_DATA (the_info, codep + 2);
11829 x = *codep++ & 0xff;
11830 x |= (*codep++ & 0xff) << 8;
11831 return x;
11832}
11833
11834static void
26ca5450 11835set_op (bfd_vma op, int riprel)
252b5132
RH		 11836{
11837 op_index[op_ad] = op_ad;
cb712a9e 11838 if (address_mode == mode_64bit)
7081ff04
AJ		 11839 {
11840 op_address[op_ad] = op;
11841 op_riprel[op_ad] = riprel;
11842 }
11843 else
11844 {
11845 /* Mask to get a 32-bit address. */
11846 op_address[op_ad] = op & 0xffffffff;
11847 op_riprel[op_ad] = riprel & 0xffffffff;
11848 }
252b5132
RH		 11849}
11850
11851static void
26ca5450 11852OP_REG (int code, int sizeflag)
252b5132 11853{
2da11e11 11854 const char *s;
9b60702d 11855 int add;
161a04f6
L		 11856 USED_REX (REX_B);
11857 if (rex & REX_B)
52b15da3 11858 add = 8;
9b60702d
L		 11859 else
11860 add = 0;
52b15da3
JH		 11861
11862 switch (code)
11863 {
52b15da3
JH		 11864 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
11865 case sp_reg: case bp_reg: case si_reg: case di_reg:
11866 s = names16[code - ax_reg + add];
11867 break;
11868 case es_reg: case ss_reg: case cs_reg:
11869 case ds_reg: case fs_reg: case gs_reg:
11870 s = names_seg[code - es_reg + add];
11871 break;
11872 case al_reg: case ah_reg: case cl_reg: case ch_reg:
11873 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
11874 USED_REX (0);
11875 if (rex)
11876 s = names8rex[code - al_reg + add];
11877 else
11878 s = names8[code - al_reg];
11879 break;
6439fc28
AM		 11880 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
11881 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
cb712a9e 11882 if (address_mode == mode_64bit && (sizeflag & DFLAG))
6439fc28
AM		 11883 {
11884 s = names64[code - rAX_reg + add];
11885 break;
11886 }
11887 code += eAX_reg - rAX_reg;
6608db57 11888 /* Fall through. */
52b15da3
JH		 11889 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
11890 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 11891 USED_REX (REX_W);
11892 if (rex & REX_W)
52b15da3
JH		 11893 s = names64[code - eAX_reg + add];
11894 else if (sizeflag & DFLAG)
11895 s = names32[code - eAX_reg + add];
11896 else
11897 s = names16[code - eAX_reg + add];
11898 used_prefixes |= (prefixes & PREFIX_DATA);
11899 break;
52b15da3
JH		 11900 default:
11901 s = INTERNAL_DISASSEMBLER_ERROR;
11902 break;
11903 }
11904 oappend (s);
11905}
11906
11907static void
26ca5450 11908OP_IMREG (int code, int sizeflag)
52b15da3
JH		 11909{
11910 const char *s;
252b5132
RH		 11911
11912 switch (code)
11913 {
11914 case indir_dx_reg:
d708bcba 11915 if (intel_syntax)
52fd6d94 11916 s = "dx";
d708bcba 11917 else
db6eb5be 11918 s = "(%dx)";
252b5132
RH		 11919 break;
11920 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
11921 case sp_reg: case bp_reg: case si_reg: case di_reg:
11922 s = names16[code - ax_reg];
11923 break;
11924 case es_reg: case ss_reg: case cs_reg:
11925 case ds_reg: case fs_reg: case gs_reg:
11926 s = names_seg[code - es_reg];
11927 break;
11928 case al_reg: case ah_reg: case cl_reg: case ch_reg:
11929 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
52b15da3
JH		 11930 USED_REX (0);
11931 if (rex)
11932 s = names8rex[code - al_reg];
11933 else
11934 s = names8[code - al_reg];
252b5132
RH		 11935 break;
11936 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
11937 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
161a04f6
L		 11938 USED_REX (REX_W);
11939 if (rex & REX_W)
52b15da3
JH		 11940 s = names64[code - eAX_reg];
11941 else if (sizeflag & DFLAG)
252b5132
RH		 11942 s = names32[code - eAX_reg];
11943 else
11944 s = names16[code - eAX_reg];
7d421014 11945 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 11946 break;
52fd6d94 11947 case z_mode_ax_reg:
161a04f6 11948 if ((rex & REX_W) || (sizeflag & DFLAG))
52fd6d94
JB		 11949 s = *names32;
11950 else
11951 s = *names16;
161a04f6 11952 if (!(rex & REX_W))
52fd6d94
JB		 11953 used_prefixes |= (prefixes & PREFIX_DATA);
11954 break;
252b5132
RH		 11955 default:
11956 s = INTERNAL_DISASSEMBLER_ERROR;
11957 break;
11958 }
11959 oappend (s);
11960}
11961
11962static void
26ca5450 11963OP_I (int bytemode, int sizeflag)
252b5132 11964{
52b15da3
JH		 11965 bfd_signed_vma op;
11966 bfd_signed_vma mask = -1;
252b5132
RH		 11967
11968 switch (bytemode)
11969 {
11970 case b_mode:
11971 FETCH_DATA (the_info, codep + 1);
52b15da3
JH		 11972 op = *codep++;
11973 mask = 0xff;
11974 break;
11975 case q_mode:
cb712a9e 11976 if (address_mode == mode_64bit)
6439fc28
AM		 11977 {
11978 op = get32s ();
11979 break;
11980 }
6608db57 11981 /* Fall through. */
252b5132 11982 case v_mode:
161a04f6
L		 11983 USED_REX (REX_W);
11984 if (rex & REX_W)
52b15da3
JH		 11985 op = get32s ();
11986 else if (sizeflag & DFLAG)
11987 {
11988 op = get32 ();
11989 mask = 0xffffffff;
11990 }
252b5132 11991 else
52b15da3
JH		 11992 {
11993 op = get16 ();
11994 mask = 0xfffff;
11995 }
7d421014 11996 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 11997 break;
11998 case w_mode:
52b15da3 11999 mask = 0xfffff;
252b5132
RH		 12000 op = get16 ();
12001 break;
9306ca4a
JB		 12002 case const_1_mode:
12003 if (intel_syntax)
12004 oappend ("1");
12005 return;
252b5132
RH		 12006 default:
12007 oappend (INTERNAL_DISASSEMBLER_ERROR);
12008 return;
12009 }
12010
52b15da3
JH		 12011 op &= mask;
12012 scratchbuf[0] = '$';
d708bcba
AM		 12013 print_operand_value (scratchbuf + 1, 1, op);
12014 oappend (scratchbuf + intel_syntax);
52b15da3
JH		 12015 scratchbuf[0] = '\0';
12016}
12017
12018static void
26ca5450 12019OP_I64 (int bytemode, int sizeflag)
52b15da3
JH		 12020{
12021 bfd_signed_vma op;
12022 bfd_signed_vma mask = -1;
12023
cb712a9e 12024 if (address_mode != mode_64bit)
6439fc28
AM		 12025 {
12026 OP_I (bytemode, sizeflag);
12027 return;
12028 }
12029
52b15da3
JH		 12030 switch (bytemode)
12031 {
12032 case b_mode:
12033 FETCH_DATA (the_info, codep + 1);
12034 op = *codep++;
12035 mask = 0xff;
12036 break;
12037 case v_mode:
161a04f6
L		 12038 USED_REX (REX_W);
12039 if (rex & REX_W)
52b15da3
JH		 12040 op = get64 ();
12041 else if (sizeflag & DFLAG)
12042 {
12043 op = get32 ();
12044 mask = 0xffffffff;
12045 }
12046 else
12047 {
12048 op = get16 ();
12049 mask = 0xfffff;
12050 }
12051 used_prefixes |= (prefixes & PREFIX_DATA);
12052 break;
12053 case w_mode:
12054 mask = 0xfffff;
12055 op = get16 ();
12056 break;
12057 default:
12058 oappend (INTERNAL_DISASSEMBLER_ERROR);
12059 return;
12060 }
12061
12062 op &= mask;
12063 scratchbuf[0] = '$';
d708bcba
AM		 12064 print_operand_value (scratchbuf + 1, 1, op);
12065 oappend (scratchbuf + intel_syntax);
252b5132
RH		 12066 scratchbuf[0] = '\0';
12067}
12068
12069static void
26ca5450 12070OP_sI (int bytemode, int sizeflag)
252b5132 12071{
52b15da3
JH		 12072 bfd_signed_vma op;
12073 bfd_signed_vma mask = -1;
252b5132
RH		 12074
12075 switch (bytemode)
12076 {
12077 case b_mode:
12078 FETCH_DATA (the_info, codep + 1);
12079 op = *codep++;
12080 if ((op & 0x80) != 0)
12081 op -= 0x100;
52b15da3 12082 mask = 0xffffffff;
252b5132
RH		 12083 break;
12084 case v_mode:
161a04f6
L		 12085 USED_REX (REX_W);
12086 if (rex & REX_W)
52b15da3
JH		 12087 op = get32s ();
12088 else if (sizeflag & DFLAG)
12089 {
12090 op = get32s ();
12091 mask = 0xffffffff;
12092 }
252b5132
RH		 12093 else
12094 {
52b15da3 12095 mask = 0xffffffff;
6608db57 12096 op = get16 ();
252b5132
RH		 12097 if ((op & 0x8000) != 0)
12098 op -= 0x10000;
12099 }
7d421014 12100 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 12101 break;
12102 case w_mode:
12103 op = get16 ();
52b15da3 12104 mask = 0xffffffff;
252b5132
RH		 12105 if ((op & 0x8000) != 0)
12106 op -= 0x10000;
12107 break;
12108 default:
12109 oappend (INTERNAL_DISASSEMBLER_ERROR);
12110 return;
12111 }
52b15da3
JH		 12112
12113 scratchbuf[0] = '$';
12114 print_operand_value (scratchbuf + 1, 1, op);
d708bcba 12115 oappend (scratchbuf + intel_syntax);
252b5132
RH		 12116}
12117
12118static void
26ca5450 12119OP_J (int bytemode, int sizeflag)
252b5132 12120{
52b15da3 12121 bfd_vma disp;
7081ff04 12122 bfd_vma mask = -1;
65ca155d 12123 bfd_vma segment = 0;
252b5132
RH		 12124
12125 switch (bytemode)
12126 {
12127 case b_mode:
12128 FETCH_DATA (the_info, codep + 1);
12129 disp = *codep++;
12130 if ((disp & 0x80) != 0)
12131 disp -= 0x100;
12132 break;
12133 case v_mode:
161a04f6 12134 if ((sizeflag & DFLAG) || (rex & REX_W))
52b15da3 12135 disp = get32s ();
252b5132
RH		 12136 else
12137 {
12138 disp = get16 ();
206717e8
L		 12139 if ((disp & 0x8000) != 0)
12140 disp -= 0x10000;
65ca155d
L		 12141 /* In 16bit mode, address is wrapped around at 64k within
12142 the same segment. Otherwise, a data16 prefix on a jump
12143 instruction means that the pc is masked to 16 bits after
12144 the displacement is added! */
12145 mask = 0xffff;
12146 if ((prefixes & PREFIX_DATA) == 0)
12147 segment = ((start_pc + codep - start_codep)
12148 & ~((bfd_vma) 0xffff));
252b5132 12149 }
d807a492 12150 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 12151 break;
12152 default:
12153 oappend (INTERNAL_DISASSEMBLER_ERROR);
12154 return;
12155 }
65ca155d 12156 disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
52b15da3
JH		 12157 set_op (disp, 0);
12158 print_operand_value (scratchbuf, 1, disp);
252b5132
RH		 12159 oappend (scratchbuf);
12160}
12161
252b5132 12162static void
ed7841b3 12163OP_SEG (int bytemode, int sizeflag)
252b5132 12164{
ed7841b3 12165 if (bytemode == w_mode)
7967e09e 12166 oappend (names_seg[modrm.reg]);
ed7841b3 12167 else
7967e09e 12168 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
252b5132
RH		 12169}
12170
12171static void
26ca5450 12172OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
252b5132
RH		 12173{
12174 int seg, offset;
12175
c608c12e 12176 if (sizeflag & DFLAG)
252b5132 12177 {
c608c12e
AM		 12178 offset = get32 ();
12179 seg = get16 ();
252b5132 12180 }
c608c12e
AM		 12181 else
12182 {
12183 offset = get16 ();
12184 seg = get16 ();
12185 }
7d421014 12186 used_prefixes |= (prefixes & PREFIX_DATA);
d708bcba 12187 if (intel_syntax)
3f31e633 12188 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
d708bcba
AM		 12189 else
12190 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
c608c12e 12191 oappend (scratchbuf);
252b5132
RH		 12192}
12193
252b5132 12194static void
3f31e633 12195OP_OFF (int bytemode, int sizeflag)
252b5132 12196{
52b15da3 12197 bfd_vma off;
252b5132 12198
3f31e633
JB		 12199 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12200 intel_operand_size (bytemode, sizeflag);
252b5132
RH		 12201 append_seg ();
12202
cb712a9e 12203 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
252b5132
RH		 12204 off = get32 ();
12205 else
12206 off = get16 ();
12207
12208 if (intel_syntax)
12209 {
12210 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 12211 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
252b5132 12212 {
d708bcba 12213 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 12214 oappend (":");
12215 }
12216 }
52b15da3
JH		 12217 print_operand_value (scratchbuf, 1, off);
12218 oappend (scratchbuf);
12219}
6439fc28 12220
52b15da3 12221static void
3f31e633 12222OP_OFF64 (int bytemode, int sizeflag)
52b15da3
JH		 12223{
12224 bfd_vma off;
12225
539e75ad
L		 12226 if (address_mode != mode_64bit
12227 || (prefixes & PREFIX_ADDR))
6439fc28
AM		 12228 {
12229 OP_OFF (bytemode, sizeflag);
12230 return;
12231 }
12232
3f31e633
JB		 12233 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12234 intel_operand_size (bytemode, sizeflag);
52b15da3
JH		 12235 append_seg ();
12236
6608db57 12237 off = get64 ();
52b15da3
JH		 12238
12239 if (intel_syntax)
12240 {
12241 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 12242 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
52b15da3 12243 {
d708bcba 12244 oappend (names_seg[ds_reg - es_reg]);
52b15da3
JH		 12245 oappend (":");
12246 }
12247 }
12248 print_operand_value (scratchbuf, 1, off);
252b5132
RH		 12249 oappend (scratchbuf);
12250}
12251
12252static void
26ca5450 12253ptr_reg (int code, int sizeflag)
252b5132 12254{
2da11e11 12255 const char *s;
d708bcba 12256
1d9f512f 12257 *obufp++ = open_char;
20f0a1fc 12258 used_prefixes |= (prefixes & PREFIX_ADDR);
cb712a9e 12259 if (address_mode == mode_64bit)
c1a64871
JH		 12260 {
12261 if (!(sizeflag & AFLAG))
db6eb5be 12262 s = names32[code - eAX_reg];
c1a64871 12263 else
db6eb5be 12264 s = names64[code - eAX_reg];
c1a64871 12265 }
52b15da3 12266 else if (sizeflag & AFLAG)
252b5132
RH		 12267 s = names32[code - eAX_reg];
12268 else
12269 s = names16[code - eAX_reg];
12270 oappend (s);
1d9f512f
AM		 12271 *obufp++ = close_char;
12272 *obufp = 0;
252b5132
RH		 12273}
12274
12275static void
26ca5450 12276OP_ESreg (int code, int sizeflag)
252b5132 12277{
9306ca4a 12278 if (intel_syntax)
52fd6d94
JB		 12279 {
12280 switch (codep[-1])
12281 {
12282 case 0x6d: /* insw/insl */
12283 intel_operand_size (z_mode, sizeflag);
12284 break;
12285 case 0xa5: /* movsw/movsl/movsq */
12286 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12287 case 0xab: /* stosw/stosl */
12288 case 0xaf: /* scasw/scasl */
12289 intel_operand_size (v_mode, sizeflag);
12290 break;
12291 default:
12292 intel_operand_size (b_mode, sizeflag);
12293 }
12294 }
d708bcba 12295 oappend ("%es:" + intel_syntax);
252b5132
RH		 12296 ptr_reg (code, sizeflag);
12297}
12298
12299static void
26ca5450 12300OP_DSreg (int code, int sizeflag)
252b5132 12301{
9306ca4a 12302 if (intel_syntax)
52fd6d94
JB		 12303 {
12304 switch (codep[-1])
12305 {
12306 case 0x6f: /* outsw/outsl */
12307 intel_operand_size (z_mode, sizeflag);
12308 break;
12309 case 0xa5: /* movsw/movsl/movsq */
12310 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12311 case 0xad: /* lodsw/lodsl/lodsq */
12312 intel_operand_size (v_mode, sizeflag);
12313 break;
12314 default:
12315 intel_operand_size (b_mode, sizeflag);
12316 }
12317 }
252b5132
RH		 12318 if ((prefixes
12319 & (PREFIX_CS
12320 | PREFIX_DS
12321 | PREFIX_SS
12322 | PREFIX_ES
12323 | PREFIX_FS
12324 | PREFIX_GS)) == 0)
12325 prefixes |= PREFIX_DS;
6608db57 12326 append_seg ();
252b5132
RH		 12327 ptr_reg (code, sizeflag);
12328}
12329
252b5132 12330static void
26ca5450 12331OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 12332{
9b60702d 12333 int add;
161a04f6 12334 if (rex & REX_R)
c4a530c5 12335 {
161a04f6 12336 USED_REX (REX_R);
c4a530c5
JB		 12337 add = 8;
12338 }
cb712a9e 12339 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
c4a530c5 12340 {
b844680a 12341 lock_prefix = NULL;
c4a530c5
JB		 12342 used_prefixes |= PREFIX_LOCK;
12343 add = 8;
12344 }
9b60702d
L		 12345 else
12346 add = 0;
7967e09e 12347 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
d708bcba 12348 oappend (scratchbuf + intel_syntax);
252b5132
RH		 12349}
12350
252b5132 12351static void
26ca5450 12352OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 12353{
9b60702d 12354 int add;
161a04f6
L		 12355 USED_REX (REX_R);
12356 if (rex & REX_R)
52b15da3 12357 add = 8;
9b60702d
L		 12358 else
12359 add = 0;
d708bcba 12360 if (intel_syntax)
7967e09e 12361 sprintf (scratchbuf, "db%d", modrm.reg + add);
d708bcba 12362 else
7967e09e 12363 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
252b5132
RH		 12364 oappend (scratchbuf);
12365}
12366
252b5132 12367static void
26ca5450 12368OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 12369{
7967e09e 12370 sprintf (scratchbuf, "%%tr%d", modrm.reg);
d708bcba 12371 oappend (scratchbuf + intel_syntax);
252b5132
RH		 12372}
12373
12374static void
6f74c397 12375OP_R (int bytemode, int sizeflag)
252b5132 12376{
7967e09e 12377 if (modrm.mod == 3)
2da11e11
AM		 12378 OP_E (bytemode, sizeflag);
12379 else
6608db57 12380 BadOp ();
252b5132
RH		 12381}
12382
12383static void
26ca5450 12384OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 12385{
041bd2e0
JH		 12386 used_prefixes |= (prefixes & PREFIX_DATA);
12387 if (prefixes & PREFIX_DATA)
20f0a1fc 12388 {
9b60702d 12389 int add;
161a04f6
L		 12390 USED_REX (REX_R);
12391 if (rex & REX_R)
20f0a1fc 12392 add = 8;
9b60702d
L		 12393 else
12394 add = 0;
7967e09e 12395 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
20f0a1fc 12396 }
041bd2e0 12397 else
7967e09e 12398 sprintf (scratchbuf, "%%mm%d", modrm.reg);
d708bcba 12399 oappend (scratchbuf + intel_syntax);
252b5132
RH		 12400}
12401
c608c12e 12402static void
c0f3af97 12403OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
c608c12e 12404{
9b60702d 12405 int add;
161a04f6
L		 12406 USED_REX (REX_R);
12407 if (rex & REX_R)
041bd2e0 12408 add = 8;
9b60702d
L		 12409 else
12410 add = 0;
c0f3af97
L		 12411 if (need_vex && bytemode != xmm_mode)
12412 {
12413 switch (vex.length)
12414 {
12415 case 128:
12416 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12417 break;
12418 case 256:
12419 sprintf (scratchbuf, "%%ymm%d", modrm.reg + add);
12420 break;
12421 default:
12422 abort ();
12423 }
12424 }
12425 else
12426 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
d708bcba 12427 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 12428}
12429
252b5132 12430static void
26ca5450 12431OP_EM (int bytemode, int sizeflag)
252b5132 12432{
7967e09e 12433 if (modrm.mod != 3)
252b5132 12434 {
9306ca4a
JB		 12435 if (intel_syntax && bytemode == v_mode)
12436 {
12437 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12438 used_prefixes |= (prefixes & PREFIX_DATA);
12439 }
252b5132
RH		 12440 OP_E (bytemode, sizeflag);
12441 return;
12442 }
12443
6608db57 12444 /* Skip mod/rm byte. */
4bba6815 12445 MODRM_CHECK;
252b5132 12446 codep++;
041bd2e0
JH		 12447 used_prefixes |= (prefixes & PREFIX_DATA);
12448 if (prefixes & PREFIX_DATA)
20f0a1fc 12449 {
9b60702d 12450 int add;
20f0a1fc 12451
161a04f6
L		 12452 USED_REX (REX_B);
12453 if (rex & REX_B)
20f0a1fc 12454 add = 8;
9b60702d
L		 12455 else
12456 add = 0;
7967e09e 12457 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
20f0a1fc 12458 }
041bd2e0 12459 else
7967e09e 12460 sprintf (scratchbuf, "%%mm%d", modrm.rm);
d708bcba 12461 oappend (scratchbuf + intel_syntax);
252b5132
RH		 12462}
12463
246c51aa
L		 12464/* cvt* are the only instructions in sse2 which have
12465 both SSE and MMX operands and also have 0x66 prefix
12466 in their opcode. 0x66 was originally used to differentiate
12467 between SSE and MMX instruction(operands). So we have to handle the
4d9567e0
MM		 12468 cvt* separately using OP_EMC and OP_MXC */
12469static void
12470OP_EMC (int bytemode, int sizeflag)
12471{
7967e09e 12472 if (modrm.mod != 3)
4d9567e0
MM		 12473 {
12474 if (intel_syntax && bytemode == v_mode)
12475 {
12476 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12477 used_prefixes |= (prefixes & PREFIX_DATA);
12478 }
12479 OP_E (bytemode, sizeflag);
12480 return;
12481 }
246c51aa 12482
4d9567e0
MM		 12483 /* Skip mod/rm byte. */
12484 MODRM_CHECK;
12485 codep++;
12486 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 12487 sprintf (scratchbuf, "%%mm%d", modrm.rm);
4d9567e0
MM		 12488 oappend (scratchbuf + intel_syntax);
12489}
12490
12491static void
12492OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12493{
12494 used_prefixes |= (prefixes & PREFIX_DATA);
7967e09e 12495 sprintf (scratchbuf, "%%mm%d", modrm.reg);
4d9567e0
MM		 12496 oappend (scratchbuf + intel_syntax);
12497}
12498
c608c12e 12499static void
26ca5450 12500OP_EX (int bytemode, int sizeflag)
c608c12e 12501{
9b60702d 12502 int add;
7967e09e 12503 if (modrm.mod != 3)
c608c12e
AM		 12504 {
12505 OP_E (bytemode, sizeflag);
12506 return;
12507 }
161a04f6
L		 12508 USED_REX (REX_B);
12509 if (rex & REX_B)
041bd2e0 12510 add = 8;
9b60702d
L		 12511 else
12512 add = 0;
c608c12e 12513
6608db57 12514 /* Skip mod/rm byte. */
4bba6815 12515 MODRM_CHECK;
c608c12e 12516 codep++;
c0f3af97
L		 12517 if (need_vex
12518 && bytemode != xmm_mode
12519 && bytemode != xmmq_mode)
12520 {
12521 switch (vex.length)
12522 {
12523 case 128:
12524 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12525 break;
12526 case 256:
12527 sprintf (scratchbuf, "%%ymm%d", modrm.rm + add);
12528 break;
12529 default:
12530 abort ();
12531 }
12532 }
12533 else
12534 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
d708bcba 12535 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 12536}
12537
252b5132 12538static void
26ca5450 12539OP_MS (int bytemode, int sizeflag)
252b5132 12540{
7967e09e 12541 if (modrm.mod == 3)
2da11e11
AM		 12542 OP_EM (bytemode, sizeflag);
12543 else
6608db57 12544 BadOp ();
252b5132
RH		 12545}
12546
992aaec9 12547static void
26ca5450 12548OP_XS (int bytemode, int sizeflag)
992aaec9 12549{
7967e09e 12550 if (modrm.mod == 3)
992aaec9
AM		 12551 OP_EX (bytemode, sizeflag);
12552 else
6608db57 12553 BadOp ();
992aaec9
AM		 12554}
12555
cc0ec051
AM		 12556static void
12557OP_M (int bytemode, int sizeflag)
12558{
7967e09e 12559 if (modrm.mod == 3)
75413a22
L		 12560 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12561 BadOp ();
cc0ec051
AM		 12562 else
12563 OP_E (bytemode, sizeflag);
12564}
12565
12566static void
12567OP_0f07 (int bytemode, int sizeflag)
12568{
7967e09e 12569 if (modrm.mod != 3 || modrm.rm != 0)
cc0ec051
AM		 12570 BadOp ();
12571 else
12572 OP_E (bytemode, sizeflag);
12573}
12574
46e883c5 12575/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
246c51aa 12576 32bit mode and "xchg %rax,%rax" in 64bit mode. */
46e883c5 12577
cc0ec051 12578static void
46e883c5 12579NOP_Fixup1 (int bytemode, int sizeflag)
cc0ec051 12580{
8b38ad71
L		 12581 if ((prefixes & PREFIX_DATA) != 0
12582 || (rex != 0
12583 && rex != 0x48
12584 && address_mode == mode_64bit))
46e883c5
L		 12585 OP_REG (bytemode, sizeflag);
12586 else
12587 strcpy (obuf, "nop");
12588}
12589
12590static void
12591NOP_Fixup2 (int bytemode, int sizeflag)
12592{
8b38ad71
L		 12593 if ((prefixes & PREFIX_DATA) != 0
12594 || (rex != 0
12595 && rex != 0x48
12596 && address_mode == mode_64bit))
46e883c5 12597 OP_IMREG (bytemode, sizeflag);
cc0ec051
AM		 12598}
12599
84037f8c 12600static const char *const Suffix3DNow[] = {
252b5132
RH		 12601/* 00 */ NULL, NULL, NULL, NULL,
12602/* 04 */ NULL, NULL, NULL, NULL,
12603/* 08 */ NULL, NULL, NULL, NULL,
9e525108 12604/* 0C */ "pi2fw", "pi2fd", NULL, NULL,
252b5132
RH		 12605/* 10 */ NULL, NULL, NULL, NULL,
12606/* 14 */ NULL, NULL, NULL, NULL,
12607/* 18 */ NULL, NULL, NULL, NULL,
9e525108 12608/* 1C */ "pf2iw", "pf2id", NULL, NULL,
252b5132
RH		 12609/* 20 */ NULL, NULL, NULL, NULL,
12610/* 24 */ NULL, NULL, NULL, NULL,
12611/* 28 */ NULL, NULL, NULL, NULL,
12612/* 2C */ NULL, NULL, NULL, NULL,
12613/* 30 */ NULL, NULL, NULL, NULL,
12614/* 34 */ NULL, NULL, NULL, NULL,
12615/* 38 */ NULL, NULL, NULL, NULL,
12616/* 3C */ NULL, NULL, NULL, NULL,
12617/* 40 */ NULL, NULL, NULL, NULL,
12618/* 44 */ NULL, NULL, NULL, NULL,
12619/* 48 */ NULL, NULL, NULL, NULL,
12620/* 4C */ NULL, NULL, NULL, NULL,
12621/* 50 */ NULL, NULL, NULL, NULL,
12622/* 54 */ NULL, NULL, NULL, NULL,
12623/* 58 */ NULL, NULL, NULL, NULL,
12624/* 5C */ NULL, NULL, NULL, NULL,
12625/* 60 */ NULL, NULL, NULL, NULL,
12626/* 64 */ NULL, NULL, NULL, NULL,
12627/* 68 */ NULL, NULL, NULL, NULL,
12628/* 6C */ NULL, NULL, NULL, NULL,
12629/* 70 */ NULL, NULL, NULL, NULL,
12630/* 74 */ NULL, NULL, NULL, NULL,
12631/* 78 */ NULL, NULL, NULL, NULL,
12632/* 7C */ NULL, NULL, NULL, NULL,
12633/* 80 */ NULL, NULL, NULL, NULL,
12634/* 84 */ NULL, NULL, NULL, NULL,
9e525108
AM		 12635/* 88 */ NULL, NULL, "pfnacc", NULL,
12636/* 8C */ NULL, NULL, "pfpnacc", NULL,
252b5132
RH		 12637/* 90 */ "pfcmpge", NULL, NULL, NULL,
12638/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
12639/* 98 */ NULL, NULL, "pfsub", NULL,
12640/* 9C */ NULL, NULL, "pfadd", NULL,
12641/* A0 */ "pfcmpgt", NULL, NULL, NULL,
12642/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
12643/* A8 */ NULL, NULL, "pfsubr", NULL,
12644/* AC */ NULL, NULL, "pfacc", NULL,
12645/* B0 */ "pfcmpeq", NULL, NULL, NULL,
9beff690 12646/* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
9e525108 12647/* B8 */ NULL, NULL, NULL, "pswapd",
252b5132
RH		 12648/* BC */ NULL, NULL, NULL, "pavgusb",
12649/* C0 */ NULL, NULL, NULL, NULL,
12650/* C4 */ NULL, NULL, NULL, NULL,
12651/* C8 */ NULL, NULL, NULL, NULL,
12652/* CC */ NULL, NULL, NULL, NULL,
12653/* D0 */ NULL, NULL, NULL, NULL,
12654/* D4 */ NULL, NULL, NULL, NULL,
12655/* D8 */ NULL, NULL, NULL, NULL,
12656/* DC */ NULL, NULL, NULL, NULL,
12657/* E0 */ NULL, NULL, NULL, NULL,
12658/* E4 */ NULL, NULL, NULL, NULL,
12659/* E8 */ NULL, NULL, NULL, NULL,
12660/* EC */ NULL, NULL, NULL, NULL,
12661/* F0 */ NULL, NULL, NULL, NULL,
12662/* F4 */ NULL, NULL, NULL, NULL,
12663/* F8 */ NULL, NULL, NULL, NULL,
12664/* FC */ NULL, NULL, NULL, NULL,
12665};
12666
12667static void
26ca5450 12668OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132
RH		 12669{
12670 const char *mnemonic;
12671
12672 FETCH_DATA (the_info, codep + 1);
12673 /* AMD 3DNow! instructions are specified by an opcode suffix in the
12674 place where an 8-bit immediate would normally go. ie. the last
12675 byte of the instruction. */
6608db57 12676 obufp = obuf + strlen (obuf);
c608c12e 12677 mnemonic = Suffix3DNow[*codep++ & 0xff];
252b5132 12678 if (mnemonic)
2da11e11 12679 oappend (mnemonic);
252b5132
RH		 12680 else
12681 {
12682 /* Since a variable sized modrm/sib chunk is between the start
12683 of the opcode (0x0f0f) and the opcode suffix, we need to do
12684 all the modrm processing first, and don't know until now that
12685 we have a bad opcode. This necessitates some cleaning up. */
ce518a5f
L		 12686 op_out[0][0] = '\0';
12687 op_out[1][0] = '\0';
6608db57 12688 BadOp ();
252b5132
RH		 12689 }
12690}
c608c12e 12691
6608db57 12692static const char *simd_cmp_op[] = {
c608c12e
AM		 12693 "eq",
12694 "lt",
12695 "le",
12696 "unord",
12697 "neq",
12698 "nlt",
12699 "nle",
12700 "ord"
12701};
12702
12703static void
ad19981d 12704CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e
AM		 12705{
12706 unsigned int cmp_type;
12707
12708 FETCH_DATA (the_info, codep + 1);
12709 cmp_type = *codep++ & 0xff;
c0f3af97 12710 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
c608c12e 12711 {
ad19981d
L		 12712 char suffix [3];
12713 char *p = obuf + strlen (obuf) - 2;
12714 suffix[0] = p[0];
12715 suffix[1] = p[1];
12716 suffix[2] = '\0';
12717 sprintf (p, "%s%s", simd_cmp_op[cmp_type], suffix);
c608c12e
AM		 12718 }
12719 else
12720 {
ad19981d
L		 12721 /* We have a reserved extension byte. Output it directly. */
12722 scratchbuf[0] = '$';
12723 print_operand_value (scratchbuf + 1, 1, cmp_type);
12724 oappend (scratchbuf + intel_syntax);
12725 scratchbuf[0] = '\0';
c608c12e
AM		 12726 }
12727}
12728
ca164297 12729static void
b844680a
L		 12730OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
12731 int sizeflag ATTRIBUTE_UNUSED)
12732{
12733 /* mwait %eax,%ecx */
12734 if (!intel_syntax)
12735 {
12736 const char **names = (address_mode == mode_64bit
12737 ? names64 : names32);
12738 strcpy (op_out[0], names[0]);
12739 strcpy (op_out[1], names[1]);
12740 two_source_ops = 1;
12741 }
12742 /* Skip mod/rm byte. */
12743 MODRM_CHECK;
12744 codep++;
12745}
12746
12747static void
12748OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
12749 int sizeflag ATTRIBUTE_UNUSED)
ca164297 12750{
b844680a
L		 12751 /* monitor %eax,%ecx,%edx" */
12752 if (!intel_syntax)
ca164297 12753 {
b844680a 12754 const char **op1_names;
cb712a9e
L		 12755 const char **names = (address_mode == mode_64bit
12756 ? names64 : names32);
1d9f512f 12757
b844680a
L		 12758 if (!(prefixes & PREFIX_ADDR))
12759 op1_names = (address_mode == mode_16bit
12760 ? names16 : names);
ca164297
L		 12761 else
12762 {
b844680a
L		 12763 /* Remove "addr16/addr32". */
12764 addr_prefix = NULL;
12765 op1_names = (address_mode != mode_32bit
12766 ? names32 : names16);
12767 used_prefixes |= PREFIX_ADDR;
ca164297 12768 }
b844680a
L		 12769 strcpy (op_out[0], op1_names[0]);
12770 strcpy (op_out[1], names[1]);
12771 strcpy (op_out[2], names[2]);
12772 two_source_ops = 1;
ca164297 12773 }
b844680a
L		 12774 /* Skip mod/rm byte. */
12775 MODRM_CHECK;
12776 codep++;
30123838
JB		 12777}
12778
6608db57
KH		 12779static void
12780BadOp (void)
2da11e11 12781{
6608db57
KH		 12782 /* Throw away prefixes and 1st. opcode byte. */
12783 codep = insn_codep + 1;
2da11e11
AM		 12784 oappend ("(bad)");
12785}
4cc91dba 12786
35c52694
L		 12787static void
12788REP_Fixup (int bytemode, int sizeflag)
12789{
12790 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
12791 lods and stos. */
35c52694 12792 if (prefixes & PREFIX_REPZ)
b844680a 12793 repz_prefix = "rep ";
35c52694
L		 12794
12795 switch (bytemode)
12796 {
12797 case al_reg:
12798 case eAX_reg:
12799 case indir_dx_reg:
12800 OP_IMREG (bytemode, sizeflag);
12801 break;
12802 case eDI_reg:
12803 OP_ESreg (bytemode, sizeflag);
12804 break;
12805 case eSI_reg:
12806 OP_DSreg (bytemode, sizeflag);
12807 break;
12808 default:
12809 abort ();
12810 break;
12811 }
12812}
f5804c90
L		 12813
12814static void
12815CMPXCHG8B_Fixup (int bytemode, int sizeflag)
12816{
161a04f6
L		 12817 USED_REX (REX_W);
12818 if (rex & REX_W)
f5804c90
L		 12819 {
12820 /* Change cmpxchg8b to cmpxchg16b. */
12821 char *p = obuf + strlen (obuf) - 2;
12822 strcpy (p, "16b");
fb9c77c7 12823 bytemode = o_mode;
f5804c90
L		 12824 }
12825 OP_M (bytemode, sizeflag);
12826}
42903f7f
L		 12827
12828static void
12829XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
12830{
c0f3af97
L		 12831 if (need_vex)
12832 {
12833 switch (vex.length)
12834 {
12835 case 128:
12836 sprintf (scratchbuf, "%%xmm%d", reg);
12837 break;
12838 case 256:
12839 sprintf (scratchbuf, "%%ymm%d", reg);
12840 break;
12841 default:
12842 abort ();
12843 }
12844 }
12845 else
12846 sprintf (scratchbuf, "%%xmm%d", reg);
42903f7f
L		 12847 oappend (scratchbuf + intel_syntax);
12848}
381d071f
L		 12849
12850static void
12851CRC32_Fixup (int bytemode, int sizeflag)
12852{
12853 /* Add proper suffix to "crc32". */
12854 char *p = obuf + strlen (obuf);
12855
12856 switch (bytemode)
12857 {
12858 case b_mode:
20592a94
L		 12859 if (intel_syntax)
12860 break;
12861
381d071f
L		 12862 *p++ = 'b';
12863 break;
12864 case v_mode:
20592a94
L		 12865 if (intel_syntax)
12866 break;
12867
381d071f
L		 12868 USED_REX (REX_W);
12869 if (rex & REX_W)
12870 *p++ = 'q';
9344ff29 12871 else if (sizeflag & DFLAG)
20592a94 12872 *p++ = 'l';
381d071f 12873 else
9344ff29
L		 12874 *p++ = 'w';
12875 used_prefixes |= (prefixes & PREFIX_DATA);
381d071f
L		 12876 break;
12877 default:
12878 oappend (INTERNAL_DISASSEMBLER_ERROR);
12879 break;
12880 }
12881 *p = '\0';
12882
12883 if (modrm.mod == 3)
12884 {
12885 int add;
12886
12887 /* Skip mod/rm byte. */
12888 MODRM_CHECK;
12889 codep++;
12890
12891 USED_REX (REX_B);
12892 add = (rex & REX_B) ? 8 : 0;
12893 if (bytemode == b_mode)
12894 {
12895 USED_REX (0);
12896 if (rex)
12897 oappend (names8rex[modrm.rm + add]);
12898 else
12899 oappend (names8[modrm.rm + add]);
12900 }
12901 else
12902 {
12903 USED_REX (REX_W);
12904 if (rex & REX_W)
12905 oappend (names64[modrm.rm + add]);
12906 else if ((prefixes & PREFIX_DATA))
12907 oappend (names16[modrm.rm + add]);
12908 else
12909 oappend (names32[modrm.rm + add]);
12910 }
12911 }
12912 else
9344ff29 12913 OP_E (bytemode, sizeflag);
381d071f 12914}
85f10a01
MM		 12915
12916/* Print a DREX argument as either a register or memory operation. */
12917static void
12918print_drex_arg (unsigned int reg, int bytemode, int sizeflag)
12919{
12920 if (reg == DREX_REG_UNKNOWN)
12921 BadOp ();
12922
12923 else if (reg != DREX_REG_MEMORY)
12924 {
12925 sprintf (scratchbuf, "%%xmm%d", reg);
12926 oappend (scratchbuf + intel_syntax);
12927 }
12928
12929 else
12930 OP_E_extended (bytemode, sizeflag, 1);
12931}
12932
12933/* SSE5 instructions that have 4 arguments are encoded as:
12934 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>.
12935
12936 The <sub-opcode> byte has 1 bit (0x4) that is combined with 1 bit in
12937 the DREX field (0x8) to determine how the arguments are laid out.
12938 The destination register must be the same register as one of the
12939 inputs, and it is encoded in the DREX byte. No REX prefix is used
12940 for these instructions, since the DREX field contains the 3 extension
12941 bits provided by the REX prefix.
12942
12943 The bytemode argument adds 2 extra bits for passing extra information:
12944 DREX_OC1 -- Set the OC1 bit to indicate dest == 1st arg
12945 DREX_NO_OC0 -- OC0 in DREX is invalid
12946 (but pretend it is set). */
12947
12948static void
12949OP_DREX4 (int flag_bytemode, int sizeflag)
12950{
12951 unsigned int drex_byte;
12952 unsigned int regs[4];
12953 unsigned int modrm_regmem;
12954 unsigned int modrm_reg;
12955 unsigned int drex_reg;
12956 int bytemode;
12957 int rex_save = rex;
12958 int rex_used_save = rex_used;
12959 int has_sib = 0;
12960 int oc1 = (flag_bytemode & DREX_OC1) ? 2 : 0;
12961 int oc0;
12962 int i;
12963
12964 bytemode = flag_bytemode & ~ DREX_MASK;
12965
12966 for (i = 0; i < 4; i++)
12967 regs[i] = DREX_REG_UNKNOWN;
12968
12969 /* Determine if we have a SIB byte in addition to MODRM before the
12970 DREX byte. */
12971 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
12972 && (modrm.mod != 3)
12973 && (modrm.rm == 4))
12974 has_sib = 1;
12975
12976 /* Get the DREX byte. */
12977 FETCH_DATA (the_info, codep + 2 + has_sib);
12978 drex_byte = codep[has_sib+1];
12979 drex_reg = DREX_XMM (drex_byte);
12980 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
12981
12982 /* Is OC0 legal? If not, hardwire oc0 == 1. */
12983 if (flag_bytemode & DREX_NO_OC0)
12984 {
12985 oc0 = 1;
12986 if (DREX_OC0 (drex_byte))
12987 BadOp ();
12988 }
12989 else
12990 oc0 = DREX_OC0 (drex_byte);
12991
12992 if (modrm.mod == 3)
12993 {
12994 /* regmem == register */
12995 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
12996 rex = rex_used = 0;
12997 /* skip modrm/drex since we don't call OP_E_extended */
12998 codep += 2;
12999 }
13000 else
13001 {
13002 /* regmem == memory, fill in appropriate REX bits */
13003 modrm_regmem = DREX_REG_MEMORY;
13004 rex = drex_byte & (REX_B | REX_X | REX_R);
13005 if (rex)
13006 rex |= REX_OPCODE;
13007 rex_used = rex;
13008 }
13009
13010 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
13011 order. */
13012 switch (oc0 + oc1)
13013 {
13014 default:
13015 BadOp ();
13016 return;
13017
13018 case 0:
13019 regs[0] = modrm_regmem;
13020 regs[1] = modrm_reg;
13021 regs[2] = drex_reg;
13022 regs[3] = drex_reg;
13023 break;
13024
13025 case 1:
13026 regs[0] = modrm_reg;
13027 regs[1] = modrm_regmem;
13028 regs[2] = drex_reg;
13029 regs[3] = drex_reg;
13030 break;
13031
13032 case 2:
13033 regs[0] = drex_reg;
13034 regs[1] = modrm_regmem;
13035 regs[2] = modrm_reg;
13036 regs[3] = drex_reg;
13037 break;
13038
13039 case 3:
13040 regs[0] = drex_reg;
13041 regs[1] = modrm_reg;
13042 regs[2] = modrm_regmem;
13043 regs[3] = drex_reg;
13044 break;
13045 }
13046
13047 /* Print out the arguments. */
13048 for (i = 0; i < 4; i++)
13049 {
13050 int j = (intel_syntax) ? 3 - i : i;
13051 if (i > 0)
13052 {
13053 *obufp++ = ',';
13054 *obufp = '\0';
13055 }
13056
13057 print_drex_arg (regs[j], bytemode, sizeflag);
13058 }
13059
13060 rex = rex_save;
13061 rex_used = rex_used_save;
13062}
13063
13064/* SSE5 instructions that have 3 arguments, and are encoded as:
13065 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset> (or)
13066 0f 25 <sub-opcode> <modrm> <optional-sib> <drex> <offset> <cmp-byte>
13067
13068 The DREX field has 1 bit (0x8) to determine how the arguments are
13069 laid out. The destination register is encoded in the DREX byte.
13070 No REX prefix is used for these instructions, since the DREX field
13071 contains the 3 extension bits provided by the REX prefix. */
13072
13073static void
13074OP_DREX3 (int flag_bytemode, int sizeflag)
13075{
13076 unsigned int drex_byte;
13077 unsigned int regs[3];
13078 unsigned int modrm_regmem;
13079 unsigned int modrm_reg;
13080 unsigned int drex_reg;
13081 int bytemode;
13082 int rex_save = rex;
13083 int rex_used_save = rex_used;
13084 int has_sib = 0;
13085 int oc0;
13086 int i;
13087
13088 bytemode = flag_bytemode & ~ DREX_MASK;
13089
13090 for (i = 0; i < 3; i++)
13091 regs[i] = DREX_REG_UNKNOWN;
13092
13093 /* Determine if we have a SIB byte in addition to MODRM before the
13094 DREX byte. */
13095 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
13096 && (modrm.mod != 3)
13097 && (modrm.rm == 4))
13098 has_sib = 1;
13099
13100 /* Get the DREX byte. */
13101 FETCH_DATA (the_info, codep + 2 + has_sib);
13102 drex_byte = codep[has_sib+1];
13103 drex_reg = DREX_XMM (drex_byte);
13104 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
13105
13106 /* Is OC0 legal? If not, hardwire oc0 == 0 */
13107 oc0 = DREX_OC0 (drex_byte);
13108 if ((flag_bytemode & DREX_NO_OC0) && oc0)
13109 BadOp ();
13110
13111 if (modrm.mod == 3)
13112 {
13113 /* regmem == register */
13114 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
13115 rex = rex_used = 0;
13116 /* skip modrm/drex since we don't call OP_E_extended. */
13117 codep += 2;
13118 }
13119 else
13120 {
13121 /* regmem == memory, fill in appropriate REX bits. */
13122 modrm_regmem = DREX_REG_MEMORY;
13123 rex = drex_byte & (REX_B | REX_X | REX_R);
13124 if (rex)
13125 rex |= REX_OPCODE;
13126 rex_used = rex;
13127 }
13128
13129 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
13130 order. */
13131 switch (oc0)
13132 {
13133 default:
13134 BadOp ();
13135 return;
13136
13137 case 0:
13138 regs[0] = modrm_regmem;
13139 regs[1] = modrm_reg;
13140 regs[2] = drex_reg;
13141 break;
13142
13143 case 1:
13144 regs[0] = modrm_reg;
13145 regs[1] = modrm_regmem;
13146 regs[2] = drex_reg;
13147 break;
13148 }
13149
13150 /* Print out the arguments. */
13151 for (i = 0; i < 3; i++)
13152 {
13153 int j = (intel_syntax) ? 2 - i : i;
13154 if (i > 0)
13155 {
13156 *obufp++ = ',';
13157 *obufp = '\0';
13158 }
13159
13160 print_drex_arg (regs[j], bytemode, sizeflag);
13161 }
13162
13163 rex = rex_save;
13164 rex_used = rex_used_save;
13165}
13166
13167/* Emit a floating point comparison for comp<xx> instructions. */
13168
13169static void
13170OP_DREX_FCMP (int bytemode ATTRIBUTE_UNUSED,
13171 int sizeflag ATTRIBUTE_UNUSED)
13172{
13173 unsigned char byte;
13174
13175 static const char *const cmp_test[] = {
13176 "eq",
13177 "lt",
13178 "le",
13179 "unord",
13180 "ne",
13181 "nlt",
13182 "nle",
13183 "ord",
13184 "ueq",
13185 "ult",
13186 "ule",
13187 "false",
13188 "une",
13189 "unlt",
13190 "unle",
13191 "true"
13192 };
13193
13194 FETCH_DATA (the_info, codep + 1);
13195 byte = *codep & 0xff;
13196
13197 if (byte >= ARRAY_SIZE (cmp_test)
13198 || obuf[0] != 'c'
13199 || obuf[1] != 'o'
13200 || obuf[2] != 'm')
13201 {
13202 /* The instruction isn't one we know about, so just append the
13203 extension byte as a numeric value. */
13204 OP_I (b_mode, 0);
13205 }
13206
13207 else
13208 {
13209 sprintf (scratchbuf, "com%s%s", cmp_test[byte], obuf+3);
13210 strcpy (obuf, scratchbuf);
13211 codep++;
13212 }
13213}
13214
13215/* Emit an integer point comparison for pcom<xx> instructions,
13216 rewriting the instruction to have the test inside of it. */
13217
13218static void
13219OP_DREX_ICMP (int bytemode ATTRIBUTE_UNUSED,
13220 int sizeflag ATTRIBUTE_UNUSED)
13221{
13222 unsigned char byte;
13223
13224 static const char *const cmp_test[] = {
13225 "lt",
13226 "le",
13227 "gt",
13228 "ge",
13229 "eq",
13230 "ne",
13231 "false",
13232 "true"
13233 };
13234
13235 FETCH_DATA (the_info, codep + 1);
13236 byte = *codep & 0xff;
13237
13238 if (byte >= ARRAY_SIZE (cmp_test)
13239 || obuf[0] != 'p'
13240 || obuf[1] != 'c'
13241 || obuf[2] != 'o'
13242 || obuf[3] != 'm')
13243 {
13244 /* The instruction isn't one we know about, so just print the
13245 comparison test byte as a numeric value. */
13246 OP_I (b_mode, 0);
13247 }
13248
13249 else
13250 {
13251 sprintf (scratchbuf, "pcom%s%s", cmp_test[byte], obuf+4);
13252 strcpy (obuf, scratchbuf);
13253 codep++;
13254 }
13255}
c0f3af97
L		 13256
13257/* Display the destination register operand for instructions with
13258 VEX. */
13259
13260static void
13261OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13262{
13263 if (!need_vex)
13264 abort ();
13265
13266 if (!need_vex_reg)
13267 return;
13268
13269 switch (vex.length)
13270 {
13271 case 128:
13272 switch (bytemode)
13273 {
13274 case vex_mode:
13275 case vex128_mode:
13276 break;
13277 default:
13278 abort ();
13279 return;
13280 }
13281
13282 sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
13283 break;
13284 case 256:
13285 switch (bytemode)
13286 {
13287 case vex_mode:
13288 case vex256_mode:
13289 break;
13290 default:
13291 abort ();
13292 return;
13293 }
13294
13295 sprintf (scratchbuf, "%%ymm%d", vex.register_specifier);
13296 break;
13297 default:
13298 abort ();
13299 break;
13300 }
13301 oappend (scratchbuf + intel_syntax);
13302}
13303
dae39acc 13304/* Get the VEX immediate byte without moving codep. */
c0f3af97 13305
dae39acc
L		 13306static unsigned char
13307get_vex_imm8 (int sizeflag)
13308{
13309 int bytes_before_imm = 0;
c0f3af97 13310
dae39acc
L		 13311 /* Skip mod/rm byte. */
13312 MODRM_CHECK;
13313 codep++;
c0f3af97 13314
dae39acc
L		 13315 if (modrm.mod != 3)
13316 {
13317 /* There are SIB/displacement bytes. */
13318 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
c0f3af97 13319 {
dae39acc
L		 13320 /* 32/64 bit address mode */
13321 int base = modrm.rm;
c0f3af97 13322
dae39acc
L		 13323 /* Check SIB byte. */
13324 if (base == 4)
13325 {
13326 FETCH_DATA (the_info, codep + 1);
13327 base = *codep & 7;
13328 bytes_before_imm++;
13329 }
c0f3af97 13330
dae39acc
L		 13331 switch (modrm.mod)
13332 {
13333 case 0:
13334 /* When modrm.rm == 5 or modrm.rm == 4 and base in
13335 SIB == 5, there is a 4 byte displacement. */
13336 if (base != 5)
13337 /* No displacement. */
13338 break;
13339 case 2:
13340 /* 4 byte displacement. */
13341 bytes_before_imm += 4;
13342 break;
13343 case 1:
13344 /* 1 byte displacement. */
13345 bytes_before_imm++;
13346 break;
c0f3af97 13347 }
dae39acc
L		 13348 }
13349 else
13350 { /* 16 bit address mode */
13351 switch (modrm.mod)
13352 {
13353 case 0:
13354 /* When modrm.rm == 6, there is a 2 byte displacement. */
13355 if (modrm.rm != 6)
13356 /* No displacement. */
13357 break;
13358 case 2:
13359 /* 2 byte displacement. */
13360 bytes_before_imm += 2;
13361 break;
13362 case 1:
13363 /* 1 byte displacement. */
13364 bytes_before_imm++;
13365 break;
c0f3af97
L		 13366 }
13367 }
c0f3af97
L		 13368 }
13369
dae39acc
L		 13370 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
13371 return codep [bytes_before_imm];
13372}
13373
13374static void
13375OP_EX_VexReg (int bytemode, int sizeflag, int reg)
13376{
c0f3af97
L		 13377 if (reg == -1 && modrm.mod != 3)
13378 {
13379 OP_E_memory (bytemode, sizeflag, 0);
13380 return;
13381 }
13382 else
13383 {
13384 if (reg == -1)
13385 {
13386 reg = modrm.rm;
13387 USED_REX (REX_B);
13388 if (rex & REX_B)
13389 reg += 8;
13390 }
13391 else if (reg > 7 && address_mode != mode_64bit)
13392 BadOp ();
13393 }
13394
13395 switch (vex.length)
13396 {
13397 case 128:
13398 sprintf (scratchbuf, "%%xmm%d", reg);
13399 break;
13400 case 256:
13401 sprintf (scratchbuf, "%%ymm%d", reg);
13402 break;
13403 default:
13404 abort ();
13405 }
13406 oappend (scratchbuf + intel_syntax);
13407}
13408
dae39acc
L		 13409static void
13410OP_EX_VexImmW (int bytemode, int sizeflag)
13411{
13412 int reg = -1;
13413 static unsigned char vex_imm8;
13414
13415 if (!vex_w_done)
13416 {
13417 vex_imm8 = get_vex_imm8 (sizeflag);
13418 if (vex.w)
13419 reg = vex_imm8 >> 4;
13420 vex_w_done = 1;
13421 }
13422 else
13423 {
13424 if (!vex.w)
13425 reg = vex_imm8 >> 4;
13426 }
13427
13428 OP_EX_VexReg (bytemode, sizeflag, reg);
13429}
13430
13431static void
13432OP_EX_VexW (int bytemode, int sizeflag)
13433{
13434 int reg = -1;
13435
13436 if (!vex_w_done)
13437 {
13438 vex_w_done = 1;
13439 if (vex.w)
13440 reg = vex.register_specifier;
13441 }
13442 else
13443 {
13444 if (!vex.w)
13445 reg = vex.register_specifier;
13446 }
13447
13448 OP_EX_VexReg (bytemode, sizeflag, reg);
13449}
13450
13451static void
13452OP_VEX_FMA (int bytemode, int sizeflag)
13453{
13454 int reg = get_vex_imm8 (sizeflag) >> 4;
13455
13456 if (reg > 7 && address_mode != mode_64bit)
13457 BadOp ();
13458
13459 switch (vex.length)
13460 {
13461 case 128:
13462 switch (bytemode)
13463 {
13464 case vex_mode:
13465 case vex128_mode:
13466 break;
13467 default:
13468 abort ();
13469 return;
13470 }
13471
13472 sprintf (scratchbuf, "%%xmm%d", reg);
13473 break;
13474 case 256:
13475 switch (bytemode)
13476 {
13477 case vex_mode:
13478 break;
13479 default:
13480 abort ();
13481 return;
13482 }
13483
13484 sprintf (scratchbuf, "%%ymm%d", reg);
13485 break;
13486 default:
13487 abort ();
13488 }
13489 oappend (scratchbuf + intel_syntax);
13490}
13491
c0f3af97
L		 13492static void
13493VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
13494 int sizeflag ATTRIBUTE_UNUSED)
13495{
13496 /* Skip the immediate byte and check for invalid bits. */
13497 FETCH_DATA (the_info, codep + 1);
13498 if (*codep++ & 0xf)
13499 BadOp ();
13500}
13501
13502static void
13503OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13504{
13505 int reg;
13506 FETCH_DATA (the_info, codep + 1);
13507 reg = *codep++;
13508
13509 if (bytemode != x_mode)
13510 abort ();
13511
13512 if (reg & 0xf)
13513 BadOp ();
13514
13515 reg >>= 4;
dae39acc
L		 13516 if (reg > 7 && address_mode != mode_64bit)
13517 BadOp ();
13518
c0f3af97
L		 13519 switch (vex.length)
13520 {
13521 case 128:
13522 sprintf (scratchbuf, "%%xmm%d", reg);
13523 break;
13524 case 256:
13525 sprintf (scratchbuf, "%%ymm%d", reg);
13526 break;
13527 default:
13528 abort ();
13529 }
13530 oappend (scratchbuf + intel_syntax);
13531}
13532
13533static void
13534OP_XMM_VexW (int bytemode, int sizeflag)
13535{
13536 /* Turn off the REX.W bit since it is used for swapping operands
13537 now. */
13538 rex &= ~REX_W;
13539 OP_XMM (bytemode, sizeflag);
13540}
13541
13542static void
13543OP_EX_Vex (int bytemode, int sizeflag)
13544{
13545 if (modrm.mod != 3)
13546 {
13547 if (vex.register_specifier != 0)
13548 BadOp ();
13549 need_vex_reg = 0;
13550 }
13551 OP_EX (bytemode, sizeflag);
13552}
13553
13554static void
13555OP_XMM_Vex (int bytemode, int sizeflag)
13556{
13557 if (modrm.mod != 3)
13558 {
13559 if (vex.register_specifier != 0)
13560 BadOp ();
13561 need_vex_reg = 0;
13562 }
13563 OP_XMM (bytemode, sizeflag);
13564}
13565
13566static void
13567VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13568{
13569 switch (vex.length)
13570 {
13571 case 128:
13572 strcpy (obuf, "vzeroupper");
13573 break;
13574 case 256:
13575 strcpy (obuf, "vzeroall");
13576 break;
13577 default:
13578 abort ();
13579 }
13580}
13581
13582static const char *vex_cmp_op[] = {
13583 "eq",
13584 "lt",
13585 "le",
13586 "unord",
13587 "neq",
13588 "nlt",
13589 "nle",
13590 "ord",
13591 "eq_uq",
13592 "nge",
13593 "ngt",
13594 "false",
13595 "neq_oq",
13596 "ge",
13597 "gt",
13598 "true",
13599 "eq_os",
13600 "lt_oq",
13601 "le_oq",
13602 "unord_s",
13603 "neq_us",
13604 "nlt_uq",
13605 "nle_uq",
13606 "ord_s",
13607 "eq_us",
13608 "nge_uq",
13609 "ngt_uq",
13610 "false_os",
13611 "neq_os",
13612 "ge_oq",
13613 "gt_oq",
13614 "true_us"
13615};
13616
13617static void
13618VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13619{
13620 unsigned int cmp_type;
13621
13622 FETCH_DATA (the_info, codep + 1);
13623 cmp_type = *codep++ & 0xff;
13624 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
13625 {
13626 char suffix [3];
13627 char *p = obuf + strlen (obuf) - 2;
13628 suffix[0] = p[0];
13629 suffix[1] = p[1];
13630 suffix[2] = '\0';
13631 sprintf (p, "%s%s", vex_cmp_op[cmp_type], suffix);
13632 }
13633 else
13634 {
13635 /* We have a reserved extension byte. Output it directly. */
13636 scratchbuf[0] = '$';
13637 print_operand_value (scratchbuf + 1, 1, cmp_type);
13638 oappend (scratchbuf + intel_syntax);
13639 scratchbuf[0] = '\0';
13640 }
13641}
13642
13643static const char *pclmul_op[] = {
13644 "lql",
13645 "hql",
13646 "lqh",
13647 "hqh"
13648};
13649
13650static void
13651PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13652 int sizeflag ATTRIBUTE_UNUSED)
13653{
13654 unsigned int pclmul_type;
13655
13656 FETCH_DATA (the_info, codep + 1);
13657 pclmul_type = *codep++ & 0xff;
13658 switch (pclmul_type)
13659 {
13660 case 0x10:
13661 pclmul_type = 2;
13662 break;
13663 case 0x11:
13664 pclmul_type = 3;
13665 break;
13666 default:
13667 break;
13668 }
13669 if (pclmul_type < ARRAY_SIZE (pclmul_op))
13670 {
13671 char suffix [4];
13672 char *p = obuf + strlen (obuf) - 3;
13673 suffix[0] = p[0];
13674 suffix[1] = p[1];
13675 suffix[2] = p[2];
13676 suffix[3] = '\0';
13677 sprintf (p, "%s%s", pclmul_op[pclmul_type], suffix);
13678 }
13679 else
13680 {
13681 /* We have a reserved extension byte. Output it directly. */
13682 scratchbuf[0] = '$';
13683 print_operand_value (scratchbuf + 1, 1, pclmul_type);
13684 oappend (scratchbuf + intel_syntax);
13685 scratchbuf[0] = '\0';
13686 }
13687}
13688
13689static const char *vpermil2_op[] = {
13690 "td",
13691 "td",
13692 "mo",
13693 "mz"
13694};
13695
13696static void
13697VPERMIL2_Fixup (int bytemode ATTRIBUTE_UNUSED,
13698 int sizeflag ATTRIBUTE_UNUSED)
13699{
13700 unsigned int vpermil2_type;
13701
13702 FETCH_DATA (the_info, codep + 1);
13703 vpermil2_type = *codep++ & 0xf;
13704 if (vpermil2_type < ARRAY_SIZE (vpermil2_op))
13705 {
13706 char suffix [4];
13707 char *p = obuf + strlen (obuf) - 3;
13708 suffix[0] = p[0];
13709 suffix[1] = p[1];
13710 suffix[2] = p[2];
13711 suffix[3] = '\0';
13712 sprintf (p, "%s%s", vpermil2_op[vpermil2_type], suffix);
13713 }
13714 else
13715 {
13716 /* We have a reserved extension byte. Output it directly. */
13717 scratchbuf[0] = '$';
13718 print_operand_value (scratchbuf + 1, 1, vpermil2_type);
13719 oappend (scratchbuf + intel_syntax);
13720 scratchbuf[0] = '\0';
13721 }
13722}
f1f8f695
L		 13723
13724static void
13725MOVBE_Fixup (int bytemode, int sizeflag)
13726{
13727 /* Add proper suffix to "movbe". */
13728 char *p = obuf + strlen (obuf);
13729
13730 switch (bytemode)
13731 {
13732 case v_mode:
13733 if (intel_syntax)
13734 break;
13735
13736 USED_REX (REX_W);
13737 if (sizeflag & SUFFIX_ALWAYS)
13738 {
13739 if (rex & REX_W)
13740 *p++ = 'q';
13741 else if (sizeflag & DFLAG)
13742 *p++ = 'l';
13743 else
13744 *p++ = 'w';
13745 }
13746 used_prefixes |= (prefixes & PREFIX_DATA);
13747 break;
13748 default:
13749 oappend (INTERNAL_DISASSEMBLER_ERROR);
13750 break;
13751 }
13752 *p = '\0';
13753
13754 OP_M (bytemode, sizeflag);
13755}
GDB Binutils - Deliverables
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