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* gas/all/gas.exp: Remove a29k and m88k support.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
aef6203b 3 2000, 2001, 2002, 2003, 2004, 2005
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
29b0f896
AM		 66static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70static INLINE int fits_in_signed_word PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 73static int smallest_imm_type PARAMS ((offsetT));
74static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 75static int add_prefix PARAMS ((unsigned int));
3e73aa7c 76static void set_code_flag PARAMS ((int));
47926f60 77static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 78static void set_intel_syntax PARAMS ((int));
e413e4e9 79static void set_cpu_arch PARAMS ((int));
6482c264
NC		 80#ifdef TE_PE
81static void pe_directive_secrel PARAMS ((int));
82#endif
29b0f896
AM		 83static char *output_invalid PARAMS ((int c));
84static int i386_operand PARAMS ((char *operand_string));
85static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
86static const reg_entry *parse_register PARAMS ((char *reg_string,
87 char **end_op));
88static char *parse_insn PARAMS ((char *, char *));
89static char *parse_operands PARAMS ((char *, const char *));
90static void swap_operands PARAMS ((void));
91static void optimize_imm PARAMS ((void));
92static void optimize_disp PARAMS ((void));
93static int match_template PARAMS ((void));
94static int check_string PARAMS ((void));
95static int process_suffix PARAMS ((void));
96static int check_byte_reg PARAMS ((void));
97static int check_long_reg PARAMS ((void));
98static int check_qword_reg PARAMS ((void));
99static int check_word_reg PARAMS ((void));
100static int finalize_imm PARAMS ((void));
101static int process_operands PARAMS ((void));
102static const seg_entry *build_modrm_byte PARAMS ((void));
103static void output_insn PARAMS ((void));
104static void output_branch PARAMS ((void));
105static void output_jump PARAMS ((void));
106static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 107static void output_imm PARAMS ((fragS *insn_start_frag,
108 offsetT insn_start_off));
109static void output_disp PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
29b0f896
AM		 111#ifndef I386COFF
112static void s_bss PARAMS ((int));
252b5132 113#endif
17d4e2a2
L		 114#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
115static void handle_large_common (int small ATTRIBUTE_UNUSED);
116#endif
252b5132 117
a847613f 118static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 119
252b5132 120/* 'md_assemble ()' gathers together information and puts it into a
47926f60 121 i386_insn. */
252b5132 122
520dc8e8
AM		 123union i386_op
124 {
125 expressionS *disps;
126 expressionS *imms;
127 const reg_entry *regs;
128 };
129
252b5132
RH		 130struct _i386_insn
131 {
47926f60 132 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 133 template tm;
134
135 /* SUFFIX holds the instruction mnemonic suffix if given.
136 (e.g. 'l' for 'movl') */
137 char suffix;
138
47926f60 139 /* OPERANDS gives the number of given operands. */
252b5132
RH		 140 unsigned int operands;
141
142 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
143 of given register, displacement, memory operands and immediate
47926f60 144 operands. */
252b5132
RH		 145 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
146
147 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 148 use OP[i] for the corresponding operand. */
252b5132
RH		 149 unsigned int types[MAX_OPERANDS];
150
520dc8e8
AM		 151 /* Displacement expression, immediate expression, or register for each
152 operand. */
153 union i386_op op[MAX_OPERANDS];
252b5132 154
3e73aa7c
JH		 155 /* Flags for operands. */
156 unsigned int flags[MAX_OPERANDS];
157#define Operand_PCrel 1
158
252b5132 159 /* Relocation type for operand */
f86103b7 160 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 161
252b5132
RH		 162 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
163 the base index byte below. */
164 const reg_entry *base_reg;
165 const reg_entry *index_reg;
166 unsigned int log2_scale_factor;
167
168 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 169 explicit segment overrides are given. */
ce8a8b2f 170 const seg_entry *seg[2];
252b5132
RH		 171
172 /* PREFIX holds all the given prefix opcodes (usually null).
173 PREFIXES is the number of prefix opcodes. */
174 unsigned int prefixes;
175 unsigned char prefix[MAX_PREFIXES];
176
177 /* RM and SIB are the modrm byte and the sib byte where the
178 addressing modes of this insn are encoded. */
179
180 modrm_byte rm;
3e73aa7c 181 rex_byte rex;
252b5132
RH		 182 sib_byte sib;
183 };
184
185typedef struct _i386_insn i386_insn;
186
187/* List of chars besides those in app.c:symbol_chars that can start an
188 operand. Used to prevent the scrubber eating vital white-space. */
32137342 189const char extra_symbol_chars[] = "*%-(["
252b5132 190#ifdef LEX_AT
32137342
NC		 191 "@"
192#endif
193#ifdef LEX_QM
194 "?"
252b5132 195#endif
32137342 196 ;
252b5132 197
29b0f896
AM		 198#if (defined (TE_I386AIX) \
199 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
200 && !defined (TE_LINUX) \
32137342 201 && !defined (TE_NETWARE) \
29b0f896
AM		 202 && !defined (TE_FreeBSD) \
203 && !defined (TE_NetBSD)))
252b5132 204/* This array holds the chars that always start a comment. If the
ce8a8b2f 205 pre-processor is disabled, these aren't very useful. */
252b5132
RH		 206const char comment_chars[] = "#/";
207#define PREFIX_SEPARATOR '\\'
252b5132
RH		 208
209/* This array holds the chars that only start a comment at the beginning of
210 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 211 .line and .file directives will appear in the pre-processed output.
212 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 213 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 214 #NO_APP at the beginning of its output.
215 Also note that comments started like this one will always work if
252b5132 216 '/' isn't otherwise defined. */
0d9f6d04 217const char line_comment_chars[] = "#";
29b0f896 218
252b5132 219#else
29b0f896
AM		 220/* Putting '/' here makes it impossible to use the divide operator.
221 However, we need it for compatibility with SVR4 systems. */
222const char comment_chars[] = "#";
223#define PREFIX_SEPARATOR '/'
224
0d9f6d04 225const char line_comment_chars[] = "/#";
252b5132
RH		 226#endif
227
63a0b638 228const char line_separator_chars[] = ";";
252b5132 229
ce8a8b2f
AM		 230/* Chars that can be used to separate mant from exp in floating point
231 nums. */
252b5132
RH		 232const char EXP_CHARS[] = "eE";
233
ce8a8b2f
AM		 234/* Chars that mean this number is a floating point constant
235 As in 0f12.456
236 or 0d1.2345e12. */
252b5132
RH		 237const char FLT_CHARS[] = "fFdDxX";
238
ce8a8b2f 239/* Tables for lexical analysis. */
252b5132
RH		 240static char mnemonic_chars[256];
241static char register_chars[256];
242static char operand_chars[256];
243static char identifier_chars[256];
244static char digit_chars[256];
245
ce8a8b2f 246/* Lexical macros. */
252b5132
RH		 247#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
248#define is_operand_char(x) (operand_chars[(unsigned char) x])
249#define is_register_char(x) (register_chars[(unsigned char) x])
250#define is_space_char(x) ((x) == ' ')
251#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
252#define is_digit_char(x) (digit_chars[(unsigned char) x])
253
0234cb7c 254/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 255static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
256
257/* md_assemble() always leaves the strings it's passed unaltered. To
258 effect this we maintain a stack of saved characters that we've smashed
259 with '\0's (indicating end of strings for various sub-fields of the
47926f60 260 assembler instruction). */
252b5132 261static char save_stack[32];
ce8a8b2f 262static char *save_stack_p;
252b5132
RH		 263#define END_STRING_AND_SAVE(s) \
264 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
265#define RESTORE_END_STRING(s) \
266 do { *(s) = *--save_stack_p; } while (0)
267
47926f60 268/* The instruction we're assembling. */
252b5132
RH		 269static i386_insn i;
270
271/* Possible templates for current insn. */
272static const templates *current_templates;
273
47926f60 274/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 275static expressionS disp_expressions[2], im_expressions[2];
276
47926f60
KH		 277/* Current operand we are working on. */
278static int this_operand;
252b5132 279
3e73aa7c
JH		 280/* We support four different modes. FLAG_CODE variable is used to distinguish
281 these. */
282
283enum flag_code {
284 CODE_32BIT,
285 CODE_16BIT,
286 CODE_64BIT };
f3c180ae 287#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 288
289static enum flag_code flag_code;
290static int use_rela_relocations = 0;
291
292/* The names used to print error messages. */
b77a7acd 293static const char *flag_code_names[] =
3e73aa7c
JH		 294 {
295 "32",
296 "16",
297 "64"
298 };
252b5132 299
47926f60
KH		 300/* 1 for intel syntax,
301 0 if att syntax. */
302static int intel_syntax = 0;
252b5132 303
47926f60
KH		 304/* 1 if register prefix % not required. */
305static int allow_naked_reg = 0;
252b5132 306
47926f60
KH		 307/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
308 leave, push, and pop instructions so that gcc has the same stack
309 frame as in 32 bit mode. */
310static char stackop_size = '\0';
eecb386c 311
12b55ccc
L		 312/* Non-zero to optimize code alignment. */
313int optimize_align_code = 1;
314
47926f60
KH		 315/* Non-zero to quieten some warnings. */
316static int quiet_warnings = 0;
a38cf1db 317
47926f60
KH		 318/* CPU name. */
319static const char *cpu_arch_name = NULL;
5c6af06e 320static const char *cpu_sub_arch_name = NULL;
a38cf1db 321
47926f60 322/* CPU feature flags. */
29b0f896 323static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 324
fddf5b5b
AM		 325/* If set, conditional jumps are not automatically promoted to handle
326 larger than a byte offset. */
327static unsigned int no_cond_jump_promotion = 0;
328
29b0f896 329/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 330static symbolS *GOT_symbol;
29b0f896 331
a4447b93
RH		 332/* The dwarf2 return column, adjusted for 32 or 64 bit. */
333unsigned int x86_dwarf2_return_column;
334
335/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
336int x86_cie_data_alignment;
337
252b5132 338/* Interface to relax_segment.
fddf5b5b
AM		 339 There are 3 major relax states for 386 jump insns because the
340 different types of jumps add different sizes to frags when we're
341 figuring out what sort of jump to choose to reach a given label. */
252b5132 342
47926f60 343/* Types. */
93c2a809
AM		 344#define UNCOND_JUMP 0
345#define COND_JUMP 1
346#define COND_JUMP86 2
fddf5b5b 347
47926f60 348/* Sizes. */
252b5132
RH		 349#define CODE16 1
350#define SMALL 0
29b0f896 351#define SMALL16 (SMALL | CODE16)
252b5132 352#define BIG 2
29b0f896 353#define BIG16 (BIG | CODE16)
252b5132
RH		 354
355#ifndef INLINE
356#ifdef __GNUC__
357#define INLINE __inline__
358#else
359#define INLINE
360#endif
361#endif
362
fddf5b5b
AM		 363#define ENCODE_RELAX_STATE(type, size) \
364 ((relax_substateT) (((type) << 2) | (size)))
365#define TYPE_FROM_RELAX_STATE(s) \
366 ((s) >> 2)
367#define DISP_SIZE_FROM_RELAX_STATE(s) \
368 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 369
370/* This table is used by relax_frag to promote short jumps to long
371 ones where necessary. SMALL (short) jumps may be promoted to BIG
372 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
373 don't allow a short jump in a 32 bit code segment to be promoted to
374 a 16 bit offset jump because it's slower (requires data size
375 prefix), and doesn't work, unless the destination is in the bottom
376 64k of the code segment (The top 16 bits of eip are zeroed). */
377
378const relax_typeS md_relax_table[] =
379{
24eab124
AM		 380 /* The fields are:
381 1) most positive reach of this state,
382 2) most negative reach of this state,
93c2a809 383 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 384 4) which index into the table to try if we can't fit into this one. */
252b5132 385
fddf5b5b 386 /* UNCOND_JUMP states. */
93c2a809
AM		 387 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
388 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
389 /* dword jmp adds 4 bytes to frag:
390 0 extra opcode bytes, 4 displacement bytes. */
252b5132 391 {0, 0, 4, 0},
93c2a809
AM		 392 /* word jmp adds 2 byte2 to frag:
393 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 394 {0, 0, 2, 0},
395
93c2a809
AM		 396 /* COND_JUMP states. */
397 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
399 /* dword conditionals adds 5 bytes to frag:
400 1 extra opcode byte, 4 displacement bytes. */
401 {0, 0, 5, 0},
fddf5b5b 402 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 403 1 extra opcode byte, 2 displacement bytes. */
404 {0, 0, 3, 0},
405
406 /* COND_JUMP86 states. */
407 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
409 /* dword conditionals adds 5 bytes to frag:
410 1 extra opcode byte, 4 displacement bytes. */
411 {0, 0, 5, 0},
412 /* word conditionals add 4 bytes to frag:
413 1 displacement byte and a 3 byte long branch insn. */
414 {0, 0, 4, 0}
252b5132
RH		 415};
416
e413e4e9
AM		 417static const arch_entry cpu_arch[] = {
418 {"i8086", Cpu086 },
419 {"i186", Cpu086|Cpu186 },
420 {"i286", Cpu086|Cpu186|Cpu286 },
421 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
422 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
5c6af06e
JB		 423 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
424 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
425 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
426 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
427 {"pentiumii", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX },
428 {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE },
429 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
430 {"prescott", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI },
431 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX },
432 {"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
433 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
434 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
30123838 435 {"opteron", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
5c6af06e
JB		 436 {".mmx", CpuMMX },
437 {".sse", CpuMMX|CpuMMX2|CpuSSE },
438 {".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
bf50992e 439 {".sse3", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3 },
5c6af06e
JB		 440 {".3dnow", CpuMMX|Cpu3dnow },
441 {".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
442 {".padlock", CpuPadLock },
30123838
JB		 443 {".pacifica", CpuSVME },
444 {".svme", CpuSVME },
e413e4e9
AM		 445 {NULL, 0 }
446};
447
29b0f896
AM		 448const pseudo_typeS md_pseudo_table[] =
449{
450#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
451 {"align", s_align_bytes, 0},
452#else
453 {"align", s_align_ptwo, 0},
454#endif
455 {"arch", set_cpu_arch, 0},
456#ifndef I386COFF
457 {"bss", s_bss, 0},
458#endif
459 {"ffloat", float_cons, 'f'},
460 {"dfloat", float_cons, 'd'},
461 {"tfloat", float_cons, 'x'},
462 {"value", cons, 2},
463 {"noopt", s_ignore, 0},
464 {"optim", s_ignore, 0},
465 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
466 {"code16", set_code_flag, CODE_16BIT},
467 {"code32", set_code_flag, CODE_32BIT},
468 {"code64", set_code_flag, CODE_64BIT},
469 {"intel_syntax", set_intel_syntax, 1},
470 {"att_syntax", set_intel_syntax, 0},
c6682705 471 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
29b0f896 472 {"loc", dwarf2_directive_loc, 0},
3b22753a
L		 473#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
474 {"largecomm", handle_large_common, 0},
475#endif
6482c264
NC		 476#ifdef TE_PE
477 {"secrel32", pe_directive_secrel, 0},
478#endif
29b0f896
AM		 479 {0, 0, 0}
480};
481
482/* For interface with expression (). */
483extern char *input_line_pointer;
484
485/* Hash table for instruction mnemonic lookup. */
486static struct hash_control *op_hash;
487
488/* Hash table for register lookup. */
489static struct hash_control *reg_hash;
490\f
252b5132
RH		 491void
492i386_align_code (fragP, count)
493 fragS *fragP;
494 int count;
495{
ce8a8b2f
AM		 496 /* Various efficient no-op patterns for aligning code labels.
497 Note: Don't try to assemble the instructions in the comments.
498 0L and 0w are not legal. */
252b5132
RH		 499 static const char f32_1[] =
500 {0x90}; /* nop */
501 static const char f32_2[] =
502 {0x89,0xf6}; /* movl %esi,%esi */
503 static const char f32_3[] =
504 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
505 static const char f32_4[] =
506 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
507 static const char f32_5[] =
508 {0x90, /* nop */
509 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
510 static const char f32_6[] =
511 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
512 static const char f32_7[] =
513 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
514 static const char f32_8[] =
515 {0x90, /* nop */
516 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
517 static const char f32_9[] =
518 {0x89,0xf6, /* movl %esi,%esi */
519 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
520 static const char f32_10[] =
521 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
522 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
523 static const char f32_11[] =
524 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
525 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
526 static const char f32_12[] =
527 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
528 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
529 static const char f32_13[] =
530 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
531 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
532 static const char f32_14[] =
533 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
534 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
535 static const char f32_15[] =
536 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
537 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 538 static const char f16_3[] =
539 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 540 static const char f16_4[] =
541 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
542 static const char f16_5[] =
543 {0x90, /* nop */
544 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
545 static const char f16_6[] =
546 {0x89,0xf6, /* mov %si,%si */
547 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
548 static const char f16_7[] =
549 {0x8d,0x74,0x00, /* lea 0(%si),%si */
550 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
551 static const char f16_8[] =
552 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
553 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
554 static const char *const f32_patt[] = {
555 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
556 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
557 };
558 static const char *const f16_patt[] = {
c3332e24 559 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 560 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
561 };
562
33fef721
JH		 563 if (count <= 0 || count > 15)
564 return;
3e73aa7c 565
33fef721
JH		 566 /* The recommended way to pad 64bit code is to use NOPs preceded by
567 maximally four 0x66 prefixes. Balance the size of nops. */
568 if (flag_code == CODE_64BIT)
252b5132 569 {
33fef721
JH		 570 int i;
571 int nnops = (count + 3) / 4;
572 int len = count / nnops;
573 int remains = count - nnops * len;
574 int pos = 0;
575
576 for (i = 0; i < remains; i++)
252b5132 577 {
33fef721
JH		 578 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
579 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
580 pos += len + 1;
581 }
582 for (; i < nnops; i++)
583 {
584 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
585 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
586 pos += len;
252b5132 587 }
252b5132 588 }
33fef721
JH		 589 else
590 if (flag_code == CODE_16BIT)
591 {
592 memcpy (fragP->fr_literal + fragP->fr_fix,
593 f16_patt[count - 1], count);
594 if (count > 8)
595 /* Adjust jump offset. */
596 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
597 }
598 else
599 memcpy (fragP->fr_literal + fragP->fr_fix,
600 f32_patt[count - 1], count);
601 fragP->fr_var = count;
252b5132
RH		 602}
603
252b5132
RH		 604static INLINE unsigned int
605mode_from_disp_size (t)
606 unsigned int t;
607{
3e73aa7c 608 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 609}
610
611static INLINE int
612fits_in_signed_byte (num)
847f7ad4 613 offsetT num;
252b5132
RH		 614{
615 return (num >= -128) && (num <= 127);
47926f60 616}
252b5132
RH		 617
618static INLINE int
619fits_in_unsigned_byte (num)
847f7ad4 620 offsetT num;
252b5132
RH		 621{
622 return (num & 0xff) == num;
47926f60 623}
252b5132
RH		 624
625static INLINE int
626fits_in_unsigned_word (num)
847f7ad4 627 offsetT num;
252b5132
RH		 628{
629 return (num & 0xffff) == num;
47926f60 630}
252b5132
RH		 631
632static INLINE int
633fits_in_signed_word (num)
847f7ad4 634 offsetT num;
252b5132
RH		 635{
636 return (-32768 <= num) && (num <= 32767);
47926f60 637}
3e73aa7c
JH		 638static INLINE int
639fits_in_signed_long (num)
640 offsetT num ATTRIBUTE_UNUSED;
641{
642#ifndef BFD64
643 return 1;
644#else
645 return (!(((offsetT) -1 << 31) & num)
646 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
647#endif
648} /* fits_in_signed_long() */
649static INLINE int
650fits_in_unsigned_long (num)
651 offsetT num ATTRIBUTE_UNUSED;
652{
653#ifndef BFD64
654 return 1;
655#else
656 return (num & (((offsetT) 2 << 31) - 1)) == num;
657#endif
658} /* fits_in_unsigned_long() */
252b5132
RH		 659
660static int
661smallest_imm_type (num)
847f7ad4 662 offsetT num;
252b5132 663{
a847613f 664 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 665 {
666 /* This code is disabled on the 486 because all the Imm1 forms
667 in the opcode table are slower on the i486. They're the
668 versions with the implicitly specified single-position
669 displacement, which has another syntax if you really want to
670 use that form. */
671 if (num == 1)
3e73aa7c 672 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 673 }
252b5132 674 return (fits_in_signed_byte (num)
3e73aa7c 675 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 676 : fits_in_unsigned_byte (num)
3e73aa7c 677 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 678 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 679 ? (Imm16 | Imm32 | Imm32S | Imm64)
680 : fits_in_signed_long (num)
681 ? (Imm32 | Imm32S | Imm64)
682 : fits_in_unsigned_long (num)
683 ? (Imm32 | Imm64)
684 : Imm64);
47926f60 685}
252b5132 686
847f7ad4
AM		 687static offsetT
688offset_in_range (val, size)
689 offsetT val;
690 int size;
691{
508866be 692 addressT mask;
ba2adb93 693
847f7ad4
AM		 694 switch (size)
695 {
508866be
L		 696 case 1: mask = ((addressT) 1 << 8) - 1; break;
697 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 698 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 699#ifdef BFD64
700 case 8: mask = ((addressT) 2 << 63) - 1; break;
701#endif
47926f60 702 default: abort ();
847f7ad4
AM		 703 }
704
ba2adb93 705 /* If BFD64, sign extend val. */
3e73aa7c
JH		 706 if (!use_rela_relocations)
707 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
708 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 709
47926f60 710 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 711 {
712 char buf1[40], buf2[40];
713
714 sprint_value (buf1, val);
715 sprint_value (buf2, val & mask);
716 as_warn (_("%s shortened to %s"), buf1, buf2);
717 }
718 return val & mask;
719}
720
252b5132
RH		 721/* Returns 0 if attempting to add a prefix where one from the same
722 class already exists, 1 if non rep/repne added, 2 if rep/repne
723 added. */
724static int
725add_prefix (prefix)
726 unsigned int prefix;
727{
728 int ret = 1;
729 int q;
730
29b0f896
AM		 731 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
732 && flag_code == CODE_64BIT)
3e73aa7c
JH		 733 q = REX_PREFIX;
734 else
735 switch (prefix)
736 {
737 default:
738 abort ();
739
740 case CS_PREFIX_OPCODE:
741 case DS_PREFIX_OPCODE:
742 case ES_PREFIX_OPCODE:
743 case FS_PREFIX_OPCODE:
744 case GS_PREFIX_OPCODE:
745 case SS_PREFIX_OPCODE:
746 q = SEG_PREFIX;
747 break;
252b5132 748
3e73aa7c
JH		 749 case REPNE_PREFIX_OPCODE:
750 case REPE_PREFIX_OPCODE:
751 ret = 2;
752 /* fall thru */
753 case LOCK_PREFIX_OPCODE:
754 q = LOCKREP_PREFIX;
755 break;
252b5132 756
3e73aa7c
JH		 757 case FWAIT_OPCODE:
758 q = WAIT_PREFIX;
759 break;
252b5132 760
3e73aa7c
JH		 761 case ADDR_PREFIX_OPCODE:
762 q = ADDR_PREFIX;
763 break;
252b5132 764
3e73aa7c
JH		 765 case DATA_PREFIX_OPCODE:
766 q = DATA_PREFIX;
767 break;
768 }
252b5132 769
29b0f896 770 if (i.prefix[q] != 0)
252b5132
RH		 771 {
772 as_bad (_("same type of prefix used twice"));
773 return 0;
774 }
775
776 i.prefixes += 1;
777 i.prefix[q] = prefix;
778 return ret;
779}
780
781static void
3e73aa7c 782set_code_flag (value)
e5cb08ac 783 int value;
eecb386c 784{
3e73aa7c
JH		 785 flag_code = value;
786 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
787 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
788 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
789 {
790 as_bad (_("64bit mode not supported on this CPU."));
791 }
792 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
793 {
794 as_bad (_("32bit mode not supported on this CPU."));
795 }
eecb386c
AM		 796 stackop_size = '\0';
797}
798
799static void
3e73aa7c
JH		 800set_16bit_gcc_code_flag (new_code_flag)
801 int new_code_flag;
252b5132 802{
3e73aa7c
JH		 803 flag_code = new_code_flag;
804 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
805 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 806 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 807}
808
809static void
810set_intel_syntax (syntax_flag)
eecb386c 811 int syntax_flag;
252b5132
RH		 812{
813 /* Find out if register prefixing is specified. */
814 int ask_naked_reg = 0;
815
816 SKIP_WHITESPACE ();
29b0f896 817 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 818 {
819 char *string = input_line_pointer;
820 int e = get_symbol_end ();
821
47926f60 822 if (strcmp (string, "prefix") == 0)
252b5132 823 ask_naked_reg = 1;
47926f60 824 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 825 ask_naked_reg = -1;
826 else
d0b47220 827 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 828 *input_line_pointer = e;
829 }
830 demand_empty_rest_of_line ();
c3332e24 831
252b5132
RH		 832 intel_syntax = syntax_flag;
833
834 if (ask_naked_reg == 0)
f86103b7
AM		 835 allow_naked_reg = (intel_syntax
836 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 837 else
838 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a
JB		 839
840 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
841 identifier_chars['$'] = intel_syntax ? '$' : 0;
252b5132
RH		 842}
843
e413e4e9
AM		 844static void
845set_cpu_arch (dummy)
47926f60 846 int dummy ATTRIBUTE_UNUSED;
e413e4e9 847{
47926f60 848 SKIP_WHITESPACE ();
e413e4e9 849
29b0f896 850 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 851 {
852 char *string = input_line_pointer;
853 int e = get_symbol_end ();
854 int i;
855
856 for (i = 0; cpu_arch[i].name; i++)
857 {
858 if (strcmp (string, cpu_arch[i].name) == 0)
859 {
5c6af06e
JB		 860 if (*string != '.')
861 {
862 cpu_arch_name = cpu_arch[i].name;
863 cpu_sub_arch_name = NULL;
864 cpu_arch_flags = (cpu_arch[i].flags
865 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
866 break;
867 }
868 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
869 {
870 cpu_sub_arch_name = cpu_arch[i].name;
871 cpu_arch_flags |= cpu_arch[i].flags;
872 }
873 *input_line_pointer = e;
874 demand_empty_rest_of_line ();
875 return;
e413e4e9
AM		 876 }
877 }
878 if (!cpu_arch[i].name)
879 as_bad (_("no such architecture: `%s'"), string);
880
881 *input_line_pointer = e;
882 }
883 else
884 as_bad (_("missing cpu architecture"));
885
fddf5b5b
AM		 886 no_cond_jump_promotion = 0;
887 if (*input_line_pointer == ','
29b0f896 888 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 889 {
890 char *string = ++input_line_pointer;
891 int e = get_symbol_end ();
892
893 if (strcmp (string, "nojumps") == 0)
894 no_cond_jump_promotion = 1;
895 else if (strcmp (string, "jumps") == 0)
896 ;
897 else
898 as_bad (_("no such architecture modifier: `%s'"), string);
899
900 *input_line_pointer = e;
901 }
902
e413e4e9
AM		 903 demand_empty_rest_of_line ();
904}
905
b9d79e03
JH		 906unsigned long
907i386_mach ()
908{
909 if (!strcmp (default_arch, "x86_64"))
910 return bfd_mach_x86_64;
911 else if (!strcmp (default_arch, "i386"))
912 return bfd_mach_i386_i386;
913 else
914 as_fatal (_("Unknown architecture"));
915}
b9d79e03 916\f
252b5132
RH		 917void
918md_begin ()
919{
920 const char *hash_err;
921
47926f60 922 /* Initialize op_hash hash table. */
252b5132
RH		 923 op_hash = hash_new ();
924
925 {
29b0f896
AM		 926 const template *optab;
927 templates *core_optab;
252b5132 928
47926f60
KH		 929 /* Setup for loop. */
930 optab = i386_optab;
252b5132
RH		 931 core_optab = (templates *) xmalloc (sizeof (templates));
932 core_optab->start = optab;
933
934 while (1)
935 {
936 ++optab;
937 if (optab->name == NULL
938 || strcmp (optab->name, (optab - 1)->name) != 0)
939 {
940 /* different name --> ship out current template list;
47926f60 941 add to hash table; & begin anew. */
252b5132
RH		 942 core_optab->end = optab;
943 hash_err = hash_insert (op_hash,
944 (optab - 1)->name,
945 (PTR) core_optab);
946 if (hash_err)
947 {
252b5132
RH		 948 as_fatal (_("Internal Error: Can't hash %s: %s"),
949 (optab - 1)->name,
950 hash_err);
951 }
952 if (optab->name == NULL)
953 break;
954 core_optab = (templates *) xmalloc (sizeof (templates));
955 core_optab->start = optab;
956 }
957 }
958 }
959
47926f60 960 /* Initialize reg_hash hash table. */
252b5132
RH		 961 reg_hash = hash_new ();
962 {
29b0f896 963 const reg_entry *regtab;
252b5132
RH		 964
965 for (regtab = i386_regtab;
966 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
967 regtab++)
968 {
969 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
970 if (hash_err)
3e73aa7c
JH		 971 as_fatal (_("Internal Error: Can't hash %s: %s"),
972 regtab->reg_name,
973 hash_err);
252b5132
RH		 974 }
975 }
976
47926f60 977 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 978 {
29b0f896
AM		 979 int c;
980 char *p;
252b5132
RH		 981
982 for (c = 0; c < 256; c++)
983 {
3882b010 984 if (ISDIGIT (c))
252b5132
RH		 985 {
986 digit_chars[c] = c;
987 mnemonic_chars[c] = c;
988 register_chars[c] = c;
989 operand_chars[c] = c;
990 }
3882b010 991 else if (ISLOWER (c))
252b5132
RH		 992 {
993 mnemonic_chars[c] = c;
994 register_chars[c] = c;
995 operand_chars[c] = c;
996 }
3882b010 997 else if (ISUPPER (c))
252b5132 998 {
3882b010 999 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1000 register_chars[c] = mnemonic_chars[c];
1001 operand_chars[c] = c;
1002 }
1003
3882b010 1004 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1005 identifier_chars[c] = c;
1006 else if (c >= 128)
1007 {
1008 identifier_chars[c] = c;
1009 operand_chars[c] = c;
1010 }
1011 }
1012
1013#ifdef LEX_AT
1014 identifier_chars['@'] = '@';
32137342
NC		 1015#endif
1016#ifdef LEX_QM
1017 identifier_chars['?'] = '?';
1018 operand_chars['?'] = '?';
252b5132 1019#endif
252b5132 1020 digit_chars['-'] = '-';
791fe849 1021 mnemonic_chars['-'] = '-';
252b5132
RH		 1022 identifier_chars['_'] = '_';
1023 identifier_chars['.'] = '.';
1024
1025 for (p = operand_special_chars; *p != '\0'; p++)
1026 operand_chars[(unsigned char) *p] = *p;
1027 }
1028
1029#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1030 if (IS_ELF)
252b5132
RH		 1031 {
1032 record_alignment (text_section, 2);
1033 record_alignment (data_section, 2);
1034 record_alignment (bss_section, 2);
1035 }
1036#endif
a4447b93
RH		 1037
1038 if (flag_code == CODE_64BIT)
1039 {
1040 x86_dwarf2_return_column = 16;
1041 x86_cie_data_alignment = -8;
1042 }
1043 else
1044 {
1045 x86_dwarf2_return_column = 8;
1046 x86_cie_data_alignment = -4;
1047 }
252b5132
RH		 1048}
1049
1050void
1051i386_print_statistics (file)
1052 FILE *file;
1053{
1054 hash_print_statistics (file, "i386 opcode", op_hash);
1055 hash_print_statistics (file, "i386 register", reg_hash);
1056}
1057\f
252b5132
RH		 1058#ifdef DEBUG386
1059
ce8a8b2f 1060/* Debugging routines for md_assemble. */
252b5132
RH		 1061static void pi PARAMS ((char *, i386_insn *));
1062static void pte PARAMS ((template *));
1063static void pt PARAMS ((unsigned int));
1064static void pe PARAMS ((expressionS *));
1065static void ps PARAMS ((symbolS *));
1066
1067static void
1068pi (line, x)
1069 char *line;
1070 i386_insn *x;
1071{
09f131f2 1072 unsigned int i;
252b5132
RH		 1073
1074 fprintf (stdout, "%s: template ", line);
1075 pte (&x->tm);
09f131f2
JH		 1076 fprintf (stdout, " address: base %s index %s scale %x\n",
1077 x->base_reg ? x->base_reg->reg_name : "none",
1078 x->index_reg ? x->index_reg->reg_name : "none",
1079 x->log2_scale_factor);
1080 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1081 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1082 fprintf (stdout, " sib: base %x index %x scale %x\n",
1083 x->sib.base, x->sib.index, x->sib.scale);
1084 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1085 (x->rex & REX_MODE64) != 0,
1086 (x->rex & REX_EXTX) != 0,
1087 (x->rex & REX_EXTY) != 0,
1088 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1089 for (i = 0; i < x->operands; i++)
1090 {
1091 fprintf (stdout, " #%d: ", i + 1);
1092 pt (x->types[i]);
1093 fprintf (stdout, "\n");
1094 if (x->types[i]
3f4438ab 1095 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1096 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1097 if (x->types[i] & Imm)
520dc8e8 1098 pe (x->op[i].imms);
252b5132 1099 if (x->types[i] & Disp)
520dc8e8 1100 pe (x->op[i].disps);
252b5132
RH		 1101 }
1102}
1103
1104static void
1105pte (t)
1106 template *t;
1107{
09f131f2 1108 unsigned int i;
252b5132 1109 fprintf (stdout, " %d operands ", t->operands);
47926f60 1110 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1111 if (t->extension_opcode != None)
1112 fprintf (stdout, "ext %x ", t->extension_opcode);
1113 if (t->opcode_modifier & D)
1114 fprintf (stdout, "D");
1115 if (t->opcode_modifier & W)
1116 fprintf (stdout, "W");
1117 fprintf (stdout, "\n");
1118 for (i = 0; i < t->operands; i++)
1119 {
1120 fprintf (stdout, " #%d type ", i + 1);
1121 pt (t->operand_types[i]);
1122 fprintf (stdout, "\n");
1123 }
1124}
1125
1126static void
1127pe (e)
1128 expressionS *e;
1129{
24eab124 1130 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1131 fprintf (stdout, " add_number %ld (%lx)\n",
1132 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1133 if (e->X_add_symbol)
1134 {
1135 fprintf (stdout, " add_symbol ");
1136 ps (e->X_add_symbol);
1137 fprintf (stdout, "\n");
1138 }
1139 if (e->X_op_symbol)
1140 {
1141 fprintf (stdout, " op_symbol ");
1142 ps (e->X_op_symbol);
1143 fprintf (stdout, "\n");
1144 }
1145}
1146
1147static void
1148ps (s)
1149 symbolS *s;
1150{
1151 fprintf (stdout, "%s type %s%s",
1152 S_GET_NAME (s),
1153 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1154 segment_name (S_GET_SEGMENT (s)));
1155}
1156
1157struct type_name
1158 {
1159 unsigned int mask;
1160 char *tname;
1161 }
1162
29b0f896 1163static const type_names[] =
252b5132
RH		 1164{
1165 { Reg8, "r8" },
1166 { Reg16, "r16" },
1167 { Reg32, "r32" },
09f131f2 1168 { Reg64, "r64" },
252b5132
RH		 1169 { Imm8, "i8" },
1170 { Imm8S, "i8s" },
1171 { Imm16, "i16" },
1172 { Imm32, "i32" },
09f131f2
JH		 1173 { Imm32S, "i32s" },
1174 { Imm64, "i64" },
252b5132
RH		 1175 { Imm1, "i1" },
1176 { BaseIndex, "BaseIndex" },
1177 { Disp8, "d8" },
1178 { Disp16, "d16" },
1179 { Disp32, "d32" },
09f131f2
JH		 1180 { Disp32S, "d32s" },
1181 { Disp64, "d64" },
252b5132
RH		 1182 { InOutPortReg, "InOutPortReg" },
1183 { ShiftCount, "ShiftCount" },
1184 { Control, "control reg" },
1185 { Test, "test reg" },
1186 { Debug, "debug reg" },
1187 { FloatReg, "FReg" },
1188 { FloatAcc, "FAcc" },
1189 { SReg2, "SReg2" },
1190 { SReg3, "SReg3" },
1191 { Acc, "Acc" },
1192 { JumpAbsolute, "Jump Absolute" },
1193 { RegMMX, "rMMX" },
3f4438ab 1194 { RegXMM, "rXMM" },
252b5132
RH		 1195 { EsSeg, "es" },
1196 { 0, "" }
1197};
1198
1199static void
1200pt (t)
1201 unsigned int t;
1202{
29b0f896 1203 const struct type_name *ty;
252b5132 1204
09f131f2
JH		 1205 for (ty = type_names; ty->mask; ty++)
1206 if (t & ty->mask)
1207 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1208 fflush (stdout);
1209}
1210
1211#endif /* DEBUG386 */
1212\f
252b5132 1213static bfd_reloc_code_real_type
3956db08
JB		 1214reloc (unsigned int size,
1215 int pcrel,
1216 int sign,
1217 bfd_reloc_code_real_type other)
252b5132 1218{
47926f60 1219 if (other != NO_RELOC)
3956db08
JB		 1220 {
1221 reloc_howto_type *reloc;
1222
1223 if (size == 8)
1224 switch (other)
1225 {
1226 case BFD_RELOC_X86_64_TPOFF32:
1227 other = BFD_RELOC_X86_64_TPOFF64;
1228 break;
1229 case BFD_RELOC_X86_64_DTPOFF32:
1230 other = BFD_RELOC_X86_64_DTPOFF64;
1231 break;
1232 default:
1233 break;
1234 }
1235 reloc = bfd_reloc_type_lookup (stdoutput, other);
1236 if (!reloc)
1237 as_bad (_("unknown relocation (%u)"), other);
1238 else if (size != bfd_get_reloc_size (reloc))
1239 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1240 bfd_get_reloc_size (reloc),
1241 size);
1242 else if (pcrel && !reloc->pc_relative)
1243 as_bad (_("non-pc-relative relocation for pc-relative field"));
1244 else if ((reloc->complain_on_overflow == complain_overflow_signed
1245 && !sign)
1246 || (reloc->complain_on_overflow == complain_overflow_unsigned
1247 && sign > 0))
1248 as_bad (_("relocated field and relocation type differ in signedness"));
1249 else
1250 return other;
1251 return NO_RELOC;
1252 }
252b5132
RH		 1253
1254 if (pcrel)
1255 {
3e73aa7c 1256 if (!sign)
3956db08 1257 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1258 switch (size)
1259 {
1260 case 1: return BFD_RELOC_8_PCREL;
1261 case 2: return BFD_RELOC_16_PCREL;
1262 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1263 case 8: return BFD_RELOC_64_PCREL;
252b5132 1264 }
3956db08 1265 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1266 }
1267 else
1268 {
3956db08 1269 if (sign > 0)
e5cb08ac 1270 switch (size)
3e73aa7c
JH		 1271 {
1272 case 4: return BFD_RELOC_X86_64_32S;
1273 }
1274 else
1275 switch (size)
1276 {
1277 case 1: return BFD_RELOC_8;
1278 case 2: return BFD_RELOC_16;
1279 case 4: return BFD_RELOC_32;
1280 case 8: return BFD_RELOC_64;
1281 }
3956db08
JB		 1282 as_bad (_("cannot do %s %u byte relocation"),
1283 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1284 }
1285
bfb32b52 1286 abort ();
252b5132
RH		 1287 return BFD_RELOC_NONE;
1288}
1289
47926f60
KH		 1290/* Here we decide which fixups can be adjusted to make them relative to
1291 the beginning of the section instead of the symbol. Basically we need
1292 to make sure that the dynamic relocations are done correctly, so in
1293 some cases we force the original symbol to be used. */
1294
252b5132 1295int
c0c949c7 1296tc_i386_fix_adjustable (fixP)
31312f95 1297 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1298{
6d249963 1299#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1300 if (!IS_ELF)
31312f95
AM		 1301 return 1;
1302
a161fe53
AM		 1303 /* Don't adjust pc-relative references to merge sections in 64-bit
1304 mode. */
1305 if (use_rela_relocations
1306 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1307 && fixP->fx_pcrel)
252b5132 1308 return 0;
31312f95 1309
8d01d9a9
AJ		 1310 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1311 and changed later by validate_fix. */
1312 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1313 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1314 return 0;
1315
ce8a8b2f 1316 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1317 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1318 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1319 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1320 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1321 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1322 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1323 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1324 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1325 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1326 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1327 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3e73aa7c
JH		 1328 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1329 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1330 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1331 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1332 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1333 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1334 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1335 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1336 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1337 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1338 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
252b5132
RH		 1339 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1340 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1341 return 0;
31312f95 1342#endif
252b5132
RH		 1343 return 1;
1344}
252b5132 1345
29b0f896 1346static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1347
1348static int
252b5132 1349intel_float_operand (mnemonic)
29b0f896 1350 const char *mnemonic;
252b5132 1351{
9306ca4a
JB		 1352 /* Note that the value returned is meaningful only for opcodes with (memory)
1353 operands, hence the code here is free to improperly handle opcodes that
1354 have no operands (for better performance and smaller code). */
1355
1356 if (mnemonic[0] != 'f')
1357 return 0; /* non-math */
1358
1359 switch (mnemonic[1])
1360 {
1361 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1362 the fs segment override prefix not currently handled because no
1363 call path can make opcodes without operands get here */
1364 case 'i':
1365 return 2 /* integer op */;
1366 case 'l':
1367 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1368 return 3; /* fldcw/fldenv */
1369 break;
1370 case 'n':
1371 if (mnemonic[2] != 'o' /* fnop */)
1372 return 3; /* non-waiting control op */
1373 break;
1374 case 'r':
1375 if (mnemonic[2] == 's')
1376 return 3; /* frstor/frstpm */
1377 break;
1378 case 's':
1379 if (mnemonic[2] == 'a')
1380 return 3; /* fsave */
1381 if (mnemonic[2] == 't')
1382 {
1383 switch (mnemonic[3])
1384 {
1385 case 'c': /* fstcw */
1386 case 'd': /* fstdw */
1387 case 'e': /* fstenv */
1388 case 's': /* fsts[gw] */
1389 return 3;
1390 }
1391 }
1392 break;
1393 case 'x':
1394 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1395 return 0; /* fxsave/fxrstor are not really math ops */
1396 break;
1397 }
252b5132 1398
9306ca4a 1399 return 1;
252b5132
RH		 1400}
1401
1402/* This is the guts of the machine-dependent assembler. LINE points to a
1403 machine dependent instruction. This function is supposed to emit
1404 the frags/bytes it assembles to. */
1405
1406void
1407md_assemble (line)
1408 char *line;
1409{
252b5132 1410 int j;
252b5132
RH		 1411 char mnemonic[MAX_MNEM_SIZE];
1412
47926f60 1413 /* Initialize globals. */
252b5132
RH		 1414 memset (&i, '\0', sizeof (i));
1415 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1416 i.reloc[j] = NO_RELOC;
252b5132
RH		 1417 memset (disp_expressions, '\0', sizeof (disp_expressions));
1418 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1419 save_stack_p = save_stack;
252b5132
RH		 1420
1421 /* First parse an instruction mnemonic & call i386_operand for the operands.
1422 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1423 start of a (possibly prefixed) mnemonic. */
252b5132 1424
29b0f896
AM		 1425 line = parse_insn (line, mnemonic);
1426 if (line == NULL)
1427 return;
252b5132 1428
29b0f896
AM		 1429 line = parse_operands (line, mnemonic);
1430 if (line == NULL)
1431 return;
252b5132 1432
29b0f896
AM		 1433 /* Now we've parsed the mnemonic into a set of templates, and have the
1434 operands at hand. */
1435
1436 /* All intel opcodes have reversed operands except for "bound" and
1437 "enter". We also don't reverse intersegment "jmp" and "call"
1438 instructions with 2 immediate operands so that the immediate segment
1439 precedes the offset, as it does when in AT&T mode. "enter" and the
1440 intersegment "jmp" and "call" instructions are the only ones that
1441 have two immediate operands. */
1442 if (intel_syntax && i.operands > 1
1443 && (strcmp (mnemonic, "bound") != 0)
30123838 1444 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1445 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1446 swap_operands ();
1447
1448 if (i.imm_operands)
1449 optimize_imm ();
1450
b300c311
L		 1451 /* Don't optimize displacement for movabs since it only takes 64bit
1452 displacement. */
1453 if (i.disp_operands
1454 && (flag_code != CODE_64BIT
1455 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1456 optimize_disp ();
1457
1458 /* Next, we find a template that matches the given insn,
1459 making sure the overlap of the given operands types is consistent
1460 with the template operand types. */
252b5132 1461
29b0f896
AM		 1462 if (!match_template ())
1463 return;
252b5132 1464
cd61ebfe
AM		 1465 if (intel_syntax)
1466 {
1467 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1468 if (SYSV386_COMPAT
1469 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1470 i.tm.base_opcode ^= FloatR;
1471
1472 /* Zap movzx and movsx suffix. The suffix may have been set from
1473 "word ptr" or "byte ptr" on the source operand, but we'll use
1474 the suffix later to choose the destination register. */
1475 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1476 {
1477 if (i.reg_operands < 2
1478 && !i.suffix
1479 && (~i.tm.opcode_modifier
1480 & (No_bSuf
1481 | No_wSuf
1482 | No_lSuf
1483 | No_sSuf
1484 | No_xSuf
1485 | No_qSuf)))
1486 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1487
1488 i.suffix = 0;
1489 }
cd61ebfe 1490 }
24eab124 1491
29b0f896
AM		 1492 if (i.tm.opcode_modifier & FWait)
1493 if (!add_prefix (FWAIT_OPCODE))
1494 return;
252b5132 1495
29b0f896
AM		 1496 /* Check string instruction segment overrides. */
1497 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1498 {
1499 if (!check_string ())
5dd0794d 1500 return;
29b0f896 1501 }
5dd0794d 1502
29b0f896
AM		 1503 if (!process_suffix ())
1504 return;
e413e4e9 1505
29b0f896
AM		 1506 /* Make still unresolved immediate matches conform to size of immediate
1507 given in i.suffix. */
1508 if (!finalize_imm ())
1509 return;
252b5132 1510
29b0f896
AM		 1511 if (i.types[0] & Imm1)
1512 i.imm_operands = 0; /* kludge for shift insns. */
1513 if (i.types[0] & ImplicitRegister)
1514 i.reg_operands--;
1515 if (i.types[1] & ImplicitRegister)
1516 i.reg_operands--;
1517 if (i.types[2] & ImplicitRegister)
1518 i.reg_operands--;
252b5132 1519
29b0f896
AM		 1520 if (i.tm.opcode_modifier & ImmExt)
1521 {
02fc3089
L		 1522 expressionS *exp;
1523
ca164297
L		 1524 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1525 {
67c1ffbe 1526 /* These Intel Prescott New Instructions have the fixed
ca164297
L		 1527 operands with an opcode suffix which is coded in the same
1528 place as an 8-bit immediate field would be. Here we check
1529 those operands and remove them afterwards. */
1530 unsigned int x;
1531
a4622f40 1532 for (x = 0; x < i.operands; x++)
ca164297
L		 1533 if (i.op[x].regs->reg_num != x)
1534 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1535 i.op[x].regs->reg_name, x + 1, i.tm.name);
1536 i.operands = 0;
1537 }
1538
29b0f896
AM		 1539 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1540 opcode suffix which is coded in the same place as an 8-bit
1541 immediate field would be. Here we fake an 8-bit immediate
1542 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1543
29b0f896 1544 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1545
29b0f896
AM		 1546 exp = &im_expressions[i.imm_operands++];
1547 i.op[i.operands].imms = exp;
1548 i.types[i.operands++] = Imm8;
1549 exp->X_op = O_constant;
1550 exp->X_add_number = i.tm.extension_opcode;
1551 i.tm.extension_opcode = None;
1552 }
252b5132 1553
29b0f896
AM		 1554 /* For insns with operands there are more diddles to do to the opcode. */
1555 if (i.operands)
1556 {
1557 if (!process_operands ())
1558 return;
1559 }
1560 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1561 {
1562 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1563 as_warn (_("translating to `%sp'"), i.tm.name);
1564 }
252b5132 1565
29b0f896
AM		 1566 /* Handle conversion of 'int $3' --> special int3 insn. */
1567 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1568 {
1569 i.tm.base_opcode = INT3_OPCODE;
1570 i.imm_operands = 0;
1571 }
252b5132 1572
29b0f896
AM		 1573 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1574 && i.op[0].disps->X_op == O_constant)
1575 {
1576 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1577 the absolute address given by the constant. Since ix86 jumps and
1578 calls are pc relative, we need to generate a reloc. */
1579 i.op[0].disps->X_add_symbol = &abs_symbol;
1580 i.op[0].disps->X_op = O_symbol;
1581 }
252b5132 1582
29b0f896
AM		 1583 if ((i.tm.opcode_modifier & Rex64) != 0)
1584 i.rex |= REX_MODE64;
252b5132 1585
29b0f896
AM		 1586 /* For 8 bit registers we need an empty rex prefix. Also if the
1587 instruction already has a prefix, we need to convert old
1588 registers to new ones. */
773f551c 1589
29b0f896
AM		 1590 if (((i.types[0] & Reg8) != 0
1591 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1592 || ((i.types[1] & Reg8) != 0
1593 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1594 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1595 && i.rex != 0))
1596 {
1597 int x;
726c5dcd 1598
29b0f896
AM		 1599 i.rex |= REX_OPCODE;
1600 for (x = 0; x < 2; x++)
1601 {
1602 /* Look for 8 bit operand that uses old registers. */
1603 if ((i.types[x] & Reg8) != 0
1604 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1605 {
29b0f896
AM		 1606 /* In case it is "hi" register, give up. */
1607 if (i.op[x].regs->reg_num > 3)
0477af35 1608 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1609 i.op[x].regs->reg_name);
773f551c 1610
29b0f896
AM		 1611 /* Otherwise it is equivalent to the extended register.
1612 Since the encoding doesn't change this is merely
1613 cosmetic cleanup for debug output. */
1614
1615 i.op[x].regs = i.op[x].regs + 8;
773f551c 1616 }
29b0f896
AM		 1617 }
1618 }
773f551c 1619
29b0f896
AM		 1620 if (i.rex != 0)
1621 add_prefix (REX_OPCODE | i.rex);
1622
1623 /* We are ready to output the insn. */
1624 output_insn ();
1625}
1626
1627static char *
1628parse_insn (line, mnemonic)
1629 char *line;
1630 char *mnemonic;
1631{
1632 char *l = line;
1633 char *token_start = l;
1634 char *mnem_p;
5c6af06e
JB		 1635 int supported;
1636 const template *t;
29b0f896
AM		 1637
1638 /* Non-zero if we found a prefix only acceptable with string insns. */
1639 const char *expecting_string_instruction = NULL;
45288df1 1640
29b0f896
AM		 1641 while (1)
1642 {
1643 mnem_p = mnemonic;
1644 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1645 {
1646 mnem_p++;
1647 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1648 {
29b0f896
AM		 1649 as_bad (_("no such instruction: `%s'"), token_start);
1650 return NULL;
1651 }
1652 l++;
1653 }
1654 if (!is_space_char (*l)
1655 && *l != END_OF_INSN
e44823cf
JB		 1656 && (intel_syntax
1657 || (*l != PREFIX_SEPARATOR
1658 && *l != ',')))
29b0f896
AM		 1659 {
1660 as_bad (_("invalid character %s in mnemonic"),
1661 output_invalid (*l));
1662 return NULL;
1663 }
1664 if (token_start == l)
1665 {
e44823cf 1666 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1667 as_bad (_("expecting prefix; got nothing"));
1668 else
1669 as_bad (_("expecting mnemonic; got nothing"));
1670 return NULL;
1671 }
45288df1 1672
29b0f896
AM		 1673 /* Look up instruction (or prefix) via hash table. */
1674 current_templates = hash_find (op_hash, mnemonic);
47926f60 1675
29b0f896
AM		 1676 if (*l != END_OF_INSN
1677 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1678 && current_templates
1679 && (current_templates->start->opcode_modifier & IsPrefix))
1680 {
2dd88dca
JB		 1681 if (current_templates->start->cpu_flags
1682 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1683 {
1684 as_bad ((flag_code != CODE_64BIT
1685 ? _("`%s' is only supported in 64-bit mode")
1686 : _("`%s' is not supported in 64-bit mode")),
1687 current_templates->start->name);
1688 return NULL;
1689 }
29b0f896
AM		 1690 /* If we are in 16-bit mode, do not allow addr16 or data16.
1691 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1692 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1693 && flag_code != CODE_64BIT
1694 && (((current_templates->start->opcode_modifier & Size32) != 0)
1695 ^ (flag_code == CODE_16BIT)))
1696 {
1697 as_bad (_("redundant %s prefix"),
1698 current_templates->start->name);
1699 return NULL;
45288df1 1700 }
29b0f896
AM		 1701 /* Add prefix, checking for repeated prefixes. */
1702 switch (add_prefix (current_templates->start->base_opcode))
1703 {
1704 case 0:
1705 return NULL;
1706 case 2:
1707 expecting_string_instruction = current_templates->start->name;
1708 break;
1709 }
1710 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1711 token_start = ++l;
1712 }
1713 else
1714 break;
1715 }
45288df1 1716
29b0f896
AM		 1717 if (!current_templates)
1718 {
1719 /* See if we can get a match by trimming off a suffix. */
1720 switch (mnem_p[-1])
1721 {
1722 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 1723 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
1724 i.suffix = SHORT_MNEM_SUFFIX;
1725 else
29b0f896
AM		 1726 case BYTE_MNEM_SUFFIX:
1727 case QWORD_MNEM_SUFFIX:
1728 i.suffix = mnem_p[-1];
1729 mnem_p[-1] = '\0';
1730 current_templates = hash_find (op_hash, mnemonic);
1731 break;
1732 case SHORT_MNEM_SUFFIX:
1733 case LONG_MNEM_SUFFIX:
1734 if (!intel_syntax)
1735 {
1736 i.suffix = mnem_p[-1];
1737 mnem_p[-1] = '\0';
1738 current_templates = hash_find (op_hash, mnemonic);
1739 }
1740 break;
252b5132 1741
29b0f896
AM		 1742 /* Intel Syntax. */
1743 case 'd':
1744 if (intel_syntax)
1745 {
9306ca4a 1746 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 1747 i.suffix = SHORT_MNEM_SUFFIX;
1748 else
1749 i.suffix = LONG_MNEM_SUFFIX;
1750 mnem_p[-1] = '\0';
1751 current_templates = hash_find (op_hash, mnemonic);
1752 }
1753 break;
1754 }
1755 if (!current_templates)
1756 {
1757 as_bad (_("no such instruction: `%s'"), token_start);
1758 return NULL;
1759 }
1760 }
252b5132 1761
29b0f896
AM		 1762 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1763 {
1764 /* Check for a branch hint. We allow ",pt" and ",pn" for
1765 predict taken and predict not taken respectively.
1766 I'm not sure that branch hints actually do anything on loop
1767 and jcxz insns (JumpByte) for current Pentium4 chips. They
1768 may work in the future and it doesn't hurt to accept them
1769 now. */
1770 if (l[0] == ',' && l[1] == 'p')
1771 {
1772 if (l[2] == 't')
1773 {
1774 if (!add_prefix (DS_PREFIX_OPCODE))
1775 return NULL;
1776 l += 3;
1777 }
1778 else if (l[2] == 'n')
1779 {
1780 if (!add_prefix (CS_PREFIX_OPCODE))
1781 return NULL;
1782 l += 3;
1783 }
1784 }
1785 }
1786 /* Any other comma loses. */
1787 if (*l == ',')
1788 {
1789 as_bad (_("invalid character %s in mnemonic"),
1790 output_invalid (*l));
1791 return NULL;
1792 }
252b5132 1793
29b0f896 1794 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 1795 supported = 0;
1796 for (t = current_templates->start; t < current_templates->end; ++t)
1797 {
1798 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
1799 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
1800 supported |= 1;
1801 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
1802 supported |= 2;
1803 }
1804 if (!(supported & 2))
1805 {
1806 as_bad (flag_code == CODE_64BIT
1807 ? _("`%s' is not supported in 64-bit mode")
1808 : _("`%s' is only supported in 64-bit mode"),
1809 current_templates->start->name);
1810 return NULL;
1811 }
1812 if (!(supported & 1))
29b0f896 1813 {
5c6af06e
JB		 1814 as_warn (_("`%s' is not supported on `%s%s'"),
1815 current_templates->start->name,
1816 cpu_arch_name,
1817 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 1818 }
1819 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1820 {
1821 as_warn (_("use .code16 to ensure correct addressing mode"));
1822 }
252b5132 1823
29b0f896 1824 /* Check for rep/repne without a string instruction. */
f41bbced 1825 if (expecting_string_instruction)
29b0f896 1826 {
f41bbced
JB		 1827 static templates override;
1828
1829 for (t = current_templates->start; t < current_templates->end; ++t)
1830 if (t->opcode_modifier & IsString)
1831 break;
1832 if (t >= current_templates->end)
1833 {
1834 as_bad (_("expecting string instruction after `%s'"),
1835 expecting_string_instruction);
1836 return NULL;
1837 }
1838 for (override.start = t; t < current_templates->end; ++t)
1839 if (!(t->opcode_modifier & IsString))
1840 break;
1841 override.end = t;
1842 current_templates = &override;
29b0f896 1843 }
252b5132 1844
29b0f896
AM		 1845 return l;
1846}
252b5132 1847
29b0f896
AM		 1848static char *
1849parse_operands (l, mnemonic)
1850 char *l;
1851 const char *mnemonic;
1852{
1853 char *token_start;
3138f287 1854
29b0f896
AM		 1855 /* 1 if operand is pending after ','. */
1856 unsigned int expecting_operand = 0;
252b5132 1857
29b0f896
AM		 1858 /* Non-zero if operand parens not balanced. */
1859 unsigned int paren_not_balanced;
1860
1861 while (*l != END_OF_INSN)
1862 {
1863 /* Skip optional white space before operand. */
1864 if (is_space_char (*l))
1865 ++l;
1866 if (!is_operand_char (*l) && *l != END_OF_INSN)
1867 {
1868 as_bad (_("invalid character %s before operand %d"),
1869 output_invalid (*l),
1870 i.operands + 1);
1871 return NULL;
1872 }
1873 token_start = l; /* after white space */
1874 paren_not_balanced = 0;
1875 while (paren_not_balanced || *l != ',')
1876 {
1877 if (*l == END_OF_INSN)
1878 {
1879 if (paren_not_balanced)
1880 {
1881 if (!intel_syntax)
1882 as_bad (_("unbalanced parenthesis in operand %d."),
1883 i.operands + 1);
1884 else
1885 as_bad (_("unbalanced brackets in operand %d."),
1886 i.operands + 1);
1887 return NULL;
1888 }
1889 else
1890 break; /* we are done */
1891 }
1892 else if (!is_operand_char (*l) && !is_space_char (*l))
1893 {
1894 as_bad (_("invalid character %s in operand %d"),
1895 output_invalid (*l),
1896 i.operands + 1);
1897 return NULL;
1898 }
1899 if (!intel_syntax)
1900 {
1901 if (*l == '(')
1902 ++paren_not_balanced;
1903 if (*l == ')')
1904 --paren_not_balanced;
1905 }
1906 else
1907 {
1908 if (*l == '[')
1909 ++paren_not_balanced;
1910 if (*l == ']')
1911 --paren_not_balanced;
1912 }
1913 l++;
1914 }
1915 if (l != token_start)
1916 { /* Yes, we've read in another operand. */
1917 unsigned int operand_ok;
1918 this_operand = i.operands++;
1919 if (i.operands > MAX_OPERANDS)
1920 {
1921 as_bad (_("spurious operands; (%d operands/instruction max)"),
1922 MAX_OPERANDS);
1923 return NULL;
1924 }
1925 /* Now parse operand adding info to 'i' as we go along. */
1926 END_STRING_AND_SAVE (l);
1927
1928 if (intel_syntax)
1929 operand_ok =
1930 i386_intel_operand (token_start,
1931 intel_float_operand (mnemonic));
1932 else
1933 operand_ok = i386_operand (token_start);
1934
1935 RESTORE_END_STRING (l);
1936 if (!operand_ok)
1937 return NULL;
1938 }
1939 else
1940 {
1941 if (expecting_operand)
1942 {
1943 expecting_operand_after_comma:
1944 as_bad (_("expecting operand after ','; got nothing"));
1945 return NULL;
1946 }
1947 if (*l == ',')
1948 {
1949 as_bad (_("expecting operand before ','; got nothing"));
1950 return NULL;
1951 }
1952 }
7f3f1ea2 1953
29b0f896
AM		 1954 /* Now *l must be either ',' or END_OF_INSN. */
1955 if (*l == ',')
1956 {
1957 if (*++l == END_OF_INSN)
1958 {
1959 /* Just skip it, if it's \n complain. */
1960 goto expecting_operand_after_comma;
1961 }
1962 expecting_operand = 1;
1963 }
1964 }
1965 return l;
1966}
7f3f1ea2 1967
29b0f896
AM		 1968static void
1969swap_operands ()
1970{
1971 union i386_op temp_op;
1972 unsigned int temp_type;
f86103b7 1973 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 1974 int xchg1 = 0;
1975 int xchg2 = 0;
252b5132 1976
29b0f896
AM		 1977 if (i.operands == 2)
1978 {
1979 xchg1 = 0;
1980 xchg2 = 1;
1981 }
1982 else if (i.operands == 3)
1983 {
1984 xchg1 = 0;
1985 xchg2 = 2;
1986 }
1987 temp_type = i.types[xchg2];
1988 i.types[xchg2] = i.types[xchg1];
1989 i.types[xchg1] = temp_type;
1990 temp_op = i.op[xchg2];
1991 i.op[xchg2] = i.op[xchg1];
1992 i.op[xchg1] = temp_op;
1993 temp_reloc = i.reloc[xchg2];
1994 i.reloc[xchg2] = i.reloc[xchg1];
1995 i.reloc[xchg1] = temp_reloc;
1996
1997 if (i.mem_operands == 2)
1998 {
1999 const seg_entry *temp_seg;
2000 temp_seg = i.seg[0];
2001 i.seg[0] = i.seg[1];
2002 i.seg[1] = temp_seg;
2003 }
2004}
252b5132 2005
29b0f896
AM		 2006/* Try to ensure constant immediates are represented in the smallest
2007 opcode possible. */
2008static void
2009optimize_imm ()
2010{
2011 char guess_suffix = 0;
2012 int op;
252b5132 2013
29b0f896
AM		 2014 if (i.suffix)
2015 guess_suffix = i.suffix;
2016 else if (i.reg_operands)
2017 {
2018 /* Figure out a suffix from the last register operand specified.
2019 We can't do this properly yet, ie. excluding InOutPortReg,
2020 but the following works for instructions with immediates.
2021 In any case, we can't set i.suffix yet. */
2022 for (op = i.operands; --op >= 0;)
2023 if (i.types[op] & Reg)
252b5132 2024 {
29b0f896
AM		 2025 if (i.types[op] & Reg8)
2026 guess_suffix = BYTE_MNEM_SUFFIX;
2027 else if (i.types[op] & Reg16)
2028 guess_suffix = WORD_MNEM_SUFFIX;
2029 else if (i.types[op] & Reg32)
2030 guess_suffix = LONG_MNEM_SUFFIX;
2031 else if (i.types[op] & Reg64)
2032 guess_suffix = QWORD_MNEM_SUFFIX;
2033 break;
252b5132 2034 }
29b0f896
AM		 2035 }
2036 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2037 guess_suffix = WORD_MNEM_SUFFIX;
2038
2039 for (op = i.operands; --op >= 0;)
2040 if (i.types[op] & Imm)
2041 {
2042 switch (i.op[op].imms->X_op)
252b5132 2043 {
29b0f896
AM		 2044 case O_constant:
2045 /* If a suffix is given, this operand may be shortened. */
2046 switch (guess_suffix)
252b5132 2047 {
29b0f896
AM		 2048 case LONG_MNEM_SUFFIX:
2049 i.types[op] |= Imm32 | Imm64;
2050 break;
2051 case WORD_MNEM_SUFFIX:
2052 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2053 break;
2054 case BYTE_MNEM_SUFFIX:
2055 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2056 break;
252b5132 2057 }
252b5132 2058
29b0f896
AM		 2059 /* If this operand is at most 16 bits, convert it
2060 to a signed 16 bit number before trying to see
2061 whether it will fit in an even smaller size.
2062 This allows a 16-bit operand such as $0xffe0 to
2063 be recognised as within Imm8S range. */
2064 if ((i.types[op] & Imm16)
2065 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2066 {
29b0f896
AM		 2067 i.op[op].imms->X_add_number =
2068 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2069 }
2070 if ((i.types[op] & Imm32)
2071 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2072 == 0))
2073 {
2074 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2075 ^ ((offsetT) 1 << 31))
2076 - ((offsetT) 1 << 31));
2077 }
2078 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2079
29b0f896
AM		 2080 /* We must avoid matching of Imm32 templates when 64bit
2081 only immediate is available. */
2082 if (guess_suffix == QWORD_MNEM_SUFFIX)
2083 i.types[op] &= ~Imm32;
2084 break;
252b5132 2085
29b0f896
AM		 2086 case O_absent:
2087 case O_register:
2088 abort ();
2089
2090 /* Symbols and expressions. */
2091 default:
9cd96992
JB		 2092 /* Convert symbolic operand to proper sizes for matching, but don't
2093 prevent matching a set of insns that only supports sizes other
2094 than those matching the insn suffix. */
2095 {
2096 unsigned int mask, allowed = 0;
2097 const template *t;
2098
2099 for (t = current_templates->start; t < current_templates->end; ++t)
2100 allowed |= t->operand_types[op];
2101 switch (guess_suffix)
2102 {
2103 case QWORD_MNEM_SUFFIX:
2104 mask = Imm64 | Imm32S;
2105 break;
2106 case LONG_MNEM_SUFFIX:
2107 mask = Imm32;
2108 break;
2109 case WORD_MNEM_SUFFIX:
2110 mask = Imm16;
2111 break;
2112 case BYTE_MNEM_SUFFIX:
2113 mask = Imm8;
2114 break;
2115 default:
2116 mask = 0;
2117 break;
2118 }
2119 if (mask & allowed)
2120 i.types[op] &= mask;
2121 }
29b0f896 2122 break;
252b5132 2123 }
29b0f896
AM		 2124 }
2125}
47926f60 2126
29b0f896
AM		 2127/* Try to use the smallest displacement type too. */
2128static void
2129optimize_disp ()
2130{
2131 int op;
3e73aa7c 2132
29b0f896 2133 for (op = i.operands; --op >= 0;)
b300c311 2134 if (i.types[op] & Disp)
252b5132 2135 {
b300c311 2136 if (i.op[op].disps->X_op == O_constant)
252b5132 2137 {
b300c311 2138 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2139
b300c311
L		 2140 if ((i.types[op] & Disp16)
2141 && (disp & ~(offsetT) 0xffff) == 0)
2142 {
2143 /* If this operand is at most 16 bits, convert
2144 to a signed 16 bit number and don't use 64bit
2145 displacement. */
2146 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2147 i.types[op] &= ~Disp64;
2148 }
2149 if ((i.types[op] & Disp32)
2150 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2151 {
2152 /* If this operand is at most 32 bits, convert
2153 to a signed 32 bit number and don't use 64bit
2154 displacement. */
2155 disp &= (((offsetT) 2 << 31) - 1);
2156 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2157 i.types[op] &= ~Disp64;
2158 }
2159 if (!disp && (i.types[op] & BaseIndex))
2160 {
2161 i.types[op] &= ~Disp;
2162 i.op[op].disps = 0;
2163 i.disp_operands--;
2164 }
2165 else if (flag_code == CODE_64BIT)
2166 {
2167 if (fits_in_signed_long (disp))
28a9d8f5
L		 2168 {
2169 i.types[op] &= ~Disp64;
2170 i.types[op] |= Disp32S;
2171 }
b300c311
L		 2172 if (fits_in_unsigned_long (disp))
2173 i.types[op] |= Disp32;
2174 }
2175 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2176 && fits_in_signed_byte (disp))
2177 i.types[op] |= Disp8;
252b5132 2178 }
b300c311
L		 2179 else
2180 /* We only support 64bit displacement on constants. */
2181 i.types[op] &= ~Disp64;
252b5132 2182 }
29b0f896
AM		 2183}
2184
2185static int
2186match_template ()
2187{
2188 /* Points to template once we've found it. */
2189 const template *t;
2190 unsigned int overlap0, overlap1, overlap2;
2191 unsigned int found_reverse_match;
2192 int suffix_check;
2193
2194#define MATCH(overlap, given, template) \
2195 ((overlap & ~JumpAbsolute) \
2196 && (((given) & (BaseIndex | JumpAbsolute)) \
2197 == ((overlap) & (BaseIndex | JumpAbsolute))))
2198
2199 /* If given types r0 and r1 are registers they must be of the same type
2200 unless the expected operand type register overlap is null.
2201 Note that Acc in a template matches every size of reg. */
2202#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2203 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2204 || ((g0) & Reg) == ((g1) & Reg) \
2205 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2206
2207 overlap0 = 0;
2208 overlap1 = 0;
2209 overlap2 = 0;
2210 found_reverse_match = 0;
2211 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2212 ? No_bSuf
2213 : (i.suffix == WORD_MNEM_SUFFIX
2214 ? No_wSuf
2215 : (i.suffix == SHORT_MNEM_SUFFIX
2216 ? No_sSuf
2217 : (i.suffix == LONG_MNEM_SUFFIX
2218 ? No_lSuf
2219 : (i.suffix == QWORD_MNEM_SUFFIX
2220 ? No_qSuf
2221 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2222 ? No_xSuf : 0))))));
2223
20f0a1fc
NC		 2224 t = current_templates->start;
2225 if (i.suffix == QWORD_MNEM_SUFFIX
2226 && flag_code != CODE_64BIT
9306ca4a
JB		 2227 && (intel_syntax
2228 ? !(t->opcode_modifier & IgnoreSize)
2229 && !intel_float_operand (t->name)
2230 : intel_float_operand (t->name) != 2)
20f0a1fc
NC		 2231 && (!(t->operand_types[0] & (RegMMX | RegXMM))
2232 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2233 && (t->base_opcode != 0x0fc7
2234 || t->extension_opcode != 1 /* cmpxchg8b */))
2235 t = current_templates->end;
2236 for (; t < current_templates->end; t++)
29b0f896
AM		 2237 {
2238 /* Must have right number of operands. */
2239 if (i.operands != t->operands)
2240 continue;
2241
2242 /* Check the suffix, except for some instructions in intel mode. */
2243 if ((t->opcode_modifier & suffix_check)
2244 && !(intel_syntax
9306ca4a 2245 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2246 continue;
2247
2248 /* Do not verify operands when there are none. */
2249 else if (!t->operands)
2250 {
2251 if (t->cpu_flags & ~cpu_arch_flags)
2252 continue;
2253 /* We've found a match; break out of loop. */
2254 break;
2255 }
252b5132 2256
29b0f896
AM		 2257 overlap0 = i.types[0] & t->operand_types[0];
2258 switch (t->operands)
2259 {
2260 case 1:
2261 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2262 continue;
2263 break;
2264 case 2:
2265 case 3:
2266 overlap1 = i.types[1] & t->operand_types[1];
2267 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2268 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2269 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2270 t->operand_types[0],
2271 overlap1, i.types[1],
2272 t->operand_types[1]))
2273 {
2274 /* Check if other direction is valid ... */
2275 if ((t->opcode_modifier & (D | FloatD)) == 0)
2276 continue;
2277
2278 /* Try reversing direction of operands. */
2279 overlap0 = i.types[0] & t->operand_types[1];
2280 overlap1 = i.types[1] & t->operand_types[0];
2281 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2282 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2283 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2284 t->operand_types[1],
2285 overlap1, i.types[1],
2286 t->operand_types[0]))
2287 {
2288 /* Does not match either direction. */
2289 continue;
2290 }
2291 /* found_reverse_match holds which of D or FloatDR
2292 we've found. */
2293 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2294 }
2295 /* Found a forward 2 operand match here. */
2296 else if (t->operands == 3)
2297 {
2298 /* Here we make use of the fact that there are no
2299 reverse match 3 operand instructions, and all 3
2300 operand instructions only need to be checked for
2301 register consistency between operands 2 and 3. */
2302 overlap2 = i.types[2] & t->operand_types[2];
2303 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2304 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2305 t->operand_types[1],
2306 overlap2, i.types[2],
2307 t->operand_types[2]))
2308
2309 continue;
2310 }
2311 /* Found either forward/reverse 2 or 3 operand match here:
2312 slip through to break. */
2313 }
2314 if (t->cpu_flags & ~cpu_arch_flags)
2315 {
2316 found_reverse_match = 0;
2317 continue;
2318 }
2319 /* We've found a match; break out of loop. */
2320 break;
2321 }
2322
2323 if (t == current_templates->end)
2324 {
2325 /* We found no match. */
2326 as_bad (_("suffix or operands invalid for `%s'"),
2327 current_templates->start->name);
2328 return 0;
2329 }
252b5132 2330
29b0f896
AM		 2331 if (!quiet_warnings)
2332 {
2333 if (!intel_syntax
2334 && ((i.types[0] & JumpAbsolute)
2335 != (t->operand_types[0] & JumpAbsolute)))
2336 {
2337 as_warn (_("indirect %s without `*'"), t->name);
2338 }
2339
2340 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2341 == (IsPrefix | IgnoreSize))
2342 {
2343 /* Warn them that a data or address size prefix doesn't
2344 affect assembly of the next line of code. */
2345 as_warn (_("stand-alone `%s' prefix"), t->name);
2346 }
2347 }
2348
2349 /* Copy the template we found. */
2350 i.tm = *t;
2351 if (found_reverse_match)
2352 {
2353 /* If we found a reverse match we must alter the opcode
2354 direction bit. found_reverse_match holds bits to change
2355 (different for int & float insns). */
2356
2357 i.tm.base_opcode ^= found_reverse_match;
2358
2359 i.tm.operand_types[0] = t->operand_types[1];
2360 i.tm.operand_types[1] = t->operand_types[0];
2361 }
2362
2363 return 1;
2364}
2365
2366static int
2367check_string ()
2368{
2369 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2370 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2371 {
2372 if (i.seg[0] != NULL && i.seg[0] != &es)
2373 {
2374 as_bad (_("`%s' operand %d must use `%%es' segment"),
2375 i.tm.name,
2376 mem_op + 1);
2377 return 0;
2378 }
2379 /* There's only ever one segment override allowed per instruction.
2380 This instruction possibly has a legal segment override on the
2381 second operand, so copy the segment to where non-string
2382 instructions store it, allowing common code. */
2383 i.seg[0] = i.seg[1];
2384 }
2385 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2386 {
2387 if (i.seg[1] != NULL && i.seg[1] != &es)
2388 {
2389 as_bad (_("`%s' operand %d must use `%%es' segment"),
2390 i.tm.name,
2391 mem_op + 2);
2392 return 0;
2393 }
2394 }
2395 return 1;
2396}
2397
2398static int
543613e9 2399process_suffix (void)
29b0f896
AM		 2400{
2401 /* If matched instruction specifies an explicit instruction mnemonic
2402 suffix, use it. */
2403 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2404 {
2405 if (i.tm.opcode_modifier & Size16)
2406 i.suffix = WORD_MNEM_SUFFIX;
2407 else if (i.tm.opcode_modifier & Size64)
2408 i.suffix = QWORD_MNEM_SUFFIX;
2409 else
2410 i.suffix = LONG_MNEM_SUFFIX;
2411 }
2412 else if (i.reg_operands)
2413 {
2414 /* If there's no instruction mnemonic suffix we try to invent one
2415 based on register operands. */
2416 if (!i.suffix)
2417 {
2418 /* We take i.suffix from the last register operand specified,
2419 Destination register type is more significant than source
2420 register type. */
2421 int op;
543613e9 2422
29b0f896
AM		 2423 for (op = i.operands; --op >= 0;)
2424 if ((i.types[op] & Reg)
2425 && !(i.tm.operand_types[op] & InOutPortReg))
2426 {
2427 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2428 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2429 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2430 LONG_MNEM_SUFFIX);
2431 break;
2432 }
2433 }
2434 else if (i.suffix == BYTE_MNEM_SUFFIX)
2435 {
2436 if (!check_byte_reg ())
2437 return 0;
2438 }
2439 else if (i.suffix == LONG_MNEM_SUFFIX)
2440 {
2441 if (!check_long_reg ())
2442 return 0;
2443 }
2444 else if (i.suffix == QWORD_MNEM_SUFFIX)
2445 {
2446 if (!check_qword_reg ())
2447 return 0;
2448 }
2449 else if (i.suffix == WORD_MNEM_SUFFIX)
2450 {
2451 if (!check_word_reg ())
2452 return 0;
2453 }
2454 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2455 /* Do nothing if the instruction is going to ignore the prefix. */
2456 ;
2457 else
2458 abort ();
2459 }
9306ca4a
JB		 2460 else if ((i.tm.opcode_modifier & DefaultSize)
2461 && !i.suffix
2462 /* exclude fldenv/frstor/fsave/fstenv */
2463 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2464 {
2465 i.suffix = stackop_size;
2466 }
9306ca4a
JB		 2467 else if (intel_syntax
2468 && !i.suffix
2469 && ((i.tm.operand_types[0] & JumpAbsolute)
2470 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2471 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2472 && i.tm.extension_opcode <= 3)))
2473 {
2474 switch (flag_code)
2475 {
2476 case CODE_64BIT:
2477 if (!(i.tm.opcode_modifier & No_qSuf))
2478 {
2479 i.suffix = QWORD_MNEM_SUFFIX;
2480 break;
2481 }
2482 case CODE_32BIT:
2483 if (!(i.tm.opcode_modifier & No_lSuf))
2484 i.suffix = LONG_MNEM_SUFFIX;
2485 break;
2486 case CODE_16BIT:
2487 if (!(i.tm.opcode_modifier & No_wSuf))
2488 i.suffix = WORD_MNEM_SUFFIX;
2489 break;
2490 }
2491 }
252b5132 2492
9306ca4a 2493 if (!i.suffix)
29b0f896 2494 {
9306ca4a
JB		 2495 if (!intel_syntax)
2496 {
2497 if (i.tm.opcode_modifier & W)
2498 {
2499 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2500 return 0;
2501 }
2502 }
2503 else
2504 {
2505 unsigned int suffixes = ~i.tm.opcode_modifier
2506 & (No_bSuf
2507 | No_wSuf
2508 | No_lSuf
2509 | No_sSuf
2510 | No_xSuf
2511 | No_qSuf);
2512
2513 if ((i.tm.opcode_modifier & W)
2514 || ((suffixes & (suffixes - 1))
2515 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2516 {
2517 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2518 return 0;
2519 }
2520 }
29b0f896 2521 }
252b5132 2522
9306ca4a
JB		 2523 /* Change the opcode based on the operand size given by i.suffix;
2524 We don't need to change things for byte insns. */
2525
29b0f896
AM		 2526 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2527 {
2528 /* It's not a byte, select word/dword operation. */
2529 if (i.tm.opcode_modifier & W)
2530 {
2531 if (i.tm.opcode_modifier & ShortForm)
2532 i.tm.base_opcode |= 8;
2533 else
2534 i.tm.base_opcode |= 1;
2535 }
0f3f3d8b 2536
29b0f896
AM		 2537 /* Now select between word & dword operations via the operand
2538 size prefix, except for instructions that will ignore this
2539 prefix anyway. */
2540 if (i.suffix != QWORD_MNEM_SUFFIX
9306ca4a
JB		 2541 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2542 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
9146926a
AM		 2543 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2544 || (flag_code == CODE_64BIT
2545 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2546 {
2547 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2548
29b0f896
AM		 2549 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2550 prefix = ADDR_PREFIX_OPCODE;
252b5132 2551
29b0f896
AM		 2552 if (!add_prefix (prefix))
2553 return 0;
24eab124 2554 }
252b5132 2555
29b0f896
AM		 2556 /* Set mode64 for an operand. */
2557 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2558 && flag_code == CODE_64BIT
29b0f896 2559 && (i.tm.opcode_modifier & NoRex64) == 0)
9146926a 2560 i.rex |= REX_MODE64;
3e73aa7c 2561
29b0f896
AM		 2562 /* Size floating point instruction. */
2563 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 2564 if (i.tm.opcode_modifier & FloatMF)
2565 i.tm.base_opcode ^= 4;
29b0f896 2566 }
7ecd2f8b 2567
29b0f896
AM		 2568 return 1;
2569}
3e73aa7c 2570
29b0f896 2571static int
543613e9 2572check_byte_reg (void)
29b0f896
AM		 2573{
2574 int op;
543613e9 2575
29b0f896
AM		 2576 for (op = i.operands; --op >= 0;)
2577 {
2578 /* If this is an eight bit register, it's OK. If it's the 16 or
2579 32 bit version of an eight bit register, we will just use the
2580 low portion, and that's OK too. */
2581 if (i.types[op] & Reg8)
2582 continue;
2583
2584 /* movzx and movsx should not generate this warning. */
2585 if (intel_syntax
2586 && (i.tm.base_opcode == 0xfb7
2587 || i.tm.base_opcode == 0xfb6
2588 || i.tm.base_opcode == 0x63
2589 || i.tm.base_opcode == 0xfbe
2590 || i.tm.base_opcode == 0xfbf))
2591 continue;
2592
65ec77d2 2593 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 2594 {
2595 /* Prohibit these changes in the 64bit mode, since the
2596 lowering is more complicated. */
2597 if (flag_code == CODE_64BIT
2598 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2599 {
0f3f3d8b 2600 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2601 i.op[op].regs->reg_name,
2602 i.suffix);
2603 return 0;
2604 }
2605#if REGISTER_WARNINGS
2606 if (!quiet_warnings
2607 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2608 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2609 (i.op[op].regs + (i.types[op] & Reg16
2610 ? REGNAM_AL - REGNAM_AX
2611 : REGNAM_AL - REGNAM_EAX))->reg_name,
2612 i.op[op].regs->reg_name,
2613 i.suffix);
2614#endif
2615 continue;
2616 }
2617 /* Any other register is bad. */
2618 if (i.types[op] & (Reg | RegMMX | RegXMM
2619 | SReg2 | SReg3
2620 | Control | Debug | Test
2621 | FloatReg | FloatAcc))
2622 {
2623 as_bad (_("`%%%s' not allowed with `%s%c'"),
2624 i.op[op].regs->reg_name,
2625 i.tm.name,
2626 i.suffix);
2627 return 0;
2628 }
2629 }
2630 return 1;
2631}
2632
2633static int
2634check_long_reg ()
2635{
2636 int op;
2637
2638 for (op = i.operands; --op >= 0;)
2639 /* Reject eight bit registers, except where the template requires
2640 them. (eg. movzb) */
2641 if ((i.types[op] & Reg8) != 0
2642 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2643 {
2644 as_bad (_("`%%%s' not allowed with `%s%c'"),
2645 i.op[op].regs->reg_name,
2646 i.tm.name,
2647 i.suffix);
2648 return 0;
2649 }
2650 /* Warn if the e prefix on a general reg is missing. */
2651 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2652 && (i.types[op] & Reg16) != 0
2653 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2654 {
2655 /* Prohibit these changes in the 64bit mode, since the
2656 lowering is more complicated. */
2657 if (flag_code == CODE_64BIT)
252b5132 2658 {
0f3f3d8b 2659 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2660 i.op[op].regs->reg_name,
2661 i.suffix);
2662 return 0;
252b5132 2663 }
29b0f896
AM		 2664#if REGISTER_WARNINGS
2665 else
2666 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2667 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2668 i.op[op].regs->reg_name,
2669 i.suffix);
2670#endif
252b5132 2671 }
29b0f896
AM		 2672 /* Warn if the r prefix on a general reg is missing. */
2673 else if ((i.types[op] & Reg64) != 0
2674 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2675 {
0f3f3d8b 2676 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2677 i.op[op].regs->reg_name,
2678 i.suffix);
2679 return 0;
2680 }
2681 return 1;
2682}
252b5132 2683
29b0f896
AM		 2684static int
2685check_qword_reg ()
2686{
2687 int op;
252b5132 2688
29b0f896
AM		 2689 for (op = i.operands; --op >= 0; )
2690 /* Reject eight bit registers, except where the template requires
2691 them. (eg. movzb) */
2692 if ((i.types[op] & Reg8) != 0
2693 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2694 {
2695 as_bad (_("`%%%s' not allowed with `%s%c'"),
2696 i.op[op].regs->reg_name,
2697 i.tm.name,
2698 i.suffix);
2699 return 0;
2700 }
2701 /* Warn if the e prefix on a general reg is missing. */
2702 else if (((i.types[op] & Reg16) != 0
2703 || (i.types[op] & Reg32) != 0)
2704 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2705 {
2706 /* Prohibit these changes in the 64bit mode, since the
2707 lowering is more complicated. */
0f3f3d8b 2708 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2709 i.op[op].regs->reg_name,
2710 i.suffix);
2711 return 0;
252b5132 2712 }
29b0f896
AM		 2713 return 1;
2714}
252b5132 2715
29b0f896
AM		 2716static int
2717check_word_reg ()
2718{
2719 int op;
2720 for (op = i.operands; --op >= 0;)
2721 /* Reject eight bit registers, except where the template requires
2722 them. (eg. movzb) */
2723 if ((i.types[op] & Reg8) != 0
2724 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2725 {
2726 as_bad (_("`%%%s' not allowed with `%s%c'"),
2727 i.op[op].regs->reg_name,
2728 i.tm.name,
2729 i.suffix);
2730 return 0;
2731 }
2732 /* Warn if the e prefix on a general reg is present. */
2733 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2734 && (i.types[op] & Reg32) != 0
2735 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2736 {
29b0f896
AM		 2737 /* Prohibit these changes in the 64bit mode, since the
2738 lowering is more complicated. */
2739 if (flag_code == CODE_64BIT)
252b5132 2740 {
0f3f3d8b 2741 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2742 i.op[op].regs->reg_name,
2743 i.suffix);
2744 return 0;
252b5132 2745 }
29b0f896
AM		 2746 else
2747#if REGISTER_WARNINGS
2748 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2749 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2750 i.op[op].regs->reg_name,
2751 i.suffix);
2752#endif
2753 }
2754 return 1;
2755}
252b5132 2756
29b0f896
AM		 2757static int
2758finalize_imm ()
2759{
2760 unsigned int overlap0, overlap1, overlap2;
2761
2762 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 2763 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 2764 && overlap0 != Imm8 && overlap0 != Imm8S
2765 && overlap0 != Imm16 && overlap0 != Imm32S
2766 && overlap0 != Imm32 && overlap0 != Imm64)
2767 {
2768 if (i.suffix)
2769 {
2770 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2771 ? Imm8 | Imm8S
2772 : (i.suffix == WORD_MNEM_SUFFIX
2773 ? Imm16
2774 : (i.suffix == QWORD_MNEM_SUFFIX
2775 ? Imm64 | Imm32S
2776 : Imm32)));
2777 }
2778 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2779 || overlap0 == (Imm16 | Imm32)
2780 || overlap0 == (Imm16 | Imm32S))
2781 {
2782 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2783 ? Imm16 : Imm32S);
2784 }
2785 if (overlap0 != Imm8 && overlap0 != Imm8S
2786 && overlap0 != Imm16 && overlap0 != Imm32S
2787 && overlap0 != Imm32 && overlap0 != Imm64)
2788 {
2789 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2790 return 0;
2791 }
2792 }
2793 i.types[0] = overlap0;
2794
2795 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 2796 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 2797 && overlap1 != Imm8 && overlap1 != Imm8S
2798 && overlap1 != Imm16 && overlap1 != Imm32S
2799 && overlap1 != Imm32 && overlap1 != Imm64)
2800 {
2801 if (i.suffix)
2802 {
2803 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2804 ? Imm8 | Imm8S
2805 : (i.suffix == WORD_MNEM_SUFFIX
2806 ? Imm16
2807 : (i.suffix == QWORD_MNEM_SUFFIX
2808 ? Imm64 | Imm32S
2809 : Imm32)));
2810 }
2811 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2812 || overlap1 == (Imm16 | Imm32)
2813 || overlap1 == (Imm16 | Imm32S))
2814 {
2815 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2816 ? Imm16 : Imm32S);
2817 }
2818 if (overlap1 != Imm8 && overlap1 != Imm8S
2819 && overlap1 != Imm16 && overlap1 != Imm32S
2820 && overlap1 != Imm32 && overlap1 != Imm64)
2821 {
2822 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2823 return 0;
2824 }
2825 }
2826 i.types[1] = overlap1;
2827
2828 overlap2 = i.types[2] & i.tm.operand_types[2];
2829 assert ((overlap2 & Imm) == 0);
2830 i.types[2] = overlap2;
2831
2832 return 1;
2833}
2834
2835static int
2836process_operands ()
2837{
2838 /* Default segment register this instruction will use for memory
2839 accesses. 0 means unknown. This is only for optimizing out
2840 unnecessary segment overrides. */
2841 const seg_entry *default_seg = 0;
2842
2843 /* The imul $imm, %reg instruction is converted into
2844 imul $imm, %reg, %reg, and the clr %reg instruction
2845 is converted into xor %reg, %reg. */
2846 if (i.tm.opcode_modifier & regKludge)
2847 {
2848 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2849 /* Pretend we saw the extra register operand. */
2850 assert (i.op[first_reg_op + 1].regs == 0);
2851 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2852 i.types[first_reg_op + 1] = i.types[first_reg_op];
2853 i.reg_operands = 2;
2854 }
2855
2856 if (i.tm.opcode_modifier & ShortForm)
2857 {
2858 /* The register or float register operand is in operand 0 or 1. */
2859 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2860 /* Register goes in low 3 bits of opcode. */
2861 i.tm.base_opcode |= i.op[op].regs->reg_num;
2862 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2863 i.rex |= REX_EXTZ;
2864 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2865 {
2866 /* Warn about some common errors, but press on regardless.
2867 The first case can be generated by gcc (<= 2.8.1). */
2868 if (i.operands == 2)
2869 {
2870 /* Reversed arguments on faddp, fsubp, etc. */
2871 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2872 i.op[1].regs->reg_name,
2873 i.op[0].regs->reg_name);
2874 }
2875 else
2876 {
2877 /* Extraneous `l' suffix on fp insn. */
2878 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2879 i.op[0].regs->reg_name);
2880 }
2881 }
2882 }
2883 else if (i.tm.opcode_modifier & Modrm)
2884 {
2885 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 2886 must be put into the modrm byte). Now, we make the modrm and
2887 index base bytes based on all the info we've collected. */
29b0f896
AM		 2888
2889 default_seg = build_modrm_byte ();
2890 }
2891 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2892 {
2893 if (i.tm.base_opcode == POP_SEG_SHORT
2894 && i.op[0].regs->reg_num == 1)
2895 {
2896 as_bad (_("you can't `pop %%cs'"));
2897 return 0;
2898 }
2899 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2900 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2901 i.rex |= REX_EXTZ;
2902 }
2903 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2904 {
2905 default_seg = &ds;
2906 }
2907 else if ((i.tm.opcode_modifier & IsString) != 0)
2908 {
2909 /* For the string instructions that allow a segment override
2910 on one of their operands, the default segment is ds. */
2911 default_seg = &ds;
2912 }
2913
30123838
JB		 2914 if ((i.tm.base_opcode == 0x8d /* lea */
2915 || (i.tm.cpu_flags & CpuSVME))
2916 && i.seg[0] && !quiet_warnings)
2917 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 2918
2919 /* If a segment was explicitly specified, and the specified segment
2920 is not the default, use an opcode prefix to select it. If we
2921 never figured out what the default segment is, then default_seg
2922 will be zero at this point, and the specified segment prefix will
2923 always be used. */
29b0f896
AM		 2924 if ((i.seg[0]) && (i.seg[0] != default_seg))
2925 {
2926 if (!add_prefix (i.seg[0]->seg_prefix))
2927 return 0;
2928 }
2929 return 1;
2930}
2931
2932static const seg_entry *
2933build_modrm_byte ()
2934{
2935 const seg_entry *default_seg = 0;
2936
2937 /* i.reg_operands MUST be the number of real register operands;
2938 implicit registers do not count. */
2939 if (i.reg_operands == 2)
2940 {
2941 unsigned int source, dest;
2942 source = ((i.types[0]
2943 & (Reg | RegMMX | RegXMM
2944 | SReg2 | SReg3
2945 | Control | Debug | Test))
2946 ? 0 : 1);
2947 dest = source + 1;
2948
2949 i.rm.mode = 3;
2950 /* One of the register operands will be encoded in the i.tm.reg
2951 field, the other in the combined i.tm.mode and i.tm.regmem
2952 fields. If no form of this instruction supports a memory
2953 destination operand, then we assume the source operand may
2954 sometimes be a memory operand and so we need to store the
2955 destination in the i.rm.reg field. */
2956 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2957 {
2958 i.rm.reg = i.op[dest].regs->reg_num;
2959 i.rm.regmem = i.op[source].regs->reg_num;
2960 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2961 i.rex |= REX_EXTX;
2962 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2963 i.rex |= REX_EXTZ;
2964 }
2965 else
2966 {
2967 i.rm.reg = i.op[source].regs->reg_num;
2968 i.rm.regmem = i.op[dest].regs->reg_num;
2969 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2970 i.rex |= REX_EXTZ;
2971 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2972 i.rex |= REX_EXTX;
2973 }
c4a530c5
JB		 2974 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
2975 {
2976 if (!((i.types[0] | i.types[1]) & Control))
2977 abort ();
2978 i.rex &= ~(REX_EXTX | REX_EXTZ);
2979 add_prefix (LOCK_PREFIX_OPCODE);
2980 }
29b0f896
AM		 2981 }
2982 else
2983 { /* If it's not 2 reg operands... */
2984 if (i.mem_operands)
2985 {
2986 unsigned int fake_zero_displacement = 0;
2987 unsigned int op = ((i.types[0] & AnyMem)
2988 ? 0
2989 : (i.types[1] & AnyMem) ? 1 : 2);
2990
2991 default_seg = &ds;
2992
2993 if (i.base_reg == 0)
2994 {
2995 i.rm.mode = 0;
2996 if (!i.disp_operands)
2997 fake_zero_displacement = 1;
2998 if (i.index_reg == 0)
2999 {
3000 /* Operand is just <disp> */
20f0a1fc 3001 if (flag_code == CODE_64BIT)
29b0f896
AM		 3002 {
3003 /* 64bit mode overwrites the 32bit absolute
3004 addressing by RIP relative addressing and
3005 absolute addressing is encoded by one of the
3006 redundant SIB forms. */
3007 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3008 i.sib.base = NO_BASE_REGISTER;
3009 i.sib.index = NO_INDEX_REGISTER;
20f0a1fc
NC		 3010 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
3011 }
3012 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3013 {
3014 i.rm.regmem = NO_BASE_REGISTER_16;
3015 i.types[op] = Disp16;
3016 }
3017 else
3018 {
3019 i.rm.regmem = NO_BASE_REGISTER;
3020 i.types[op] = Disp32;
29b0f896
AM		 3021 }
3022 }
3023 else /* !i.base_reg && i.index_reg */
3024 {
3025 i.sib.index = i.index_reg->reg_num;
3026 i.sib.base = NO_BASE_REGISTER;
3027 i.sib.scale = i.log2_scale_factor;
3028 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3029 i.types[op] &= ~Disp;
3030 if (flag_code != CODE_64BIT)
3031 i.types[op] |= Disp32; /* Must be 32 bit */
3032 else
3033 i.types[op] |= Disp32S;
3034 if ((i.index_reg->reg_flags & RegRex) != 0)
3035 i.rex |= REX_EXTY;
3036 }
3037 }
3038 /* RIP addressing for 64bit mode. */
3039 else if (i.base_reg->reg_type == BaseIndex)
3040 {
3041 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3042 i.types[op] &= ~ Disp;
29b0f896
AM		 3043 i.types[op] |= Disp32S;
3044 i.flags[op] = Operand_PCrel;
20f0a1fc
NC		 3045 if (! i.disp_operands)
3046 fake_zero_displacement = 1;
29b0f896
AM		 3047 }
3048 else if (i.base_reg->reg_type & Reg16)
3049 {
3050 switch (i.base_reg->reg_num)
3051 {
3052 case 3: /* (%bx) */
3053 if (i.index_reg == 0)
3054 i.rm.regmem = 7;
3055 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3056 i.rm.regmem = i.index_reg->reg_num - 6;
3057 break;
3058 case 5: /* (%bp) */
3059 default_seg = &ss;
3060 if (i.index_reg == 0)
3061 {
3062 i.rm.regmem = 6;
3063 if ((i.types[op] & Disp) == 0)
3064 {
3065 /* fake (%bp) into 0(%bp) */
3066 i.types[op] |= Disp8;
252b5132 3067 fake_zero_displacement = 1;
29b0f896
AM		 3068 }
3069 }
3070 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3071 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3072 break;
3073 default: /* (%si) -> 4 or (%di) -> 5 */
3074 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3075 }
3076 i.rm.mode = mode_from_disp_size (i.types[op]);
3077 }
3078 else /* i.base_reg and 32/64 bit mode */
3079 {
3080 if (flag_code == CODE_64BIT
3081 && (i.types[op] & Disp))
20f0a1fc
NC		 3082 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3083
29b0f896
AM		 3084 i.rm.regmem = i.base_reg->reg_num;
3085 if ((i.base_reg->reg_flags & RegRex) != 0)
3086 i.rex |= REX_EXTZ;
3087 i.sib.base = i.base_reg->reg_num;
3088 /* x86-64 ignores REX prefix bit here to avoid decoder
3089 complications. */
3090 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3091 {
3092 default_seg = &ss;
3093 if (i.disp_operands == 0)
3094 {
3095 fake_zero_displacement = 1;
3096 i.types[op] |= Disp8;
3097 }
3098 }
3099 else if (i.base_reg->reg_num == ESP_REG_NUM)
3100 {
3101 default_seg = &ss;
3102 }
3103 i.sib.scale = i.log2_scale_factor;
3104 if (i.index_reg == 0)
3105 {
3106 /* <disp>(%esp) becomes two byte modrm with no index
3107 register. We've already stored the code for esp
3108 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3109 Any base register besides %esp will not use the
3110 extra modrm byte. */
3111 i.sib.index = NO_INDEX_REGISTER;
3112#if !SCALE1_WHEN_NO_INDEX
3113 /* Another case where we force the second modrm byte. */
3114 if (i.log2_scale_factor)
3115 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3116#endif
29b0f896
AM		 3117 }
3118 else
3119 {
3120 i.sib.index = i.index_reg->reg_num;
3121 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3122 if ((i.index_reg->reg_flags & RegRex) != 0)
3123 i.rex |= REX_EXTY;
3124 }
3125 i.rm.mode = mode_from_disp_size (i.types[op]);
3126 }
252b5132 3127
29b0f896
AM		 3128 if (fake_zero_displacement)
3129 {
3130 /* Fakes a zero displacement assuming that i.types[op]
3131 holds the correct displacement size. */
3132 expressionS *exp;
3133
3134 assert (i.op[op].disps == 0);
3135 exp = &disp_expressions[i.disp_operands++];
3136 i.op[op].disps = exp;
3137 exp->X_op = O_constant;
3138 exp->X_add_number = 0;
3139 exp->X_add_symbol = (symbolS *) 0;
3140 exp->X_op_symbol = (symbolS *) 0;
3141 }
3142 }
252b5132 3143
29b0f896
AM		 3144 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3145 (if any) based on i.tm.extension_opcode. Again, we must be
3146 careful to make sure that segment/control/debug/test/MMX
3147 registers are coded into the i.rm.reg field. */
3148 if (i.reg_operands)
3149 {
3150 unsigned int op =
3151 ((i.types[0]
3152 & (Reg | RegMMX | RegXMM
3153 | SReg2 | SReg3
3154 | Control | Debug | Test))
3155 ? 0
3156 : ((i.types[1]
3157 & (Reg | RegMMX | RegXMM
3158 | SReg2 | SReg3
3159 | Control | Debug | Test))
3160 ? 1
3161 : 2));
3162 /* If there is an extension opcode to put here, the register
3163 number must be put into the regmem field. */
3164 if (i.tm.extension_opcode != None)
3165 {
3166 i.rm.regmem = i.op[op].regs->reg_num;
3167 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3168 i.rex |= REX_EXTZ;
3169 }
3170 else
3171 {
3172 i.rm.reg = i.op[op].regs->reg_num;
3173 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3174 i.rex |= REX_EXTX;
3175 }
252b5132 3176
29b0f896
AM		 3177 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3178 must set it to 3 to indicate this is a register operand
3179 in the regmem field. */
3180 if (!i.mem_operands)
3181 i.rm.mode = 3;
3182 }
252b5132 3183
29b0f896
AM		 3184 /* Fill in i.rm.reg field with extension opcode (if any). */
3185 if (i.tm.extension_opcode != None)
3186 i.rm.reg = i.tm.extension_opcode;
3187 }
3188 return default_seg;
3189}
252b5132 3190
29b0f896
AM		 3191static void
3192output_branch ()
3193{
3194 char *p;
3195 int code16;
3196 int prefix;
3197 relax_substateT subtype;
3198 symbolS *sym;
3199 offsetT off;
3200
3201 code16 = 0;
3202 if (flag_code == CODE_16BIT)
3203 code16 = CODE16;
3204
3205 prefix = 0;
3206 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3207 {
29b0f896
AM		 3208 prefix = 1;
3209 i.prefixes -= 1;
3210 code16 ^= CODE16;
252b5132 3211 }
29b0f896
AM		 3212 /* Pentium4 branch hints. */
3213 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3214 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3215 {
29b0f896
AM		 3216 prefix++;
3217 i.prefixes--;
3218 }
3219 if (i.prefix[REX_PREFIX] != 0)
3220 {
3221 prefix++;
3222 i.prefixes--;
2f66722d
AM		 3223 }
3224
29b0f896
AM		 3225 if (i.prefixes != 0 && !intel_syntax)
3226 as_warn (_("skipping prefixes on this instruction"));
3227
3228 /* It's always a symbol; End frag & setup for relax.
3229 Make sure there is enough room in this frag for the largest
3230 instruction we may generate in md_convert_frag. This is 2
3231 bytes for the opcode and room for the prefix and largest
3232 displacement. */
3233 frag_grow (prefix + 2 + 4);
3234 /* Prefix and 1 opcode byte go in fr_fix. */
3235 p = frag_more (prefix + 1);
3236 if (i.prefix[DATA_PREFIX] != 0)
3237 *p++ = DATA_PREFIX_OPCODE;
3238 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3239 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3240 *p++ = i.prefix[SEG_PREFIX];
3241 if (i.prefix[REX_PREFIX] != 0)
3242 *p++ = i.prefix[REX_PREFIX];
3243 *p = i.tm.base_opcode;
3244
3245 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3246 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3247 else if ((cpu_arch_flags & Cpu386) != 0)
3248 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3249 else
3250 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3251 subtype |= code16;
3e73aa7c 3252
29b0f896
AM		 3253 sym = i.op[0].disps->X_add_symbol;
3254 off = i.op[0].disps->X_add_number;
3e73aa7c 3255
29b0f896
AM		 3256 if (i.op[0].disps->X_op != O_constant
3257 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3258 {
29b0f896
AM		 3259 /* Handle complex expressions. */
3260 sym = make_expr_symbol (i.op[0].disps);
3261 off = 0;
3262 }
3e73aa7c 3263
29b0f896
AM		 3264 /* 1 possible extra opcode + 4 byte displacement go in var part.
3265 Pass reloc in fr_var. */
3266 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3267}
3e73aa7c 3268
29b0f896
AM		 3269static void
3270output_jump ()
3271{
3272 char *p;
3273 int size;
3e02c1cc 3274 fixS *fixP;
29b0f896
AM		 3275
3276 if (i.tm.opcode_modifier & JumpByte)
3277 {
3278 /* This is a loop or jecxz type instruction. */
3279 size = 1;
3280 if (i.prefix[ADDR_PREFIX] != 0)
3281 {
3282 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3283 i.prefixes -= 1;
3284 }
3285 /* Pentium4 branch hints. */
3286 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3287 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3288 {
3289 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3290 i.prefixes--;
3e73aa7c
JH		 3291 }
3292 }
29b0f896
AM		 3293 else
3294 {
3295 int code16;
3e73aa7c 3296
29b0f896
AM		 3297 code16 = 0;
3298 if (flag_code == CODE_16BIT)
3299 code16 = CODE16;
3e73aa7c 3300
29b0f896
AM		 3301 if (i.prefix[DATA_PREFIX] != 0)
3302 {
3303 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3304 i.prefixes -= 1;
3305 code16 ^= CODE16;
3306 }
252b5132 3307
29b0f896
AM		 3308 size = 4;
3309 if (code16)
3310 size = 2;
3311 }
9fcc94b6 3312
29b0f896
AM		 3313 if (i.prefix[REX_PREFIX] != 0)
3314 {
3315 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3316 i.prefixes -= 1;
3317 }
252b5132 3318
29b0f896
AM		 3319 if (i.prefixes != 0 && !intel_syntax)
3320 as_warn (_("skipping prefixes on this instruction"));
e0890092 3321
29b0f896
AM		 3322 p = frag_more (1 + size);
3323 *p++ = i.tm.base_opcode;
e0890092 3324
3e02c1cc
AM		 3325 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3326 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3327
3328 /* All jumps handled here are signed, but don't use a signed limit
3329 check for 32 and 16 bit jumps as we want to allow wrap around at
3330 4G and 64k respectively. */
3331 if (size == 1)
3332 fixP->fx_signed = 1;
29b0f896 3333}
e0890092 3334
29b0f896
AM		 3335static void
3336output_interseg_jump ()
3337{
3338 char *p;
3339 int size;
3340 int prefix;
3341 int code16;
252b5132 3342
29b0f896
AM		 3343 code16 = 0;
3344 if (flag_code == CODE_16BIT)
3345 code16 = CODE16;
a217f122 3346
29b0f896
AM		 3347 prefix = 0;
3348 if (i.prefix[DATA_PREFIX] != 0)
3349 {
3350 prefix = 1;
3351 i.prefixes -= 1;
3352 code16 ^= CODE16;
3353 }
3354 if (i.prefix[REX_PREFIX] != 0)
3355 {
3356 prefix++;
3357 i.prefixes -= 1;
3358 }
252b5132 3359
29b0f896
AM		 3360 size = 4;
3361 if (code16)
3362 size = 2;
252b5132 3363
29b0f896
AM		 3364 if (i.prefixes != 0 && !intel_syntax)
3365 as_warn (_("skipping prefixes on this instruction"));
252b5132 3366
29b0f896
AM		 3367 /* 1 opcode; 2 segment; offset */
3368 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3369
29b0f896
AM		 3370 if (i.prefix[DATA_PREFIX] != 0)
3371 *p++ = DATA_PREFIX_OPCODE;
252b5132 3372
29b0f896
AM		 3373 if (i.prefix[REX_PREFIX] != 0)
3374 *p++ = i.prefix[REX_PREFIX];
252b5132 3375
29b0f896
AM		 3376 *p++ = i.tm.base_opcode;
3377 if (i.op[1].imms->X_op == O_constant)
3378 {
3379 offsetT n = i.op[1].imms->X_add_number;
252b5132 3380
29b0f896
AM		 3381 if (size == 2
3382 && !fits_in_unsigned_word (n)
3383 && !fits_in_signed_word (n))
3384 {
3385 as_bad (_("16-bit jump out of range"));
3386 return;
3387 }
3388 md_number_to_chars (p, n, size);
3389 }
3390 else
3391 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3392 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3393 if (i.op[0].imms->X_op != O_constant)
3394 as_bad (_("can't handle non absolute segment in `%s'"),
3395 i.tm.name);
3396 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3397}
a217f122 3398
29b0f896
AM		 3399static void
3400output_insn ()
3401{
2bbd9c25
JJ		 3402 fragS *insn_start_frag;
3403 offsetT insn_start_off;
3404
29b0f896
AM		 3405 /* Tie dwarf2 debug info to the address at the start of the insn.
3406 We can't do this after the insn has been output as the current
3407 frag may have been closed off. eg. by frag_var. */
3408 dwarf2_emit_insn (0);
3409
2bbd9c25
JJ		 3410 insn_start_frag = frag_now;
3411 insn_start_off = frag_now_fix ();
3412
29b0f896
AM		 3413 /* Output jumps. */
3414 if (i.tm.opcode_modifier & Jump)
3415 output_branch ();
3416 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3417 output_jump ();
3418 else if (i.tm.opcode_modifier & JumpInterSegment)
3419 output_interseg_jump ();
3420 else
3421 {
3422 /* Output normal instructions here. */
3423 char *p;
3424 unsigned char *q;
252b5132 3425
bc4bd9ab
MK		 3426 /* All opcodes on i386 have either 1 or 2 bytes. We may use one
3427 more higher byte to specify a prefix the instruction
3428 requires. */
3429 if ((i.tm.base_opcode & 0xff0000) != 0)
3430 {
3431 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3432 {
3433 unsigned int prefix;
3434 prefix = (i.tm.base_opcode >> 16) & 0xff;
3435
3436 if (prefix != REPE_PREFIX_OPCODE
3437 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3438 add_prefix (prefix);
3439 }
3440 else
3441 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
0f10071e 3442 }
252b5132 3443
29b0f896
AM		 3444 /* The prefix bytes. */
3445 for (q = i.prefix;
3446 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3447 q++)
3448 {
3449 if (*q)
3450 {
3451 p = frag_more (1);
3452 md_number_to_chars (p, (valueT) *q, 1);
3453 }
3454 }
252b5132 3455
29b0f896
AM		 3456 /* Now the opcode; be careful about word order here! */
3457 if (fits_in_unsigned_byte (i.tm.base_opcode))
3458 {
3459 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3460 }
3461 else
3462 {
bc4bd9ab 3463 p = frag_more (2);
0f10071e 3464
29b0f896
AM		 3465 /* Put out high byte first: can't use md_number_to_chars! */
3466 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3467 *p = i.tm.base_opcode & 0xff;
3468 }
3e73aa7c 3469
29b0f896
AM		 3470 /* Now the modrm byte and sib byte (if present). */
3471 if (i.tm.opcode_modifier & Modrm)
3472 {
3473 p = frag_more (1);
3474 md_number_to_chars (p,
3475 (valueT) (i.rm.regmem << 0
3476 | i.rm.reg << 3
3477 | i.rm.mode << 6),
3478 1);
3479 /* If i.rm.regmem == ESP (4)
3480 && i.rm.mode != (Register mode)
3481 && not 16 bit
3482 ==> need second modrm byte. */
3483 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3484 && i.rm.mode != 3
3485 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3486 {
3487 p = frag_more (1);
3488 md_number_to_chars (p,
3489 (valueT) (i.sib.base << 0
3490 | i.sib.index << 3
3491 | i.sib.scale << 6),
3492 1);
3493 }
3494 }
3e73aa7c 3495
29b0f896 3496 if (i.disp_operands)
2bbd9c25 3497 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3498
29b0f896 3499 if (i.imm_operands)
2bbd9c25 3500 output_imm (insn_start_frag, insn_start_off);
29b0f896 3501 }
252b5132 3502
29b0f896
AM		 3503#ifdef DEBUG386
3504 if (flag_debug)
3505 {
3506 pi (line, &i);
3507 }
3508#endif /* DEBUG386 */
3509}
252b5132 3510
29b0f896 3511static void
2bbd9c25
JJ		 3512output_disp (insn_start_frag, insn_start_off)
3513 fragS *insn_start_frag;
3514 offsetT insn_start_off;
29b0f896
AM		 3515{
3516 char *p;
3517 unsigned int n;
252b5132 3518
29b0f896
AM		 3519 for (n = 0; n < i.operands; n++)
3520 {
3521 if (i.types[n] & Disp)
3522 {
3523 if (i.op[n].disps->X_op == O_constant)
3524 {
3525 int size;
3526 offsetT val;
252b5132 3527
29b0f896
AM		 3528 size = 4;
3529 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3530 {
3531 size = 2;
3532 if (i.types[n] & Disp8)
3533 size = 1;
3534 if (i.types[n] & Disp64)
3535 size = 8;
3536 }
3537 val = offset_in_range (i.op[n].disps->X_add_number,
3538 size);
3539 p = frag_more (size);
3540 md_number_to_chars (p, val, size);
3541 }
3542 else
3543 {
f86103b7 3544 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3545 int size = 4;
3546 int sign = 0;
3547 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3548
3549 /* The PC relative address is computed relative
3550 to the instruction boundary, so in case immediate
3551 fields follows, we need to adjust the value. */
3552 if (pcrel && i.imm_operands)
3553 {
3554 int imm_size = 4;
3555 unsigned int n1;
252b5132 3556
29b0f896
AM		 3557 for (n1 = 0; n1 < i.operands; n1++)
3558 if (i.types[n1] & Imm)
252b5132 3559 {
29b0f896 3560 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3561 {
29b0f896
AM		 3562 imm_size = 2;
3563 if (i.types[n1] & (Imm8 | Imm8S))
3564 imm_size = 1;
3565 if (i.types[n1] & Imm64)
3566 imm_size = 8;
252b5132 3567 }
29b0f896 3568 break;
252b5132 3569 }
29b0f896
AM		 3570 /* We should find the immediate. */
3571 if (n1 == i.operands)
3572 abort ();
3573 i.op[n].disps->X_add_number -= imm_size;
3574 }
520dc8e8 3575
29b0f896
AM		 3576 if (i.types[n] & Disp32S)
3577 sign = 1;
3e73aa7c 3578
29b0f896
AM		 3579 if (i.types[n] & (Disp16 | Disp64))
3580 {
3581 size = 2;
3582 if (i.types[n] & Disp64)
3583 size = 8;
3584 }
520dc8e8 3585
29b0f896 3586 p = frag_more (size);
2bbd9c25 3587 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 3588 if (GOT_symbol
2bbd9c25 3589 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113
JB		 3590 && (((reloc_type == BFD_RELOC_32
3591 || reloc_type == BFD_RELOC_X86_64_32S)
3592 && (i.op[n].disps->X_op == O_symbol
3593 || (i.op[n].disps->X_op == O_add
3594 && ((symbol_get_value_expression
3595 (i.op[n].disps->X_op_symbol)->X_op)
3596 == O_subtract))))
3597 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 3598 {
3599 offsetT add;
3600
3601 if (insn_start_frag == frag_now)
3602 add = (p - frag_now->fr_literal) - insn_start_off;
3603 else
3604 {
3605 fragS *fr;
3606
3607 add = insn_start_frag->fr_fix - insn_start_off;
3608 for (fr = insn_start_frag->fr_next;
3609 fr && fr != frag_now; fr = fr->fr_next)
3610 add += fr->fr_fix;
3611 add += p - frag_now->fr_literal;
3612 }
3613
d6ab8113
JB		 3614 if (flag_code != CODE_64BIT)
3615 reloc_type = BFD_RELOC_386_GOTPC;
3616 else
3617 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25
JJ		 3618 i.op[n].disps->X_add_number += add;
3619 }
062cd5e7 3620 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 3621 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 3622 }
3623 }
3624 }
3625}
252b5132 3626
29b0f896 3627static void
2bbd9c25
JJ		 3628output_imm (insn_start_frag, insn_start_off)
3629 fragS *insn_start_frag;
3630 offsetT insn_start_off;
29b0f896
AM		 3631{
3632 char *p;
3633 unsigned int n;
252b5132 3634
29b0f896
AM		 3635 for (n = 0; n < i.operands; n++)
3636 {
3637 if (i.types[n] & Imm)
3638 {
3639 if (i.op[n].imms->X_op == O_constant)
3640 {
3641 int size;
3642 offsetT val;
b4cac588 3643
29b0f896
AM		 3644 size = 4;
3645 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3646 {
3647 size = 2;
3648 if (i.types[n] & (Imm8 | Imm8S))
3649 size = 1;
3650 else if (i.types[n] & Imm64)
3651 size = 8;
3652 }
3653 val = offset_in_range (i.op[n].imms->X_add_number,
3654 size);
3655 p = frag_more (size);
3656 md_number_to_chars (p, val, size);
3657 }
3658 else
3659 {
3660 /* Not absolute_section.
3661 Need a 32-bit fixup (don't support 8bit
3662 non-absolute imms). Try to support other
3663 sizes ... */
f86103b7 3664 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3665 int size = 4;
3666 int sign = 0;
3667
3668 if ((i.types[n] & (Imm32S))
a7d61044
JB		 3669 && (i.suffix == QWORD_MNEM_SUFFIX
3670 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 3671 sign = 1;
3672 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3673 {
3674 size = 2;
3675 if (i.types[n] & (Imm8 | Imm8S))
3676 size = 1;
3677 if (i.types[n] & Imm64)
3678 size = 8;
3679 }
520dc8e8 3680
29b0f896
AM		 3681 p = frag_more (size);
3682 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 3683
2bbd9c25
JJ		 3684 /* This is tough to explain. We end up with this one if we
3685 * have operands that look like
3686 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3687 * obtain the absolute address of the GOT, and it is strongly
3688 * preferable from a performance point of view to avoid using
3689 * a runtime relocation for this. The actual sequence of
3690 * instructions often look something like:
3691 *
3692 * call .L66
3693 * .L66:
3694 * popl %ebx
3695 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3696 *
3697 * The call and pop essentially return the absolute address
3698 * of the label .L66 and store it in %ebx. The linker itself
3699 * will ultimately change the first operand of the addl so
3700 * that %ebx points to the GOT, but to keep things simple, the
3701 * .o file must have this operand set so that it generates not
3702 * the absolute address of .L66, but the absolute address of
3703 * itself. This allows the linker itself simply treat a GOTPC
3704 * relocation as asking for a pcrel offset to the GOT to be
3705 * added in, and the addend of the relocation is stored in the
3706 * operand field for the instruction itself.
3707 *
3708 * Our job here is to fix the operand so that it would add
3709 * the correct offset so that %ebx would point to itself. The
3710 * thing that is tricky is that .-.L66 will point to the
3711 * beginning of the instruction, so we need to further modify
3712 * the operand so that it will point to itself. There are
3713 * other cases where you have something like:
3714 *
3715 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3716 *
3717 * and here no correction would be required. Internally in
3718 * the assembler we treat operands of this form as not being
3719 * pcrel since the '.' is explicitly mentioned, and I wonder
3720 * whether it would simplify matters to do it this way. Who
3721 * knows. In earlier versions of the PIC patches, the
3722 * pcrel_adjust field was used to store the correction, but
3723 * since the expression is not pcrel, I felt it would be
3724 * confusing to do it this way. */
3725
d6ab8113
JB		 3726 if ((reloc_type == BFD_RELOC_32
3727 || reloc_type == BFD_RELOC_X86_64_32S)
29b0f896
AM		 3728 && GOT_symbol
3729 && GOT_symbol == i.op[n].imms->X_add_symbol
3730 && (i.op[n].imms->X_op == O_symbol
3731 || (i.op[n].imms->X_op == O_add
3732 && ((symbol_get_value_expression
3733 (i.op[n].imms->X_op_symbol)->X_op)
3734 == O_subtract))))
3735 {
2bbd9c25
JJ		 3736 offsetT add;
3737
3738 if (insn_start_frag == frag_now)
3739 add = (p - frag_now->fr_literal) - insn_start_off;
3740 else
3741 {
3742 fragS *fr;
3743
3744 add = insn_start_frag->fr_fix - insn_start_off;
3745 for (fr = insn_start_frag->fr_next;
3746 fr && fr != frag_now; fr = fr->fr_next)
3747 add += fr->fr_fix;
3748 add += p - frag_now->fr_literal;
3749 }
3750
d6ab8113
JB		 3751 if (flag_code != CODE_64BIT)
3752 reloc_type = BFD_RELOC_386_GOTPC;
3753 else
3754 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 3755 i.op[n].imms->X_add_number += add;
29b0f896 3756 }
29b0f896
AM		 3757 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3758 i.op[n].imms, 0, reloc_type);
3759 }
3760 }
3761 }
252b5132
RH		 3762}
3763\f
718ddfc0
JB		 3764#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
3765# define lex_got(reloc, adjust, types) NULL
3766#else
f3c180ae
AM		 3767/* Parse operands of the form
3768 <symbol>@GOTOFF+<nnn>
3769 and similar .plt or .got references.
3770
3771 If we find one, set up the correct relocation in RELOC and copy the
3772 input string, minus the `@GOTOFF' into a malloc'd buffer for
3773 parsing by the calling routine. Return this buffer, and if ADJUST
3774 is non-null set it to the length of the string we removed from the
3775 input line. Otherwise return NULL. */
3776static char *
3956db08
JB		 3777lex_got (enum bfd_reloc_code_real *reloc,
3778 int *adjust,
3779 unsigned int *types)
f3c180ae
AM		 3780{
3781 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3782 static const struct {
3783 const char *str;
f86103b7 3784 const enum bfd_reloc_code_real rel[NUM_FLAG_CODE];
3956db08 3785 const unsigned int types64;
f3c180ae 3786 } gotrel[] = {
3956db08
JB		 3787 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
3788 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
3789 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
3790 { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
3791 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 }, 0 },
3792 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
3793 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
3794 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3795 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 }, 0 },
3796 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3797 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0, 0 }, 0 },
3798 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0, 0 }, 0 },
3799 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32 }
f3c180ae
AM		 3800 };
3801 char *cp;
3802 unsigned int j;
3803
718ddfc0
JB		 3804 if (!IS_ELF)
3805 return NULL;
3806
f3c180ae
AM		 3807 for (cp = input_line_pointer; *cp != '@'; cp++)
3808 if (is_end_of_line[(unsigned char) *cp])
3809 return NULL;
3810
3811 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3812 {
3813 int len;
3814
3815 len = strlen (gotrel[j].str);
28f81592 3816 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae
AM		 3817 {
3818 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3819 {
28f81592
AM		 3820 int first, second;
3821 char *tmpbuf, *past_reloc;
f3c180ae
AM		 3822
3823 *reloc = gotrel[j].rel[(unsigned int) flag_code];
28f81592
AM		 3824 if (adjust)
3825 *adjust = len;
f3c180ae 3826
3956db08
JB		 3827 if (types)
3828 {
3829 if (flag_code != CODE_64BIT)
3830 *types = Imm32|Disp32;
3831 else
3832 *types = gotrel[j].types64;
3833 }
3834
f3c180ae
AM		 3835 if (GOT_symbol == NULL)
3836 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3837
3838 /* Replace the relocation token with ' ', so that
3839 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3840
3841 /* The length of the first part of our input line. */
f3c180ae 3842 first = cp - input_line_pointer;
28f81592
AM		 3843
3844 /* The second part goes from after the reloc token until
3845 (and including) an end_of_line char. Don't use strlen
3846 here as the end_of_line char may not be a NUL. */
3847 past_reloc = cp + 1 + len;
3848 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3849 ;
3850 second = cp - past_reloc;
3851
3852 /* Allocate and copy string. The trailing NUL shouldn't
3853 be necessary, but be safe. */
3854 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3855 memcpy (tmpbuf, input_line_pointer, first);
3856 tmpbuf[first] = ' ';
28f81592
AM		 3857 memcpy (tmpbuf + first + 1, past_reloc, second);
3858 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3859 return tmpbuf;
3860 }
3861
3862 as_bad (_("@%s reloc is not supported in %s bit mode"),
3863 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3864 return NULL;
3865 }
3866 }
3867
3868 /* Might be a symbol version string. Don't as_bad here. */
3869 return NULL;
3870}
3871
3872/* x86_cons_fix_new is called via the expression parsing code when a
3873 reloc is needed. We use this hook to get the correct .got reloc. */
f86103b7 3874static enum bfd_reloc_code_real got_reloc = NO_RELOC;
f3c180ae
AM		 3875
3876void
3877x86_cons_fix_new (frag, off, len, exp)
3878 fragS *frag;
3879 unsigned int off;
3880 unsigned int len;
3881 expressionS *exp;
3882{
3956db08 3883 enum bfd_reloc_code_real r = reloc (len, 0, -1, got_reloc);
f3c180ae
AM		 3884 got_reloc = NO_RELOC;
3885 fix_new_exp (frag, off, len, exp, 0, r);
3886}
3887
3888void
3889x86_cons (exp, size)
3890 expressionS *exp;
3891 int size;
3892{
d6ab8113 3893 if (size == 4 || (flag_code == CODE_64BIT && size == 8))
f3c180ae
AM		 3894 {
3895 /* Handle @GOTOFF and the like in an expression. */
3896 char *save;
3897 char *gotfree_input_line;
3898 int adjust;
3899
3900 save = input_line_pointer;
3956db08 3901 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 3902 if (gotfree_input_line)
3903 input_line_pointer = gotfree_input_line;
3904
3905 expression (exp);
3906
3907 if (gotfree_input_line)
3908 {
3909 /* expression () has merrily parsed up to the end of line,
3910 or a comma - in the wrong buffer. Transfer how far
3911 input_line_pointer has moved to the right buffer. */
3912 input_line_pointer = (save
3913 + (input_line_pointer - gotfree_input_line)
3914 + adjust);
3915 free (gotfree_input_line);
3916 }
3917 }
3918 else
3919 expression (exp);
3920}
3921#endif
3922
6482c264
NC		 3923#ifdef TE_PE
3924
6482c264
NC		 3925void
3926x86_pe_cons_fix_new (frag, off, len, exp)
3927 fragS *frag;
3928 unsigned int off;
3929 unsigned int len;
3930 expressionS *exp;
3931{
3956db08 3932 enum bfd_reloc_code_real r = reloc (len, 0, -1, NO_RELOC);
6482c264
NC		 3933
3934 if (exp->X_op == O_secrel)
3935 {
3936 exp->X_op = O_symbol;
3937 r = BFD_RELOC_32_SECREL;
3938 }
3939
3940 fix_new_exp (frag, off, len, exp, 0, r);
3941}
3942
3943static void
3944pe_directive_secrel (dummy)
3945 int dummy ATTRIBUTE_UNUSED;
3946{
3947 expressionS exp;
3948
3949 do
3950 {
3951 expression (&exp);
3952 if (exp.X_op == O_symbol)
3953 exp.X_op = O_secrel;
3954
3955 emit_expr (&exp, 4);
3956 }
3957 while (*input_line_pointer++ == ',');
3958
3959 input_line_pointer--;
3960 demand_empty_rest_of_line ();
3961}
3962
3963#endif
3964
252b5132
RH		 3965static int i386_immediate PARAMS ((char *));
3966
3967static int
3968i386_immediate (imm_start)
3969 char *imm_start;
3970{
3971 char *save_input_line_pointer;
f3c180ae 3972 char *gotfree_input_line;
252b5132 3973 segT exp_seg = 0;
47926f60 3974 expressionS *exp;
3956db08 3975 unsigned int types = ~0U;
252b5132
RH		 3976
3977 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3978 {
d0b47220 3979 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 3980 return 0;
3981 }
3982
3983 exp = &im_expressions[i.imm_operands++];
520dc8e8 3984 i.op[this_operand].imms = exp;
252b5132
RH		 3985
3986 if (is_space_char (*imm_start))
3987 ++imm_start;
3988
3989 save_input_line_pointer = input_line_pointer;
3990 input_line_pointer = imm_start;
3991
3956db08 3992 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 3993 if (gotfree_input_line)
3994 input_line_pointer = gotfree_input_line;
252b5132
RH		 3995
3996 exp_seg = expression (exp);
3997
83183c0c 3998 SKIP_WHITESPACE ();
252b5132 3999 if (*input_line_pointer)
f3c180ae 4000 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4001
4002 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4003 if (gotfree_input_line)
4004 free (gotfree_input_line);
252b5132 4005
2daf4fd8 4006 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4007 {
47926f60 4008 /* Missing or bad expr becomes absolute 0. */
d0b47220 4009 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4010 imm_start);
252b5132
RH		 4011 exp->X_op = O_constant;
4012 exp->X_add_number = 0;
4013 exp->X_add_symbol = (symbolS *) 0;
4014 exp->X_op_symbol = (symbolS *) 0;
252b5132 4015 }
3e73aa7c 4016 else if (exp->X_op == O_constant)
252b5132 4017 {
47926f60 4018 /* Size it properly later. */
3e73aa7c
JH		 4019 i.types[this_operand] |= Imm64;
4020 /* If BFD64, sign extend val. */
4021 if (!use_rela_relocations)
4022 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4023 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4024 }
4c63da97 4025#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4026 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4027 && exp_seg != absolute_section
47926f60 4028 && exp_seg != text_section
24eab124
AM		 4029 && exp_seg != data_section
4030 && exp_seg != bss_section
4031 && exp_seg != undefined_section
f86103b7 4032 && !bfd_is_com_section (exp_seg))
252b5132 4033 {
d0b47220 4034 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4035 return 0;
4036 }
4037#endif
4038 else
4039 {
4040 /* This is an address. The size of the address will be
24eab124 4041 determined later, depending on destination register,
3e73aa7c
JH		 4042 suffix, or the default for the section. */
4043 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4044 i.types[this_operand] &= types;
252b5132
RH		 4045 }
4046
4047 return 1;
4048}
4049
551c1ca1 4050static char *i386_scale PARAMS ((char *));
252b5132 4051
551c1ca1 4052static char *
252b5132
RH		 4053i386_scale (scale)
4054 char *scale;
4055{
551c1ca1
AM		 4056 offsetT val;
4057 char *save = input_line_pointer;
252b5132 4058
551c1ca1
AM		 4059 input_line_pointer = scale;
4060 val = get_absolute_expression ();
4061
4062 switch (val)
252b5132 4063 {
551c1ca1 4064 case 1:
252b5132
RH		 4065 i.log2_scale_factor = 0;
4066 break;
551c1ca1 4067 case 2:
252b5132
RH		 4068 i.log2_scale_factor = 1;
4069 break;
551c1ca1 4070 case 4:
252b5132
RH		 4071 i.log2_scale_factor = 2;
4072 break;
551c1ca1 4073 case 8:
252b5132
RH		 4074 i.log2_scale_factor = 3;
4075 break;
4076 default:
a724f0f4
JB		 4077 {
4078 char sep = *input_line_pointer;
4079
4080 *input_line_pointer = '\0';
4081 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4082 scale);
4083 *input_line_pointer = sep;
4084 input_line_pointer = save;
4085 return NULL;
4086 }
252b5132 4087 }
29b0f896 4088 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4089 {
4090 as_warn (_("scale factor of %d without an index register"),
24eab124 4091 1 << i.log2_scale_factor);
252b5132
RH		 4092#if SCALE1_WHEN_NO_INDEX
4093 i.log2_scale_factor = 0;
4094#endif
4095 }
551c1ca1
AM		 4096 scale = input_line_pointer;
4097 input_line_pointer = save;
4098 return scale;
252b5132
RH		 4099}
4100
4101static int i386_displacement PARAMS ((char *, char *));
4102
4103static int
4104i386_displacement (disp_start, disp_end)
4105 char *disp_start;
4106 char *disp_end;
4107{
29b0f896 4108 expressionS *exp;
252b5132
RH		 4109 segT exp_seg = 0;
4110 char *save_input_line_pointer;
f3c180ae 4111 char *gotfree_input_line;
252b5132 4112 int bigdisp = Disp32;
3956db08 4113 unsigned int types = Disp;
252b5132 4114
3e73aa7c 4115 if (flag_code == CODE_64BIT)
7ecd2f8b 4116 {
29b0f896 4117 if (i.prefix[ADDR_PREFIX] == 0)
3956db08 4118 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b
JH		 4119 }
4120 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4121 bigdisp = Disp16;
252b5132
RH		 4122 i.types[this_operand] |= bigdisp;
4123
4124 exp = &disp_expressions[i.disp_operands];
520dc8e8 4125 i.op[this_operand].disps = exp;
252b5132
RH		 4126 i.disp_operands++;
4127 save_input_line_pointer = input_line_pointer;
4128 input_line_pointer = disp_start;
4129 END_STRING_AND_SAVE (disp_end);
4130
4131#ifndef GCC_ASM_O_HACK
4132#define GCC_ASM_O_HACK 0
4133#endif
4134#if GCC_ASM_O_HACK
4135 END_STRING_AND_SAVE (disp_end + 1);
4136 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4137 && displacement_string_end[-1] == '+')
252b5132
RH		 4138 {
4139 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4140 constraint within gcc asm statements.
4141 For instance:
4142
4143 #define _set_tssldt_desc(n,addr,limit,type) \
4144 __asm__ __volatile__ ( \
4145 "movw %w2,%0\n\t" \
4146 "movw %w1,2+%0\n\t" \
4147 "rorl $16,%1\n\t" \
4148 "movb %b1,4+%0\n\t" \
4149 "movb %4,5+%0\n\t" \
4150 "movb $0,6+%0\n\t" \
4151 "movb %h1,7+%0\n\t" \
4152 "rorl $16,%1" \
4153 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4154
4155 This works great except that the output assembler ends
4156 up looking a bit weird if it turns out that there is
4157 no offset. You end up producing code that looks like:
4158
4159 #APP
4160 movw $235,(%eax)
4161 movw %dx,2+(%eax)
4162 rorl $16,%edx
4163 movb %dl,4+(%eax)
4164 movb $137,5+(%eax)
4165 movb $0,6+(%eax)
4166 movb %dh,7+(%eax)
4167 rorl $16,%edx
4168 #NO_APP
4169
47926f60 4170 So here we provide the missing zero. */
24eab124
AM		 4171
4172 *displacement_string_end = '0';
252b5132
RH		 4173 }
4174#endif
3956db08 4175 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4176 if (gotfree_input_line)
4177 input_line_pointer = gotfree_input_line;
252b5132 4178
24eab124 4179 exp_seg = expression (exp);
252b5132 4180
636c26b0
AM		 4181 SKIP_WHITESPACE ();
4182 if (*input_line_pointer)
4183 as_bad (_("junk `%s' after expression"), input_line_pointer);
4184#if GCC_ASM_O_HACK
4185 RESTORE_END_STRING (disp_end + 1);
4186#endif
4187 RESTORE_END_STRING (disp_end);
4188 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4189 if (gotfree_input_line)
4190 free (gotfree_input_line);
636c26b0 4191
24eab124
AM		 4192 /* We do this to make sure that the section symbol is in
4193 the symbol table. We will ultimately change the relocation
47926f60 4194 to be relative to the beginning of the section. */
1ae12ab7 4195 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4196 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4197 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4198 {
636c26b0
AM		 4199 if (exp->X_op != O_symbol)
4200 {
4201 as_bad (_("bad expression used with @%s"),
4202 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4203 ? "GOTPCREL"
4204 : "GOTOFF"));
4205 return 0;
4206 }
4207
e5cb08ac 4208 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4209 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4210 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4211 exp->X_op = O_subtract;
4212 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4213 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4214 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4215 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4216 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4217 else
29b0f896 4218 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4219 }
252b5132 4220
2daf4fd8
AM		 4221 if (exp->X_op == O_absent || exp->X_op == O_big)
4222 {
47926f60 4223 /* Missing or bad expr becomes absolute 0. */
d0b47220 4224 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4225 disp_start);
4226 exp->X_op = O_constant;
4227 exp->X_add_number = 0;
4228 exp->X_add_symbol = (symbolS *) 0;
4229 exp->X_op_symbol = (symbolS *) 0;
4230 }
4231
4c63da97 4232#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4233 if (exp->X_op != O_constant
45288df1 4234 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4235 && exp_seg != absolute_section
45288df1
AM		 4236 && exp_seg != text_section
4237 && exp_seg != data_section
4238 && exp_seg != bss_section
31312f95 4239 && exp_seg != undefined_section
f86103b7 4240 && !bfd_is_com_section (exp_seg))
24eab124 4241 {
d0b47220 4242 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4243 return 0;
4244 }
252b5132 4245#endif
3956db08
JB		 4246
4247 if (!(i.types[this_operand] & ~Disp))
4248 i.types[this_operand] &= types;
4249
252b5132
RH		 4250 return 1;
4251}
4252
e5cb08ac 4253static int i386_index_check PARAMS ((const char *));
252b5132 4254
eecb386c 4255/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4256 Return 1 on success, 0 on a failure. */
4257
252b5132 4258static int
eecb386c
AM		 4259i386_index_check (operand_string)
4260 const char *operand_string;
252b5132 4261{
3e73aa7c 4262 int ok;
24eab124 4263#if INFER_ADDR_PREFIX
eecb386c
AM		 4264 int fudged = 0;
4265
24eab124
AM		 4266 tryprefix:
4267#endif
3e73aa7c 4268 ok = 1;
30123838
JB		 4269 if ((current_templates->start->cpu_flags & CpuSVME)
4270 && current_templates->end[-1].operand_types[0] == AnyMem)
4271 {
4272 /* Memory operands of SVME insns are special in that they only allow
4273 rAX as their memory address and ignore any segment override. */
4274 unsigned RegXX;
4275
4276 /* SKINIT is even more restrictive: it always requires EAX. */
4277 if (strcmp (current_templates->start->name, "skinit") == 0)
4278 RegXX = Reg32;
4279 else if (flag_code == CODE_64BIT)
4280 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4281 else
4282 RegXX = (flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4283 ? Reg16
4284 : Reg32;
4285 if (!i.base_reg
4286 || !(i.base_reg->reg_type & Acc)
4287 || !(i.base_reg->reg_type & RegXX)
4288 || i.index_reg
4289 || (i.types[0] & Disp))
4290 ok = 0;
4291 }
4292 else if (flag_code == CODE_64BIT)
20f0a1fc
NC		 4293 {
4294 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4295
4296 if ((i.base_reg
4297 && ((i.base_reg->reg_type & RegXX) == 0)
4298 && (i.base_reg->reg_type != BaseIndex
4299 || i.index_reg))
4300 || (i.index_reg
4301 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4302 != (RegXX | BaseIndex))))
4303 ok = 0;
3e73aa7c
JH		 4304 }
4305 else
4306 {
4307 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4308 {
4309 /* 16bit checks. */
4310 if ((i.base_reg
29b0f896
AM		 4311 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4312 != (Reg16 | BaseIndex)))
3e73aa7c 4313 || (i.index_reg
29b0f896
AM		 4314 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4315 != (Reg16 | BaseIndex))
4316 || !(i.base_reg
4317 && i.base_reg->reg_num < 6
4318 && i.index_reg->reg_num >= 6
4319 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4320 ok = 0;
4321 }
4322 else
e5cb08ac 4323 {
3e73aa7c
JH		 4324 /* 32bit checks. */
4325 if ((i.base_reg
4326 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4327 || (i.index_reg
29b0f896
AM		 4328 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4329 != (Reg32 | BaseIndex))))
e5cb08ac 4330 ok = 0;
3e73aa7c
JH		 4331 }
4332 }
4333 if (!ok)
24eab124
AM		 4334 {
4335#if INFER_ADDR_PREFIX
20f0a1fc 4336 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4337 {
4338 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4339 i.prefixes += 1;
b23bac36
AM		 4340 /* Change the size of any displacement too. At most one of
4341 Disp16 or Disp32 is set.
4342 FIXME. There doesn't seem to be any real need for separate
4343 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4344 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4345 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
29b0f896 4346 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4347 fudged = 1;
24eab124
AM		 4348 goto tryprefix;
4349 }
eecb386c
AM		 4350 if (fudged)
4351 as_bad (_("`%s' is not a valid base/index expression"),
4352 operand_string);
4353 else
c388dee8 4354#endif
eecb386c
AM		 4355 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4356 operand_string,
3e73aa7c 4357 flag_code_names[flag_code]);
24eab124 4358 }
20f0a1fc 4359 return ok;
24eab124 4360}
252b5132 4361
252b5132 4362/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4363 on error. */
252b5132 4364
252b5132
RH		 4365static int
4366i386_operand (operand_string)
4367 char *operand_string;
4368{
af6bdddf
AM		 4369 const reg_entry *r;
4370 char *end_op;
24eab124 4371 char *op_string = operand_string;
252b5132 4372
24eab124 4373 if (is_space_char (*op_string))
252b5132
RH		 4374 ++op_string;
4375
24eab124 4376 /* We check for an absolute prefix (differentiating,
47926f60 4377 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4378 if (*op_string == ABSOLUTE_PREFIX)
4379 {
4380 ++op_string;
4381 if (is_space_char (*op_string))
4382 ++op_string;
4383 i.types[this_operand] |= JumpAbsolute;
4384 }
252b5132 4385
47926f60 4386 /* Check if operand is a register. */
af6bdddf
AM		 4387 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
4388 && (r = parse_register (op_string, &end_op)) != NULL)
24eab124 4389 {
24eab124
AM		 4390 /* Check for a segment override by searching for ':' after a
4391 segment register. */
4392 op_string = end_op;
4393 if (is_space_char (*op_string))
4394 ++op_string;
4395 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4396 {
4397 switch (r->reg_num)
4398 {
4399 case 0:
4400 i.seg[i.mem_operands] = &es;
4401 break;
4402 case 1:
4403 i.seg[i.mem_operands] = &cs;
4404 break;
4405 case 2:
4406 i.seg[i.mem_operands] = &ss;
4407 break;
4408 case 3:
4409 i.seg[i.mem_operands] = &ds;
4410 break;
4411 case 4:
4412 i.seg[i.mem_operands] = &fs;
4413 break;
4414 case 5:
4415 i.seg[i.mem_operands] = &gs;
4416 break;
4417 }
252b5132 4418
24eab124 4419 /* Skip the ':' and whitespace. */
252b5132
RH		 4420 ++op_string;
4421 if (is_space_char (*op_string))
24eab124 4422 ++op_string;
252b5132 4423
24eab124
AM		 4424 if (!is_digit_char (*op_string)
4425 && !is_identifier_char (*op_string)
4426 && *op_string != '('
4427 && *op_string != ABSOLUTE_PREFIX)
4428 {
4429 as_bad (_("bad memory operand `%s'"), op_string);
4430 return 0;
4431 }
47926f60 4432 /* Handle case of %es:*foo. */
24eab124
AM		 4433 if (*op_string == ABSOLUTE_PREFIX)
4434 {
4435 ++op_string;
4436 if (is_space_char (*op_string))
4437 ++op_string;
4438 i.types[this_operand] |= JumpAbsolute;
4439 }
4440 goto do_memory_reference;
4441 }
4442 if (*op_string)
4443 {
d0b47220 4444 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4445 return 0;
4446 }
4447 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4448 i.op[this_operand].regs = r;
24eab124
AM		 4449 i.reg_operands++;
4450 }
af6bdddf
AM		 4451 else if (*op_string == REGISTER_PREFIX)
4452 {
4453 as_bad (_("bad register name `%s'"), op_string);
4454 return 0;
4455 }
24eab124 4456 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4457 {
24eab124
AM		 4458 ++op_string;
4459 if (i.types[this_operand] & JumpAbsolute)
4460 {
d0b47220 4461 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4462 return 0;
4463 }
4464 if (!i386_immediate (op_string))
4465 return 0;
4466 }
4467 else if (is_digit_char (*op_string)
4468 || is_identifier_char (*op_string)
e5cb08ac 4469 || *op_string == '(')
24eab124 4470 {
47926f60 4471 /* This is a memory reference of some sort. */
af6bdddf 4472 char *base_string;
252b5132 4473
47926f60 4474 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4475 char *displacement_string_start;
4476 char *displacement_string_end;
252b5132 4477
24eab124 4478 do_memory_reference:
24eab124
AM		 4479 if ((i.mem_operands == 1
4480 && (current_templates->start->opcode_modifier & IsString) == 0)
4481 || i.mem_operands == 2)
4482 {
4483 as_bad (_("too many memory references for `%s'"),
4484 current_templates->start->name);
4485 return 0;
4486 }
252b5132 4487
24eab124
AM		 4488 /* Check for base index form. We detect the base index form by
4489 looking for an ')' at the end of the operand, searching
4490 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4491 after the '('. */
af6bdddf 4492 base_string = op_string + strlen (op_string);
c3332e24 4493
af6bdddf
AM		 4494 --base_string;
4495 if (is_space_char (*base_string))
4496 --base_string;
252b5132 4497
47926f60 4498 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4499 displacement_string_start = op_string;
4500 displacement_string_end = base_string + 1;
252b5132 4501
24eab124
AM		 4502 if (*base_string == ')')
4503 {
af6bdddf 4504 char *temp_string;
24eab124
AM		 4505 unsigned int parens_balanced = 1;
4506 /* We've already checked that the number of left & right ()'s are
47926f60 4507 equal, so this loop will not be infinite. */
24eab124
AM		 4508 do
4509 {
4510 base_string--;
4511 if (*base_string == ')')
4512 parens_balanced++;
4513 if (*base_string == '(')
4514 parens_balanced--;
4515 }
4516 while (parens_balanced);
c3332e24 4517
af6bdddf 4518 temp_string = base_string;
c3332e24 4519
24eab124 4520 /* Skip past '(' and whitespace. */
252b5132
RH		 4521 ++base_string;
4522 if (is_space_char (*base_string))
24eab124 4523 ++base_string;
252b5132 4524
af6bdddf
AM		 4525 if (*base_string == ','
4526 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4527 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4528 {
af6bdddf 4529 displacement_string_end = temp_string;
252b5132 4530
af6bdddf 4531 i.types[this_operand] |= BaseIndex;
252b5132 4532
af6bdddf 4533 if (i.base_reg)
24eab124 4534 {
24eab124
AM		 4535 base_string = end_op;
4536 if (is_space_char (*base_string))
4537 ++base_string;
af6bdddf
AM		 4538 }
4539
4540 /* There may be an index reg or scale factor here. */
4541 if (*base_string == ',')
4542 {
4543 ++base_string;
4544 if (is_space_char (*base_string))
4545 ++base_string;
4546
4547 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4548 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4549 {
af6bdddf 4550 base_string = end_op;
24eab124
AM		 4551 if (is_space_char (*base_string))
4552 ++base_string;
af6bdddf
AM		 4553 if (*base_string == ',')
4554 {
4555 ++base_string;
4556 if (is_space_char (*base_string))
4557 ++base_string;
4558 }
e5cb08ac 4559 else if (*base_string != ')')
af6bdddf
AM		 4560 {
4561 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4562 operand_string);
4563 return 0;
4564 }
24eab124 4565 }
af6bdddf 4566 else if (*base_string == REGISTER_PREFIX)
24eab124 4567 {
af6bdddf 4568 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4569 return 0;
4570 }
252b5132 4571
47926f60 4572 /* Check for scale factor. */
551c1ca1 4573 if (*base_string != ')')
af6bdddf 4574 {
551c1ca1
AM		 4575 char *end_scale = i386_scale (base_string);
4576
4577 if (!end_scale)
af6bdddf 4578 return 0;
24eab124 4579
551c1ca1 4580 base_string = end_scale;
af6bdddf
AM		 4581 if (is_space_char (*base_string))
4582 ++base_string;
4583 if (*base_string != ')')
4584 {
4585 as_bad (_("expecting `)' after scale factor in `%s'"),
4586 operand_string);
4587 return 0;
4588 }
4589 }
4590 else if (!i.index_reg)
24eab124 4591 {
af6bdddf
AM		 4592 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4593 *base_string);
24eab124
AM		 4594 return 0;
4595 }
4596 }
af6bdddf 4597 else if (*base_string != ')')
24eab124 4598 {
af6bdddf
AM		 4599 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4600 operand_string);
24eab124
AM		 4601 return 0;
4602 }
c3332e24 4603 }
af6bdddf 4604 else if (*base_string == REGISTER_PREFIX)
c3332e24 4605 {
af6bdddf 4606 as_bad (_("bad register name `%s'"), base_string);
24eab124 4607 return 0;
c3332e24 4608 }
24eab124
AM		 4609 }
4610
4611 /* If there's an expression beginning the operand, parse it,
4612 assuming displacement_string_start and
4613 displacement_string_end are meaningful. */
4614 if (displacement_string_start != displacement_string_end)
4615 {
4616 if (!i386_displacement (displacement_string_start,
4617 displacement_string_end))
4618 return 0;
4619 }
4620
4621 /* Special case for (%dx) while doing input/output op. */
4622 if (i.base_reg
4623 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4624 && i.index_reg == 0
4625 && i.log2_scale_factor == 0
4626 && i.seg[i.mem_operands] == 0
4627 && (i.types[this_operand] & Disp) == 0)
4628 {
4629 i.types[this_operand] = InOutPortReg;
4630 return 1;
4631 }
4632
eecb386c
AM		 4633 if (i386_index_check (operand_string) == 0)
4634 return 0;
24eab124
AM		 4635 i.mem_operands++;
4636 }
4637 else
ce8a8b2f
AM		 4638 {
4639 /* It's not a memory operand; argh! */
24eab124
AM		 4640 as_bad (_("invalid char %s beginning operand %d `%s'"),
4641 output_invalid (*op_string),
4642 this_operand + 1,
4643 op_string);
4644 return 0;
4645 }
47926f60 4646 return 1; /* Normal return. */
252b5132
RH		 4647}
4648\f
ee7fcc42
AM		 4649/* md_estimate_size_before_relax()
4650
4651 Called just before relax() for rs_machine_dependent frags. The x86
4652 assembler uses these frags to handle variable size jump
4653 instructions.
4654
4655 Any symbol that is now undefined will not become defined.
4656 Return the correct fr_subtype in the frag.
4657 Return the initial "guess for variable size of frag" to caller.
4658 The guess is actually the growth beyond the fixed part. Whatever
4659 we do to grow the fixed or variable part contributes to our
4660 returned value. */
4661
252b5132
RH		 4662int
4663md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4664 fragS *fragP;
4665 segT segment;
252b5132 4666{
252b5132 4667 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4668 check for un-relaxable symbols. On an ELF system, we can't relax
4669 an externally visible symbol, because it may be overridden by a
4670 shared library. */
4671 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4672#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 4673 || (IS_ELF
31312f95
AM		 4674 && (S_IS_EXTERNAL (fragP->fr_symbol)
4675 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 4676#endif
4677 )
252b5132 4678 {
b98ef147
AM		 4679 /* Symbol is undefined in this segment, or we need to keep a
4680 reloc so that weak symbols can be overridden. */
4681 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 4682 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 4683 unsigned char *opcode;
4684 int old_fr_fix;
f6af82bd 4685
ee7fcc42
AM		 4686 if (fragP->fr_var != NO_RELOC)
4687 reloc_type = fragP->fr_var;
b98ef147 4688 else if (size == 2)
f6af82bd
AM		 4689 reloc_type = BFD_RELOC_16_PCREL;
4690 else
4691 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4692
ee7fcc42
AM		 4693 old_fr_fix = fragP->fr_fix;
4694 opcode = (unsigned char *) fragP->fr_opcode;
4695
fddf5b5b 4696 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4697 {
fddf5b5b
AM		 4698 case UNCOND_JUMP:
4699 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4700 opcode[0] = 0xe9;
252b5132 4701 fragP->fr_fix += size;
062cd5e7
AS		 4702 fix_new (fragP, old_fr_fix, size,
4703 fragP->fr_symbol,
4704 fragP->fr_offset, 1,
4705 reloc_type);
252b5132
RH		 4706 break;
4707
fddf5b5b 4708 case COND_JUMP86:
412167cb
AM		 4709 if (size == 2
4710 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4711 {
4712 /* Negate the condition, and branch past an
4713 unconditional jump. */
4714 opcode[0] ^= 1;
4715 opcode[1] = 3;
4716 /* Insert an unconditional jump. */
4717 opcode[2] = 0xe9;
4718 /* We added two extra opcode bytes, and have a two byte
4719 offset. */
4720 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4721 fix_new (fragP, old_fr_fix + 2, 2,
4722 fragP->fr_symbol,
4723 fragP->fr_offset, 1,
4724 reloc_type);
fddf5b5b
AM		 4725 break;
4726 }
4727 /* Fall through. */
4728
4729 case COND_JUMP:
412167cb
AM		 4730 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4731 {
3e02c1cc
AM		 4732 fixS *fixP;
4733
412167cb 4734 fragP->fr_fix += 1;
3e02c1cc
AM		 4735 fixP = fix_new (fragP, old_fr_fix, 1,
4736 fragP->fr_symbol,
4737 fragP->fr_offset, 1,
4738 BFD_RELOC_8_PCREL);
4739 fixP->fx_signed = 1;
412167cb
AM		 4740 break;
4741 }
93c2a809 4742
24eab124 4743 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4744 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4745 opcode[1] = opcode[0] + 0x10;
f6af82bd 4746 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4747 /* We've added an opcode byte. */
4748 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4749 fix_new (fragP, old_fr_fix + 1, size,
4750 fragP->fr_symbol,
4751 fragP->fr_offset, 1,
4752 reloc_type);
252b5132 4753 break;
fddf5b5b
AM		 4754
4755 default:
4756 BAD_CASE (fragP->fr_subtype);
4757 break;
252b5132
RH		 4758 }
4759 frag_wane (fragP);
ee7fcc42 4760 return fragP->fr_fix - old_fr_fix;
252b5132 4761 }
93c2a809 4762
93c2a809
AM		 4763 /* Guess size depending on current relax state. Initially the relax
4764 state will correspond to a short jump and we return 1, because
4765 the variable part of the frag (the branch offset) is one byte
4766 long. However, we can relax a section more than once and in that
4767 case we must either set fr_subtype back to the unrelaxed state,
4768 or return the value for the appropriate branch. */
4769 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4770}
4771
47926f60
KH		 4772/* Called after relax() is finished.
4773
4774 In: Address of frag.
4775 fr_type == rs_machine_dependent.
4776 fr_subtype is what the address relaxed to.
4777
4778 Out: Any fixSs and constants are set up.
4779 Caller will turn frag into a ".space 0". */
4780
252b5132
RH		 4781void
4782md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4783 bfd *abfd ATTRIBUTE_UNUSED;
4784 segT sec ATTRIBUTE_UNUSED;
29b0f896 4785 fragS *fragP;
252b5132 4786{
29b0f896 4787 unsigned char *opcode;
252b5132 4788 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4789 offsetT target_address;
4790 offsetT opcode_address;
252b5132 4791 unsigned int extension = 0;
847f7ad4 4792 offsetT displacement_from_opcode_start;
252b5132
RH		 4793
4794 opcode = (unsigned char *) fragP->fr_opcode;
4795
47926f60 4796 /* Address we want to reach in file space. */
252b5132 4797 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4798
47926f60 4799 /* Address opcode resides at in file space. */
252b5132
RH		 4800 opcode_address = fragP->fr_address + fragP->fr_fix;
4801
47926f60 4802 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4803 displacement_from_opcode_start = target_address - opcode_address;
4804
fddf5b5b 4805 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4806 {
47926f60
KH		 4807 /* Don't have to change opcode. */
4808 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4809 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4810 }
4811 else
4812 {
4813 if (no_cond_jump_promotion
4814 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4815 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4816
fddf5b5b
AM		 4817 switch (fragP->fr_subtype)
4818 {
4819 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4820 extension = 4; /* 1 opcode + 4 displacement */
4821 opcode[0] = 0xe9;
4822 where_to_put_displacement = &opcode[1];
4823 break;
252b5132 4824
fddf5b5b
AM		 4825 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4826 extension = 2; /* 1 opcode + 2 displacement */
4827 opcode[0] = 0xe9;
4828 where_to_put_displacement = &opcode[1];
4829 break;
252b5132 4830
fddf5b5b
AM		 4831 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4832 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4833 extension = 5; /* 2 opcode + 4 displacement */
4834 opcode[1] = opcode[0] + 0x10;
4835 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4836 where_to_put_displacement = &opcode[2];
4837 break;
252b5132 4838
fddf5b5b
AM		 4839 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4840 extension = 3; /* 2 opcode + 2 displacement */
4841 opcode[1] = opcode[0] + 0x10;
4842 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4843 where_to_put_displacement = &opcode[2];
4844 break;
252b5132 4845
fddf5b5b
AM		 4846 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4847 extension = 4;
4848 opcode[0] ^= 1;
4849 opcode[1] = 3;
4850 opcode[2] = 0xe9;
4851 where_to_put_displacement = &opcode[3];
4852 break;
4853
4854 default:
4855 BAD_CASE (fragP->fr_subtype);
4856 break;
4857 }
252b5132 4858 }
fddf5b5b 4859
47926f60 4860 /* Now put displacement after opcode. */
252b5132
RH		 4861 md_number_to_chars ((char *) where_to_put_displacement,
4862 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4863 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 4864 fragP->fr_fix += extension;
4865}
4866\f
47926f60
KH		 4867/* Size of byte displacement jmp. */
4868int md_short_jump_size = 2;
4869
4870/* Size of dword displacement jmp. */
4871int md_long_jump_size = 5;
252b5132 4872
47926f60
KH		 4873/* Size of relocation record. */
4874const int md_reloc_size = 8;
252b5132
RH		 4875
4876void
4877md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4878 char *ptr;
4879 addressT from_addr, to_addr;
ab9da554
ILT		 4880 fragS *frag ATTRIBUTE_UNUSED;
4881 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4882{
847f7ad4 4883 offsetT offset;
252b5132
RH		 4884
4885 offset = to_addr - (from_addr + 2);
47926f60
KH		 4886 /* Opcode for byte-disp jump. */
4887 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 4888 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4889}
4890
4891void
4892md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4893 char *ptr;
4894 addressT from_addr, to_addr;
a38cf1db
AM		 4895 fragS *frag ATTRIBUTE_UNUSED;
4896 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4897{
847f7ad4 4898 offsetT offset;
252b5132 4899
a38cf1db
AM		 4900 offset = to_addr - (from_addr + 5);
4901 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4902 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 4903}
4904\f
4905/* Apply a fixup (fixS) to segment data, once it has been determined
4906 by our caller that we have all the info we need to fix it up.
4907
4908 On the 386, immediates, displacements, and data pointers are all in
4909 the same (little-endian) format, so we don't need to care about which
4910 we are handling. */
4911
94f592af 4912void
55cf6793 4913md_apply_fix (fixP, valP, seg)
47926f60
KH		 4914 /* The fix we're to put in. */
4915 fixS *fixP;
47926f60 4916 /* Pointer to the value of the bits. */
c6682705 4917 valueT *valP;
47926f60
KH		 4918 /* Segment fix is from. */
4919 segT seg ATTRIBUTE_UNUSED;
252b5132 4920{
94f592af 4921 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 4922 valueT value = *valP;
252b5132 4923
f86103b7 4924#if !defined (TE_Mach)
93382f6d
AM		 4925 if (fixP->fx_pcrel)
4926 {
4927 switch (fixP->fx_r_type)
4928 {
5865bb77
ILT		 4929 default:
4930 break;
4931
d6ab8113
JB		 4932 case BFD_RELOC_64:
4933 fixP->fx_r_type = BFD_RELOC_64_PCREL;
4934 break;
93382f6d 4935 case BFD_RELOC_32:
ae8887b5 4936 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 4937 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4938 break;
4939 case BFD_RELOC_16:
4940 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4941 break;
4942 case BFD_RELOC_8:
4943 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4944 break;
4945 }
4946 }
252b5132 4947
a161fe53 4948 if (fixP->fx_addsy != NULL
31312f95 4949 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 4950 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 4951 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4952 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4953 && !use_rela_relocations)
252b5132 4954 {
31312f95
AM		 4955 /* This is a hack. There should be a better way to handle this.
4956 This covers for the fact that bfd_install_relocation will
4957 subtract the current location (for partial_inplace, PC relative
4958 relocations); see more below. */
252b5132 4959#ifndef OBJ_AOUT
718ddfc0 4960 if (IS_ELF
252b5132
RH		 4961#ifdef TE_PE
4962 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4963#endif
4964 )
4965 value += fixP->fx_where + fixP->fx_frag->fr_address;
4966#endif
4967#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 4968 if (IS_ELF)
252b5132 4969 {
6539b54b 4970 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 4971
6539b54b 4972 if ((sym_seg == seg
2f66722d 4973 || (symbol_section_p (fixP->fx_addsy)
6539b54b 4974 && sym_seg != absolute_section))
ae6063d4 4975 && !generic_force_reloc (fixP))
2f66722d
AM		 4976 {
4977 /* Yes, we add the values in twice. This is because
6539b54b
AM		 4978 bfd_install_relocation subtracts them out again. I think
4979 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 4980 it. FIXME. */
4981 value += fixP->fx_where + fixP->fx_frag->fr_address;
4982 }
252b5132
RH		 4983 }
4984#endif
4985#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 4986 /* For some reason, the PE format does not store a
4987 section address offset for a PC relative symbol. */
4988 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
4989#if defined(BFD_ASSEMBLER) || defined(S_IS_WEAK)
4990 || S_IS_WEAK (fixP->fx_addsy)
4991#endif
4992 )
252b5132
RH		 4993 value += md_pcrel_from (fixP);
4994#endif
4995 }
4996
4997 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 4998 and we must not disappoint it. */
252b5132 4999#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5000 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5001 switch (fixP->fx_r_type)
5002 {
5003 case BFD_RELOC_386_PLT32:
3e73aa7c 5004 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5005 /* Make the jump instruction point to the address of the operand. At
5006 runtime we merely add the offset to the actual PLT entry. */
5007 value = -4;
5008 break;
31312f95 5009
13ae64f3
JJ		 5010 case BFD_RELOC_386_TLS_GD:
5011 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5012 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5013 case BFD_RELOC_386_TLS_IE:
5014 case BFD_RELOC_386_TLS_GOTIE:
bffbf940
JJ		 5015 case BFD_RELOC_X86_64_TLSGD:
5016 case BFD_RELOC_X86_64_TLSLD:
5017 case BFD_RELOC_X86_64_GOTTPOFF:
00f7efb6
JJ		 5018 value = 0; /* Fully resolved at runtime. No addend. */
5019 /* Fallthrough */
5020 case BFD_RELOC_386_TLS_LE:
5021 case BFD_RELOC_386_TLS_LDO_32:
5022 case BFD_RELOC_386_TLS_LE_32:
5023 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5024 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5025 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5026 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5027 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5028 break;
5029
5030 case BFD_RELOC_386_GOT32:
5031 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5032 value = 0; /* Fully resolved at runtime. No addend. */
5033 break;
47926f60
KH		 5034
5035 case BFD_RELOC_VTABLE_INHERIT:
5036 case BFD_RELOC_VTABLE_ENTRY:
5037 fixP->fx_done = 0;
94f592af 5038 return;
47926f60
KH		 5039
5040 default:
5041 break;
5042 }
5043#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5044 *valP = value;
f86103b7 5045#endif /* !defined (TE_Mach) */
3e73aa7c 5046
3e73aa7c 5047 /* Are we finished with this relocation now? */
c6682705 5048 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5049 fixP->fx_done = 1;
5050 else if (use_rela_relocations)
5051 {
5052 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5053 /* Remember value for tc_gen_reloc. */
5054 fixP->fx_addnumber = value;
3e73aa7c
JH		 5055 value = 0;
5056 }
f86103b7 5057
94f592af 5058 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5059}
252b5132 5060\f
252b5132
RH		 5061#define MAX_LITTLENUMS 6
5062
47926f60
KH		 5063/* Turn the string pointed to by litP into a floating point constant
5064 of type TYPE, and emit the appropriate bytes. The number of
5065 LITTLENUMS emitted is stored in *SIZEP. An error message is
5066 returned, or NULL on OK. */
5067
252b5132
RH		 5068char *
5069md_atof (type, litP, sizeP)
2ab9b79e 5070 int type;
252b5132
RH		 5071 char *litP;
5072 int *sizeP;
5073{
5074 int prec;
5075 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5076 LITTLENUM_TYPE *wordP;
5077 char *t;
5078
5079 switch (type)
5080 {
5081 case 'f':
5082 case 'F':
5083 prec = 2;
5084 break;
5085
5086 case 'd':
5087 case 'D':
5088 prec = 4;
5089 break;
5090
5091 case 'x':
5092 case 'X':
5093 prec = 5;
5094 break;
5095
5096 default:
5097 *sizeP = 0;
5098 return _("Bad call to md_atof ()");
5099 }
5100 t = atof_ieee (input_line_pointer, type, words);
5101 if (t)
5102 input_line_pointer = t;
5103
5104 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5105 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5106 the bigendian 386. */
5107 for (wordP = words + prec - 1; prec--;)
5108 {
5109 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5110 litP += sizeof (LITTLENUM_TYPE);
5111 }
5112 return 0;
5113}
5114\f
87c245cc 5115static char output_invalid_buf[8];
252b5132 5116
252b5132
RH		 5117static char *
5118output_invalid (c)
5119 int c;
5120{
3882b010 5121 if (ISPRINT (c))
252b5132
RH		 5122 sprintf (output_invalid_buf, "'%c'", c);
5123 else
5124 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
5125 return output_invalid_buf;
5126}
5127
af6bdddf 5128/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5129
5130static const reg_entry *
5131parse_register (reg_string, end_op)
5132 char *reg_string;
5133 char **end_op;
5134{
af6bdddf
AM		 5135 char *s = reg_string;
5136 char *p;
252b5132
RH		 5137 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5138 const reg_entry *r;
5139
5140 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5141 if (*s == REGISTER_PREFIX)
5142 ++s;
5143
5144 if (is_space_char (*s))
5145 ++s;
5146
5147 p = reg_name_given;
af6bdddf 5148 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5149 {
5150 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5151 return (const reg_entry *) NULL;
5152 s++;
252b5132
RH		 5153 }
5154
6588847e
DN		 5155 /* For naked regs, make sure that we are not dealing with an identifier.
5156 This prevents confusing an identifier like `eax_var' with register
5157 `eax'. */
5158 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5159 return (const reg_entry *) NULL;
5160
af6bdddf 5161 *end_op = s;
252b5132
RH		 5162
5163 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5164
5f47d35b 5165 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5166 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5167 {
5f47d35b
AM		 5168 if (is_space_char (*s))
5169 ++s;
5170 if (*s == '(')
5171 {
af6bdddf 5172 ++s;
5f47d35b
AM		 5173 if (is_space_char (*s))
5174 ++s;
5175 if (*s >= '0' && *s <= '7')
5176 {
5177 r = &i386_float_regtab[*s - '0'];
af6bdddf 5178 ++s;
5f47d35b
AM		 5179 if (is_space_char (*s))
5180 ++s;
5181 if (*s == ')')
5182 {
5183 *end_op = s + 1;
5184 return r;
5185 }
5f47d35b 5186 }
47926f60 5187 /* We have "%st(" then garbage. */
5f47d35b
AM		 5188 return (const reg_entry *) NULL;
5189 }
5190 }
5191
1ae00879 5192 if (r != NULL
20f0a1fc 5193 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5194 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5195 && flag_code != CODE_64BIT)
20f0a1fc 5196 return (const reg_entry *) NULL;
1ae00879 5197
252b5132
RH		 5198 return r;
5199}
5200\f
4cc782b5 5201#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5202const char *md_shortopts = "kVQ:sqn";
252b5132 5203#else
12b55ccc 5204const char *md_shortopts = "qn";
252b5132 5205#endif
6e0b89ee 5206
252b5132 5207struct option md_longopts[] = {
3e73aa7c
JH		 5208#define OPTION_32 (OPTION_MD_BASE + 0)
5209 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 5210#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c
JH		 5211#define OPTION_64 (OPTION_MD_BASE + 1)
5212 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5213#endif
252b5132
RH		 5214 {NULL, no_argument, NULL, 0}
5215};
5216size_t md_longopts_size = sizeof (md_longopts);
5217
5218int
5219md_parse_option (c, arg)
5220 int c;
ab9da554 5221 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 5222{
5223 switch (c)
5224 {
12b55ccc
L		 5225 case 'n':
5226 optimize_align_code = 0;
5227 break;
5228
a38cf1db
AM		 5229 case 'q':
5230 quiet_warnings = 1;
252b5132
RH		 5231 break;
5232
5233#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5234 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5235 should be emitted or not. FIXME: Not implemented. */
5236 case 'Q':
252b5132
RH		 5237 break;
5238
5239 /* -V: SVR4 argument to print version ID. */
5240 case 'V':
5241 print_version_id ();
5242 break;
5243
a38cf1db
AM		 5244 /* -k: Ignore for FreeBSD compatibility. */
5245 case 'k':
252b5132 5246 break;
4cc782b5
ILT		 5247
5248 case 's':
5249 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5250 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5251 break;
6e0b89ee 5252
3e73aa7c
JH		 5253 case OPTION_64:
5254 {
5255 const char **list, **l;
5256
3e73aa7c
JH		 5257 list = bfd_target_list ();
5258 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 5259 if (strcmp (*l, "elf64-x86-64") == 0)
5260 {
5261 default_arch = "x86_64";
5262 break;
5263 }
3e73aa7c 5264 if (*l == NULL)
6e0b89ee 5265 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5266 free (list);
5267 }
5268 break;
5269#endif
252b5132 5270
6e0b89ee
AM		 5271 case OPTION_32:
5272 default_arch = "i386";
5273 break;
5274
252b5132
RH		 5275 default:
5276 return 0;
5277 }
5278 return 1;
5279}
5280
5281void
5282md_show_usage (stream)
5283 FILE *stream;
5284{
4cc782b5
ILT		 5285#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5286 fprintf (stream, _("\
a38cf1db
AM		 5287 -Q ignored\n\
5288 -V print assembler version number\n\
5289 -k ignored\n\
12b55ccc 5290 -n Do not optimize code alignment\n\
a38cf1db
AM		 5291 -q quieten some warnings\n\
5292 -s ignored\n"));
5293#else
5294 fprintf (stream, _("\
12b55ccc 5295 -n Do not optimize code alignment\n\
a38cf1db 5296 -q quieten some warnings\n"));
4cc782b5 5297#endif
252b5132
RH		 5298}
5299
3e73aa7c
JH		 5300#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5301 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 5302
5303/* Pick the target format to use. */
5304
47926f60 5305const char *
252b5132
RH		 5306i386_target_format ()
5307{
3e73aa7c
JH		 5308 if (!strcmp (default_arch, "x86_64"))
5309 set_code_flag (CODE_64BIT);
5310 else if (!strcmp (default_arch, "i386"))
5311 set_code_flag (CODE_32BIT);
5312 else
5313 as_fatal (_("Unknown architecture"));
252b5132
RH		 5314 switch (OUTPUT_FLAVOR)
5315 {
4c63da97
AM		 5316#ifdef OBJ_MAYBE_AOUT
5317 case bfd_target_aout_flavour:
47926f60 5318 return AOUT_TARGET_FORMAT;
4c63da97
AM		 5319#endif
5320#ifdef OBJ_MAYBE_COFF
252b5132
RH		 5321 case bfd_target_coff_flavour:
5322 return "coff-i386";
4c63da97 5323#endif
3e73aa7c 5324#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 5325 case bfd_target_elf_flavour:
3e73aa7c 5326 {
e5cb08ac
KH		 5327 if (flag_code == CODE_64BIT)
5328 use_rela_relocations = 1;
4ada7262 5329 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
3e73aa7c 5330 }
4c63da97 5331#endif
252b5132
RH		 5332 default:
5333 abort ();
5334 return NULL;
5335 }
5336}
5337
47926f60 5338#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 5339
5340#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5341void i386_elf_emit_arch_note ()
5342{
718ddfc0 5343 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 5344 {
5345 char *p;
5346 asection *seg = now_seg;
5347 subsegT subseg = now_subseg;
5348 Elf_Internal_Note i_note;
5349 Elf_External_Note e_note;
5350 asection *note_secp;
5351 int len;
5352
5353 /* Create the .note section. */
5354 note_secp = subseg_new (".note", 0);
5355 bfd_set_section_flags (stdoutput,
5356 note_secp,
5357 SEC_HAS_CONTENTS | SEC_READONLY);
5358
5359 /* Process the arch string. */
5360 len = strlen (cpu_arch_name);
5361
5362 i_note.namesz = len + 1;
5363 i_note.descsz = 0;
5364 i_note.type = NT_ARCH;
5365 p = frag_more (sizeof (e_note.namesz));
5366 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5367 p = frag_more (sizeof (e_note.descsz));
5368 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5369 p = frag_more (sizeof (e_note.type));
5370 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5371 p = frag_more (len + 1);
5372 strcpy (p, cpu_arch_name);
5373
5374 frag_align (2, 0, 0);
5375
5376 subseg_set (seg, subseg);
5377 }
5378}
5379#endif
252b5132 5380\f
252b5132
RH		 5381symbolS *
5382md_undefined_symbol (name)
5383 char *name;
5384{
18dc2407
ILT		 5385 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5386 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5387 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5388 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 5389 {
5390 if (!GOT_symbol)
5391 {
5392 if (symbol_find (name))
5393 as_bad (_("GOT already in symbol table"));
5394 GOT_symbol = symbol_new (name, undefined_section,
5395 (valueT) 0, &zero_address_frag);
5396 };
5397 return GOT_symbol;
5398 }
252b5132
RH		 5399 return 0;
5400}
5401
5402/* Round up a section size to the appropriate boundary. */
47926f60 5403
252b5132
RH		 5404valueT
5405md_section_align (segment, size)
ab9da554 5406 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 5407 valueT size;
5408{
4c63da97
AM		 5409#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5410 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5411 {
5412 /* For a.out, force the section size to be aligned. If we don't do
5413 this, BFD will align it for us, but it will not write out the
5414 final bytes of the section. This may be a bug in BFD, but it is
5415 easier to fix it here since that is how the other a.out targets
5416 work. */
5417 int align;
5418
5419 align = bfd_get_section_alignment (stdoutput, segment);
5420 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5421 }
252b5132
RH		 5422#endif
5423
5424 return size;
5425}
5426
5427/* On the i386, PC-relative offsets are relative to the start of the
5428 next instruction. That is, the address of the offset, plus its
5429 size, since the offset is always the last part of the insn. */
5430
5431long
5432md_pcrel_from (fixP)
5433 fixS *fixP;
5434{
5435 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5436}
5437
5438#ifndef I386COFF
5439
5440static void
5441s_bss (ignore)
ab9da554 5442 int ignore ATTRIBUTE_UNUSED;
252b5132 5443{
29b0f896 5444 int temp;
252b5132 5445
8a75718c
JB		 5446#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5447 if (IS_ELF)
5448 obj_elf_section_change_hook ();
5449#endif
252b5132
RH		 5450 temp = get_absolute_expression ();
5451 subseg_set (bss_section, (subsegT) temp);
5452 demand_empty_rest_of_line ();
5453}
5454
5455#endif
5456
252b5132
RH		 5457void
5458i386_validate_fix (fixp)
5459 fixS *fixp;
5460{
5461 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5462 {
23df1078
JH		 5463 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5464 {
5465 if (flag_code != CODE_64BIT)
5466 abort ();
5467 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5468 }
5469 else
5470 {
d6ab8113
JB		 5471 if (flag_code != CODE_64BIT)
5472 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5473 else
5474 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 5475 }
252b5132
RH		 5476 fixp->fx_subsy = 0;
5477 }
5478}
5479
252b5132
RH		 5480arelent *
5481tc_gen_reloc (section, fixp)
ab9da554 5482 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5483 fixS *fixp;
5484{
5485 arelent *rel;
5486 bfd_reloc_code_real_type code;
5487
5488 switch (fixp->fx_r_type)
5489 {
3e73aa7c
JH		 5490 case BFD_RELOC_X86_64_PLT32:
5491 case BFD_RELOC_X86_64_GOT32:
5492 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5493 case BFD_RELOC_386_PLT32:
5494 case BFD_RELOC_386_GOT32:
5495 case BFD_RELOC_386_GOTOFF:
5496 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5497 case BFD_RELOC_386_TLS_GD:
5498 case BFD_RELOC_386_TLS_LDM:
5499 case BFD_RELOC_386_TLS_LDO_32:
5500 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5501 case BFD_RELOC_386_TLS_IE:
5502 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 5503 case BFD_RELOC_386_TLS_LE_32:
5504 case BFD_RELOC_386_TLS_LE:
bffbf940
JJ		 5505 case BFD_RELOC_X86_64_TLSGD:
5506 case BFD_RELOC_X86_64_TLSLD:
5507 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5508 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 5509 case BFD_RELOC_X86_64_GOTTPOFF:
5510 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 5511 case BFD_RELOC_X86_64_TPOFF64:
5512 case BFD_RELOC_X86_64_GOTOFF64:
5513 case BFD_RELOC_X86_64_GOTPC32:
252b5132
RH		 5514 case BFD_RELOC_RVA:
5515 case BFD_RELOC_VTABLE_ENTRY:
5516 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 5517#ifdef TE_PE
5518 case BFD_RELOC_32_SECREL:
5519#endif
252b5132
RH		 5520 code = fixp->fx_r_type;
5521 break;
dbbaec26
L		 5522 case BFD_RELOC_X86_64_32S:
5523 if (!fixp->fx_pcrel)
5524 {
5525 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5526 code = fixp->fx_r_type;
5527 break;
5528 }
252b5132 5529 default:
93382f6d 5530 if (fixp->fx_pcrel)
252b5132 5531 {
93382f6d
AM		 5532 switch (fixp->fx_size)
5533 {
5534 default:
b091f402
AM		 5535 as_bad_where (fixp->fx_file, fixp->fx_line,
5536 _("can not do %d byte pc-relative relocation"),
5537 fixp->fx_size);
93382f6d
AM		 5538 code = BFD_RELOC_32_PCREL;
5539 break;
5540 case 1: code = BFD_RELOC_8_PCREL; break;
5541 case 2: code = BFD_RELOC_16_PCREL; break;
5542 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 5543#ifdef BFD64
5544 case 8: code = BFD_RELOC_64_PCREL; break;
5545#endif
93382f6d
AM		 5546 }
5547 }
5548 else
5549 {
5550 switch (fixp->fx_size)
5551 {
5552 default:
b091f402
AM		 5553 as_bad_where (fixp->fx_file, fixp->fx_line,
5554 _("can not do %d byte relocation"),
5555 fixp->fx_size);
93382f6d
AM		 5556 code = BFD_RELOC_32;
5557 break;
5558 case 1: code = BFD_RELOC_8; break;
5559 case 2: code = BFD_RELOC_16; break;
5560 case 4: code = BFD_RELOC_32; break;
937149dd 5561#ifdef BFD64
3e73aa7c 5562 case 8: code = BFD_RELOC_64; break;
937149dd 5563#endif
93382f6d 5564 }
252b5132
RH		 5565 }
5566 break;
5567 }
252b5132 5568
d6ab8113 5569 if ((code == BFD_RELOC_32 || code == BFD_RELOC_32_PCREL)
252b5132
RH		 5570 && GOT_symbol
5571 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 5572 {
d6ab8113
JB		 5573 if (flag_code != CODE_64BIT)
5574 code = BFD_RELOC_386_GOTPC;
5575 else
5576 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 5577 }
252b5132
RH		 5578
5579 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5580 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5581 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5582
5583 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 5584
3e73aa7c
JH		 5585 if (!use_rela_relocations)
5586 {
5587 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5588 vtable entry to be used in the relocation's section offset. */
5589 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5590 rel->address = fixp->fx_offset;
252b5132 5591
c6682705 5592 rel->addend = 0;
3e73aa7c
JH		 5593 }
5594 /* Use the rela in 64bit mode. */
252b5132 5595 else
3e73aa7c 5596 {
062cd5e7
AS		 5597 if (!fixp->fx_pcrel)
5598 rel->addend = fixp->fx_offset;
5599 else
5600 switch (code)
5601 {
5602 case BFD_RELOC_X86_64_PLT32:
5603 case BFD_RELOC_X86_64_GOT32:
5604 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 5605 case BFD_RELOC_X86_64_TLSGD:
5606 case BFD_RELOC_X86_64_TLSLD:
5607 case BFD_RELOC_X86_64_GOTTPOFF:
062cd5e7
AS		 5608 rel->addend = fixp->fx_offset - fixp->fx_size;
5609 break;
5610 default:
5611 rel->addend = (section->vma
5612 - fixp->fx_size
5613 + fixp->fx_addnumber
5614 + md_pcrel_from (fixp));
5615 break;
5616 }
3e73aa7c
JH		 5617 }
5618
252b5132
RH		 5619 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5620 if (rel->howto == NULL)
5621 {
5622 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5623 _("cannot represent relocation type %s"),
252b5132
RH		 5624 bfd_get_reloc_code_name (code));
5625 /* Set howto to a garbage value so that we can keep going. */
5626 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5627 assert (rel->howto != NULL);
5628 }
5629
5630 return rel;
5631}
5632
64a0c779
DN		 5633\f
5634/* Parse operands using Intel syntax. This implements a recursive descent
5635 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5636 Programmer's Guide.
5637
5638 FIXME: We do not recognize the full operand grammar defined in the MASM
5639 documentation. In particular, all the structure/union and
5640 high-level macro operands are missing.
5641
5642 Uppercase words are terminals, lower case words are non-terminals.
5643 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5644 bars '|' denote choices. Most grammar productions are implemented in
5645 functions called 'intel_<production>'.
5646
5647 Initial production is 'expr'.
5648
9306ca4a 5649 addOp + | -
64a0c779
DN		 5650
5651 alpha [a-zA-Z]
5652
9306ca4a
JB		 5653 binOp & | AND | \| | OR | ^ | XOR
5654
64a0c779
DN		 5655 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5656
5657 constant digits [[ radixOverride ]]
5658
9306ca4a 5659 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 5660
5661 digits decdigit
b77a7acd
AJ		 5662 | digits decdigit
5663 | digits hexdigit
64a0c779
DN		 5664
5665 decdigit [0-9]
5666
9306ca4a
JB		 5667 e04 e04 addOp e05
5668 | e05
5669
5670 e05 e05 binOp e06
b77a7acd 5671 | e06
64a0c779
DN		 5672
5673 e06 e06 mulOp e09
b77a7acd 5674 | e09
64a0c779
DN		 5675
5676 e09 OFFSET e10
a724f0f4
JB		 5677 | SHORT e10
5678 | + e10
5679 | - e10
9306ca4a
JB		 5680 | ~ e10
5681 | NOT e10
64a0c779
DN		 5682 | e09 PTR e10
5683 | e09 : e10
5684 | e10
5685
5686 e10 e10 [ expr ]
b77a7acd 5687 | e11
64a0c779
DN		 5688
5689 e11 ( expr )
b77a7acd 5690 | [ expr ]
64a0c779
DN		 5691 | constant
5692 | dataType
5693 | id
5694 | $
5695 | register
5696
a724f0f4 5697 => expr expr cmpOp e04
9306ca4a 5698 | e04
64a0c779
DN		 5699
5700 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5701 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5702
5703 hexdigit a | b | c | d | e | f
b77a7acd 5704 | A | B | C | D | E | F
64a0c779
DN		 5705
5706 id alpha
b77a7acd 5707 | id alpha
64a0c779
DN		 5708 | id decdigit
5709
9306ca4a 5710 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 5711
5712 quote " | '
5713
5714 register specialRegister
b77a7acd 5715 | gpRegister
64a0c779
DN		 5716 | byteRegister
5717
5718 segmentRegister CS | DS | ES | FS | GS | SS
5719
9306ca4a 5720 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 5721 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5722 | TR3 | TR4 | TR5 | TR6 | TR7
5723
64a0c779
DN		 5724 We simplify the grammar in obvious places (e.g., register parsing is
5725 done by calling parse_register) and eliminate immediate left recursion
5726 to implement a recursive-descent parser.
5727
a724f0f4
JB		 5728 expr e04 expr'
5729
5730 expr' cmpOp e04 expr'
5731 | Empty
9306ca4a
JB		 5732
5733 e04 e05 e04'
5734
5735 e04' addOp e05 e04'
5736 | Empty
64a0c779
DN		 5737
5738 e05 e06 e05'
5739
9306ca4a 5740 e05' binOp e06 e05'
b77a7acd 5741 | Empty
64a0c779
DN		 5742
5743 e06 e09 e06'
5744
5745 e06' mulOp e09 e06'
b77a7acd 5746 | Empty
64a0c779
DN		 5747
5748 e09 OFFSET e10 e09'
a724f0f4
JB		 5749 | SHORT e10'
5750 | + e10'
5751 | - e10'
5752 | ~ e10'
5753 | NOT e10'
b77a7acd 5754 | e10 e09'
64a0c779
DN		 5755
5756 e09' PTR e10 e09'
b77a7acd 5757 | : e10 e09'
64a0c779
DN		 5758 | Empty
5759
5760 e10 e11 e10'
5761
5762 e10' [ expr ] e10'
b77a7acd 5763 | Empty
64a0c779
DN		 5764
5765 e11 ( expr )
b77a7acd 5766 | [ expr ]
64a0c779
DN		 5767 | BYTE
5768 | WORD
5769 | DWORD
9306ca4a 5770 | FWORD
64a0c779 5771 | QWORD
9306ca4a
JB		 5772 | TBYTE
5773 | OWORD
5774 | XMMWORD
64a0c779
DN		 5775 | .
5776 | $
5777 | register
5778 | id
5779 | constant */
5780
5781/* Parsing structure for the intel syntax parser. Used to implement the
5782 semantic actions for the operand grammar. */
5783struct intel_parser_s
5784 {
5785 char *op_string; /* The string being parsed. */
5786 int got_a_float; /* Whether the operand is a float. */
4a1805b1 5787 int op_modifier; /* Operand modifier. */
64a0c779 5788 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 5789 int in_offset; /* >=1 if parsing operand of offset. */
5790 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 5791 const reg_entry *reg; /* Last register reference found. */
5792 char *disp; /* Displacement string being built. */
a724f0f4 5793 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 5794 };
5795
5796static struct intel_parser_s intel_parser;
5797
5798/* Token structure for parsing intel syntax. */
5799struct intel_token
5800 {
5801 int code; /* Token code. */
5802 const reg_entry *reg; /* Register entry for register tokens. */
5803 char *str; /* String representation. */
5804 };
5805
5806static struct intel_token cur_token, prev_token;
5807
50705ef4
AM		 5808/* Token codes for the intel parser. Since T_SHORT is already used
5809 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 5810#define T_NIL -1
5811#define T_CONST 1
5812#define T_REG 2
5813#define T_BYTE 3
5814#define T_WORD 4
9306ca4a
JB		 5815#define T_DWORD 5
5816#define T_FWORD 6
5817#define T_QWORD 7
5818#define T_TBYTE 8
5819#define T_XMMWORD 9
50705ef4 5820#undef T_SHORT
9306ca4a
JB		 5821#define T_SHORT 10
5822#define T_OFFSET 11
5823#define T_PTR 12
5824#define T_ID 13
5825#define T_SHL 14
5826#define T_SHR 15
64a0c779
DN		 5827
5828/* Prototypes for intel parser functions. */
5829static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 5830static void intel_get_token PARAMS ((void));
5831static void intel_putback_token PARAMS ((void));
5832static int intel_expr PARAMS ((void));
9306ca4a 5833static int intel_e04 PARAMS ((void));
cce0cbdc 5834static int intel_e05 PARAMS ((void));
cce0cbdc 5835static int intel_e06 PARAMS ((void));
cce0cbdc 5836static int intel_e09 PARAMS ((void));
a724f0f4 5837static int intel_bracket_expr PARAMS ((void));
cce0cbdc 5838static int intel_e10 PARAMS ((void));
cce0cbdc 5839static int intel_e11 PARAMS ((void));
64a0c779 5840
64a0c779
DN		 5841static int
5842i386_intel_operand (operand_string, got_a_float)
5843 char *operand_string;
5844 int got_a_float;
5845{
5846 int ret;
5847 char *p;
5848
a724f0f4
JB		 5849 p = intel_parser.op_string = xstrdup (operand_string);
5850 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
5851
5852 for (;;)
64a0c779 5853 {
a724f0f4
JB		 5854 /* Initialize token holders. */
5855 cur_token.code = prev_token.code = T_NIL;
5856 cur_token.reg = prev_token.reg = NULL;
5857 cur_token.str = prev_token.str = NULL;
5858
5859 /* Initialize parser structure. */
5860 intel_parser.got_a_float = got_a_float;
5861 intel_parser.op_modifier = 0;
5862 intel_parser.is_mem = 0;
5863 intel_parser.in_offset = 0;
5864 intel_parser.in_bracket = 0;
5865 intel_parser.reg = NULL;
5866 intel_parser.disp[0] = '\0';
5867 intel_parser.next_operand = NULL;
5868
5869 /* Read the first token and start the parser. */
5870 intel_get_token ();
5871 ret = intel_expr ();
5872
5873 if (!ret)
5874 break;
5875
9306ca4a
JB		 5876 if (cur_token.code != T_NIL)
5877 {
5878 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
5879 current_templates->start->name, cur_token.str);
5880 ret = 0;
5881 }
64a0c779
DN		 5882 /* If we found a memory reference, hand it over to i386_displacement
5883 to fill in the rest of the operand fields. */
9306ca4a 5884 else if (intel_parser.is_mem)
64a0c779
DN		 5885 {
5886 if ((i.mem_operands == 1
5887 && (current_templates->start->opcode_modifier & IsString) == 0)
5888 || i.mem_operands == 2)
5889 {
5890 as_bad (_("too many memory references for '%s'"),
5891 current_templates->start->name);
5892 ret = 0;
5893 }
5894 else
5895 {
5896 char *s = intel_parser.disp;
5897 i.mem_operands++;
5898
a724f0f4
JB		 5899 if (!quiet_warnings && intel_parser.is_mem < 0)
5900 /* See the comments in intel_bracket_expr. */
5901 as_warn (_("Treating `%s' as memory reference"), operand_string);
5902
64a0c779
DN		 5903 /* Add the displacement expression. */
5904 if (*s != '\0')
a4622f40
AM		 5905 ret = i386_displacement (s, s + strlen (s));
5906 if (ret)
a724f0f4
JB		 5907 {
5908 /* Swap base and index in 16-bit memory operands like
5909 [si+bx]. Since i386_index_check is also used in AT&T
5910 mode we have to do that here. */
5911 if (i.base_reg
5912 && i.index_reg
5913 && (i.base_reg->reg_type & Reg16)
5914 && (i.index_reg->reg_type & Reg16)
5915 && i.base_reg->reg_num >= 6
5916 && i.index_reg->reg_num < 6)
5917 {
5918 const reg_entry *base = i.index_reg;
5919
5920 i.index_reg = i.base_reg;
5921 i.base_reg = base;
5922 }
5923 ret = i386_index_check (operand_string);
5924 }
64a0c779
DN		 5925 }
5926 }
5927
5928 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 5929 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 5930 || intel_parser.reg == NULL)
5931 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 5932
5933 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
5934 ret = 0;
5935 if (!ret || !intel_parser.next_operand)
5936 break;
5937 intel_parser.op_string = intel_parser.next_operand;
5938 this_operand = i.operands++;
64a0c779
DN		 5939 }
5940
5941 free (p);
5942 free (intel_parser.disp);
5943
5944 return ret;
5945}
5946
a724f0f4
JB		 5947#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
5948
5949/* expr e04 expr'
5950
5951 expr' cmpOp e04 expr'
5952 | Empty */
64a0c779
DN		 5953static int
5954intel_expr ()
5955{
a724f0f4
JB		 5956 /* XXX Implement the comparison operators. */
5957 return intel_e04 ();
9306ca4a
JB		 5958}
5959
a724f0f4 5960/* e04 e05 e04'
9306ca4a 5961
a724f0f4 5962 e04' addOp e05 e04'
9306ca4a
JB		 5963 | Empty */
5964static int
5965intel_e04 ()
5966{
a724f0f4 5967 int nregs = -1;
9306ca4a 5968
a724f0f4 5969 for (;;)
9306ca4a 5970 {
a724f0f4
JB		 5971 if (!intel_e05())
5972 return 0;
9306ca4a 5973
a724f0f4
JB		 5974 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
5975 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 5976
a724f0f4
JB		 5977 if (cur_token.code == '+')
5978 nregs = -1;
5979 else if (cur_token.code == '-')
5980 nregs = NUM_ADDRESS_REGS;
5981 else
5982 return 1;
64a0c779 5983
a724f0f4
JB		 5984 strcat (intel_parser.disp, cur_token.str);
5985 intel_match_token (cur_token.code);
5986 }
64a0c779
DN		 5987}
5988
64a0c779
DN		 5989/* e05 e06 e05'
5990
9306ca4a 5991 e05' binOp e06 e05'
64a0c779
DN		 5992 | Empty */
5993static int
5994intel_e05 ()
5995{
a724f0f4 5996 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 5997
a724f0f4 5998 for (;;)
64a0c779 5999 {
a724f0f4
JB		 6000 if (!intel_e06())
6001 return 0;
6002
6003 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6004 {
6005 char str[2];
6006
6007 str[0] = cur_token.code;
6008 str[1] = 0;
6009 strcat (intel_parser.disp, str);
6010 }
6011 else
6012 break;
9306ca4a 6013
64a0c779
DN		 6014 intel_match_token (cur_token.code);
6015
a724f0f4
JB		 6016 if (nregs < 0)
6017 nregs = ~nregs;
64a0c779 6018 }
a724f0f4
JB		 6019 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6020 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6021 return 1;
4a1805b1 6022}
64a0c779
DN		 6023
6024/* e06 e09 e06'
6025
6026 e06' mulOp e09 e06'
b77a7acd 6027 | Empty */
64a0c779
DN		 6028static int
6029intel_e06 ()
6030{
a724f0f4 6031 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6032
a724f0f4 6033 for (;;)
64a0c779 6034 {
a724f0f4
JB		 6035 if (!intel_e09())
6036 return 0;
9306ca4a 6037
a724f0f4
JB		 6038 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6039 {
6040 char str[2];
9306ca4a 6041
a724f0f4
JB		 6042 str[0] = cur_token.code;
6043 str[1] = 0;
6044 strcat (intel_parser.disp, str);
6045 }
6046 else if (cur_token.code == T_SHL)
6047 strcat (intel_parser.disp, "<<");
6048 else if (cur_token.code == T_SHR)
6049 strcat (intel_parser.disp, ">>");
6050 else
6051 break;
9306ca4a 6052
a724f0f4 6053 intel_match_token (cur_token.code);
64a0c779 6054
a724f0f4
JB		 6055 if (nregs < 0)
6056 nregs = ~nregs;
64a0c779 6057 }
a724f0f4
JB		 6058 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6059 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6060 return 1;
64a0c779
DN		 6061}
6062
a724f0f4
JB		 6063/* e09 OFFSET e09
6064 | SHORT e09
6065 | + e09
6066 | - e09
6067 | ~ e09
6068 | NOT e09
9306ca4a
JB		 6069 | e10 e09'
6070
64a0c779 6071 e09' PTR e10 e09'
b77a7acd 6072 | : e10 e09'
64a0c779
DN		 6073 | Empty */
6074static int
6075intel_e09 ()
6076{
a724f0f4
JB		 6077 int nregs = ~NUM_ADDRESS_REGS;
6078 int in_offset = 0;
6079
6080 for (;;)
64a0c779 6081 {
a724f0f4
JB		 6082 /* Don't consume constants here. */
6083 if (cur_token.code == '+' || cur_token.code == '-')
6084 {
6085 /* Need to look one token ahead - if the next token
6086 is a constant, the current token is its sign. */
6087 int next_code;
6088
6089 intel_match_token (cur_token.code);
6090 next_code = cur_token.code;
6091 intel_putback_token ();
6092 if (next_code == T_CONST)
6093 break;
6094 }
6095
6096 /* e09 OFFSET e09 */
6097 if (cur_token.code == T_OFFSET)
6098 {
6099 if (!in_offset++)
6100 ++intel_parser.in_offset;
6101 }
6102
6103 /* e09 SHORT e09 */
6104 else if (cur_token.code == T_SHORT)
6105 intel_parser.op_modifier |= 1 << T_SHORT;
6106
6107 /* e09 + e09 */
6108 else if (cur_token.code == '+')
6109 strcat (intel_parser.disp, "+");
6110
6111 /* e09 - e09
6112 | ~ e09
6113 | NOT e09 */
6114 else if (cur_token.code == '-' || cur_token.code == '~')
6115 {
6116 char str[2];
64a0c779 6117
a724f0f4
JB		 6118 if (nregs < 0)
6119 nregs = ~nregs;
6120 str[0] = cur_token.code;
6121 str[1] = 0;
6122 strcat (intel_parser.disp, str);
6123 }
6124
6125 /* e09 e10 e09' */
6126 else
6127 break;
6128
6129 intel_match_token (cur_token.code);
64a0c779
DN		 6130 }
6131
a724f0f4 6132 for (;;)
9306ca4a 6133 {
a724f0f4
JB		 6134 if (!intel_e10 ())
6135 return 0;
9306ca4a 6136
a724f0f4
JB		 6137 /* e09' PTR e10 e09' */
6138 if (cur_token.code == T_PTR)
6139 {
6140 char suffix;
9306ca4a 6141
a724f0f4
JB		 6142 if (prev_token.code == T_BYTE)
6143 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6144
a724f0f4
JB		 6145 else if (prev_token.code == T_WORD)
6146 {
6147 if (current_templates->start->name[0] == 'l'
6148 && current_templates->start->name[2] == 's'
6149 && current_templates->start->name[3] == 0)
6150 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6151 else if (intel_parser.got_a_float == 2) /* "fi..." */
6152 suffix = SHORT_MNEM_SUFFIX;
6153 else
6154 suffix = WORD_MNEM_SUFFIX;
6155 }
64a0c779 6156
a724f0f4
JB		 6157 else if (prev_token.code == T_DWORD)
6158 {
6159 if (current_templates->start->name[0] == 'l'
6160 && current_templates->start->name[2] == 's'
6161 && current_templates->start->name[3] == 0)
6162 suffix = WORD_MNEM_SUFFIX;
6163 else if (flag_code == CODE_16BIT
6164 && (current_templates->start->opcode_modifier
6165 & (Jump|JumpDword|JumpInterSegment)))
6166 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6167 else if (intel_parser.got_a_float == 1) /* "f..." */
6168 suffix = SHORT_MNEM_SUFFIX;
6169 else
6170 suffix = LONG_MNEM_SUFFIX;
6171 }
9306ca4a 6172
a724f0f4
JB		 6173 else if (prev_token.code == T_FWORD)
6174 {
6175 if (current_templates->start->name[0] == 'l'
6176 && current_templates->start->name[2] == 's'
6177 && current_templates->start->name[3] == 0)
6178 suffix = LONG_MNEM_SUFFIX;
6179 else if (!intel_parser.got_a_float)
6180 {
6181 if (flag_code == CODE_16BIT)
6182 add_prefix (DATA_PREFIX_OPCODE);
6183 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6184 }
6185 else
6186 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6187 }
64a0c779 6188
a724f0f4
JB		 6189 else if (prev_token.code == T_QWORD)
6190 {
6191 if (intel_parser.got_a_float == 1) /* "f..." */
6192 suffix = LONG_MNEM_SUFFIX;
6193 else
6194 suffix = QWORD_MNEM_SUFFIX;
6195 }
64a0c779 6196
a724f0f4
JB		 6197 else if (prev_token.code == T_TBYTE)
6198 {
6199 if (intel_parser.got_a_float == 1)
6200 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6201 else
6202 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6203 }
9306ca4a 6204
a724f0f4 6205 else if (prev_token.code == T_XMMWORD)
9306ca4a 6206 {
a724f0f4
JB		 6207 /* XXX ignored for now, but accepted since gcc uses it */
6208 suffix = 0;
9306ca4a 6209 }
64a0c779 6210
f16b83df 6211 else
a724f0f4
JB		 6212 {
6213 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6214 return 0;
6215 }
6216
6217 if (current_templates->start->base_opcode == 0x8d /* lea */)
6218 ;
6219 else if (!i.suffix)
6220 i.suffix = suffix;
6221 else if (i.suffix != suffix)
6222 {
6223 as_bad (_("Conflicting operand modifiers"));
6224 return 0;
6225 }
64a0c779 6226
9306ca4a
JB		 6227 }
6228
a724f0f4
JB		 6229 /* e09' : e10 e09' */
6230 else if (cur_token.code == ':')
9306ca4a 6231 {
a724f0f4
JB		 6232 if (prev_token.code != T_REG)
6233 {
6234 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6235 segment/group identifier (which we don't have), using comma
6236 as the operand separator there is even less consistent, since
6237 there all branches only have a single operand. */
6238 if (this_operand != 0
6239 || intel_parser.in_offset
6240 || intel_parser.in_bracket
6241 || (!(current_templates->start->opcode_modifier
6242 & (Jump|JumpDword|JumpInterSegment))
6243 && !(current_templates->start->operand_types[0]
6244 & JumpAbsolute)))
6245 return intel_match_token (T_NIL);
6246 /* Remember the start of the 2nd operand and terminate 1st
6247 operand here.
6248 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6249 another expression), but it gets at least the simplest case
6250 (a plain number or symbol on the left side) right. */
6251 intel_parser.next_operand = intel_parser.op_string;
6252 *--intel_parser.op_string = '\0';
6253 return intel_match_token (':');
6254 }
9306ca4a 6255 }
64a0c779 6256
a724f0f4 6257 /* e09' Empty */
64a0c779 6258 else
a724f0f4 6259 break;
64a0c779 6260
a724f0f4
JB		 6261 intel_match_token (cur_token.code);
6262
6263 }
6264
6265 if (in_offset)
6266 {
6267 --intel_parser.in_offset;
6268 if (nregs < 0)
6269 nregs = ~nregs;
6270 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 6271 {
a724f0f4 6272 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 6273 return 0;
6274 }
a724f0f4
JB		 6275 intel_parser.op_modifier |= 1 << T_OFFSET;
6276 }
9306ca4a 6277
a724f0f4
JB		 6278 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6279 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
6280 return 1;
6281}
64a0c779 6282
a724f0f4
JB		 6283static int
6284intel_bracket_expr ()
6285{
6286 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
6287 const char *start = intel_parser.op_string;
6288 int len;
6289
6290 if (i.op[this_operand].regs)
6291 return intel_match_token (T_NIL);
6292
6293 intel_match_token ('[');
6294
6295 /* Mark as a memory operand only if it's not already known to be an
6296 offset expression. If it's an offset expression, we need to keep
6297 the brace in. */
6298 if (!intel_parser.in_offset)
6299 {
6300 ++intel_parser.in_bracket;
6301 /* Unfortunately gas always diverged from MASM in a respect that can't
6302 be easily fixed without risking to break code sequences likely to be
6303 encountered (the testsuite even check for this): MASM doesn't consider
6304 an expression inside brackets unconditionally as a memory reference.
6305 When that is e.g. a constant, an offset expression, or the sum of the
6306 two, this is still taken as a constant load. gas, however, always
6307 treated these as memory references. As a compromise, we'll try to make
6308 offset expressions inside brackets work the MASM way (since that's
6309 less likely to be found in real world code), but make constants alone
6310 continue to work the traditional gas way. In either case, issue a
6311 warning. */
6312 intel_parser.op_modifier &= ~was_offset;
64a0c779 6313 }
a724f0f4
JB		 6314 else
6315 strcat (intel_parser.disp, "[");
6316
6317 /* Add a '+' to the displacement string if necessary. */
6318 if (*intel_parser.disp != '\0'
6319 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
6320 strcat (intel_parser.disp, "+");
64a0c779 6321
a724f0f4
JB		 6322 if (intel_expr ()
6323 && (len = intel_parser.op_string - start - 1,
6324 intel_match_token (']')))
64a0c779 6325 {
a724f0f4
JB		 6326 /* Preserve brackets when the operand is an offset expression. */
6327 if (intel_parser.in_offset)
6328 strcat (intel_parser.disp, "]");
6329 else
6330 {
6331 --intel_parser.in_bracket;
6332 if (i.base_reg || i.index_reg)
6333 intel_parser.is_mem = 1;
6334 if (!intel_parser.is_mem)
6335 {
6336 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
6337 /* Defer the warning until all of the operand was parsed. */
6338 intel_parser.is_mem = -1;
6339 else if (!quiet_warnings)
6340 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
6341 }
6342 }
6343 intel_parser.op_modifier |= was_offset;
64a0c779 6344
a724f0f4 6345 return 1;
64a0c779 6346 }
a724f0f4 6347 return 0;
64a0c779
DN		 6348}
6349
6350/* e10 e11 e10'
6351
6352 e10' [ expr ] e10'
b77a7acd 6353 | Empty */
64a0c779
DN		 6354static int
6355intel_e10 ()
6356{
a724f0f4
JB		 6357 if (!intel_e11 ())
6358 return 0;
64a0c779 6359
a724f0f4 6360 while (cur_token.code == '[')
64a0c779 6361 {
a724f0f4 6362 if (!intel_bracket_expr ())
21d6c4af 6363 return 0;
64a0c779
DN		 6364 }
6365
a724f0f4 6366 return 1;
64a0c779
DN		 6367}
6368
64a0c779 6369/* e11 ( expr )
b77a7acd 6370 | [ expr ]
64a0c779
DN		 6371 | BYTE
6372 | WORD
6373 | DWORD
9306ca4a 6374 | FWORD
64a0c779 6375 | QWORD
9306ca4a
JB		 6376 | TBYTE
6377 | OWORD
6378 | XMMWORD
4a1805b1 6379 | $
64a0c779
DN		 6380 | .
6381 | register
6382 | id
6383 | constant */
6384static int
6385intel_e11 ()
6386{
a724f0f4 6387 switch (cur_token.code)
64a0c779 6388 {
a724f0f4
JB		 6389 /* e11 ( expr ) */
6390 case '(':
64a0c779
DN		 6391 intel_match_token ('(');
6392 strcat (intel_parser.disp, "(");
6393
6394 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 6395 {
6396 strcat (intel_parser.disp, ")");
6397 return 1;
6398 }
a724f0f4 6399 return 0;
4a1805b1 6400
a724f0f4
JB		 6401 /* e11 [ expr ] */
6402 case '[':
6403 /* Operands for jump/call inside brackets denote absolute addresses.
6404 XXX This shouldn't be needed anymore (or if it should rather live
6405 in intel_bracket_expr). */
9306ca4a
JB		 6406 if (current_templates->start->opcode_modifier
6407 & (Jump|JumpDword|JumpByte|JumpInterSegment))
64a0c779
DN		 6408 i.types[this_operand] |= JumpAbsolute;
6409
a724f0f4 6410 return intel_bracket_expr ();
64a0c779 6411
a724f0f4
JB		 6412 /* e11 $
6413 | . */
6414 case '.':
64a0c779
DN		 6415 strcat (intel_parser.disp, cur_token.str);
6416 intel_match_token (cur_token.code);
21d6c4af
DN		 6417
6418 /* Mark as a memory operand only if it's not already known to be an
6419 offset expression. */
a724f0f4 6420 if (!intel_parser.in_offset)
21d6c4af 6421 intel_parser.is_mem = 1;
64a0c779
DN		 6422
6423 return 1;
64a0c779 6424
a724f0f4
JB		 6425 /* e11 register */
6426 case T_REG:
6427 {
6428 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 6429
a724f0f4 6430 intel_match_token (T_REG);
64a0c779 6431
a724f0f4
JB		 6432 /* Check for segment change. */
6433 if (cur_token.code == ':')
6434 {
6435 if (!(reg->reg_type & (SReg2 | SReg3)))
6436 {
6437 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
6438 return 0;
6439 }
6440 else if (i.seg[i.mem_operands])
6441 as_warn (_("Extra segment override ignored"));
6442 else
6443 {
6444 if (!intel_parser.in_offset)
6445 intel_parser.is_mem = 1;
6446 switch (reg->reg_num)
6447 {
6448 case 0:
6449 i.seg[i.mem_operands] = &es;
6450 break;
6451 case 1:
6452 i.seg[i.mem_operands] = &cs;
6453 break;
6454 case 2:
6455 i.seg[i.mem_operands] = &ss;
6456 break;
6457 case 3:
6458 i.seg[i.mem_operands] = &ds;
6459 break;
6460 case 4:
6461 i.seg[i.mem_operands] = &fs;
6462 break;
6463 case 5:
6464 i.seg[i.mem_operands] = &gs;
6465 break;
6466 }
6467 }
6468 }
64a0c779 6469
a724f0f4
JB		 6470 /* Not a segment register. Check for register scaling. */
6471 else if (cur_token.code == '*')
6472 {
6473 if (!intel_parser.in_bracket)
6474 {
6475 as_bad (_("Register scaling only allowed in memory operands"));
6476 return 0;
6477 }
64a0c779 6478
a724f0f4
JB		 6479 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
6480 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6481 else if (i.index_reg)
6482 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 6483
a724f0f4
JB		 6484 /* What follows must be a valid scale. */
6485 intel_match_token ('*');
6486 i.index_reg = reg;
6487 i.types[this_operand] |= BaseIndex;
64a0c779 6488
a724f0f4
JB		 6489 /* Set the scale after setting the register (otherwise,
6490 i386_scale will complain) */
6491 if (cur_token.code == '+' || cur_token.code == '-')
6492 {
6493 char *str, sign = cur_token.code;
6494 intel_match_token (cur_token.code);
6495 if (cur_token.code != T_CONST)
6496 {
6497 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6498 cur_token.str);
6499 return 0;
6500 }
6501 str = (char *) xmalloc (strlen (cur_token.str) + 2);
6502 strcpy (str + 1, cur_token.str);
6503 *str = sign;
6504 if (!i386_scale (str))
6505 return 0;
6506 free (str);
6507 }
6508 else if (!i386_scale (cur_token.str))
64a0c779 6509 return 0;
a724f0f4
JB		 6510 intel_match_token (cur_token.code);
6511 }
64a0c779 6512
a724f0f4
JB		 6513 /* No scaling. If this is a memory operand, the register is either a
6514 base register (first occurrence) or an index register (second
6515 occurrence). */
6516 else if (intel_parser.in_bracket && !(reg->reg_type & (SReg2 | SReg3)))
6517 {
64a0c779 6518
a724f0f4
JB		 6519 if (!i.base_reg)
6520 i.base_reg = reg;
6521 else if (!i.index_reg)
6522 i.index_reg = reg;
6523 else
6524 {
6525 as_bad (_("Too many register references in memory operand"));
6526 return 0;
6527 }
64a0c779 6528
a724f0f4
JB		 6529 i.types[this_operand] |= BaseIndex;
6530 }
4a1805b1 6531
a724f0f4
JB		 6532 /* Offset modifier. Add the register to the displacement string to be
6533 parsed as an immediate expression after we're done. */
6534 else if (intel_parser.in_offset)
6535 {
6536 as_warn (_("Using register names in OFFSET expressions is deprecated"));
6537 strcat (intel_parser.disp, reg->reg_name);
6538 }
64a0c779 6539
a724f0f4
JB		 6540 /* It's neither base nor index nor offset. */
6541 else if (!intel_parser.is_mem)
6542 {
6543 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
6544 i.op[this_operand].regs = reg;
6545 i.reg_operands++;
6546 }
6547 else
6548 {
6549 as_bad (_("Invalid use of register"));
6550 return 0;
6551 }
64a0c779 6552
a724f0f4
JB		 6553 /* Since registers are not part of the displacement string (except
6554 when we're parsing offset operands), we may need to remove any
6555 preceding '+' from the displacement string. */
6556 if (*intel_parser.disp != '\0'
6557 && !intel_parser.in_offset)
6558 {
6559 char *s = intel_parser.disp;
6560 s += strlen (s) - 1;
6561 if (*s == '+')
6562 *s = '\0';
6563 }
4a1805b1 6564
a724f0f4
JB		 6565 return 1;
6566 }
6567
6568 /* e11 BYTE
6569 | WORD
6570 | DWORD
6571 | FWORD
6572 | QWORD
6573 | TBYTE
6574 | OWORD
6575 | XMMWORD */
6576 case T_BYTE:
6577 case T_WORD:
6578 case T_DWORD:
6579 case T_FWORD:
6580 case T_QWORD:
6581 case T_TBYTE:
6582 case T_XMMWORD:
6583 intel_match_token (cur_token.code);
64a0c779 6584
a724f0f4
JB		 6585 if (cur_token.code == T_PTR)
6586 return 1;
6587
6588 /* It must have been an identifier. */
6589 intel_putback_token ();
6590 cur_token.code = T_ID;
6591 /* FALLTHRU */
6592
6593 /* e11 id
6594 | constant */
6595 case T_ID:
6596 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 6597 {
6598 symbolS *symbolP;
6599
a724f0f4
JB		 6600 /* The identifier represents a memory reference only if it's not
6601 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 6602 symbolP = symbol_find(cur_token.str);
6603 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
6604 intel_parser.is_mem = 1;
6605 }
a724f0f4 6606 /* FALLTHRU */
64a0c779 6607
a724f0f4
JB		 6608 case T_CONST:
6609 case '-':
6610 case '+':
6611 {
6612 char *save_str, sign = 0;
64a0c779 6613
a724f0f4
JB		 6614 /* Allow constants that start with `+' or `-'. */
6615 if (cur_token.code == '-' || cur_token.code == '+')
6616 {
6617 sign = cur_token.code;
6618 intel_match_token (cur_token.code);
6619 if (cur_token.code != T_CONST)
6620 {
6621 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6622 cur_token.str);
6623 return 0;
6624 }
6625 }
64a0c779 6626
a724f0f4
JB		 6627 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
6628 strcpy (save_str + !!sign, cur_token.str);
6629 if (sign)
6630 *save_str = sign;
64a0c779 6631
a724f0f4
JB		 6632 /* Get the next token to check for register scaling. */
6633 intel_match_token (cur_token.code);
64a0c779 6634
a724f0f4
JB		 6635 /* Check if this constant is a scaling factor for an index register. */
6636 if (cur_token.code == '*')
6637 {
6638 if (intel_match_token ('*') && cur_token.code == T_REG)
6639 {
6640 const reg_entry *reg = cur_token.reg;
6641
6642 if (!intel_parser.in_bracket)
6643 {
6644 as_bad (_("Register scaling only allowed in memory operands"));
6645 return 0;
6646 }
6647
6648 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
6649 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6650 else if (i.index_reg)
6651 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
6652
6653 /* The constant is followed by `* reg', so it must be
6654 a valid scale. */
6655 i.index_reg = reg;
6656 i.types[this_operand] |= BaseIndex;
6657
6658 /* Set the scale after setting the register (otherwise,
6659 i386_scale will complain) */
6660 if (!i386_scale (save_str))
64a0c779 6661 return 0;
a724f0f4
JB		 6662 intel_match_token (T_REG);
6663
6664 /* Since registers are not part of the displacement
6665 string, we may need to remove any preceding '+' from
6666 the displacement string. */
6667 if (*intel_parser.disp != '\0')
6668 {
6669 char *s = intel_parser.disp;
6670 s += strlen (s) - 1;
6671 if (*s == '+')
6672 *s = '\0';
6673 }
6674
6675 free (save_str);
6676
6677 return 1;
6678 }
64a0c779 6679
a724f0f4
JB		 6680 /* The constant was not used for register scaling. Since we have
6681 already consumed the token following `*' we now need to put it
6682 back in the stream. */
64a0c779 6683 intel_putback_token ();
a724f0f4 6684 }
64a0c779 6685
a724f0f4
JB		 6686 /* Add the constant to the displacement string. */
6687 strcat (intel_parser.disp, save_str);
6688 free (save_str);
64a0c779 6689
a724f0f4
JB		 6690 return 1;
6691 }
64a0c779
DN		 6692 }
6693
64a0c779
DN		 6694 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6695 return 0;
6696}
6697
64a0c779
DN		 6698/* Match the given token against cur_token. If they match, read the next
6699 token from the operand string. */
6700static int
6701intel_match_token (code)
e5cb08ac 6702 int code;
64a0c779
DN		 6703{
6704 if (cur_token.code == code)
6705 {
6706 intel_get_token ();
6707 return 1;
6708 }
6709 else
6710 {
0477af35 6711 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 6712 return 0;
6713 }
6714}
6715
64a0c779
DN		 6716/* Read a new token from intel_parser.op_string and store it in cur_token. */
6717static void
6718intel_get_token ()
6719{
6720 char *end_op;
6721 const reg_entry *reg;
6722 struct intel_token new_token;
6723
6724 new_token.code = T_NIL;
6725 new_token.reg = NULL;
6726 new_token.str = NULL;
6727
4a1805b1 6728 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6729 cur_token to prev_token. */
6730 if (prev_token.str)
6731 free (prev_token.str);
6732
6733 prev_token = cur_token;
6734
6735 /* Skip whitespace. */
6736 while (is_space_char (*intel_parser.op_string))
6737 intel_parser.op_string++;
6738
6739 /* Return an empty token if we find nothing else on the line. */
6740 if (*intel_parser.op_string == '\0')
6741 {
6742 cur_token = new_token;
6743 return;
6744 }
6745
6746 /* The new token cannot be larger than the remainder of the operand
6747 string. */
a724f0f4 6748 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 6749 new_token.str[0] = '\0';
6750
6751 if (strchr ("0123456789", *intel_parser.op_string))
6752 {
6753 char *p = new_token.str;
6754 char *q = intel_parser.op_string;
6755 new_token.code = T_CONST;
6756
6757 /* Allow any kind of identifier char to encompass floating point and
6758 hexadecimal numbers. */
6759 while (is_identifier_char (*q))
6760 *p++ = *q++;
6761 *p = '\0';
6762
6763 /* Recognize special symbol names [0-9][bf]. */
6764 if (strlen (intel_parser.op_string) == 2
4a1805b1 6765 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 6766 || intel_parser.op_string[1] == 'f'))
6767 new_token.code = T_ID;
6768 }
6769
64a0c779
DN		 6770 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6771 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6772 {
6773 new_token.code = T_REG;
6774 new_token.reg = reg;
6775
6776 if (*intel_parser.op_string == REGISTER_PREFIX)
6777 {
6778 new_token.str[0] = REGISTER_PREFIX;
6779 new_token.str[1] = '\0';
6780 }
6781
6782 strcat (new_token.str, reg->reg_name);
6783 }
6784
6785 else if (is_identifier_char (*intel_parser.op_string))
6786 {
6787 char *p = new_token.str;
6788 char *q = intel_parser.op_string;
6789
6790 /* A '.' or '$' followed by an identifier char is an identifier.
6791 Otherwise, it's operator '.' followed by an expression. */
6792 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6793 {
9306ca4a
JB		 6794 new_token.code = '.';
6795 new_token.str[0] = '.';
64a0c779
DN		 6796 new_token.str[1] = '\0';
6797 }
6798 else
6799 {
6800 while (is_identifier_char (*q) || *q == '@')
6801 *p++ = *q++;
6802 *p = '\0';
6803
9306ca4a
JB		 6804 if (strcasecmp (new_token.str, "NOT") == 0)
6805 new_token.code = '~';
6806
6807 else if (strcasecmp (new_token.str, "MOD") == 0)
6808 new_token.code = '%';
6809
6810 else if (strcasecmp (new_token.str, "AND") == 0)
6811 new_token.code = '&';
6812
6813 else if (strcasecmp (new_token.str, "OR") == 0)
6814 new_token.code = '|';
6815
6816 else if (strcasecmp (new_token.str, "XOR") == 0)
6817 new_token.code = '^';
6818
6819 else if (strcasecmp (new_token.str, "SHL") == 0)
6820 new_token.code = T_SHL;
6821
6822 else if (strcasecmp (new_token.str, "SHR") == 0)
6823 new_token.code = T_SHR;
6824
6825 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 6826 new_token.code = T_BYTE;
6827
6828 else if (strcasecmp (new_token.str, "WORD") == 0)
6829 new_token.code = T_WORD;
6830
6831 else if (strcasecmp (new_token.str, "DWORD") == 0)
6832 new_token.code = T_DWORD;
6833
9306ca4a
JB		 6834 else if (strcasecmp (new_token.str, "FWORD") == 0)
6835 new_token.code = T_FWORD;
6836
64a0c779
DN		 6837 else if (strcasecmp (new_token.str, "QWORD") == 0)
6838 new_token.code = T_QWORD;
6839
9306ca4a
JB		 6840 else if (strcasecmp (new_token.str, "TBYTE") == 0
6841 /* XXX remove (gcc still uses it) */
6842 || strcasecmp (new_token.str, "XWORD") == 0)
6843 new_token.code = T_TBYTE;
6844
6845 else if (strcasecmp (new_token.str, "XMMWORD") == 0
6846 || strcasecmp (new_token.str, "OWORD") == 0)
6847 new_token.code = T_XMMWORD;
64a0c779
DN		 6848
6849 else if (strcasecmp (new_token.str, "PTR") == 0)
6850 new_token.code = T_PTR;
6851
6852 else if (strcasecmp (new_token.str, "SHORT") == 0)
6853 new_token.code = T_SHORT;
6854
6855 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6856 {
6857 new_token.code = T_OFFSET;
6858
6859 /* ??? This is not mentioned in the MASM grammar but gcc
6860 makes use of it with -mintel-syntax. OFFSET may be
6861 followed by FLAT: */
6862 if (strncasecmp (q, " FLAT:", 6) == 0)
6863 strcat (new_token.str, " FLAT:");
6864 }
6865
6866 /* ??? This is not mentioned in the MASM grammar. */
6867 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 6868 {
6869 new_token.code = T_OFFSET;
6870 if (*q == ':')
6871 strcat (new_token.str, ":");
6872 else
6873 as_bad (_("`:' expected"));
6874 }
64a0c779
DN		 6875
6876 else
6877 new_token.code = T_ID;
6878 }
6879 }
6880
9306ca4a
JB		 6881 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
6882 {
6883 new_token.code = *intel_parser.op_string;
6884 new_token.str[0] = *intel_parser.op_string;
6885 new_token.str[1] = '\0';
6886 }
6887
6888 else if (strchr ("<>", *intel_parser.op_string)
6889 && *intel_parser.op_string == *(intel_parser.op_string + 1))
6890 {
6891 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
6892 new_token.str[0] = *intel_parser.op_string;
6893 new_token.str[1] = *intel_parser.op_string;
6894 new_token.str[2] = '\0';
6895 }
6896
64a0c779 6897 else
0477af35 6898 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 6899
6900 intel_parser.op_string += strlen (new_token.str);
6901 cur_token = new_token;
6902}
6903
64a0c779
DN		 6904/* Put cur_token back into the token stream and make cur_token point to
6905 prev_token. */
6906static void
6907intel_putback_token ()
6908{
a724f0f4
JB		 6909 if (cur_token.code != T_NIL)
6910 {
6911 intel_parser.op_string -= strlen (cur_token.str);
6912 free (cur_token.str);
6913 }
64a0c779 6914 cur_token = prev_token;
4a1805b1 6915
64a0c779
DN		 6916 /* Forget prev_token. */
6917 prev_token.code = T_NIL;
6918 prev_token.reg = NULL;
6919 prev_token.str = NULL;
6920}
54cfded0 6921
a4447b93 6922int
54cfded0
AM		 6923tc_x86_regname_to_dw2regnum (const char *regname)
6924{
6925 unsigned int regnum;
6926 unsigned int regnames_count;
089dfecd 6927 static const char *const regnames_32[] =
54cfded0 6928 {
a4447b93
RH		 6929 "eax", "ecx", "edx", "ebx",
6930 "esp", "ebp", "esi", "edi",
089dfecd
JB		 6931 "eip", "eflags", NULL,
6932 "st0", "st1", "st2", "st3",
6933 "st4", "st5", "st6", "st7",
6934 NULL, NULL,
6935 "xmm0", "xmm1", "xmm2", "xmm3",
6936 "xmm4", "xmm5", "xmm6", "xmm7",
6937 "mm0", "mm1", "mm2", "mm3",
6938 "mm4", "mm5", "mm6", "mm7"
54cfded0 6939 };
089dfecd 6940 static const char *const regnames_64[] =
54cfded0 6941 {
089dfecd
JB		 6942 "rax", "rdx", "rcx", "rbx",
6943 "rsi", "rdi", "rbp", "rsp",
6944 "r8", "r9", "r10", "r11",
54cfded0 6945 "r12", "r13", "r14", "r15",
089dfecd
JB		 6946 "rip",
6947 "xmm0", "xmm1", "xmm2", "xmm3",
6948 "xmm4", "xmm5", "xmm6", "xmm7",
6949 "xmm8", "xmm9", "xmm10", "xmm11",
6950 "xmm12", "xmm13", "xmm14", "xmm15",
6951 "st0", "st1", "st2", "st3",
6952 "st4", "st5", "st6", "st7",
6953 "mm0", "mm1", "mm2", "mm3",
6954 "mm4", "mm5", "mm6", "mm7"
54cfded0 6955 };
089dfecd 6956 const char *const *regnames;
54cfded0
AM		 6957
6958 if (flag_code == CODE_64BIT)
6959 {
6960 regnames = regnames_64;
0cea6190 6961 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 6962 }
6963 else
6964 {
6965 regnames = regnames_32;
0cea6190 6966 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 6967 }
6968
6969 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 6970 if (regnames[regnum] != NULL
6971 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 6972 return regnum;
6973
54cfded0
AM		 6974 return -1;
6975}
6976
6977void
6978tc_x86_frame_initial_instructions (void)
6979{
a4447b93
RH		 6980 static unsigned int sp_regno;
6981
6982 if (!sp_regno)
6983 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
6984 ? "rsp" : "esp");
6985
6986 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
6987 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 6988}
d2b2c203
DJ		 6989
6990int
6991i386_elf_section_type (const char *str, size_t len)
6992{
6993 if (flag_code == CODE_64BIT
6994 && len == sizeof ("unwind") - 1
6995 && strncmp (str, "unwind", 6) == 0)
6996 return SHT_X86_64_UNWIND;
6997
6998 return -1;
6999}
bb41ade5
AM		 7000
7001#ifdef TE_PE
7002void
7003tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7004{
7005 expressionS expr;
7006
7007 expr.X_op = O_secrel;
7008 expr.X_add_symbol = symbol;
7009 expr.X_add_number = 0;
7010 emit_expr (&expr, size);
7011}
7012#endif
3b22753a
L		 7013
7014#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7015/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7016
7017int
7018x86_64_section_letter (int letter, char **ptr_msg)
7019{
7020 if (flag_code == CODE_64BIT)
7021 {
7022 if (letter == 'l')
7023 return SHF_X86_64_LARGE;
7024
7025 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7026 }
7027 else
7028 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
7029 return -1;
7030}
7031
7032int
7033x86_64_section_word (char *str, size_t len)
7034{
7035 if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0)
7036 return SHF_X86_64_LARGE;
7037
7038 return -1;
7039}
7040
7041static void
7042handle_large_common (int small ATTRIBUTE_UNUSED)
7043{
7044 if (flag_code != CODE_64BIT)
7045 {
7046 s_comm_internal (0, elf_common_parse);
7047 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7048 }
7049 else
7050 {
7051 static segT lbss_section;
7052 asection *saved_com_section_ptr = elf_com_section_ptr;
7053 asection *saved_bss_section = bss_section;
7054
7055 if (lbss_section == NULL)
7056 {
7057 flagword applicable;
7058 segT seg = now_seg;
7059 subsegT subseg = now_subseg;
7060
7061 /* The .lbss section is for local .largecomm symbols. */
7062 lbss_section = subseg_new (".lbss", 0);
7063 applicable = bfd_applicable_section_flags (stdoutput);
7064 bfd_set_section_flags (stdoutput, lbss_section,
7065 applicable & SEC_ALLOC);
7066 seg_info (lbss_section)->bss = 1;
7067
7068 subseg_set (seg, subseg);
7069 }
7070
7071 elf_com_section_ptr = &_bfd_elf_large_com_section;
7072 bss_section = lbss_section;
7073
7074 s_comm_internal (0, elf_common_parse);
7075
7076 elf_com_section_ptr = saved_com_section_ptr;
7077 bss_section = saved_bss_section;
7078 }
7079}
7080#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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